subject:"\[PATCH v2 3\/9\] clk\: rockchip\: add clock controller for rk3036"

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-10-07 Thread Heiko Stuebner

Hi,

Am Donnerstag, 24. September 2015, 11:31:58 schrieb Xing Zheng:
> On 2015年09月24日 11:04, Xing Zheng wrote:
> >>>   #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)\
> >>> 
> >>> @@ -95,12 +106,31 @@ enum rockchip_pll_type {
> >>> 
> >>>   .nb = _nb,\
> >>>   
> >>>   }
> >>> 
> >>> +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,\
> >>> +_postdiv2, _dsmpd, _frac)\
> >>> +{\
> >>> +.rate= _rate##U,\
> >>> +.fbdiv = _fbdiv,\
> >>> +.postdiv1 = _postdiv1,\
> >>> +.refdiv = _refdiv,\
> >>> +.postdiv2 = _postdiv2,\
> >>> +.dsmpd = _dsmpd,\
> >>> +.frac = _frac,\
> >>> +}
> >>> +
> >>> 
> >>>   struct rockchip_pll_rate_table {
> >>>   
> >>>   unsigned long rate;
> >>>   unsigned int nr;
> >>>   unsigned int nf;
> >>>   unsigned int no;
> >>>   unsigned int nb;
> >>> 
> >>> +/* for RK3036 */
> >>> +unsigned int fbdiv;
> >>> +unsigned int postdiv1;
> >>> +unsigned int refdiv;
> >>> +unsigned int postdiv2;
> >>> +unsigned int dsmpd;
> >>> +unsigned int frac;
> >> 
> >> same for these 2 ... should be part of the pll addition itself
> >> 
> >   };
> > 
> > Done.
> 
> Sorry, I have one question:
> The "struct rockchip_pll_rate_table" is called in "rockchip/clk-pll.c"
> on many functions, I think I could add a struct like:
> struct rk3036_pll_rate_table {
>  unsigned int fbdiv;
>  unsigned int postdiv1;
>  unsigned int refdiv;
>  unsigned int postdiv2;
>  unsigned int dsmpd;
>  unsigned int frac;
> };
> but, it will add many redundancy codes in "rockchip/clk-pll.c" just for
> call "struct rk3036_pll_rate_table".


One possible solution may be to cast to void* in the general functions, so 
have sturct rk3066_pll_rate_table, rk3036_pll_rate_table, have 
rockchip_clk_register_pll and friends handle it as void* and then only have 
the rockchip_rk3066_pll_* functions as well as the clk-rk.c use them as 
their actual type, as they know which they need.


Heiko

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Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-10-07 Thread Heiko Stuebner

Hi,

Am Donnerstag, 24. September 2015, 11:31:58 schrieb Xing Zheng:
> On 2015年09月24日 11:04, Xing Zheng wrote:
> >>>   #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)\
> >>> 
> >>> @@ -95,12 +106,31 @@ enum rockchip_pll_type {
> >>> 
> >>>   .nb = _nb,\
> >>>   
> >>>   }
> >>> 
> >>> +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,\
> >>> +_postdiv2, _dsmpd, _frac)\
> >>> +{\
> >>> +.rate= _rate##U,\
> >>> +.fbdiv = _fbdiv,\
> >>> +.postdiv1 = _postdiv1,\
> >>> +.refdiv = _refdiv,\
> >>> +.postdiv2 = _postdiv2,\
> >>> +.dsmpd = _dsmpd,\
> >>> +.frac = _frac,\
> >>> +}
> >>> +
> >>> 
> >>>   struct rockchip_pll_rate_table {
> >>>   
> >>>   unsigned long rate;
> >>>   unsigned int nr;
> >>>   unsigned int nf;
> >>>   unsigned int no;
> >>>   unsigned int nb;
> >>> 
> >>> +/* for RK3036 */
> >>> +unsigned int fbdiv;
> >>> +unsigned int postdiv1;
> >>> +unsigned int refdiv;
> >>> +unsigned int postdiv2;
> >>> +unsigned int dsmpd;
> >>> +unsigned int frac;
> >> 
> >> same for these 2 ... should be part of the pll addition itself
> >> 
> >   };
> > 
> > Done.
> 
> Sorry, I have one question:
> The "struct rockchip_pll_rate_table" is called in "rockchip/clk-pll.c"
> on many functions, I think I could add a struct like:
> struct rk3036_pll_rate_table {
>  unsigned int fbdiv;
>  unsigned int postdiv1;
>  unsigned int refdiv;
>  unsigned int postdiv2;
>  unsigned int dsmpd;
>  unsigned int frac;
> };
> but, it will add many redundancy codes in "rockchip/clk-pll.c" just for
> call "struct rk3036_pll_rate_table".


One possible solution may be to cast to void* in the general functions, so 
have sturct rk3066_pll_rate_table, rk3036_pll_rate_table, have 
rockchip_clk_register_pll and friends handle it as void* and then only have 
the rockchip_rk3066_pll_* functions as well as the clk-rk.c use them as 
their actual type, as they know which they need.


Heiko

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Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-23 Thread Xing Zheng


On 2015年09月24日 11:04, Xing Zheng wrote:


  #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)\
@@ -95,12 +106,31 @@ enum rockchip_pll_type {
  .nb = _nb,\
  }

+#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,\
+_postdiv2, _dsmpd, _frac)\
+{\
+.rate= _rate##U,\
+.fbdiv = _fbdiv,\
+.postdiv1 = _postdiv1,\
+.refdiv = _refdiv,\
+.postdiv2 = _postdiv2,\
+.dsmpd = _dsmpd,\
+.frac = _frac,\
+}
+
  struct rockchip_pll_rate_table {
  unsigned long rate;
  unsigned int nr;
  unsigned int nf;
  unsigned int no;
  unsigned int nb;
+/* for RK3036 */
+unsigned int fbdiv;
+unsigned int postdiv1;
+unsigned int refdiv;
+unsigned int postdiv2;
+unsigned int dsmpd;
+unsigned int frac;

same for these 2 ... should be part of the pll addition itself

  };
Done.


Sorry, I have one question:
The "struct rockchip_pll_rate_table" is called in "rockchip/clk-pll.c" 
on many functions, I think I could add a struct like:

struct rk3036_pll_rate_table {
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
but, it will add many redundancy codes in "rockchip/clk-pll.c" just for 
call "struct rk3036_pll_rate_table".


Thanks.


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Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-23 Thread Xing Zheng


On 2015年09月17日 17:47, Heiko Stübner wrote:

Hi,

Am Donnerstag, 17. September 2015, 16:28:54 schrieb Xing Zheng:

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng

missing a dt-bindings document in a separate patch. See "dt-bindings: add
documentation of rk3668 clock controller"
(http://lists.infradead.org/pipermail/linux-rockchip/2015-July/003396.html)
for comparison.

Yes, I sent a dt-bindings document in patch 5:
"dt-bindings: add documentation of rk3036 clock controller",
and I think I will adjust the order of document before "Add the clock 
tree..."

for rk3036.


---

Changes in v2: None

  drivers/clk/rockchip/Makefile |1 +
  drivers/clk/rockchip/clk-rk3036.c |  504
+ drivers/clk/rockchip/clk.h|
30 +++
  3 files changed, 535 insertions(+)
  create mode 100644 drivers/clk/rockchip/clk-rk3036.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
  obj-y += clk-mmc-phase.o
  obj-$(CONFIG_RESET_CONTROLLER)+= softrst.o

+obj-y  += clk-rk3036.o
  obj-y += clk-rk3188.o
  obj-y += clk-rk3288.o
  obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/drivers/clk/rockchip/clk-rk3036.c new file mode 100644
index 000..724d467
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+enum rk3036_plls {
+   apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+   RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+   RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+   RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+   RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+   RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+   RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+   RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+   RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+   RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+   RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+   RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+   RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+   RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+   RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+   RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+   RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+   RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+   RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+   RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
+   RK3036_PLL_RATE(0, 1, 0, 1, 1, 1, 0),

you shouldn't need a "0" rate entry I guess

Done.

+   { /* sentinel */ },
+};
+
+#define RK3036_DIV_CPU_MASK0x1f
+#define RK3036_DIV_CPU_SHIFT

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-23 Thread Xing Zheng


On 2015年09月24日 11:04, Xing Zheng wrote:


  #define RK3066_PLL_RATE(_rate, _nr, _nf, _no)\
@@ -95,12 +106,31 @@ enum rockchip_pll_type {
  .nb = _nb,\
  }

+#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,\
+_postdiv2, _dsmpd, _frac)\
+{\
+.rate= _rate##U,\
+.fbdiv = _fbdiv,\
+.postdiv1 = _postdiv1,\
+.refdiv = _refdiv,\
+.postdiv2 = _postdiv2,\
+.dsmpd = _dsmpd,\
+.frac = _frac,\
+}
+
  struct rockchip_pll_rate_table {
  unsigned long rate;
  unsigned int nr;
  unsigned int nf;
  unsigned int no;
  unsigned int nb;
+/* for RK3036 */
+unsigned int fbdiv;
+unsigned int postdiv1;
+unsigned int refdiv;
+unsigned int postdiv2;
+unsigned int dsmpd;
+unsigned int frac;

same for these 2 ... should be part of the pll addition itself

  };
Done.


Sorry, I have one question:
The "struct rockchip_pll_rate_table" is called in "rockchip/clk-pll.c" 
on many functions, I think I could add a struct like:

struct rk3036_pll_rate_table {
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
but, it will add many redundancy codes in "rockchip/clk-pll.c" just for 
call "struct rk3036_pll_rate_table".


Thanks.


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Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-23 Thread Xing Zheng


On 2015年09月17日 17:47, Heiko Stübner wrote:

Hi,

Am Donnerstag, 17. September 2015, 16:28:54 schrieb Xing Zheng:

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng

missing a dt-bindings document in a separate patch. See "dt-bindings: add
documentation of rk3668 clock controller"
(http://lists.infradead.org/pipermail/linux-rockchip/2015-July/003396.html)
for comparison.

Yes, I sent a dt-bindings document in patch 5:
"dt-bindings: add documentation of rk3036 clock controller",
and I think I will adjust the order of document before "Add the clock 
tree..."

for rk3036.


---

Changes in v2: None

  drivers/clk/rockchip/Makefile |1 +
  drivers/clk/rockchip/clk-rk3036.c |  504
+ drivers/clk/rockchip/clk.h|
30 +++
  3 files changed, 535 insertions(+)
  create mode 100644 drivers/clk/rockchip/clk-rk3036.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
  obj-y += clk-mmc-phase.o
  obj-$(CONFIG_RESET_CONTROLLER)+= softrst.o

+obj-y  += clk-rk3036.o
  obj-y += clk-rk3188.o
  obj-y += clk-rk3288.o
  obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/drivers/clk/rockchip/clk-rk3036.c new file mode 100644
index 000..724d467
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+enum rk3036_plls {
+   apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+   RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+   RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+   RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+   RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+   RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+   RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+   RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+   RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+   RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+   RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+   RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+   RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+   RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+   RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+   RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+   RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+   RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+   RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+   RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
+   RK3036_PLL_RATE(0, 1, 0, 1, 1, 1, 0),

you shouldn't need a "0" rate entry I guess

Done.

+   { /* sentinel */ },
+};
+
+#define

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-17 Thread Heiko Stübner

Hi,

Am Donnerstag, 17. September 2015, 16:28:54 schrieb Xing Zheng:
> Add the clock tree definition for the new rk3036 SoC.
> 
> Signed-off-by: Xing Zheng 

missing a dt-bindings document in a separate patch. See "dt-bindings: add 
documentation of rk3668 clock controller" 
(http://lists.infradead.org/pipermail/linux-rockchip/2015-July/003396.html) 
for comparison.


> ---
> 
> Changes in v2: None
> 
>  drivers/clk/rockchip/Makefile |1 +
>  drivers/clk/rockchip/clk-rk3036.c |  504
> + drivers/clk/rockchip/clk.h|  
> 30 +++
>  3 files changed, 535 insertions(+)
>  create mode 100644 drivers/clk/rockchip/clk-rk3036.c
> 
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index b27edd6..d599829 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -10,6 +10,7 @@ obj-y   += clk-inverter.o
>  obj-y+= clk-mmc-phase.o
>  obj-$(CONFIG_RESET_CONTROLLER)   += softrst.o
> 
> +obj-y+= clk-rk3036.o
>  obj-y+= clk-rk3188.o
>  obj-y+= clk-rk3288.o
>  obj-y+= clk-rk3368.o
> diff --git a/drivers/clk/rockchip/clk-rk3036.c
> b/drivers/clk/rockchip/clk-rk3036.c new file mode 100644
> index 000..724d467
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk-rk3036.c
> @@ -0,0 +1,504 @@
> +/*
> + * Copyright (c) 2014 MundoReader S.L.
> + * Author: Heiko Stuebner 
> + *
> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
> + * Author: Xing Zheng 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "clk.h"
> +
> +enum rk3036_plls {
> + apll, dpll, gpll,
> +};
> +
> +static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
> + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
> + RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
> + RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
> + RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
> + RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
> + RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
> + RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
> + RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
> + RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
> + RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
> + RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
> + RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
> + RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
> + RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
> + RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
> + RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
> + RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
> + RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
> + RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
> + RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
> + RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
> + RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
> + RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
> + RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
> + RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
> + RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
> + RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
> + RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
> + RK3036_PLL_RATE(0, 1, 0, 1, 1, 1, 0),

you shouldn't need a "0" rate entry I guess


> + { /* sentinel */ },
> +};
> +
> +#define RK3036_DIV_CPU_MASK  0x1f
> +#define RK3036_DIV_CPU_SHIFT 8
> +
> +#define RK3036_DIV_PERI_MASK 0xf
> +#define RK3036_DIV_PERI_SHIFT

[PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-17 Thread Xing Zheng

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk-rk3036.c |  504 +
 drivers/clk/rockchip/clk.h|   30 +++
 3 files changed, 535 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
 obj-y  += clk-mmc-phase.o
 obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
+obj-y  += clk-rk3036.o
 obj-y  += clk-rk3188.o
 obj-y  += clk-rk3288.o
 obj-y  += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c 
b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000..724d467
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clk.h"
+
+enum rk3036_plls {
+   apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+   RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+   RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+   RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+   RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+   RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+   RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+   RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+   RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+   RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+   RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+   RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+   RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+   RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+   RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+   RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+   RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+   RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+   RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+   RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
+   RK3036_PLL_RATE(0, 1, 0, 1, 1, 1, 0),
+   { /* sentinel */ },
+};
+
+#define RK3036_DIV_CPU_MASK0x1f
+#define RK3036_DIV_CPU_SHIFT   8
+
+#define RK3036_DIV_PERI_MASK   0xf
+#define RK3036_DIV_PERI_SHIFT  0
+#define RK3036_DIV_ACLK_MASK   0x7
+#define RK3036_DIV_ACLK_SHIFT  4
+#define RK3036_DIV_HCLK_MASK   0x3
+#define RK3036_DIV_HCLK_SHIFT  8
+#define RK3036_DIV_PCLK_MASK   0x7
+#define RK3036_DIV_PCLK_SHIFT  12
+
+#define RK3036_CLKSEL1(_core_periph_div)   
\
+   {   
\
+   .reg = RK2928_CLKSEL_CON(1),

[PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-17 Thread Xing Zheng

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk-rk3036.c |  504 +
 drivers/clk/rockchip/clk.h|   30 +++
 3 files changed, 535 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
 obj-y  += clk-mmc-phase.o
 obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
+obj-y  += clk-rk3036.o
 obj-y  += clk-rk3188.o
 obj-y  += clk-rk3288.o
 obj-y  += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c 
b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000..724d467
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clk.h"
+
+enum rk3036_plls {
+   apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+   RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+   RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+   RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+   RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+   RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+   RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+   RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+   RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+   RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+   RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+   RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+   RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+   RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+   RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+   RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+   RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+   RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+   RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+   RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
+   RK3036_PLL_RATE(0, 1, 0, 1, 1, 1, 0),
+   { /* sentinel */ },
+};
+
+#define RK3036_DIV_CPU_MASK0x1f
+#define RK3036_DIV_CPU_SHIFT   8
+
+#define RK3036_DIV_PERI_MASK   0xf
+#define RK3036_DIV_PERI_SHIFT  0
+#define RK3036_DIV_ACLK_MASK   0x7
+#define RK3036_DIV_ACLK_SHIFT  4
+#define RK3036_DIV_HCLK_MASK   0x3
+#define RK3036_DIV_HCLK_SHIFT  8
+#define RK3036_DIV_PCLK_MASK   0x7
+#define RK3036_DIV_PCLK_SHIFT  12
+
+#define RK3036_CLKSEL1(_core_periph_div)   
\
+   {

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

2015-09-17 Thread Heiko Stübner

Hi,

Am Donnerstag, 17. September 2015, 16:28:54 schrieb Xing Zheng:
> Add the clock tree definition for the new rk3036 SoC.
> 
> Signed-off-by: Xing Zheng 

missing a dt-bindings document in a separate patch. See "dt-bindings: add 
documentation of rk3668 clock controller" 
(http://lists.infradead.org/pipermail/linux-rockchip/2015-July/003396.html) 
for comparison.


> ---
> 
> Changes in v2: None
> 
>  drivers/clk/rockchip/Makefile |1 +
>  drivers/clk/rockchip/clk-rk3036.c |  504
> + drivers/clk/rockchip/clk.h|  
> 30 +++
>  3 files changed, 535 insertions(+)
>  create mode 100644 drivers/clk/rockchip/clk-rk3036.c
> 
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index b27edd6..d599829 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -10,6 +10,7 @@ obj-y   += clk-inverter.o
>  obj-y+= clk-mmc-phase.o
>  obj-$(CONFIG_RESET_CONTROLLER)   += softrst.o
> 
> +obj-y+= clk-rk3036.o
>  obj-y+= clk-rk3188.o
>  obj-y+= clk-rk3288.o
>  obj-y+= clk-rk3368.o
> diff --git a/drivers/clk/rockchip/clk-rk3036.c
> b/drivers/clk/rockchip/clk-rk3036.c new file mode 100644
> index 000..724d467
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk-rk3036.c
> @@ -0,0 +1,504 @@
> +/*
> + * Copyright (c) 2014 MundoReader S.L.
> + * Author: Heiko Stuebner 
> + *
> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
> + * Author: Xing Zheng 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "clk.h"
> +
> +enum rk3036_plls {
> + apll, dpll, gpll,
> +};
> +
> +static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
> + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
> + RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
> + RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
> + RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
> + RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
> + RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
> + RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
> + RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
> + RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
> + RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
> + RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
> + RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
> + RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
> + RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
> + RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
> + RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
> + RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
> + RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
> + RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
> + RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
> + RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
> + RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
> + RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
> + RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
> + RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
> + RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
> + RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
> + RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
> + RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
> + RK3036_PLL_RATE(0, 1, 0, 1, 1, 1, 0),

you shouldn't need a "0" rate entry I guess


> + { /* sentinel */ },
> +};
> +
> +#define RK3036_DIV_CPU_MASK  0x1f
> +#define RK3036_DIV_CPU_SHIFT 8
> +
> +#define

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

[PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

[PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036

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