Re: [PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
On Thu, May 22, 2014 at 6:59 AM, Zhu, Lejun wrote:
> Devices based on Intel SoC products such as Baytrail have a Power
> Management IC. In the PMIC there are subsystems for voltage regulation,
> A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is called
> Crystal Cove.
>
> This patch adds support for the GPIO function in Crystal Cove.
>
> v2:
> - Use IRQ chip helper to provide irqdomain.
> - Implement .remove and can now build as a module.
> - Various fix for unreadable or ugly code pieces.
> v3:
> - More fix in irq_handler and probe.
(...)
> + gpiochip_irqchip_add(>chip, _irqchip, 0,
> +handle_simple_irq, IRQ_TYPE_NONE);
> +
> + retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
> + IRQF_ONESHOT, KBUILD_MODNAME, cg);
> +
> + if (retval) {
> + dev_warn(>dev, "request irq failed: %d\n", retval);
> + goto out;
> + }
> +
> + retval = gpiochip_add(>chip);
> + if (retval) {
> + dev_warn(>dev, "add gpio chip error: %d\n", retval);
> + goto out_free_irq;
> + }
As concluded from discussion, please switch the order of
gpiochip_irqchip_add() and gpiochip_add() so that the
gpiochip is added first, then the irqchip.
Yours,
Linus Walleij
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Re: [PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
On Thu, May 22, 2014 at 6:59 AM, Zhu, Lejun lejun@linux.intel.com wrote:
Devices based on Intel SoC products such as Baytrail have a Power
Management IC. In the PMIC there are subsystems for voltage regulation,
A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is called
Crystal Cove.
This patch adds support for the GPIO function in Crystal Cove.
v2:
- Use IRQ chip helper to provide irqdomain.
- Implement .remove and can now build as a module.
- Various fix for unreadable or ugly code pieces.
v3:
- More fix in irq_handler and probe.
(...)
+ gpiochip_irqchip_add(cg-chip, crystalcove_irqchip, 0,
+handle_simple_irq, IRQ_TYPE_NONE);
+
+ retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, cg);
+
+ if (retval) {
+ dev_warn(pdev-dev, request irq failed: %d\n, retval);
+ goto out;
+ }
+
+ retval = gpiochip_add(cg-chip);
+ if (retval) {
+ dev_warn(pdev-dev, add gpio chip error: %d\n, retval);
+ goto out_free_irq;
+ }
As concluded from discussion, please switch the order of
gpiochip_irqchip_add() and gpiochip_add() so that the
gpiochip is added first, then the irqchip.
Yours,
Linus Walleij
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Re: [PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
On 5/22/2014 7:15 PM, Mika Westerberg wrote: > I suppose this is dependent on the MFD driver right? If so, this should > probably be merged along with that patch. > The MFD driver has been submitted on LKML as well. I think these two drivers can be pulled into corresponding trees, and meet each other in the Linus tree in the end, right? Best Regards Lejun -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
On Thu, May 22, 2014 at 12:59:03PM +0800, Zhu, Lejun wrote:
> +static int crystalcove_gpio_probe(struct platform_device *pdev)
> +{
> + int irq = platform_get_irq(pdev, 0);
> + struct crystalcove_gpio *cg;
> + int retval;
> + struct device *dev = pdev->dev.parent;
> +
> + cg = devm_kzalloc(>dev, sizeof(*cg), GFP_KERNEL);
> + if (!cg) {
A minor comment here:
return -ENOMEM;
> + retval = -ENOMEM;
> + goto out;
> + }
Other than that this looks good to me,
Reviewed-by: Mika Westerberg
I suppose this is dependent on the MFD driver right? If so, this should
probably be merged along with that patch.
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Re: [PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
On Thu, May 22, 2014 at 12:59:03PM +0800, Zhu, Lejun wrote:
+static int crystalcove_gpio_probe(struct platform_device *pdev)
+{
+ int irq = platform_get_irq(pdev, 0);
+ struct crystalcove_gpio *cg;
+ int retval;
+ struct device *dev = pdev-dev.parent;
+
+ cg = devm_kzalloc(pdev-dev, sizeof(*cg), GFP_KERNEL);
+ if (!cg) {
A minor comment here:
return -ENOMEM;
+ retval = -ENOMEM;
+ goto out;
+ }
Other than that this looks good to me,
Reviewed-by: Mika Westerberg mika.westerb...@linux.intel.com
I suppose this is dependent on the MFD driver right? If so, this should
probably be merged along with that patch.
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
On 5/22/2014 7:15 PM, Mika Westerberg wrote: I suppose this is dependent on the MFD driver right? If so, this should probably be merged along with that patch. The MFD driver has been submitted on LKML as well. I think these two drivers can be pulled into corresponding trees, and meet each other in the Linus tree in the end, right? Best Regards Lejun -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
Devices based on Intel SoC products such as Baytrail have a Power
Management IC. In the PMIC there are subsystems for voltage regulation,
A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is called
Crystal Cove.
This patch adds support for the GPIO function in Crystal Cove.
v2:
- Use IRQ chip helper to provide irqdomain.
- Implement .remove and can now build as a module.
- Various fix for unreadable or ugly code pieces.
v3:
- More fix in irq_handler and probe.
Signed-off-by: Yang, Bin
Signed-off-by: Zhu, Lejun
---
drivers/gpio/Kconfig| 13 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-crystalcove.c | 347
3 files changed, 361 insertions(+)
create mode 100644 drivers/gpio/gpio-crystalcove.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index a86c49a..fed08d9d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -440,6 +440,19 @@ config GPIO_ARIZONA
help
Support for GPIOs on Wolfson Arizona class devices.
+config GPIO_CRYSTAL_COVE
+ tristate "GPIO support for Crystal Cove PMIC"
+ depends on INTEL_SOC_PMIC
+ select GPIOLIB_IRQCHIP
+ help
+ Support for GPIO pins on Crystal Cove PMIC.
+
+ Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC
+ inside.
+
+ This driver can also be built as a module. If so, the module will be
+ called gpio-crystalcove.
+
config GPIO_LP3943
tristate "TI/National Semiconductor LP3943 GPIO expander"
depends on MFD_LP3943
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 6309aff..e6cd935 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
obj-$(CONFIG_GPIO_CLPS711X)+= gpio-clps711x.o
obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
+obj-$(CONFIG_GPIO_CRYSTAL_COVE)+= gpio-crystalcove.o
obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c
new file mode 100644
index 000..ea6ae1d
--- /dev/null
+++ b/drivers/gpio/gpio-crystalcove.c
@@ -0,0 +1,347 @@
+/*
+ * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
+ *
+ * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Author: Yang, Bin
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define NUM_GPIO 16
+
+#define UPDATE_TYPEBIT(0)
+#define UPDATE_MASKBIT(1)
+
+#define GPIO0IRQ 0x0b
+#define GPIO1IRQ 0x0c
+#define MGPIO0IRQS00x19
+#define MGPIO1IRQS00x1a
+#define MGPIO0IRQSX0x1b
+#define MGPIO1IRQSX0x1c
+#define GPIO0P0CTLO0x2b
+#define GPIO0P0CTLI0x33
+#define GPIO1P0CTLO0x3b
+#define GPIO1P0CTLI0x43
+
+#define CTLI_INTCNT_NE (1 << 1)
+#define CTLI_INTCNT_PE (2 << 1)
+#define CTLI_INTCNT_BE (3 << 1)
+
+#define CTLO_DIR_OUT (1 << 5)
+
+#define CTLO_DRV_CMOS (0 << 4)
+#define CTLO_DRV_OD(1 << 4)
+
+#define CTLO_DRV_REN (1 << 3)
+
+#define CTLO_RVAL_2KDW (0)
+#define CTLO_RVAL_2KUP (1 << 1)
+#define CTLO_RVAL_50KDW(2 << 1)
+#define CTLO_RVAL_50KUP(3 << 1)
+
+#define CTLO_INPUT_DEF (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
+#define CTLO_OUTPUT_DEF(CTLO_DIR_OUT | CTLO_INPUT_DEF)
+
+#define GPIO_TO_CTL(gpio, dir) \
+ ((gpio < 8 ? GPIO0P0CTL ## dir : GPIO1P0CTL ## dir) + (gpio % 8))
+
+/**
+ * struct crystalcove_gpio - Crystal Cove GPIO controller
+ * @buslock: for bus lock/sync and unlock.
+ * @chip: the abstract gpio_chip structure.
+ * @update: pending IRQ setting update, to be written to the chip upon unlock.
+ * @trigger_type: the trigger type of the IRQ.
+ * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
+ */
+struct crystalcove_gpio {
+ struct mutexbuslock; /* irq_bus_lock */
+ struct gpio_chipchip;
+ int update;
+ int trigger_type;
+ boolset_irq_mask;
+};
+
+static void
[PATCH v3] gpio: Add support for Intel SoC PMIC (Crystal Cove)
Devices based on Intel SoC products such as Baytrail have a Power
Management IC. In the PMIC there are subsystems for voltage regulation,
A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is called
Crystal Cove.
This patch adds support for the GPIO function in Crystal Cove.
v2:
- Use IRQ chip helper to provide irqdomain.
- Implement .remove and can now build as a module.
- Various fix for unreadable or ugly code pieces.
v3:
- More fix in irq_handler and probe.
Signed-off-by: Yang, Bin bin.y...@intel.com
Signed-off-by: Zhu, Lejun lejun@linux.intel.com
---
drivers/gpio/Kconfig| 13 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-crystalcove.c | 347
3 files changed, 361 insertions(+)
create mode 100644 drivers/gpio/gpio-crystalcove.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index a86c49a..fed08d9d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -440,6 +440,19 @@ config GPIO_ARIZONA
help
Support for GPIOs on Wolfson Arizona class devices.
+config GPIO_CRYSTAL_COVE
+ tristate GPIO support for Crystal Cove PMIC
+ depends on INTEL_SOC_PMIC
+ select GPIOLIB_IRQCHIP
+ help
+ Support for GPIO pins on Crystal Cove PMIC.
+
+ Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC
+ inside.
+
+ This driver can also be built as a module. If so, the module will be
+ called gpio-crystalcove.
+
config GPIO_LP3943
tristate TI/National Semiconductor LP3943 GPIO expander
depends on MFD_LP3943
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 6309aff..e6cd935 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
obj-$(CONFIG_GPIO_CLPS711X)+= gpio-clps711x.o
obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
+obj-$(CONFIG_GPIO_CRYSTAL_COVE)+= gpio-crystalcove.o
obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c
new file mode 100644
index 000..ea6ae1d
--- /dev/null
+++ b/drivers/gpio/gpio-crystalcove.c
@@ -0,0 +1,347 @@
+/*
+ * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
+ *
+ * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Author: Yang, Bin bin.y...@intel.com
+ */
+
+#include linux/module.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/seq_file.h
+#include linux/sched.h
+#include linux/mfd/intel_soc_pmic.h
+#include linux/gpio.h
+#include linux/bitops.h
+
+#define NUM_GPIO 16
+
+#define UPDATE_TYPEBIT(0)
+#define UPDATE_MASKBIT(1)
+
+#define GPIO0IRQ 0x0b
+#define GPIO1IRQ 0x0c
+#define MGPIO0IRQS00x19
+#define MGPIO1IRQS00x1a
+#define MGPIO0IRQSX0x1b
+#define MGPIO1IRQSX0x1c
+#define GPIO0P0CTLO0x2b
+#define GPIO0P0CTLI0x33
+#define GPIO1P0CTLO0x3b
+#define GPIO1P0CTLI0x43
+
+#define CTLI_INTCNT_NE (1 1)
+#define CTLI_INTCNT_PE (2 1)
+#define CTLI_INTCNT_BE (3 1)
+
+#define CTLO_DIR_OUT (1 5)
+
+#define CTLO_DRV_CMOS (0 4)
+#define CTLO_DRV_OD(1 4)
+
+#define CTLO_DRV_REN (1 3)
+
+#define CTLO_RVAL_2KDW (0)
+#define CTLO_RVAL_2KUP (1 1)
+#define CTLO_RVAL_50KDW(2 1)
+#define CTLO_RVAL_50KUP(3 1)
+
+#define CTLO_INPUT_DEF (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
+#define CTLO_OUTPUT_DEF(CTLO_DIR_OUT | CTLO_INPUT_DEF)
+
+#define GPIO_TO_CTL(gpio, dir) \
+ ((gpio 8 ? GPIO0P0CTL ## dir : GPIO1P0CTL ## dir) + (gpio % 8))
+
+/**
+ * struct crystalcove_gpio - Crystal Cove GPIO controller
+ * @buslock: for bus lock/sync and unlock.
+ * @chip: the abstract gpio_chip structure.
+ * @update: pending IRQ setting update, to be written to the chip upon unlock.
+ * @trigger_type: the trigger type of the IRQ.
+ * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
+ */
+struct crystalcove_gpio {
+ struct mutexbuslock; /*
