Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210
> > This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has > one memory bus to translate data between DRAM and eMMC/sub-IPs because > Exynos4210 must need only one regulator for memory bus. > > Following list specifies the detailed relation between memory bus clock and > sub-IPs: > - DMC/ACP clock : DMC (Dynamic Memory Controller) > - ACLK200 clock : LCD0 > - ACLK100 clock : PERIL/PERIR/MFC(PCLK) > - ACLK160 clock : CAM/TV/LCD0/LCD1 > - ACLK133 clock : FSYS/GPS > - GDL/GDR clock : leftbus/rightbus > - SCLK_MFC clock : MFC > > Cc: Kukjin Kim > Cc: Myungjoo Ham > Cc: Kyungmin Park > Signed-off-by: Chanwoo Choi Acked-by: MyungJoo Ham Revisiting good old days..? (good to see the first busfreq driver experimented with is being DT-nized... :) ) Cheers, MyungJoo
Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has one memory bus to translate data between DRAM and eMMC/sub-IPs because Exynos4210 must need only one regulator for memory bus. Following list specifies the detailed relation between memory bus clock and sub-IPs: - DMC/ACP clock : DMC (Dynamic Memory Controller) - ACLK200 clock : LCD0 - ACLK100 clock : PERIL/PERIR/MFC(PCLK) - ACLK160 clock : CAM/TV/LCD0/LCD1 - ACLK133 clock : FSYS/GPS - GDL/GDR clock : leftbus/rightbus - SCLK_MFC clock : MFC Cc: Kukjin Kim kg...@kernel.org Cc: Myungjoo Ham myungjoo@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: MyungJoo Ham myungjoo@samsung.com Revisiting good old days..? (good to see the first busfreq driver experimented with is being DT-nized... :) ) Cheers, MyungJoo
[PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has one memory bus to translate data between DRAM and eMMC/sub-IPs because Exynos4210 must need only one regulator for memory bus. Following list specifies the detailed relation between memory bus clock and sub-IPs: - DMC/ACP clock : DMC (Dynamic Memory Controller) - ACLK200 clock : LCD0 - ACLK100 clock : PERIL/PERIR/MFC(PCLK) - ACLK160 clock : CAM/TV/LCD0/LCD1 - ACLK133 clock : FSYS/GPS - GDL/GDR clock : leftbus/rightbus - SCLK_MFC clock : MFC Cc: Kukjin Kim Cc: Myungjoo Ham Cc: Kyungmin Park Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos4210.dtsi | 93 +++ 1 file changed, 93 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b2598de..c039409 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -48,6 +48,99 @@ }; }; + memory_bus: memory_bus@0 { + compatible = "samsung,exynos-memory-bus"; + + operating-points = < + 40 115 + 267000 105 + 133000 1025000>; + status = "disabled"; + + blocks { + dmc_block: memory_bus_block1 { + clocks = < CLK_DIV_DMC>; + clock-names = "memory-bus"; + frequency = < + 40 + 267000 + 133000>; + }; + + acp_block: memory_bus_block2 { + clocks = < CLK_DIV_ACP>; + clock-names = "memory-bus"; + frequency = < + 20 + 16 + 133000>; + }; + + peri_block: memory_bus_block3 { + clocks = < CLK_ACLK100>; + clock-names = "memory-bus"; + frequency = < + 10 + 10 + 10>; + }; + + fsys_block: memory_bus_block4 { + clocks = < CLK_ACLK133>; + clock-names = "memory-bus"; + frequency = < + 133000 + 133000 + 10>; + }; + + display_block: memory_bus_block5 { + clocks = < CLK_ACLK160>; + clock-names = "memory-bus"; + frequency = < + 16 + 133000 + 10>; + }; + + lcd0_block: memory_bus_block6 { + clocks = < CLK_ACLK200>; + clock-names = "memory-bus"; + frequency = < + 20 + 16 + 10>; + }; + + leftbus_block: memory_bus_block7 { + clocks = < CLK_DIV_GDL>; + clock-names = "memory-bus"; + frequency = < + 20 + 16 + 10>; + }; + + rightbus_block: memory_bus_block8 { + clocks = < CLK_DIV_GDR>; + clock-names = "memory-bus"; + frequency = < + 20 + 16 + 10>; + }; + + mfc_block: memory_bus_block9 { + clocks = < CLK_SCLK_MFC>; + clock-names = "memory-bus"; + frequency = < + 20 + 16 + 10>; + }; + }; + }; + pmu_system_controller: system-controller@1002 { clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
[PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has one memory bus to translate data between DRAM and eMMC/sub-IPs because Exynos4210 must need only one regulator for memory bus. Following list specifies the detailed relation between memory bus clock and sub-IPs: - DMC/ACP clock : DMC (Dynamic Memory Controller) - ACLK200 clock : LCD0 - ACLK100 clock : PERIL/PERIR/MFC(PCLK) - ACLK160 clock : CAM/TV/LCD0/LCD1 - ACLK133 clock : FSYS/GPS - GDL/GDR clock : leftbus/rightbus - SCLK_MFC clock : MFC Cc: Kukjin Kim kg...@kernel.org Cc: Myungjoo Ham myungjoo@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com --- arch/arm/boot/dts/exynos4210.dtsi | 93 +++ 1 file changed, 93 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b2598de..c039409 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -48,6 +48,99 @@ }; }; + memory_bus: memory_bus@0 { + compatible = samsung,exynos-memory-bus; + + operating-points = + 40 115 + 267000 105 + 133000 1025000; + status = disabled; + + blocks { + dmc_block: memory_bus_block1 { + clocks = clock CLK_DIV_DMC; + clock-names = memory-bus; + frequency = + 40 + 267000 + 133000; + }; + + acp_block: memory_bus_block2 { + clocks = clock CLK_DIV_ACP; + clock-names = memory-bus; + frequency = + 20 + 16 + 133000; + }; + + peri_block: memory_bus_block3 { + clocks = clock CLK_ACLK100; + clock-names = memory-bus; + frequency = + 10 + 10 + 10; + }; + + fsys_block: memory_bus_block4 { + clocks = clock CLK_ACLK133; + clock-names = memory-bus; + frequency = + 133000 + 133000 + 10; + }; + + display_block: memory_bus_block5 { + clocks = clock CLK_ACLK160; + clock-names = memory-bus; + frequency = + 16 + 133000 + 10; + }; + + lcd0_block: memory_bus_block6 { + clocks = clock CLK_ACLK200; + clock-names = memory-bus; + frequency = + 20 + 16 + 10; + }; + + leftbus_block: memory_bus_block7 { + clocks = clock CLK_DIV_GDL; + clock-names = memory-bus; + frequency = + 20 + 16 + 10; + }; + + rightbus_block: memory_bus_block8 { + clocks = clock CLK_DIV_GDR; + clock-names = memory-bus; + frequency = + 20 + 16 + 10; + }; + + mfc_block: memory_bus_block9 { + clocks = clock CLK_SCLK_MFC; + clock-names = memory-bus; + frequency = + 20 + 16 + 10; + }; + }; + }; + pmu_system_controller: system-controller@1002 { clock-names