RE: [PATCH v5 1/4] phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver
Hi,
Thank you for the review!
> From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
> Sent: Friday, November 27, 2015 2:21 PM
>
> Hi,
>
> On Tuesday 20 October 2015 02:27 PM, Yoshihiro Shimoda wrote:
> > This patch adds support for R-Car generation 3 USB2 PHY driver.
> > This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
> > with the HSUSB (USB2.0 peripheral) device. And each channel has
> > independent registers about the PHYs.
> >
> > So, the purpose of this driver is:
> > 1) initializes some registers of SoC specific to use the
> > {ehci,ohci}-platform driver.
> >
> > 2) detects id pin to select host or peripheral on the channel 0.
> >
> > For now, this driver only supports 1) above.
>
> When you do 2), make sure to use the extcon framework.
Thank you for your proposal! I will use the extcon framework for it.
> One minor comment below and then I can queue it for 4.5.
Thank you!
< snip >
> > + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> > + if (IS_ERR(provider)) {
> > + dev_err(dev, "Failed to register PHY provider\n");
> > + return PTR_ERR(provider);
> > + }
> > +
> > + return 0;
>
> This can simply be replaced with return PTR_ERR_OR_ZERO(provider);
Yes, I tested that this could simply be replaced with "return
PTR_ERR_OR_ZERO(provider);".
So, should I send v6 patch?
Best regards,
Yoshihiro Shimoda
> Thanks
> Kishon
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 1/4] phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver
Hi,
On Tuesday 20 October 2015 02:27 PM, Yoshihiro Shimoda wrote:
> This patch adds support for R-Car generation 3 USB2 PHY driver.
> This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
> with the HSUSB (USB2.0 peripheral) device. And each channel has
> independent registers about the PHYs.
>
> So, the purpose of this driver is:
> 1) initializes some registers of SoC specific to use the
> {ehci,ohci}-platform driver.
>
> 2) detects id pin to select host or peripheral on the channel 0.
>
> For now, this driver only supports 1) above.
When you do 2), make sure to use the extcon framework.
One minor comment below and then I can queue it for 4.5.
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> .../devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 37
> drivers/phy/Kconfig| 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rcar-gen3-usb2.c | 219
> +
> 4 files changed, 264 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
> create mode 100644 drivers/phy/phy-rcar-gen3-usb2.c
>
> diff --git a/drivers/phy/phy-rcar-gen3-usb2.c
> b/drivers/phy/phy-rcar-gen3-usb2.c
> new file mode 100644
> index 000..9d9cf26
> --- /dev/null
> +++ b/drivers/phy/phy-rcar-gen3-usb2.c
> @@ -0,0 +1,219 @@
> +/*
> + * Renesas R-Car Gen3 for USB2.0 PHY driver
> + *
> + * Copyright (C) 2015 Renesas Electronics Corporation
> + *
> + * This is based on the phy-rcar-gen2 driver:
> + * Copyright (C) 2014 Renesas Solutions Corp.
> + * Copyright (C) 2014 Cogent Embedded, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/*** USB2.0 Host registers (original offset is +0x200) ***/
> +#define USB2_INT_ENABLE 0x000
> +#define USB2_USBCTR 0x00c
> +#define USB2_SPD_RSM_TIMSET 0x10c
> +#define USB2_OC_TIMSET 0x110
> +
> +/* INT_ENABLE */
> +#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
> +#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
> +#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_USBH_INTB_EN | \
> + USB2_INT_ENABLE_USBH_INTA_EN)
> +
> +/* USBCTR */
> +#define USB2_USBCTR_DIRPDBIT(2)
> +#define USB2_USBCTR_PLL_RST BIT(1)
> +
> +/* SPD_RSM_TIMSET */
> +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
> +
> +/* OC_TIMSET */
> +#define USB2_OC_TIMSET_INIT 0x000209ab
> +
> +/*** HSUSB registers (original offset is +0x100) ***/
> +#define HSUSB_LPSTS 0x02
> +#define HSUSB_UGCTRL20x84
> +
> +/* Low Power Status register (LPSTS) */
> +#define HSUSB_LPSTS_SUSPM0x4000
> +
> +/* USB General control register 2 (UGCTRL2) */
> +#define HSUSB_UGCTRL2_MASK 0x0031 /* bit[31:6] should be 0 */
> +#define HSUSB_UGCTRL2_USB0SEL0x0030
> +#define HSUSB_UGCTRL2_USB0SEL_HOST 0x0010
> +#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x0020
> +#define HSUSB_UGCTRL2_USB0SEL_OTG0x0030
> +
> +struct rcar_gen3_data {
> + void __iomem *base;
> + struct clk *clk;
> +};
> +
> +struct rcar_gen3_chan {
> + struct rcar_gen3_data usb2;
> + struct rcar_gen3_data hsusb;
> + struct phy *phy;
> +};
> +
> +static int rcar_gen3_phy_usb2_init(struct phy *p)
> +{
> + struct rcar_gen3_chan *channel = phy_get_drvdata(p);
> + void __iomem *usb2_base = channel->usb2.base;
> + void __iomem *hsusb_base = channel->hsusb.base;
> + u32 val;
> +
> + /* Initialize USB2 part */
> + writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
> + writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
> + writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
> +
> + /* Initialize HSUSB part */
> + if (hsusb_base) {
> + /* TODO: support "OTG" mode */
> + val = readl(hsusb_base + HSUSB_UGCTRL2);
> + val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
> + HSUSB_UGCTRL2_USB0SEL_HOST;
> + writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
> + }
> +
> + return 0;
> +}
> +
> +static int rcar_gen3_phy_usb2_exit(struct phy *p)
> +{
> + struct rcar_gen3_chan *channel = phy_get_drvdata(p);
> +
> + writel(0, channel->usb2.base + USB2_INT_ENABLE);
> +
> + return 0;
> +}
> +
> +static int rcar_gen3_phy_usb2_power_on(struct phy *p)
> +{
> + struct rcar_gen3_chan *channel = phy_get_drvdata(p);
> + void __iomem *usb2_base = channel->usb2.base;
> + void __iomem *hsusb_base = channel->hsusb.base;
> + u32 val;
> +
> + val = readl(usb2_base + USB2_USBCTR);
> + val |= USB2_USBCTR_PLL_RST;
> + writel(val,
Re: [PATCH v5 1/4] phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver
Hi,
On Tuesday 20 October 2015 02:27 PM, Yoshihiro Shimoda wrote:
> This patch adds support for R-Car generation 3 USB2 PHY driver.
> This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
> with the HSUSB (USB2.0 peripheral) device. And each channel has
> independent registers about the PHYs.
>
> So, the purpose of this driver is:
> 1) initializes some registers of SoC specific to use the
> {ehci,ohci}-platform driver.
>
> 2) detects id pin to select host or peripheral on the channel 0.
>
> For now, this driver only supports 1) above.
When you do 2), make sure to use the extcon framework.
One minor comment below and then I can queue it for 4.5.
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> .../devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 37
> drivers/phy/Kconfig| 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rcar-gen3-usb2.c | 219
> +
> 4 files changed, 264 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
> create mode 100644 drivers/phy/phy-rcar-gen3-usb2.c
>
> diff --git a/drivers/phy/phy-rcar-gen3-usb2.c
> b/drivers/phy/phy-rcar-gen3-usb2.c
> new file mode 100644
> index 000..9d9cf26
> --- /dev/null
> +++ b/drivers/phy/phy-rcar-gen3-usb2.c
> @@ -0,0 +1,219 @@
> +/*
> + * Renesas R-Car Gen3 for USB2.0 PHY driver
> + *
> + * Copyright (C) 2015 Renesas Electronics Corporation
> + *
> + * This is based on the phy-rcar-gen2 driver:
> + * Copyright (C) 2014 Renesas Solutions Corp.
> + * Copyright (C) 2014 Cogent Embedded, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/*** USB2.0 Host registers (original offset is +0x200) ***/
> +#define USB2_INT_ENABLE 0x000
> +#define USB2_USBCTR 0x00c
> +#define USB2_SPD_RSM_TIMSET 0x10c
> +#define USB2_OC_TIMSET 0x110
> +
> +/* INT_ENABLE */
> +#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
> +#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
> +#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_USBH_INTB_EN | \
> + USB2_INT_ENABLE_USBH_INTA_EN)
> +
> +/* USBCTR */
> +#define USB2_USBCTR_DIRPDBIT(2)
> +#define USB2_USBCTR_PLL_RST BIT(1)
> +
> +/* SPD_RSM_TIMSET */
> +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
> +
> +/* OC_TIMSET */
> +#define USB2_OC_TIMSET_INIT 0x000209ab
> +
> +/*** HSUSB registers (original offset is +0x100) ***/
> +#define HSUSB_LPSTS 0x02
> +#define HSUSB_UGCTRL20x84
> +
> +/* Low Power Status register (LPSTS) */
> +#define HSUSB_LPSTS_SUSPM0x4000
> +
> +/* USB General control register 2 (UGCTRL2) */
> +#define HSUSB_UGCTRL2_MASK 0x0031 /* bit[31:6] should be 0 */
> +#define HSUSB_UGCTRL2_USB0SEL0x0030
> +#define HSUSB_UGCTRL2_USB0SEL_HOST 0x0010
> +#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x0020
> +#define HSUSB_UGCTRL2_USB0SEL_OTG0x0030
> +
> +struct rcar_gen3_data {
> + void __iomem *base;
> + struct clk *clk;
> +};
> +
> +struct rcar_gen3_chan {
> + struct rcar_gen3_data usb2;
> + struct rcar_gen3_data hsusb;
> + struct phy *phy;
> +};
> +
> +static int rcar_gen3_phy_usb2_init(struct phy *p)
> +{
> + struct rcar_gen3_chan *channel = phy_get_drvdata(p);
> + void __iomem *usb2_base = channel->usb2.base;
> + void __iomem *hsusb_base = channel->hsusb.base;
> + u32 val;
> +
> + /* Initialize USB2 part */
> + writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
> + writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
> + writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
> +
> + /* Initialize HSUSB part */
> + if (hsusb_base) {
> + /* TODO: support "OTG" mode */
> + val = readl(hsusb_base + HSUSB_UGCTRL2);
> + val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
> + HSUSB_UGCTRL2_USB0SEL_HOST;
> + writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
> + }
> +
> + return 0;
> +}
> +
> +static int rcar_gen3_phy_usb2_exit(struct phy *p)
> +{
> + struct rcar_gen3_chan *channel = phy_get_drvdata(p);
> +
> + writel(0, channel->usb2.base + USB2_INT_ENABLE);
> +
> + return 0;
> +}
> +
> +static int rcar_gen3_phy_usb2_power_on(struct phy *p)
> +{
> + struct rcar_gen3_chan *channel = phy_get_drvdata(p);
> + void __iomem *usb2_base = channel->usb2.base;
> + void __iomem *hsusb_base = channel->hsusb.base;
> + u32 val;
> +
> + val = readl(usb2_base + USB2_USBCTR);
> + val |=
RE: [PATCH v5 1/4] phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver
Hi,
Thank you for the review!
> From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
> Sent: Friday, November 27, 2015 2:21 PM
>
> Hi,
>
> On Tuesday 20 October 2015 02:27 PM, Yoshihiro Shimoda wrote:
> > This patch adds support for R-Car generation 3 USB2 PHY driver.
> > This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
> > with the HSUSB (USB2.0 peripheral) device. And each channel has
> > independent registers about the PHYs.
> >
> > So, the purpose of this driver is:
> > 1) initializes some registers of SoC specific to use the
> > {ehci,ohci}-platform driver.
> >
> > 2) detects id pin to select host or peripheral on the channel 0.
> >
> > For now, this driver only supports 1) above.
>
> When you do 2), make sure to use the extcon framework.
Thank you for your proposal! I will use the extcon framework for it.
> One minor comment below and then I can queue it for 4.5.
Thank you!
< snip >
> > + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> > + if (IS_ERR(provider)) {
> > + dev_err(dev, "Failed to register PHY provider\n");
> > + return PTR_ERR(provider);
> > + }
> > +
> > + return 0;
>
> This can simply be replaced with return PTR_ERR_OR_ZERO(provider);
Yes, I tested that this could simply be replaced with "return
PTR_ERR_OR_ZERO(provider);".
So, should I send v6 patch?
Best regards,
Yoshihiro Shimoda
> Thanks
> Kishon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
