RE: [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes
Hi Karthikeyan,
Thanks a lot for your comments!
> -Original Message-
> From: Karthikeyan Mitran [mailto:m.karthike...@mobiveil.co.in]
> Sent: 2019年6月3日 13:13
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; robh...@kernel.org; a...@arndb.de;
> mark.rutl...@arm.com; l.subrahma...@mobiveil.co.in;
> shawn...@kernel.org; Leo Li ;
> lorenzo.pieral...@arm.com; catalin.mari...@arm.com;
> will.dea...@arm.com; Mingkai Hu ; M.h. Lian
> ; Xiaowei Bao
> Subject: Re: [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes
>
> Hi Hou Zhiqiang
>Two instances [@360 and @380] of the six has a different
> window count, the RC can not have more than 8 windows.
> apio-wins = <256>; //Can we change it to 8
> ppio-wins = <24>;//Can we change it to 8
>
I checked with hardware team, the PCIe controllers @360 and @380 support
up to x8 and SRIOV, these 2 controllers have different number of inbound and
outbound
windows from the other 4 PCIe controllers which are support up to x4 and not
support
SRIOV.
> On Tue, May 28, 2019 at 12:20 PM Z.q. Hou wrote:
> >
> > From: Hou Zhiqiang
> >
> > The LX2160A integrated 6 PCIe Gen4 controllers.
> >
> > Signed-off-by: Hou Zhiqiang
> > Reviewed-by: Minghuan Lian
> > ---
> > V6:
> > - No change.
> >
> > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163
> > ++
> > 1 file changed, 163 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index 125a8cc2c5b3..7a2b91ff1fbc 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -964,5 +964,168 @@
> > };
> > };
> > };
> > +
> > + pcie@340 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x0340 0x0 0x0010
> /* controller registers */
> > + 0x80 0x 0x0 0x1000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + apio-wins = <8>;
> > + ppio-wins = <8>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x8200 0x0 0x4000 0x80
> 0x4000 0x0 0x4000>; /* non-prefetchable memory */
> > + msi-parent = <>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = < 0 0 1 0 0 GIC_SPI
> 109 IRQ_TYPE_LEVEL_HIGH>,
> > + < 0 0 2 0 0
> GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > + < 0 0 3 0 0
> GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > + < 0 0 4 0 0
> GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + pcie@350 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x0350 0x0 0x0010
> /* controller registers */
> > + 0x88 0x 0x0 0x1000>;
> /* configuration space */
> > + reg-names = "csr_axi_slave",
> "config_axi_slave";
> > + interrupts = IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + IRQ_TYPE_LEVEL_HIGH>; /* controll
Re: [PATCHv6 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes
Hi Hou Zhiqiang
Two instances [@360 and @380] of the six has a different
window count, the RC can not have more than 8 windows.
apio-wins = <256>; //Can we change it to 8
ppio-wins = <24>;//Can we change it to 8
On Tue, May 28, 2019 at 12:20 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The LX2160A integrated 6 PCIe Gen4 controllers.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V6:
> - No change.
>
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++
> 1 file changed, 163 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 125a8cc2c5b3..7a2b91ff1fbc 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -964,5 +964,168 @@
> };
> };
> };
> +
> + pcie@340 {
> + compatible = "fsl,lx2160a-pcie";
> + reg = <0x00 0x0340 0x0 0x0010 /* controller
> registers */
> + 0x80 0x 0x0 0x1000>; /*
> configuration space */
> + reg-names = "csr_axi_slave", "config_axi_slave";
> + interrupts = , /*
> AER interrupt */
> +, /*
> PME interrupt */
> +; /*
> controller interrupt */
> + interrupt-names = "aer", "pme", "intr";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + dma-coherent;
> + apio-wins = <8>;
> + ppio-wins = <8>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x8200 0x0 0x4000 0x80 0x4000
> 0x0 0x4000>; /* non-prefetchable memory */
> + msi-parent = <>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = < 0 0 1 0 0 GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 2 0 0 GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 3 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 4 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + pcie@350 {
> + compatible = "fsl,lx2160a-pcie";
> + reg = <0x00 0x0350 0x0 0x0010 /* controller
> registers */
> + 0x88 0x 0x0 0x1000>; /*
> configuration space */
> + reg-names = "csr_axi_slave", "config_axi_slave";
> + interrupts = , /*
> AER interrupt */
> +, /*
> PME interrupt */
> +; /*
> controller interrupt */
> + interrupt-names = "aer", "pme", "intr";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + dma-coherent;
> + apio-wins = <8>;
> + ppio-wins = <8>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x8200 0x0 0x4000 0x88 0x4000
> 0x0 0x4000>; /* non-prefetchable memory */
> + msi-parent = <>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = < 0 0 1 0 0 GIC_SPI 114
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 2 0 0 GIC_SPI 115
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 3 0 0 GIC_SPI 116
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 4 0 0 GIC_SPI 117
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + pcie@360 {
> + compatible = "fsl,lx2160a-pcie";
> + reg = <0x00 0x0360 0x0 0x0010 /* controller
> registers */
> + 0x90 0x 0x0 0x1000>; /*
> configuration space */
> + reg-names = "csr_axi_slave", "config_axi_slave";
> + interrupts = , /*
> AER interrupt */
> +, /*
> PME interrupt */
> +; /*
> controller interrupt */
> + interrupt-names = "aer", "pme", "intr";
> + #address-cells = <3>;
> + #size-cells
