Re: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Hi Rob,
On 8/27/2019 10:04 PM, Dilip Kota wrote:
Hi Rob,
On 8/26/2019 7:23 PM, Rob Herring wrote:
On Mon, Aug 26, 2019 at 4:52 AM Dilip Kota
wrote:
Hi Rob,
On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota
wrote:
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota
---
Changes on v2:
Address review comments
Update the compatible property definition
Add description for reset-cells
Add 'additionalProperties: false' property
.../bindings/reset/intel,syscon-reset.yaml | 53
++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
diff --git
a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index ..3403a967190a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightening Mountain SoC System Reset Controller
+
+maintainers:
+ - Dilip Kota
+
+properties:
+ compatible:
+ items:
+ - const: intel,rcu-lgm
+ - const: syscon
+
+ reg:
+ description: Reset controller register base address and size
+
+ intel,global-reset:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Global reset register offset and bit offset.
+
+ "#reset-cells":
+ const: 2
+ description: |
+ The 1st cell is the register offset.
+ The 2nd cell is the bit offset in the register.
+
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rcu0: reset-controller@ {
+ compatible = "intel,rcu-lgm", "syscon";
+ reg = <0x00 0x8>;
+ intel,global-reset = <0x10 30>;
+ #reset-cells = <2>;
+ };
+
+ pcie_phy0: pciephy@... {
+ ...
You need to run 'make dt_binding_check' and fix the warnings. The
example has to be buildable and it is not.
Sure, i will correct this pcie_phy0 node. But i didn't get any
warnings
for make dt_binding_check
CHKDT
Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
DTC Documentation/devicetree/bindings/arm/renesas.example.dt.yaml
FATAL ERROR: Unknown output format "yaml"
Will DTC report about the example node errors? But, DTC is failing with
FATAL_ERROR.
I tried it even after installing libyaml and headers in my local
directory and export the path, but no luck.(ref:
https://lkml.org/lkml/2018/12/3/951)
Could you please let me know if i miss anything and help me to proceed
further.
See Documentation/devicetree/writing-schema.md
I have followed all the steps mentioned in the document before keeping
the mail itself.
Does the dtc script looks for libyaml and its header files at any
default or specific location?
DTC is working for me now.
It is working for me after updating the libyaml and header paths in
scripts/dtc/Makefile and yamltree.c (since i have installed libyaml and
header files in my local directories)
I have fixed all the warnings and DTC checks are successful. I will push
the changes in the next patch version.
DTC
Documentation/devicetree/bindings/reset/intel,syscon-reset.example.dt.yaml
CHECK
Documentation/devicetree/bindings/reset/intel,syscon-reset.example.dt.yaml
Regards,
Dilip
Re: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Hi Rob,
On 8/26/2019 7:23 PM, Rob Herring wrote:
On Mon, Aug 26, 2019 at 4:52 AM Dilip Kota wrote:
Hi Rob,
On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota wrote:
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota
---
Changes on v2:
Address review comments
Update the compatible property definition
Add description for reset-cells
Add 'additionalProperties: false' property
.../bindings/reset/intel,syscon-reset.yaml | 53
++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index ..3403a967190a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightening Mountain SoC System Reset Controller
+
+maintainers:
+ - Dilip Kota
+
+properties:
+ compatible:
+items:
+ - const: intel,rcu-lgm
+ - const: syscon
+
+ reg:
+description: Reset controller register base address and size
+
+ intel,global-reset:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description: Global reset register offset and bit offset.
+
+ "#reset-cells":
+const: 2
+description: |
+ The 1st cell is the register offset.
+ The 2nd cell is the bit offset in the register.
+
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+rcu0: reset-controller@ {
+compatible = "intel,rcu-lgm", "syscon";
+reg = <0x00 0x8>;
+intel,global-reset = <0x10 30>;
+#reset-cells = <2>;
+};
+
+pcie_phy0: pciephy@... {
+...
You need to run 'make dt_binding_check' and fix the warnings. The
example has to be buildable and it is not.
Sure, i will correct this pcie_phy0 node. But i didn't get any warnings
for make dt_binding_check
CHKDT Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
DTC Documentation/devicetree/bindings/arm/renesas.example.dt.yaml
FATAL ERROR: Unknown output format "yaml"
Will DTC report about the example node errors? But, DTC is failing with
FATAL_ERROR.
I tried it even after installing libyaml and headers in my local
directory and export the path, but no luck.(ref:
https://lkml.org/lkml/2018/12/3/951)
Could you please let me know if i miss anything and help me to proceed
further.
See Documentation/devicetree/writing-schema.md
I have followed all the steps mentioned in the document before keeping
the mail itself.
Does the dtc script looks for libyaml and its header files at any
default or specific location?
Regards,
Dilip
Rob
Re: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
On Mon, Aug 26, 2019 at 4:52 AM Dilip Kota wrote:
>
> Hi Rob,
>
> On 8/23/2019 8:25 PM, Rob Herring wrote:
> > On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota
> > wrote:
> >> Add YAML schemas for the reset controller on Intel
> >> Lightening Mountain (LGM) SoC.
> >>
> >> Signed-off-by: Dilip Kota
> >> ---
> >> Changes on v2:
> >> Address review comments
> >>Update the compatible property definition
> >>Add description for reset-cells
> >>Add 'additionalProperties: false' property
> >>
> >> .../bindings/reset/intel,syscon-reset.yaml | 53
> >> ++
> >> 1 file changed, 53 insertions(+)
> >> create mode 100644
> >> Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> >> b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> >> new file mode 100644
> >> index ..3403a967190a
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> >> @@ -0,0 +1,53 @@
> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Intel Lightening Mountain SoC System Reset Controller
> >> +
> >> +maintainers:
> >> + - Dilip Kota
> >> +
> >> +properties:
> >> + compatible:
> >> +items:
> >> + - const: intel,rcu-lgm
> >> + - const: syscon
> >> +
> >> + reg:
> >> +description: Reset controller register base address and size
> >> +
> >> + intel,global-reset:
> >> +$ref: /schemas/types.yaml#/definitions/uint32-array
> >> +description: Global reset register offset and bit offset.
> >> +
> >> + "#reset-cells":
> >> +const: 2
> >> +description: |
> >> + The 1st cell is the register offset.
> >> + The 2nd cell is the bit offset in the register.
> >> +
> >> +required:
> >> + - compatible
> >> + - reg
> >> + - intel,global-reset
> >> + - "#reset-cells"
> >> +
> >> +additionalProperties: false
> >> +
> >> +examples:
> >> + - |
> >> +rcu0: reset-controller@ {
> >> +compatible = "intel,rcu-lgm", "syscon";
> >> +reg = <0x00 0x8>;
> >> +intel,global-reset = <0x10 30>;
> >> +#reset-cells = <2>;
> >> +};
> >> +
> >> +pcie_phy0: pciephy@... {
> >> +...
> > You need to run 'make dt_binding_check' and fix the warnings. The
> > example has to be buildable and it is not.
>
> Sure, i will correct this pcie_phy0 node. But i didn't get any warnings
> for make dt_binding_check
>
>CHKDT Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> DTC Documentation/devicetree/bindings/arm/renesas.example.dt.yaml
> FATAL ERROR: Unknown output format "yaml"
>
> Will DTC report about the example node errors? But, DTC is failing with
> FATAL_ERROR.
> I tried it even after installing libyaml and headers in my local
> directory and export the path, but no luck.(ref:
> https://lkml.org/lkml/2018/12/3/951)
> Could you please let me know if i miss anything and help me to proceed
> further.
See Documentation/devicetree/writing-schema.md
Rob
Re: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Hi Rob,
On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota wrote:
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota
---
Changes on v2:
Address review comments
Update the compatible property definition
Add description for reset-cells
Add 'additionalProperties: false' property
.../bindings/reset/intel,syscon-reset.yaml | 53 ++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index ..3403a967190a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightening Mountain SoC System Reset Controller
+
+maintainers:
+ - Dilip Kota
+
+properties:
+ compatible:
+items:
+ - const: intel,rcu-lgm
+ - const: syscon
+
+ reg:
+description: Reset controller register base address and size
+
+ intel,global-reset:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description: Global reset register offset and bit offset.
+
+ "#reset-cells":
+const: 2
+description: |
+ The 1st cell is the register offset.
+ The 2nd cell is the bit offset in the register.
+
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+rcu0: reset-controller@ {
+compatible = "intel,rcu-lgm", "syscon";
+reg = <0x00 0x8>;
+intel,global-reset = <0x10 30>;
+#reset-cells = <2>;
+};
+
+pcie_phy0: pciephy@... {
+...
You need to run 'make dt_binding_check' and fix the warnings. The
example has to be buildable and it is not.
Sure, i will correct this pcie_phy0 node. But i didn't get any warnings
for make dt_binding_check
CHKDT Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
DTC Documentation/devicetree/bindings/arm/renesas.example.dt.yaml
FATAL ERROR: Unknown output format "yaml"
Will DTC report about the example node errors? But, DTC is failing with
FATAL_ERROR.
I tried it even after installing libyaml and headers in my local
directory and export the path, but no luck.(ref:
https://lkml.org/lkml/2018/12/3/951)
Could you please let me know if i miss anything and help me to proceed
further.
Regards,
Dilip
+/* address offset: 0x10, bit offset: 12 */
+resets = < 0x10 12>;
+...
+};
--
2.11.0
Re: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota wrote:
>
> Add YAML schemas for the reset controller on Intel
> Lightening Mountain (LGM) SoC.
>
> Signed-off-by: Dilip Kota
> ---
> Changes on v2:
> Address review comments
> Update the compatible property definition
> Add description for reset-cells
> Add 'additionalProperties: false' property
>
> .../bindings/reset/intel,syscon-reset.yaml | 53
> ++
> 1 file changed, 53 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> new file mode 100644
> index ..3403a967190a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Lightening Mountain SoC System Reset Controller
> +
> +maintainers:
> + - Dilip Kota
> +
> +properties:
> + compatible:
> +items:
> + - const: intel,rcu-lgm
> + - const: syscon
> +
> + reg:
> +description: Reset controller register base address and size
> +
> + intel,global-reset:
> +$ref: /schemas/types.yaml#/definitions/uint32-array
> +description: Global reset register offset and bit offset.
> +
> + "#reset-cells":
> +const: 2
> +description: |
> + The 1st cell is the register offset.
> + The 2nd cell is the bit offset in the register.
> +
> +required:
> + - compatible
> + - reg
> + - intel,global-reset
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +rcu0: reset-controller@ {
> +compatible = "intel,rcu-lgm", "syscon";
> +reg = <0x00 0x8>;
> +intel,global-reset = <0x10 30>;
> +#reset-cells = <2>;
> +};
> +
> +pcie_phy0: pciephy@... {
> +...
You need to run 'make dt_binding_check' and fix the warnings. The
example has to be buildable and it is not.
> +/* address offset: 0x10, bit offset: 12 */
> +resets = < 0x10 12>;
> +...
> +};
> --
> 2.11.0
>
