Re: USB Ethernet gadget on Nokia n900
Hi, On Tue, Oct 21, 2014 at 12:35:18AM +0300, Aaro Koskinen wrote: > On Sun, Oct 19, 2014 at 09:19:37PM +0200, Pavel Machek wrote: > > I am trying to use nfsroot, so I can't use modules. > > Why not? > > > (I am attaching full config, in case I missed something important). > > I'm using the below config with 3.17 and g_ether works OK. Also, I'm using DT boot. A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: N900 modem support in 3.18-rc1
Hi, On Thu, Nov 13, 2014 at 09:45:36AM -0800, Tony Lindgren wrote: > * Pavel Machek [141113 08:23]: > > OTOH ofono seems pretty reasonable. So I played a bit, and result > > is python/pygtk gui which can receive an sms, initiate a call, and > > report missed call. If someone wants to play, source is at > > > > https://gitorious.org/tui/tui/source/b6141107e9341a1412720aed4b0d09143dfa2f4e:ofone > > Pavel, care to fill in the the following type patch with some > instructions in the description now that you got it working? Could we even have some "permanent" instructions under Documentation/? > I did not have luck yet when I tried. I got the /dev/cmt/* > entries after adding pm=1 param, but no luck scanning any networks. I haven't tested anything yet, but looking forward to do that during the weekend... Sounds pretty exciting. :-) A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v12 11/15] arm: omap1: Migrate debug_ll macros to use 8250.S
Hi, On Fri, Oct 24, 2014 at 11:54:32AM +0100, Daniel Thompson wrote: > + config DEBUG_OMAP1UART1 > + bool "Kernel low-level debugging via OMAP1 UART1" > + depends on ARCH_OMAP1 > + select DEBUG_UART_8250 > + help > + Say Y here if you want kernel low-level debugging support > + on OMAP1 based platforms (expect OMAP730) on the UART1. [...] > + on OMAP1 based platforms (expect OMAP730) on the UART2. [...] > + on OMAP1 based platforms (expect OMAP730) on the UART3. ^^ Spelling again wrong. I think it was already corrected in v11? A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] parisc architecture patch for v3.18
Hi, On Mon, Oct 13, 2014 at 10:24:53PM +0200, Helge Deller wrote: > On 10/13/2014 03:41 PM, One Thousand Gnomes wrote: > >I somehow doubt your kill command magically corrects its signal numbering > >table. Likewise what does gdb do given a core dump that died from one of > >those signals, and what does your shell report if you kill one that way. > >It seems to me your minimal set of binaries to swap to get it right is > >non-zero but not problematic (libc, kill, shells, top, gdb) ? > > My patch of course just marks the start of a transition phase, in which > some few applications need to be rebuilt (libc as the most important one). Busybox handles changed signals correctly after rebuilding against new headers. Based on quick look, GDB has never known about PA-RISC specific numbers, so it has probably always reported some wrong signal name... A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] staging: nokia_h4: remove deprecated IRQF_DISABLED
Hi, On Wed, Oct 01, 2014 at 10:33:48PM +0200, Michael Opdenacker wrote: > Remove the use of the IRQF_DISABLED flag > from drivers/staging/nokia_h4p/nokia_core.c > > It's a NOOP since 2.6.35 and it will be removed soon. This driver has been deleted from the staging tree already. A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RESEND] MIPS/loongson2_cpufreq: Fix CPU clock rate setting mismerge
During 3.16 merge window, parts of the commit 8e8acb32960f
(MIPS/loongson2_cpufreq: Fix CPU clock rate setting) seem to have
been deleted probably due to a mismerge, and as a result cpufreq
is broken again on Loongson2 boards in 3.16 and newer kernels.
Fix by repeating the fix.
Signed-off-by: Aaro Koskinen
Cc: sta...@vger.kernel.org # 3.16
---
arch/mips/loongson/lemote-2f/clock.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/mips/loongson/lemote-2f/clock.c
b/arch/mips/loongson/lemote-2f/clock.c
index a217061..462e34d 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned int rate_khz = rate / 1000;
struct cpufreq_frequency_table *pos;
int ret = 0;
int regval;
@@ -107,9 +108,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
propagate_rate(clk);
cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
- if (rate == pos->frequency)
+ if (rate_khz == pos->frequency)
break;
- if (rate != pos->frequency)
+ if (rate_khz != pos->frequency)
return -ENOTSUPP;
clk->rate = rate;
--
2.1.0
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[PATCH] octeon_edac: fix broken build
Commit debe6a623d3c ("MIPS: OCTEON: Update octeon-model.h code for new
SoCs.") renamed some SoC model helper functions, but forgot to update
the EDAC drivers resulting in build failures. Fix that.
Cc: sta...@vger.kernel.org # v4.0+
Signed-off-by: Aaro Koskinen
---
drivers/edac/octeon_edac-l2c.c | 2 +-
drivers/edac/octeon_edac-lmc.c | 2 +-
drivers/edac/octeon_edac-pc.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/octeon_edac-l2c.c b/drivers/edac/octeon_edac-l2c.c
index 7e98084..afea7fc 100644
--- a/drivers/edac/octeon_edac-l2c.c
+++ b/drivers/edac/octeon_edac-l2c.c
@@ -151,7 +151,7 @@ static int octeon_l2c_probe(struct platform_device *pdev)
l2c->ctl_name = "octeon_l2c_err";
- if (OCTEON_IS_MODEL(OCTEON_FAM_1_PLUS)) {
+ if (OCTEON_IS_OCTEON1PLUS()) {
union cvmx_l2t_err l2t_err;
union cvmx_l2d_err l2d_err;
diff --git a/drivers/edac/octeon_edac-lmc.c b/drivers/edac/octeon_edac-lmc.c
index bb19e07..cda6dab 100644
--- a/drivers/edac/octeon_edac-lmc.c
+++ b/drivers/edac/octeon_edac-lmc.c
@@ -234,7 +234,7 @@ static int octeon_lmc_edac_probe(struct platform_device
*pdev)
layers[0].size = 1;
layers[0].is_virt_csrow = false;
- if (OCTEON_IS_MODEL(OCTEON_FAM_1_PLUS)) {
+ if (OCTEON_IS_OCTEON1PLUS()) {
union cvmx_lmcx_mem_cfg0 cfg0;
cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
diff --git a/drivers/edac/octeon_edac-pc.c b/drivers/edac/octeon_edac-pc.c
index 0f83c33..2ab6cf2 100644
--- a/drivers/edac/octeon_edac-pc.c
+++ b/drivers/edac/octeon_edac-pc.c
@@ -73,7 +73,7 @@ static int co_cache_error_event(struct notifier_block *this,
edac_device_handle_ce(p->ed, cpu, 0, "dcache");
/* Clear the error indication */
- if (OCTEON_IS_MODEL(OCTEON_FAM_2))
+ if (OCTEON_IS_OCTEON2())
write_octeon_c0_dcacheerr(1);
else
write_octeon_c0_dcacheerr(0);
--
2.4.2
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[PATCH RESEND] octeon_edac: fix broken build
Commit debe6a623d3c ("MIPS: OCTEON: Update octeon-model.h code for new
SoCs.") renamed some SoC model helper functions, but forgot to update
the EDAC drivers resulting in build failures. Fix that.
Cc: sta...@vger.kernel.org # v4.0+
Signed-off-by: Aaro Koskinen
---
drivers/edac/octeon_edac-l2c.c | 2 +-
drivers/edac/octeon_edac-lmc.c | 2 +-
drivers/edac/octeon_edac-pc.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/octeon_edac-l2c.c b/drivers/edac/octeon_edac-l2c.c
index 7e98084..afea7fc 100644
--- a/drivers/edac/octeon_edac-l2c.c
+++ b/drivers/edac/octeon_edac-l2c.c
@@ -151,7 +151,7 @@ static int octeon_l2c_probe(struct platform_device *pdev)
l2c->ctl_name = "octeon_l2c_err";
- if (OCTEON_IS_MODEL(OCTEON_FAM_1_PLUS)) {
+ if (OCTEON_IS_OCTEON1PLUS()) {
union cvmx_l2t_err l2t_err;
union cvmx_l2d_err l2d_err;
diff --git a/drivers/edac/octeon_edac-lmc.c b/drivers/edac/octeon_edac-lmc.c
index bb19e07..cda6dab 100644
--- a/drivers/edac/octeon_edac-lmc.c
+++ b/drivers/edac/octeon_edac-lmc.c
@@ -234,7 +234,7 @@ static int octeon_lmc_edac_probe(struct platform_device
*pdev)
layers[0].size = 1;
layers[0].is_virt_csrow = false;
- if (OCTEON_IS_MODEL(OCTEON_FAM_1_PLUS)) {
+ if (OCTEON_IS_OCTEON1PLUS()) {
union cvmx_lmcx_mem_cfg0 cfg0;
cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
diff --git a/drivers/edac/octeon_edac-pc.c b/drivers/edac/octeon_edac-pc.c
index 0f83c33..2ab6cf2 100644
--- a/drivers/edac/octeon_edac-pc.c
+++ b/drivers/edac/octeon_edac-pc.c
@@ -73,7 +73,7 @@ static int co_cache_error_event(struct notifier_block *this,
edac_device_handle_ce(p->ed, cpu, 0, "dcache");
/* Clear the error indication */
- if (OCTEON_IS_MODEL(OCTEON_FAM_2))
+ if (OCTEON_IS_OCTEON2())
write_octeon_c0_dcacheerr(1);
else
write_octeon_c0_dcacheerr(0);
--
2.4.3
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[PATCH 2/2] perf: allow to specify custom linker command
Allow to specify custom linker command. This fixes MIPS64 builds for 64-bit userspace as it will allow to pass a linker using the correct linker flags for 64-bit ABI (by default GNU binutils ld will assume N32). Signed-off-by: Aaro Koskinen --- tools/perf/Makefile.perf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 14e823f..a3fbe65 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -108,7 +108,7 @@ $(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD $(Q)touch $(OUTPUT)PERF-VERSION-FILE CC = $(CROSS_COMPILE)gcc -LD = $(CROSS_COMPILE)ld +LD ?= $(CROSS_COMPILE)ld AR = $(CROSS_COMPILE)ar PKG_CONFIG = $(CROSS_COMPILE)pkg-config -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/2] perf: create config.detected into OUTPUT directory
Create config.detected into OUTPUT directory instead of source directory. This fixes parallel builds that share the same source directory. Signed-off-by: Aaro Koskinen --- tools/build/Makefile.build | 2 +- tools/perf/Makefile.perf | 2 +- tools/perf/config/Makefile | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/build/Makefile.build b/tools/build/Makefile.build index 69c35cf..7ebd35a 100644 --- a/tools/build/Makefile.build +++ b/tools/build/Makefile.build @@ -25,7 +25,7 @@ build-dir := $(srctree)/tools/build include $(build-dir)/Build.include # do not force detected configuration --include .config-detected +-include $(OUTPUT).config-detected # Init all relevant variables used in build files so # 1) they have correct type diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index c43a205..14e823f 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -528,7 +528,7 @@ config-clean: clean: $(LIBTRACEEVENT)-clean $(LIBAPI)-clean config-clean $(call QUIET_CLEAN, core-objs) $(RM) $(LIB_FILE) $(OUTPUT)perf-archive $(OUTPUT)perf-with-kcore $(LANG_BINDINGS) $(Q)find . -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete - $(Q)$(RM) .config-detected + $(Q)$(RM) $(OUTPUT).config-detected $(call QUIET_CLEAN, core-progs) $(RM) $(ALL_PROGRAMS) perf perf-read-vdso32 perf-read-vdsox32 $(call QUIET_CLEAN, core-gen) $(RM) *.spec *.pyc *.pyo */*.pyc */*.pyo $(OUTPUT)common-cmds.h TAGS tags cscope* $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)FEATURE-DUMP $(OUTPUT)util/*-bison* $(OUTPUT)util/*-flex* $(QUIET_SUBDIR0)Documentation $(QUIET_SUBDIR1) clean diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile index 59a98c6..3440fc1 100644 --- a/tools/perf/config/Makefile +++ b/tools/perf/config/Makefile @@ -11,9 +11,9 @@ ifneq ($(obj-perf),) obj-perf := $(abspath $(obj-perf))/ endif -$(shell echo -n > .config-detected) -detected = $(shell echo "$(1)=y" >> .config-detected) -detected_var = $(shell echo "$(1)=$($(1))" >> .config-detected) +$(shell echo -n > $(OUTPUT).config-detected) +detected = $(shell echo "$(1)=y" >> $(OUTPUT).config-detected) +detected_var = $(shell echo "$(1)=$($(1))" >> $(OUTPUT).config-detected) CFLAGS := $(EXTRA_CFLAGS) $(EXTRA_WARNINGS) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: mips build failures due to commit 8dd928915a73 (mips: fix up obsolete cpu function usage)
On Tue, Apr 21, 2015 at 08:41:08AM -0700, Guenter Roeck wrote: > The following might do it. Note that I can not really test it since I > don't have a real mips system, and qemu gets rcu hangs if I enable more > than one CPU (I see that with older kernels as well, so it is not a new > problem). Someone will have to test the patch on a real multi-core system. That works on Octeon+ EBH5600 board (8 cores) with 4.1-rc1. Tested-by: Aaro Koskinen Thanks, A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: Build regressions/improvements in v4.1-rc1
Hi, On Mon, Apr 27, 2015 at 12:03:32PM +0200, Geert Uytterhoeven wrote: > > *** ERRORS *** > > > > 34 regressions: > > The quiet days are over... > > > + /home/kisskb/slave/src/arch/mips/cavium-octeon/smp.c: error: passing > > argument 2 of 'cpumask_clear_cpu' discards 'volatile' qualifier from > > pointer target type [-Werror]: => 242:2 > > + /home/kisskb/slave/src/arch/mips/kernel/process.c: error: passing > > argument 2 of 'cpumask_test_cpu' discards 'volatile' qualifier from pointer > > target type [-Werror]: => 52:2 > > + /home/kisskb/slave/src/arch/mips/kernel/smp.c: error: passing argument > > 2 of 'cpumask_set_cpu' discards 'volatile' qualifier from pointer target > > type [-Werror]: => 149:2, 211:2 For these there is a fix proposal: http://patchwork.linux-mips.org/patch/9828/ A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 01/11] MIPS: OCTEON: cvmx-helper: use function to access interface_port_count
Use function to access interface_port_count. This allows moving
functions requiring the info to different files.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/cvmx-helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c
b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index 7e5cf7a..301a9ce 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -557,7 +557,7 @@ int cvmx_helper_interface_probe(int interface)
static int __cvmx_helper_interface_setup_ipd(int interface)
{
int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
- int num_ports = interface_port_count[interface];
+ int num_ports = cvmx_helper_ports_on_interface(interface);
while (num_ports--) {
__cvmx_helper_port_setup_ipd(ipd_port);
@@ -620,7 +620,7 @@ static int __cvmx_helper_interface_setup_pko(int interface)
* priorities are set.
*/
int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
- int num_ports = interface_port_count[interface];
+ int num_ports = cvmx_helper_ports_on_interface(interface);
while (num_ports--) {
/*
* Give the user a chance to override the per queue
--
2.3.3
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[RFC PATCH 07/11] MIPS: OCTEON: make all interface enumeration helpers static
Make all interface enumeration helpers static.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/cvmx-helper.c | 10 +-
arch/mips/include/asm/octeon/cvmx-helper-npi.h | 11 ---
arch/mips/include/asm/octeon/cvmx-helper-rgmii.h | 9 -
arch/mips/include/asm/octeon/cvmx-helper-sgmii.h | 1 -
arch/mips/include/asm/octeon/cvmx-helper-spi.h | 1 -
arch/mips/include/asm/octeon/cvmx-helper-xaui.h | 1 -
6 files changed, 5 insertions(+), 28 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c
b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index c0c541b..414ca1a 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -316,7 +316,7 @@ static int __cvmx_helper_loop_enumerate(int interface)
*
* Returns Number of ports on the interface. Zero to disable.
*/
-int __cvmx_helper_npi_enumerate(int interface)
+static int __cvmx_helper_npi_enumerate(int interface)
{
#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
@@ -352,7 +352,7 @@ int __cvmx_helper_npi_enumerate(int interface)
*
* Returns Number of RGMII/GMII/MII ports (0-4).
*/
-int __cvmx_helper_rgmii_enumerate(int interface)
+static int __cvmx_helper_rgmii_enumerate(int interface)
{
int num_ports = 0;
union cvmx_gmxx_inf_mode mode;
@@ -391,12 +391,12 @@ int __cvmx_helper_rgmii_enumerate(int interface)
return num_ports;
}
-int __cvmx_helper_sgmii_enumerate(int interface)
+static int __cvmx_helper_sgmii_enumerate(int interface)
{
return 4;
}
-int __cvmx_helper_spi_enumerate(int interface)
+static int __cvmx_helper_spi_enumerate(int interface)
{
if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
cvmx_spi4000_is_present(interface)) {
@@ -406,7 +406,7 @@ int __cvmx_helper_spi_enumerate(int interface)
}
}
-int __cvmx_helper_xaui_enumerate(int interface)
+static int __cvmx_helper_xaui_enumerate(int interface)
{
union cvmx_gmxx_hg2_control gmx_hg2_control;
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h
b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
index bab9931..84a94ee 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-npi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -36,17 +36,6 @@
#define __CVMX_HELPER_NPI_H__
/**
- * Enumerate a NPI interface and determine the number of ports
- * connected to it. The NPI interface should still be down after
- * this call.
- *
- * @interface: Interface to enumerate
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-extern int __cvmx_helper_npi_enumerate(int interface);
-
-/**
* Bringup and enable a NPI interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
index df7717b..7dfe5f5 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -36,15 +36,6 @@
#define __CVMX_HELPER_RGMII_H__
/**
- * Enumerate RGMII ports and determine the number present
- *
- * @interface: Interface to enumerate
- *
- * Returns Number of RGMII/GMII/MII ports (0-4).
- */
-extern int __cvmx_helper_rgmii_enumerate(int interface);
-
-/**
* Put an RGMII interface in loopback mode. Internal packets sent
* out will be received back again on the same port. Externally
* received packets will echo back out.
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
index eb51835..f4c9eb1 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -45,7 +45,6 @@
* Returns Number of ports on the interface. Zero to disable.
*/
extern void __cvmx_helper_sgmii_probe(int interface);
-extern int __cvmx_helper_sgmii_enumerate(int interface);
/**
* Bringup and enable a SGMII interface. After this call packet
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h
b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
index 9f1c6b9..69bac03 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-spi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
@@ -42,7 +42,6 @@
* Returns Number of ports on the interface. Zero to disable.
*/
extern int __cvmx_helper_spi_probe(int interface);
-extern int __cvmx_helper_spi_enumerate(int interface);
/**
* Bringup and enable a SPI interface. After this call packet I/O
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
index 9fbcea3..c392808 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -45,7 +45,6 @@
* Returns Number of ports on the interface. Z
[RFC PATCH 11/11] MIPS: OCTEON: move all ethernet-specific headers to staging
Move all ethernet-specific headers to staging.
Signed-off-by: Aaro Koskinen
---
arch/mips/include/asm/octeon/cvmx-helper-board.h | 70 ---
arch/mips/include/asm/octeon/cvmx-helper.h | 124
.../asm => drivers/staging}/octeon/cvmx-address.h | 0
.../staging}/octeon/cvmx-asxx-defs.h | 0
drivers/staging/octeon/cvmx-cmd-queue.c| 11 +-
.../staging}/octeon/cvmx-cmd-queue.h | 4 +-
.../asm => drivers/staging}/octeon/cvmx-dbg-defs.h | 0
.../asm => drivers/staging}/octeon/cvmx-fau.h | 0
.../asm => drivers/staging}/octeon/cvmx-fpa-defs.h | 0
.../asm => drivers/staging}/octeon/cvmx-fpa.h | 4 +-
drivers/staging/octeon/cvmx-helper-ethernet.c | 25 ++-
drivers/staging/octeon/cvmx-helper-ethernet.h | 219 +
drivers/staging/octeon/cvmx-helper-loop.c | 6 +-
.../staging}/octeon/cvmx-helper-loop.h | 0
drivers/staging/octeon/cvmx-helper-npi.c | 6 +-
.../staging}/octeon/cvmx-helper-npi.h | 0
drivers/staging/octeon/cvmx-helper-rgmii.c | 17 +-
.../staging}/octeon/cvmx-helper-rgmii.h| 2 +
drivers/staging/octeon/cvmx-helper-sgmii.c | 11 +-
.../staging}/octeon/cvmx-helper-sgmii.h| 2 +
drivers/staging/octeon/cvmx-helper-spi.c | 9 +-
.../staging}/octeon/cvmx-helper-spi.h | 2 +
drivers/staging/octeon/cvmx-helper-util.c | 18 +-
.../staging}/octeon/cvmx-helper-util.h | 3 +
drivers/staging/octeon/cvmx-helper-xaui.c | 11 +-
.../staging}/octeon/cvmx-helper-xaui.h | 2 +
drivers/staging/octeon/cvmx-interrupt-decodes.c| 11 +-
drivers/staging/octeon/cvmx-interrupt-rsl.c| 5 +-
.../asm => drivers/staging}/octeon/cvmx-ipd.h | 3 +-
drivers/staging/octeon/cvmx-link.c | 15 +-
.../asm => drivers/staging}/octeon/cvmx-mdio.h | 0
.../staging}/octeon/cvmx-pcsx-defs.h | 0
.../staging}/octeon/cvmx-pcsxx-defs.h | 0
.../asm => drivers/staging}/octeon/cvmx-pip-defs.h | 0
.../asm => drivers/staging}/octeon/cvmx-pip.h | 6 +-
.../asm => drivers/staging}/octeon/cvmx-pko-defs.h | 0
drivers/staging/octeon/cvmx-pko.c | 6 +-
.../asm => drivers/staging}/octeon/cvmx-pko.h | 8 +-
.../asm => drivers/staging}/octeon/cvmx-pow.h | 5 +-
.../asm => drivers/staging}/octeon/cvmx-scratch.h | 0
drivers/staging/octeon/cvmx-spi.c | 12 +-
.../staging}/octeon/cvmx-spxx-defs.h | 0
.../staging}/octeon/cvmx-srxx-defs.h | 0
.../staging}/octeon/cvmx-stxx-defs.h | 0
.../asm => drivers/staging}/octeon/cvmx-wqe.h | 0
drivers/staging/octeon/ethernet-mem.c | 6 +-
drivers/staging/octeon/ethernet-rgmii.c| 18 +-
drivers/staging/octeon/ethernet-rx.c | 24 ++-
drivers/staging/octeon/ethernet-rx.h | 4 +-
drivers/staging/octeon/ethernet-spi.c | 17 +-
drivers/staging/octeon/ethernet-tx.c | 19 +-
drivers/staging/octeon/ethernet-xaui.c | 14 +-
drivers/staging/octeon/ethernet.c | 40 ++--
drivers/staging/octeon/octeon-ethernet.h | 3 +-
54 files changed, 390 insertions(+), 372 deletions(-)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-address.h (100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-asxx-defs.h
(100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-cmd-queue.h (99%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-dbg-defs.h (100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-fau.h (100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-fpa-defs.h (100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-fpa.h (99%)
create mode 100644 drivers/staging/octeon/cvmx-helper-ethernet.h
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-loop.h
(100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-npi.h
(100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-rgmii.h
(98%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-sgmii.h
(98%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-spi.h
(98%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-util.h
(99%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-helper-xaui.h
(98%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-ipd.h (99%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-mdio.h (100%)
rename {arch/mips/include/asm => drivers/staging}/octeon/cvmx-pcsx-defs.h
(100%)
rename {arch/mips/include/asm => dri
[RFC PATCH 00/11] MIPS: OCTEON: move all octeon-ethernet code to staging
Hi, In order to octeon-ethernet staging work to proceed, we should have all the code in the same tree (staging). Currently, most of the driver code actually lives in the MIPS tree in the "cvmx" helper or OS abstraction routines and include files. Majority of this code needs refactoring (or deletion) for the octeon-ethernet to become a normal Linux driver. Since rest of the kernel does not need this code at all, it should make sense to move it all into the same place while the driver is being developed. This series does not make any functional changes, just moves the code. Tested on EdgeRouter Lite, EdgeRouter Pro and D-Link DSR-1000N. Also build tested with octeon-ethernet as built-in, module and completely disabled. Patches are based on staging-next. A. Aaro Koskinen (11): MIPS: OCTEON: cvmx-helper: use function to access interface_port_count MIPS: OCTEON: move ethernet-specific helpers into a separate file MIPS: OCTEON: make __cvmx_helper_sgmii/xaui_probe void MIPS: OCTEON: move interface enumeration helpers to cvmx-helper MIPS: OCTEON: delete calls to __cvmx_helper_npi/rgmii_probe MIPS: OCTEON: rename __cvmx_helper_npi/rgmii_probe MIPS: OCTEON: make all interface enumeration helpers static MIPS: OCTEON: move the link helpers into a separate file MIPS: OCTEON: move ethernet-specific helpers to staging MIPS: OCTEON: ethernet: delete unneeded symbol exports MIPS: OCTEON: move all ethernet-specific headers to staging arch/mips/cavium-octeon/executive/Makefile |7 +- .../cavium-octeon/executive/cvmx-helper-board.c| 512 +- arch/mips/cavium-octeon/executive/cvmx-helper.c| 1017 +++- arch/mips/include/asm/octeon/cvmx-helper-board.h | 70 -- arch/mips/include/asm/octeon/cvmx-helper.h | 124 --- drivers/staging/octeon/Makefile| 15 +- .../asm => drivers/staging}/octeon/cvmx-address.h |0 .../staging}/octeon/cvmx-asxx-defs.h |0 .../staging/octeon}/cvmx-cmd-queue.c | 12 +- .../staging}/octeon/cvmx-cmd-queue.h |4 +- .../asm => drivers/staging}/octeon/cvmx-dbg-defs.h |0 .../asm => drivers/staging}/octeon/cvmx-fau.h |0 .../asm => drivers/staging}/octeon/cvmx-fpa-defs.h |0 .../asm => drivers/staging}/octeon/cvmx-fpa.h |4 +- drivers/staging/octeon/cvmx-helper-ethernet.c | 914 ++ drivers/staging/octeon/cvmx-helper-ethernet.h | 219 + .../staging/octeon}/cvmx-helper-loop.c |6 +- .../staging}/octeon/cvmx-helper-loop.h |1 - .../staging/octeon}/cvmx-helper-npi.c | 44 +- .../staging}/octeon/cvmx-helper-npi.h | 12 - .../staging/octeon}/cvmx-helper-rgmii.c| 63 +- .../staging}/octeon/cvmx-helper-rgmii.h| 10 +- .../staging/octeon}/cvmx-helper-sgmii.c| 20 +- .../staging}/octeon/cvmx-helper-sgmii.h|5 +- .../staging/octeon}/cvmx-helper-spi.c | 19 +- .../staging}/octeon/cvmx-helper-spi.h |3 +- .../staging/octeon}/cvmx-helper-util.c | 22 +- .../staging}/octeon/cvmx-helper-util.h |3 + .../staging/octeon}/cvmx-helper-xaui.c | 28 +- .../staging}/octeon/cvmx-helper-xaui.h |5 +- .../staging/octeon}/cvmx-interrupt-decodes.c | 11 +- .../staging/octeon}/cvmx-interrupt-rsl.c |5 +- .../asm => drivers/staging}/octeon/cvmx-ipd.h |3 +- drivers/staging/octeon/cvmx-link.c | 531 ++ .../asm => drivers/staging}/octeon/cvmx-mdio.h |0 .../staging}/octeon/cvmx-pcsx-defs.h |0 .../staging}/octeon/cvmx-pcsxx-defs.h |0 .../asm => drivers/staging}/octeon/cvmx-pip-defs.h |0 .../asm => drivers/staging}/octeon/cvmx-pip.h |6 +- .../asm => drivers/staging}/octeon/cvmx-pko-defs.h |0 .../staging/octeon}/cvmx-pko.c |8 +- .../asm => drivers/staging}/octeon/cvmx-pko.h |8 +- .../asm => drivers/staging}/octeon/cvmx-pow.h |5 +- .../asm => drivers/staging}/octeon/cvmx-scratch.h |0 .../staging/octeon}/cvmx-spi.c | 13 +- .../staging}/octeon/cvmx-spxx-defs.h |0 .../staging}/octeon/cvmx-srxx-defs.h |0 .../staging}/octeon/cvmx-stxx-defs.h |0 .../asm => drivers/staging}/octeon/cvmx-wqe.h |0 drivers/staging/octeon/ethernet-mem.c |6 +- drivers/staging/octeon/ethernet-rgmii.c| 18 +- drivers/staging/octeon/ethernet-rx.c | 24 +- drivers/staging/octeon/ethernet-rx.h |4 +- drivers/staging/octeon/ethernet-spi.c | 17 +- drivers/staging/octeon/ethernet-tx.c | 19 +- drivers/staging/octeon/ethernet-xaui.c
[RFC PATCH 08/11] MIPS: OCTEON: move the link helpers into a separate file
Move the link helpers into a separate file.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/Makefile | 2 +-
.../cavium-octeon/executive/cvmx-helper-board.c| 511
arch/mips/cavium-octeon/executive/cvmx-link.c | 534 +
3 files changed, 535 insertions(+), 512 deletions(-)
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-link.c
diff --git a/arch/mips/cavium-octeon/executive/Makefile
b/arch/mips/cavium-octeon/executive/Makefile
index e755a73..abafe06 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -14,7 +14,7 @@ obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
- cvmx-helper-ethernet.o \
+ cvmx-helper-ethernet.o cvmx-link.o \
cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 9eb0fee..10f8de1 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -36,26 +36,9 @@
#include
-#include
-
#include
-#include
#include
-#include
-#include
-
-/**
- * cvmx_override_board_link_get(int ipd_port) is a function
- * pointer. It is meant to allow customization of the process of
- * talking to a PHY to determine link speed. It is called every
- * time a PHY must be polled for link status. Users should set
- * this pointer to a function before calling any cvmx-helper
- * operations.
- */
-cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) =
-NULL;
-
/**
* Return the MII PHY address associated with the given IPD
* port. A result of -1 means there isn't a MII capable PHY
@@ -205,419 +188,6 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
}
/**
- * This function is the board specific method of determining an
- * ethernet ports link speed. Most Octeon boards have Marvell PHYs
- * and are handled by the fall through case. This function must be
- * updated for boards that don't have the normal Marvell PHYs.
- *
- * This function must be modified for every new Octeon board.
- * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relies on the
- * fact that every Octeon board receives a unique board type
- * enumeration from the bootloader.
- *
- * @ipd_port: IPD input port associated with the port we want to get link
- *status for.
- *
- * Returns The ports link status. If the link isn't fully resolved, this must
- *return zero.
- */
-cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
-{
- cvmx_helper_link_info_t result;
- int phy_addr;
- int is_broadcom_phy = 0;
-
- /* Give the user a chance to override the processing of this function */
- if (cvmx_override_board_link_get)
- return cvmx_override_board_link_get(ipd_port);
-
- /* Unless we fix it later, all links are defaulted to down */
- result.u64 = 0;
-
- /*
-* This switch statement should handle all ports that either don't use
-* Marvell PHYS, or don't support in-band status.
-*/
- switch (cvmx_sysinfo_get()->board_type) {
- case CVMX_BOARD_TYPE_SIM:
- /* The simulator gives you a simulated 1Gbps full duplex link */
- result.s.link_up = 1;
- result.s.full_duplex = 1;
- result.s.speed = 1000;
- return result;
- case CVMX_BOARD_TYPE_EBH3100:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
- case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
- case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
- /* Port 1 on these boards is always Gigabit */
- if (ipd_port == 1) {
- result.s.link_up = 1;
- result.s.full_duplex = 1;
- result.s.speed = 1000;
- return result;
- }
- /* Fall through to the generic code below */
- break;
- case CVMX_BOARD_TYPE_CUST_NB5:
- /* Port 1 on these boards is always Gigabit */
- if (ipd_port == 1) {
- result.s.link_up = 1;
- result.s.full_duplex = 1;
- result.s.speed = 1000;
- return result;
- } else /* The other port uses a broadcom PHY */
- is_broadcom_phy = 1;
- break;
- case CVMX_BOARD_TYPE_BBGW_REF:
- /* Port 1 on these boards is always Gigabit */
- if (ipd_port =
[RFC PATCH 04/11] MIPS: OCTEON: move interface enumeration helpers to cvmx-helper
Move interface enumeration helpers to cvmx-helper.
Signed-off-by: Aaro Koskinen
---
.../mips/cavium-octeon/executive/cvmx-helper-npi.c | 38 ---
.../cavium-octeon/executive/cvmx-helper-rgmii.c| 46
.../cavium-octeon/executive/cvmx-helper-sgmii.c| 4 -
.../mips/cavium-octeon/executive/cvmx-helper-spi.c | 10 --
.../cavium-octeon/executive/cvmx-helper-xaui.c | 12 ---
arch/mips/cavium-octeon/executive/cvmx-helper.c| 117 +
arch/mips/include/asm/octeon/cvmx-helper-loop.h| 1 -
7 files changed, 117 insertions(+), 111 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
index cc94cfa..9f7bcc4 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
@@ -38,44 +38,6 @@
#include
/**
- * Probe a NPI interface and determine the number of ports
- * connected to it. The NPI interface should still be down
- * after this call.
- *
- * @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-int __cvmx_helper_npi_probe(int interface)
-{
-#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
- if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
- return 4;
- else if (OCTEON_IS_MODEL(OCTEON_CN56XX)
-&& !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
- /* The packet engines didn't exist before pass 2 */
- return 4;
- else if (OCTEON_IS_MODEL(OCTEON_CN52XX)
-&& !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
- /* The packet engines didn't exist before pass 2 */
- return 4;
-#if 0
- /*
-* Technically CN30XX, CN31XX, and CN50XX contain packet
-* engines, but nobody ever uses them. Since this is the case,
-* we disable them here.
-*/
- else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
-|| OCTEON_IS_MODEL(OCTEON_CN50XX))
- return 2;
- else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
- return 1;
-#endif
-#endif
- return 0;
-}
-
-/**
* Bringup and enable a NPI interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
index f59c88e..730812c 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -48,52 +48,6 @@ void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_asxx_enable(int block);
/**
- * Probe RGMII ports and determine the number present
- *
- * @interface: Interface to probe
- *
- * Returns Number of RGMII/GMII/MII ports (0-4).
- */
-int __cvmx_helper_rgmii_probe(int interface)
-{
- int num_ports = 0;
- union cvmx_gmxx_inf_mode mode;
- mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
-
- if (mode.s.type) {
- if (OCTEON_IS_MODEL(OCTEON_CN38XX)
- || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
- cvmx_dprintf("ERROR: RGMII initialize called in "
-"SPI interface\n");
- } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN30XX)
- || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
- /*
-* On these chips "type" says we're in
-* GMII/MII mode. This limits us to 2 ports
-*/
- num_ports = 2;
- } else {
- cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
-__func__);
- }
- } else {
- if (OCTEON_IS_MODEL(OCTEON_CN38XX)
- || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
- num_ports = 4;
- } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN30XX)
- || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
- num_ports = 3;
- } else {
- cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
-__func__);
- }
- }
- return num_ports;
-}
-
-/**
* Put an RGMII interface in loopback mode. Internal packets sent
* out will be received back again on the same port. Externally
* received packets will echo back out.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 6a47b04..03ae748 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
+++ b/arch/mips/ca
[RFC PATCH 09/11] MIPS: OCTEON: move ethernet-specific helpers to staging
Move all ethernet-specific helpers to staging.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/Makefile| 8 +---
arch/mips/cavium-octeon/executive/cvmx-helper-board.c | 1 +
arch/mips/cavium-octeon/executive/cvmx-helper.c | 1 +
drivers/staging/octeon/Makefile | 15 ++-
.../executive => drivers/staging/octeon}/cvmx-cmd-queue.c | 0
.../staging/octeon}/cvmx-helper-ethernet.c| 0
.../staging/octeon}/cvmx-helper-loop.c| 0
.../staging/octeon}/cvmx-helper-npi.c | 0
.../staging/octeon}/cvmx-helper-rgmii.c | 0
.../staging/octeon}/cvmx-helper-sgmii.c | 0
.../staging/octeon}/cvmx-helper-spi.c | 0
.../staging/octeon}/cvmx-helper-util.c| 0
.../staging/octeon}/cvmx-helper-xaui.c| 0
.../staging/octeon}/cvmx-interrupt-decodes.c | 0
.../staging/octeon}/cvmx-interrupt-rsl.c | 0
.../executive => drivers/staging/octeon}/cvmx-link.c | 0
.../executive => drivers/staging/octeon}/cvmx-pko.c | 0
.../executive => drivers/staging/octeon}/cvmx-spi.c | 0
18 files changed, 17 insertions(+), 8 deletions(-)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-cmd-queue.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-ethernet.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-loop.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-npi.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-rgmii.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-sgmii.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-spi.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-util.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-helper-xaui.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-interrupt-decodes.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-interrupt-rsl.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-link.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-pko.c (100%)
rename {arch/mips/cavium-octeon/executive =>
drivers/staging/octeon}/cvmx-spi.c (100%)
diff --git a/arch/mips/cavium-octeon/executive/Makefile
b/arch/mips/cavium-octeon/executive/Makefile
index abafe06..6e59ee4 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -10,11 +10,5 @@
#
obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
-obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
- cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
- cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
- cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
- cvmx-helper-ethernet.o cvmx-link.o \
- cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
-
+obj-y += cvmx-helper-board.o cvmx-helper.o
obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 10f8de1..32d3284 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -186,6 +186,7 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
cvmx_sysinfo_get()->board_type);
return -1;
}
+EXPORT_SYMBOL_GPL(cvmx_helper_board_get_mii_address);
/**
* This function is called by cvmx_helper_interface_probe() after it
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c
b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index 414ca1a..995fa42 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -506,3 +506,4 @@ int cvmx_helper_interface_enumerate(int interface)
return 0;
}
+EXPORT_SYMBOL_GPL(cvmx_helper_interface_enumerate);
diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile
index 9012dee..9a72fea 100644
--- a/drivers/staging/octeon/Makefile
+++ b/drivers/staging/octeon/Makefile
@@ -20,4 +20,17 @@ octeon-ethernet-y += ethernet-sgmii.o
octeon-ethernet-y += ethernet-spi.o
octeon-ethernet-y += ethernet-tx.o
octeon-ethernet-y += ethernet-xaui.o
-
+octeon-ethernet-y += cvmx-cmd-queue.o
+octeon-ethernet-y += cvmx-helper-ethernet.o
+octeon-ethernet-y += cvmx-helper-loop.o
+octeon-ethernet-y += cvmx-helper-npi.o
+octeon-ethernet-y += cvmx-helper-rgmii.o
+octeon-eth
[RFC PATCH 03/11] MIPS: OCTEON: make __cvmx_helper_sgmii/xaui_probe void
Make __cvmx_helper_sgmii/xaui_probe void, nobody is using return values
and this makes functions independent of enumeration functions.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c | 5 +
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c | 5 +
arch/mips/include/asm/octeon/cvmx-helper-sgmii.h | 2 +-
arch/mips/include/asm/octeon/cvmx-helper-xaui.h | 2 +-
4 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 6f9609e..6a47b04 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -340,10 +340,8 @@ int __cvmx_helper_sgmii_enumerate(int interface)
* this call.
*
* @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
*/
-int __cvmx_helper_sgmii_probe(int interface)
+void __cvmx_helper_sgmii_probe(int interface)
{
union cvmx_gmxx_inf_mode mode;
@@ -355,7 +353,6 @@ int __cvmx_helper_sgmii_probe(int interface)
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
mode.s.en = 1;
cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
- return __cvmx_helper_sgmii_enumerate(interface);
}
/**
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index 7653b7e..49d7507 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -63,10 +63,8 @@ int __cvmx_helper_xaui_enumerate(int interface)
* after this call.
*
* @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
*/
-int __cvmx_helper_xaui_probe(int interface)
+void __cvmx_helper_xaui_probe(int interface)
{
int i;
union cvmx_gmxx_inf_mode mode;
@@ -102,7 +100,6 @@ int __cvmx_helper_xaui_probe(int interface)
pko_mem_port_ptrs.s.pid = interface * 16 + i;
cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
}
- return __cvmx_helper_xaui_enumerate(interface);
}
/**
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
index 4debb1c..eb51835 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -44,7 +44,7 @@
*
* Returns Number of ports on the interface. Zero to disable.
*/
-extern int __cvmx_helper_sgmii_probe(int interface);
+extern void __cvmx_helper_sgmii_probe(int interface);
extern int __cvmx_helper_sgmii_enumerate(int interface);
/**
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
index 5e89ed7..9fbcea3 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -44,7 +44,7 @@
*
* Returns Number of ports on the interface. Zero to disable.
*/
-extern int __cvmx_helper_xaui_probe(int interface);
+extern void __cvmx_helper_xaui_probe(int interface);
extern int __cvmx_helper_xaui_enumerate(int interface);
/**
--
2.3.3
--
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[RFC PATCH 05/11] MIPS: OCTEON: delete calls to __cvmx_helper_npi/rgmii_probe
These calls have no side effects so drop the calls, so that we don't need to export these functions to modules. Signed-off-by: Aaro Koskinen --- arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c b/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c index 6fe990e..390f8f80 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c @@ -130,7 +130,6 @@ int cvmx_helper_interface_probe(int interface) */ case CVMX_HELPER_INTERFACE_MODE_RGMII: case CVMX_HELPER_INTERFACE_MODE_GMII: - __cvmx_helper_rgmii_probe(interface); break; /* * SPI4 can have 1-16 ports depending on the device at @@ -149,7 +148,6 @@ int cvmx_helper_interface_probe(int interface) break; /* PCI target Network Packet Interface */ case CVMX_HELPER_INTERFACE_MODE_NPI: - __cvmx_helper_npi_probe(interface); break; /* * Special loopback only ports. These are not the same -- 2.3.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 10/11] MIPS: OCTEON: ethernet: delete unneeded symbol exports
Delete unneeded symbol exports. Signed-off-by: Aaro Koskinen --- drivers/staging/octeon/cvmx-cmd-queue.c | 1 - drivers/staging/octeon/cvmx-helper-ethernet.c | 5 - drivers/staging/octeon/cvmx-helper-util.c | 4 drivers/staging/octeon/cvmx-pko.c | 2 -- drivers/staging/octeon/cvmx-spi.c | 1 - 5 files changed, 13 deletions(-) diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/drivers/staging/octeon/cvmx-cmd-queue.c index 8241fc6..132bccc 100644 --- a/drivers/staging/octeon/cvmx-cmd-queue.c +++ b/drivers/staging/octeon/cvmx-cmd-queue.c @@ -47,7 +47,6 @@ * state. It points to a bootmem named block. */ __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; -EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr); /** * Initialize the Global queue state pointer. diff --git a/drivers/staging/octeon/cvmx-helper-ethernet.c b/drivers/staging/octeon/cvmx-helper-ethernet.c index 390f8f80..ba90678 100644 --- a/drivers/staging/octeon/cvmx-helper-ethernet.c +++ b/drivers/staging/octeon/cvmx-helper-ethernet.c @@ -614,7 +614,6 @@ int cvmx_helper_ipd_and_packet_input_enable(void) __cvmx_helper_errata_fix_ipd_ptr_alignment(); return 0; } -EXPORT_SYMBOL_GPL(cvmx_helper_ipd_and_packet_input_enable); /** * Initialize the PIP, IPD, and PKO hardware to support @@ -693,7 +692,6 @@ int cvmx_helper_initialize_packet_io_global(void) #endif return result; } -EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global); /** * Does core local initialization for packet io @@ -738,7 +736,6 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port) */ return port_link_info[ipd_port]; } -EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf); /** * Return the link state of an IPD/PKO port as returned by @@ -797,7 +794,6 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port) } return result; } -EXPORT_SYMBOL_GPL(cvmx_helper_link_get); /** * Configure an IPD/PKO port for the specified link state. This @@ -853,7 +849,6 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) port_link_info[ipd_port].u64 = link_info.u64; return result; } -EXPORT_SYMBOL_GPL(cvmx_helper_link_set); /** * Configure a port for internal and/or external loopback. Internal loopback diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/drivers/staging/octeon/cvmx-helper-util.c index 453d7f6..65d2bc9 100644 --- a/drivers/staging/octeon/cvmx-helper-util.c +++ b/drivers/staging/octeon/cvmx-helper-util.c @@ -251,7 +251,6 @@ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) return 0; } -EXPORT_SYMBOL_GPL(cvmx_helper_setup_red); /** * Setup the common GMX settings that determine the number of @@ -385,7 +384,6 @@ int cvmx_helper_get_ipd_port(int interface, int port) } return -1; } -EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port); /** * Returns the interface number for an IPD/PKO port number. @@ -410,7 +408,6 @@ int cvmx_helper_get_interface_num(int ipd_port) return -1; } -EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num); /** * Returns the interface index number for an IPD/PKO port @@ -434,4 +431,3 @@ int cvmx_helper_get_interface_index_num(int ipd_port) return -1; } -EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_index_num); diff --git a/drivers/staging/octeon/cvmx-pko.c b/drivers/staging/octeon/cvmx-pko.c index 008b881..ade16c6a 100644 --- a/drivers/staging/octeon/cvmx-pko.c +++ b/drivers/staging/octeon/cvmx-pko.c @@ -140,7 +140,6 @@ void cvmx_pko_disable(void) pko_reg_flags.s.ena_pko = 0; cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); } -EXPORT_SYMBOL_GPL(cvmx_pko_disable); /** * Reset the packet output. @@ -182,7 +181,6 @@ void cvmx_pko_shutdown(void) } __cvmx_pko_reset(); } -EXPORT_SYMBOL_GPL(cvmx_pko_shutdown); /** * Configure a output port and the associated queues for use. diff --git a/drivers/staging/octeon/cvmx-spi.c b/drivers/staging/octeon/cvmx-spi.c index 459e3b1..ef5198d 100644 --- a/drivers/staging/octeon/cvmx-spi.c +++ b/drivers/staging/octeon/cvmx-spi.c @@ -177,7 +177,6 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) return res; } -EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface); /** * Callback to perform SPI4 reset -- 2.3.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 06/11] MIPS: OCTEON: rename __cvmx_helper_npi/rgmii_probe
Rename __cvmx_helper_npi/rgmii_probe to __cvmx_helper_npi/rgmii_enumerate
as only latter are used.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/cvmx-helper.c | 12 ++--
arch/mips/include/asm/octeon/cvmx-helper-npi.h | 7 +++
arch/mips/include/asm/octeon/cvmx-helper-rgmii.h | 7 +++
3 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c
b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index de6e619..c0c541b 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -308,15 +308,15 @@ static int __cvmx_helper_loop_enumerate(int interface)
}
/**
- * Probe a NPI interface and determine the number of ports
+ * Enumerate a NPI interface and determine the number of ports
* connected to it. The NPI interface should still be down
* after this call.
*
- * @interface: Interface to probe
+ * @interface: Interface to enumerate
*
* Returns Number of ports on the interface. Zero to disable.
*/
-int __cvmx_helper_npi_probe(int interface)
+int __cvmx_helper_npi_enumerate(int interface)
{
#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
@@ -346,13 +346,13 @@ int __cvmx_helper_npi_probe(int interface)
}
/**
- * Probe RGMII ports and determine the number present
+ * Enumerate RGMII ports and determine the number present
*
- * @interface: Interface to probe
+ * @interface: Interface to enumerate
*
* Returns Number of RGMII/GMII/MII ports (0-4).
*/
-int __cvmx_helper_rgmii_probe(int interface)
+int __cvmx_helper_rgmii_enumerate(int interface)
{
int num_ports = 0;
union cvmx_gmxx_inf_mode mode;
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h
b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
index 8df4c7f..bab9931 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-npi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -36,16 +36,15 @@
#define __CVMX_HELPER_NPI_H__
/**
- * Probe a NPI interface and determine the number of ports
+ * Enumerate a NPI interface and determine the number of ports
* connected to it. The NPI interface should still be down after
* this call.
*
- * @interface: Interface to probe
+ * @interface: Interface to enumerate
*
* Returns Number of ports on the interface. Zero to disable.
*/
-extern int __cvmx_helper_npi_probe(int interface);
-#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
+extern int __cvmx_helper_npi_enumerate(int interface);
/**
* Bringup and enable a NPI interface. After this call packet
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
index 4d7a3db..df7717b 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -36,14 +36,13 @@
#define __CVMX_HELPER_RGMII_H__
/**
- * Probe RGMII ports and determine the number present
+ * Enumerate RGMII ports and determine the number present
*
- * @interface: Interface to probe
+ * @interface: Interface to enumerate
*
* Returns Number of RGMII/GMII/MII ports (0-4).
*/
-extern int __cvmx_helper_rgmii_probe(int interface);
-#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
+extern int __cvmx_helper_rgmii_enumerate(int interface);
/**
* Put an RGMII interface in loopback mode. Internal packets sent
--
2.3.3
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Please read the FAQ at http://www.tux.org/lkml/
[RFC PATCH 02/11] MIPS: OCTEON: move ethernet-specific helpers into a separate file
Move ethernet-specific helpers into a separate file.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/Makefile | 1 +
.../cavium-octeon/executive/cvmx-helper-ethernet.c | 912
arch/mips/cavium-octeon/executive/cvmx-helper.c| 915 +
3 files changed, 921 insertions(+), 907 deletions(-)
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c
diff --git a/arch/mips/cavium-octeon/executive/Makefile
b/arch/mips/cavium-octeon/executive/Makefile
index b6d6e84..e755a73 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -14,6 +14,7 @@ obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
+ cvmx-helper-ethernet.o \
cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c
b/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c
new file mode 100644
index 000..6fe990e
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-ethernet.c
@@ -0,0 +1,912 @@
+/*
+ * This file is based on code from OCTEON SDK by Cavium Networks.
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * priorities[16]) is a function pointer. It is meant to allow
+ * customization of the PKO queue priorities based on the port
+ * number. Users should set this pointer to a function before
+ * calling any cvmx-helper operations.
+ */
+void (*cvmx_override_pko_queue_priority) (int pko_port,
+ uint64_t priorities[16]);
+
+/**
+ * cvmx_override_ipd_port_setup(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the IPD port
+ * setup before packet input/output comes online. It is called
+ * after cvmx-helper does the default IPD configuration, but
+ * before IPD is enabled. Users should set this pointer to a
+ * function before calling any cvmx-helper operations.
+ */
+void (*cvmx_override_ipd_port_setup) (int ipd_port);
+
+/* Port last configured link info index by IPD/PKO port */
+static cvmx_helper_link_info_t
+port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
+
+/**
+ * Configure the IPD/PIP tagging and QoS options for a specific
+ * port. This function determines the POW work queue entry
+ * contents for a port. The setup performed here is controlled by
+ * the defines in executive-config.h.
+ *
+ * @ipd_port: Port to configure. This follows the IPD numbering, not the
+ *per interface numbering
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_port_setup_ipd(int ipd_port)
+{
+ union cvmx_pip_prt_cfgx port_config;
+ union cvmx_pip_prt_tagx tag_config;
+
+ port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+ tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
+
+ /* Have each port go to a different POW queue */
+ port_config.s.qos = ipd_port & 0x7;
+
+ /* Process the headers and place the IP header in the work queue */
+ port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE;
+
+ tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP;
+ tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP;
+ tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT;
+ tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT;
+ tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER;
+ tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP;
+ tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP;
+ tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT;
+ tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT;
+ tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL;
+ tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT;
+ tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+ tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+ tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+ tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+ tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+ /* Put all packets in group 0. Other groups can be used by the app */
+ tag_config.s.grp
Re: RCU bug with v3.17-rc3 ?
Hi, On Thu, Oct 09, 2014 at 10:41:01PM +0200, Rabin Vincent wrote: > What GCC version are you using? > > 4.8.1 and 4.8.2 are known to miscompile the ARM kernel and these > find_get_entry() crashes with 0x involved smell a lot like the > earlier reports from kernels build with those compilers: > > https://lkml.org/lkml/2014/6/25/456 > https://lkml.org/lkml/2014/6/30/375 > https://lkml.org/lkml/2014/6/30/660 > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854 > https://lkml.org/lkml/2014/5/9/330 Is it possible to blacklist those GCC versions on ARM somehow as it seems people are still using them? This bug also ruined a file system on one of my boxes last year (see e.g. http://marc.info/?l=linux-arm-kernel=139033442527244=2). A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: RCU bug with v3.17-rc3 ?
On Fri, Oct 10, 2014 at 05:18:35PM +0100, Russell King - ARM Linux wrote: > On Fri, Oct 10, 2014 at 12:47:06AM +0300, Aaro Koskinen wrote: > > On Thu, Oct 09, 2014 at 10:41:01PM +0200, Rabin Vincent wrote: > > > What GCC version are you using? > > > > > > 4.8.1 and 4.8.2 are known to miscompile the ARM kernel and these > > > find_get_entry() crashes with 0x involved smell a lot like the > > > earlier reports from kernels build with those compilers: > > > > > > https://lkml.org/lkml/2014/6/25/456 > > > https://lkml.org/lkml/2014/6/30/375 > > > https://lkml.org/lkml/2014/6/30/660 > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854 > > > https://lkml.org/lkml/2014/5/9/330 > > > > Is it possible to blacklist those GCC versions on ARM somehow as it > > seems people are still using them? > > > > This bug also ruined a file system on one of my boxes last year > > (see e.g. http://marc.info/?l=linux-arm-kernel=139033442527244=2). > > Given that, why the fsck (pun intended) did you not shout a little louder > about getting it blacklisted. Looking at your marc.info URL, there's > very little information there which hints at filesystem corruption, and > it's a thread of only *one* message according to marc.info. > > Even _if_ I did read the message you point to above, that on its own did > not hint at filesystem corruption. > > So, would you please mind passing on further details about this, > specifically which function in the ext4 code is affected, so it can > be properly written up. I have not done any proper deeper analysis. After I first mailed about the issue I just downgraded GCC and pretty much forgot about it until an engineer from some commercial Linux vendor replied privately months later and kindly pointed me the needed GCC fix (which I then shared in the reply). Then I just moved on using a newer GCC with no issues. Obviously this was not a widespread problem since no one else reported the same. Today I again booted a kernel compiled with GCC 4.8.2 and still was able reproduce the issue, and I think below shows that at least ext3 can easily end up in inconsistent state using these compiler versions: 0) Run the bad kernel: ~ # dmesg|grep GCC [0.00] Linux version 3.17.0-mvebu-los_9755+ (aaro@cooljazz) (gcc version 4.8.2 (GCC) ) #1 Fri Oct 10 21:05:20 EEST 2014 1) Start with small ext3 (writeback) fs with gcc tarball: /mnt/test # ls -l total 84092 -rw-r--r--1 root root 85999682 Apr 24 21:52 gcc-4.8.2.tar.bz2 drwx--2 root root 16384 Oct 10 10:33 lost+found /mnt/test # df -h . FilesystemSize Used Available Use% Mounted on /dev/sdc1 3.8G 90.2M 3.5G 2% /mnt/test 2) Extract, delete & crash: /mnt/test # tar xjf gcc-4.8.2.tar.bz2 /mnt/test # rm -rf gcc-4.8.2 rm: can't remove 'gcc-4.8.2/libgfortran/generated': Directory not empty rm: can't remove 'gcc-4.8.2/libgfortran': Directory not empty rm: can't remove 'gcc-4.8.2/gcc/testsuite/gcc.dg/compat/struct-by-value-18a_y.c': No such file or directory rm: can't remove 'gcc-4.8.2/gcc/testsuite/gcc.dg/compat': Directory not empty rm: can't remove 'gcc-4.8.2/gcc/testsuite/gcc.dg/tree-ssa': Directory not empty rm: can't remove 'gcc-4.8.2/gcc/testsuite/gcc.dg': Directory not empty rm: can't remove 'gcc-4.8.2/gcc/testsuite/gfortran.dg/result_default_init_1.f90': No such file or directory rm: can't remove 'gcc-4.8.2/gcc/testsuite/gfortran.dg': Directory not empty [ 960.864433] Unable to handle kernel paging request at virtual address [ 960.930597] pgd = df6e [ 960.990849] [] *pgd=1fffd831, *pte=, *ppte= [ 961.056512] Internal error: Oops: 1 [#1] ARM [ 961.120063] Modules linked in: [ 961.180974] CPU: 0 PID: 684 Comm: rm Not tainted 3.17.0-mvebu-los_9755+ #1 [ 961.247146] task: df447b00 ti: df4de000 task.ti: df4de000 [ 961.311524] PC is at find_get_entry+0x28/0x84 [ 961.375037] LR is at radix_tree_lookup_slot+0x1c/0x2c [ 961.439061] pc : []lr : []psr: a013 [ 961.439061] sp : df4dfc68 ip : fp : df4dfc7c [ 961.570018] r10: 0001 r9 : c04e3253 r8 : df020b60 [ 961.634596] r7 : 0009001a r6 : r5 : 0009001a r4 : df020c90 [ 961.700070] r3 : r2 : r1 : 0009001a r0 : [ 961.764437] Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 961.830518] Control: 0005317f Table: 1f6e DAC: 0015 [ 961.895866] Process rm (pid: 684, stack limit = 0xdf4de1c0) [ 961.960597] Stack: (0xdf4dfc68 to 0xdf4e) [ 962.022968] fc60: 0001 df020c8c df4dfcb4 df4dfc80 c006eef68 c006e400 [ 962.091214] fc80: c00d4e80 c00d4764 1000 0009001a df0200b60 df020b60 [ 962.159490] fca0: df020bd8 df04e
[PATCH 1/5] MIPS: OCTEON: add crypto helper functions
Add crypto helper functions which are needed for kernel level usage.
The code for these has been extracted from the EdgeRouter Pro GPL tarball.
While at it, also delete duplicate definitions of the functions.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/Makefile | 1 +
arch/mips/cavium-octeon/crypto/Makefile| 5 ++
arch/mips/cavium-octeon/crypto/octeon-crypto.c | 66 ++
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 17 +++
arch/mips/include/asm/octeon/octeon.h | 5 --
5 files changed, 89 insertions(+), 5 deletions(-)
create mode 100644 arch/mips/cavium-octeon/crypto/Makefile
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-crypto.c
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-crypto.h
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 42f5f1a..69a8a8d 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -16,6 +16,7 @@ obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o
csrc-octeon.o
obj-y += dma-octeon.o
obj-y += octeon-memcpy.o
obj-y += executive/
+obj-y += crypto/
obj-$(CONFIG_MTD)+= flash_setup.o
obj-$(CONFIG_SMP)+= smp.o
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
new file mode 100644
index 000..739b803
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -0,0 +1,5 @@
+#
+# OCTEON-specific crypto modules.
+#
+
+obj-y += octeon-crypto.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.c
b/arch/mips/cavium-octeon/crypto/octeon-crypto.c
new file mode 100644
index 000..7c82ff4
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.c
@@ -0,0 +1,66 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2012 Cavium Networks
+ */
+
+#include
+#include
+#include
+
+#include "octeon-crypto.h"
+
+/**
+ * Enable access to Octeon's COP2 crypto hardware for kernel use. Wrap any
+ * crypto operations in calls to octeon_crypto_enable/disable in order to make
+ * sure the state of COP2 isn't corrupted if userspace is also performing
+ * hardware crypto operations. Allocate the state parameter on the stack.
+ * Preemption must be disabled to prevent context switches.
+ *
+ * @state: Pointer to state structure to store current COP2 state in.
+ *
+ * Returns: Flags to be passed to octeon_crypto_disable()
+ */
+unsigned long octeon_crypto_enable(struct octeon_cop2_state *state)
+{
+ int status;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ status = read_c0_status();
+ write_c0_status(status | ST0_CU2);
+ if (KSTK_STATUS(current) & ST0_CU2) {
+ octeon_cop2_save(&(current->thread.cp2));
+ KSTK_STATUS(current) &= ~ST0_CU2;
+ status &= ~ST0_CU2;
+ } else if (status & ST0_CU2) {
+ octeon_cop2_save(state);
+ }
+ local_irq_restore(flags);
+ return status & ST0_CU2;
+}
+EXPORT_SYMBOL_GPL(octeon_crypto_enable);
+
+/**
+ * Disable access to Octeon's COP2 crypto hardware in the kernel. This must be
+ * called after an octeon_crypto_enable() before any context switch or return
to
+ * userspace.
+ *
+ * @state: Pointer to COP2 state to restore
+ * @flags: Return value from octeon_crypto_enable()
+ */
+void octeon_crypto_disable(struct octeon_cop2_state *state,
+ unsigned long crypto_flags)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ if (crypto_flags & ST0_CU2)
+ octeon_cop2_restore(state);
+ else
+ write_c0_status(read_c0_status() & ~ST0_CU2);
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL_GPL(octeon_crypto_disable);
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
new file mode 100644
index 000..5ca86d4
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
+ */
+#ifndef __LINUX_OCTEON_CRYPTO_H
+#define __LINUX_OCTEON_CRYPTO_H
+
+#include
+
+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
+extern void octeon_crypto_disable(struct octeon_cop2_state *state,
+ unsigned long flags);
+
+#endif /* __LINUX_OCTEON_CRYPTO_H */
diff --git a/arch/mips/include/asm/octeon/octeon.h
b/arch/mips/include/asm/octeon/octeon.h
index d781f9e..6dfefd2 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/ar
[PATCH 0/5] MIPS/crypto: MD5 for OCTEON
Hi, This adds accelerated MD5 cryptoapi module for OCTEON. Tested with 3.19-rc1 on EdgeRouter Lite (OCTEON+) and EdgeRouter Pro (OCTEON2) by running selftest, tcrypt and also by sending TCP MD5SIG traffic between OCTEON <-> X86 box. Below figures show the improvement on ER Lite compared to md5-generic (calculated from output of tcrypt mode=402). test 0 ( 16 byte blocks, 16 bytes per update, 1 updates): 1.20x faster test 1 ( 64 byte blocks, 16 bytes per update, 4 updates): 1.17x faster test 2 ( 64 byte blocks, 64 bytes per update, 1 updates): 1.30x faster test 3 ( 256 byte blocks, 16 bytes per update, 16 updates): 1.14x faster test 4 ( 256 byte blocks, 64 bytes per update, 4 updates): 1.29x faster test 5 ( 256 byte blocks, 256 bytes per update, 1 updates): 1.84x faster test 6 ( 1024 byte blocks, 16 bytes per update, 64 updates): 1.13x faster test 7 ( 1024 byte blocks, 256 bytes per update, 4 updates): 2.01x faster test 8 ( 1024 byte blocks, 1024 bytes per update, 1 updates): 2.49x faster test 9 ( 2048 byte blocks, 16 bytes per update, 128 updates): 1.13x faster test 10 ( 2048 byte blocks, 256 bytes per update, 8 updates): 2.05x faster test 11 ( 2048 byte blocks, 1024 bytes per update, 2 updates): 2.57x faster test 12 ( 2048 byte blocks, 2048 bytes per update, 1 updates): 2.71x faster test 13 ( 4096 byte blocks, 16 bytes per update, 256 updates): 1.15x faster test 14 ( 4096 byte blocks, 256 bytes per update, 16 updates): 2.08x faster test 15 ( 4096 byte blocks, 1024 bytes per update, 4 updates): 2.63x faster test 16 ( 4096 byte blocks, 4096 bytes per update, 1 updates): 2.83x faster test 17 ( 8192 byte blocks, 16 bytes per update, 512 updates): 1.13x faster test 18 ( 8192 byte blocks, 256 bytes per update, 32 updates): 2.09x faster test 19 ( 8192 byte blocks, 1024 bytes per update, 8 updates): 2.66x faster test 20 ( 8192 byte blocks, 4096 bytes per update, 2 updates): 2.87x faster test 21 ( 8192 byte blocks, 8192 bytes per update, 1 updates): 2.87x faster A. Aaro Koskinen (5): MIPS: OCTEON: add crypto helper functions MIPS: OCTEON: crypto: add instruction definitions for MD5 MIPS: OCTEON: reintroduce crypto features check MIPS: OCTEON: crypto: add MD5 module crypto: enable OCTEON MD5 module selection arch/mips/cavium-octeon/Makefile | 1 + arch/mips/cavium-octeon/crypto/Makefile | 7 + arch/mips/cavium-octeon/crypto/octeon-crypto.c | 66 +++ arch/mips/cavium-octeon/crypto/octeon-crypto.h | 75 arch/mips/cavium-octeon/crypto/octeon-md5.c | 216 +++ arch/mips/cavium-octeon/executive/octeon-model.c | 6 + arch/mips/include/asm/octeon/octeon-feature.h| 17 +- arch/mips/include/asm/octeon/octeon.h| 5 - crypto/Kconfig | 9 + 9 files changed, 395 insertions(+), 7 deletions(-) create mode 100644 arch/mips/cavium-octeon/crypto/Makefile create mode 100644 arch/mips/cavium-octeon/crypto/octeon-crypto.c create mode 100644 arch/mips/cavium-octeon/crypto/octeon-crypto.h create mode 100644 arch/mips/cavium-octeon/crypto/octeon-md5.c -- 2.2.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/5] MIPS: OCTEON: reintroduce crypto features check
Reintroduce run-time check for crypto features. The old one was deleted
because it was unreliable, now decide the crypto availability on early
boot when the model string is constructed.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/executive/octeon-model.c | 6 ++
arch/mips/include/asm/octeon/octeon-feature.h| 17 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c
b/arch/mips/cavium-octeon/executive/octeon-model.c
index e15b049..b2104bd 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -27,6 +27,9 @@
#include
+enum octeon_feature_bits __octeon_feature_bits __read_mostly;
+EXPORT_SYMBOL_GPL(__octeon_feature_bits);
+
/**
* Read a byte of fuse data
* @byte_addr: address to read
@@ -103,6 +106,9 @@ static const char *__init
octeon_model_get_string_buffer(uint32_t chip_id,
else
suffix = "NSP";
+ if (!fus_dat2.s.nocrypto)
+ __octeon_feature_bits |= OCTEON_HAS_CRYPTO;
+
/*
* Assume pass number is encoded using <5:3><2:0>. Exceptions
* will be fixed later.
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h
b/arch/mips/include/asm/octeon/octeon-feature.h
index c4fe81f..8ebd3f57 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -46,8 +46,6 @@ enum octeon_feature {
OCTEON_FEATURE_SAAD,
/* Does this Octeon support the ZIP offload engine? */
OCTEON_FEATURE_ZIP,
- /* Does this Octeon support crypto acceleration using COP2? */
- OCTEON_FEATURE_CRYPTO,
OCTEON_FEATURE_DORM_CRYPTO,
/* Does this Octeon support PCI express? */
OCTEON_FEATURE_PCIE,
@@ -86,6 +84,21 @@ enum octeon_feature {
OCTEON_MAX_FEATURE
};
+enum octeon_feature_bits {
+ OCTEON_HAS_CRYPTO = 0x0001, /* Crypto acceleration using COP2 */
+};
+extern enum octeon_feature_bits __octeon_feature_bits;
+
+/**
+ * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
+ *
+ * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
+ */
+static inline int octeon_has_crypto(void)
+{
+ return __octeon_feature_bits & OCTEON_HAS_CRYPTO;
+}
+
/**
* Determine if the current Octeon supports a specific feature. These
* checks have been optimized to be fairly quick, but they should still
--
2.2.0
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/5] MIPS: OCTEON: crypto: add MD5 module
Add OCTEON MD5 module.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/crypto/Makefile| 2 +
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 2 +
arch/mips/cavium-octeon/crypto/octeon-md5.c| 216 +
3 files changed, 220 insertions(+)
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-md5.c
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
index 739b803..a74f76d 100644
--- a/arch/mips/cavium-octeon/crypto/Makefile
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -3,3 +3,5 @@
#
obj-y += octeon-crypto.o
+
+obj-$(CONFIG_CRYPTO_MD5_OCTEON) += octeon-md5.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 3f65bc6..e2a4aec 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -14,6 +14,8 @@
#include
#include
+#define OCTEON_CR_OPCODE_PRIORITY 300
+
extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
extern void octeon_crypto_disable(struct octeon_cop2_state *state,
unsigned long flags);
diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c
b/arch/mips/cavium-octeon/crypto/octeon-md5.c
new file mode 100644
index 000..b909881
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c
@@ -0,0 +1,216 @@
+/*
+ * Cryptographic API.
+ *
+ * MD5 Message Digest Algorithm (RFC1321).
+ *
+ * Adapted for OCTEON by Aaro Koskinen .
+ *
+ * Based on crypto/md5.c, which is:
+ *
+ * Derived from cryptoapi implementation, originally based on the
+ * public domain implementation written by Colin Plumb in 1993.
+ *
+ * Copyright (c) Cryptoapi developers.
+ * Copyright (c) 2002 James Morris
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "octeon-crypto.h"
+
+/*
+ * We pass everything as 64-bit. OCTEON can handle misaligned data.
+ */
+
+static void octeon_md5_store_hash(struct md5_state *ctx)
+{
+ u64 *hash = (u64 *)ctx->hash;
+
+ write_octeon_64bit_hash_dword(hash[0], 0);
+ write_octeon_64bit_hash_dword(hash[1], 1);
+}
+
+static void octeon_md5_read_hash(struct md5_state *ctx)
+{
+ u64 *hash = (u64 *)ctx->hash;
+
+ hash[0] = read_octeon_64bit_hash_dword(0);
+ hash[1] = read_octeon_64bit_hash_dword(1);
+}
+
+static void octeon_md5_transform(const void *_block)
+{
+ const u64 *block = _block;
+
+ write_octeon_64bit_block_dword(block[0], 0);
+ write_octeon_64bit_block_dword(block[1], 1);
+ write_octeon_64bit_block_dword(block[2], 2);
+ write_octeon_64bit_block_dword(block[3], 3);
+ write_octeon_64bit_block_dword(block[4], 4);
+ write_octeon_64bit_block_dword(block[5], 5);
+ write_octeon_64bit_block_dword(block[6], 6);
+ octeon_md5_start(block[7]);
+}
+
+static int octeon_md5_init(struct shash_desc *desc)
+{
+ struct md5_state *mctx = shash_desc_ctx(desc);
+
+ mctx->hash[0] = cpu_to_le32(0x67452301);
+ mctx->hash[1] = cpu_to_le32(0xefcdab89);
+ mctx->hash[2] = cpu_to_le32(0x98badcfe);
+ mctx->hash[3] = cpu_to_le32(0x10325476);
+ mctx->byte_count = 0;
+
+ return 0;
+}
+
+static int octeon_md5_update(struct shash_desc *desc, const u8 *data,
+unsigned int len)
+{
+ struct md5_state *mctx = shash_desc_ctx(desc);
+ const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
+ struct octeon_cop2_state state;
+ unsigned long flags;
+
+ mctx->byte_count += len;
+
+ if (avail > len) {
+ memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
+ data, len);
+ return 0;
+ }
+
+ memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), data,
+ avail);
+
+ local_bh_disable();
+ preempt_disable();
+ flags = octeon_crypto_enable();
+ octeon_md5_store_hash(mctx);
+
+ octeon_md5_transform(mctx->block);
+ data += avail;
+ len -= avail;
+
+ while (len >= sizeof(mctx->block)) {
+ octeon_md5_transform(data);
+ data += sizeof(mctx->block);
+ len -= sizeof(mctx->block);
+ }
+
+ octeon_md5_read_hash(mctx);
+ octeon_crypto_disable(, flags);
+ preempt_enable();
+ local_bh_enable();
+
+ memcpy(mctx->block, data, len);
+
+ return 0;
+}
+
+static int octeon_md5_final(struct shash_desc *desc, u8 *out)
+{
+ struct md5_state *mctx = shas
[PATCH 2/5] MIPS: OCTEON: crypto: add instruction definitions for MD5
Add instruction definitions for MD5. Based on information extracted
from EdgeRouter Pro GPL source tarball.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 56 ++
1 file changed, 56 insertions(+)
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 5ca86d4..3f65bc6 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -4,14 +4,70 @@
* for more details.
*
* Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
+ *
+ * MD5 instruction definitions added by Aaro Koskinen .
+ *
*/
#ifndef __LINUX_OCTEON_CRYPTO_H
#define __LINUX_OCTEON_CRYPTO_H
#include
+#include
extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
extern void octeon_crypto_disable(struct octeon_cop2_state *state,
unsigned long flags);
+/*
+ * Macros needed to implement MD5:
+ */
+
+/*
+ * The index can be 0-1.
+ */
+#define write_octeon_64bit_hash_dword(value, index)\
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x0048+" STR(index)\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
+/*
+ * The index can be 0-1.
+ */
+#define read_octeon_64bit_hash_dword(index)\
+({ \
+ u64 __value;\
+ \
+ __asm__ __volatile__ ( \
+ "dmfc2 %[rt],0x0048+" STR(index)\
+ : [rt] "=d" (__value) \
+ : );\
+ \
+ __value;\
+})
+
+/*
+ * The index can be 0-6.
+ */
+#define write_octeon_64bit_block_dword(value, index) \
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x0040+" STR(index)\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
+/*
+ * The value is the final block dword (64-bit).
+ */
+#define octeon_md5_start(value)\
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x4047"\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
#endif /* __LINUX_OCTEON_CRYPTO_H */
--
2.2.0
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[PATCH 5/5] crypto: enable OCTEON MD5 module selection
Enable user to select OCTEON MD5 module. Signed-off-by: Aaro Koskinen --- crypto/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/crypto/Kconfig b/crypto/Kconfig index 87bbc9c..1618468 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -427,6 +427,15 @@ config CRYPTO_MD5 help MD5 message digest algorithm (RFC1321). +config CRYPTO_MD5_OCTEON + tristate "MD5 digest algorithm (OCTEON)" + depends on CPU_CAVIUM_OCTEON + select CRYPTO_MD5 + select CRYPTO_HASH + help + MD5 message digest algorithm (RFC1321) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_MD5_SPARC64 tristate "MD5 digest algorithm (SPARC64)" depends on SPARC64 -- 2.2.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 07/10] MIPS: support for hybrid FPRs
Hi, On Thu, Sep 11, 2014 at 08:30:20AM +0100, Paul Burton wrote: > Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but > accesses to odd indexed single registers use bits 63:32 of the > preceeding even indexed 64b register. In this mode all FP code > except that built for the plain FP64 ABI can execute correctly. Most > notably a combination of FP64A & FP32 code can execute correctly, > allowing for existing FP32 binaries to be linked with new FP64A binaries > that can make use of 64 bit FP & MSA. This commit (4227a2d4efc9c84f35826dc4d1e6dc183f6c1c05, bisected) in 3.19-rc1 breaks my Loongson-2F system. I get endless amount of "Reserved instruction in kernel code" exceptions when booting. See some examples below. Nothing crashes, and there is some forward progress, but obviously it's completely unusable. Any ideas? [2.872000] Reserved instruction in kernel code[#1]: [2.872000] CPU: 0 PID: 231 Comm: hotplug Not tainted 3.18.0-lemote-los_7f08-09423-g988adfd #1 [2.872000] task: 98009f1c7480 ti: 98009a2e8000 task.ti: 98009a2e8000 [2.872000] $ 0 : 77d32c14 0001 [2.872000] $ 4 : 1000802c 98009a2ebeb0 0002 [2.872000] $ 8 : 0010 7efefeff 24242424 81010100 [2.872000] $12 : 100044e1 101f [2.872000] $16 : 00400164 7fdb3ee0 77d62cf8 [2.872000] $20 : 77d61ed0 77d61ed0 004022d8 [2.872000] $24 : 0005 77d4ba80 [2.872000] $28 : 98009a2e8000 98009a2ebe70 7fdb3ee8 802077e0 [2.872000] Hi: 002c [2.872000] Lo: 000b [2.872000] epc : 8020e8d4 do_cpu+0x304/0x4f0 [2.872000] Not tainted [2.872000] ra: 802077e0 ret_from_exception+0x0/0x1c [2.872000] Status: 100044e3 KX SX UX KERNEL EXL IE [2.872000] Cause : 10008028 [2.872000] PrId : 6303 (ICT Loongson-2) [2.872000] Modules linked in: [2.872000] Process hotplug (pid: 231, threadinfo=98009a2e8000, task=98009f1c7480, tls=) [2.872000] Stack : 77d5 77d62c10 c000 77d61ed0 77d622d8 00400164 7fdb3ee0 802077e0 77d32c14 7fdb3da8 77d62bf0 7fdb3db8 7fdb3d90 7fdb3ee8 bba0ffce 7efefeff 24242424 81010100 0fc1 00400164 7fdb3ee0 77d62cf8 77d61ed0 77d61ed0 004022d8 0005 77d4ba80 6474e552 77d6a000 7fdb3d90 7fdb3ee8 77d41038 ... [2.872000] Call Trace: [2.872000] [] do_cpu+0x304/0x4f0 [2.872000] [] ret_from_exception+0x0/0x1c [2.872000] [2.872000] Code: 30420001 2c420001 0040202d <40038005> 2405feff 00651824 40838005 3c032000 3c052400 [2.876000] ---[ end trace 71c7b14ce7da936f ]--- [2.88] Reserved instruction in kernel code[#2]: [2.88] CPU: 0 PID: 232 Comm: hotplug Tainted: G D 3.18.0-lemote-los_7f08-09423-g988adfd #1 [2.88] task: 98009f1c5ea8 ti: 98009a2e4000 task.ti: 98009a2e4000 [2.88] $ 0 : 77832c14 0001 [2.88] $ 4 : 1000802c 98009a2e7eb0 0002 [2.88] $ 8 : 0010 7efefeff 24242424 81010100 [2.88] $12 : 100044e1 101f [2.88] $16 : 00400164 7fd876e0 77862cf8 [2.88] $20 : 77861ed0 77861ed0 004022d8 [2.88] $24 : 0005 7784ba80 [2.88] $28 : 98009a2e4000 98009a2e7e70 7fd876e8 802077e0 [2.88] Hi: 002c [2.88] Lo: 000b [2.88] epc : 8020e8d4 do_cpu+0x304/0x4f0 [2.88] Tainted: G D [2.88] ra: 802077e0 ret_from_exception+0x0/0x1c [2.88] Status: 100044e3 KX SX UX KERNEL EXL IE [2.88] Cause : 10008028 [2.88] PrId : 6303 (ICT Loongson-2) [2.88] Modules linked in: [2.88] Process hotplug (pid: 232, threadinfo=98009a2e4000, task=98009f1c5ea8, tls=) [2.88] Stack
Re: [PATCH 07/10] MIPS: support for hybrid FPRs
Hi, On Tue, Dec 23, 2014 at 11:31:54PM +, James Hogan wrote: > On Wed, Dec 24, 2014 at 01:21:11AM +0200, Aaro Koskinen wrote: > > On Thu, Sep 11, 2014 at 08:30:20AM +0100, Paul Burton wrote: > > > Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but > > > accesses to odd indexed single registers use bits 63:32 of the > > > preceeding even indexed 64b register. In this mode all FP code > > > except that built for the plain FP64 ABI can execute correctly. Most > > > notably a combination of FP64A & FP32 code can execute correctly, > > > allowing for existing FP32 binaries to be linked with new FP64A binaries > > > that can make use of 64 bit FP & MSA. > > > > This commit (4227a2d4efc9c84f35826dc4d1e6dc183f6c1c05, bisected) > > in 3.19-rc1 breaks my Loongson-2F system. I get endless amount > > of "Reserved instruction in kernel code" exceptions when booting. > > See some examples below. Nothing crashes, and there is some forward > > progress, but obviously it's completely unusable. > > > > Any ideas? > > > > [2.872000] Reserved instruction in kernel code[#1]: > ... > > Code: 30420001 2c420001 0040202d <40038005> 2405feff 00651824 40838005 > > 3c032000 3c052400 > > 0x40038005 = mfc0 v1,$16,5 = mfc0 v1,Config5 > > Does this help (in linux-next)?: > http://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=5bba8dec735f18fe7a2fcd8327f28ef095337ff2 Yes, it does. Many thanks! A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: v3.19-rc1 regression(?) on N900
Hi, On Thu, Dec 25, 2014 at 10:11:21AM +0100, Pavel Machek wrote: > On Thu 2014-12-25 09:32:40, Pali Rohár wrote: > > On Wednesday 24 December 2014 23:57:38 Nishanth Menon wrote: > > > based on automated testing with u-boot as a chained > > > bootloader.. > > > > > > v3.19-rc1: hung > > > https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc1/omap > > > 2plus_defconfig/n900.txt > > Early hang, independend on config. That's "dtb too big". Delete > something, and it should work again. For me, DT boot works fine with 3.19-rc1 as is... > Plus you'll note video regression. ...however, I can confirm that framebuffer is broken: [8.230743] omapfb omapfb: no displays [8.255584] omapfb omapfb: failed to setup omapfb [8.260620] platform omapfb: Driver omapfb requests probe deferral [8.284118] of_get_named_gpiod_flags: parsed 'reset-gpios' property of node '/ocp/spi@48098000/acx565akm@2[0]' - status (0) [8.284271] acx565akm spi1.2: failed to find video source [8.290069] spi spi1.2: Driver acx565akm requests probe deferral I bisected it to ef691ff48bc8 (OMAPDSS: DT: Get source endpoint by matching reg-id). When I revert that, also FB works with 3.19-rc1. A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RESEND] MIPS/loongson2_cpufreq: Fix CPU clock rate setting mismerge
During 3.16 merge window, parts of the commit 8e8acb32960f
(MIPS/loongson2_cpufreq: Fix CPU clock rate setting) seem to have
been deleted probably due to a mismerge, and as a result cpufreq
is broken again on Loongson2 boards in 3.16 and newer kernels.
Fix by repeating the fix.
Signed-off-by: Aaro Koskinen
Cc: sta...@vger.kernel.org # 3.16
---
arch/mips/loongson/lemote-2f/clock.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/mips/loongson/lemote-2f/clock.c
b/arch/mips/loongson/lemote-2f/clock.c
index a217061..462e34d 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
+ unsigned int rate_khz = rate / 1000;
struct cpufreq_frequency_table *pos;
int ret = 0;
int regval;
@@ -107,9 +108,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
propagate_rate(clk);
cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
- if (rate == pos->frequency)
+ if (rate_khz == pos->frequency)
break;
- if (rate != pos->frequency)
+ if (rate_khz != pos->frequency)
return -ENOTSUPP;
clk->rate = rate;
--
2.1.2
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Re: v3.19-rc1 regression(?) on N900
Hi, On Mon, Dec 29, 2014 at 10:04:46AM +0200, Tomi Valkeinen wrote: > On 26/12/14 00:21, Aaro Koskinen wrote: > > > ...however, I can confirm that framebuffer is broken: > > > > [8.230743] omapfb omapfb: no displays > > [8.255584] omapfb omapfb: failed to setup omapfb > > [8.260620] platform omapfb: Driver omapfb requests probe deferral > > [8.284118] of_get_named_gpiod_flags: parsed 'reset-gpios' property of > > node > > '/ocp/spi@48098000/acx565akm@2[0]' - status (0) > > [8.284271] acx565akm spi1.2: failed to find video source > > [8.290069] spi spi1.2: Driver acx565akm requests probe deferral > > > > I bisected it to ef691ff48bc8 (OMAPDSS: DT: Get source endpoint > > by matching reg-id). When I revert that, also FB works with 3.19-rc1. > > I've attached a patch for this. Only hack-tested on OMAP3 beagle, so > please report if it works. That works, thanks. A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] hsi: nokia-modem: fix uninitialized device pointer
modem->device was never initialized. This resulted in logs such as:
[ 241.386322] (NULL device *): CMT rst line change detected
Signed-off-by: Aaro Koskinen
---
drivers/hsi/clients/nokia-modem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/hsi/clients/nokia-modem.c
b/drivers/hsi/clients/nokia-modem.c
index f0c2145..eb4dc63 100644
--- a/drivers/hsi/clients/nokia-modem.c
+++ b/drivers/hsi/clients/nokia-modem.c
@@ -162,6 +162,7 @@ static int nokia_modem_probe(struct device *dev)
return -ENOMEM;
}
dev_set_drvdata(dev, modem);
+ modem->device = dev;
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
--
2.2.0
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Re: [PATCH] Revert 9fc2105aeaaf56b0cf75296a84702d0f9e64437b to fix pyaudio (and probably more)
Hi, On Sun, Jan 04, 2015 at 10:40:49PM +0100, Pavel Machek wrote: > On Sun 2015-01-04 21:26:59, Russell King - ARM Linux wrote: > > On Sun, Jan 04, 2015 at 04:20:57PM -0500, Nicolas Pitre wrote: > > > On Sun, 4 Jan 2015, Linus Torvalds wrote: > > > > > > > On Sun, Jan 4, 2015 at 12:56 PM, Nicolas Pitre > > > > wrote: > > > > > > > > > > It wasted a lot of people's time before by simply being there and > > > > > wrong > > > > > before it was removed. It's only a matter of whose time you want to > > > > > waste. Really. > > > > > > > > Really. Shut up. > > > > > > > > The whole "no regressions" thing is very much about the fact that we > > > > don't waste users time. > > > > > > I was talking about users time all along. > > > > > > Never mind. I'm sorry for the NAK and sorry for attempting to start a > > > discussion to find a better replacement. > > > > Nico, > > > > I encourage you *not* to back down like this. Linus is right in so far > > as the regressions issue, but he is *totally* wrong to do the revert, > > which IMHO has been done out of nothing more than spite. > > > > Either *with or without* the revert, the issue still remains, and needs > > to be addressed properly. > > > > With the revert in place, we now have insanely small bogomips values > > reported via /proc/cpuinfo when hardware timers are used. That needs > > fixing. > > Too bad 9fc2105aeaaf56b0cf75296a84702d0f9e64437b's changelog did not > mention that :-(. > > I see reasonable values on Nokia N900. Do I need to change my config > to see the problem, or should I try reproducing on socfpga board? I believe Nokia boards fall into the "antique hardware" category, so for us using such HW the issue is not visible... A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] staging: xgifb: XGI_main_26: Change variables that is never used
Hi,
On Wed, Jan 28, 2015 at 10:38:07PM +0100, Rickard Strandqvist wrote:
> Variable ar assigned a value that is never used.
> Instead use the struct variable of the same name.
>
> This was found using a static code analysis program called cppcheck
>
> Signed-off-by: Rickard Strandqvist
> ---
> drivers/staging/xgifb/XGI_main_26.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/xgifb/XGI_main_26.c
> b/drivers/staging/xgifb/XGI_main_26.c
> index 709d49e..ecfdf34 100644
> --- a/drivers/staging/xgifb/XGI_main_26.c
> +++ b/drivers/staging/xgifb/XGI_main_26.c
> @@ -1233,7 +1233,7 @@ static int XGIfb_check_var(struct fb_var_screeninfo
> *var, struct fb_info *info)
> unsigned int vtotal = 0;
> unsigned int drate = 0, hrate = 0;
> int found_mode = 0;
> - int refresh_rate, search_idx;
> + int search_idx;
>
> if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED) {
> vtotal = var->upper_margin + var->yres + var->lower_margin
> @@ -1271,7 +1271,7 @@ static int XGIfb_check_var(struct fb_var_screeninfo
> *var, struct fb_info *info)
>
> /* Calculation wrong for 1024x600 - force it to 60Hz */
> if ((var->xres == 1024) && (var->yres == 600))
> - refresh_rate = 60;
> + xgifb_info->refresh_rate = 60;
You are changing behaviour here. Did you test it, is it fixing something?
Otherwise you could just delete the whole if block...
A.
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Re: [PATCH v2 2/2] MIPS: fix kernel lockup or crash after CPU offline/online
Hi,
On Fri, Jan 30, 2015 at 02:59:57PM +, James Hogan wrote:
> On 30/01/15 12:47, Maciej W. Rozycki wrote:
> > On Fri, 30 Jan 2015, James Hogan wrote:
> >
> >>> Hmm, why can a call to `printk' cause a TLB miss, what's so special
> >>> about
> >>> this function? Does it use kernel mapped addresses for any purpose such
> >>> as `vmalloc'?
> >>
> >> It would be the fact netconsole (or whatever other console is in use) is
> >> built as a kernel module, memory for which is allocated from the vmalloc
> >> area.
> >
> > Ah, I see, thanks for enlightening me. But in that case wouldn't it be
> > possible to postpone console output from `printk' until it is safe to
> > access the device? In a manner similar to how for example we handle calls
> > to `printk' made from the hardirq context. That would make things less
> > fragile.
>
> Hmm, kernel/printk/printk.c does have:
>
> static inline int can_use_console(unsigned int cpu)
> {
> return cpu_online(cpu) || have_callable_console();
> }
>
> which should prevent it dumping printk buffer to console. CPU shouldn't
> be marked online that early, which suggests that the console has the
> CON_ANYTIME flag set, which it probably shouldn't if it depends on
> module code. call_console_drivers() seems to ensure the CPU is online or
> has CON_ANYTIME before calling the console write callback.
>
> A quick glance and I can't see any evidence of netconsole being able to
> get CON_ANYTIME.
It does not set the flag. But flags are kept in module's static data,
so the original problem stays.
A.
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Re: [PATCHv3 01/17] mm: add missing __PAGETABLE_{PUD,PMD}_FOLDED defines
Hi,
On Thu, Feb 26, 2015 at 01:35:04PM +0200, Kirill A. Shutemov wrote:
> Core mm expects __PAGETABLE_{PUD,PMD}_FOLDED to be defined if these page
> table levels folded. Usually, these defines are provided by
> and .
>
> But some architectures fold page table levels in a custom way. They need
> to define these macros themself. This patch adds missing defines.
>
> The patch fixes mm->nr_pmds underflow and eliminates dead __pmd_alloc()
> and __pud_alloc() on architectures without these page table levels.
>
> Signed-off-by: Kirill A. Shutemov
> Cc: Aaro Koskinen
PA-RISC change:
Tested-by: Aaro Koskinen
A.
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[PATCH 1/7] crypto: octeon - don't disable bottom half in octeon-md5
Don't disable bottom half while the crypto engine is in use, as it should be unnecessary: All kernel crypto engine usage is wrapped with crypto engine state save/restore, so if we get interrupted by softirq that uses crypto they should save and restore our context. This actually fixes an issue when running OCTEON MD5 with interrupts disabled (tcrypt mode=302). There's a WARNING because the module is trying to enable the bottom half with irqs disabled: [ 52.656610] [ cut here ] [ 52.661439] WARNING: CPU: 1 PID: 428 at /home/aaro/git/linux/kernel/softirq.c:150 __local_bh_enable_ip+0x9c/0xd8() [ 52.671780] Modules linked in: tcrypt(+) [...] [ 52.763539] [] warn_slowpath_common+0x94/0xd8 [ 52.769465] [] __local_bh_enable_ip+0x9c/0xd8 [ 52.775390] [] octeon_md5_final+0x12c/0x1e8 [ 52.781144] [] shash_compat_digest+0xd0/0x1b0 Signed-off-by: Aaro Koskinen --- arch/mips/cavium-octeon/crypto/octeon-md5.c | 4 1 file changed, 4 deletions(-) diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c b/arch/mips/cavium-octeon/crypto/octeon-md5.c index b909881..3dd8845 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-md5.c +++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c @@ -97,7 +97,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), data, avail); - local_bh_disable(); preempt_disable(); flags = octeon_crypto_enable(); octeon_md5_store_hash(mctx); @@ -115,7 +114,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, octeon_md5_read_hash(mctx); octeon_crypto_disable(, flags); preempt_enable(); - local_bh_enable(); memcpy(mctx->block, data, len); @@ -133,7 +131,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) *p++ = 0x80; - local_bh_disable(); preempt_disable(); flags = octeon_crypto_enable(); octeon_md5_store_hash(mctx); @@ -153,7 +150,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) octeon_md5_read_hash(mctx); octeon_crypto_disable(, flags); preempt_enable(); - local_bh_enable(); memcpy(out, mctx->hash, sizeof(mctx->hash)); memset(mctx, 0, sizeof(*mctx)); -- 2.2.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/7] crypto: octeon - add instruction definitions for SHA1/256/512
Add instruction definitions for SHA1/256/512.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 83 --
1 file changed, 79 insertions(+), 4 deletions(-)
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index e2a4aec..3550725 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -5,7 +5,8 @@
*
* Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
*
- * MD5 instruction definitions added by Aaro Koskinen .
+ * MD5/SHA1/SHA256/SHA512 instruction definitions added by
+ * Aaro Koskinen .
*
*/
#ifndef __LINUX_OCTEON_CRYPTO_H
@@ -21,11 +22,11 @@ extern void octeon_crypto_disable(struct octeon_cop2_state
*state,
unsigned long flags);
/*
- * Macros needed to implement MD5:
+ * Macros needed to implement MD5/SHA1/SHA256:
*/
/*
- * The index can be 0-1.
+ * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
*/
#define write_octeon_64bit_hash_dword(value, index)\
do { \
@@ -36,7 +37,7 @@ do { \
} while (0)
/*
- * The index can be 0-1.
+ * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
*/
#define read_octeon_64bit_hash_dword(index)\
({ \
@@ -72,4 +73,78 @@ do { \
: [rt] "d" (value));\
} while (0)
+/*
+ * The value is the final block dword (64-bit).
+ */
+#define octeon_sha1_start(value) \
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x4057"\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
+/*
+ * The value is the final block dword (64-bit).
+ */
+#define octeon_sha256_start(value) \
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x404f"\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
+/*
+ * Macros needed to implement SHA512:
+ */
+
+/*
+ * The index can be 0-7.
+ */
+#define write_octeon_64bit_hash_sha512(value, index) \
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x0250+" STR(index)\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
+/*
+ * The index can be 0-7.
+ */
+#define read_octeon_64bit_hash_sha512(index) \
+({ \
+ u64 __value;\
+ \
+ __asm__ __volatile__ ( \
+ "dmfc2 %[rt],0x0250+" STR(index)\
+ : [rt] "=d" (__value) \
+ : );\
+ \
+ __value;\
+})
+
+/*
+ * The index can be 0-14.
+ */
+#define write_octeon_64bit_block_sha512(value, index) \
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x0240+" STR(index)\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
+/*
+ * The value is the final block word (64-bit).
+ */
+#define octeon_sha512_start(value) \
+do { \
+ __asm__ __volatile__ ( \
+ "dmtc2 %[rt],0x424f"\
+ : \
+ : [rt] "d" (value));\
+} while (0)
+
#endif /* __LINUX_OCTEON_CRYPTO_H */
--
2.2.0
--
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[PATCH 4/7] crypto: octeon - add SHA1 module
Add OCTEON SHA1 module.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/crypto/Makefile | 3 +-
arch/mips/cavium-octeon/crypto/octeon-sha1.c | 241 +++
2 files changed, 243 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha1.c
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
index a74f76d..3f671d6 100644
--- a/arch/mips/cavium-octeon/crypto/Makefile
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -4,4 +4,5 @@
obj-y += octeon-crypto.o
-obj-$(CONFIG_CRYPTO_MD5_OCTEON) += octeon-md5.o
+obj-$(CONFIG_CRYPTO_MD5_OCTEON)+= octeon-md5.o
+obj-$(CONFIG_CRYPTO_SHA1_OCTEON) += octeon-sha1.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha1.c
b/arch/mips/cavium-octeon/crypto/octeon-sha1.c
new file mode 100644
index 000..2b74b5b
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-sha1.c
@@ -0,0 +1,241 @@
+/*
+ * Cryptographic API.
+ *
+ * SHA1 Secure Hash Algorithm.
+ *
+ * Adapted for OCTEON by Aaro Koskinen .
+ *
+ * Based on crypto/sha1_generic.c, which is:
+ *
+ * Copyright (c) Alan Smithee.
+ * Copyright (c) Andrew McDonald
+ * Copyright (c) Jean-Francois Dive
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "octeon-crypto.h"
+
+/*
+ * We pass everything as 64-bit. OCTEON can handle misaligned data.
+ */
+
+static void octeon_sha1_store_hash(struct sha1_state *sctx)
+{
+ u64 *hash = (u64 *)sctx->state;
+ union {
+ u32 word[2];
+ u64 dword;
+ } hash_tail = { { sctx->state[4], } };
+
+ write_octeon_64bit_hash_dword(hash[0], 0);
+ write_octeon_64bit_hash_dword(hash[1], 1);
+ write_octeon_64bit_hash_dword(hash_tail.dword, 2);
+ memzero_explicit(_tail.word[0], sizeof(hash_tail.word[0]));
+}
+
+static void octeon_sha1_read_hash(struct sha1_state *sctx)
+{
+ u64 *hash = (u64 *)sctx->state;
+ union {
+ u32 word[2];
+ u64 dword;
+ } hash_tail;
+
+ hash[0] = read_octeon_64bit_hash_dword(0);
+ hash[1] = read_octeon_64bit_hash_dword(1);
+ hash_tail.dword = read_octeon_64bit_hash_dword(2);
+ sctx->state[4] = hash_tail.word[0];
+ memzero_explicit(_tail.dword, sizeof(hash_tail.dword));
+}
+
+static void octeon_sha1_transform(const void *_block)
+{
+ const u64 *block = _block;
+
+ write_octeon_64bit_block_dword(block[0], 0);
+ write_octeon_64bit_block_dword(block[1], 1);
+ write_octeon_64bit_block_dword(block[2], 2);
+ write_octeon_64bit_block_dword(block[3], 3);
+ write_octeon_64bit_block_dword(block[4], 4);
+ write_octeon_64bit_block_dword(block[5], 5);
+ write_octeon_64bit_block_dword(block[6], 6);
+ octeon_sha1_start(block[7]);
+}
+
+static int octeon_sha1_init(struct shash_desc *desc)
+{
+ struct sha1_state *sctx = shash_desc_ctx(desc);
+
+ sctx->state[0] = SHA1_H0;
+ sctx->state[1] = SHA1_H1;
+ sctx->state[2] = SHA1_H2;
+ sctx->state[3] = SHA1_H3;
+ sctx->state[4] = SHA1_H4;
+ sctx->count = 0;
+
+ return 0;
+}
+
+static void __octeon_sha1_update(struct sha1_state *sctx, const u8 *data,
+unsigned int len)
+{
+ unsigned int partial;
+ unsigned int done;
+ const u8 *src;
+
+ partial = sctx->count % SHA1_BLOCK_SIZE;
+ sctx->count += len;
+ done = 0;
+ src = data;
+
+ if ((partial + len) >= SHA1_BLOCK_SIZE) {
+ if (partial) {
+ done = -partial;
+ memcpy(sctx->buffer + partial, data,
+ done + SHA1_BLOCK_SIZE);
+ src = sctx->buffer;
+ }
+
+ do {
+ octeon_sha1_transform(src);
+ done += SHA1_BLOCK_SIZE;
+ src = data + done;
+ } while (done + SHA1_BLOCK_SIZE <= len);
+
+ partial = 0;
+ }
+ memcpy(sctx->buffer + partial, src, len - done);
+}
+
+static int octeon_sha1_update(struct shash_desc *desc, const u8 *data,
+ unsigned int len)
+{
+ struct sha1_state *sctx = shash_desc_ctx(desc);
+ struct octeon_cop2_state state;
+ unsigned long flags;
+
+ /*
+* Small updates never reach the crypto engine, so the generic sha1 is
+* faster because of the heavyweight octeon_crypto_enable() /
+* octeon_crypto_disable().
+*/
+
[PATCH 2/7] crypto: octeon - always disable preemption when using crypto engine
Always disable preemption on behalf of the drivers when crypto engine is taken into use. This will simplify the usage. Signed-off-by: Aaro Koskinen --- arch/mips/cavium-octeon/crypto/octeon-crypto.c | 4 +++- arch/mips/cavium-octeon/crypto/octeon-md5.c| 4 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.c b/arch/mips/cavium-octeon/crypto/octeon-crypto.c index 7c82ff4..f66bd1a 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-crypto.c +++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.c @@ -17,7 +17,7 @@ * crypto operations in calls to octeon_crypto_enable/disable in order to make * sure the state of COP2 isn't corrupted if userspace is also performing * hardware crypto operations. Allocate the state parameter on the stack. - * Preemption must be disabled to prevent context switches. + * Returns with preemption disabled. * * @state: Pointer to state structure to store current COP2 state in. * @@ -28,6 +28,7 @@ unsigned long octeon_crypto_enable(struct octeon_cop2_state *state) int status; unsigned long flags; + preempt_disable(); local_irq_save(flags); status = read_c0_status(); write_c0_status(status | ST0_CU2); @@ -62,5 +63,6 @@ void octeon_crypto_disable(struct octeon_cop2_state *state, else write_c0_status(read_c0_status() & ~ST0_CU2); local_irq_restore(flags); + preempt_enable(); } EXPORT_SYMBOL_GPL(octeon_crypto_disable); diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c b/arch/mips/cavium-octeon/crypto/octeon-md5.c index 3dd8845..12dccdb 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-md5.c +++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c @@ -97,7 +97,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), data, avail); - preempt_disable(); flags = octeon_crypto_enable(); octeon_md5_store_hash(mctx); @@ -113,7 +112,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, octeon_md5_read_hash(mctx); octeon_crypto_disable(, flags); - preempt_enable(); memcpy(mctx->block, data, len); @@ -131,7 +129,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) *p++ = 0x80; - preempt_disable(); flags = octeon_crypto_enable(); octeon_md5_store_hash(mctx); @@ -149,7 +146,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) octeon_md5_read_hash(mctx); octeon_crypto_disable(, flags); - preempt_enable(); memcpy(out, mctx->hash, sizeof(mctx->hash)); memset(mctx, 0, sizeof(*mctx)); -- 2.2.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 6/7] crypto: octeon - add SHA512 module
Add OCTEON SHA512 module.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/crypto/Makefile| 1 +
arch/mips/cavium-octeon/crypto/octeon-sha512.c | 277 +
2 files changed, 278 insertions(+)
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha512.c
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
index 47806a5..f7aa9d5 100644
--- a/arch/mips/cavium-octeon/crypto/Makefile
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -7,3 +7,4 @@ obj-y += octeon-crypto.o
obj-$(CONFIG_CRYPTO_MD5_OCTEON)+= octeon-md5.o
obj-$(CONFIG_CRYPTO_SHA1_OCTEON) += octeon-sha1.o
obj-$(CONFIG_CRYPTO_SHA256_OCTEON) += octeon-sha256.o
+obj-$(CONFIG_CRYPTO_SHA512_OCTEON) += octeon-sha512.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha512.c
b/arch/mips/cavium-octeon/crypto/octeon-sha512.c
new file mode 100644
index 000..d5fb3c6
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-sha512.c
@@ -0,0 +1,277 @@
+/*
+ * Cryptographic API.
+ *
+ * SHA-512 and SHA-384 Secure Hash Algorithm.
+ *
+ * Adapted for OCTEON by Aaro Koskinen .
+ *
+ * Based on crypto/sha512_generic.c, which is:
+ *
+ * Copyright (c) Jean-Luc Cooke
+ * Copyright (c) Andrew McDonald
+ * Copyright (c) 2003 Kyle McMartin
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2, or (at your option) any
+ * later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "octeon-crypto.h"
+
+/*
+ * We pass everything as 64-bit. OCTEON can handle misaligned data.
+ */
+
+static void octeon_sha512_store_hash(struct sha512_state *sctx)
+{
+ write_octeon_64bit_hash_sha512(sctx->state[0], 0);
+ write_octeon_64bit_hash_sha512(sctx->state[1], 1);
+ write_octeon_64bit_hash_sha512(sctx->state[2], 2);
+ write_octeon_64bit_hash_sha512(sctx->state[3], 3);
+ write_octeon_64bit_hash_sha512(sctx->state[4], 4);
+ write_octeon_64bit_hash_sha512(sctx->state[5], 5);
+ write_octeon_64bit_hash_sha512(sctx->state[6], 6);
+ write_octeon_64bit_hash_sha512(sctx->state[7], 7);
+}
+
+static void octeon_sha512_read_hash(struct sha512_state *sctx)
+{
+ sctx->state[0] = read_octeon_64bit_hash_sha512(0);
+ sctx->state[1] = read_octeon_64bit_hash_sha512(1);
+ sctx->state[2] = read_octeon_64bit_hash_sha512(2);
+ sctx->state[3] = read_octeon_64bit_hash_sha512(3);
+ sctx->state[4] = read_octeon_64bit_hash_sha512(4);
+ sctx->state[5] = read_octeon_64bit_hash_sha512(5);
+ sctx->state[6] = read_octeon_64bit_hash_sha512(6);
+ sctx->state[7] = read_octeon_64bit_hash_sha512(7);
+}
+
+static void octeon_sha512_transform(const void *_block)
+{
+ const u64 *block = _block;
+
+ write_octeon_64bit_block_sha512(block[0], 0);
+ write_octeon_64bit_block_sha512(block[1], 1);
+ write_octeon_64bit_block_sha512(block[2], 2);
+ write_octeon_64bit_block_sha512(block[3], 3);
+ write_octeon_64bit_block_sha512(block[4], 4);
+ write_octeon_64bit_block_sha512(block[5], 5);
+ write_octeon_64bit_block_sha512(block[6], 6);
+ write_octeon_64bit_block_sha512(block[7], 7);
+ write_octeon_64bit_block_sha512(block[8], 8);
+ write_octeon_64bit_block_sha512(block[9], 9);
+ write_octeon_64bit_block_sha512(block[10], 10);
+ write_octeon_64bit_block_sha512(block[11], 11);
+ write_octeon_64bit_block_sha512(block[12], 12);
+ write_octeon_64bit_block_sha512(block[13], 13);
+ write_octeon_64bit_block_sha512(block[14], 14);
+ octeon_sha512_start(block[15]);
+}
+
+static int octeon_sha512_init(struct shash_desc *desc)
+{
+ struct sha512_state *sctx = shash_desc_ctx(desc);
+
+ sctx->state[0] = SHA512_H0;
+ sctx->state[1] = SHA512_H1;
+ sctx->state[2] = SHA512_H2;
+ sctx->state[3] = SHA512_H3;
+ sctx->state[4] = SHA512_H4;
+ sctx->state[5] = SHA512_H5;
+ sctx->state[6] = SHA512_H6;
+ sctx->state[7] = SHA512_H7;
+ sctx->count[0] = sctx->count[1] = 0;
+
+ return 0;
+}
+
+static int octeon_sha384_init(struct shash_desc *desc)
+{
+ struct sha512_state *sctx = shash_desc_ctx(desc);
+
+ sctx->state[0] = SHA384_H0;
+ sctx->state[1] = SHA384_H1;
+ sctx->state[2] = SHA384_H2;
+ sctx->state[3] = SHA384_H3;
+ sctx->state[4] = SHA384_H4;
+ sctx->state[5] = SHA384_H5;
+ sctx->state[6] = SHA384_H6;
+ sctx->state[7] = SHA384_H7;
+ sctx->count[0] = sctx->count[1] = 0;
+
+ return 0;
+}
+
+static void __octeon_sha512_update(struct sha512_state *sctx, const u8 *data,
+
[PATCH 0/7] crypto: OCTEON MD5 bugfix + SHA modules
bytes per update, 256 updates): 1.86x faster test 14 ( 4096 byte blocks, 256 bytes per update, 16 updates): 6.12x faster test 15 ( 4096 byte blocks, 1024 bytes per update, 4 updates): 9.03x faster test 16 ( 4096 byte blocks, 4096 bytes per update, 1 updates): 10.31x faster test 17 ( 8192 byte blocks, 16 bytes per update, 512 updates): 1.85x faster test 18 ( 8192 byte blocks, 256 bytes per update, 32 updates): 6.18x faster test 19 ( 8192 byte blocks, 1024 bytes per update, 8 updates): 9.26x faster test 20 ( 8192 byte blocks, 4096 bytes per update, 2 updates): 10.64x faster test 21 ( 8192 byte blocks, 8192 bytes per update, 1 updates): 10.65x faster A. Aaro Koskinen (7): crypto: octeon - don't disable bottom half in octeon-md5 crypto: octeon - always disable preemption when using crypto engine crypto: octeon - add instruction definitions for SHA1/256/512 crypto: octeon - add SHA1 module crypto: octeon - add SHA256 module crypto: octeon - add SHA512 module crypto: octeon - enable OCTEON SHA1/256/512 module selection arch/mips/cavium-octeon/crypto/Makefile| 5 +- arch/mips/cavium-octeon/crypto/octeon-crypto.c | 4 +- arch/mips/cavium-octeon/crypto/octeon-crypto.h | 83 +++- arch/mips/cavium-octeon/crypto/octeon-md5.c| 8 - arch/mips/cavium-octeon/crypto/octeon-sha1.c | 241 + arch/mips/cavium-octeon/crypto/octeon-sha256.c | 280 + arch/mips/cavium-octeon/crypto/octeon-sha512.c | 277 crypto/Kconfig | 27 +++ 8 files changed, 911 insertions(+), 14 deletions(-) create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha1.c create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha256.c create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha512.c -- 2.2.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 5/7] crypto: octeon - add SHA256 module
Add OCTEON SHA256 module.
Signed-off-by: Aaro Koskinen
---
arch/mips/cavium-octeon/crypto/Makefile| 1 +
arch/mips/cavium-octeon/crypto/octeon-sha256.c | 280 +
2 files changed, 281 insertions(+)
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha256.c
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
index 3f671d6..47806a5 100644
--- a/arch/mips/cavium-octeon/crypto/Makefile
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -6,3 +6,4 @@ obj-y += octeon-crypto.o
obj-$(CONFIG_CRYPTO_MD5_OCTEON)+= octeon-md5.o
obj-$(CONFIG_CRYPTO_SHA1_OCTEON) += octeon-sha1.o
+obj-$(CONFIG_CRYPTO_SHA256_OCTEON) += octeon-sha256.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha256.c
b/arch/mips/cavium-octeon/crypto/octeon-sha256.c
new file mode 100644
index 000..97e96fe
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-sha256.c
@@ -0,0 +1,280 @@
+/*
+ * Cryptographic API.
+ *
+ * SHA-224 and SHA-256 Secure Hash Algorithm.
+ *
+ * Adapted for OCTEON by Aaro Koskinen .
+ *
+ * Based on crypto/sha256_generic.c, which is:
+ *
+ * Copyright (c) Jean-Luc Cooke
+ * Copyright (c) Andrew McDonald
+ * Copyright (c) 2002 James Morris
+ * SHA224 Support Copyright 2007 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "octeon-crypto.h"
+
+/*
+ * We pass everything as 64-bit. OCTEON can handle misaligned data.
+ */
+
+static void octeon_sha256_store_hash(struct sha256_state *sctx)
+{
+ u64 *hash = (u64 *)sctx->state;
+
+ write_octeon_64bit_hash_dword(hash[0], 0);
+ write_octeon_64bit_hash_dword(hash[1], 1);
+ write_octeon_64bit_hash_dword(hash[2], 2);
+ write_octeon_64bit_hash_dword(hash[3], 3);
+}
+
+static void octeon_sha256_read_hash(struct sha256_state *sctx)
+{
+ u64 *hash = (u64 *)sctx->state;
+
+ hash[0] = read_octeon_64bit_hash_dword(0);
+ hash[1] = read_octeon_64bit_hash_dword(1);
+ hash[2] = read_octeon_64bit_hash_dword(2);
+ hash[3] = read_octeon_64bit_hash_dword(3);
+}
+
+static void octeon_sha256_transform(const void *_block)
+{
+ const u64 *block = _block;
+
+ write_octeon_64bit_block_dword(block[0], 0);
+ write_octeon_64bit_block_dword(block[1], 1);
+ write_octeon_64bit_block_dword(block[2], 2);
+ write_octeon_64bit_block_dword(block[3], 3);
+ write_octeon_64bit_block_dword(block[4], 4);
+ write_octeon_64bit_block_dword(block[5], 5);
+ write_octeon_64bit_block_dword(block[6], 6);
+ octeon_sha256_start(block[7]);
+}
+
+static int octeon_sha224_init(struct shash_desc *desc)
+{
+ struct sha256_state *sctx = shash_desc_ctx(desc);
+
+ sctx->state[0] = SHA224_H0;
+ sctx->state[1] = SHA224_H1;
+ sctx->state[2] = SHA224_H2;
+ sctx->state[3] = SHA224_H3;
+ sctx->state[4] = SHA224_H4;
+ sctx->state[5] = SHA224_H5;
+ sctx->state[6] = SHA224_H6;
+ sctx->state[7] = SHA224_H7;
+ sctx->count = 0;
+
+ return 0;
+}
+
+static int octeon_sha256_init(struct shash_desc *desc)
+{
+ struct sha256_state *sctx = shash_desc_ctx(desc);
+
+ sctx->state[0] = SHA256_H0;
+ sctx->state[1] = SHA256_H1;
+ sctx->state[2] = SHA256_H2;
+ sctx->state[3] = SHA256_H3;
+ sctx->state[4] = SHA256_H4;
+ sctx->state[5] = SHA256_H5;
+ sctx->state[6] = SHA256_H6;
+ sctx->state[7] = SHA256_H7;
+ sctx->count = 0;
+
+ return 0;
+}
+
+static void __octeon_sha256_update(struct sha256_state *sctx, const u8 *data,
+ unsigned int len)
+{
+ unsigned int partial;
+ unsigned int done;
+ const u8 *src;
+
+ partial = sctx->count % SHA256_BLOCK_SIZE;
+ sctx->count += len;
+ done = 0;
+ src = data;
+
+ if ((partial + len) >= SHA256_BLOCK_SIZE) {
+ if (partial) {
+ done = -partial;
+ memcpy(sctx->buf + partial, data,
+ done + SHA256_BLOCK_SIZE);
+ src = sctx->buf;
+ }
+
+ do {
+ octeon_sha256_transform(src);
+ done += SHA256_BLOCK_SIZE;
+ src = data + done;
+ } while (done + SHA256_BLOCK_SIZE <= len);
+
+ partial = 0;
+ }
+ memcpy(sctx->buf + partial, src, len - done);
+}
+
+static int octeon_sha256_update(struct shash_desc *desc, const u8 *data,
+
[PATCH 7/7] crypto: octeon - enable OCTEON SHA1/256/512 module selection
Enable user to select OCTEON SHA1/256/512 modules. Signed-off-by: Aaro Koskinen --- crypto/Kconfig | 27 +++ 1 file changed, 27 insertions(+) diff --git a/crypto/Kconfig b/crypto/Kconfig index 50f4da4..38b2315 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -546,6 +546,15 @@ config CRYPTO_SHA512_SSSE3 Extensions version 1 (AVX1), or Advanced Vector Extensions version 2 (AVX2) instructions, when available. +config CRYPTO_SHA1_OCTEON + tristate "SHA1 digest algorithm (OCTEON)" + depends on CPU_CAVIUM_OCTEON + select CRYPTO_SHA1 + select CRYPTO_HASH + help + SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_SHA1_SPARC64 tristate "SHA1 digest algorithm (SPARC64)" depends on SPARC64 @@ -610,6 +619,15 @@ config CRYPTO_SHA256 This code also includes SHA-224, a 224 bit hash with 112 bits of security against collision attacks. +config CRYPTO_SHA256_OCTEON + tristate "SHA224 and SHA256 digest algorithm (OCTEON)" + depends on CPU_CAVIUM_OCTEON + select CRYPTO_SHA256 + select CRYPTO_HASH + help + SHA-256 secure hash standard (DFIPS 180-2) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_SHA256_SPARC64 tristate "SHA224 and SHA256 digest algorithm (SPARC64)" depends on SPARC64 @@ -631,6 +649,15 @@ config CRYPTO_SHA512 This code also includes SHA-384, a 384 bit hash with 192 bits of security against collision attacks. +config CRYPTO_SHA512_OCTEON + tristate "SHA384 and SHA512 digest algorithms (OCTEON)" + depends on CPU_CAVIUM_OCTEON + select CRYPTO_SHA512 + select CRYPTO_HASH + help + SHA-512 secure hash standard (DFIPS 180-2) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_SHA512_SPARC64 tristate "SHA384 and SHA512 digest algorithm (SPARC64)" depends on SPARC64 -- 2.2.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] staging: octeon-usb: Made octeon_usb_match const
Hi, On Mon, Mar 09, 2015 at 11:09:03PM +0100, Mateusz Kulikowski wrote: > An of_device_id should be const (checkpatch.pl warning). > > Signed-off-by: Mateusz Kulikowski Acked-by: Aaro Koskinen A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCHv2 0/2] N900 Modem Speech Support
On Wed, Mar 04, 2015 at 08:24:19PM +0100, Pavel Machek wrote:
> @@ -1239,8 +1234,8 @@ static long cs_char_ioctl(struct file *file, unsigned
> int cmd,
>
> if (copy_to_user((void __user *)arg, , sizeof(ifver)))
> r = -EFAULT;
> - break;
> }
> + break;
> case CS_CONFIG_BUFS: {
> struct cs_buffer_config buf_cfg;
>
> @@ -1249,8 +1244,8 @@ static long cs_char_ioctl(struct file *file, unsigned
> int cmd,
> r = -EFAULT;
> else
> r = cs_hsi_buf_config(csdata->hi, _cfg);
> - break;
> }
> + break;
I think having the break inside the block is more readable.
Now the indendation is mess.
A.
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 00/10] omap3 crypto fixes
Hi, On Fri, Mar 06, 2015 at 10:36:32AM -0800, Tony Lindgren wrote: > Are there any fixes in this series that should go into > v4.0-rc series, or can it all wait for v4.1? I think these all should wait for v4.1. A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 00/10] omap3 crypto fixes
Hi, On Fri, Feb 27, 2015 at 01:40:44PM +0100, Pali Rohár wrote: > > However I get these when CONFIG_CRYPTO_MANAGER_DISABLE_TESTS > > is not set: > > > > alg: hash: Chunking test 1 failed for omap-sha1 > > alg: hash: Chunking test 1 failed for omap-md5 > > alg: hash: Chunking test 1 failed for omap-hmac-sha1 > > alg: hash: Chunking test 1 failed for omap-hmac-md5 BTW, it seems these errors are reported to be introduced possibly somewhere between 3.11 and 3.15: https://lists.fedoraproject.org/pipermail/arm/2014-August/008240.html A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] perf: fix building error in x86_64
Hi, On Fri, Feb 13, 2015 at 03:11:14PM +0800, He Kuang wrote: > When build with ARCH=x86_64, perf failed to compile with following error: > > tests/builtin-test.o:(.data+0x158): undefined reference to > `test__perf_time_to_tsc' [...] > +ifeq ($(ARCH), x86_64) > + override ARCH := x86 > +endif The same error happens also with ARCH=i386. So I think both cases should be fixed. A. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: wl1251 & mac address & calibration data
Hi, On Thu, Nov 24, 2016 at 04:20:45PM +0100, Pali Rohár wrote: > Proprietary, signed and closed bootloader NOLO does not support DT. So > for booting you need to append DTS file to kernel image. > > U-Boot is optional and can be used as intermediate bootloader between > NOLO and kernel. But still it has problems with reading from nand, so > cannot read NVS data nor MAC address. You could use kexec to pass the fixed DT. A.
v4.8 cpufreq regression?
Hi, I'm upgrading from v4.7 to v4.8 on MIPS/loongson2_cpufreq with cpufreq/ondemand and I noticed that /proc/cpuinfo is always reporting (regardless of system load): BogoMIPS: 697150.20 and sysfs: /sys/devices/system/cpu/cpufreq/policy0/affected_cpus:0 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq:797800 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_max_freq:797800 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_min_freq:199450 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_transition_latency:0 /sys/devices/system/cpu/cpufreq/policy0/related_cpus:0 /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies:199450 299175 398900 498625 598350 698075 797800 /sys/devices/system/cpu/cpufreq/policy0/scaling_available_governors:ondemand performance /sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:797800 /sys/devices/system/cpu/cpufreq/policy0/scaling_driver:loongson2 /sys/devices/system/cpu/cpufreq/policy0/scaling_governor:ondemand /sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq:797800 /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq:199450 /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed: although previously they reported (when idle): BogoMIPS: 132.09 /sys/devices/system/cpu/cpufreq/policy0/affected_cpus:0 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq:199445 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_max_freq:797780 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_min_freq:199445 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_transition_latency:0 /sys/devices/system/cpu/cpufreq/policy0/related_cpus:0 /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies:199445 299167 398890 498612 598335 698057 797780 /sys/devices/system/cpu/cpufreq/policy0/scaling_available_governors:ondemand performance /sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:199445 /sys/devices/system/cpu/cpufreq/policy0/scaling_driver:loongson2 /sys/devices/system/cpu/cpufreq/policy0/scaling_governor:ondemand /sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq:797780 /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq:199445 /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed: and under full load: BogoMIPS: 528.38 /sys/devices/system/cpu/cpufreq/policy0/affected_cpus:0 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq:797780 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_max_freq:797780 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_min_freq:199445 /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_transition_latency:0 /sys/devices/system/cpu/cpufreq/policy0/related_cpus:0 /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies:199445 299167 398890 498612 598335 698057 797780 /sys/devices/system/cpu/cpufreq/policy0/scaling_available_governors:ondemand performance /sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:797780 /sys/devices/system/cpu/cpufreq/policy0/scaling_driver:loongson2 /sys/devices/system/cpu/cpufreq/policy0/scaling_governor:ondemand /sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq:797780 /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq:199445 /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed: The offeding commit (bisected) seems to be: commit da0c6dc00c69d0adaae99c3b3d2ea0c869a3fb35 Author: Viresh Kumar Date: Mon Jun 27 16:04:07 2016 +0530 cpufreq: Handle sorted frequency tables more efficiently Any ideas? A.
[PATCH 0/9] staging: octeon: multi rx group (queue) support
Hi, This series implements multiple RX group support that should improve the networking performance on multi-core OCTEONs. Basically we register IRQ and NAPI for each group, and ask the HW to select the group for the incoming packets based on hash. Tested on EdgeRouter Lite with a simple forwarding test using two flows and 16 RX groups distributed between two cores - the routing throughput is roughly doubled. A. Aaro Koskinen (9): staging: octeon: disable rx interrupts in oct_rx_shutdown staging: octeon: use passed interrupt number in the handler staging: octeon: pass the NAPI instance reference to irq handler staging: octeon: move common poll code into a separate function staging: octeon: create a struct for rx group specific data staging: octeon: move irq into rx group specific data staging: octeon: move group number into rx group data staging: octeon: support enabling multiple rx groups staging: octeon: enable taking multiple rx groups into use drivers/staging/octeon/ethernet-rx.c | 178 --- drivers/staging/octeon/ethernet.c| 55 -- drivers/staging/octeon/octeon-ethernet.h | 2 +- 3 files changed, 159 insertions(+), 76 deletions(-) -- 2.9.2
[PATCH 3/9] staging: octeon: pass the NAPI instance reference to irq handler
Pass the NAPI instance reference to the interrupt handler.
This is preparation for having multiple NAPI instances.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 808c415..27e3459 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -48,16 +48,16 @@ static struct napi_struct cvm_oct_napi;
/**
* cvm_oct_do_interrupt - interrupt handler.
* @irq: Interrupt number.
- * @dev_id: Cookie to identify the device. Unused
+ * @napi_id: Cookie to identify the NAPI instance.
*
* The interrupt occurs whenever the POW has packets in our group.
*
*/
-static irqreturn_t cvm_oct_do_interrupt(int irq, void *dev_id)
+static irqreturn_t cvm_oct_do_interrupt(int irq, void *napi_id)
{
/* Disable the IRQ and start napi_poll. */
disable_irq_nosync(irq);
- napi_schedule(_oct_napi);
+ napi_schedule(napi_id);
return IRQ_HANDLED;
}
@@ -452,7 +452,7 @@ void cvm_oct_rx_initialize(void)
/* Register an IRQ handler to receive POW interrupts */
i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
- cvm_oct_do_interrupt, 0, "Ethernet", cvm_oct_device);
+ cvm_oct_do_interrupt, 0, "Ethernet", _oct_napi);
if (i)
panic("Could not acquire Ethernet IRQ %d\n",
--
2.9.2
[PATCH 4/9] staging: octeon: move common poll code into a separate function
Move common poll code into a separate function.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 27e3459..140e8af 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -143,14 +143,7 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
return 0;
}
-/**
- * cvm_oct_napi_poll - the NAPI poll function.
- * @napi: The NAPI instance, or null if called from cvm_oct_poll_controller
- * @budget: Maximum number of packets to receive.
- *
- * Returns the number of packets processed.
- */
-static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
+static int cvm_oct_poll(int budget)
{
const int coreid = cvmx_get_core_num();
u64 old_group_mask;
@@ -410,7 +403,23 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
}
cvm_oct_rx_refill_pool(0);
- if (rx_count < budget && napi) {
+ return rx_count;
+}
+
+/**
+ * cvm_oct_napi_poll - the NAPI poll function.
+ * @napi: The NAPI instance.
+ * @budget: Maximum number of packets to receive.
+ *
+ * Returns the number of packets processed.
+ */
+static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
+{
+ int rx_count;
+
+ rx_count = cvm_oct_poll(budget);
+
+ if (rx_count < budget) {
/* No more work */
napi_complete(napi);
enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
@@ -427,7 +436,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
*/
void cvm_oct_poll_controller(struct net_device *dev)
{
- cvm_oct_napi_poll(NULL, 16);
+ cvm_oct_poll(16);
}
#endif
--
2.9.2
[PATCH 1/9] staging: octeon: disable rx interrupts in oct_rx_shutdown
Disable RX interrupts in oct_rx_shutdown(). This way we don't need to
expose the RX IRQ numbers outside the RX module.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 9 +
drivers/staging/octeon/ethernet.c| 9 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index a10fe3a..5b26f2a 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -495,5 +495,14 @@ void cvm_oct_rx_initialize(void)
void cvm_oct_rx_shutdown(void)
{
+ /* Disable POW interrupt */
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group), 0);
+ else
+ cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
+
+ /* Free the interrupt handler */
+ free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
+
netif_napi_del(_oct_napi);
}
diff --git a/drivers/staging/octeon/ethernet.c
b/drivers/staging/octeon/ethernet.c
index 073a1e3..1e2e1ef 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -853,17 +853,8 @@ static int cvm_oct_remove(struct platform_device *pdev)
{
int port;
- /* Disable POW interrupt */
- if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group), 0);
- else
- cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
-
cvmx_ipd_disable();
- /* Free the interrupt handler */
- free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
-
atomic_inc_return(_oct_poll_queue_stopping);
cancel_delayed_work_sync(_oct_rx_refill_work);
--
2.9.2
[PATCH 9/9] staging: octeon: enable taking multiple rx groups into use
Enable taking multiple RX groups into use.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet.c | 42 +--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/octeon/ethernet.c
b/drivers/staging/octeon/ethernet.c
index 7d48745..c1d0cfd 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -53,6 +53,15 @@ MODULE_PARM_DESC(pow_receive_group, "\n"
"\tgroup. Also any other software can submit packets to this\n"
"\tgroup for the kernel to process.");
+static int receive_group_order;
+module_param(receive_group_order, int, 0444);
+MODULE_PARM_DESC(receive_group_order, "\n"
+ "\tOrder (0..4) of receive groups to take into use. Ethernet hardware\n"
+ "\twill be configured to send incoming packets to multiple POW\n"
+ "\tgroups. pow_receive_group parameter is ignored when multiple\n"
+ "\tgroups are taken into use and groups are allocated starting\n"
+ "\tfrom 0. By default, a single group is used.\n");
+
int pow_send_group = -1;
module_param(pow_send_group, int, 0644);
MODULE_PARM_DESC(pow_send_group, "\n"
@@ -680,7 +689,13 @@ static int cvm_oct_probe(struct platform_device *pdev)
cvmx_helper_initialize_packet_io_global();
- pow_receive_groups = BIT(pow_receive_group);
+ if (receive_group_order) {
+ if (receive_group_order > 4)
+ receive_group_order = 4;
+ pow_receive_groups = (1 << (1 << receive_group_order)) - 1;
+ } else {
+ pow_receive_groups = BIT(pow_receive_group);
+ }
/* Change the input group for all ports before input is enabled */
num_interfaces = cvmx_helper_get_number_of_interfaces();
@@ -695,7 +710,30 @@ static int cvm_oct_probe(struct platform_device *pdev)
pip_prt_tagx.u64 =
cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
- pip_prt_tagx.s.grp = pow_receive_group;
+
+ if (receive_group_order) {
+ int tag_mask;
+
+ tag_mask = ~((1 << receive_group_order) - 1);
+ pip_prt_tagx.s.grptagbase = 0;
+ pip_prt_tagx.s.grptagmask = tag_mask;
+ pip_prt_tagx.s.grptag = 1;
+ pip_prt_tagx.s.tag_mode = 0;
+ pip_prt_tagx.s.inc_prt_flag = 1;
+ pip_prt_tagx.s.ip6_dprt_flag= 1;
+ pip_prt_tagx.s.ip4_dprt_flag= 1;
+ pip_prt_tagx.s.ip6_sprt_flag= 1;
+ pip_prt_tagx.s.ip4_sprt_flag= 1;
+ pip_prt_tagx.s.ip6_dst_flag = 1;
+ pip_prt_tagx.s.ip4_dst_flag = 1;
+ pip_prt_tagx.s.ip6_src_flag = 1;
+ pip_prt_tagx.s.ip4_src_flag = 1;
+ pip_prt_tagx.s.grp = 0;
+ } else {
+ pip_prt_tagx.s.grptag = 0;
+ pip_prt_tagx.s.grp = pow_receive_group;
+ }
+
cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
pip_prt_tagx.u64);
}
--
2.9.2
[PATCH 2/9] staging: octeon: use passed interrupt number in the handler
Use passed interrupt number in the handler, so we can avoid using
the global variable.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 5b26f2a..808c415 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -47,16 +47,16 @@ static struct napi_struct cvm_oct_napi;
/**
* cvm_oct_do_interrupt - interrupt handler.
- * @cpl: Interrupt number. Unused
+ * @irq: Interrupt number.
* @dev_id: Cookie to identify the device. Unused
*
* The interrupt occurs whenever the POW has packets in our group.
*
*/
-static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id)
+static irqreturn_t cvm_oct_do_interrupt(int irq, void *dev_id)
{
/* Disable the IRQ and start napi_poll. */
- disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ disable_irq_nosync(irq);
napi_schedule(_oct_napi);
return IRQ_HANDLED;
--
2.9.2
[PATCH 5/9] staging: octeon: create a struct for rx group specific data
Create a struct for RX group specific data.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 140e8af..65f6013 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -43,7 +43,9 @@
#include
-static struct napi_struct cvm_oct_napi;
+static struct oct_rx_group {
+ struct napi_struct napi;
+} oct_rx_group;
/**
* cvm_oct_do_interrupt - interrupt handler.
@@ -455,13 +457,14 @@ void cvm_oct_rx_initialize(void)
if (!dev_for_napi)
panic("No net_devices were allocated.");
- netif_napi_add(dev_for_napi, _oct_napi, cvm_oct_napi_poll,
+ netif_napi_add(dev_for_napi, _rx_group.napi, cvm_oct_napi_poll,
rx_napi_weight);
- napi_enable(_oct_napi);
+ napi_enable(_rx_group.napi);
/* Register an IRQ handler to receive POW interrupts */
i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
- cvm_oct_do_interrupt, 0, "Ethernet", _oct_napi);
+ cvm_oct_do_interrupt, 0, "Ethernet",
+ _rx_group.napi);
if (i)
panic("Could not acquire Ethernet IRQ %d\n",
@@ -499,7 +502,7 @@ void cvm_oct_rx_initialize(void)
}
/* Schedule NAPI now. This will indirectly enable the interrupt. */
- napi_schedule(_oct_napi);
+ napi_schedule(_rx_group.napi);
}
void cvm_oct_rx_shutdown(void)
@@ -513,5 +516,5 @@ void cvm_oct_rx_shutdown(void)
/* Free the interrupt handler */
free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
- netif_napi_del(_oct_napi);
+ netif_napi_del(_rx_group.napi);
}
--
2.9.2
[PATCH 6/9] staging: octeon: move irq into rx group specific data
Move IRQ number into RX group specific data.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 65f6013..776003c 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -44,6 +44,7 @@
#include
static struct oct_rx_group {
+ int irq;
struct napi_struct napi;
} oct_rx_group;
@@ -417,6 +418,8 @@ static int cvm_oct_poll(int budget)
*/
static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
{
+ struct oct_rx_group *rx_group = container_of(napi, struct oct_rx_group,
+napi);
int rx_count;
rx_count = cvm_oct_poll(budget);
@@ -424,7 +427,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
if (rx_count < budget) {
/* No more work */
napi_complete(napi);
- enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ enable_irq(rx_group->irq);
}
return rx_count;
}
@@ -461,16 +464,16 @@ void cvm_oct_rx_initialize(void)
rx_napi_weight);
napi_enable(_rx_group.napi);
+ oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
+
/* Register an IRQ handler to receive POW interrupts */
- i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
- cvm_oct_do_interrupt, 0, "Ethernet",
+ i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
_rx_group.napi);
if (i)
- panic("Could not acquire Ethernet IRQ %d\n",
- OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ panic("Could not acquire Ethernet IRQ %d\n", oct_rx_group.irq);
- disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ disable_irq_nosync(oct_rx_group.irq);
/* Enable POW interrupt when our port has at least one packet */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -514,7 +517,7 @@ void cvm_oct_rx_shutdown(void)
cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
/* Free the interrupt handler */
- free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
+ free_irq(oct_rx_group.irq, cvm_oct_device);
netif_napi_del(_rx_group.napi);
}
--
2.9.2
[PATCH 7/9] staging: octeon: move group number into rx group data
Move group number into RX group data.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 776003c..668aee6 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -45,6 +45,7 @@
static struct oct_rx_group {
int irq;
+ int group;
struct napi_struct napi;
} oct_rx_group;
@@ -146,7 +147,7 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
return 0;
}
-static int cvm_oct_poll(int budget)
+static int cvm_oct_poll(struct oct_rx_group *rx_group, int budget)
{
const int coreid = cvmx_get_core_num();
u64 old_group_mask;
@@ -168,13 +169,13 @@ static int cvm_oct_poll(int budget)
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid));
cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid),
- 1ull << pow_receive_group);
+ BIT(rx_group->group));
cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */
} else {
old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
(old_group_mask & ~0xull) |
- 1 << pow_receive_group);
+ BIT(rx_group->group));
}
if (USE_ASYNC_IOBDMA) {
@@ -199,15 +200,15 @@ static int cvm_oct_poll(int budget)
if (!work) {
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
cvmx_write_csr(CVMX_SSO_WQ_IQ_DIS,
- 1ull << pow_receive_group);
+ BIT(rx_group->group));
cvmx_write_csr(CVMX_SSO_WQ_INT,
- 1ull << pow_receive_group);
+ BIT(rx_group->group));
} else {
union cvmx_pow_wq_int wq_int;
wq_int.u64 = 0;
- wq_int.s.iq_dis = 1 << pow_receive_group;
- wq_int.s.wq_int = 1 << pow_receive_group;
+ wq_int.s.iq_dis = BIT(rx_group->group);
+ wq_int.s.wq_int = BIT(rx_group->group);
cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);
}
break;
@@ -422,7 +423,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
napi);
int rx_count;
- rx_count = cvm_oct_poll(budget);
+ rx_count = cvm_oct_poll(rx_group, budget);
if (rx_count < budget) {
/* No more work */
@@ -441,7 +442,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
*/
void cvm_oct_poll_controller(struct net_device *dev)
{
- cvm_oct_poll(16);
+ cvm_oct_poll(oct_rx_group, 16);
}
#endif
@@ -465,6 +466,7 @@ void cvm_oct_rx_initialize(void)
napi_enable(_rx_group.napi);
oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
+ oct_rx_group.group = pow_receive_group;
/* Register an IRQ handler to receive POW interrupts */
i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
--
2.9.2
[PATCH 8/9] staging: octeon: support enabling multiple rx groups
Support enabling multiple RX groups.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 126 ++-
drivers/staging/octeon/ethernet.c| 6 +-
drivers/staging/octeon/octeon-ethernet.h | 2 +-
3 files changed, 81 insertions(+), 53 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 668aee6..407020f 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -47,7 +47,7 @@ static struct oct_rx_group {
int irq;
int group;
struct napi_struct napi;
-} oct_rx_group;
+} oct_rx_group[16];
/**
* cvm_oct_do_interrupt - interrupt handler.
@@ -442,7 +442,16 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
*/
void cvm_oct_poll_controller(struct net_device *dev)
{
- cvm_oct_poll(oct_rx_group, 16);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
+
+ if (!(pow_receive_groups & BIT(i)))
+ continue;
+
+ cvm_oct_poll(oct_rx_group[i], 16);
+
+ }
}
#endif
@@ -461,65 +470,80 @@ void cvm_oct_rx_initialize(void)
if (!dev_for_napi)
panic("No net_devices were allocated.");
- netif_napi_add(dev_for_napi, _rx_group.napi, cvm_oct_napi_poll,
- rx_napi_weight);
- napi_enable(_rx_group.napi);
+ for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
+ int ret;
- oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
- oct_rx_group.group = pow_receive_group;
+ if (!(pow_receive_groups & BIT(i)))
+ continue;
- /* Register an IRQ handler to receive POW interrupts */
- i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
- _rx_group.napi);
+ netif_napi_add(dev_for_napi, _rx_group[i].napi,
+ cvm_oct_napi_poll, rx_napi_weight);
+ napi_enable(_rx_group[i].napi);
- if (i)
- panic("Could not acquire Ethernet IRQ %d\n", oct_rx_group.irq);
+ oct_rx_group[i].irq = OCTEON_IRQ_WORKQ0 + i;
+ oct_rx_group[i].group = i;
- disable_irq_nosync(oct_rx_group.irq);
+ /* Register an IRQ handler to receive POW interrupts */
+ ret = request_irq(oct_rx_group[i].irq, cvm_oct_do_interrupt, 0,
+ "Ethernet", _rx_group[i].napi);
+ if (ret)
+ panic("Could not acquire Ethernet IRQ %d\n",
+ oct_rx_group[i].irq);
- /* Enable POW interrupt when our port has at least one packet */
- if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
- union cvmx_sso_wq_int_thrx int_thr;
- union cvmx_pow_wq_int_pc int_pc;
-
- int_thr.u64 = 0;
- int_thr.s.tc_en = 1;
- int_thr.s.tc_thr = 1;
- cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group),
- int_thr.u64);
-
- int_pc.u64 = 0;
- int_pc.s.pc_thr = 5;
- cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
- } else {
- union cvmx_pow_wq_int_thrx int_thr;
- union cvmx_pow_wq_int_pc int_pc;
-
- int_thr.u64 = 0;
- int_thr.s.tc_en = 1;
- int_thr.s.tc_thr = 1;
- cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group),
- int_thr.u64);
-
- int_pc.u64 = 0;
- int_pc.s.pc_thr = 5;
- cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
- }
+ disable_irq_nosync(oct_rx_group[i].irq);
+
+ /* Enable POW interrupt when our port has at least one packet */
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ union cvmx_sso_wq_int_thrx int_thr;
+ union cvmx_pow_wq_int_pc int_pc;
+
+ int_thr.u64 = 0;
+ int_thr.s.tc_en = 1;
+ int_thr.s.tc_thr = 1;
+ cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64);
+
+ int_pc.u64 = 0;
+ int_pc.s.pc_thr = 5;
+ cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
+ } else {
+ union cvmx_pow_wq_int_thrx int_thr;
+ union cvmx_pow_wq_int_pc int_pc;
- /* Schedule NAPI now. This will indirectly enable the interrupt. */
- napi_schedule(_rx_group.napi);
+ int_thr.u64 = 0;
+ int_thr.s.tc_en = 1;
+ int_thr.s.tc_thr = 1;
+ cvmx_write_csr(CVMX_POW_WQ_INT
Re: [PATCH 0/9] staging: octeon: multi rx group (queue) support
Hi, On Tue, Aug 30, 2016 at 06:12:17PM -0700, Ed Swierk wrote: > On Tue, Aug 30, 2016 at 11:47 AM, Aaro Koskinen wrote: > > This series implements multiple RX group support that should improve > > the networking performance on multi-core OCTEONs. Basically we register > > IRQ and NAPI for each group, and ask the HW to select the group for > > the incoming packets based on hash. > > > > Tested on EdgeRouter Lite with a simple forwarding test using two flows > > and 16 RX groups distributed between two cores - the routing throughput > > is roughly doubled. > > I applied the series to my 4.4.19 tree, which involved backporting a > bunch of other patches from master, most of them trivial. > > When I test it on a Cavium Octeon 2 (CN6880) board, I get an immediate > crash (bus error) in the netif_receive_skb() call from cvm_oct_poll(). > Replacing the rx_group argument to cvm_oct_poll() with int group, and > dereferencing rx_group->group in the caller (cvm_oct_napi_poll()) > instead makes the crash disappear. Apparently there's some race in > dereferencing rx_group from within cvm_oct_poll(). Oops, looks like I tested without CONFIG_NET_POLL_CONTROLLER enabled and that seems to be broken. Sorry. > With this workaround in place, I can send and receive on XAUI > interfaces, but don't see any performance improvement. I'm guessing I > need to set receive_group_order > 0. But any value between 1 and 4 > seems to break rx altogether. When I ping another host I see both > request and response on the wire, and the interface counters increase, > but the response doesn't make it back to ping. Can you see multiple ethernet IRQs in /proc/interrupts and their counters increasing? With receive_group_order=4 you should see 16 IRQs. > Is some other configuration needed to make use of multiple rx groups? Once RX interrupts are working you need to divide them to multiple cores using /proc/irq//smp_affinity, or use irqbalance or such. A.
Re: [PATCH 0/9] staging: octeon: multi rx group (queue) support
Hi, On Tue, Aug 30, 2016 at 06:12:17PM -0700, Ed Swierk wrote: > On Tue, Aug 30, 2016 at 11:47 AM, Aaro Koskinen wrote: > > This series implements multiple RX group support that should improve > > the networking performance on multi-core OCTEONs. Basically we register > > IRQ and NAPI for each group, and ask the HW to select the group for > > the incoming packets based on hash. > > > > Tested on EdgeRouter Lite with a simple forwarding test using two flows > > and 16 RX groups distributed between two cores - the routing throughput > > is roughly doubled. > > I applied the series to my 4.4.19 tree, which involved backporting a > bunch of other patches from master, most of them trivial. > > When I test it on a Cavium Octeon 2 (CN6880) board, I get an immediate > crash (bus error) in the netif_receive_skb() call from cvm_oct_poll(). > Replacing the rx_group argument to cvm_oct_poll() with int group, and > dereferencing rx_group->group in the caller (cvm_oct_napi_poll()) > instead makes the crash disappear. Apparently there's some race in > dereferencing rx_group from within cvm_oct_poll(). > > With this workaround in place, I can send and receive on XAUI > interfaces, but don't see any performance improvement. I'm guessing I > need to set receive_group_order > 0. But any value between 1 and 4 > seems to break rx altogether. When I ping another host I see both > request and response on the wire, and the interface counters increase, > but the response doesn't make it back to ping. This happens only on CN68XX, and I found the root cause. I will send a new series later today. A.
[PATCH v2 00/11] staging: octeon: multi rx group (queue) support
Hi, This series implements multiple RX group support that should improve the networking performance on multi-core OCTEONs. Basically we register IRQ and NAPI for each group, and ask the HW to select the group for the incoming packets based on hash. Tested on EdgeRouter Lite with a simple forwarding test using two flows and 16 RX groups distributed between two cores - the routing throughput is roughly doubled. Also tested with EBH5600 (8 cores) and EBB6800 (16 cores) by sending and receiving traffic in both directions using SGMII interfaces. A. v2: - Fix build failure with CONFIG_NET_POLL_CONSOLE. - Disable the extended group tag mask bits on CN68XX. - Set up PKND for all interfaces. - Don't allow poll before RX init is completed. v1: http://marc.info/?t=14725829975=1=2 Aaro Koskinen (11): staging: octeon: disable rx interrupts in oct_rx_shutdown staging: octeon: use passed interrupt number in the handler staging: octeon: pass the NAPI instance reference to irq handler staging: octeon: move common poll code into a separate function staging: octeon: create a struct for rx group specific data staging: octeon: move irq into rx group specific data staging: octeon: move group number into rx group data staging: octeon: support enabling multiple rx groups staging: octeon: enable taking multiple rx groups into use staging: octeon: set up pknd for all interfaces staging: octeon: prevent poll during rx init drivers/staging/octeon/ethernet-rx.c | 184 --- drivers/staging/octeon/ethernet.c| 64 +-- drivers/staging/octeon/octeon-ethernet.h | 2 +- 3 files changed, 174 insertions(+), 76 deletions(-) -- 2.9.2
[PATCH v2 06/11] staging: octeon: move irq into rx group specific data
Move IRQ number into RX group specific data.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 65f6013..776003c 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -44,6 +44,7 @@
#include
static struct oct_rx_group {
+ int irq;
struct napi_struct napi;
} oct_rx_group;
@@ -417,6 +418,8 @@ static int cvm_oct_poll(int budget)
*/
static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
{
+ struct oct_rx_group *rx_group = container_of(napi, struct oct_rx_group,
+napi);
int rx_count;
rx_count = cvm_oct_poll(budget);
@@ -424,7 +427,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
if (rx_count < budget) {
/* No more work */
napi_complete(napi);
- enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ enable_irq(rx_group->irq);
}
return rx_count;
}
@@ -461,16 +464,16 @@ void cvm_oct_rx_initialize(void)
rx_napi_weight);
napi_enable(_rx_group.napi);
+ oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
+
/* Register an IRQ handler to receive POW interrupts */
- i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
- cvm_oct_do_interrupt, 0, "Ethernet",
+ i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
_rx_group.napi);
if (i)
- panic("Could not acquire Ethernet IRQ %d\n",
- OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ panic("Could not acquire Ethernet IRQ %d\n", oct_rx_group.irq);
- disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ disable_irq_nosync(oct_rx_group.irq);
/* Enable POW interrupt when our port has at least one packet */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -514,7 +517,7 @@ void cvm_oct_rx_shutdown(void)
cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
/* Free the interrupt handler */
- free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
+ free_irq(oct_rx_group.irq, cvm_oct_device);
netif_napi_del(_rx_group.napi);
}
--
2.9.2
[PATCH v2 05/11] staging: octeon: create a struct for rx group specific data
Create a struct for RX group specific data.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 140e8af..65f6013 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -43,7 +43,9 @@
#include
-static struct napi_struct cvm_oct_napi;
+static struct oct_rx_group {
+ struct napi_struct napi;
+} oct_rx_group;
/**
* cvm_oct_do_interrupt - interrupt handler.
@@ -455,13 +457,14 @@ void cvm_oct_rx_initialize(void)
if (!dev_for_napi)
panic("No net_devices were allocated.");
- netif_napi_add(dev_for_napi, _oct_napi, cvm_oct_napi_poll,
+ netif_napi_add(dev_for_napi, _rx_group.napi, cvm_oct_napi_poll,
rx_napi_weight);
- napi_enable(_oct_napi);
+ napi_enable(_rx_group.napi);
/* Register an IRQ handler to receive POW interrupts */
i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
- cvm_oct_do_interrupt, 0, "Ethernet", _oct_napi);
+ cvm_oct_do_interrupt, 0, "Ethernet",
+ _rx_group.napi);
if (i)
panic("Could not acquire Ethernet IRQ %d\n",
@@ -499,7 +502,7 @@ void cvm_oct_rx_initialize(void)
}
/* Schedule NAPI now. This will indirectly enable the interrupt. */
- napi_schedule(_oct_napi);
+ napi_schedule(_rx_group.napi);
}
void cvm_oct_rx_shutdown(void)
@@ -513,5 +516,5 @@ void cvm_oct_rx_shutdown(void)
/* Free the interrupt handler */
free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
- netif_napi_del(_oct_napi);
+ netif_napi_del(_rx_group.napi);
}
--
2.9.2
[PATCH v2 09/11] staging: octeon: enable taking multiple rx groups into use
Enable taking multiple RX groups into use.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet.c | 49 +--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/octeon/ethernet.c
b/drivers/staging/octeon/ethernet.c
index 7d48745..8d51f05 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -53,6 +53,15 @@ MODULE_PARM_DESC(pow_receive_group, "\n"
"\tgroup. Also any other software can submit packets to this\n"
"\tgroup for the kernel to process.");
+static int receive_group_order;
+module_param(receive_group_order, int, 0444);
+MODULE_PARM_DESC(receive_group_order, "\n"
+ "\tOrder (0..4) of receive groups to take into use. Ethernet hardware\n"
+ "\twill be configured to send incoming packets to multiple POW\n"
+ "\tgroups. pow_receive_group parameter is ignored when multiple\n"
+ "\tgroups are taken into use and groups are allocated starting\n"
+ "\tfrom 0. By default, a single group is used.\n");
+
int pow_send_group = -1;
module_param(pow_send_group, int, 0644);
MODULE_PARM_DESC(pow_send_group, "\n"
@@ -680,7 +689,13 @@ static int cvm_oct_probe(struct platform_device *pdev)
cvmx_helper_initialize_packet_io_global();
- pow_receive_groups = BIT(pow_receive_group);
+ if (receive_group_order) {
+ if (receive_group_order > 4)
+ receive_group_order = 4;
+ pow_receive_groups = (1 << (1 << receive_group_order)) - 1;
+ } else {
+ pow_receive_groups = BIT(pow_receive_group);
+ }
/* Change the input group for all ports before input is enabled */
num_interfaces = cvmx_helper_get_number_of_interfaces();
@@ -695,7 +710,37 @@ static int cvm_oct_probe(struct platform_device *pdev)
pip_prt_tagx.u64 =
cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
- pip_prt_tagx.s.grp = pow_receive_group;
+
+ if (receive_group_order) {
+ int tag_mask;
+
+ /* We support only 16 groups at the moment, so
+* always disable the two additional "hidden"
+* tag_mask bits on CN68XX.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ pip_prt_tagx.u64 |= 0x3ull << 44;
+
+ tag_mask = ~((1 << receive_group_order) - 1);
+ pip_prt_tagx.s.grptagbase = 0;
+ pip_prt_tagx.s.grptagmask = tag_mask;
+ pip_prt_tagx.s.grptag = 1;
+ pip_prt_tagx.s.tag_mode = 0;
+ pip_prt_tagx.s.inc_prt_flag = 1;
+ pip_prt_tagx.s.ip6_dprt_flag= 1;
+ pip_prt_tagx.s.ip4_dprt_flag= 1;
+ pip_prt_tagx.s.ip6_sprt_flag= 1;
+ pip_prt_tagx.s.ip4_sprt_flag= 1;
+ pip_prt_tagx.s.ip6_dst_flag = 1;
+ pip_prt_tagx.s.ip4_dst_flag = 1;
+ pip_prt_tagx.s.ip6_src_flag = 1;
+ pip_prt_tagx.s.ip4_src_flag = 1;
+ pip_prt_tagx.s.grp = 0;
+ } else {
+ pip_prt_tagx.s.grptag = 0;
+ pip_prt_tagx.s.grp = pow_receive_group;
+ }
+
cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
pip_prt_tagx.u64);
}
--
2.9.2
[PATCH v2 02/11] staging: octeon: use passed interrupt number in the handler
Use passed interrupt number in the handler, so we can avoid using
the global variable.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 5b26f2a..808c415 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -47,16 +47,16 @@ static struct napi_struct cvm_oct_napi;
/**
* cvm_oct_do_interrupt - interrupt handler.
- * @cpl: Interrupt number. Unused
+ * @irq: Interrupt number.
* @dev_id: Cookie to identify the device. Unused
*
* The interrupt occurs whenever the POW has packets in our group.
*
*/
-static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id)
+static irqreturn_t cvm_oct_do_interrupt(int irq, void *dev_id)
{
/* Disable the IRQ and start napi_poll. */
- disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
+ disable_irq_nosync(irq);
napi_schedule(_oct_napi);
return IRQ_HANDLED;
--
2.9.2
[PATCH v2 03/11] staging: octeon: pass the NAPI instance reference to irq handler
Pass the NAPI instance reference to the interrupt handler.
This is preparation for having multiple NAPI instances.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 808c415..27e3459 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -48,16 +48,16 @@ static struct napi_struct cvm_oct_napi;
/**
* cvm_oct_do_interrupt - interrupt handler.
* @irq: Interrupt number.
- * @dev_id: Cookie to identify the device. Unused
+ * @napi_id: Cookie to identify the NAPI instance.
*
* The interrupt occurs whenever the POW has packets in our group.
*
*/
-static irqreturn_t cvm_oct_do_interrupt(int irq, void *dev_id)
+static irqreturn_t cvm_oct_do_interrupt(int irq, void *napi_id)
{
/* Disable the IRQ and start napi_poll. */
disable_irq_nosync(irq);
- napi_schedule(_oct_napi);
+ napi_schedule(napi_id);
return IRQ_HANDLED;
}
@@ -452,7 +452,7 @@ void cvm_oct_rx_initialize(void)
/* Register an IRQ handler to receive POW interrupts */
i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
- cvm_oct_do_interrupt, 0, "Ethernet", cvm_oct_device);
+ cvm_oct_do_interrupt, 0, "Ethernet", _oct_napi);
if (i)
panic("Could not acquire Ethernet IRQ %d\n",
--
2.9.2
[PATCH v2 04/11] staging: octeon: move common poll code into a separate function
Move common poll code into a separate function.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 27e3459..140e8af 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -143,14 +143,7 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
return 0;
}
-/**
- * cvm_oct_napi_poll - the NAPI poll function.
- * @napi: The NAPI instance, or null if called from cvm_oct_poll_controller
- * @budget: Maximum number of packets to receive.
- *
- * Returns the number of packets processed.
- */
-static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
+static int cvm_oct_poll(int budget)
{
const int coreid = cvmx_get_core_num();
u64 old_group_mask;
@@ -410,7 +403,23 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
}
cvm_oct_rx_refill_pool(0);
- if (rx_count < budget && napi) {
+ return rx_count;
+}
+
+/**
+ * cvm_oct_napi_poll - the NAPI poll function.
+ * @napi: The NAPI instance.
+ * @budget: Maximum number of packets to receive.
+ *
+ * Returns the number of packets processed.
+ */
+static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
+{
+ int rx_count;
+
+ rx_count = cvm_oct_poll(budget);
+
+ if (rx_count < budget) {
/* No more work */
napi_complete(napi);
enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
@@ -427,7 +436,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
*/
void cvm_oct_poll_controller(struct net_device *dev)
{
- cvm_oct_napi_poll(NULL, 16);
+ cvm_oct_poll(16);
}
#endif
--
2.9.2
[PATCH v2 07/11] staging: octeon: move group number into rx group data
Move group number into RX group data.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 776003c..80d5f24 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -45,6 +45,7 @@
static struct oct_rx_group {
int irq;
+ int group;
struct napi_struct napi;
} oct_rx_group;
@@ -146,7 +147,7 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
return 0;
}
-static int cvm_oct_poll(int budget)
+static int cvm_oct_poll(struct oct_rx_group *rx_group, int budget)
{
const int coreid = cvmx_get_core_num();
u64 old_group_mask;
@@ -168,13 +169,13 @@ static int cvm_oct_poll(int budget)
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid));
cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid),
- 1ull << pow_receive_group);
+ BIT(rx_group->group));
cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */
} else {
old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
(old_group_mask & ~0xull) |
- 1 << pow_receive_group);
+ BIT(rx_group->group));
}
if (USE_ASYNC_IOBDMA) {
@@ -199,15 +200,15 @@ static int cvm_oct_poll(int budget)
if (!work) {
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
cvmx_write_csr(CVMX_SSO_WQ_IQ_DIS,
- 1ull << pow_receive_group);
+ BIT(rx_group->group));
cvmx_write_csr(CVMX_SSO_WQ_INT,
- 1ull << pow_receive_group);
+ BIT(rx_group->group));
} else {
union cvmx_pow_wq_int wq_int;
wq_int.u64 = 0;
- wq_int.s.iq_dis = 1 << pow_receive_group;
- wq_int.s.wq_int = 1 << pow_receive_group;
+ wq_int.s.iq_dis = BIT(rx_group->group);
+ wq_int.s.wq_int = BIT(rx_group->group);
cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);
}
break;
@@ -422,7 +423,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
napi);
int rx_count;
- rx_count = cvm_oct_poll(budget);
+ rx_count = cvm_oct_poll(rx_group, budget);
if (rx_count < budget) {
/* No more work */
@@ -441,7 +442,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
*/
void cvm_oct_poll_controller(struct net_device *dev)
{
- cvm_oct_poll(16);
+ cvm_oct_poll(_rx_group, 16);
}
#endif
@@ -465,6 +466,7 @@ void cvm_oct_rx_initialize(void)
napi_enable(_rx_group.napi);
oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
+ oct_rx_group.group = pow_receive_group;
/* Register an IRQ handler to receive POW interrupts */
i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
--
2.9.2
[PATCH v2 10/11] staging: octeon: set up pknd for all interfaces
RX path uses pknd to find the correct device, and we maintain 1:1 port to pknd mapping. However, this is only set for XAUI interfaces (in the arch code). But it should be set for all interface types. Signed-off-by: Aaro Koskinen --- drivers/staging/octeon/ethernet.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 8d51f05..5497fac 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -488,6 +488,8 @@ int cvm_oct_common_open(struct net_device *dev, gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); gmx_cfg.s.en = 1; + if (octeon_has_feature(OCTEON_FEATURE_PKND)) + gmx_cfg.s.pknd = priv->port; cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); if (octeon_is_simulation()) -- 2.9.2
[PATCH v2 08/11] staging: octeon: support enabling multiple rx groups
Support enabling multiple RX groups.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 126 ++-
drivers/staging/octeon/ethernet.c| 6 +-
drivers/staging/octeon/octeon-ethernet.h | 2 +-
3 files changed, 81 insertions(+), 53 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 80d5f24..4f32fa3 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -47,7 +47,7 @@ static struct oct_rx_group {
int irq;
int group;
struct napi_struct napi;
-} oct_rx_group;
+} oct_rx_group[16];
/**
* cvm_oct_do_interrupt - interrupt handler.
@@ -442,7 +442,16 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int
budget)
*/
void cvm_oct_poll_controller(struct net_device *dev)
{
- cvm_oct_poll(_rx_group, 16);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
+
+ if (!(pow_receive_groups & BIT(i)))
+ continue;
+
+ cvm_oct_poll(_rx_group[i], 16);
+
+ }
}
#endif
@@ -461,65 +470,80 @@ void cvm_oct_rx_initialize(void)
if (!dev_for_napi)
panic("No net_devices were allocated.");
- netif_napi_add(dev_for_napi, _rx_group.napi, cvm_oct_napi_poll,
- rx_napi_weight);
- napi_enable(_rx_group.napi);
+ for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
+ int ret;
- oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
- oct_rx_group.group = pow_receive_group;
+ if (!(pow_receive_groups & BIT(i)))
+ continue;
- /* Register an IRQ handler to receive POW interrupts */
- i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
- _rx_group.napi);
+ netif_napi_add(dev_for_napi, _rx_group[i].napi,
+ cvm_oct_napi_poll, rx_napi_weight);
+ napi_enable(_rx_group[i].napi);
- if (i)
- panic("Could not acquire Ethernet IRQ %d\n", oct_rx_group.irq);
+ oct_rx_group[i].irq = OCTEON_IRQ_WORKQ0 + i;
+ oct_rx_group[i].group = i;
- disable_irq_nosync(oct_rx_group.irq);
+ /* Register an IRQ handler to receive POW interrupts */
+ ret = request_irq(oct_rx_group[i].irq, cvm_oct_do_interrupt, 0,
+ "Ethernet", _rx_group[i].napi);
+ if (ret)
+ panic("Could not acquire Ethernet IRQ %d\n",
+ oct_rx_group[i].irq);
- /* Enable POW interrupt when our port has at least one packet */
- if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
- union cvmx_sso_wq_int_thrx int_thr;
- union cvmx_pow_wq_int_pc int_pc;
-
- int_thr.u64 = 0;
- int_thr.s.tc_en = 1;
- int_thr.s.tc_thr = 1;
- cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group),
- int_thr.u64);
-
- int_pc.u64 = 0;
- int_pc.s.pc_thr = 5;
- cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
- } else {
- union cvmx_pow_wq_int_thrx int_thr;
- union cvmx_pow_wq_int_pc int_pc;
-
- int_thr.u64 = 0;
- int_thr.s.tc_en = 1;
- int_thr.s.tc_thr = 1;
- cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group),
- int_thr.u64);
-
- int_pc.u64 = 0;
- int_pc.s.pc_thr = 5;
- cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
- }
+ disable_irq_nosync(oct_rx_group[i].irq);
+
+ /* Enable POW interrupt when our port has at least one packet */
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ union cvmx_sso_wq_int_thrx int_thr;
+ union cvmx_pow_wq_int_pc int_pc;
+
+ int_thr.u64 = 0;
+ int_thr.s.tc_en = 1;
+ int_thr.s.tc_thr = 1;
+ cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64);
+
+ int_pc.u64 = 0;
+ int_pc.s.pc_thr = 5;
+ cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
+ } else {
+ union cvmx_pow_wq_int_thrx int_thr;
+ union cvmx_pow_wq_int_pc int_pc;
- /* Schedule NAPI now. This will indirectly enable the interrupt. */
- napi_schedule(_rx_group.napi);
+ int_thr.u64 = 0;
+ int_thr.s.tc_en = 1;
+ int_thr.s.tc_thr = 1;
+ cvmx_write_csr(CVMX_POW_WQ_INT
[PATCH v2 11/11] staging: octeon: prevent poll during rx init
Prevent poll before the RX init has been completed.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 4f32fa3..ce1e2a3 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -43,6 +43,8 @@
#include
+static atomic_t oct_rx_ready = ATOMIC_INIT(0);
+
static struct oct_rx_group {
int irq;
int group;
@@ -444,6 +446,9 @@ void cvm_oct_poll_controller(struct net_device *dev)
{
int i;
+ if (!atomic_read(_rx_ready))
+ return;
+
for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
if (!(pow_receive_groups & BIT(i)))
@@ -524,6 +529,7 @@ void cvm_oct_rx_initialize(void)
*/
napi_schedule(_rx_group[i].napi);
}
+ atomic_inc(_rx_ready);
}
void cvm_oct_rx_shutdown(void)
--
2.9.2
[PATCH v2 01/11] staging: octeon: disable rx interrupts in oct_rx_shutdown
Disable RX interrupts in oct_rx_shutdown(). This way we don't need to
expose the RX IRQ numbers outside the RX module.
Signed-off-by: Aaro Koskinen
---
drivers/staging/octeon/ethernet-rx.c | 9 +
drivers/staging/octeon/ethernet.c| 9 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index a10fe3a..5b26f2a 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -495,5 +495,14 @@ void cvm_oct_rx_initialize(void)
void cvm_oct_rx_shutdown(void)
{
+ /* Disable POW interrupt */
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group), 0);
+ else
+ cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
+
+ /* Free the interrupt handler */
+ free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
+
netif_napi_del(_oct_napi);
}
diff --git a/drivers/staging/octeon/ethernet.c
b/drivers/staging/octeon/ethernet.c
index 073a1e3..1e2e1ef 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -853,17 +853,8 @@ static int cvm_oct_remove(struct platform_device *pdev)
{
int port;
- /* Disable POW interrupt */
- if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group), 0);
- else
- cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
-
cvmx_ipd_disable();
- /* Free the interrupt handler */
- free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
-
atomic_inc_return(_oct_poll_queue_stopping);
cancel_delayed_work_sync(_oct_rx_refill_work);
--
2.9.2
Re: [PATCH 0/9] staging: octeon: multi rx group (queue) support
Hi,
On Wed, Aug 31, 2016 at 09:20:07AM -0700, Ed Swierk wrote:
> I'm not using CONFIG_NET_POLL_CONTROLLER either; the problem is in the
> normal cvm_oct_napi_poll() path.
>
> Here's my workaround:
[...]
> -static int cvm_oct_poll(struct oct_rx_group *rx_group, int budget)
> +static int cvm_oct_poll(int group, int budget)
> {
> const int coreid = cvmx_get_core_num();
> u64 old_group_mask;
> @@ -181,13 +181,13 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group,
> int budget)
> if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
> old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid));
> cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid),
> -BIT(rx_group->group));
> +BIT(group));
> @@ -447,7 +447,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi,
> int budget)
>napi);
> int rx_count;
>
> - rx_count = cvm_oct_poll(rx_group, budget);
> + rx_count = cvm_oct_poll(rx_group->group, budget);
I'm confused - there should be no difference?!
> > Can you see multiple ethernet IRQs in /proc/interrupts and their
> > counters increasing?
> >
> > With receive_group_order=4 you should see 16 IRQs.
>
> I see the 16 IRQs, and the first one does increase. But packets don't make
> it to the application.
Yeah, turns out that CN68XX supports up to 64 receive groups, and the
reset value is such that up to 64 groups get enabled by default in the
tag mask unless we know how to disabled them. So probably your packets
end up in those 48 other groups that do not have handler. This should
be fixed in v2 (by limiting to 16).
A.
Re: [PATCH] USB: ohci-omap: defer probe if PHY is missing
Hi, On Tue, Jan 03, 2017 at 05:51:43PM +0100, Greg Kroah-Hartman wrote: > On Mon, Jan 02, 2017 at 10:53:55PM +0200, Aaro Koskinen wrote: > > Defer probe if PHY is missing. E.g. on Nokia 770 several modules needs > > to be loaded to get the PHY going and ohci-omap should wait for those. > > > > Signed-off-by: Aaro Koskinen > > Is this a new bug? The 770 has been around for forever, why has this > not been a problem before now? PHY/OTG support for 770 has been around only since v3.14. I was previously compiling phy-tahvo as built-in, and bumped into this issue when compiling it as a module. A.
Re: [PATCH] USB: ohci-omap: defer probe if PHY is missing
Hi, On Tue, Jan 03, 2017 at 08:05:04PM +0100, Greg Kroah-Hartman wrote: > On Tue, Jan 03, 2017 at 08:50:31PM +0200, Aaro Koskinen wrote: > > On Tue, Jan 03, 2017 at 05:51:43PM +0100, Greg Kroah-Hartman wrote: > > > On Mon, Jan 02, 2017 at 10:53:55PM +0200, Aaro Koskinen wrote: > > > > Defer probe if PHY is missing. E.g. on Nokia 770 several modules needs > > > > to be loaded to get the PHY going and ohci-omap should wait for those. > > > > > > > > Signed-off-by: Aaro Koskinen > > > > > > Is this a new bug? The 770 has been around for forever, why has this > > > not been a problem before now? > > > > PHY/OTG support for 770 has been around only since v3.14. > > 3.14 was released March, 2014. A long time ago in kernel development :) > > > I was previously compiling phy-tahvo as built-in, and bumped into this > > issue when compiling it as a module. > > Why not just make the defconfig as built-in? I have reverted back to using built-in in my .config. > I'm not objecting to this patch, just really curious why no one else has > ever hit it. Maybe I'm the only user... The only other board using OHCI OMAP with PHY driver is H2/H3, and they have solved the issue making USB_OHCI_HCD_OMAP1 depend on the PHY driver: depends on ISP1301_OMAP || !(MACH_OMAP_H2 || MACH_OMAP_H3) This way modprobe will handle the loading order automatically. BTW, I just realized the same issue is with omap_udc. So I guess this patch should be just dropped, or resent so that both drivers are fixed. A.
Re: Nokia N900 sound driver and ECI GPIOs
Hi, On Mon, Jan 02, 2017 at 10:05:39PM +0100, joerg Reisenweber wrote: > On Mon 02 January 2017 21:01:01 Pali Rohár wrote: > > On Monday 02 January 2017 19:49:45 Aaro Koskinen wrote: > > > The schematic shows ECI(5:0), but only 3 are connected/used. There > > > were 3 other GPIOs reserved but not used in the final product. > > > > Are you sure that this is truth (maybe you have some information)? Or > > you just looked at schematic and deduced this observation (as other > > people too)? > > > > Joerg already told us that RX51 schematic does not 100% match production > > N900 and e.g. there is missing UART3 pins... > > We found this, see https://irclog.whitequark.org/neo900/2017-01-01 (has a lot > of possibly useful references/links) > The question is if pin AA3 aka GPIO_178 is actually NotConnected in N900 or > it's just an omission in schematics and there's actually some more 'stealth > hardware' in N900 that doesn't show up in docs, just like the testpoint UART > console http://wiki.maemo.org/N900_Hardware_Hacking#Debug_ports which also > are > missing in schematics. > > > > What we know that gpio 178 is *already* controlled and changed by > > production Nokia kernel running on production N900 devices (as I wrote > > in first email). > > I could use one of the unpopulated N900 PCB and solder a wire to the OMAP AA3 > pad, then try to make sure it's not connected to anything, or if it is then > find out about the details of this. > But I'm reluctant to do this, since it's an error prone and (in case of N/C) > not verifiable procedure, so I'd appreciate any further info, whether from > historical anecdote or from sourcecode review and conclusions, regarding that. Even if the published production kernel source controls GPIO 178, it does not mean the production device has it connected, as the same kernel also supported many older in-house prototype versions of the hardware (and some of those had it connected). Probably the easiest test would be to take the final published source, and then comment out all the GPIO 178 related code and build and run the kernel on the production device. Then see if you can observe any difference in behaviour. A.
Re: [PATCH] ARM: OMAP1: DMA: Correct the number of logical channels
Hi,
On Tue, Jan 03, 2017 at 01:22:34PM +0200, Peter Ujfalusi wrote:
> OMAP1510, OMAP5910 and OMAP310 have only 9 logical channels.
> OMAP1610, OMAP5912, OMAP1710, OMAP730, and OMAP850 have 16 logical channels
> available.
>
> The wired 17 for the lch_count must have been used to cover the 16 + 1
> dedicated LCD channel, in reality we can only use 9 or 16 channels.
>
> The d->chan_count is not used by the omap-dma stack, so we can skip the
> setup. chan_count was configured to the number of logical channels and not
> the actual number of physical channels anyways.
>
> Signed-off-by: Peter Ujfalusi
Acked-by: Aaro Koskinen
A.
> ---
> arch/arm/mach-omap1/dma.c | 16 +++-
> 1 file changed, 7 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
> index f6ba589cd312..c821c1d5610e 100644
> --- a/arch/arm/mach-omap1/dma.c
> +++ b/arch/arm/mach-omap1/dma.c
> @@ -32,7 +32,6 @@
> #include "soc.h"
>
> #define OMAP1_DMA_BASE (0xfffed800)
> -#define OMAP1_LOGICAL_DMA_CH_COUNT 17
>
> static u32 enable_1510_mode;
>
> @@ -348,8 +347,6 @@ static int __init omap1_system_dma_init(void)
> goto exit_iounmap;
> }
>
> - d->lch_count= OMAP1_LOGICAL_DMA_CH_COUNT;
> -
> /* Valid attributes for omap1 plus processors */
> if (cpu_is_omap15xx())
> d->dev_caps = ENABLE_1510_MODE;
> @@ -366,13 +363,14 @@ static int __init omap1_system_dma_init(void)
> d->dev_caps |= CLEAR_CSR_ON_READ;
> d->dev_caps |= IS_WORD_16;
>
> - if (cpu_is_omap15xx())
> - d->chan_count = 9;
> - else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
> - if (!(d->dev_caps & ENABLE_1510_MODE))
> - d->chan_count = 16;
> + /* available logical channels */
> + if (cpu_is_omap15xx()) {
> + d->lch_count = 9;
> + } else {
> + if (d->dev_caps & ENABLE_1510_MODE)
> + d->lch_count = 9;
> else
> - d->chan_count = 9;
> + d->lch_count = 16;
> }
>
> p = dma_plat_info;
> --
> 2.11.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MAINTAINERS: Add Aaro Koskinen as TI omap1 SoC co-maintainer
Hi, On Thu, Jan 05, 2017 at 01:41:01PM -0800, Tony Lindgren wrote: > Aaro has been doing a great job making sure mach-omap1 stays working > with the mainline kernel. So let's add Aaro as omap1 co-maintainer to > the MAINTAINERS file. > > Cc: Aaro Koskinen > Signed-off-by: Tony Lindgren Acked-by: Aaro Koskinen A. > --- > MAINTAINERS | 19 --- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -8933,7 +8933,20 @@ M: Josh Poimboeuf > S: Supported > F: tools/objtool/ > > -OMAP SUPPORT > +OMAP1 SUPPORT > +M: Aaro Koskinen > +M: Tony Lindgren > +L: linux-o...@vger.kernel.org > +Q: http://patchwork.kernel.org/project/linux-omap/list/ > +T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git > +S: Maintained > +F: arch/arm/mach-omap1/ > +F: arch/arm/plat-omap/ > +F: arch/arm/configs/omap1_defconfig > +F: drivers/i2c/busses/i2c-omap.c > +F: include/linux/i2c-omap.h > + > +OMAP2+ SUPPORT > M: Tony Lindgren > L: linux-o...@vger.kernel.org > W: http://www.muru.com/linux/omap/ > @@ -8941,8 +8954,8 @@ W: http://linux.omap.com/ > Q: http://patchwork.kernel.org/project/linux-omap/list/ > T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git > S: Maintained > -F: arch/arm/*omap*/ > -F: arch/arm/configs/omap1_defconfig > +F: arch/arm/mach-omap2/ > +F: arch/arm/plat-omap/ > F: arch/arm/configs/omap2plus_defconfig > F: drivers/i2c/busses/i2c-omap.c > F: drivers/irqchip/irq-omap-intc.c > -- > 2.11.0
Re: [PATCH] mfd: menelaus: remove obsolete local_irq_disable() and local_irq_enable()
On Mon, Apr 10, 2017 at 11:37:18AM +0200, Martin Kepplinger wrote:
> Since
>
> commit e6229bec25be ("rtc: make rtc_update_irq callable with irqs enabled")
>
> rtc_update_irq() is callable with irqs enabled, see the rtc drivers.
> So update this accordingly.
>
> Signed-off-by: Martin Kepplinger
> Cc: Henri Roosen
I think the patch looks OK, so:
Acked-by: Aaro Koskinen
But when trying to test it on N810/N800, I noticed I was missing RTC
altogether. My custom config was missing CONFIG_RTC_DRV_TWL92330, but
when enabling it I still get:
[5.759918] menelaus 0-0072: no 32k oscillator
Anyway, this issue is unrelated to this patch...
A.
> ---
> drivers/mfd/menelaus.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/mfd/menelaus.c b/drivers/mfd/menelaus.c
> index a4a8f1e..29b7164 100644
> --- a/drivers/mfd/menelaus.c
> +++ b/drivers/mfd/menelaus.c
> @@ -1022,9 +1022,7 @@ static int menelaus_set_alarm(struct device *dev,
> struct rtc_wkalrm *w)
> static void menelaus_rtc_update_work(struct menelaus_chip *m)
> {
> /* report 1/sec update */
> - local_irq_disable();
> rtc_update_irq(m->rtc, 1, RTC_IRQF | RTC_UF);
> - local_irq_enable();
> }
>
> static int menelaus_ioctl(struct device *dev, unsigned cmd, unsigned long
> arg)
> @@ -1086,9 +1084,7 @@ static const struct rtc_class_ops menelaus_rtc_ops = {
> static void menelaus_rtc_alarm_work(struct menelaus_chip *m)
> {
> /* report alarm */
> - local_irq_disable();
> rtc_update_irq(m->rtc, 1, RTC_IRQF | RTC_AF);
> - local_irq_enable();
>
> /* then disable it; alarms are oneshot */
> the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v13 0/6] Cavium MMC driver
Hi, On Thu, Mar 30, 2017 at 05:31:22PM +0200, Jan Glauber wrote: > Hi Ulf, > > we have a bug on some Octeon plattforms so I removed the Octeon driver for now > (but kept the DT bindings for it). We'll submit the Octeon driver later when > we've fixed the issue. Please rather post a new version that also works with OCTEON. I don't think a partial driver should be merged; originally this driver was working fine with OCTEON so there should be no issue supporting that?! A.
Re: [PATCH V2] cpufreq: skip invalid entries when searching the frequency
Hi,
On Wed, Oct 12, 2016 at 08:45:05AM +0530, Viresh Kumar wrote:
> From: Aaro Koskinen
>
> Skip invalid entries when searching the frequency. This fixes cpufreq
> at least on loongson2 MIPS board.
>
> Fixes: da0c6dc00c69 ("cpufreq: Handle sorted frequency tables more
> efficiently")
> Signed-off-by: Aaro Koskinen
> Signed-off-by: Viresh Kumar
> ---
> V1->V2:
> - Use cpufreq_frequency_table() instead.
>
> Hi Aaro,
>
> Can you please test this patch instead?
Seems to work as well.
Thanks,
A.
> include/linux/cpufreq.h | 104
>
> 1 file changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
> index 631ba33bbe9f..5fa55fc56e18 100644
> --- a/include/linux/cpufreq.h
> +++ b/include/linux/cpufreq.h
> @@ -639,19 +639,19 @@ static inline int cpufreq_table_find_index_al(struct
> cpufreq_policy *policy,
> unsigned int target_freq)
> {
> struct cpufreq_frequency_table *table = policy->freq_table;
> + struct cpufreq_frequency_table *pos, *best = table - 1;
> unsigned int freq;
> - int i, best = -1;
>
> - for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
> - freq = table[i].frequency;
> + cpufreq_for_each_valid_entry(pos, table) {
> + freq = pos->frequency;
>
> if (freq >= target_freq)
> - return i;
> + return pos - table;
>
> - best = i;
> + best = pos;
> }
>
> - return best;
> + return best - table;
> }
>
> /* Find lowest freq at or above target in a table in descending order */
> @@ -659,28 +659,28 @@ static inline int cpufreq_table_find_index_dl(struct
> cpufreq_policy *policy,
> unsigned int target_freq)
> {
> struct cpufreq_frequency_table *table = policy->freq_table;
> + struct cpufreq_frequency_table *pos, *best = table - 1;
> unsigned int freq;
> - int i, best = -1;
>
> - for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
> - freq = table[i].frequency;
> + cpufreq_for_each_valid_entry(pos, table) {
> + freq = pos->frequency;
>
> if (freq == target_freq)
> - return i;
> + return pos - table;
>
> if (freq > target_freq) {
> - best = i;
> + best = pos;
> continue;
> }
>
> /* No freq found above target_freq */
> - if (best == -1)
> - return i;
> + if (best == table - 1)
> + return pos - table;
>
> - return best;
> + return best - pos;
> }
>
> - return best;
> + return best - pos;
> }
>
> /* Works only on sorted freq-tables */
> @@ -700,28 +700,28 @@ static inline int cpufreq_table_find_index_ah(struct
> cpufreq_policy *policy,
> unsigned int target_freq)
> {
> struct cpufreq_frequency_table *table = policy->freq_table;
> + struct cpufreq_frequency_table *pos, *best = table - 1;
> unsigned int freq;
> - int i, best = -1;
>
> - for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
> - freq = table[i].frequency;
> + cpufreq_for_each_valid_entry(pos, table) {
> + freq = pos->frequency;
>
> if (freq == target_freq)
> - return i;
> + return pos - table;
>
> if (freq < target_freq) {
> - best = i;
> + best = pos;
> continue;
> }
>
> /* No freq found below target_freq */
> - if (best == -1)
> - return i;
> + if (best == table - 1)
> + return pos - table;
>
> - return best;
> + return best - table;
> }
>
> - return best;
> + return best - table;
> }
>
> /* Find highest freq at or below target in a table in descending order */
> @@ -729,19 +729,19 @@ static inline int cpufreq_table_find_index_dh(struct
> cpufreq_policy *policy,
> unsigned int target_freq)
> {
> struct cpufreq_frequency_table *table = policy->freq_table;
> + struct cpufreq_fr
[PATCH] ALSA: snd-aoa: enable sound on PowerBook G4 12"
Enable sound on PowerBook G4 12".
Signed-off-by: Aaro Koskinen
---
sound/aoa/fabrics/layout.c | 8
sound/aoa/soundbus/i2sbus/core.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/sound/aoa/fabrics/layout.c b/sound/aoa/fabrics/layout.c
index 8f71f7e..edc8681 100644
--- a/sound/aoa/fabrics/layout.c
+++ b/sound/aoa/fabrics/layout.c
@@ -112,6 +112,7 @@ MODULE_ALIAS("sound-layout-100");
MODULE_ALIAS("aoa-device-id-14");
MODULE_ALIAS("aoa-device-id-22");
+MODULE_ALIAS("aoa-device-id-31");
MODULE_ALIAS("aoa-device-id-35");
MODULE_ALIAS("aoa-device-id-44");
@@ -362,6 +363,13 @@ static struct layout layouts[] = {
.connections = tas_connections_nolineout,
},
},
+ /* PowerBook6,1 */
+ { .device_id = 31,
+ .codecs[0] = {
+ .name = "tas",
+ .connections = tas_connections_nolineout,
+ },
+ },
/* PowerBook6,5 */
{ .device_id = 44,
.codecs[0] = {
diff --git a/sound/aoa/soundbus/i2sbus/core.c b/sound/aoa/soundbus/i2sbus/core.c
index 1cbf210..000b585 100644
--- a/sound/aoa/soundbus/i2sbus/core.c
+++ b/sound/aoa/soundbus/i2sbus/core.c
@@ -197,7 +197,7 @@ static int i2sbus_add_dev(struct macio_dev *macio,
* so restrict to those we do handle for now.
*/
if (id && (*id == 22 || *id == 14 || *id == 35 ||
- *id == 44)) {
+ *id == 31 || *id == 44)) {
snprintf(dev->sound.modalias, 32,
"aoa-device-id-%d", *id);
ok = 1;
--
2.9.2
Re: [PATCH] ALSA: snd-aoa: enable sound on PowerBook G4 12"
Hi, On Wed, Aug 24, 2016 at 09:43:23PM +0200, Johannes Berg wrote: > On Wed, 2016-08-24 at 20:57 +0300, Aaro Koskinen wrote: > > Enable sound on PowerBook G4 12". > > Looks good to me, I assume you tested it and it works :) Yes, I have this laptop in use. A.
Re: [BISECTED REGRESSION] v4.8-rc: gpio-leds broken on OCTEON
Hi,
On Wed, Aug 24, 2016 at 11:42:00AM -0500, Steven J. Hill wrote:
> It is actually two patches that cause the breakage. The other is:
>
>commit e55aeb6ba4e8cc3549bff1e75ea1d029324bce21
>of/irq: Mark interrupt controllers as populated before initialisation
>
> I needed to revert both of these in order to get MMC working on our 71xx and
> 78xx boards. For our MMC, I got error messages from the MMC core of "Invalid
> POWER GPIO" until I applied the second patch. I will have a fix worthy of
> upstreaming today which will be posted today.
The below change works for me...
diff --git a/arch/mips/cavium-octeon/octeon-irq.c
b/arch/mips/cavium-octeon/octeon-irq.c
index 5a9b87b..5fd57c2 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1618,6 +1618,7 @@ static int __init octeon_irq_init_gpio(
pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
return -ENOMEM;
}
+ of_node_clear_flag(gpio_node, OF_POPULATED);
return 0;
}
A.
Re: [BISECTED REGRESSION] v4.8-rc: DT/OCTEON driver probing broken
Hi,
On Sun, Aug 28, 2016 at 12:34:06PM +0200, Thorsten Leemhuis wrote:
> Lo! Kefeng, below report made it to the list of regression for 4.8, but
> afaics nothing happened after the initial report. Is there maybe some
> reason why it shouldn't be on the list of regressions at all? Or was the
> problem discussed elsewhere? Or is it even fixed already? I noticed
> https://git.kernel.org/torvalds/c/fc520f8b4f (of/platform: disable the
> of_platform_default_populate_init() for all the ppc board), but that
> change is PPC specific.
There is a fix proposal here:
https://patchwork.linux-mips.org/patch/14041/
There is still few other boards remaining that use of_platform_bus_probe()
from device_initcall, but who knows, maybe they are not affected.
arch/microblaze/kernel/platform.c
arch/mips/mti-malta/malta-dt.c
arch/mips/netlogic/xlp/dt.c
arch/x86/platform/olpc/olpc_dt.c
A.
> On 16.08.2016 17:00, Aaro Koskinen wrote:
> > Hi,
> >
> > Commit 44a7185c2ae6 ("of/platform: Add common method to populate default
> > bus") added new arch_initcall of_platform_default_populate_init() that
> > will be called before device_initcall octeon_publish_devices(). Now the
> > of_platform_bus_probe() called in octeon_publish_devices() is apparently
> > doing nothing:
> >
> > [ 52.331353] calling octeon_publish_devices+0x0/0x14 @ 1
> > [ 52.331358] OF: of_platform_bus_probe()
> > [ 52.331362] OF: starting at: /
> > [ 52.331378] OF: of_platform_bus_create() - skipping /soc@0, already
> > populated
> > [ 52.331394] initcall octeon_publish_devices+0x0/0x14 returned 0 after 29
> > usecs
> >
> > This also means that USB etc. won't get probed.
> >
> > Any ideas what would be the proper fix for this? Changing
> > octeon_publish_devices() to arch_initcall seems to work but that may be
> > a bit hackish... Also, there might be also other MIPS boards affected
> > (arch/mips/netlogic/xlp/dt.c, arch/mips/mti-malta/malta-dt.c).
> >
> > A.
> >
> > http://news.gmane.org/find-root.php?message_id=20160816150056.GD18731%40ak-desktop.emea.nsn-net.net
> >
> > http://mid.gmane.org/20160816150056.GD18731%40ak-desktop.emea.nsn-net.net
> >
>
[BISECTED, REGRESSION] v4.12-rc: omapdrm fails to probe on Nokia N900
Hi, When booting v4.12-rc5 on Nokia N900, omapdrm fails to probe and there is no display. Bisected to: a09d2bc1503508c17ef3a71c6b1905e3660f3029 is the first bad commit commit a09d2bc1503508c17ef3a71c6b1905e3660f3029 Author: Peter Ujfalusi Date: Tue May 3 22:08:01 2016 +0300 drm/omap: Use omapdss_stack_is_ready() to check that the display stack is up Instead of 'guessing' based on aliases of the status of the DSS drivers, use the new interface to check that all needed drivers are loaded. In this way we can be sure that all needed drivers are loaded so it is safe to continue the probing of omapdrm. This method will allow the omapdrm to be probed 'headless', without outputs. Signed-off-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Reverting the commit seems to fix the issue. A.
Re: [BISECTED, REGRESSION] v4.12-rc: omapdrm fails to probe on Nokia N900
Hi, On Thu, Jun 15, 2017 at 09:51:06AM +0300, Tomi Valkeinen wrote: > On 15/06/17 01:11, Aaro Koskinen wrote: > > When booting v4.12-rc5 on Nokia N900, omapdrm fails to probe and there > > is no display. > > Are you sure it doesn't probe? It fails the omapdss_stack_is_ready() > check? If that's the case then this is easier to debug. Yes I think so, I added debug prints to omap_connect_dssdevs() and pdev_probe(), and it's omapdss_stack_is_ready() that is failing. > > Bisected to: > > > > a09d2bc1503508c17ef3a71c6b1905e3660f3029 is the first bad commit > > commit a09d2bc1503508c17ef3a71c6b1905e3660f3029 > > Author: Peter Ujfalusi > > Date: Tue May 3 22:08:01 2016 +0300 > > > > drm/omap: Use omapdss_stack_is_ready() to check that the display stack > > is up > > > > Instead of 'guessing' based on aliases of the status of the DSS drivers, > > use the new interface to check that all needed drivers are loaded. > > In this way we can be sure that all needed drivers are loaded so it is > > safe to continue the probing of omapdrm. > > This method will allow the omapdrm to be probed 'headless', without > > outputs. > > > > Signed-off-by: Peter Ujfalusi > > Signed-off-by: Tomi Valkeinen > > > > Reverting the commit seems to fix the issue. > > This is probably "fixed" by adding the display aliases into the n900 dts > file. The aliases should not really be required, although they are > recommended. Without the aliases the order of the displays is random, > and n900 could end up using tv-out as the first display. But even then, > the displays should still work. I'm using up-to-date DTS from the kernel tree. A.
Re: [BISECTED, REGRESSION] v4.12-rc: omapdrm fails to probe on Nokia N900
Hi, On Thu, Jun 15, 2017 at 10:28:31AM +0300, Peter Ujfalusi wrote: > On 2017-06-15 01:11, Aaro Koskinen wrote: > > When booting v4.12-rc5 on Nokia N900, omapdrm fails to probe and there > > is no display. > > > > Bisected to: > > > > a09d2bc1503508c17ef3a71c6b1905e3660f3029 is the first bad commit > > commit a09d2bc1503508c17ef3a71c6b1905e3660f3029 > > Author: Peter Ujfalusi > > Date: Tue May 3 22:08:01 2016 +0300 > > > > drm/omap: Use omapdss_stack_is_ready() to check that the display stack > > is up > > > > Instead of 'guessing' based on aliases of the status of the DSS drivers, > > use the new interface to check that all needed drivers are loaded. > > In this way we can be sure that all needed drivers are loaded so it is > > safe to continue the probing of omapdrm. > > This method will allow the omapdrm to be probed 'headless', without > > outputs. > > > > Signed-off-by: Peter Ujfalusi > > Signed-off-by: Tomi Valkeinen > > > > Reverting the commit seems to fix the issue. > > When you revert this patch do you see a warning saying: > "could not connect display: blah" ? if so what is 'blah'? No. A.
Re: [PATCH v2 00/11] staging: octeon: multi rx group (queue) support
Hi, On Wed, Aug 31, 2016 at 07:09:13PM -0700, Ed Swierk wrote: > On 8/31/16 13:57, Aaro Koskinen wrote: > > This series implements multiple RX group support that should improve > > the networking performance on multi-core OCTEONs. Basically we register > > IRQ and NAPI for each group, and ask the HW to select the group for > > the incoming packets based on hash. > > > > Tested on EdgeRouter Lite with a simple forwarding test using two flows > > and 16 RX groups distributed between two cores - the routing throughput > > is roughly doubled. > > > > Also tested with EBH5600 (8 cores) and EBB6800 (16 cores) by sending > > and receiving traffic in both directions using SGMII interfaces. > > With this series on 4.4.19, rx works with receive_group_order > 0. Good. > Setting receive_group_order=4, I do see 16 Ethernet interrupts. I tried > fiddling with various smp_affinity values (e.g. setting them all to > , or assigning a different one to each interrupt, or giving a > few to some and a few to others), as well as different values for > rps_cpus. 10-thread parallel iperf performance varies between 0.5 and 1.5 > Gbit/sec total depending on the particular settings. > > With the SDK kernel I get over 8 Gbit/sec. It seems to be achieving that > using just one interrupt (not even a separate one for tx, as far as I can > tell) pegged to CPU 0 (the default smp_affinity). I must be missing some > other major configuration tweak, perhaps specific to 10G. > > Can you run a test on the EBB6800 with the interfaces in 10G mode? Yes, I attached two EBB6800s with XAUI and ran iperf -P 10. With single group it gives 2.9 Gbit/s, and with 16 groups (on 16 cores) 4.3 Gbit/s. In 16 group case none of the CPUs are even close to 100%, so the bottleneck is somewhere else. I guess implementing the proper SSO init should increase the throughput. A.
[PATCH 0/3] MIPS: OCTEON: Add support for D-Link DSR-500N router
Hi, D-Link DSR-500N is close to 1000N and with small changes we can support both. A. Aaro Koskinen (3): MIPS: OCTEON: split dlink_dsr-1000n.dts MIPS: OCTEON: add DTS for D-Link DSR-500N MIPS: OCTEON: fix PCI interrupt routing on D-Link DSR-500N .../boot/dts/cavium-octeon/dlink_dsr-1000n.dts | 45 + .../dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi| 58 ++ .../mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts | 42 arch/mips/pci/pci-octeon.c | 2 + 4 files changed, 103 insertions(+), 44 deletions(-) create mode 100644 arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi create mode 100644 arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts -- 2.9.2
[PATCH 3/3] MIPS: OCTEON: fix PCI interrupt routing on D-Link DSR-500N
Fix PCI interrupt routing on D-Link DSR-500N.
Signed-off-by: Aaro Koskinen
---
arch/mips/pci/pci-octeon.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index c258cd4..308d051 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -204,6 +204,8 @@ const char *octeon_get_pci_interrupts(void)
* Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
* INTD# = 3)
*/
+ if (of_machine_is_compatible("dlink,dsr-500n"))
+ return "";
switch (octeon_bootinfo->board_type) {
case CVMX_BOARD_TYPE_NAO38:
/* This is really the NAC38 */
--
2.9.2
