Re: [PATCH v3 0/6] Introduce ZONE_CMA
On 2016/6/20 14:48, Joonsoo Kim wrote: > On Fri, Jun 17, 2016 at 03:38:49PM +0800, Chen Feng wrote: >> Hi Kim & feng, >> >> Thanks for the share. In our platform also has the same use case. >> >> We only let the alloc with GFP_HIGHUSER_MOVABLE in memory.c to use cma >> memory. >> >> If we add zone_cma, It seems can resolve the cma migrate issue. >> >> But when free_hot_cold_page, we need let the cma page goto system directly >> not the pcp. >> It can be fail while cma_alloc and cma_release. If we alloc the whole cma >> pages which >> declared before. > > Hmm...I'm not sure I understand your explanation. So, if I miss > something, please let me know. We calls drain_all_pages() when > isolating pageblock and alloc_contig_range() also has one > drain_all_pages() calls to drain pcp pages. And, after pageblock isolation, > freed pages belonging to MIGRATE_ISOLATE pageblock will go to the > buddy directly so there would be no problem you mentioned. Isn't it? > Yes, you are right. I mean if the we free cma page to pcp-list, it will goto the migrate_movable list. Then the alloc with movable flag can use the cma memory from the list with buffered_rmqueue. But that's not what we want. It will cause the migrate fail if all movable alloc can use cma memory. If I am wrong, please correct me. Thanks. > Thanks. > > . >
[PATCH] staging: ion: remove __GFP_NOWARN when use low order gfp flags
It's useful to show the current memory in detail when alloc failed.
And, there may be a lot of high order alloc failed, just show memory
when an order 0 alloc failed.
Signed-off-by: Chen Feng
---
drivers/staging/android/ion/ion_system_heap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/android/ion/ion_system_heap.c
b/drivers/staging/android/ion/ion_system_heap.c
index b69dfc7..c3b7975 100644
--- a/drivers/staging/android/ion/ion_system_heap.c
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -28,7 +28,7 @@
static gfp_t high_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN |
__GFP_NORETRY) & ~__GFP_RECLAIM;
-static gfp_t low_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN);
+static gfp_t low_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO);
static const unsigned int orders[] = {8, 4, 0};
static const int num_orders = ARRAY_SIZE(orders);
static int order_to_index(unsigned int order)
--
1.9.1
Re: [PATCH] reset: hisilicon: Fix hi6220 module license
looks good to me.
On 2017/5/25 17:22, Andreas Färber wrote:
> The hi6220_reset driver fails to load:
>
> [ 10.423640] hi6220_reset: module license 'unspecified' taints kernel.
> [ 10.423644] Disabling lock debugging due to kernel taint
> [ 10.423735] hi6220_reset: Unknown symbol regmap_write (err 0)
> [ 10.423747] hi6220_reset: Unknown symbol devm_kmalloc (err 0)
> [ 10.423759] hi6220_reset: Unknown symbol syscon_node_to_regmap (err 0)
> [ 10.423768] hi6220_reset: Unknown symbol reset_controller_register (err
> 0)
> [ 10.423784] hi6220_reset: Unknown symbol __platform_driver_register (err
> 0)
>
> Add a MODULE_LICENSE() to fix this.
>
> Fixes: 70b3590f639f ("reset: hi6220: fix modular build")
> Cc: Arnd Bergmann
> Cc: Chen Feng
> Signed-off-by: Andreas Färber
> ---
> drivers/reset/hisilicon/hi6220_reset.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/reset/hisilicon/hi6220_reset.c
> b/drivers/reset/hisilicon/hi6220_reset.c
> index 35ce53edabf9..d5e5229308f2 100644
> --- a/drivers/reset/hisilicon/hi6220_reset.c
> +++ b/drivers/reset/hisilicon/hi6220_reset.c
> @@ -155,3 +155,5 @@ static int __init hi6220_reset_init(void)
> }
>
> postcore_initcall(hi6220_reset_init);
> +
> +MODULE_LICENSE("GPL v2");
Re: [PATCH RFC] random: fix syzkaller fuzzer test int overflow
On 2017/10/24 17:09, Greg KH wrote:
> On Tue, Oct 24, 2017 at 03:44:17PM +0800, Chen Feng wrote:
>> [pid:11940,cpu6,syz-executor][flp_ioctl]cmd[0x1]
>> Restart is not permit
>> =
>> UBSAN: Undefined behaviour in
>> kernel/linux-4.4/drivers/char/random.c:676:19
>> signed integer overflow:
>> 2147483645 + 268435455 cannot be represented in type 'int'
>> CPU: 4 PID: 11941 Comm: syz-executor Not tainted 4.4.76+ #2
>
> Does this also happen on 4.14-rc6?
No, mainline also has this issue.
>
>> TGID: 11928 Comm: syz-executor
>> Hardware name: hi3660 (DT)
>> Call trace:
>> [] dump_backtrace+0x0/0x314
>> [] show_stack+0x1c/0x24
>> [] dump_stack+0xdc/0x130
>> [] ubsan_epilogue+0x18/0x6c
>> [] handle_overflow+0x180/0x1d4
>> [] __ubsan_handle_add_overflow+0x2c/0x34
>> [] credit_entropy_bits+0x358/0x9a8
>> [] random_ioctl+0x338/0x384
>> [] do_vfs_ioctl+0x60c/0xa4c
>> [] SyS_ioctl+0x9c/0xc0
>> [] el0_svc_naked+0x24/0x28
>> =
>>
>> Signed-off-by: Chen Feng
>> Signed-off-by: Yukun Zhao
>> ---
>> drivers/char/random.c | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/char/random.c b/drivers/char/random.c
>> index 1ef2640..6f2bd6a 100644
>> --- a/drivers/char/random.c
>> +++ b/drivers/char/random.c
>> @@ -699,6 +699,11 @@ static void credit_entropy_bits(struct entropy_store
>> *r, int nbits)
>> if (cmpxchg(&r->entropy_count, orig, entropy_count) != orig)
>> goto retry;
>>
>> +if (INT_MAX - nbits < r->entropy_total) {
>> +WARN_ON(1);
>
> Why WARN_ON()? What is that going to help with?
Actually, I am not familiar with the random module
This patch is RFC to see if some one has better idea.
-feng
>
> thanks,
>
> greg k-h
>
> .
>
Re: [PATCH RFC] random: fix syzkaller fuzzer test int overflow
Hi Ted, On 2017/10/24 18:25, Theodore Ts'o wrote: > On Tue, Oct 24, 2017 at 11:09:27AM +0200, Greg KH wrote: >> On Tue, Oct 24, 2017 at 03:44:17PM +0800, Chen Feng wrote: >>> [pid:11940,cpu6,syz-executor][flp_ioctl]cmd[0x1] >>> Restart is not permit >>> = >>> UBSAN: Undefined behaviour in >>> kernel/linux-4.4/drivers/char/random.c:676:19 >>> signed integer overflow: >>> 2147483645 + 268435455 cannot be represented in type 'int' >>> CPU: 4 PID: 11941 Comm: syz-executor Not tainted 4.4.76+ #2 >> >> Does this also happen on 4.14-rc6? > > No. It was fixed in 4.8, by commit 86a574de4590: "random: strengthen > input validation for RNDADDTOENTCNT". I see my kernel has already merged this patch. So I don't think this patch can resolve the issue above. -feng > > - Ted > > . >
Re: [PATCH RFC] random: fix syzkaller fuzzer test int overflow
On 2017/10/25 14:56, Greg KH wrote: > On Wed, Oct 25, 2017 at 02:30:56PM +0800, Chen Feng wrote: >> Hi Ted, >> >> On 2017/10/24 18:25, Theodore Ts'o wrote: >>> On Tue, Oct 24, 2017 at 11:09:27AM +0200, Greg KH wrote: >>>> On Tue, Oct 24, 2017 at 03:44:17PM +0800, Chen Feng wrote: >>>>> [pid:11940,cpu6,syz-executor][flp_ioctl]cmd[0x1] >>>>> Restart is not permit >>>>> = >>>>> UBSAN: Undefined behaviour in >>>>> kernel/linux-4.4/drivers/char/random.c:676:19 >>>>> signed integer overflow: >>>>> 2147483645 + 268435455 cannot be represented in type 'int' >>>>> CPU: 4 PID: 11941 Comm: syz-executor Not tainted 4.4.76+ #2 >>>> >>>> Does this also happen on 4.14-rc6? >>> >>> No. It was fixed in 4.8, by commit 86a574de4590: "random: strengthen >>> input validation for RNDADDTOENTCNT". >> >> >> I see my kernel has already merged this patch. So I don't think this patch >> can resolve the issue above. > > Do you have a reproducer for this issue that we can use to test? > It's hard to reproduce, we found this on stress test with syzkaller test. r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) syz_open_dev$random(&(0x7f005000-0xc)="2f6465762f72616e646f6d00", 0x0, 0x10100) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", 0x0, 0x0) UBSAN: Undefined behaviour in kernel/linux-4.4/drivers/char/random.c:676:19 [] random_ioctl+0x338/0x384 git log --oneline drivers/char/random.c 3991576 random: properly align get_random_int_hash 5f87c47 Merge branch 'linux-linaro-lsk-v4.4' into linux-linaro-lsk-v4.4-android f48dd2d random: add interrupt callback to VMBus IRQ handler 529025b random: print a warning for the first ten uninitialized random users f41fc0b random: initialize the non-blocking pool via add_hwgenerator_randomness() fdd8543 Merge branch 'linux-linaro-lsk-v4.4' into linux-linaro-lsk-v4.4-android 93f84c8 random: strengthen input validation for RNDADDTOENTCNT 06bfe14 FROMLIST: drivers: char: random: add get_random_long() c271950 random: Remove kernel blocking API 205a525 random: Add callback API for random pool readiness 16b369a random: Blocking API for accessing nonblocking_pool 1d9de44 random: Wake up all getrandom(2) callers when pool is ready 19acc77 random: Fix fast_mix() function > thanks, > > greg k-h > > . >
Re: [PATCH RFC] random: fix syzkaller fuzzer test int overflow
On 2017/10/25 16:49, Theodore Ts'o wrote: > Other people who have sent me fuzzer test reproducers are able to > reproduce syzkaller logs into a simple C program. Can you explain to > me what the heck: > >> r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00", >> 0x0, 0x0) > > means? Take a look at this: https://github.com/google/syzkaller/blob/master/sys/linux/random.txt > > - Ted > >
Re: [PATCH RFC] random: fix syzkaller fuzzer test int overflow
Hi ted,
On 2017/10/26 23:04, Theodore Ts'o wrote:
> On Thu, Oct 26, 2017 at 04:25:15PM +0800, Chen Feng wrote:
>>
>>
>> On 2017/10/25 16:49, Theodore Ts'o wrote:
>>> Other people who have sent me fuzzer test reproducers are able to
>>> reproduce syzkaller logs into a simple C program. Can you explain to
>>> me what the heck:
>>>
>>>> r3 = syz_open_dev$urandom(&(0x7f00a000)="2f6465762f7572616e646f6d00",
>>>> 0x0, 0x0)
>>>
>>> means?
>>
>> Take a look at this:
>>
>> https://github.com/google/syzkaller/blob/master/sys/linux/random.txt
>
> Sorry, this *still* looks like gobbledygook.
>
> What ioctls are you executing, and with what arguments?
>
> *Please*, give me a C program I can compile.
I checked the ioctl. What's the purpose of RNDADDTOENTCNT ioctl to userspace?
We need to checked the user-input at credit_entropy_bits_safe.
+ if (INT_MAX - nbits < r->entropy_total)
+ return -EINVAL;
+
The test-code below:
void *random_ioctl_test(void *args)
{
int fd = -1;
int ret = -1;
int test_arg = 0x7fff;
fd = open("dev/urandom", 0x0, 0x0);
if (fd < 0) {
printf("open dev/urandom failed!\n");
return NULL;
}
ret = ioctl(fd, 0x40045201, &test_arg);
printf("random_ioctl ret=%d\n", ret);
close(fd);
return NULL;
}
int main(int argc, char *argv[])
{
int ret, i;
pthread_t thread[100];
for (i = 0; i < 100; i++) {
ret = pthread_create(&thread[i], NULL, random_ioctl_test, &i);
if (ret) {
printf("create thread %d fail with ret=%d\n", i, ret);
return -1;
}
}
for (i = 0; i < 100; i++) {
pthread_join(thread[i], NULL);
}
return 0;
}
>
>-Ted
>
> .
>
[PATCH 3/3] arm64: dts: Add dts node for hi6220 iommu
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3ef33b4 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -5,6 +5,7 @@
*/
#include
+#include
/ {
compatible = "hisilicon,hi6220";
@@ -167,5 +168,19 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ smmu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu_clk",
+ "media_sc_clk",
+ "smmu_peri_clk";
+ #iommu-cells = <1>;
+ };
+
};
};
--
1.9.1
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[PATCH 1/3] docs: dts: Documentation for smmu in hi6220 SoC.
Documentation for system mmu in hi6220 platform.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
.../bindings/iommu/hisi,hi6220-iommu.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
new file mode 100644
index 000..32d1156
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
@@ -0,0 +1,52 @@
+Hi6220 SoC SMMU Device Driver devicetree document
+===
+The Architecture of SMMU on Hi6220 SoC:
+
+ +--+
+ | |
+ | +-+ ++ +-+ +---+ |
+ | | ADE | | ISP | | V/J codec | | G3D | |
+ | +|+ +---|+ +--|--+ +---|---| |
+ | | | | | |
+ | -v---v--v--v-|
+ | Media Bus |
+ | |---||
+ | | ||
+ | +---v---v+ |
+ | |SMMU| |
+ | +--|-|---+ |
+ || | |
+ +|-|---+
+| |
+ +v-v---+
+ | DDRC|
+ +--+
+
+Note:
+The media system shared the same smmu IP. to access DDR memory. And all
+media IP used the same page table.
+
+Below binding describes the system mmu for media system in hi6220 platform
+
+Required properties:
+- compatible: Should be "hisilicon,hi6220-smmu" example:
+ compatible = "hisilicon,hi6220-smmu";
+- reg: A tuple of base address and size of System MMU registers.
+- interrupts: An interrupt specifier for interrupt signal of System MMU.
+- clocks: The clock used for smmu IP.
+- clock-names: The name to enable clock with clock framework.
+- #iommu-cells: The iommu-cells should be 1 for muti-master to use.
+
+Examples:
+ smmu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+ <&media_ctrl HI6220_MED_MMU>,
+ <&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu_clk",
+ "media_sc_clk",
+ "smmu_peri_clk";
+ #iommu-cells = <1>;
+ };
--
1.9.1
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[PATCH 2/3] staging: android: ion: Add ion driver for Hi6220 SoC platform
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
drivers/staging/android/ion/Kconfig| 7 +
drivers/staging/android/ion/Makefile | 1 +
drivers/staging/android/ion/hisilicon/Kconfig | 5 +
drivers/staging/android/ion/hisilicon/Makefile | 1 +
drivers/staging/android/ion/hisilicon/hi6220_ion.c | 201 +
5 files changed, 215 insertions(+)
create mode 100644 drivers/staging/android/ion/hisilicon/Kconfig
create mode 100644 drivers/staging/android/ion/hisilicon/Makefile
create mode 100644 drivers/staging/android/ion/hisilicon/hi6220_ion.c
diff --git a/drivers/staging/android/ion/Kconfig
b/drivers/staging/android/ion/Kconfig
index 3452346..19c1572 100644
--- a/drivers/staging/android/ion/Kconfig
+++ b/drivers/staging/android/ion/Kconfig
@@ -33,3 +33,10 @@ config ION_TEGRA
help
Choose this option if you wish to use ion on an nVidia Tegra.
+config ION_HISI
+ tristate "Ion for Hisilicon"
+ depends on ARCH_HISI && ION
+ help
+ Choose this option if you wish to use ion on Hisilicon Platform.
+
+source "drivers/staging/android/ion/hisilicon/Kconfig"
diff --git a/drivers/staging/android/ion/Makefile
b/drivers/staging/android/ion/Makefile
index b56fd2b..18cc2aa 100644
--- a/drivers/staging/android/ion/Makefile
+++ b/drivers/staging/android/ion/Makefile
@@ -7,4 +7,5 @@ endif
obj-$(CONFIG_ION_DUMMY) += ion_dummy_driver.o
obj-$(CONFIG_ION_TEGRA) += tegra/
+obj-$(CONFIG_ION_HISI) += hisilicon/
diff --git a/drivers/staging/android/ion/hisilicon/Kconfig
b/drivers/staging/android/ion/hisilicon/Kconfig
new file mode 100644
index 000..2b4bd07
--- /dev/null
+++ b/drivers/staging/android/ion/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config HI6220_ION
+bool "Hi6220 ION Driver"
+depends on ARCH_HISI && ION
+help
+ Build the Hisilicon Hi6220 ion driver.
diff --git a/drivers/staging/android/ion/hisilicon/Makefile
b/drivers/staging/android/ion/hisilicon/Makefile
new file mode 100644
index 000..2a89414
--- /dev/null
+++ b/drivers/staging/android/ion/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HI6220_ION) += hi6220_ion.o
diff --git a/drivers/staging/android/ion/hisilicon/hi6220_ion.c
b/drivers/staging/android/ion/hisilicon/hi6220_ion.c
new file mode 100644
index 000..b7d39b8
--- /dev/null
+++ b/drivers/staging/android/ion/hisilicon/hi6220_ion.c
@@ -0,0 +1,201 @@
+#define pr_fmt(fmt) "Ion: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include "../ion_priv.h"
+#include "../ion.h"
+
+struct hi6220_ion_type_table {
+ const char *name;
+ enum ion_heap_type type;
+};
+
+static struct hi6220_ion_type_table ion_type_table[] = {
+ {"ion_system", ION_HEAP_TYPE_SYSTEM},
+ {"ion_system_contig", ION_HEAP_TYPE_SYSTEM_CONTIG},
+ {"ion_carveout", ION_HEAP_TYPE_CARVEOUT},
+ {"ion_chunk", ION_HEAP_TYPE_CHUNK},
+ {"ion_dma", ION_HEAP_TYPE_DMA},
+ {"ion_custom", ION_HEAP_TYPE_CUSTOM},
+};
+
+static struct ion_device *idev;
+static int num_heaps;
+static struct ion_heap **heaps;
+static struct ion_platform_heap **heaps_data;
+
+static int get_type_by_name(const char *name, enum ion_heap_type *type)
+{
+ int i, n;
+
+ n = ARRAY_SIZE(ion_type_table);
+ for (i = 0; i < n; i++) {
+ if (strncmp(name, ion_type_table[i].name, strlen(name)))
+ continue;
+
+ *type = ion_type_table[i].type;
+ return 0;
+ }
+
+ return -1;
+}
+
+static int hi6220_set_platform_data(struct platform_device *pdev)
+{
+ unsigned int base;
+ unsigned int size;
+ unsigned int id;
+ const char *heap_name;
+ const char *type_name;
+ enum ion_heap_type type;
+ int ret;
+ struct device_node *np;
+ struct ion_platform_heap *p_data;
+ const struct device_node *dt_node = pdev->dev.of_node;
+ int index = 0;
+
+ for_each_child_of_node(dt_node, np)
+ num_heaps++;
+
+ heaps_data = devm_kzalloc(&pdev->dev,
+ sizeof(struct ion_platform_heap *) *
num_heaps,
+ GFP_KERNEL);
+
+ for_each_child_of_node(dt_node, np) {
+ p_data = devm_kzalloc(&pdev->dev,
+ sizeof(struct ion_platform_heap),
+ GFP_KERNEL);
+
+ ret = of_property_read_string(np, "heap-name", &heap_name);
+ if (ret < 0) {
+ pr_err("check the name of node %s\n", np->name);
+ continue;
+ }
+
+ ret = of_property_read_u32(np, "heap-id", &id);
+ if (ret < 0) {
+
[PATCH 1/3] docs: dts: Add documentation for hi6220 SoC ION node
Documentation for hi6220 SoC ION node
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
.../devicetree/bindings/staging/ion/hi6220-ion.txt | 27 ++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/staging/ion/hi6220-ion.txt
diff --git a/Documentation/devicetree/bindings/staging/ion/hi6220-ion.txt
b/Documentation/devicetree/bindings/staging/ion/hi6220-ion.txt
new file mode 100644
index 000..5f969d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/staging/ion/hi6220-ion.txt
@@ -0,0 +1,27 @@
+Hi6220 SoC ION
+
+Required properties:
+- compatible : "hisilicon,hi6220-ion"
+- list of the ION heaps
+
+Example:
+hi6220-ion {
+compatible = "hisilicon,hi6220-ion";
+
+heap_sys_user@0 {
+heap-name = "sys_user";
+heap-id = <0x0>;
+heap-base = <0x0>;
+heap-size = <0x0>;
+heap-type = "ion_system";
+};
+
+heap_sys_contig@0 {
+heap-name = "sys_contig";
+heap-id = <0x1>;
+heap-base = <0x0>;
+heap-size = <0x0>;
+heap-type = "ion_system_contig";
+};
+};
+
--
1.9.1
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[PATCH 3/3] arm64: dts: Add dts files to enable ION on Hi6220 SoC.
Add ION node to enable ION on hi6220 SoC platform
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 +
arch/arm64/boot/dts/hisilicon/hi6220-ion.dtsi | 23 +++
2 files changed, 24 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-ion.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e36a539..44b75d2 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -11,6 +11,7 @@
/memreserve/ 0x05e0 0x0010;
#include "hi6220.dtsi"
+#include "hi6220-ion.dtsi"
/ {
model = "HiKey Development Board";
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-ion.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220-ion.dtsi
new file mode 100644
index 000..24d3722
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-ion.dtsi
@@ -0,0 +1,23 @@
+/ {
+ hi6220-ion {
+ compatible = "hisilicon,hi6220-ion";
+
+ heap_sys_user@0 {
+ heap-name = "sys_user";
+ heap-id = <0x0>;
+ heap-base = <0x0>;
+ heap-size = <0x0>;
+ heap-type = "ion_system";
+ };
+
+ heap_sys_contig@0 {
+ heap-name = "sys_contig";
+ heap-id = <0x1>;
+ heap-base = <0x0>;
+ heap-size = <0x0>;
+ heap-type = "ion_system_contig";
+ };
+ };
+
+};
+
--
1.9.1
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[PATCH 2/3] iommu/hisilicon: Add hi6220 iommu driver
Enable iommu on hi6220 SoC platform.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
drivers/iommu/Kconfig| 8 +
drivers/iommu/Makefile | 1 +
drivers/iommu/hi6220_iommu.c | 503 +++
3 files changed, 512 insertions(+)
create mode 100644 drivers/iommu/hi6220_iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 4664c2a..9b41708 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -343,6 +343,14 @@ config SPAPR_TCE_IOMMU
Enables bits of IOMMU API required by VFIO. The iommu_ops
is not implemented as it is not necessary for VFIO.
+config HI6220_IOMMU
+ bool "Hi6220 IOMMU Support"
+ depends on ARM64
+ select IOMMU_API
+ select IOMMU_IOVA
+ help
+ Enable IOMMU Driver for hi6220 SoC.
+
# ARM IOMMU support
config ARM_SMMU
bool "ARM Ltd. System MMU (SMMU) Support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index c6dcc51..ee4dfef 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o
obj-$(CONFIG_SHMOBILE_IPMMU) += shmobile-ipmmu.o
obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o
+obj-$(CONFIG_HI6220_IOMMU) += hi6220_iommu.o
diff --git a/drivers/iommu/hi6220_iommu.c b/drivers/iommu/hi6220_iommu.c
new file mode 100644
index 000..9e9b19d
--- /dev/null
+++ b/drivers/iommu/hi6220_iommu.c
@@ -0,0 +1,503 @@
+/*
+ * Hisilicon Hi6220 IOMMU driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "IOMMU: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SMMU_CTRL_OFFSET (0x)
+#define SMMU_ENABLE_OFFSET (0x0004)
+#define SMMU_PTBR_OFFSET (0x0008)
+#define SMMU_START_OFFSET(0x000C)
+#define SMMU_END_OFFSET (0x0010)
+#define SMMU_INTMASK_OFFSET (0x0014)
+#define SMMU_RINTSTS_OFFSET (0x0018)
+#define SMMU_MINTSTS_OFFSET (0x001C)
+#define SMMU_INTCLR_OFFSET (0x0020)
+#define SMMU_STATUS_OFFSET (0x0024)
+#define SMMU_AXIID_OFFSET(0x0028)
+#define SMMU_CNTCTRL_OFFSET (0x002C)
+#define SMMU_TRANSCNT_OFFSET (0x0030)
+#define SMMU_L0TLBHITCNT_OFFSET (0x0034)
+#define SMMU_L1TLBHITCNT_OFFSET (0x0038)
+#define SMMU_WRAPCNT_OFFSET (0x003C)
+#define SMMU_SEC_START_OFFSET(0x0040)
+#define SMMU_SEC_END_OFFSET (0x0044)
+#define SMMU_VERSION_OFFSET (0x0048)
+#define SMMU_IPTSRC_OFFSET (0x004C)
+#define SMMU_IPTPA_OFFSET(0x0050)
+#define SMMU_TRBA_OFFSET (0x0054)
+#define SMMU_BYS_START_OFFSET(0x0058)
+#define SMMU_BYS_END_OFFSET (0x005C)
+#define SMMU_RAM_OFFSET (0x1000)
+#define SMMU_REGS_MAX(15)
+#define SMMU_REGS_SGMT_END (0x60)
+#define SMMU_CHIP_ID_V100(1)
+#define SMMU_CHIP_ID_V200(2)
+
+#define SMMU_REGS_OPS_SEGMT_START(0xf00)
+#define SMMU_REGS_OPS_SEGMT_NUMB (8)
+#define SMMU_REGS_AXI_SEGMT_START(0xf80)
+#define SMMU_REGS_AXI_SEGMT_NUMB (8)
+
+#define SMMU_INIT(0x1)
+#define SMMU_RUNNING (0x2)
+#define SMMU_SUSPEND (0x3)
+#define SMMU_STOP(0x4)
+
+#define PAGE_ENTRY_VALID (0x1)
+
+#define IOVA_START_PFN (1)
+#define IOPAGE_SHIFT (12)
+#define IOVA_PFN(addr) ((addr) >> IOPAGE_SHIFT)
+#define IOVA_PAGE_SZ (1UL << IOPAGE_SHIFT)
+#define IOVA_START (0x2000)
+#define IOVA_END (0x8000)
+
+struct hi6220_smmu {
+ unsigned int irq;
+ irq_handler_t smmu_isr;
+ void __iomem *reg_base;
+ struct clk *smmu_peri_clk;
+ struct clk *smmu_clk;
+ struct clk *media_sc_clk;
+ size_t page_size;
+ struct iova_domain iova_allocator;
+ dma_addr_t pgtable_phy;
+ void *pgtable_virt;
+};
+
+struct hi6220_domain {
+ struct hi6220_smmu *smmu_dev;
+ struct device *dev;
+ spinlock_t spinlock; /*spinlock for device&resource*/
+ struct iommu_domain io_domain;
+ unsigned long iova_start;
+ unsigned long iova_end;
+};
+
+static struct hi6220_smmu *smmu_dev_handle;
+static unsigned int smmu_regs_value[SMMU_REGS_MAX] = {0};
+
+static struct hi6220_domain *to_hi6220_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct hi622
[PATCH V2 2/3] Add iommu driver for hi6220 SoC platform
iommu/hisilicon: Add hi6220-SoC smmu driver
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
drivers/iommu/Kconfig| 8 +
drivers/iommu/Makefile | 1 +
drivers/iommu/hi6220_iommu.c | 482 +++
3 files changed, 491 insertions(+)
create mode 100644 drivers/iommu/hi6220_iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 4664c2a..9b41708 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -343,6 +343,14 @@ config SPAPR_TCE_IOMMU
Enables bits of IOMMU API required by VFIO. The iommu_ops
is not implemented as it is not necessary for VFIO.
+config HI6220_IOMMU
+ bool "Hi6220 IOMMU Support"
+ depends on ARM64
+ select IOMMU_API
+ select IOMMU_IOVA
+ help
+ Enable IOMMU Driver for hi6220 SoC.
+
# ARM IOMMU support
config ARM_SMMU
bool "ARM Ltd. System MMU (SMMU) Support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index c6dcc51..ee4dfef 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o
obj-$(CONFIG_SHMOBILE_IPMMU) += shmobile-ipmmu.o
obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o
+obj-$(CONFIG_HI6220_IOMMU) += hi6220_iommu.o
diff --git a/drivers/iommu/hi6220_iommu.c b/drivers/iommu/hi6220_iommu.c
new file mode 100644
index 000..6c5198d
--- /dev/null
+++ b/drivers/iommu/hi6220_iommu.c
@@ -0,0 +1,482 @@
+/*
+ * Hisilicon Hi6220 IOMMU driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "IOMMU: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SMMU_CTRL_OFFSET (0x)
+#define SMMU_ENABLE_OFFSET (0x0004)
+#define SMMU_PTBR_OFFSET (0x0008)
+#define SMMU_START_OFFSET(0x000C)
+#define SMMU_END_OFFSET (0x0010)
+#define SMMU_INTMASK_OFFSET (0x0014)
+#define SMMU_RINTSTS_OFFSET (0x0018)
+#define SMMU_MINTSTS_OFFSET (0x001C)
+#define SMMU_INTCLR_OFFSET (0x0020)
+#define SMMU_STATUS_OFFSET (0x0024)
+#define SMMU_AXIID_OFFSET(0x0028)
+#define SMMU_CNTCTRL_OFFSET (0x002C)
+#define SMMU_TRANSCNT_OFFSET (0x0030)
+#define SMMU_L0TLBHITCNT_OFFSET (0x0034)
+#define SMMU_L1TLBHITCNT_OFFSET (0x0038)
+#define SMMU_WRAPCNT_OFFSET (0x003C)
+#define SMMU_SEC_START_OFFSET(0x0040)
+#define SMMU_SEC_END_OFFSET (0x0044)
+#define SMMU_VERSION_OFFSET (0x0048)
+#define SMMU_IPTSRC_OFFSET (0x004C)
+#define SMMU_IPTPA_OFFSET(0x0050)
+#define SMMU_TRBA_OFFSET (0x0054)
+#define SMMU_BYS_START_OFFSET(0x0058)
+#define SMMU_BYS_END_OFFSET (0x005C)
+#define SMMU_RAM_OFFSET (0x1000)
+#define SMMU_REGS_MAX(15)
+#define SMMU_REGS_SGMT_END (0x60)
+#define SMMU_CHIP_ID_V100(1)
+#define SMMU_CHIP_ID_V200(2)
+
+#define SMMU_REGS_OPS_SEGMT_START(0xf00)
+#define SMMU_REGS_OPS_SEGMT_NUMB (8)
+#define SMMU_REGS_AXI_SEGMT_START(0xf80)
+#define SMMU_REGS_AXI_SEGMT_NUMB (8)
+
+#define SMMU_INIT(0x1)
+#define SMMU_RUNNING (0x2)
+#define SMMU_SUSPEND (0x3)
+#define SMMU_STOP(0x4)
+#define SMMU_CTRL_INVALID(BIT(10))
+#define PAGE_ENTRY_VALID (0x1)
+
+#define IOVA_START_PFN (1)
+#define IOPAGE_SHIFT (12)
+#define IOVA_PFN(addr) ((addr) >> IOPAGE_SHIFT)
+#define IOVA_PAGE_SZ (SZ_4K)
+#define IOVA_START (0x2000)
+#define IOVA_END (0x8000)
+
+struct hi6220_smmu {
+ unsigned int irq;
+ irq_handler_t smmu_isr;
+ void __iomem *reg_base;
+ struct clk *smmu_peri_clk;
+ struct clk *smmu_clk;
+ struct clk *media_sc_clk;
+ size_t page_size;
+ spinlock_t spinlock; /*spinlock for tlb invalid*/
+ dma_addr_t pgtable_phy;
+ void *pgtable_virt;
+};
+
+struct hi6220_domain {
+ struct hi6220_smmu *smmu_dev;
+ struct device *dev;
+ struct iommu_domain io_domain;
+ unsigned long iova_start;
+ unsigned long iova_end;
+};
+
+static struct hi6220_smmu *smmu_dev_handle;
+static unsigned int smmu_regs_value[SMMU_REGS_MAX] = {0};
+static struct iova_domain iova_allocator;
+
+static struct hi6220_domain *to_hi6220_domain(struct iommu_domain *dom
[PATCH V2 3/3] Add dts node for smmu on hi6220 SoC
arm64: dts: Add dts node for hi6220 smmu driver
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3ef33b4 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -5,6 +5,7 @@
*/
#include
+#include
/ {
compatible = "hisilicon,hi6220";
@@ -167,5 +168,19 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ smmu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu_clk",
+ "media_sc_clk",
+ "smmu_peri_clk";
+ #iommu-cells = <1>;
+ };
+
};
};
--
1.9.1
--
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[PATCH V2 1/3] Documentation for system mmu in hi6220 platform.
docs: iommu: Documentation for smmu in hi6220 SoC.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
.../bindings/iommu/hisi,hi6220-iommu.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
new file mode 100644
index 000..93e0701
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
@@ -0,0 +1,52 @@
+Hi6220 SoC SMMU Device Driver devicetree document
+===
+The Architecture of SMMU on Hi6220 SoC:
+
+ +--+
+ | |
+ | +-+ ++ +-+ +---+ |
+ | | ADE | | ISP | | V/J codec | | G3D | |
+ | +|+ +---|+ +--|--+ +---|---| |
+ | | | | | |
+ | -v---v--v--v-|
+ | Media Bus |
+ | |---||
+ | | ||
+ | +---v---v+ |
+ | |SMMU| |
+ | +--|-|---+ |
+ || | |
+ +|-|---+
+| |
+ +v-v---+
+ | DDRC|
+ +--+
+
+Note:
+The media system shared the same smmu IP. to access DDR memory. And all
+media IP used the same page table.
+
+Below binding describes the system mmu for media system in hi6220 platform
+
+Required properties:
+- compatible: Should be "hisilicon,hi6220-smmu" example:
+ compatible = "hisilicon,hi6220-smmu";
+- reg: A tuple of base address and size of System MMU registers.
+- interrupts: An interrupt specifier for interrupt signal of System MMU.
+- clocks: The clock used for smmu IP.
+- clock-names: The name to enable clock with clock framework.
+- #iommu-cells: The iommu-cells should be 1 for muti-master to use.
+
+Examples:
+ smmu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu_clk",
+ "media_sc_clk",
+ "smmu_peri_clk";
+ #iommu-cells = <1>;
+ };
--
1.9.1
--
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[PATCH 3/3] Add iommu node for hi6220 SoC platform
arm64: dts: Add dts node for hi6220 smmu driver
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..7ae0984 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,18 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ iommu: iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
};
};
--
1.9.1
--
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[PATCH 2/3] Add iommu driver for hi6220 SoC platform
iommu/hisilicon: Add hi6220-SoC smmu driver
The smmu on hi6220 SoC is for media system.And the
media IP use the same page-table. It supports only
one-to-one mapping from iova to phys address.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
drivers/iommu/Kconfig| 11 +
drivers/iommu/Makefile | 1 +
drivers/iommu/hi6220_iommu.c | 492 +++
3 files changed, 504 insertions(+)
create mode 100644 drivers/iommu/hi6220_iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index cbe6a89..6ca24db 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -342,6 +342,17 @@ config SPAPR_TCE_IOMMU
Enables bits of IOMMU API required by VFIO. The iommu_ops
is not implemented as it is not necessary for VFIO.
+config HI6220_IOMMU
+ bool "Hi6220 IOMMU Support"
+ depends on ARM64
+ select IOMMU_API
+ select IOMMU_IOVA
+ help
+ Enable IOMMU Driver for hi6220 SoC. The IOMMU API and IOMMU IOVA
+ is also selected.
+
+ If unsure, say N.
+
# ARM IOMMU support
config ARM_SMMU
bool "ARM Ltd. System MMU (SMMU) Support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index c6dcc51..db68fb3 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o
obj-$(CONFIG_ARM_SMMU) += arm-smmu.o
obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
obj-$(CONFIG_DMAR_TABLE) += dmar.o
+obj-$(CONFIG_HI6220_IOMMU) += hi6220_iommu.o
obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
diff --git a/drivers/iommu/hi6220_iommu.c b/drivers/iommu/hi6220_iommu.c
new file mode 100644
index 000..47eb390
--- /dev/null
+++ b/drivers/iommu/hi6220_iommu.c
@@ -0,0 +1,492 @@
+/*
+ * Hisilicon Hi6220 IOMMU driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "IOMMU: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SMMU_CTRL_OFFSET (0x)
+#define SMMU_ENABLE_OFFSET (0x0004)
+#define SMMU_PTBR_OFFSET (0x0008)
+#define SMMU_START_OFFSET(0x000C)
+#define SMMU_END_OFFSET (0x0010)
+#define SMMU_INTMASK_OFFSET (0x0014)
+#define SMMU_RINTSTS_OFFSET (0x0018)
+#define SMMU_MINTSTS_OFFSET (0x001C)
+#define SMMU_INTCLR_OFFSET (0x0020)
+#define SMMU_STATUS_OFFSET (0x0024)
+#define SMMU_AXIID_OFFSET(0x0028)
+#define SMMU_CNTCTRL_OFFSET (0x002C)
+#define SMMU_TRANSCNT_OFFSET (0x0030)
+#define SMMU_L0TLBHITCNT_OFFSET (0x0034)
+#define SMMU_L1TLBHITCNT_OFFSET (0x0038)
+#define SMMU_WRAPCNT_OFFSET (0x003C)
+#define SMMU_SEC_START_OFFSET(0x0040)
+#define SMMU_SEC_END_OFFSET (0x0044)
+#define SMMU_VERSION_OFFSET (0x0048)
+#define SMMU_IPTSRC_OFFSET (0x004C)
+#define SMMU_IPTPA_OFFSET(0x0050)
+#define SMMU_TRBA_OFFSET (0x0054)
+#define SMMU_BYS_START_OFFSET(0x0058)
+#define SMMU_BYS_END_OFFSET (0x005C)
+#define SMMU_RAM_OFFSET (0x1000)
+
+#define SMMU_CTRL_INVALID(BIT(10))
+#define SMMU_SR_REGS_NUM (15)
+#define SMMU_REGS_SGMT_END (0x60)
+#define PAGE_ENTRY_VALID (0x1)
+#define IOPAGE_SHIFT (12)
+#define IOVA_PFN(addr) ((addr) >> IOPAGE_SHIFT)
+#define IOVA_PAGE_SZ (SZ_4K)
+
+/**
+ * The iova address from 0 ~ 2G
+ */
+#define IOVA_START (0x0)
+#define IOVA_END (0x8000)
+
+struct hi6220_smmu {
+ unsigned int irq;
+ void __iomem *reg_base;
+ struct clk *smmu_peri_clk;
+ struct clk *smmu_clk;
+ struct clk *media_sc_clk;
+ spinlock_t spinlock; /*spinlock for tlb invalid*/
+ dma_addr_t pgtable_phy;
+ void *pgtable_virt;
+ u32 pgtable_size;
+ u32 *sr_data;
+};
+
+struct hi6220_domain {
+ struct hi6220_smmu *smmu_dev;
+ struct iommu_domain io_domain;
+};
+
+static struct hi6220_smmu *smmu_dev_handle;
+static struct iova_domain iova_allocator;
+
+static struct hi6220_domain *to_hi6220_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct hi6220_domain, io_domain);
+}
+
+static inline void __smmu_writel(struct hi6220_smmu *smmu_dev, u32 value,
+unsigned long offset)
+{
+ writel(value, smmu_dev->reg_base + offset);
+}
+
+static inl
[PATCH 1/3] bindings for hisilicon hi6220 iommu driver
docs: iommu: Documentation for iommu in hi6220 SoC.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
.../bindings/iommu/hisi,hi6220-iommu.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
new file mode 100644
index 000..756e64f
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
@@ -0,0 +1,56 @@
+Hi6220 SoC SMMU Device Driver devicetree document
+===
+The Architecture of SMMU on Hi6220 SoC:
+
+ +--+
+ | |
+ | +-+ ++ +-+ +---+ |
+ | | ADE | | ISP | | V/J codec | | G3D | |
+ | +|+ +---|+ +--|--+ +---|---| |
+ | | | | | |
+ | -v---v--v--v-|
+ | Media Bus |
+ | |---||
+ | | ||
+ | +---v---v+ |
+ | |SMMU| |
+ | +--|-|---+ |
+ || | |
+ +|-|---+
+| |
+ +v-v---+
+ | DDRC|
+ +--+
+
+Note:
+The media system shared the same smmu IP to access DDR memory. And all
+media IP used the same page table.
+
+Below binding describes the system mmu for media system in hi6220 platform
+
+Required properties:
+- compatible: should contain "hisilicon,hi6220-smmu".
+- reg: A tuple of base address and size of System MMU registers.
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+ in clock-names.
+- clock-names: should contain:
+ * "smmu"
+ * "media-sc"
+ * "smmu-peri"
+- interrupts: An interrupt specifier for interrupt signal of System MMU.
+- #iommu-cells: The iommu-cells should be 0. Because no additional information
+ needs to be encoded in the specifier.
+
+Examples:
+ iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
--
1.9.1
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[PATCH V3 RESEND 1/3] bindings for hisilicon hi6220 iommu driver
docs: iommu: Documentation for iommu in hi6220 SoC.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
.../bindings/iommu/hisi,hi6220-iommu.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
new file mode 100644
index 000..756e64f
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
@@ -0,0 +1,56 @@
+Hi6220 SoC SMMU Device Driver devicetree document
+===
+The Architecture of SMMU on Hi6220 SoC:
+
+ +--+
+ | |
+ | +-+ ++ +-+ +---+ |
+ | | ADE | | ISP | | V/J codec | | G3D | |
+ | +|+ +---|+ +--|--+ +---|---| |
+ | | | | | |
+ | -v---v--v--v-|
+ | Media Bus |
+ | |---||
+ | | ||
+ | +---v---v+ |
+ | |SMMU| |
+ | +--|-|---+ |
+ || | |
+ +|-|---+
+| |
+ +v-v---+
+ | DDRC|
+ +--+
+
+Note:
+The media system shared the same smmu IP to access DDR memory. And all
+media IP used the same page table.
+
+Below binding describes the system mmu for media system in hi6220 platform
+
+Required properties:
+- compatible: should contain "hisilicon,hi6220-smmu".
+- reg: A tuple of base address and size of System MMU registers.
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+ in clock-names.
+- clock-names: should contain:
+ * "smmu"
+ * "media-sc"
+ * "smmu-peri"
+- interrupts: An interrupt specifier for interrupt signal of System MMU.
+- #iommu-cells: The iommu-cells should be 0. Because no additional information
+ needs to be encoded in the specifier.
+
+Examples:
+ iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
--
1.9.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH V3 RESEND 3/3] Add iommu node for hi6220 SoC platform
arm64: dts: Add dts node for hi6220 smmu driver
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..7ae0984 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,18 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ iommu: iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
};
};
--
1.9.1
--
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[PATCH V3 RESEND 2/3] Add iommu driver for hi6220 SoC platform
iommu/hisilicon: Add hi6220-SoC smmu driver
The smmu on hi6220 SoC is for media system.And the
media IP use the same page-table. It supports only
one-to-one mapping from iova to phys address.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
drivers/iommu/Kconfig| 11 +
drivers/iommu/Makefile | 1 +
drivers/iommu/hi6220_iommu.c | 492 +++
3 files changed, 504 insertions(+)
create mode 100644 drivers/iommu/hi6220_iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index cbe6a89..6ca24db 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -342,6 +342,17 @@ config SPAPR_TCE_IOMMU
Enables bits of IOMMU API required by VFIO. The iommu_ops
is not implemented as it is not necessary for VFIO.
+config HI6220_IOMMU
+ bool "Hi6220 IOMMU Support"
+ depends on ARM64
+ select IOMMU_API
+ select IOMMU_IOVA
+ help
+ Enable IOMMU Driver for hi6220 SoC. The IOMMU API and IOMMU IOVA
+ is also selected.
+
+ If unsure, say N.
+
# ARM IOMMU support
config ARM_SMMU
bool "ARM Ltd. System MMU (SMMU) Support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index c6dcc51..db68fb3 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o
obj-$(CONFIG_ARM_SMMU) += arm-smmu.o
obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
obj-$(CONFIG_DMAR_TABLE) += dmar.o
+obj-$(CONFIG_HI6220_IOMMU) += hi6220_iommu.o
obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
diff --git a/drivers/iommu/hi6220_iommu.c b/drivers/iommu/hi6220_iommu.c
new file mode 100644
index 000..47eb390
--- /dev/null
+++ b/drivers/iommu/hi6220_iommu.c
@@ -0,0 +1,492 @@
+/*
+ * Hisilicon Hi6220 IOMMU driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "IOMMU: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SMMU_CTRL_OFFSET (0x)
+#define SMMU_ENABLE_OFFSET (0x0004)
+#define SMMU_PTBR_OFFSET (0x0008)
+#define SMMU_START_OFFSET(0x000C)
+#define SMMU_END_OFFSET (0x0010)
+#define SMMU_INTMASK_OFFSET (0x0014)
+#define SMMU_RINTSTS_OFFSET (0x0018)
+#define SMMU_MINTSTS_OFFSET (0x001C)
+#define SMMU_INTCLR_OFFSET (0x0020)
+#define SMMU_STATUS_OFFSET (0x0024)
+#define SMMU_AXIID_OFFSET(0x0028)
+#define SMMU_CNTCTRL_OFFSET (0x002C)
+#define SMMU_TRANSCNT_OFFSET (0x0030)
+#define SMMU_L0TLBHITCNT_OFFSET (0x0034)
+#define SMMU_L1TLBHITCNT_OFFSET (0x0038)
+#define SMMU_WRAPCNT_OFFSET (0x003C)
+#define SMMU_SEC_START_OFFSET(0x0040)
+#define SMMU_SEC_END_OFFSET (0x0044)
+#define SMMU_VERSION_OFFSET (0x0048)
+#define SMMU_IPTSRC_OFFSET (0x004C)
+#define SMMU_IPTPA_OFFSET(0x0050)
+#define SMMU_TRBA_OFFSET (0x0054)
+#define SMMU_BYS_START_OFFSET(0x0058)
+#define SMMU_BYS_END_OFFSET (0x005C)
+#define SMMU_RAM_OFFSET (0x1000)
+
+#define SMMU_CTRL_INVALID(BIT(10))
+#define SMMU_SR_REGS_NUM (15)
+#define SMMU_REGS_SGMT_END (0x60)
+#define PAGE_ENTRY_VALID (0x1)
+#define IOPAGE_SHIFT (12)
+#define IOVA_PFN(addr) ((addr) >> IOPAGE_SHIFT)
+#define IOVA_PAGE_SZ (SZ_4K)
+
+/**
+ * The iova address from 0 ~ 2G
+ */
+#define IOVA_START (0x0)
+#define IOVA_END (0x8000)
+
+struct hi6220_smmu {
+ unsigned int irq;
+ void __iomem *reg_base;
+ struct clk *smmu_peri_clk;
+ struct clk *smmu_clk;
+ struct clk *media_sc_clk;
+ spinlock_t spinlock; /*spinlock for tlb invalid*/
+ dma_addr_t pgtable_phy;
+ void *pgtable_virt;
+ u32 pgtable_size;
+ u32 *sr_data;
+};
+
+struct hi6220_domain {
+ struct hi6220_smmu *smmu_dev;
+ struct iommu_domain io_domain;
+};
+
+static struct hi6220_smmu *smmu_dev_handle;
+static struct iova_domain iova_allocator;
+
+static struct hi6220_domain *to_hi6220_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct hi6220_domain, io_domain);
+}
+
+static inline void __smmu_writel(struct hi6220_smmu *smmu_dev, u32 value,
+unsigned long offset)
+{
+ writel(value, smmu_dev->reg_base + offset);
+}
+
+static inl
[PATCH V5 Base on RC7 2/3] Add reset controller for hi6220 SoC platform.
reset: add driver for hi6220 reset controller
Signed-off-by: Chen Feng
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig| 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 107 +
include/dt-bindings/reset/hisi,hi6220-resets.h | 67
6 files changed, 182 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
create mode 100644 include/dt-bindings/reset/hisi,hi6220-resets.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 85d5904..99e18c8 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
obj-$(CONFIG_ATH79) += reset-ath79.o
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..eac9531
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,107 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ASSERT_OFFSET0x300
+#define DEASSERT_OFFSET 0x304
+#define MAX_INDEX0x509
+
+#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
+
+struct hi6220_reset_data {
+ void __iomem*assert_base;
+ void __iomem*deassert_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->assert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->deassert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int hi6220_reset_probe(struct platform_device *pdev)
+{
+ struct hi6220_reset_data *data;
+ struct resource *res;
+ void __iomem *src_base;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ src_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(src_base))
+ return PTR_ERR(src_base);
+
+ data->assert_base = src_base + ASSERT_OFFSET;
+ data->deassert_base = src_base + DEASSERT_OFFSET;
+ data->rc_dev.nr_resets = MAX_INDEX;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = pdev->dev.of_node;
+
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+}
+
+static const struct of_device_id hi6220_reset_match[] = {
+ { .compatible = "hisilicon,hi6220-reset-ctl" },
+ { },
+};
+
+static struct p
[PATCH V5 Base on RC7 3/3] Add reset controller for hi6220 SoC platform.
reset: add driver for hi6220 reset controller
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3f055e2 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f703 {
+ compatible = "hisilicon,hi6220-reset-ctl";
+ reg = <0x0 0xf703 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH V5 Base on RC7 1/3] Add DT bindings documentation for hi6220 SoC reset controller.
docs: dts: Added documentation for hi6220 Reset Controller
Signed-off-by: Chen Feng
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..02a8dae
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,32 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-reset-ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+reset_ctrl: reset_ctrl@f703 {
+compatible = "hisilicon,hi6220-reset-ctl";
+reg = <0x0 0xf703 0x0 0x1000>;
+#reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: uart1@. {
+...
+resets = <&reset_ctrl 0x305>;
+...
+};
--
1.9.1
--
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Re: [Linaro-mm-sig] [PATCH v3] staging: android: ion: Zero CMA allocated memory
On 2018/1/27 1:48, Liam Mark wrote:
> Since commit 204f672255c2 ("staging: android: ion: Use CMA APIs directly")
> the CMA API is now used directly and therefore the allocated memory is no
> longer automatically zeroed.
>
> Explicitly zero CMA allocated memory to ensure that no data is exposed to
> userspace.
>
> Fixes: 204f672255c2 ("staging: android: ion: Use CMA APIs directly")
> Signed-off-by: Liam Mark
> ---
> Changes in v2:
> - Clean up the commit message.
> - Add 'Fixes:'
>
> Changes in v3:
> - Add support for highmem pages
>
> drivers/staging/android/ion/ion_cma_heap.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/staging/android/ion/ion_cma_heap.c
> b/drivers/staging/android/ion/ion_cma_heap.c
> index 86196ffd2faf..fa3e4b7e0c9f 100644
> --- a/drivers/staging/android/ion/ion_cma_heap.c
> +++ b/drivers/staging/android/ion/ion_cma_heap.c
> @@ -21,6 +21,7 @@
> #include
> #include
> #include
> +#include
>
> #include "ion.h"
>
> @@ -51,6 +52,22 @@ static int ion_cma_allocate(struct ion_heap *heap, struct
> ion_buffer *buffer,
> if (!pages)
> return -ENOMEM;
>
> + if (PageHighMem(pages)) {
> + unsigned long nr_clear_pages = nr_pages;
> + struct page *page = pages;
> +
> + while (nr_clear_pages > 0) {
> + void *vaddr = kmap_atomic(page);
> +
> + memset(vaddr, 0, PAGE_SIZE);
> + kunmap_atomic(vaddr);
Here. This way may cause performance latency at mapping-memset-umap page one
bye one.
Take a look at ion_heap_pages_zero.
Not very critical, arm64 always have linear mapping.
> + page++;
> + nr_clear_pages--;
> + }
> + } else {
> + memset(page_address(pages), 0, size);
> + }
> +
> table = kmalloc(sizeof(*table), GFP_KERNEL);
> if (!table)
> goto err;
>
Re: [PATCH] ION: Sys_heap: fix the incorrect pool->gfp_mask setting
On 2018/1/9 18:43, Zeng Tao wrote:
> This issue is introduced by the commit ("ION: Sys_heap:
> Add cached pool to spead up cached buffer alloc"), the gfp_mask low
> order pool is overlapped by the high order inside the loop, so the
> gfp_mask of all pools are set to high_order_gfp_flags.
>
Thanks
> Signed-off-by: Zeng Tao
> ---
> drivers/staging/android/ion/ion_system_heap.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/android/ion/ion_system_heap.c
> b/drivers/staging/android/ion/ion_system_heap.c
> index 4dc5d7a..b6386be 100644
> --- a/drivers/staging/android/ion/ion_system_heap.c
> +++ b/drivers/staging/android/ion/ion_system_heap.c
> @@ -298,10 +298,10 @@ static int ion_system_heap_create_pools(struct
> ion_page_pool **pools,
> bool cached)
> {
> int i;
> - gfp_t gfp_flags = low_order_gfp_flags;
>
> for (i = 0; i < NUM_ORDERS; i++) {
> struct ion_page_pool *pool;
> + gfp_t gfp_flags = low_order_gfp_flags;
Not define here. Better "gfp_flags = low_order_gfp_flags"
>
> if (orders[i] > 4)
> gfp_flags = high_order_gfp_flags;
>
Re: [PATCH] ION: Sys_heap: Makes ion buffer always alloc from page pool
On 2016/5/6 1:09, Laura Abbott wrote:
> On 05/04/2016 08:27 PM, Chen Feng wrote:
>> Makes the ion buffer always alloced from page pool, no matter
>> it's cached or not. In this way, it can improve the efficiency
>> of it.
>>
>> Currently, there is no difference from cached or non-cached buffer
>> for the page pool.
>
>
> The advantage of the uncached pool was that the pages in the pool
> were always clean in the cache. This is lost here with the addition
> of cached pages to the same pool as uncached pages I agree the
> cache path could benefit from pooling but we need to keep the caching
> model consistent.
>
Yes, the buffer in the pool is non-cached.
I found that the ion don't have a invalid cache ops.
Currently, we use ioctl to keep the cache coherency.
In this way, there is no difference between these.
So, how do you think add a new cached pool in the system heap?
If yes, I can file a new patch to do this.
>>
>> Signed-off-by: Chen Feng
>> ---
>> drivers/staging/android/ion/ion_system_heap.c | 19 ++-
>> 1 file changed, 2 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/staging/android/ion/ion_system_heap.c
>> b/drivers/staging/android/ion/ion_system_heap.c
>> index b69dfc7..caf11fc 100644
>> --- a/drivers/staging/android/ion/ion_system_heap.c
>> +++ b/drivers/staging/android/ion/ion_system_heap.c
>> @@ -56,24 +56,10 @@ static struct page *alloc_buffer_page(struct
>> ion_system_heap *heap,
>>struct ion_buffer *buffer,
>>unsigned long order)
>> {
>> -bool cached = ion_buffer_cached(buffer);
>> struct ion_page_pool *pool = heap->pools[order_to_index(order)];
>> struct page *page;
>>
>> -if (!cached) {
>> -page = ion_page_pool_alloc(pool);
>> -} else {
>> -gfp_t gfp_flags = low_order_gfp_flags;
>> -
>> -if (order > 4)
>> -gfp_flags = high_order_gfp_flags;
>> -page = alloc_pages(gfp_flags | __GFP_COMP, order);
>> -if (!page)
>> -return NULL;
>> -ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
>> -DMA_BIDIRECTIONAL);
>> -}
>> -
>> +page = ion_page_pool_alloc(pool);
>> return page;
>> }
>>
>> @@ -81,9 +67,8 @@ static void free_buffer_page(struct ion_system_heap *heap,
>> struct ion_buffer *buffer, struct page *page)
>> {
>> unsigned int order = compound_order(page);
>> -bool cached = ion_buffer_cached(buffer);
>>
>> -if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
>> +if (!(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
>> struct ion_page_pool *pool = heap->pools[order_to_index(order)];
>>
>> ion_page_pool_free(pool, page);
>>
>
>
> .
>
[PATCH] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Add ion cached pool in system heap.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
---
drivers/staging/android/ion/ion_system_heap.c | 120 +-
1 file changed, 79 insertions(+), 41 deletions(-)
diff --git a/drivers/staging/android/ion/ion_system_heap.c
b/drivers/staging/android/ion/ion_system_heap.c
index b69dfc7..5b7e5b0 100644
--- a/drivers/staging/android/ion/ion_system_heap.c
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -49,7 +49,8 @@ static inline unsigned int order_to_size(int order)
struct ion_system_heap {
struct ion_heap heap;
- struct ion_page_pool *pools[0];
+ struct ion_page_pool *uncached_pools[0];
+ struct ion_page_pool *cached_pools[0];
};
static struct page *alloc_buffer_page(struct ion_system_heap *heap,
@@ -57,39 +58,36 @@ static struct page *alloc_buffer_page(struct
ion_system_heap *heap,
unsigned long order)
{
bool cached = ion_buffer_cached(buffer);
- struct ion_page_pool *pool = heap->pools[order_to_index(order)];
+ struct ion_page_pool *pool;
struct page *page;
- if (!cached) {
- page = ion_page_pool_alloc(pool);
- } else {
- gfp_t gfp_flags = low_order_gfp_flags;
-
- if (order > 4)
- gfp_flags = high_order_gfp_flags;
- page = alloc_pages(gfp_flags | __GFP_COMP, order);
- if (!page)
- return NULL;
- ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
- DMA_BIDIRECTIONAL);
- }
+ if (!cached)
+ pool = heap->uncached_pools[order_to_index(order)];
+ else
+ pool = heap->cached_pools[order_to_index(order)];
+ page = ion_page_pool_alloc(pool);
return page;
}
static void free_buffer_page(struct ion_system_heap *heap,
struct ion_buffer *buffer, struct page *page)
{
+ struct ion_page_pool *pool;
unsigned int order = compound_order(page);
bool cached = ion_buffer_cached(buffer);
- if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
- struct ion_page_pool *pool = heap->pools[order_to_index(order)];
-
- ion_page_pool_free(pool, page);
- } else {
+ if (buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) {
__free_pages(page, order);
+ return;
}
+
+ if (!cached)
+ pool = heap->uncached_pools[order_to_index(order)];
+ else
+ pool = heap->cached_pools[order_to_index(order)];
+
+ ion_page_pool_free(pool, page);
}
@@ -224,9 +222,11 @@ static int ion_system_heap_shrink(struct ion_heap *heap,
gfp_t gfp_mask,
only_scan = 1;
for (i = 0; i < num_orders; i++) {
- struct ion_page_pool *pool = sys_heap->pools[i];
+ struct ion_page_pool *pool = sys_heap->uncached_pools[i];
- nr_freed = ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
+ nr_freed += ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
+ pool = sys_heap->cached_pools[i];
+ nr_freed += ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
nr_total += nr_freed;
if (!only_scan) {
@@ -259,27 +259,69 @@ static int ion_system_heap_debug_show(struct ion_heap
*heap, struct seq_file *s,
struct ion_system_heap,
heap);
int i;
+ struct ion_page_pool *pool;
for (i = 0; i < num_orders; i++) {
- struct ion_page_pool *pool = sys_heap->pools[i];
+ pool = sys_heap->uncached_pools[i];
- seq_printf(s, "%d order %u highmem pages in pool = %lu total\n",
+ seq_printf(s, "%d order %u highmem pages uncached %lu total\n",
pool->high_count, pool->order,
(PAGE_SIZE << pool->order) * pool->high_count);
- seq_printf(s, "%d order %u lowmem pages in pool = %lu total\n",
+ seq_printf(s, "%d order %u lowmem pages uncached %lu total\n",
pool->low_count, pool->order,
(PAGE_SIZE << pool->order) * pool->low_count);
}
+
+ for (i = 0; i < num_orders; i++) {
+ pool = sys_heap->cached_pools[i];
+
+ seq_printf(s, "%d order %u highmem pages cached %lu total\n",
+ pool->high_count, pool->order,
+ (PAGE_SIZE << pool->order) * pool->high_count);
+
Re: [PATCH] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Sorry,the order here is not right, please ignore this patch.
I will RESEND it.
On 2016/5/9 14:24, Chen Feng wrote:
> Add ion cached pool in system heap.
>
> Signed-off-by: Chen Feng
> Signed-off-by: Xia Qing
> ---
> drivers/staging/android/ion/ion_system_heap.c | 120
> +-
> 1 file changed, 79 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/staging/android/ion/ion_system_heap.c
> b/drivers/staging/android/ion/ion_system_heap.c
> index b69dfc7..5b7e5b0 100644
> --- a/drivers/staging/android/ion/ion_system_heap.c
> +++ b/drivers/staging/android/ion/ion_system_heap.c
> @@ -49,7 +49,8 @@ static inline unsigned int order_to_size(int order)
>
> struct ion_system_heap {
> struct ion_heap heap;
> - struct ion_page_pool *pools[0];
> + struct ion_page_pool *uncached_pools[0];
> + struct ion_page_pool *cached_pools[0];
> };
>
> static struct page *alloc_buffer_page(struct ion_system_heap *heap,
> @@ -57,39 +58,36 @@ static struct page *alloc_buffer_page(struct
> ion_system_heap *heap,
> unsigned long order)
> {
> bool cached = ion_buffer_cached(buffer);
> - struct ion_page_pool *pool = heap->pools[order_to_index(order)];
> + struct ion_page_pool *pool;
> struct page *page;
>
> - if (!cached) {
> - page = ion_page_pool_alloc(pool);
> - } else {
> - gfp_t gfp_flags = low_order_gfp_flags;
> -
> - if (order > 4)
> - gfp_flags = high_order_gfp_flags;
> - page = alloc_pages(gfp_flags | __GFP_COMP, order);
> - if (!page)
> - return NULL;
> - ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
> - DMA_BIDIRECTIONAL);
> - }
> + if (!cached)
> + pool = heap->uncached_pools[order_to_index(order)];
> + else
> + pool = heap->cached_pools[order_to_index(order)];
>
> + page = ion_page_pool_alloc(pool);
> return page;
> }
>
> static void free_buffer_page(struct ion_system_heap *heap,
>struct ion_buffer *buffer, struct page *page)
> {
> + struct ion_page_pool *pool;
> unsigned int order = compound_order(page);
> bool cached = ion_buffer_cached(buffer);
>
> - if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
> - struct ion_page_pool *pool = heap->pools[order_to_index(order)];
> -
> - ion_page_pool_free(pool, page);
> - } else {
> + if (buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) {
> __free_pages(page, order);
> + return;
> }
> +
> + if (!cached)
> + pool = heap->uncached_pools[order_to_index(order)];
> + else
> + pool = heap->cached_pools[order_to_index(order)];
> +
> + ion_page_pool_free(pool, page);
> }
>
>
> @@ -224,9 +222,11 @@ static int ion_system_heap_shrink(struct ion_heap *heap,
> gfp_t gfp_mask,
> only_scan = 1;
>
> for (i = 0; i < num_orders; i++) {
> - struct ion_page_pool *pool = sys_heap->pools[i];
> + struct ion_page_pool *pool = sys_heap->uncached_pools[i];
>
> - nr_freed = ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
> + nr_freed += ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
> + pool = sys_heap->cached_pools[i];
> + nr_freed += ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
> nr_total += nr_freed;
>
> if (!only_scan) {
> @@ -259,27 +259,69 @@ static int ion_system_heap_debug_show(struct ion_heap
> *heap, struct seq_file *s,
> struct ion_system_heap,
> heap);
> int i;
> + struct ion_page_pool *pool;
>
> for (i = 0; i < num_orders; i++) {
> - struct ion_page_pool *pool = sys_heap->pools[i];
> + pool = sys_heap->uncached_pools[i];
>
> - seq_printf(s, "%d order %u highmem pages in pool = %lu total\n",
> + seq_printf(s, "%d order %u highmem pages uncached %lu total\n",
> pool->high_count, pool->order,
> (PAGE_SIZE << pool->order) * pool->high_count);
> - seq_printf(s, "%d order %u lowmem pages in pool = %lu total\n",
> + seq_printf(s, "%d order %u lowm
[RESEND PATCH] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Add ion cached pool in system heap.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
Reviewed-by: Fu Jun
---
drivers/staging/android/ion/ion_system_heap.c | 145 +-
1 file changed, 95 insertions(+), 50 deletions(-)
diff --git a/drivers/staging/android/ion/ion_system_heap.c
b/drivers/staging/android/ion/ion_system_heap.c
index b69dfc7..c633252 100644
--- a/drivers/staging/android/ion/ion_system_heap.c
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -49,7 +49,8 @@ static inline unsigned int order_to_size(int order)
struct ion_system_heap {
struct ion_heap heap;
- struct ion_page_pool *pools[0];
+ struct ion_page_pool *uncached_pools[0];
+ struct ion_page_pool *cached_pools[0];
};
static struct page *alloc_buffer_page(struct ion_system_heap *heap,
@@ -57,39 +58,36 @@ static struct page *alloc_buffer_page(struct
ion_system_heap *heap,
unsigned long order)
{
bool cached = ion_buffer_cached(buffer);
- struct ion_page_pool *pool = heap->pools[order_to_index(order)];
+ struct ion_page_pool *pool;
struct page *page;
- if (!cached) {
- page = ion_page_pool_alloc(pool);
- } else {
- gfp_t gfp_flags = low_order_gfp_flags;
-
- if (order > 4)
- gfp_flags = high_order_gfp_flags;
- page = alloc_pages(gfp_flags | __GFP_COMP, order);
- if (!page)
- return NULL;
- ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
- DMA_BIDIRECTIONAL);
- }
+ if (!cached)
+ pool = heap->uncached_pools[order_to_index(order)];
+ else
+ pool = heap->cached_pools[order_to_index(order)];
+ page = ion_page_pool_alloc(pool);
return page;
}
static void free_buffer_page(struct ion_system_heap *heap,
struct ion_buffer *buffer, struct page *page)
{
+ struct ion_page_pool *pool;
unsigned int order = compound_order(page);
bool cached = ion_buffer_cached(buffer);
- if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
- struct ion_page_pool *pool = heap->pools[order_to_index(order)];
-
- ion_page_pool_free(pool, page);
- } else {
+ if (buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) {
__free_pages(page, order);
+ return;
}
+
+ if (!cached)
+ pool = heap->uncached_pools[order_to_index(order)];
+ else
+ pool = heap->cached_pools[order_to_index(order)];
+
+ ion_page_pool_free(pool, page);
}
@@ -186,11 +184,10 @@ static void ion_system_heap_free(struct ion_buffer
*buffer)
int i;
/*
-* uncached pages come from the page pools, zero them before returning
-* for security purposes (other allocations are zerod at
-* alloc time
+* zero the buffer before returning for security purposes
+* (other allocations are zerod at alloc time)
*/
- if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE))
+ if (!(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE))
ion_heap_buffer_zero(buffer);
for_each_sg(table->sgl, sg, table->nents, i)
@@ -224,19 +221,29 @@ static int ion_system_heap_shrink(struct ion_heap *heap,
gfp_t gfp_mask,
only_scan = 1;
for (i = 0; i < num_orders; i++) {
- struct ion_page_pool *pool = sys_heap->pools[i];
-
- nr_freed = ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
- nr_total += nr_freed;
+ struct ion_page_pool *pool = sys_heap->uncached_pools[i];
if (!only_scan) {
+ nr_freed = ion_page_pool_shrink(pool, gfp_mask,
+ nr_to_scan);
+ nr_to_scan -= nr_freed;
+ nr_total += nr_freed;
+ pool = sys_heap->cached_pools[i];
+ nr_freed = ion_page_pool_shrink(pool, gfp_mask,
+ nr_to_scan);
nr_to_scan -= nr_freed;
- /* shrink completed */
+ nr_total += nr_freed;
if (nr_to_scan <= 0)
break;
+ } else {
+ nr_freed = ion_page_pool_shrink(pool, gfp_mask,
+ nr_to_scan);
+ nr_total += nr_freed;
+ nr_freed = ion_page_pool_shrink(pool, gfp_mask,
+
[PATCH v1] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Add ion cached pool in system heap. This patch add a cached pool
in system heap. It has a great improvement of alloc for cached
buffer.
v1: Makes the cached buffer zeroed before going to pool
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
Reviewed-by: Fu Jun
---
drivers/staging/android/ion/ion_system_heap.c | 155 +-
1 file changed, 103 insertions(+), 52 deletions(-)
diff --git a/drivers/staging/android/ion/ion_system_heap.c
b/drivers/staging/android/ion/ion_system_heap.c
index b69dfc7..4b14a0b 100644
--- a/drivers/staging/android/ion/ion_system_heap.c
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -49,47 +49,55 @@ static inline unsigned int order_to_size(int order)
struct ion_system_heap {
struct ion_heap heap;
- struct ion_page_pool *pools[0];
+ struct ion_page_pool *uncached_pools[0];
+ struct ion_page_pool *cached_pools[0];
};
+/**
+ * The page from page-pool are all zeroed before. We need do cache
+ * clean for cached buffer. The uncached buffer are always non-cached
+ * since it's allocated. So no need for non-cached pages.
+ */
static struct page *alloc_buffer_page(struct ion_system_heap *heap,
struct ion_buffer *buffer,
unsigned long order)
{
bool cached = ion_buffer_cached(buffer);
- struct ion_page_pool *pool = heap->pools[order_to_index(order)];
+ struct ion_page_pool *pool;
struct page *page;
- if (!cached) {
- page = ion_page_pool_alloc(pool);
- } else {
- gfp_t gfp_flags = low_order_gfp_flags;
+ if (!cached)
+ pool = heap->uncached_pools[order_to_index(order)];
+ else
+ pool = heap->cached_pools[order_to_index(order)];
- if (order > 4)
- gfp_flags = high_order_gfp_flags;
- page = alloc_pages(gfp_flags | __GFP_COMP, order);
- if (!page)
- return NULL;
- ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
- DMA_BIDIRECTIONAL);
- }
+ page = ion_page_pool_alloc(pool);
+ if (cached)
+ ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
+ DMA_BIDIRECTIONAL);
return page;
}
static void free_buffer_page(struct ion_system_heap *heap,
struct ion_buffer *buffer, struct page *page)
{
+ struct ion_page_pool *pool;
unsigned int order = compound_order(page);
bool cached = ion_buffer_cached(buffer);
- if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
- struct ion_page_pool *pool = heap->pools[order_to_index(order)];
-
- ion_page_pool_free(pool, page);
- } else {
+ /* go to system */
+ if (buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) {
__free_pages(page, order);
+ return;
}
+
+ if (!cached)
+ pool = heap->uncached_pools[order_to_index(order)];
+ else
+ pool = heap->cached_pools[order_to_index(order)];
+
+ ion_page_pool_free(pool, page);
}
@@ -181,16 +189,11 @@ static void ion_system_heap_free(struct ion_buffer
*buffer)
struct ion_system_heap,
heap);
struct sg_table *table = buffer->sg_table;
- bool cached = ion_buffer_cached(buffer);
struct scatterlist *sg;
int i;
- /*
-* uncached pages come from the page pools, zero them before returning
-* for security purposes (other allocations are zerod at
-* alloc time
-*/
- if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE))
+ /* zero the buffer before goto page pool */
+ if (!(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE))
ion_heap_buffer_zero(buffer);
for_each_sg(table->sgl, sg, table->nents, i)
@@ -224,19 +227,29 @@ static int ion_system_heap_shrink(struct ion_heap *heap,
gfp_t gfp_mask,
only_scan = 1;
for (i = 0; i < num_orders; i++) {
- struct ion_page_pool *pool = sys_heap->pools[i];
-
- nr_freed = ion_page_pool_shrink(pool, gfp_mask, nr_to_scan);
- nr_total += nr_freed;
+ struct ion_page_pool *pool = sys_heap->uncached_pools[i];
if (!only_scan) {
+ nr_freed = ion_page_pool_shrink(pool, gfp_mask,
+ nr_to_scan);
nr_to_scan -= nr_freed;
- /* shrink completed */
+
Re: [RESEND PATCH] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Hi Greg, Please see my v1 version for detail. Thank you. On 2016年05月09日 17:02, Greg KH wrote: > On Mon, May 09, 2016 at 04:37:34PM +0800, Chen Feng wrote: >> Add ion cached pool in system heap. >> >> Signed-off-by: Chen Feng >> Signed-off-by: Xia Qing >> Reviewed-by: Fu Jun >> --- >> drivers/staging/android/ion/ion_system_heap.c | 145 >> +- >> 1 file changed, 95 insertions(+), 50 deletions(-) > > You didn't list what changed here. Please do so, otherwise we think > it's identical to the previous patch you sent :( > > thanks, > > greg k-h >
Re: [RESEND PATCH] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Hi Laura,
On 2016/5/10 7:50, Laura Abbott wrote:
> On 05/09/2016 01:37 AM, Chen Feng wrote:
>> Add ion cached pool in system heap.
>>
>> Signed-off-by: Chen Feng
>> Signed-off-by: Xia Qing
>> Reviewed-by: Fu Jun
>> ---
>> drivers/staging/android/ion/ion_system_heap.c | 145
>> +-
>> 1 file changed, 95 insertions(+), 50 deletions(-)
>>
>> diff --git a/drivers/staging/android/ion/ion_system_heap.c
>> b/drivers/staging/android/ion/ion_system_heap.c
>> index b69dfc7..c633252 100644
>> --- a/drivers/staging/android/ion/ion_system_heap.c
>> +++ b/drivers/staging/android/ion/ion_system_heap.c
>> @@ -49,7 +49,8 @@ static inline unsigned int order_to_size(int order)
>>
>> struct ion_system_heap {
>> struct ion_heap heap;
>> -struct ion_page_pool *pools[0];
>> +struct ion_page_pool *uncached_pools[0];
>> +struct ion_page_pool *cached_pools[0];
>> };
>>
>> static struct page *alloc_buffer_page(struct ion_system_heap *heap,
>> @@ -57,39 +58,36 @@ static struct page *alloc_buffer_page(struct
>> ion_system_heap *heap,
>>unsigned long order)
>> {
>> bool cached = ion_buffer_cached(buffer);
>> -struct ion_page_pool *pool = heap->pools[order_to_index(order)];
>> +struct ion_page_pool *pool;
>> struct page *page;
>>
>> -if (!cached) {
>> -page = ion_page_pool_alloc(pool);
>> -} else {
>> -gfp_t gfp_flags = low_order_gfp_flags;
>> -
>> -if (order > 4)
>> -gfp_flags = high_order_gfp_flags;
>> -page = alloc_pages(gfp_flags | __GFP_COMP, order);
>> -if (!page)
>> -return NULL;
>> -ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
>> -DMA_BIDIRECTIONAL);
>> -}
>> +if (!cached)
>> +pool = heap->uncached_pools[order_to_index(order)];
>> +else
>> +pool = heap->cached_pools[order_to_index(order)];
>>
>> +page = ion_page_pool_alloc(pool);
>> return page;
>> }
>>
>
> This is a change in behavior. The page is no longer guaranteed to be synced
> in the cache. If the page came from the pool (not just freshly allocated)
> the cache state is unknown. Do you have a good explanation why we no longer
> need to do the cache flush here on every allocation?
>
Yes, no more explanation here.
Please see my v1[1] version.
Thanks for review!
[1] http://thread.gmane.org/gmane.linux.kernel/2217505
> Thanks,
> Laura
>
> .
>
[PATCH] ION: Sys_heap: Makes ion buffer always alloc from page pool
Makes the ion buffer always alloced from page pool, no matter
it's cached or not. In this way, it can improve the efficiency
of it.
Currently, there is no difference from cached or non-cached buffer
for the page pool.
Signed-off-by: Chen Feng
---
drivers/staging/android/ion/ion_system_heap.c | 19 ++-
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/android/ion/ion_system_heap.c
b/drivers/staging/android/ion/ion_system_heap.c
index b69dfc7..caf11fc 100644
--- a/drivers/staging/android/ion/ion_system_heap.c
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -56,24 +56,10 @@ static struct page *alloc_buffer_page(struct
ion_system_heap *heap,
struct ion_buffer *buffer,
unsigned long order)
{
- bool cached = ion_buffer_cached(buffer);
struct ion_page_pool *pool = heap->pools[order_to_index(order)];
struct page *page;
- if (!cached) {
- page = ion_page_pool_alloc(pool);
- } else {
- gfp_t gfp_flags = low_order_gfp_flags;
-
- if (order > 4)
- gfp_flags = high_order_gfp_flags;
- page = alloc_pages(gfp_flags | __GFP_COMP, order);
- if (!page)
- return NULL;
- ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
- DMA_BIDIRECTIONAL);
- }
-
+ page = ion_page_pool_alloc(pool);
return page;
}
@@ -81,9 +67,8 @@ static void free_buffer_page(struct ion_system_heap *heap,
struct ion_buffer *buffer, struct page *page)
{
unsigned int order = compound_order(page);
- bool cached = ion_buffer_cached(buffer);
- if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
+ if (!(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
struct ion_page_pool *pool = heap->pools[order_to_index(order)];
ion_page_pool_free(pool, page);
--
1.9.1
Re: [PATCH v1] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
On 2016/5/11 6:48, Laura Abbott wrote:
> On 05/09/2016 04:35 AM, Chen Feng wrote:
>> Add ion cached pool in system heap. This patch add a cached pool
>> in system heap. It has a great improvement of alloc for cached
>> buffer.
>>
>
> Can you give some benchmark numbers here?
>
ok, My test is using iontest userspace.
I will share the result next version.
By the way, which benchmark you prefer to use for ION test?
>> v1: Makes the cached buffer zeroed before going to pool
>>
>> Signed-off-by: Chen Feng
>> Signed-off-by: Xia Qing
>> Reviewed-by: Fu Jun
>> ---
>> drivers/staging/android/ion/ion_system_heap.c | 155
>> +-
>> 1 file changed, 103 insertions(+), 52 deletions(-)
>>
>> diff --git a/drivers/staging/android/ion/ion_system_heap.c
>> b/drivers/staging/android/ion/ion_system_heap.c
>> index b69dfc7..4b14a0b 100644
>> --- a/drivers/staging/android/ion/ion_system_heap.c
>> +++ b/drivers/staging/android/ion/ion_system_heap.c
>> @@ -49,47 +49,55 @@ static inline unsigned int order_to_size(int order)
>>
>> struct ion_system_heap {
>> struct ion_heap heap;
>> -struct ion_page_pool *pools[0];
>> +struct ion_page_pool *uncached_pools[0];
>> +struct ion_page_pool *cached_pools[0];
>> };
>>
>
>
> I don't think this is correct based on
> https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
> and some discussions with others. Their tests showed this may just result in
> the
> two struct members aliasing, which is not what we want.
>
> The flexible array isn't really necessary here anyway. The number of orders
> we want
> is known at compile time and
>
Yes, change this latter.
> -static const int num_orders = ARRAY_SIZE(orders);
> +
> +#define NUM_ORDERS ARRAY_SIZE(orders)
> +
>
> should let the NUM_ORDERS be used as a constant initializer in the struct.
>
ok.
>> +/**
>> + * The page from page-pool are all zeroed before. We need do cache
>> + * clean for cached buffer. The uncached buffer are always non-cached
>> + * since it's allocated. So no need for non-cached pages.
>> + */
>> static struct page *alloc_buffer_page(struct ion_system_heap *heap,
>>struct ion_buffer *buffer,
>>unsigned long order)
>> {
>> bool cached = ion_buffer_cached(buffer);
>> -struct ion_page_pool *pool = heap->pools[order_to_index(order)];
>> +struct ion_page_pool *pool;
>> struct page *page;
>>
>> -if (!cached) {
>> -page = ion_page_pool_alloc(pool);
>> -} else {
>> -gfp_t gfp_flags = low_order_gfp_flags;
>> +if (!cached)
>> +pool = heap->uncached_pools[order_to_index(order)];
>> +else
>> +pool = heap->cached_pools[order_to_index(order)];
>>
>> -if (order > 4)
>> -gfp_flags = high_order_gfp_flags;
>> -page = alloc_pages(gfp_flags | __GFP_COMP, order);
>> -if (!page)
>> -return NULL;
>> -ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
>> -DMA_BIDIRECTIONAL);
>> -}
>> +page = ion_page_pool_alloc(pool);
>>
>> +if (cached)
>> +ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
>> + DMA_BIDIRECTIONAL);
>> return page;
>> }
>>
>
> This is doing an extra sync for newly allocated pages. If the buffer was
> just allocated the sync should be skipped.
>
Yes, if we want not to do this extra sync for newly allocated pages.
I will add a new parameter in the ion page-pool to distinguish from
it's cached or not.
>> static void free_buffer_page(struct ion_system_heap *heap,
>> struct ion_buffer *buffer, struct page *page)
>> {
>> +struct ion_page_pool *pool;
>> unsigned int order = compound_order(page);
>> bool cached = ion_buffer_cached(buffer);
>>
>> -if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) {
>> -struct ion_page_pool *pool = heap->pools[order_to_index(order)];
>> -
>> -ion_page_pool_free(pool, page);
>> -} else {
>> +/* go to system */
>> +if (buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) {
>> __free_pages(page, order);
>> +return;
>> }
>> +
>> +if (!cached)
>> +pool = heap->uncached_pools[order_to_index(order)];
>> +
[PATCH] mm: compact: remove watermark check at compact suitable
There are two paths calling this function. For direct compact, there is no need to check the zone watermark here. For kswapd wakeup kcompactd, since there is a reclaim before this. It makes sense to do compact even the watermark is ok at this time. Signed-off-by: Chen Feng --- mm/compaction.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/mm/compaction.c b/mm/compaction.c index 8fa2540..cb322df 100644 --- a/mm/compaction.c +++ b/mm/compaction.c @@ -1260,13 +1260,6 @@ static unsigned long __compaction_suitable(struct zone *zone, int order, return COMPACT_CONTINUE; watermark = low_wmark_pages(zone); - /* -* If watermarks for high-order allocation are already met, there -* should be no need for compaction at all. -*/ - if (zone_watermark_ok(zone, order, watermark, classzone_idx, - alloc_flags)) - return COMPACT_PARTIAL; /* * Watermarks for order-0 must be met for compaction. Note the 2UL. -- 1.9.1
[PATCH v2] ION: Sys_heap: Add cached pool to spead up cached buffer alloc
Add ion cached pool in system heap. This patch add a cached pool
in system heap. It has a great improvement of alloc for cached
buffer.
With memory pressue alloc test 800MB in userspace used iontest.
The result avg is 577ms. Without patch it's avg is about 883ms.
v1: Makes the cached buffer zeroed before going to pool
v2: Add cached param in pool to distinguish wheather need to flush
cache at a fresh alloc.
Rework the shrink function.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
Reviewed-by: Fu Jun
---
drivers/staging/android/ion/ion_page_pool.c | 10 +-
drivers/staging/android/ion/ion_priv.h| 5 +-
drivers/staging/android/ion/ion_system_heap.c | 183 +-
3 files changed, 133 insertions(+), 65 deletions(-)
diff --git a/drivers/staging/android/ion/ion_page_pool.c
b/drivers/staging/android/ion/ion_page_pool.c
index 1fe8016..2c5e5c5 100644
--- a/drivers/staging/android/ion/ion_page_pool.c
+++ b/drivers/staging/android/ion/ion_page_pool.c
@@ -30,8 +30,9 @@ static void *ion_page_pool_alloc_pages(struct ion_page_pool
*pool)
if (!page)
return NULL;
- ion_pages_sync_for_device(NULL, page, PAGE_SIZE << pool->order,
- DMA_BIDIRECTIONAL);
+ if (!pool->cached)
+ ion_pages_sync_for_device(NULL, page, PAGE_SIZE << pool->order,
+ DMA_BIDIRECTIONAL);
return page;
}
@@ -147,7 +148,8 @@ int ion_page_pool_shrink(struct ion_page_pool *pool, gfp_t
gfp_mask,
return freed;
}
-struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order)
+struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order,
+ bool cached)
{
struct ion_page_pool *pool = kmalloc(sizeof(*pool), GFP_KERNEL);
@@ -161,6 +163,8 @@ struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask,
unsigned int order)
pool->order = order;
mutex_init(&pool->mutex);
plist_node_init(&pool->list, order);
+ if (cached)
+ pool->cached = true;
return pool;
}
diff --git a/drivers/staging/android/ion/ion_priv.h
b/drivers/staging/android/ion/ion_priv.h
index 0239883..f3cb8b4 100644
--- a/drivers/staging/android/ion/ion_priv.h
+++ b/drivers/staging/android/ion/ion_priv.h
@@ -360,6 +360,7 @@ void ion_carveout_free(struct ion_heap *heap,
ion_phys_addr_t addr,
* @gfp_mask: gfp_mask to use from alloc
* @order: order of pages in the pool
* @list: plist node for list of pools
+ * @cached:it's cached pool or not
*
* Allows you to keep a pool of pre allocated pages to use from your heap.
* Keeping a pool of pages that is ready for dma, ie any cached mapping have
@@ -369,6 +370,7 @@ void ion_carveout_free(struct ion_heap *heap,
ion_phys_addr_t addr,
struct ion_page_pool {
int high_count;
int low_count;
+ bool cached;
struct list_head high_items;
struct list_head low_items;
struct mutex mutex;
@@ -377,7 +379,8 @@ struct ion_page_pool {
struct plist_node list;
};
-struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order);
+struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order,
+ bool cached);
void ion_page_pool_destroy(struct ion_page_pool *);
struct page *ion_page_pool_alloc(struct ion_page_pool *);
void ion_page_pool_free(struct ion_page_pool *, struct page *);
diff --git a/drivers/staging/android/ion/ion_system_heap.c
b/drivers/staging/android/ion/ion_system_heap.c
index b69dfc7..32a0ebf 100644
--- a/drivers/staging/android/ion/ion_system_heap.c
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -26,16 +26,18 @@
#include "ion.h"
#include "ion_priv.h"
+#define NUM_ORDERS ARRAY_SIZE(orders)
+
static gfp_t high_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN |
__GFP_NORETRY) & ~__GFP_RECLAIM;
static gfp_t low_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN);
static const unsigned int orders[] = {8, 4, 0};
-static const int num_orders = ARRAY_SIZE(orders);
+
static int order_to_index(unsigned int order)
{
int i;
- for (i = 0; i < num_orders; i++)
+ for (i = 0; i < NUM_ORDERS; i++)
if (order == orders[i])
return i;
BUG();
@@ -49,47 +51,55 @@ static inline unsigned int order_to_size(int order)
struct ion_system_heap {
struct ion_heap heap;
- struct ion_page_pool *pools[0];
+ struct ion_page_pool *uncached_pools[NUM_ORDERS];
+ struct ion_page_pool *cached_pools[NUM_ORDERS];
};
+/**
+ * The page from page-pool are all zeroed before. We need do cache
+ * clean for cached buffer. The u
[PATCH] mm: compact: fix zoneindex in compact
While testing the kcompactd in my platform 3G MEM only DMA ZONE.
I found the kcompactd never wakeup. It seems the zoneindex
has already minus 1 before. So the traverse here should be <=.
Signed-off-by: Chen Feng
---
mm/compaction.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/compaction.c b/mm/compaction.c
index 8fa2540..e5122d9 100644
--- a/mm/compaction.c
+++ b/mm/compaction.c
@@ -1742,7 +1742,7 @@ static bool kcompactd_node_suitable(pg_data_t *pgdat)
struct zone *zone;
enum zone_type classzone_idx = pgdat->kcompactd_classzone_idx;
- for (zoneid = 0; zoneid < classzone_idx; zoneid++) {
+ for (zoneid = 0; zoneid <= classzone_idx; zoneid++) {
zone = &pgdat->node_zones[zoneid];
if (!populated_zone(zone))
--
1.9.1
Re: [PATCH] mm: compact: fix zoneindex in compact
On 2016/5/20 1:45, Vlastimil Babka wrote:
> On 19.5.2016 19:23, Hugh Dickins wrote:
>> On Thu, 19 May 2016, Vlastimil Babka wrote:
>>> On 05/19/2016 02:11 PM, Vlastimil Babka wrote:
>>>> On 05/19/2016 01:58 PM, Chen Feng wrote:
>>>>> While testing the kcompactd in my platform 3G MEM only DMA ZONE.
>>>>> I found the kcompactd never wakeup. It seems the zoneindex
>>>>> has already minus 1 before. So the traverse here should be <=.
>>>>
>>>> Ouch, thanks!
>>>>
>>>>> Signed-off-by: Chen Feng
>>>>
>>>> Fixes: 0f87baf4f7fb ("mm: wake kcompactd before kswapd's short sleep")
>>>
>>> Bah, not that one.
>>>
>>> Fixes: accf62422b3a ("mm, kswapd: replace kswapd compaction with waking
>>> up kcompactd")
>>>
>>>> Cc: sta...@vger.kernel.org
>>>> Acked-by: Vlastimil Babka
>>>>
>>>>> ---
>>>>> mm/compaction.c | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/mm/compaction.c b/mm/compaction.c
>>>>> index 8fa2540..e5122d9 100644
>>>>> --- a/mm/compaction.c
>>>>> +++ b/mm/compaction.c
>>>>> @@ -1742,7 +1742,7 @@ static bool kcompactd_node_suitable(pg_data_t
>>>>> *pgdat)
>>>>> struct zone *zone;
>>>>> enum zone_type classzone_idx = pgdat->kcompactd_classzone_idx;
>>>>>
>>>>> - for (zoneid = 0; zoneid < classzone_idx; zoneid++) {
>>>>> + for (zoneid = 0; zoneid <= classzone_idx; zoneid++) {
>>>>> zone = &pgdat->node_zones[zoneid];
>>>>>
>>>>> if (!populated_zone(zone))
>>
>> Ignorant question: kcompactd_do_work() just below has a similar loop:
>
Yes, my mistake.
> You spelled "Important" wrong.
>
>> should that one be saying "zoneid <= cc.classzone_idx" too?
>
> Yes. Chen, can you send updated patch (also with the ack/cc/fixes tags I
> added?)
>
OK, I will send it out soon.
> Thanks!
>
>> Hugh
>>
>
>
> .
>
Re: [PATCH] mm: compact: fix zoneindex in compact
On 2016/5/20 1:45, Vlastimil Babka wrote:
> On 19.5.2016 19:23, Hugh Dickins wrote:
>> On Thu, 19 May 2016, Vlastimil Babka wrote:
>>> On 05/19/2016 02:11 PM, Vlastimil Babka wrote:
>>>> On 05/19/2016 01:58 PM, Chen Feng wrote:
>>>>> While testing the kcompactd in my platform 3G MEM only DMA ZONE.
>>>>> I found the kcompactd never wakeup. It seems the zoneindex
>>>>> has already minus 1 before. So the traverse here should be <=.
>>>>
>>>> Ouch, thanks!
>>>>
>>>>> Signed-off-by: Chen Feng
>>>>
>>>> Fixes: 0f87baf4f7fb ("mm: wake kcompactd before kswapd's short sleep")
>>>
>>> Bah, not that one.
>>>
>>> Fixes: accf62422b3a ("mm, kswapd: replace kswapd compaction with waking
>>> up kcompactd")
>>>
>>>> Cc: sta...@vger.kernel.org
>>>> Acked-by: Vlastimil Babka
>>>>
>>>>> ---
>>>>> mm/compaction.c | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/mm/compaction.c b/mm/compaction.c
>>>>> index 8fa2540..e5122d9 100644
>>>>> --- a/mm/compaction.c
>>>>> +++ b/mm/compaction.c
>>>>> @@ -1742,7 +1742,7 @@ static bool kcompactd_node_suitable(pg_data_t
>>>>> *pgdat)
>>>>> struct zone *zone;
>>>>> enum zone_type classzone_idx = pgdat->kcompactd_classzone_idx;
>>>>>
>>>>> - for (zoneid = 0; zoneid < classzone_idx; zoneid++) {
>>>>> + for (zoneid = 0; zoneid <= classzone_idx; zoneid++) {
>>>>> zone = &pgdat->node_zones[zoneid];
>>>>>
>>>>> if (!populated_zone(zone))
>>
>> Ignorant question: kcompactd_do_work() just below has a similar loop:
>
> You spelled "Important" wrong.
>
>> should that one be saying "zoneid <= cc.classzone_idx" too?
>
> Yes. Chen, can you send updated patch (also with the ack/cc/fixes tags I
> added?)
>
kcompactd_do_work()
This fix already added by Andrew Morton
I will not sent it.
> Thanks!
>
>> Hugh
>>
>
>
> .
>
Re: [PATCH v3 5/6] mm/cma: remove MIGRATE_CMA
Hi Joonsoo,
On 2016/5/26 14:22, js1...@gmail.com wrote:
> From: Joonsoo Kim
>
> Now, all reserved pages for CMA region are belong to the ZONE_CMA
> and there is no other type of pages. Therefore, we don't need to
> use MIGRATE_CMA to distinguish and handle differently for CMA pages
> and ordinary pages. Remove MIGRATE_CMA.
>
> Unfortunately, this patch make free CMA counter incorrect because
> we count it when pages are on the MIGRATE_CMA. It will be fixed
> by next patch. I can squash next patch here but it makes changes
> complicated and hard to review so I separate that.
>
> Signed-off-by: Joonsoo Kim
> ---
> include/linux/gfp.h| 3 +-
> include/linux/mmzone.h | 22 -
> include/linux/vmstat.h | 8 -
> mm/cma.c | 2 +-
> mm/compaction.c| 10 ++
> mm/hugetlb.c | 2 +-
> mm/page_alloc.c| 87
> +-
> mm/page_isolation.c| 5 ++-
> mm/vmstat.c| 5 +--
> 9 files changed, 31 insertions(+), 113 deletions(-)
>
> diff --git a/include/linux/gfp.h b/include/linux/gfp.h
> index 4d6c008..1a3b869 100644
> --- a/include/linux/gfp.h
> +++ b/include/linux/gfp.h
> @@ -559,8 +559,7 @@ static inline bool pm_suspended_storage(void)
>
> #if (defined(CONFIG_MEMORY_ISOLATION) && defined(CONFIG_COMPACTION)) ||
> defined(CONFIG_CMA)
> /* The below functions must be run on a range from a single zone. */
> -extern int alloc_contig_range(unsigned long start, unsigned long end,
> - unsigned migratetype);
> +extern int alloc_contig_range(unsigned long start, unsigned long end);
> extern void free_contig_range(unsigned long pfn, unsigned nr_pages);
> #endif
>
> diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
> index 54c92a6..236d0bd 100644
> --- a/include/linux/mmzone.h
> +++ b/include/linux/mmzone.h
> @@ -41,22 +41,6 @@ enum {
> MIGRATE_RECLAIMABLE,
> MIGRATE_PCPTYPES, /* the number of types on the pcp lists */
> MIGRATE_HIGHATOMIC = MIGRATE_PCPTYPES,
> -#ifdef CONFIG_CMA
> - /*
> - * MIGRATE_CMA migration type is designed to mimic the way
> - * ZONE_MOVABLE works. Only movable pages can be allocated
> - * from MIGRATE_CMA pageblocks and page allocator never
> - * implicitly change migration type of MIGRATE_CMA pageblock.
> - *
> - * The way to use it is to change migratetype of a range of
> - * pageblocks to MIGRATE_CMA which can be done by
> - * __free_pageblock_cma() function. What is important though
> - * is that a range of pageblocks must be aligned to
> - * MAX_ORDER_NR_PAGES should biggest page be bigger then
> - * a single pageblock.
> - */
> - MIGRATE_CMA,
> -#endif
> #ifdef CONFIG_MEMORY_ISOLATION
> MIGRATE_ISOLATE,/* can't allocate from here */
> #endif
> @@ -66,12 +50,6 @@ enum {
> /* In mm/page_alloc.c; keep in sync also with show_migration_types() there */
> extern char * const migratetype_names[MIGRATE_TYPES];
>
> -#ifdef CONFIG_CMA
> -# define is_migrate_cma(migratetype) unlikely((migratetype) == MIGRATE_CMA)
> -#else
> -# define is_migrate_cma(migratetype) false
> -#endif
> -
> #define for_each_migratetype_order(order, type) \
> for (order = 0; order < MAX_ORDER; order++) \
> for (type = 0; type < MIGRATE_TYPES; type++)
> diff --git a/include/linux/vmstat.h b/include/linux/vmstat.h
> index 0aa613d..e0eb3e5 100644
> --- a/include/linux/vmstat.h
> +++ b/include/linux/vmstat.h
> @@ -264,14 +264,6 @@ static inline void drain_zonestat(struct zone *zone,
> struct per_cpu_pageset *pset) { }
> #endif /* CONFIG_SMP */
>
> -static inline void __mod_zone_freepage_state(struct zone *zone, int nr_pages,
> - int migratetype)
> -{
> - __mod_zone_page_state(zone, NR_FREE_PAGES, nr_pages);
> - if (is_migrate_cma(migratetype))
> - __mod_zone_page_state(zone, NR_FREE_CMA_PAGES, nr_pages);
> -}
> -
> extern const char * const vmstat_text[];
>
> #endif /* _LINUX_VMSTAT_H */
> diff --git a/mm/cma.c b/mm/cma.c
> index 8684f50..bd436e4 100644
> --- a/mm/cma.c
> +++ b/mm/cma.c
> @@ -444,7 +444,7 @@ struct page *cma_alloc(struct cma *cma, size_t count,
> unsigned int align)
>
> pfn = cma->base_pfn + (bitmap_no << cma->order_per_bit);
> mutex_lock(&cma_mutex);
> - ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
> + ret = alloc_contig_range(pfn, pfn + count);
> mutex_unlock(&cma_mutex);
> if (ret == 0) {
> page = pfn_to_page(pfn);
> diff --git a/mm/compaction.c b/mm/compaction.c
> index 1427366..acb1d1a 100644
> --- a/mm/compaction.c
> +++ b/mm/compaction.c
> @@ -76,7 +76,7 @@ static void map_pages(struct list_head *list)
>
> static inline bool migrate_async_suitable(int migratetype)
> {
> - return is_m
[PATCH] firmware: Change the page arrary alloc to vmalloc
No need to use use continuous memory, it may be fail
when memory deeply fragmented.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
---
drivers/base/firmware_class.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c
index 8524450..ff8672d 100644
--- a/drivers/base/firmware_class.c
+++ b/drivers/base/firmware_class.c
@@ -257,7 +257,7 @@ static void __fw_free_buf(struct kref *ref)
vunmap(buf->data);
for (i = 0; i < buf->nr_pages; i++)
__free_page(buf->pages[i]);
- kfree(buf->pages);
+ vfree(buf->pages);
} else
#endif
vfree(buf->data);
@@ -660,7 +660,7 @@ static ssize_t firmware_loading_store(struct device *dev,
if (!test_bit(FW_STATUS_DONE, &fw_buf->status)) {
for (i = 0; i < fw_buf->nr_pages; i++)
__free_page(fw_buf->pages[i]);
- kfree(fw_buf->pages);
+ vfree(fw_buf->pages);
fw_buf->pages = NULL;
fw_buf->page_array_size = 0;
fw_buf->nr_pages = 0;
@@ -770,8 +770,7 @@ static int fw_realloc_buffer(struct firmware_priv *fw_priv,
int min_size)
buf->page_array_size * 2);
struct page **new_pages;
- new_pages = kmalloc(new_array_size * sizeof(void *),
- GFP_KERNEL);
+ new_pages = vmalloc(new_array_size * sizeof(void *));
if (!new_pages) {
fw_load_abort(fw_priv);
return -ENOMEM;
@@ -780,7 +779,7 @@ static int fw_realloc_buffer(struct firmware_priv *fw_priv,
int min_size)
buf->page_array_size * sizeof(void *));
memset(&new_pages[buf->page_array_size], 0, sizeof(void *) *
(new_array_size - buf->page_array_size));
- kfree(buf->pages);
+ vfree(buf->pages);
buf->pages = new_pages;
buf->page_array_size = new_array_size;
}
--
1.9.1
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[PATCH RESEND] firmware: Change the page arrary alloc to vmalloc
No need to use use continuous memory, it may be fail
when memory deeply fragmented.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
---
drivers/base/firmware_class.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c
index 8524450..ff8672d 100644
--- a/drivers/base/firmware_class.c
+++ b/drivers/base/firmware_class.c
@@ -257,7 +257,7 @@ static void __fw_free_buf(struct kref *ref)
vunmap(buf->data);
for (i = 0; i < buf->nr_pages; i++)
__free_page(buf->pages[i]);
- kfree(buf->pages);
+ vfree(buf->pages);
} else
#endif
vfree(buf->data);
@@ -660,7 +660,7 @@ static ssize_t firmware_loading_store(struct device *dev,
if (!test_bit(FW_STATUS_DONE, &fw_buf->status)) {
for (i = 0; i < fw_buf->nr_pages; i++)
__free_page(fw_buf->pages[i]);
- kfree(fw_buf->pages);
+ vfree(fw_buf->pages);
fw_buf->pages = NULL;
fw_buf->page_array_size = 0;
fw_buf->nr_pages = 0;
@@ -770,8 +770,7 @@ static int fw_realloc_buffer(struct firmware_priv *fw_priv,
int min_size)
buf->page_array_size * 2);
struct page **new_pages;
- new_pages = kmalloc(new_array_size * sizeof(void *),
- GFP_KERNEL);
+ new_pages = vmalloc(new_array_size * sizeof(void *));
if (!new_pages) {
fw_load_abort(fw_priv);
return -ENOMEM;
@@ -780,7 +779,7 @@ static int fw_realloc_buffer(struct firmware_priv *fw_priv,
int min_size)
buf->page_array_size * sizeof(void *));
memset(&new_pages[buf->page_array_size], 0, sizeof(void *) *
(new_array_size - buf->page_array_size));
- kfree(buf->pages);
+ vfree(buf->pages);
buf->pages = new_pages;
buf->page_array_size = new_array_size;
}
--
1.9.1
--
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[PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 34 +++
include/dt-bindings/reset/hisi,hi6220-resets.h | 67 ++
2 files changed, 101 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
create mode 100644 include/dt-bindings/reset/hisi,hi6220-resets.h
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..e0b185a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,34 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi6220 SoC.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-sysctrl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+sys_ctrl: sys_ctrl@f703 {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: serial@. {
+...
+resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
+...
+};
+
+The index could be found in .
diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h
b/include/dt-bindings/reset/hisi,hi6220-resets.h
new file mode 100644
index 000..ca08a7e
--- /dev/null
+++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
@@ -0,0 +1,67 @@
+/**
+ * This header provides index for the reset controller
+ * based on hi6220 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
+#define _DT_BINDINGS_RESET_CONTROLLER_HI6220
+
+#define PERIPH_RSTDIS0_MMC0 0x000
+#define PERIPH_RSTDIS0_MMC1 0x001
+#define PERIPH_RSTDIS0_MMC2 0x002
+#define PERIPH_RSTDIS0_NANDC0x003
+#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
+#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
+#define PERIPH_RSTDIS0_USBOTG 0x006
+#define PERIPH_RSTDIS0_USBOTG_32K 0x007
+#define PERIPH_RSTDIS1_HIFI 0x100
+#define PERIPH_RSTDIS1_DIGACODEC0x105
+#define PERIPH_RSTEN2_IPF 0x200
+#define PERIPH_RSTEN2_SOCP 0x201
+#define PERIPH_RSTEN2_DMAC 0x202
+#define PERIPH_RSTEN2_SECENG0x203
+#define PERIPH_RSTEN2_ABB 0x204
+#define PERIPH_RSTEN2_HPM0 0x205
+#define PERIPH_RSTEN2_HPM1 0x206
+#define PERIPH_RSTEN2_HPM2 0x207
+#define PERIPH_RSTEN2_HPM3 0x208
+#define PERIPH_RSTEN3_CSSYS 0x300
+#define PERIPH_RSTEN3_I2C0 0x301
+#define PERIPH_RSTEN3_I2C1 0x302
+#define PERIPH_RSTEN3_I2C2 0x303
+#define PERIPH_RSTEN3_I2C3 0x304
+#define PERIPH_RSTEN3_UART1 0x305
+#define PERIPH_RSTEN3_UART2 0x306
+#define PERIPH_RSTEN3_UART3 0x307
+#define PERIPH_RSTEN3_UART4 0x308
+#define PERIPH_RSTEN3_SSP 0x309
+#define PERIPH_RSTEN3_PWM 0x30a
+#define PERIPH_RSTEN3_BLPWM 0x30b
+#define PERIPH_RSTEN3_TSENSOR 0x30c
+#define PERIPH_RSTEN3_DAPB 0x312
+#define PERIPH_RSTEN3_HKADC 0x313
+#define PERIPH_RSTEN3_CODEC_SSI 0x314
+#define PERIPH_RSTEN3_PMUSSI1 0x316
+#define PERIPH_RSTEN8_RS0 0x400
+#define PERIPH_RSTEN8_RS2 0x401
+#define PERIPH_RSTEN8_RS3 0x402
+#define PERIPH_RSTEN8_MS0 0x403
+#define PERIPH_RSTEN8_MS2 0x405
+#define PERIPH_RSTEN8_XG2RAM0 0x406
+#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407
+#define PERIPH_RSTEN8_SRAM 0x408
+#define PERIPH_RSTEN8_HARQ 0x40a
+#define PERIPH_RSTEN8_DDRC 0x40c
+#define PERIPH_RSTEN8_DDRC_APB 0x40d
+#define PERIPH_RSTEN8_DDRPACK_APB 0x40e
+#define PERIPH_RSTEN8_DDRT 0x411
+#define PERIPH_RSDIST9_CARM_DAP 0x500
+#define PERIPH_RSDIST9_CARM_ATB 0x501
+#define PERIPH_RSDIST9_CARM_LBUS0x502
+#define PERIPH_RSDIST9_CARM_POR 0x503
+#define PERIPH_RSDIST9_CARM_CORE0x504
+#define PERIPH_RSDIST9_CARM_DBG 0x505
+#define PERIPH_RSDIST9_CARM_L2 0x506
+#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
+#define PERIPH_RSDIST9_CARM_ETM 0x508
+
+#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
--
1.9.1
--
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[PATCH V7 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..ad1f1eb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -147,6 +147,7 @@
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf703 0x0 0x2000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
media_ctrl: media_ctrl@f441 {
--
1.9.1
--
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[PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP on hi6220 SoC.
Signed-off-by: Chen Feng
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig| 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 108 +
5 files changed, 116 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 85d5904..99e18c8 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
obj-$(CONFIG_ATH79) += reset-ath79.o
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..d17c910
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,108 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ASSERT_OFFSET0x300
+#define DEASSERT_OFFSET 0x304
+#define MAX_INDEX0x509
+
+#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
+
+struct hi6220_reset_data {
+ void __iomem*assert_base;
+ void __iomem*deassert_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->assert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->deassert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int hi6220_reset_probe(struct platform_device *pdev)
+{
+ struct hi6220_reset_data *data;
+ struct resource *res;
+ void __iomem *src_base;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ src_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(src_base))
+ return PTR_ERR(src_base);
+
+ data->assert_base = src_base + ASSERT_OFFSET;
+ data->deassert_base = src_base + DEASSERT_OFFSET;
+ data->rc_dev.nr_resets = MAX_INDEX;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = pdev->dev.of_node;
+
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+}
+
+static const struct of_device_id hi6220_reset_match[] = {
+ { .compatible = "hisilicon,hi6220-sysctrl" },
+ { },
+};
+
+static struct platform_driver hi6220_reset_driver = {
+ .probe = hi6220_reset_probe,
+ .driver = {
+
[PATCH V5 RESEND 1/3] docs: iommu: Documentation for iommu in hi6220 SoC
Documentation for hi6220 iommu driver.
Signed-off-by: Chen Feng
---
.../bindings/iommu/hisi,hi6220-iommu.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
new file mode 100644
index 000..44f9101
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
@@ -0,0 +1,32 @@
+Hi6220 SoC SMMU Device Driver devicetree document
+The media system shared the same smmu IP to access DDR memory. And all
+media IP used the same page table.
+
+Below binding describes the system mmu for media system in hi6220 platform
+
+Required properties:
+- compatible: should contain "hisilicon,hi6220-smmu".
+- reg: A tuple of base address and size of System MMU registers.
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+ in clock-names.
+- clock-names: should contain:
+ * "smmu"
+ * "media-sc"
+ * "smmu-peri"
+- interrupts: An interrupt specifier for interrupt signal of System MMU.
+- #iommu-cells: The iommu-cells should be 0. Because no additional information
+ needs to be encoded in the specifier.
+
+Examples:
+ iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
--
1.9.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH V5 RESEND 0/3] Add iommu support for hi6220 HiKey board
The patch sets add iommu support for Hi6220 SoC. Current testing and support board is Hikey which is one of 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. The Architecture of SMMU on Hi6220 SoC: +--+ | | | +-+ ++ +-+ +---+ | | | ADE | | ISP | | V/J codec | | G3D | | | +|+ +---|+ +--|--+ +---|---| | | | | | | | | -v---v--v--v-| | Media Bus | | |---|| | | || | +---v---v+ | | |SMMU| | | +--|-|---+ | || | | +|-|---+ | | +v-v---+ | DDRC| +--+ Note: The media system share the same smmu IP to access DDR memory. And all media IP use the same page table. The hi6220 iommu driver also uses the iova api to manage an iova allocator to ensure that the caller get different iova address. The caller can use the follow sample code to map phy and iova address. eg: struct iommu_domain *domain = iommu_domain_alloc(bus); iommu_attach_device(domain, dev); struct iova_domain *iovad = (struct iova_domain *)m_dev->archdata.iommu; struct iova * t_iova = alloc_iova(iovad, size, limit_pfn, align); iommu_map(domain, t_iova->pfn_lo << 12, phy_addr, size, port); The patch sets are based on 4.4-RC1 V2: Fix tlb flush when unmap V3: Fix format issue and iova address range V5: Add cover-letter and resend to dt maillist Chen Feng (3): docs: iommu: Documentation for iommu in hi6220 SoC iommu/hisilicon: Add hi6220-SoC smmu driver arm64: dts: Add dts node for hi6220 smmu driver .../bindings/iommu/hisi,hi6220-iommu.txt | 32 ++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 13 + drivers/iommu/Kconfig | 11 + drivers/iommu/Makefile | 1 + drivers/iommu/hi6220_iommu.c | 492 + 5 files changed, 549 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt create mode 100644 drivers/iommu/hi6220_iommu.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH V5 RESEND 2/3] iommu/hisilicon: Add hi6220-SoC smmu driver
Add iommu driver for hi6220 SoC platform.The smmu on hi6220
SoC is for media system.And the media IP use the same page-table.
It supports only one-to-one mapping from iova to phys address.
Signed-off-by: Chen Feng
---
drivers/iommu/Kconfig| 11 +
drivers/iommu/Makefile | 1 +
drivers/iommu/hi6220_iommu.c | 492 +++
3 files changed, 504 insertions(+)
create mode 100644 drivers/iommu/hi6220_iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index b9094e9..7c13521 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -84,6 +84,17 @@ config IOMMU_PGTABLES_L2
def_bool y
depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n
+config HI6220_IOMMU
+ bool "Hi6220 IOMMU Support"
+ depends on ARM64
+ select IOMMU_API
+ select IOMMU_IOVA
+ help
+ Enable IOMMU Driver for hi6220 SoC. The IOMMU API and IOMMU IOVA
+ is also selected.
+
+ If unsure, say N.
+
# AMD IOMMU support
config AMD_IOMMU
bool "AMD IOMMU support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 68faca02..cdb2b83 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o
obj-$(CONFIG_ARM_SMMU) += arm-smmu.o
obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
obj-$(CONFIG_DMAR_TABLE) += dmar.o
+obj-$(CONFIG_HI6220_IOMMU) += hi6220_iommu.o
obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
obj-$(CONFIG_INTEL_IOMMU_SVM) += intel-svm.o
obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
diff --git a/drivers/iommu/hi6220_iommu.c b/drivers/iommu/hi6220_iommu.c
new file mode 100644
index 000..fd74f29
--- /dev/null
+++ b/drivers/iommu/hi6220_iommu.c
@@ -0,0 +1,492 @@
+/*
+ * Hisilicon Hi6220 IOMMU driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "IOMMU: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SMMU_CTRL_OFFSET (0x)
+#define SMMU_ENABLE_OFFSET (0x0004)
+#define SMMU_PTBR_OFFSET (0x0008)
+#define SMMU_START_OFFSET(0x000C)
+#define SMMU_END_OFFSET (0x0010)
+#define SMMU_INTMASK_OFFSET (0x0014)
+#define SMMU_RINTSTS_OFFSET (0x0018)
+#define SMMU_MINTSTS_OFFSET (0x001C)
+#define SMMU_INTCLR_OFFSET (0x0020)
+#define SMMU_STATUS_OFFSET (0x0024)
+#define SMMU_AXIID_OFFSET(0x0028)
+#define SMMU_CNTCTRL_OFFSET (0x002C)
+#define SMMU_TRANSCNT_OFFSET (0x0030)
+#define SMMU_L0TLBHITCNT_OFFSET (0x0034)
+#define SMMU_L1TLBHITCNT_OFFSET (0x0038)
+#define SMMU_WRAPCNT_OFFSET (0x003C)
+#define SMMU_SEC_START_OFFSET(0x0040)
+#define SMMU_SEC_END_OFFSET (0x0044)
+#define SMMU_VERSION_OFFSET (0x0048)
+#define SMMU_IPTSRC_OFFSET (0x004C)
+#define SMMU_IPTPA_OFFSET(0x0050)
+#define SMMU_TRBA_OFFSET (0x0054)
+#define SMMU_BYS_START_OFFSET(0x0058)
+#define SMMU_BYS_END_OFFSET (0x005C)
+#define SMMU_RAM_OFFSET (0x1000)
+
+#define SMMU_CTRL_INVALID(BIT(10))
+#define SMMU_SR_REGS_NUM (15)
+#define SMMU_REGS_SGMT_END (0x60)
+#define PAGE_ENTRY_VALID (0x1)
+#define IOPAGE_SHIFT (12)
+#define IOVA_PFN(addr) ((addr) >> IOPAGE_SHIFT)
+#define IOVA_PAGE_SZ (SZ_4K)
+
+/**
+ * The iova address from 0 ~ 2G
+ */
+#define IOVA_START (0x0)
+#define IOVA_END (0x8000)
+
+struct hi6220_smmu {
+ unsigned int irq;
+ void __iomem *reg_base;
+ struct clk *smmu_peri_clk;
+ struct clk *smmu_clk;
+ struct clk *media_sc_clk;
+ spinlock_t spinlock; /*spinlock for tlb invalid*/
+ dma_addr_t pgtable_phy;
+ void *pgtable_virt;
+ u32 pgtable_size;
+ u32 *sr_data;
+};
+
+struct hi6220_domain {
+ struct hi6220_smmu *smmu_dev;
+ struct iommu_domain io_domain;
+};
+
+static struct hi6220_smmu *smmu_dev_handle;
+static struct iova_domain iova_allocator;
+
+static struct hi6220_domain *to_hi6220_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct hi6220_domain, io_domain);
+}
+
+static inline void __smmu_writel(struct hi6220_smmu *smmu_dev, u32 value,
+unsigned long offset)
+{
+ writel(value, smmu_dev->reg_base + offset);
+}
+
+static inline u32 __smmu_readl(struct hi6220_smmu *smmu_dev,
+ unsigned l
[PATCH V5 RESEND 3/3] arm64: dts: Add dts node for hi6220 smmu driver
Add iommu node for hi6220 SoC platform
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..589424a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -208,5 +208,18 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ iommu: iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
};
};
--
1.9.1
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[PATCH v3 4/5] regulator: add regulator driver of hi655x PMIC
Add driver support for HiSilicon Hi655x voltage regulators.
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Tested-by: Xinwei Kong
---
drivers/regulator/Kconfig | 8 +
drivers/regulator/Makefile | 1 +
drivers/regulator/hi655x-regulator.c | 246 +
include/linux/regulator/hi655x-regulator.h | 41 +
4 files changed, 296 insertions(+)
create mode 100644 drivers/regulator/hi655x-regulator.c
create mode 100644 include/linux/regulator/hi655x-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 8df0b0e..c6ecfd7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -261,6 +261,14 @@ config REGULATOR_HI6421
21 general purpose LDOs, 3 dedicated LDOs, and 5 BUCKs. All
of them come with support to either ECO (idle) or sleep mode.
+config REGULATOR_HI655X
+ tristate "Hisilicon HI655X PMIC regulators support"
+ depends on ARCH_HISI
+ depends on MFD_HI655X_PMIC && OF
+ help
+ This driver provides support for the voltage regulators of the
+ Hisilicon Hi655x PMIC device.
+
config REGULATOR_ISL9305
tristate "Intersil ISL9305 regulator"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 0f81749..8e4db96 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o
obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
+obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o
obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
diff --git a/drivers/regulator/hi655x-regulator.c
b/drivers/regulator/hi655x-regulator.c
new file mode 100644
index 000..e222ee7
--- /dev/null
+++ b/drivers/regulator/hi655x-regulator.c
@@ -0,0 +1,246 @@
+/*
+ * Device driver for regulators in hi655x IC
+ *
+ * Copyright (c) 2015 Hisilicon.
+ *
+ * Chen Feng
+ * Fei Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int hi655x_is_enabled(struct regulator_dev *rdev)
+{
+ unsigned int value = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = ®ulator->ctrl_regs;
+
+ regmap_read(rdev->regmap, ctrl_regs->status_reg, &value);
+ return (value & BIT(regulator->ctrl_mask));
+}
+
+static int hi655x_disable(struct regulator_dev *rdev)
+{
+ int ret = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = ®ulator->ctrl_regs;
+
+ ret = regmap_write(rdev->regmap, ctrl_regs->disable_reg,
+ BIT(regulator->ctrl_mask));
+ return ret;
+}
+
+static int hi655x_get_voltage(struct regulator_dev *rdev)
+{
+ unsigned int value = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ regmap_read(rdev->regmap, regulator->vset_reg, &value);
+ value &= regulator->vset_mask;
+
+ return regulator->rdesc.volt_table[value];
+}
+
+static int hi655x_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ int i = 0;
+ int vol = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ /**
+* search the matched vol and get its index
+*/
+ for (i = 0; i < regulator->rdesc.n_voltages; i++) {
+ vol = regulator->rdesc.volt_table[i];
+ if ((vol >= min_uV) && (vol <= max_uV))
+ break;
+ }
+
+ if (i == regulator->rdesc.n_voltages)
+ return -EINVAL;
+
+ regmap_update_bits(rdev->regmap, regulator->vset_reg,
+ regulator->vset_mask, i);
+
+ *selector = i;
+
+ return 0;
+}
+
+static struct regulator_ops hi655x_regulator_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = hi655x_disable,
+ .is_enabled = hi655x_is_enabled,
+ .list_voltage = regulator_list_voltage_table,
+ .get_voltage = hi655x_get_voltage,
+ .set_voltage = hi655x_set_voltage,
+};
+
+static const struct of_device_id of_hi655x_regulator_match_tbl[] = {
+ {
+ .co
[PATCH v3 0/5] Add Support for Hi6220 PMIC Hi6553 MFD Core
The patch sets add support for Hi6220 PMIC Hi655x MFD core and its regulator driver. Current testing and support board is Hikey which is one of 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. This is hardware layout for access PMIC Hi655x from AP SoC Hi6220. Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. We can use memory-mapped I/O to communicate. ++ +-+ || | | |Hi6220 | SSI bus | Hi655x| ||-| | ||(REGMAP_MMIO)| | ++ +-+ V2: Code refactoring of regulator V3: Drop mtcmos from this patch and use regmap-irq The patch sets are based on 4.4-rc5. Chen Feng (5): doc: bindings: Add document for mfd hi665x PMIC doc: bindings: Document for hi655x regulator driver mfd: hi655x: Add hi665x pmic driver regulator: add regulator driver of hi655x PMIC hisilicon/dts: Add hi655x pmic dts node .../devicetree/bindings/mfd/hisilicon,hi655x.txt | 17 ++ .../regulator/hisilicon,hi655x-regulator.txt | 43 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 178 +++ drivers/mfd/Kconfig| 9 + drivers/mfd/Makefile | 1 + drivers/mfd/hi655x-pmic.c | 170 ++ drivers/regulator/Kconfig | 8 + drivers/regulator/Makefile | 1 + drivers/regulator/hi655x-regulator.c | 246 + include/linux/mfd/hi655x-pmic.h| 56 + include/linux/regulator/hi655x-regulator.h | 41 11 files changed, 770 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt create mode 100644 Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt create mode 100644 drivers/mfd/hi655x-pmic.c create mode 100644 drivers/regulator/hi655x-regulator.c create mode 100644 include/linux/mfd/hi655x-pmic.h create mode 100644 include/linux/regulator/hi655x-regulator.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 5/5] hisilicon/dts: Add hi655x pmic dts node
Add dts node for hi665x MFD and regulator driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Tested-by: Xinwei Kong
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 178 ++
1 file changed, 178 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..5f98a72 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -208,5 +208,183 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+ pmic: pmic@F800 {
+ compatible = "hisilicon,hi655x-pmic";
+ reg = <0x0 0xf800 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmic-gpios = <&gpio_pmu_irq_n>;
+ status = "okay";
+ ldo2: regulator@a21 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <320>;
+ regulator-valid-modes-mask = <0x02>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-ctrl-regs = <0x029 0x02a 0x02b>;
+ regulator-ctrl-mask = <0x1>;
+ regulator-vset-regs = <0x072>;
+ regulator-vset-mask = <0x7>;
+ regulator-n-vol = <8>;
+ regulator-vset-table = <250>,<260>,
+ <270>,<280>,
+ <290>,<300>,
+ <310>,<320>;
+ };
+ ldo7: regulator@a26 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-ctrl-regs = <0x029 0x02a 0x02b>;
+ regulator-ctrl-mask = <0x6>;
+ regulator-vset-regs = <0x078>;
+ regulator-vset-mask = <0x7>;
+ regulator-n-vol = <8>;
+ regulator-vset-table = <180>,<185>,
+ <285>,<290>,
+ <300>,<310>,
+ <320>,<330>;
+ };
+ ldo10: regulator@a29 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo10";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <300>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-enable-ramp-delay = <360>;
+ regulator-ctrl-regs = <0x02c 0x02d 0x02e>;
+ regulator-ctrl-mask = <0x1>;
+ regulator-vset-regs = <0x07b>;
+ regulator-vset-mask = <0x7>;
+ regulator-n-vol = <8>;
+ regulator-vset-table = <180>,<185>,
+ <190>,<275>,
+ <280>,<285>,
+ <290>,<300>;
+ };
+ ldo13: regulator@a32 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo13";
+ regulator-min-microvolt
[PATCH v3 1/5] doc: bindings: Add document for mfd hi665x PMIC
Add document for mfd driver hi655x pmic driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Tested-by: Xinwei Kong
---
.../devicetree/bindings/mfd/hisilicon,hi655x.txt| 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
new file mode 100644
index 000..d1a2fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
@@ -0,0 +1,17 @@
+Hisilicon hi655x Power Management Integrated Circuit (PMIC)
+
+Required properties:
+- compatible: Should be "hisilicon,hi655x-pmic"
+- reg: Base address of PMIC on hi6220 soc
+- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
+- pmic-gpios: The gpio used by pmic irq.
+
+Example:
+pmic: pmic@f800 {
+compatible = "hisilicon,hi655x-pmic";
+reg = <0x0 0xf800 0x0 0x1000>;
+#interrupt-cells = <2>;
+interrupt-controller;
+pmic-gpios = <&gpio_pmu_irq_n>;
+status = "okay";
+}
--
1.9.1
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[PATCH v3 3/5] mfd: hi655x: Add hi665x pmic driver
Add mfd driver to support hisilicon hi665x PMIC.
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Tested-by: Xinwei Kong
---
drivers/mfd/Kconfig | 9 +++
drivers/mfd/Makefile| 1 +
drivers/mfd/hi655x-pmic.c | 170
include/linux/mfd/hi655x-pmic.h | 56 +
4 files changed, 236 insertions(+)
create mode 100644 drivers/mfd/hi655x-pmic.c
create mode 100644 include/linux/mfd/hi655x-pmic.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6..cb70b53 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -284,6 +284,15 @@ config MFD_HI6421_PMIC
menus in order to enable them.
We communicate with the Hi6421 via memory-mapped I/O.
+config MFD_HI655X_PMIC
+ tristate "HiSilicon Hi655X series PMU/Codec IC"
+ depends on OF
+ select MFD_CORE
+ select REGMAP_MMIO
+ select REGMAP_IRQ
+ help
+ Select this option to enable Hisilicon hi655x series pmic driver.
+
config HTC_EGPIO
bool "HTC EGPIO support"
depends on GPIOLIB && ARM
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b8..6a7b0e1 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -186,6 +186,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o
obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
obj-$(CONFIG_MFD_MENF21BMC)+= menf21bmc.o
obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
+obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o
obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c
new file mode 100644
index 000..2ee455e
--- /dev/null
+++ b/drivers/mfd/hi655x-pmic.c
@@ -0,0 +1,170 @@
+/*
+ * Device driver for PMIC DRIVER in HI655X IC
+ *
+ * Copyright (c) 2015 Hisilicon Co. Ltd
+ *
+ * Chen Feng
+ * Fei Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+static const struct of_device_id of_hi655x_pmic_child_match_tbl[] = {
+ { .compatible = "hisilicon,hi655x-regulator-pmic", },
+ {},
+};
+
+static const struct of_device_id of_hi655x_pmic_match_tbl[] = {
+ { .compatible = "hisilicon,hi655x-pmic", },
+ {},
+};
+
+static const struct regmap_irq hi655x_irqs[] = {
+ { .reg_offset = 0, .mask = OTMP_D1R_INT },
+ { .reg_offset = 0, .mask = VSYS_2P5_R_INT },
+ { .reg_offset = 0, .mask = VSYS_UV_D3R_INT },
+ { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT },
+ { .reg_offset = 0, .mask = PWRON_D4SR_INT },
+ { .reg_offset = 0, .mask = PWRON_D20F_INT },
+ { .reg_offset = 0, .mask = PWRON_D20R_INT },
+ { .reg_offset = 0, .mask = RESERVE_INT },
+};
+
+static const struct regmap_irq_chip hi655x_irq_chip = {
+ .name = "hi655x-pmic",
+ .irqs = hi655x_irqs,
+ .num_regs = 1,
+ .num_irqs = ARRAY_SIZE(hi655x_irqs),
+ .status_base = HI655X_IRQ_STAT_BASE,
+ .mask_base = HI655X_IRQ_MASK_BASE,
+};
+
+static unsigned int hi655x_pmic_get_version(struct hi655x_pmic *pmic)
+{
+ u32 val;
+
+ regmap_read(pmic->regmap,
+ HI655X_BUS_ADDR(HI655X_VER_REG), &val);
+
+ return val;
+}
+
+static struct regmap_config hi655x_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = HI655X_STRIDE,
+ .val_bits = 8,
+ .max_register = HI655X_BUS_ADDR(0xFFF),
+};
+
+static void hi655x_local_irq_clear(struct regmap *map)
+{
+ unsigned int i;
+
+ regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR);
+ for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
+ regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE,
+HI655X_IRQ_CLR);
+ }
+}
+
+static int hi655x_pmic_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct hi655x_pmic *pmic;
+ struct device_node *gpio_np;
+
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *base;
+
+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+ pmic->dev = dev;
+
+ pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!pmic->res) {
+ dev_err(dev, "platform_get_resource err\n");
+ return -ENOENT;
+ }
+ base = devm_ioremap_resource(&pdev->dev, pmic->res);
+ if (!base) {
+ dev_err(dev, "cannot map register memory\n");
+ return -ENOMEM;
+ }
+ pmic->regmap = devm_regmap_init_mmio_
[PATCH v3 2/5] doc: bindings: Document for hi655x regulator driver
Add Document for hi655x pmic regulator driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Tested-by: Xinwei Kong
---
.../regulator/hisilicon,hi655x-regulator.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
diff --git
a/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
new file mode 100644
index 000..2eaebae
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
@@ -0,0 +1,43 @@
+Hisilicon Hi655x Voltage regulators
+
+Note:
+The hi655x regulator control is managed by hi655x Power IC.
+So the node of this regulator must be child node of hi655x
+pmic node.
+
+The driver uses the regulator core framework, so please also
+take the bindings of regulator.txt for reference.
+
+Required properties:
+- compatible: Must be "hisilicon,hi655x-regulator-pmic";
+- regulator-ctrl-regs: Registers offset of control register,
+ In turn with enable disable and status register offset.
+- regulator-ctrl-mask: The control mask bit of the register.
+- regulator-vset-regs: Voltage set register offset.
+- regulator-vset-mask: voltage set control mask.
+- regulator-n-vol: The num of support voltages.
+- regulator-vset-table: The table of support voltages.
+
+Example:
+pmic: pmic@f800 {
+compatible = "hisilicon,hi655x-pmic";
+ ...
+ ldo7: regulator@a26 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-ctrl-regs = <0x029 0x02a 0x02b>;
+ regulator-ctrl-mask = <0x6>;
+ regulator-vset-regs = <0x078>;
+ regulator-vset-mask = <0x7>;
+ regulator-n-vol = <8>;
+ regulator-vset-table = <180>,<185>,
+ <285>,<290>,
+ <300>,<310>,
+ <320>,<330>;
+ };
+ ...
+ }
--
1.9.1
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[PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..09bb9d1 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f7030304 {
+ compatible = "hisilicon,hisi_reset_ctl";
+ reg = <0x0 0xf7030304 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
--
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[PATCH 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +-
2 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..8a23f50
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hisi_reset_ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+ reset_ctrl: reset_ctrl@f7030304 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf7030304 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: uart1@. {
+ ...
+resets = <&reset_ctrl 0x305>;
+ ...
+};
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+ PERIPH_RSTDIS0_MMC0 = 0x000,
+ PERIPH_RSTDIS0_MMC1 = 0x001,
+ PERIPH_RSTDIS0_MMC2 = 0x002,
+ PERIPH_RSTDIS0_NANDC= 0x003,
+ PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
+ PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
+ PERIPH_RSTDIS0_USBOTG = 0x006,
+ PERIPH_RSTDIS0_USBOTG_32K = 0x007,
+
+ PERIPH_RSTDIS1_HIFI = 0x100,
+ PERIPH_RSTDIS1_DIGACODEC= 0x105,
+
+ PERIPH_RSTEN2_IPF = 0x200,
+ PERIPH_RSTEN2_SOCP = 0x201,
+ PERIPH_RSTEN2_DMAC = 0x202,
+ PERIPH_RSTEN2_SECENG= 0x203,
+ PERIPH_RSTEN2_ABB = 0x204,
+ PERIPH_RSTEN2_HPM0 = 0x205,
+ PERIPH_RSTEN2_HPM1 = 0x206,
+ PERIPH_RSTEN2_HPM2 = 0x207,
+ PERIPH_RSTEN2_HPM3 = 0x208,
+
+ PERIPH_RSTEN3_CSSYS = 0x300,
+ PERIPH_RSTEN3_I2C0 = 0x301,
+ PERIPH_RSTEN3_I2C1 = 0x302,
+ PERIPH_RSTEN3_I2C2 = 0x303,
+ PERIPH_RSTEN3_I2C3 = 0x304,
+ PERIPH_RSTEN3_UART1 = 0x305,
+ PERIPH_RSTEN3_UART2 = 0x306,
+ PERIPH_RSTEN3_UART3 = 0x307,
+ PERIPH_RSTEN3_UART4 = 0x308,
+ PERIPH_RSTEN3_SSP = 0x309,
+ PERIPH_RSTEN3_PWM = 0x30a,
+ PERIPH_RSTEN3_BLPWM = 0x30b,
+ PERIPH_RSTEN3_TSENSOR = 0x30c,
+ PERIPH_RSTEN3_DAPB = 0x312,
+ PERIPH_RSTEN3_HKADC = 0x313,
+ PERIPH_RSTEN3_CODEC_SSI = 0x314,
+ PERIPH_RSTEN3_PMUSSI1 = 0x316,
+
+ PERIPH_RSTEN8_RS0 = 0x400,
+ PERIPH_RSTEN8_RS2 = 0x401,
+ PERIPH_RSTEN8_RS3 = 0x402,
+ PERIPH_RSTEN8_MS0 = 0x403,
+ PERIPH_RSTEN8_MS2 = 0x405,
+ PERIPH_RSTEN8_XG2RAM0 = 0x406,
+ PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
+ PERIPH_RSTEN8_SRAM = 0x408,
+ PERIPH_RSTEN8_HARQ = 0x40a,
+ PERIPH_RSTEN8_DDRC = 0x40c,
+ PERIPH_RSTEN8_DDRC_APB = 0x40d,
+ PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
+ PERIPH_RSTEN8_DDRT = 0x411,
+
+ PERIPH_RSDIST9_CARM_DAP = 0x500,
+ PERIPH_RSDIST9_CARM_ATB = 0x501,
+ PERIPH_RSDIST9_CARM_LBUS= 0x502,
+ PERIPH_RSDIST9_CARM_POR = 0x503,
+ PERIPH_RSDIST9_CARM_CORE= 0x504,
+ PERIPH_RSDIST9_CARM_DBG = 0x505,
+ PERIPH_RSDIST9_CARM_L2 = 0x506,
+ PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
+ PERIPH_RSDIST9_CARM_ETM = 0x508,
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 09bb9d1..111537a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -169,7 +169,7 @@
};
reset_ctrl: reset_ctrl@f7030304 {
- compatible = "hisilicon,hisi_reset_ctl";
+ compatible = "hisilicon,hi6220_reset_ctl&q
[PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.
Signed-off-by: Chen Feng
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig| 5 +++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 74 ++
5 files changed, 82 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..bceed14
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Clock Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..a88fc57
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,74 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static void __iomem *src_base;
+static DEFINE_SPINLOCK(reset_lock);
+
+static int hi6220_reset_module(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ unsigned long timeout;
+ unsigned long flags;
+ int bit;
+ u32 val;
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&reset_lock, flags);
+
+ val = readl(src_base + (bank * 0x10));
+ writel(val | BIT(offset), src_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&reset_lock, flags);
+
+ return 0;
+
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .deassert = hi6220_reset_module,
+};
+
+static struct reset_controller_dev hi6220_reset_dev = {
+ .ops = &hi6220_reset_ops,
+ .nr_resets = 0x,
+};
+
+static void __init hi6220_reset_init(void)
+{
+ struct device_node *np;
+ struct reset_control *test = NULL;
+
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl");
+ if (!np) {
+ pr_err("find reset node in dts error!\n");
+ return;
+ }
+ src_base = of_iomap(np, 0);
+ WARN_ON(!src_base);
+
+ hi6220_reset_dev.of_node = np;
+ if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+ reset_controller_register(&hi6220_reset_dev);
+}
+
+postcore_initcall(hi6220_reset_init);
+
--
1.9.1
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[RESEND PATCH 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..09bb9d1 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f7030304 {
+ compatible = "hisilicon,hisi_reset_ctl";
+ reg = <0x0 0xf7030304 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
--
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[RESEND PATCH 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +-
2 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..8a23f50
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hisi_reset_ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+ reset_ctrl: reset_ctrl@f7030304 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf7030304 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: uart1@. {
+ ...
+resets = <&reset_ctrl 0x305>;
+ ...
+};
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+ PERIPH_RSTDIS0_MMC0 = 0x000,
+ PERIPH_RSTDIS0_MMC1 = 0x001,
+ PERIPH_RSTDIS0_MMC2 = 0x002,
+ PERIPH_RSTDIS0_NANDC= 0x003,
+ PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
+ PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
+ PERIPH_RSTDIS0_USBOTG = 0x006,
+ PERIPH_RSTDIS0_USBOTG_32K = 0x007,
+
+ PERIPH_RSTDIS1_HIFI = 0x100,
+ PERIPH_RSTDIS1_DIGACODEC= 0x105,
+
+ PERIPH_RSTEN2_IPF = 0x200,
+ PERIPH_RSTEN2_SOCP = 0x201,
+ PERIPH_RSTEN2_DMAC = 0x202,
+ PERIPH_RSTEN2_SECENG= 0x203,
+ PERIPH_RSTEN2_ABB = 0x204,
+ PERIPH_RSTEN2_HPM0 = 0x205,
+ PERIPH_RSTEN2_HPM1 = 0x206,
+ PERIPH_RSTEN2_HPM2 = 0x207,
+ PERIPH_RSTEN2_HPM3 = 0x208,
+
+ PERIPH_RSTEN3_CSSYS = 0x300,
+ PERIPH_RSTEN3_I2C0 = 0x301,
+ PERIPH_RSTEN3_I2C1 = 0x302,
+ PERIPH_RSTEN3_I2C2 = 0x303,
+ PERIPH_RSTEN3_I2C3 = 0x304,
+ PERIPH_RSTEN3_UART1 = 0x305,
+ PERIPH_RSTEN3_UART2 = 0x306,
+ PERIPH_RSTEN3_UART3 = 0x307,
+ PERIPH_RSTEN3_UART4 = 0x308,
+ PERIPH_RSTEN3_SSP = 0x309,
+ PERIPH_RSTEN3_PWM = 0x30a,
+ PERIPH_RSTEN3_BLPWM = 0x30b,
+ PERIPH_RSTEN3_TSENSOR = 0x30c,
+ PERIPH_RSTEN3_DAPB = 0x312,
+ PERIPH_RSTEN3_HKADC = 0x313,
+ PERIPH_RSTEN3_CODEC_SSI = 0x314,
+ PERIPH_RSTEN3_PMUSSI1 = 0x316,
+
+ PERIPH_RSTEN8_RS0 = 0x400,
+ PERIPH_RSTEN8_RS2 = 0x401,
+ PERIPH_RSTEN8_RS3 = 0x402,
+ PERIPH_RSTEN8_MS0 = 0x403,
+ PERIPH_RSTEN8_MS2 = 0x405,
+ PERIPH_RSTEN8_XG2RAM0 = 0x406,
+ PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
+ PERIPH_RSTEN8_SRAM = 0x408,
+ PERIPH_RSTEN8_HARQ = 0x40a,
+ PERIPH_RSTEN8_DDRC = 0x40c,
+ PERIPH_RSTEN8_DDRC_APB = 0x40d,
+ PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
+ PERIPH_RSTEN8_DDRT = 0x411,
+
+ PERIPH_RSDIST9_CARM_DAP = 0x500,
+ PERIPH_RSDIST9_CARM_ATB = 0x501,
+ PERIPH_RSDIST9_CARM_LBUS= 0x502,
+ PERIPH_RSDIST9_CARM_POR = 0x503,
+ PERIPH_RSDIST9_CARM_CORE= 0x504,
+ PERIPH_RSDIST9_CARM_DBG = 0x505,
+ PERIPH_RSDIST9_CARM_L2 = 0x506,
+ PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
+ PERIPH_RSDIST9_CARM_ETM = 0x508,
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 09bb9d1..111537a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -169,7 +169,7 @@
};
reset_ctrl: reset_ctrl@f7030304 {
- compatible = "hisilicon,hisi_reset_ctl";
+ compatible = "hisilicon,hi6220_reset_ctl&q
[RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.
Signed-off-by: Chen Feng
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig| 5 +++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 74 ++
5 files changed, 82 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..bceed14
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Clock Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..a88fc57
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,74 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static void __iomem *src_base;
+static DEFINE_SPINLOCK(reset_lock);
+
+static int hi6220_reset_module(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ unsigned long timeout;
+ unsigned long flags;
+ int bit;
+ u32 val;
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&reset_lock, flags);
+
+ val = readl(src_base + (bank * 0x10));
+ writel(val | BIT(offset), src_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&reset_lock, flags);
+
+ return 0;
+
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .deassert = hi6220_reset_module,
+};
+
+static struct reset_controller_dev hi6220_reset_dev = {
+ .ops = &hi6220_reset_ops,
+ .nr_resets = 0x,
+};
+
+static void __init hi6220_reset_init(void)
+{
+ struct device_node *np;
+ struct reset_control *test = NULL;
+
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl");
+ if (!np) {
+ pr_err("find reset node in dts error!\n");
+ return;
+ }
+ src_base = of_iomap(np, 0);
+ WARN_ON(!src_base);
+
+ hi6220_reset_dev.of_node = np;
+ if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+ reset_controller_register(&hi6220_reset_dev);
+}
+
+postcore_initcall(hi6220_reset_init);
+
--
1.9.1
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[PATCH V2 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3bbc846 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f703 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf703 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
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[PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.
Signed-off-by: Chen Feng
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig| 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 118 +
5 files changed, 126 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..097133d
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,118 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ASSET_OFFSET0x300
+#define DEASSET_OFFSET 0x304
+
+struct hi6220_reset_data {
+ spinlock_t reset_lock; /*device spin-lock*/
+ void __iomem*src_base;
+ void __iomem*asset_base;
+ void __iomem*deasset_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = container_of(rc_dev,
+ struct hi6220_reset_data,
+ rc_dev);
+
+ unsigned long flags;
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&data->reset_lock, flags);
+
+ writel(BIT(offset), data->asset_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&data->reset_lock, flags);
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+unsigned long idx)
+{
+ struct hi6220_reset_data *data = container_of(rc_dev,
+ struct hi6220_reset_data,
+ rc_dev);
+
+ unsigned long flags;
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&data->reset_lock, flags);
+
+ writel(BIT(offset), data->deasset_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&data->reset_lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int __init hi6220_reset_init(void)
+{
+ int ret;
+ struct device_node *np;
+ struct hi6220_reset_data *data;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
+ if (!np) {
+ ret = -ENXIO;
+ goto err_alloc;
+ }
+ spin_lock_init(&data->reset_lock);
+ data->src_base = of_iomap(np, 0);
+ if (!data->src_base) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
+
+ data->asset_base = data->src_base + ASSET_OFFSET;
+ data->deas
[PATCH V2 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++
1 file changed, 97 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..200dc8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220_reset_ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+ reset_ctrl: reset_ctrl@f703 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf703 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: uart1@. {
+ ...
+resets = <&reset_ctrl 0x305>;
+ ...
+};
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+ PERIPH_RSTDIS0_MMC0 = 0x000,
+ PERIPH_RSTDIS0_MMC1 = 0x001,
+ PERIPH_RSTDIS0_MMC2 = 0x002,
+ PERIPH_RSTDIS0_NANDC= 0x003,
+ PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
+ PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
+ PERIPH_RSTDIS0_USBOTG = 0x006,
+ PERIPH_RSTDIS0_USBOTG_32K = 0x007,
+
+ PERIPH_RSTDIS1_HIFI = 0x100,
+ PERIPH_RSTDIS1_DIGACODEC= 0x105,
+
+ PERIPH_RSTEN2_IPF = 0x200,
+ PERIPH_RSTEN2_SOCP = 0x201,
+ PERIPH_RSTEN2_DMAC = 0x202,
+ PERIPH_RSTEN2_SECENG= 0x203,
+ PERIPH_RSTEN2_ABB = 0x204,
+ PERIPH_RSTEN2_HPM0 = 0x205,
+ PERIPH_RSTEN2_HPM1 = 0x206,
+ PERIPH_RSTEN2_HPM2 = 0x207,
+ PERIPH_RSTEN2_HPM3 = 0x208,
+
+ PERIPH_RSTEN3_CSSYS = 0x300,
+ PERIPH_RSTEN3_I2C0 = 0x301,
+ PERIPH_RSTEN3_I2C1 = 0x302,
+ PERIPH_RSTEN3_I2C2 = 0x303,
+ PERIPH_RSTEN3_I2C3 = 0x304,
+ PERIPH_RSTEN3_UART1 = 0x305,
+ PERIPH_RSTEN3_UART2 = 0x306,
+ PERIPH_RSTEN3_UART3 = 0x307,
+ PERIPH_RSTEN3_UART4 = 0x308,
+ PERIPH_RSTEN3_SSP = 0x309,
+ PERIPH_RSTEN3_PWM = 0x30a,
+ PERIPH_RSTEN3_BLPWM = 0x30b,
+ PERIPH_RSTEN3_TSENSOR = 0x30c,
+ PERIPH_RSTEN3_DAPB = 0x312,
+ PERIPH_RSTEN3_HKADC = 0x313,
+ PERIPH_RSTEN3_CODEC_SSI = 0x314,
+ PERIPH_RSTEN3_PMUSSI1 = 0x316,
+
+ PERIPH_RSTEN8_RS0 = 0x400,
+ PERIPH_RSTEN8_RS2 = 0x401,
+ PERIPH_RSTEN8_RS3 = 0x402,
+ PERIPH_RSTEN8_MS0 = 0x403,
+ PERIPH_RSTEN8_MS2 = 0x405,
+ PERIPH_RSTEN8_XG2RAM0 = 0x406,
+ PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
+ PERIPH_RSTEN8_SRAM = 0x408,
+ PERIPH_RSTEN8_HARQ = 0x40a,
+ PERIPH_RSTEN8_DDRC = 0x40c,
+ PERIPH_RSTEN8_DDRC_APB = 0x40d,
+ PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
+ PERIPH_RSTEN8_DDRT = 0x411,
+
+ PERIPH_RSDIST9_CARM_DAP = 0x500,
+ PERIPH_RSDIST9_CARM_ATB = 0x501,
+ PERIPH_RSDIST9_CARM_LBUS= 0x502,
+ PERIPH_RSDIST9_CARM_POR = 0x503,
+ PERIPH_RSDIST9_CARM_CORE= 0x504,
+ PERIPH_RSDIST9_CARM_DBG = 0x505,
+ PERIPH_RSDIST9_CARM_L2 = 0x506,
+ PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
+ PERIPH_RSDIST9_CARM_ETM = 0x508,
--
1.9.1
--
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[PATCH V4 1/3] bindings for hisilicon hi6220 iommu driver
docs: iommu: Documentation for iommu in hi6220 SoC.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
.../bindings/iommu/hisi,hi6220-iommu.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
new file mode 100644
index 000..756e64f
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt
@@ -0,0 +1,56 @@
+Hi6220 SoC SMMU Device Driver devicetree document
+===
+The Architecture of SMMU on Hi6220 SoC:
+
+ +--+
+ | |
+ | +-+ ++ +-+ +---+ |
+ | | ADE | | ISP | | V/J codec | | G3D | |
+ | +|+ +---|+ +--|--+ +---|---| |
+ | | | | | |
+ | -v---v--v--v-|
+ | Media Bus |
+ | |---||
+ | | ||
+ | +---v---v+ |
+ | |SMMU| |
+ | +--|-|---+ |
+ || | |
+ +|-|---+
+| |
+ +v-v---+
+ | DDRC|
+ +--+
+
+Note:
+The media system shared the same smmu IP to access DDR memory. And all
+media IP used the same page table.
+
+Below binding describes the system mmu for media system in hi6220 platform
+
+Required properties:
+- compatible: should contain "hisilicon,hi6220-smmu".
+- reg: A tuple of base address and size of System MMU registers.
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+ in clock-names.
+- clock-names: should contain:
+ * "smmu"
+ * "media-sc"
+ * "smmu-peri"
+- interrupts: An interrupt specifier for interrupt signal of System MMU.
+- #iommu-cells: The iommu-cells should be 0. Because no additional information
+ needs to be encoded in the specifier.
+
+Examples:
+ iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
--
1.9.1
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[PATCH V4 2/3] Add iommu driver for hi6220 SoC platform
iommu/hisilicon: Add hi6220-SoC smmu driver
The smmu on hi6220 SoC is for media system.And the
media IP use the same page-table. It supports only
one-to-one mapping from iova to phys address.
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
drivers/iommu/Kconfig| 11 +
drivers/iommu/Makefile | 1 +
drivers/iommu/hi6220_iommu.c | 492 +++
3 files changed, 504 insertions(+)
create mode 100644 drivers/iommu/hi6220_iommu.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index cbe6a89..6ca24db 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -342,6 +342,17 @@ config SPAPR_TCE_IOMMU
Enables bits of IOMMU API required by VFIO. The iommu_ops
is not implemented as it is not necessary for VFIO.
+config HI6220_IOMMU
+ bool "Hi6220 IOMMU Support"
+ depends on ARM64
+ select IOMMU_API
+ select IOMMU_IOVA
+ help
+ Enable IOMMU Driver for hi6220 SoC. The IOMMU API and IOMMU IOVA
+ is also selected.
+
+ If unsure, say N.
+
# ARM IOMMU support
config ARM_SMMU
bool "ARM Ltd. System MMU (SMMU) Support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index c6dcc51..db68fb3 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o
obj-$(CONFIG_ARM_SMMU) += arm-smmu.o
obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
obj-$(CONFIG_DMAR_TABLE) += dmar.o
+obj-$(CONFIG_HI6220_IOMMU) += hi6220_iommu.o
obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
diff --git a/drivers/iommu/hi6220_iommu.c b/drivers/iommu/hi6220_iommu.c
new file mode 100644
index 000..47eb390
--- /dev/null
+++ b/drivers/iommu/hi6220_iommu.c
@@ -0,0 +1,492 @@
+/*
+ * Hisilicon Hi6220 IOMMU driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "IOMMU: " fmt
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SMMU_CTRL_OFFSET (0x)
+#define SMMU_ENABLE_OFFSET (0x0004)
+#define SMMU_PTBR_OFFSET (0x0008)
+#define SMMU_START_OFFSET(0x000C)
+#define SMMU_END_OFFSET (0x0010)
+#define SMMU_INTMASK_OFFSET (0x0014)
+#define SMMU_RINTSTS_OFFSET (0x0018)
+#define SMMU_MINTSTS_OFFSET (0x001C)
+#define SMMU_INTCLR_OFFSET (0x0020)
+#define SMMU_STATUS_OFFSET (0x0024)
+#define SMMU_AXIID_OFFSET(0x0028)
+#define SMMU_CNTCTRL_OFFSET (0x002C)
+#define SMMU_TRANSCNT_OFFSET (0x0030)
+#define SMMU_L0TLBHITCNT_OFFSET (0x0034)
+#define SMMU_L1TLBHITCNT_OFFSET (0x0038)
+#define SMMU_WRAPCNT_OFFSET (0x003C)
+#define SMMU_SEC_START_OFFSET(0x0040)
+#define SMMU_SEC_END_OFFSET (0x0044)
+#define SMMU_VERSION_OFFSET (0x0048)
+#define SMMU_IPTSRC_OFFSET (0x004C)
+#define SMMU_IPTPA_OFFSET(0x0050)
+#define SMMU_TRBA_OFFSET (0x0054)
+#define SMMU_BYS_START_OFFSET(0x0058)
+#define SMMU_BYS_END_OFFSET (0x005C)
+#define SMMU_RAM_OFFSET (0x1000)
+
+#define SMMU_CTRL_INVALID(BIT(10))
+#define SMMU_SR_REGS_NUM (15)
+#define SMMU_REGS_SGMT_END (0x60)
+#define PAGE_ENTRY_VALID (0x1)
+#define IOPAGE_SHIFT (12)
+#define IOVA_PFN(addr) ((addr) >> IOPAGE_SHIFT)
+#define IOVA_PAGE_SZ (SZ_4K)
+
+/**
+ * The iova address from 0 ~ 2G
+ */
+#define IOVA_START (0x0)
+#define IOVA_END (0x8000)
+
+struct hi6220_smmu {
+ unsigned int irq;
+ void __iomem *reg_base;
+ struct clk *smmu_peri_clk;
+ struct clk *smmu_clk;
+ struct clk *media_sc_clk;
+ spinlock_t spinlock; /*spinlock for tlb invalid*/
+ dma_addr_t pgtable_phy;
+ void *pgtable_virt;
+ u32 pgtable_size;
+ u32 *sr_data;
+};
+
+struct hi6220_domain {
+ struct hi6220_smmu *smmu_dev;
+ struct iommu_domain io_domain;
+};
+
+static struct hi6220_smmu *smmu_dev_handle;
+static struct iova_domain iova_allocator;
+
+static struct hi6220_domain *to_hi6220_domain(struct iommu_domain *dom)
+{
+ return container_of(dom, struct hi6220_domain, io_domain);
+}
+
+static inline void __smmu_writel(struct hi6220_smmu *smmu_dev, u32 value,
+unsigned long offset)
+{
+ writel(value, smmu_dev->reg_base + offset);
+}
+
+static inl
[PATCH V4 3/3] Add iommu node for hi6220 SoC platform
arm64: dts: Add dts node for hi6220 smmu driver
Signed-off-by: Chen Feng
Signed-off-by: Yu Dongbin
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..b4d535a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -5,6 +5,7 @@
*/
#include
+#include
/ {
compatible = "hisilicon,hi6220";
@@ -167,5 +168,18 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ iommu: iommu@f421 {
+ compatible = "hisilicon,hi6220-smmu";
+ reg = <0x0 0xf421 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&sys_ctrl HI6220_MMU_CLK>,
+<&media_ctrl HI6220_MED_MMU>,
+<&sys_ctrl HI6220_MEDIA_PLL_SRC>;
+ clock-names = "smmu",
+ "media-sc",
+ "smmu-peri";
+ #iommu-cells = <0>;
+ };
};
};
--
1.9.1
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[PATCH V6 1/3] Add DT bindings documentation for hi6220 SoC reset controller.
docs: dts: Added documentation for hi6220 Reset Controller
Signed-off-by: Chen Feng
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..be06352
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,32 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi6220 SoC.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-sysctrl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+sys_ctrl: sys_ctrl@f703 {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: uart1@. {
+...
+resets = <&sys_ctrl 0x305>;
+...
+};
--
1.9.1
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[PATCH V6 2/3] Add reset controller for hi6220 SoC platform.
reset: add driver for hi6220 reset controller
Signed-off-by: Chen Feng
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig| 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 108 +
include/dt-bindings/reset/hisi,hi6220-resets.h | 67 +++
6 files changed, 183 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
create mode 100644 include/dt-bindings/reset/hisi,hi6220-resets.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 85d5904..99e18c8 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
obj-$(CONFIG_ATH79) += reset-ath79.o
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..d17c910
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,108 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ASSERT_OFFSET0x300
+#define DEASSERT_OFFSET 0x304
+#define MAX_INDEX0x509
+
+#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
+
+struct hi6220_reset_data {
+ void __iomem*assert_base;
+ void __iomem*deassert_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->assert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->deassert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int hi6220_reset_probe(struct platform_device *pdev)
+{
+ struct hi6220_reset_data *data;
+ struct resource *res;
+ void __iomem *src_base;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ src_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(src_base))
+ return PTR_ERR(src_base);
+
+ data->assert_base = src_base + ASSERT_OFFSET;
+ data->deassert_base = src_base + DEASSERT_OFFSET;
+ data->rc_dev.nr_resets = MAX_INDEX;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = pdev->dev.of_node;
+
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+}
+
+static const struct of_device_id hi6220_reset_match[] = {
+ { .compatible = "hisilicon,hi6220-sysctrl" },
+ {
[PATCH V6 3/3] Add reset-cell node for hi6220 reset controller
arm64: dts: Add dts node for reset controller
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..e45dbb1 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -146,6 +146,7 @@
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf703 0x0 0x2000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
media_ctrl: media_ctrl@f441 {
--
1.9.1
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[PATCH v4 0/5] Add Support for Hi6220 PMIC Hi6553 MFD Core
The patch sets add support for Hi6220 PMIC Hi655x MFD core and its regulator driver. Current testing and support board is Hikey which is one of 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. This is hardware layout for access PMIC Hi655x from AP SoC Hi6220. Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. We can use memory-mapped I/O to communicate. ++ +-+ || | | |Hi6220 | SSI bus | Hi655x| ||-| | ||(REGMAP_MMIO)| | ++ +-+ V2: Code refactoring of regulator. V3: Drop mtcmos from this patch and use regmap-irq. V4: Move the vset-table to driver code and donot open code for it. Chen Feng (5): doc: bindings: Add document for mfd hi665x PMIC doc: bindings: Document for hi655x regulator driver mfd: hi655x: Add hi665x pmic driver regulator: add regulator driver of hi655x pmic hisilicon/dts: Add hi655x pmic dts node .../devicetree/bindings/mfd/hisilicon,hi655x.txt | 17 ++ .../regulator/hisilicon,hi655x-regulator.txt | 24 +++ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 5 + arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 99 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/hi655x-pmic.c | 160 ++ drivers/regulator/Kconfig | 8 + drivers/regulator/Makefile | 1 + drivers/regulator/hi655x-regulator.c | 232 + include/linux/mfd/hi655x-pmic.h| 56 + 11 files changed, 613 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt create mode 100644 Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt create mode 100644 drivers/mfd/hi655x-pmic.c create mode 100644 drivers/regulator/hi655x-regulator.c create mode 100644 include/linux/mfd/hi655x-pmic.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/5] doc: bindings: Add document for mfd hi665x PMIC
Add document for mfd driver hi655x pmic driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Signed-off-by: Xinwei Kong
---
.../devicetree/bindings/mfd/hisilicon,hi655x.txt| 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
new file mode 100644
index 000..9479619
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
@@ -0,0 +1,17 @@
+Hisilicon hi655x Power Management Integrated Circuit (PMIC)
+
+Required properties:
+- compatible: Should be "hisilicon,hi655x-pmic"
+- reg: Base address of PMIC on hi6220 soc
+- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
+- pmic-gpios: The gpio used by pmic irq.
+
+Example:
+ pmic: pmic@f800 {
+ compatible = "hisilicon,hi655x-pmic-driver";
+ reg = <0x0 0xf800 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmic-gpios = <&gpio1 2 0>;
+ status = "disabled";
+ }
--
1.9.1
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[PATCH v4 2/5] doc: bindings: Document for hi655x regulator driver
Add Document for hi655x pmic regulator driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Signed-off-by: Xinwei Kong
---
.../regulator/hisilicon,hi655x-regulator.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
diff --git
a/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
new file mode 100644
index 000..1cf71a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
@@ -0,0 +1,24 @@
+Hisilicon Hi655x Voltage regulators
+
+Note:
+The hi655x regulator control is managed by hi655x Power IC.
+So the node of this regulator must be child node of hi655x
+pmic node.
+
+The driver uses the regulator core framework, so please also
+take the bindings of regulator.txt for reference.
+
+Example:
+pmic: pmic@f800 {
+compatible = "hisilicon,hi655x-pmic";
+ ...
+ ldo2: ldo2@a21 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <320>;
+ regulator-valid-modes-mask = <0x02>;
+ regulator-enable-ramp-delay = <120>;
+ };
+ ...
+ }
--
1.9.1
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[PATCH v4 5/5] hisilicon/dts: Add hi655x pmic dts node
Add the mfd hi655x dts node and regulator support
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Signed-off-by: Xinwei Kong
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 5 ++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 99 ++
2 files changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 8d43a0f..f714ac7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -31,4 +31,9 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x4000>;
};
+
+};
+
+&pmic {
+ status = "okay";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..48966a5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -208,5 +208,104 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ pmic: pmic@f800 {
+ compatible = "hisilicon,hi655x-pmic";
+ reg = <0x0 0xf800 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmic-gpios = <&gpio1 2 0>;
+ status = "disabled";
+
+ ldo2: ldo2@a21 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <320>;
+ regulator-valid-modes-mask = <0x02>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo7: ldo7@a26 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo10: ldo10@a29 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo10";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <300>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-enable-ramp-delay = <360>;
+ };
+
+ ldo13: ldo13@a32 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo13";
+ regulator-min-microvolt = <160>;
+ regulator-max-microvolt = <195>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo14: ldo14@a33 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo14";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <320>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo15: ldo15@a34 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo15";
+ regulator-min-microvolt = <160>;
+ regulator-max-microvolt = <195>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo17: ldo17@a36 {
+ compatible = "hisilicon,hi655x-regulator";
+ regulator-name = "ldo17";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <320>;
+ regulator-enable-ramp-delay = <120>;
+
[PATCH v4 3/5] mfd: hi655x: Add hi665x pmic driver
Add pmic mfd driver to support hisilicon hi665x.
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Signed-off-by: Xinwei Kong
---
drivers/mfd/Kconfig | 10 +++
drivers/mfd/Makefile| 1 +
drivers/mfd/hi655x-pmic.c | 160
include/linux/mfd/hi655x-pmic.h | 56 ++
4 files changed, 227 insertions(+)
create mode 100644 drivers/mfd/hi655x-pmic.c
create mode 100644 include/linux/mfd/hi655x-pmic.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6..0c84186 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -284,6 +284,16 @@ config MFD_HI6421_PMIC
menus in order to enable them.
We communicate with the Hi6421 via memory-mapped I/O.
+config MFD_HI655X_PMIC
+ tristate "HiSilicon Hi655X series PMU/Codec IC"
+ depends on ARCH_HISI || COMPILE_TEST
+ depends on OF
+ select MFD_CORE
+ select REGMAP_MMIO
+ select REGMAP_IRQ
+ help
+ Select this option to enable Hisilicon hi655x series pmic driver.
+
config HTC_EGPIO
bool "HTC EGPIO support"
depends on GPIOLIB && ARM
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b8..6a7b0e1 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -186,6 +186,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o
obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
obj-$(CONFIG_MFD_MENF21BMC)+= menf21bmc.o
obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
+obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o
obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c
new file mode 100644
index 000..fa50aba
--- /dev/null
+++ b/drivers/mfd/hi655x-pmic.c
@@ -0,0 +1,160 @@
+/*
+ * Device driver for regulators in hi655x IC
+ *
+ * Copyright (c) 2016 Hisilicon.
+ *
+ * Chen Feng
+ * Fei Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const struct of_device_id of_hi655x_pmic_child_match_tbl[] = {
+ { .compatible = "hisilicon,hi655x-regulator", },
+ {},
+};
+
+static const struct of_device_id of_hi655x_pmic_match_tbl[] = {
+ { .compatible = "hisilicon,hi655x-pmic", },
+ {},
+};
+
+static const struct regmap_irq hi655x_irqs[] = {
+ { .reg_offset = 0, .mask = OTMP_D1R_INT },
+ { .reg_offset = 0, .mask = VSYS_2P5_R_INT },
+ { .reg_offset = 0, .mask = VSYS_UV_D3R_INT },
+ { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT },
+ { .reg_offset = 0, .mask = PWRON_D4SR_INT },
+ { .reg_offset = 0, .mask = PWRON_D20F_INT },
+ { .reg_offset = 0, .mask = PWRON_D20R_INT },
+ { .reg_offset = 0, .mask = RESERVE_INT },
+};
+
+static const struct regmap_irq_chip hi655x_irq_chip = {
+ .name = "hi655x-pmic",
+ .irqs = hi655x_irqs,
+ .num_regs = 1,
+ .num_irqs = ARRAY_SIZE(hi655x_irqs),
+ .status_base = HI655X_IRQ_STAT_BASE,
+ .mask_base = HI655X_IRQ_MASK_BASE,
+};
+
+static unsigned int hi655x_pmic_get_version(struct hi655x_pmic *pmic)
+{
+ u32 val;
+
+ regmap_read(pmic->regmap,
+ HI655X_BUS_ADDR(HI655X_VER_REG), &val);
+
+ return val;
+}
+
+static struct regmap_config hi655x_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = HI655X_STRIDE,
+ .val_bits = 8,
+ .max_register = HI655X_BUS_ADDR(0xFFF),
+};
+
+static void hi655x_local_irq_clear(struct regmap *map)
+{
+ int i;
+
+ regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR);
+ for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
+ regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE,
+HI655X_IRQ_CLR);
+ }
+}
+
+static int hi655x_pmic_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct hi655x_pmic *pmic;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *base;
+
+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+ pmic->dev = dev;
+
+ pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!pmic->res) {
+ dev_err(dev, "platform_get_resource err\n");
+ return -ENOENT;
+ }
+ base = devm_ioremap_resource(dev, pmic->res);
+ if (!base) {
+ dev_err(dev, "cannot map register memory\n");
+ return -ENOMEM;
+ }
+ pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
+
[PATCH v4 4/5] regulator: add regulator driver of hi655x pmic
Add regulator support for hi655x pmic
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
Signed-off-by: Xinwei Kong
---
drivers/regulator/Kconfig| 8 ++
drivers/regulator/Makefile | 1 +
drivers/regulator/hi655x-regulator.c | 232 +++
3 files changed, 241 insertions(+)
create mode 100644 drivers/regulator/hi655x-regulator.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 8df0b0e..2e9eaa7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -261,6 +261,14 @@ config REGULATOR_HI6421
21 general purpose LDOs, 3 dedicated LDOs, and 5 BUCKs. All
of them come with support to either ECO (idle) or sleep mode.
+config REGULATOR_HI655X
+ tristate "Hisilicon HI655X PMIC regulators support"
+ depends on ARCH_HISI || COMPILE_TEST
+ depends on MFD_HI655X_PMIC && OF
+ help
+ This driver provides support for the voltage regulators of the
+ Hisilicon Hi655x PMIC device.
+
config REGULATOR_ISL9305
tristate "Intersil ISL9305 regulator"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 0f81749..8e4db96 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o
obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
+obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o
obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
diff --git a/drivers/regulator/hi655x-regulator.c
b/drivers/regulator/hi655x-regulator.c
new file mode 100644
index 000..47161e6
--- /dev/null
+++ b/drivers/regulator/hi655x-regulator.c
@@ -0,0 +1,232 @@
+/*
+ * Device driver for regulators in hi655x IC
+ *
+ * Copyright (c) 2016 Hisilicon.
+ *
+ * Chen Feng
+ * Fei Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct hi655x_regulator {
+ unsigned int disable_reg;
+ unsigned int status_reg;
+ unsigned int ctrl_mask;
+ struct regulator_desc rdesc;
+};
+
+/*LDO 2 & LDO 14*/
+static const unsigned int ldo2_voltages[] = {
+ 250, 260, 270, 280,
+ 290, 300, 310, 320,
+};
+
+/*LDO7 & LDO10*/
+static const unsigned int ldo7_voltages[] = {
+ 180, 185, 285, 290,
+ 300, 310, 320, 330,
+};
+
+/*LDO13 & LDO15*/
+static const unsigned int ldo13_voltages[] = {
+ 160, 165, 170, 175,
+ 180, 185, 190, 195,
+};
+
+static const unsigned int ldo17_voltages[] = {
+ 250, 260, 270, 280,
+ 290, 300, 310, 320,
+};
+
+static const unsigned int ldo19_voltages[] = {
+ 180, 185, 190, 175,
+ 280, 285, 290, 300,
+};
+
+static const unsigned int ldo21_voltages[] = {
+ 165, 170, 175, 180,
+ 185, 190, 195, 200,
+};
+
+static const unsigned int ldo22_voltages[] = {
+90, 100, 105, 110,
+ 115, 1175000, 1185000, 120,
+};
+
+enum hi655x_regulator_id {
+ hi655x_ldo0,
+ hi655x_ldo1,
+ hi655x_ldo2,
+ hi655x_ldo3,
+ hi655x_ldo4,
+ hi655x_ldo5,
+ hi655x_ldo6,
+ hi655x_ldo7,
+ hi655x_ldo8,
+ hi655x_ldo9,
+ hi655x_ldo10,
+ hi655x_ldo11,
+ hi655x_ldo12,
+ hi655x_ldo13,
+ hi655x_ldo14,
+ hi655x_ldo15,
+ hi655x_ldo16,
+ hi655x_ldo17,
+ hi655x_ldo18,
+ hi655x_ldo19,
+ hi655x_ldo20,
+ hi655x_ldo21,
+ hi655x_ldo22,
+};
+
+static int hi655x_is_enabled(struct regulator_dev *rdev)
+{
+ unsigned int value = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ regmap_read(rdev->regmap, regulator->status_reg, &value);
+ return (value & BIT(regulator->ctrl_mask));
+}
+
+static int hi655x_disable(struct regulator_dev *rdev)
+{
+ int ret = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ ret = regmap_write(rdev->regmap, regulator->disable_reg,
+ BIT(regulator->ctrl_mask));
+ return ret;
+}
+
+static struct regulator_ops hi655x_regulator_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = hi655x_disable,
+ .is_enabled = hi655x_is_enabled,
+ .lis
Re: [PATCH v8 1/5] mfd: hi655x: Add document for mfd hi665x PMIC
Lee,
Thanks for your review.
On 2016/2/15 16:32, Lee Jones wrote:
> On Sun, 14 Feb 2016, Chen Feng wrote:
>
>> DT bindings for hisilicon hi655x MFD PMIC chip.
>>
>> Signed-off-by: Chen Feng
>> Signed-off-by: Fei Wang
>> Signed-off-by: Xinwei Kong
>> Reviewed-by: Haojian Zhuang
>> ---
>> .../devicetree/bindings/mfd/hisilicon,hi655x.txt | 27
>> ++
>> 1 file changed, 27 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
>
> For my own reference:
> Acked-by: Lee Jones
>
Will you merge this into your git-repo?
git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
I saw mark already merged the part of regulator into his git tree.
Hi Wei,
Could you help merge the DTS part of these patch sets.
>> diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
>> b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
>> new file mode 100644
>> index 000..0548569
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
>> @@ -0,0 +1,27 @@
>> +Hisilicon Hi655x Power Management Integrated Circuit (PMIC)
>> +
>> +The hardware layout for access PMIC Hi655x from AP SoC Hi6220.
>> +Between PMIC Hi655x and Hi6220, the physical signal channel is SSI.
>> +We can use memory-mapped I/O to communicate.
>> +
>> +++ +-+
>> +|| | |
>> +|Hi6220 | SSI bus | Hi655x|
>> +||-| |
>> +||(REGMAP_MMIO)| |
>> +++ +-+
>> +
>> +Required properties:
>> +- compatible: Should be "hisilicon,hi655x-pmic".
>> +- reg: Base address of PMIC on Hi6220 SoC.
>> +- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
>> +- pmic-gpios: The GPIO used by PMIC IRQ.
>> +
>> +Example:
>> +pmic: pmic@f800 {
>> +compatible = "hisilicon,hi655x-pmic";
>> +reg = <0x0 0xf800 0x0 0x1000>;
>> +interrupt-controller;
>> +#interrupt-cells = <2>;
>> +pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
>> +}
>
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
Hi Catalin, Thanks for your reply. On 2016/4/12 22:59, Catalin Marinas wrote: > On Mon, Apr 11, 2016 at 12:31:53PM +0200, Ard Biesheuvel wrote: >> On 11 April 2016 at 11:59, Chen Feng wrote: >>> On 2016/4/11 16:00, Ard Biesheuvel wrote: >>>> On 11 April 2016 at 09:55, Chen Feng wrote: >>>>> On 2016/4/11 15:35, Ard Biesheuvel wrote: >>>>>> On 11 April 2016 at 04:49, Chen Feng wrote: >>>>>>> 0 1.5G2G 3.5G4G >>>>>>> | | | | | >>>>>>> +--+--+---+--+ >>>>>>> |MEM | hole | MEM | IO (regs) | >>>>>>> +--+--+---+--+ >>>>> The hole in 1.5G ~ 2G is also allocated mem-map array. And also with the >>>>> 3.5G ~ 4G. >>>>> >>>> >>>> No, it is not. It may be covered by a section, but that does not mean >>>> sparsemem vmemmap will actually allocate backing for it. The >>>> granularity used by sparsemem vmemmap on a 4k pages kernel is 128 MB, >>>> due to the fact that the backing is performed at PMD granularity. >>>> >>>> Please, could you share the contents of the vmemmap section in >>>> /sys/kernel/debug/kernel_page_tables of your system running with >>>> sparsemem vmemmap enabled? You will need to set CONFIG_ARM64_PTDUMP=y >>> >>> Please see the pg-tables below. >>> >>> With sparse and vmemmap enable. >>> >>> ---[ vmemmap start ]--- >>> 0xffbdc020-0xffbdc480 70M RW NX SHD AFUXN >>> MEM/NORMAL >>> ---[ vmemmap end ]--- > [...] >>> The board is 4GB, and the memap is 70MB >>> 1G memory --- 14MB mem_map array. >> >> No, this is incorrect. 1 GB corresponds with 16 MB worth of struct >> pages assuming sizeof(struct page) == 64 >> >> So you are losing 6 MB to rounding here, which I agree is significant. >> I wonder if it makes sense to use a lower value for SECTION_SIZE_BITS >> on 4k pages kernels, but perhaps we're better off asking the opinion >> of the other cc'ees. > > IIRC, SECTION_SIZE_BITS was chosen to be the maximum sane value we were > thinking of at the time, assuming that 1GB RAM alignment to be fairly > normal. For the !SPARSEMEM_VMEMMAP case, we should probably be fine with > 29 but, as Will said, we need to be careful with the page flags. At a > quick look, we have 25 page flags, 2 bits per zone, NUMA nodes and (48 - > section_size_bits) for the section width. We also need to take into > account 4 more bits for 52-bit PA support (ARMv8.2). So, without NUMA > nodes, we are currently at 49 bits used in page->flags. > > For the SPARSEMEM_VMEMMAP case, we can decrease the SECTION_SIZE_BITS in > the MAX_ORDER limit. > > An alternative would be to free the vmemmap holes later (but still keep > the vmemmap mapping alias). Yet another option would be to change the > sparse_mem_map_populate() logic get the actual section end rather than > always assuming PAGES_PER_SECTION. But I don't think any of these are > worth if we can safely reduce SECTION_SIZE_BITS. > Yes, currently,it's safely to reduce the SECTION_SIZE_BITS to match this issue very well. As I mentioned before, if the memory layout is not like this scene. There will be not suitable to reduce the SECTION_SIZE_BITS. We have 4G memory, and 64GB phys address. There will be a lot of holes in the memory layout. And the *holes size are not always the same*. So,it's the reason I want to enable flat-mem in ARM64-ARCH. Why not makes the flat-mem an optional setting for arm64？
Is the page always in swapcache?
Hi Matainers,
In the file mm/migrate.c
316 int migrate_page_move_mapping(struct address_space *mapping,
317 struct page *newpage, struct page *page,
318 struct buffer_head *head, enum migrate_mode mode,
319 int extra_count)
320 {
321 struct zone *oldzone, *newzone;
322 int dirty;
323 int expected_count = 1 + extra_count;
324 void **pslot;
344
345 pslot = radix_tree_lookup_slot(&mapping->page_tree,
346 page_index(page));
347
348 expected_count += 1 + page_has_private(page);
349 if (page_count(page) != expected_count ||
350 radix_tree_deref_slot_protected(pslot,
&mapping->tree_lock) != page) {
...
353 }
In the line 345, Is the page is always in the swap-cache?
I got the follow crash issue with compaction.
[ 4433.467956s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]Unable to handle kernel
NULL pointer dereference at virtual address
[ 4433.467987s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]pgd = ffc0b46f9000
[ 4433.467987s][] *pgd=
[ 4433.468017s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]Internal error: Oops:
9605 [#1] PREEMPT SMP
[ 4433.468048s]Modules linked in:
[ 4433.468078s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]CPU: 2 PID: 324 Comm:
lmkd Tainted: GW3.10.94-g0daa20e #1
[ 4433.468109s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]task: ffc0b7783980
ti: ffc0b46c8000 task.ti: ffc0b46c8000
[ 4433.468139s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]PC is at
migrate_page_move_mapping.part.28+0x7c/0x21c
[ 4433.468170s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]LR is at
migrate_page_move_mapping.part.28+0x50/0x21c
[ 4433.468170s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]pc :
[] lr : [] pstate: 6185
[ 4433.468200s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]sp : ffc0b46cbb20
[ 4433.468200s]x29: ffc0b46cbb20 x28: fff5
[ 4433.468231s]x27: ffc0bb20b000 x26:
[ 4433.468261s]x25: x24: 0001
[ 4433.468292s]x23: ffc0013be1a8 x22:
[ 4433.468322s]x21: 0002 x20: ffc0bdbfc900
[ 4433.468353s]x19: ffc0bb20b000 x18:
[ 4433.468353s]x17: x16:
[ 4433.468383s]x15: x14: fff8fff8
[ 4433.468414s]x13: fff8fff8 x12: fff8fff8
[ 4433.468444s]x11: fff8fff8 x10:
[ 4433.468475s]x9 : d61f0220913be210 x8 : ffc0ba60ee80
[ 4433.468475s]x7 : 0006 x6 : 0001
[ 4433.468505s]x5 : 01440006010b x4 : 0001
[ 4433.468536s]x3 : x2 : 01440006010b
[ 4433.468566s]x1 : 01440006010b x0 : 0002
[ 4433.468597s][2016:04:13 11:06:41][pid:324,cpu2,lmkd]
[ 4433.468597s]PC: 0xffc000192838:
[ 4433.468597s]2838 d65f03c0 a9bb7bfd 910003fd a90363f7 91006017 2a0403f8
a90153f3 a9025bf5
[ 4433.468658s]2858 aa0203f3 aa0003f5 aa1703e0 aa0103f4 a9046bf9 aa0303f9
942c336b f9400260
[ 4433.468719s]2878 910022b5 37880ba0 f9400a61 aa1503e0 9407a477 aa0003fa
f9400262 aa1303e0
[ 4433.468780s]2898 f9400261 f274045f 1a9f07f6 11000ad5 37800a81 b9401c00
6b0002bf 540008a1
[ 4433.468811s]28b8 f9400340 eb00027f 54000841 d5033bbf 5281 91007263
885f7c60 6b15001f
[ 4433.468872s]28d8 5461 88027c61 3582 d5033bbf 6b0002bf 540006e1
35d8 b4b9
[ 4433.468933s]28f8 aa1903e0 978f 53001c00 34000600 f9400280 378009c0
91007282 885f7c40
[ 4433.468994s]2918 11000400 88017c40 35a1 f9400260 37880420 12000295
37000734 d5033abf
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
Hi will,
Thanks for review.
On 2016/4/7 22:21, Will Deacon wrote:
> On Tue, Apr 05, 2016 at 04:22:51PM +0800, Chen Feng wrote:
>> We can reduce the memory allocated at mem-map
>> by flatmem.
>>
>> currently, the default memory-model in arm64 is
>> sparse memory. The mem-map array is not freed in
>> this scene. If the physical address is too long,
>> it will reserved too much memory for the mem-map
>> array.
>
> Can you elaborate a bit more on this, please? We use the vmemmap, so any
> spaces between memory banks only burns up virtual space. What exactly is
> the problem you're seeing that makes you want to use flatmem (which is
> probably unsuitable for the majority of arm64 machines).
>
The root cause we want to use flat-mem is the mam_map alloced in sparse-mem
is not freed.
take a look at here:
arm64/mm/init.c
void __init mem_init(void)
{
#ifndef CONFIG_SPARSEMEM_VMEMMAP
free_unused_memmap();
#endif
}
Memory layout (3GB)
0 1.5G2G 3.5G4G
| | | | |
+--+--+---+--+
|MEM | hole | MEM | IO (regs) |
+--+--+---+--+
Memory layout (4GB)
03.5G4G4.5G
| | | |
+-+--+---+
| MEM | IO (regs) | MEM |
+-+--+---+
Currently, the sparse memory section is 1GB.
3GB ddr: the 1.5 ~2G and 3.5 ~ 4G are holes.
3GB ddr: the 3.5 ~ 4G and 4.5 ~ 5G are holes.
This will alloc 1G/4K * (struct page) memory for mem_map array.
We want to use flat-mem to reduce the alloced mem_map.
I don't know why you tell us the flatmem is unsuitable for the
majority of arm64 machines. Can tell us the reason of it?
And we are not going to limit the memdel in arm64, we just want to
make the flat-mem is an optional item in arm64.
puck,
> Will
>
> .
>
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
Hi Ard,
On 2016/4/11 15:35, Ard Biesheuvel wrote:
> On 11 April 2016 at 04:49, Chen Feng wrote:
>> Hi will,
>> Thanks for review.
>>
>> On 2016/4/7 22:21, Will Deacon wrote:
>>> On Tue, Apr 05, 2016 at 04:22:51PM +0800, Chen Feng wrote:
>>>> We can reduce the memory allocated at mem-map
>>>> by flatmem.
>>>>
>>>> currently, the default memory-model in arm64 is
>>>> sparse memory. The mem-map array is not freed in
>>>> this scene. If the physical address is too long,
>>>> it will reserved too much memory for the mem-map
>>>> array.
>>>
>>> Can you elaborate a bit more on this, please? We use the vmemmap, so any
>>> spaces between memory banks only burns up virtual space. What exactly is
>>> the problem you're seeing that makes you want to use flatmem (which is
>>> probably unsuitable for the majority of arm64 machines).
>>>
>> The root cause we want to use flat-mem is the mam_map alloced in sparse-mem
>> is not freed.
>>
>> take a look at here:
>> arm64/mm/init.c
>> void __init mem_init(void)
>> {
>> #ifndef CONFIG_SPARSEMEM_VMEMMAP
>> free_unused_memmap();
>> #endif
>> }
>>
>> Memory layout (3GB)
>>
>> 0 1.5G2G 3.5G4G
>> | | | | |
>> +--+--+---+--+
>> |MEM | hole | MEM | IO (regs) |
>> +--+--+---+--+
>>
>>
>> Memory layout (4GB)
>>
>> 03.5G4G4.5G
>> | | | |
>> +-+--+---+
>> | MEM | IO (regs) | MEM |
>> +-+--+---+
>>
>> Currently, the sparse memory section is 1GB.
>>
>> 3GB ddr: the 1.5 ~2G and 3.5 ~ 4G are holes.
>> 3GB ddr: the 3.5 ~ 4G and 4.5 ~ 5G are holes.
>>
>> This will alloc 1G/4K * (struct page) memory for mem_map array.
>>
>
> No, this is incorrect. Sparsemem vmemmap only allocates struct pages
> for memory regions that are actually populated.
>
> For instance, on the Foundation model with 4 GB of memory, you may see
> something like this in the boot log
>
> [0.00] vmemmap : 0xffbdc000 - 0xffbfc000
> ( 8 GB maximum)
> [0.00] 0xffbdc000 - 0xffbde200
> ( 544 MB actual)
>
> but in reality, only the following regions have been allocated
>
> ---[ vmemmap start ]---
> 0xffbdc000-0xffbdc200 32M RW NX SHD AF
> BLK UXN MEM/NORMAL
> 0xffbde000-0xffbde200 32M RW NX SHD AF
> BLK UXN MEM/NORMAL
> ---[ vmemmap end ]---
>
> so only 64 MB is used to back 4 GB of RAM with struct pages, which is
> minimal. Moving to flatmem will not reduce the memory footprint at
> all.
Yes,but the populate is section, which is 1GB. Take a look at the above
memory layout.
The section 1G ~ 2G is a section. But 1.5G ~ 2G is a hole.
The section 3G ~ 4G is a section. But 3.5G ~ 4G is a hole.
>> 0 1.5G2G 3.5G4G
>> | | | | |
>> +--+--+---+--+
>> |MEM | hole | MEM | IO (regs) |
>> +--+--+---+--+
The hole in 1.5G ~ 2G is also allocated mem-map array. And also with the 3.5G ~
4G.
We want free the the mem-map array. With flat-mem we can work with this scene
very well.
Thanks,
>
> --
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> see: http://www.linux-mm.org/ .
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>
> .
>
Re: [PATCH v8 0/5] Add Support for Hi6220 PMIC Hi6553 MFD Core
Hi lee, Mark already took the regulator set. Please help take the mfd part. mfd: hi655x: Add document for mfd hi665x PMIC and mfd: hi655x: Add MFD driver for hi655x thanks a lot. On 2016/4/11 16:14, Lee Jones wrote: > On Sun, 14 Feb 2016, Chen Feng wrote: > >> The patch sets add support for Hi6220 PMIC Hi655x MFD core and its >> regulator driver. >> Current testing and support board is Hikey which is one of 96boards. >> It is an arm64 open source board. For more information about this board, >> please access https://www.96boards.org. >> >> This is hardware layout for access PMIC Hi655x from AP SoC Hi6220. >> Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. >> We can use memory-mapped I/O to communicate. >> >> ++ +-+ >> || | | >> |Hi6220 | SSI bus | Hi655x| >> ||-| | >> ||(REGMAP_MMIO)| | >> ++ +-+ >> >> V2: Code refactoring of regulator. >> >> V3: Drop mtcmos from this patch and use regmap-irq. >> >> V4: Move the vset-table to driver code and donot open code for it. >> >> V5: Use regulators_node and of_match, donot open code fot it. >> >> V7: Change the constraints into hikey.dts and fix code in PMIC. >> >> V8: Change format in document, and fix bit mask in regulator. >> >> Chen Feng (5): >> mfd: hi655x: Add document for mfd hi665x PMIC >> regulator: hi655x: Document for hi655x regulator >> mfd: hi655x: Add MFD driver for hi655x >> regulator: hi655x: enable regulator for hi655x PMIC >> arm64: dts: hisilicon: Add hi655x pmic dts node > > So what's going on with this set? Can the MFD patches go in via my > tree on their own? Or are there dependencies between them and the > Regulator changes? If the latter, then we need Mark's Ack to > proceed. > >> .../devicetree/bindings/mfd/hisilicon,hi655x.txt | 27 +++ >> .../regulator/hisilicon,hi655x-regulator.txt | 29 +++ >> arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 87 >> drivers/mfd/Kconfig| 10 + >> drivers/mfd/Makefile | 1 + >> drivers/mfd/hi655x-pmic.c | 162 +++ >> drivers/regulator/Kconfig | 8 + >> drivers/regulator/Makefile | 1 + >> drivers/regulator/hi655x-regulator.c | 227 >> + >> include/linux/mfd/hi655x-pmic.h| 55 + >> 10 files changed, 607 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt >> create mode 100644 >> Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt >> create mode 100644 drivers/mfd/hi655x-pmic.c >> create mode 100644 drivers/regulator/hi655x-regulator.c >> create mode 100644 include/linux/mfd/hi655x-pmic.h >> >
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
Hi Ard,
On 2016/4/11 16:00, Ard Biesheuvel wrote:
> On 11 April 2016 at 09:55, Chen Feng wrote:
>> Hi Ard,
>>
>> On 2016/4/11 15:35, Ard Biesheuvel wrote:
>>> On 11 April 2016 at 04:49, Chen Feng wrote:
>>>> Hi will,
>>>> Thanks for review.
>>>>
>>>> On 2016/4/7 22:21, Will Deacon wrote:
>>>>> On Tue, Apr 05, 2016 at 04:22:51PM +0800, Chen Feng wrote:
>>>>>> We can reduce the memory allocated at mem-map
>>>>>> by flatmem.
>>>>>>
>>>>>> currently, the default memory-model in arm64 is
>>>>>> sparse memory. The mem-map array is not freed in
>>>>>> this scene. If the physical address is too long,
>>>>>> it will reserved too much memory for the mem-map
>>>>>> array.
>>>>>
>>>>> Can you elaborate a bit more on this, please? We use the vmemmap, so any
>>>>> spaces between memory banks only burns up virtual space. What exactly is
>>>>> the problem you're seeing that makes you want to use flatmem (which is
>>>>> probably unsuitable for the majority of arm64 machines).
>>>>>
>>>> The root cause we want to use flat-mem is the mam_map alloced in sparse-mem
>>>> is not freed.
>>>>
>>>> take a look at here:
>>>> arm64/mm/init.c
>>>> void __init mem_init(void)
>>>> {
>>>> #ifndef CONFIG_SPARSEMEM_VMEMMAP
>>>> free_unused_memmap();
>>>> #endif
>>>> }
>>>>
>>>> Memory layout (3GB)
>>>>
>>>> 0 1.5G2G 3.5G4G
>>>> | | | | |
>>>> +--+--+---+--+
>>>> |MEM | hole | MEM | IO (regs) |
>>>> +--+--+---+--+
>>>>
>>>>
>>>> Memory layout (4GB)
>>>>
>>>> 03.5G4G4.5G
>>>> | | | |
>>>> +-+--+---+
>>>> | MEM | IO (regs) | MEM |
>>>> +-+--+---+
>>>>
>>>> Currently, the sparse memory section is 1GB.
>>>>
>>>> 3GB ddr: the 1.5 ~2G and 3.5 ~ 4G are holes.
>>>> 3GB ddr: the 3.5 ~ 4G and 4.5 ~ 5G are holes.
>>>>
>>>> This will alloc 1G/4K * (struct page) memory for mem_map array.
>>>>
>>>
>>> No, this is incorrect. Sparsemem vmemmap only allocates struct pages
>>> for memory regions that are actually populated.
>>>
>>> For instance, on the Foundation model with 4 GB of memory, you may see
>>> something like this in the boot log
>>>
>>> [0.00] vmemmap : 0xffbdc000 - 0xffbfc000
>>> ( 8 GB maximum)
>>> [0.00] 0xffbdc000 - 0xffbde200
>>> ( 544 MB actual)
>>>
>>> but in reality, only the following regions have been allocated
>>>
>>> ---[ vmemmap start ]---
>>> 0xffbdc000-0xffbdc200 32M RW NX SHD AF
>>> BLK UXN MEM/NORMAL
>>> 0xffbde000-0xffbde200 32M RW NX SHD AF
>>> BLK UXN MEM/NORMAL
>>> ---[ vmemmap end ]---
>>>
>>> so only 64 MB is used to back 4 GB of RAM with struct pages, which is
>>> minimal. Moving to flatmem will not reduce the memory footprint at
>>> all.
>>
>> Yes,but the populate is section, which is 1GB. Take a look at the above
>> memory layout.
>>
>> The section 1G ~ 2G is a section. But 1.5G ~ 2G is a hole.
>>
>> The section 3G ~ 4G is a section. But 3.5G ~ 4G is a hole.
>>>> 0 1.5G2G 3.5G4G
>>>> | | | | |
>>>> +--+--+---+--+
>>>> |MEM | hole | MEM | IO (regs) |
>>>> +--+--+---+--+
>> The hole in 1.5G ~ 2G is also allocated mem-map array. And also with the
>> 3.5G ~ 4G.
>>
>
> No, it is not. It may be covered by a section, but that does not mean
> sparsemem vmemmap will actually allocate backing for it. The
> granularity used by sparsemem vmemmap on a 4k pages kernel is 128 MB,
> due to the fact that the backing is performed at PMD granularity.
>
> Please, could you share the contents of the vmemmap section in
> /sys/kernel/debug/kernel_page_tables of your system running with
> sparsemem vmemmap enabled? You will need to set CONFIG_ARM64_PTDUMP=y
>
Please see the pg-tables below.
With sparse and vmemmap enable.
---[ vmemmap start ]---
0xffbdc020-0xffbdc480 70M RW NX SHD AFUXN
MEM/NORMAL
---[ vmemmap end ]---
The board is 4GB, and the memap is 70MB
1G memory --- 14MB mem_map array.
So the 4GB has 5 sections, which used 5 * 14MB memory.
> .
>
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
On 2016/4/11 17:59, Chen Feng wrote:
> Hi Ard,
>
> On 2016/4/11 16:00, Ard Biesheuvel wrote:
>> On 11 April 2016 at 09:55, Chen Feng wrote:
>>> Hi Ard,
>>>
>>> On 2016/4/11 15:35, Ard Biesheuvel wrote:
>>>> On 11 April 2016 at 04:49, Chen Feng wrote:
>>>>> Hi will,
>>>>> Thanks for review.
>>>>>
>>>>> On 2016/4/7 22:21, Will Deacon wrote:
>>>>>> On Tue, Apr 05, 2016 at 04:22:51PM +0800, Chen Feng wrote:
>>>>>>> We can reduce the memory allocated at mem-map
>>>>>>> by flatmem.
>>>>>>>
>>>>>>> currently, the default memory-model in arm64 is
>>>>>>> sparse memory. The mem-map array is not freed in
>>>>>>> this scene. If the physical address is too long,
>>>>>>> it will reserved too much memory for the mem-map
>>>>>>> array.
>>>>>>
>>>>>> Can you elaborate a bit more on this, please? We use the vmemmap, so any
>>>>>> spaces between memory banks only burns up virtual space. What exactly is
>>>>>> the problem you're seeing that makes you want to use flatmem (which is
>>>>>> probably unsuitable for the majority of arm64 machines).
>>>>>>
>>>>> The root cause we want to use flat-mem is the mam_map alloced in
>>>>> sparse-mem
>>>>> is not freed.
>>>>>
>>>>> take a look at here:
>>>>> arm64/mm/init.c
>>>>> void __init mem_init(void)
>>>>> {
>>>>> #ifndef CONFIG_SPARSEMEM_VMEMMAP
>>>>> free_unused_memmap();
>>>>> #endif
>>>>> }
>>>>>
>>>>> Memory layout (3GB)
>>>>>
>>>>> 0 1.5G2G 3.5G4G
>>>>> | | | | |
>>>>> +--+--+---+--+
>>>>> |MEM | hole | MEM | IO (regs) |
>>>>> +--+--+---+--+
>>>>>
>>>>>
>>>>> Memory layout (4GB)
>>>>>
>>>>> 03.5G4G4.5G
>>>>> | | | |
>>>>> +-+--+---+
>>>>> | MEM | IO (regs) | MEM |
>>>>> +-+--+---+
>>>>>
>>>>> Currently, the sparse memory section is 1GB.
>>>>>
>>>>> 3GB ddr: the 1.5 ~2G and 3.5 ~ 4G are holes.
>>>>> 3GB ddr: the 3.5 ~ 4G and 4.5 ~ 5G are holes.
>>>>>
>>>>> This will alloc 1G/4K * (struct page) memory for mem_map array.
>>>>>
>>>>
>>>> No, this is incorrect. Sparsemem vmemmap only allocates struct pages
>>>> for memory regions that are actually populated.
>>>>
>>>> For instance, on the Foundation model with 4 GB of memory, you may see
>>>> something like this in the boot log
>>>>
>>>> [0.00] vmemmap : 0xffbdc000 - 0xffbfc000
>>>> ( 8 GB maximum)
>>>> [0.00] 0xffbdc000 - 0xffbde200
>>>> ( 544 MB actual)
>>>>
>>>> but in reality, only the following regions have been allocated
>>>>
>>>> ---[ vmemmap start ]---
>>>> 0xffbdc000-0xffbdc200 32M RW NX SHD AF
>>>> BLK UXN MEM/NORMAL
>>>> 0xffbde000-0xffbde200 32M RW NX SHD AF
>>>> BLK UXN MEM/NORMAL
>>>> ---[ vmemmap end ]---
>>>>
>>>> so only 64 MB is used to back 4 GB of RAM with struct pages, which is
>>>> minimal. Moving to flatmem will not reduce the memory footprint at
>>>> all.
>>>
>>> Yes,but the populate is section, which is 1GB. Take a look at the above
>>> memory layout.
>>>
>>> The section 1G ~ 2G is a section. But 1.5G ~ 2G is a hole.
>>>
>>> The section 3G ~ 4G is a section. But 3.5G ~ 4G is a hole.
>>>>> 0 1.5G2G 3.5G4G
>>>>> | | |
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
Hi Will, On 2016/4/11 18:40, Will Deacon wrote: > On Mon, Apr 11, 2016 at 12:31:53PM +0200, Ard Biesheuvel wrote: >> On 11 April 2016 at 11:59, Chen Feng wrote: >>> Please see the pg-tables below. >>> >>> >>> With sparse and vmemmap enable. >>> >>> ---[ vmemmap start ]--- >>> 0xffbdc020-0xffbdc480 70M RW NX SHD AFUXN >>> MEM/NORMAL >>> ---[ vmemmap end ]--- >>> >> >> OK, I see what you mean now. Sorry for taking so long to catch up. >> >>> The board is 4GB, and the memap is 70MB >>> 1G memory --- 14MB mem_map array. >> >> No, this is incorrect. 1 GB corresponds with 16 MB worth of struct >> pages assuming sizeof(struct page) == 64 >> >> So you are losing 6 MB to rounding here, which I agree is significant. >> I wonder if it makes sense to use a lower value for SECTION_SIZE_BITS >> on 4k pages kernels, but perhaps we're better off asking the opinion >> of the other cc'ees. > > You need to be really careful making SECTION_SIZE_BITS smaller because > it has a direct correlation on the use of page->flags and you can end up > running out of bits fairly easily. Yes, making SECTION_SIZE_BITS smaller can solve the current situation. But if the phys-addr is 64GB, but only 4GB ddr is the valid address. And the holes are not always 512MB. But, can you tell us why *smaller SIZE makes running out of bits fairly easily*? And how about the flat-mem model? > > Will > > . >
[PATCH 2/2] arm64: mm: make pfn always valid with flat memory
Make the pfn always valid when using flat memory.
If the reserved memory is not align to memblock-size,
there will be holes in zone.
This patch makes the memory in buddy always in the
array of mem-map.
Signed-off-by: Chen Feng
Signed-off-by: Fu Jun
---
arch/arm64/mm/init.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index ea989d8..0e1d5b7 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -306,7 +306,8 @@ static void __init free_unused_memmap(void)
struct memblock_region *reg;
for_each_memblock(memory, reg) {
- start = __phys_to_pfn(reg->base);
+ start = round_down(__phys_to_pfn(reg->base),
+ MAX_ORDER_NR_PAGES);
#ifdef CONFIG_SPARSEMEM
/*
@@ -327,8 +328,8 @@ static void __init free_unused_memmap(void)
* memmap entries are valid from the bank end aligned to
* MAX_ORDER_NR_PAGES.
*/
- prev_end = ALIGN(__phys_to_pfn(reg->base + reg->size),
-MAX_ORDER_NR_PAGES);
+ prev_end = round_up(__phys_to_pfn(reg->base + reg->size),
+ MAX_ORDER_NR_PAGES);
}
#ifdef CONFIG_SPARSEMEM
--
1.9.1
[PATCH 1/2] arm64: mem-model: add flatmem model for arm64
We can reduce the memory allocated at mem-map by flatmem. currently, the default memory-model in arm64 is sparse memory. The mem-map array is not freed in this scene. If the physical address is too long, it will reserved too much memory for the mem-map array. Signed-off-by: Chen Feng Signed-off-by: Fu Jun --- arch/arm64/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4f43622..c18930d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -559,6 +559,9 @@ config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_VMEMMAP_ENABLE +config ARCH_FLATMEM_ENABLE + def_bool y + config ARCH_SPARSEMEM_DEFAULT def_bool ARCH_SPARSEMEM_ENABLE -- 1.9.1
Re: [PATCH 1/2] arm64: mem-model: add flatmem model for arm64
add Mel Gorman On 2016/4/5 16:22, Chen Feng wrote: > We can reduce the memory allocated at mem-map > by flatmem. > > currently, the default memory-model in arm64 is > sparse memory. The mem-map array is not freed in > this scene. If the physical address is too long, > it will reserved too much memory for the mem-map > array. > > Signed-off-by: Chen Feng > Signed-off-by: Fu Jun > --- > arch/arm64/Kconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 4f43622..c18930d 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -559,6 +559,9 @@ config ARCH_SPARSEMEM_ENABLE > def_bool y > select SPARSEMEM_VMEMMAP_ENABLE > > +config ARCH_FLATMEM_ENABLE > + def_bool y > + > config ARCH_SPARSEMEM_DEFAULT > def_bool ARCH_SPARSEMEM_ENABLE > >
Re: [PATCH 2/2] arm64: mm: make pfn always valid with flat memory
add Mel Gorman
On 2016/4/5 16:22, Chen Feng wrote:
> Make the pfn always valid when using flat memory.
> If the reserved memory is not align to memblock-size,
> there will be holes in zone.
>
> This patch makes the memory in buddy always in the
> array of mem-map.
>
> Signed-off-by: Chen Feng
> Signed-off-by: Fu Jun
> ---
> arch/arm64/mm/init.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
> index ea989d8..0e1d5b7 100644
> --- a/arch/arm64/mm/init.c
> +++ b/arch/arm64/mm/init.c
> @@ -306,7 +306,8 @@ static void __init free_unused_memmap(void)
> struct memblock_region *reg;
>
> for_each_memblock(memory, reg) {
> - start = __phys_to_pfn(reg->base);
> + start = round_down(__phys_to_pfn(reg->base),
> +MAX_ORDER_NR_PAGES);
>
> #ifdef CONFIG_SPARSEMEM
> /*
> @@ -327,8 +328,8 @@ static void __init free_unused_memmap(void)
>* memmap entries are valid from the bank end aligned to
>* MAX_ORDER_NR_PAGES.
>*/
> - prev_end = ALIGN(__phys_to_pfn(reg->base + reg->size),
> - MAX_ORDER_NR_PAGES);
> + prev_end = round_up(__phys_to_pfn(reg->base + reg->size),
> + MAX_ORDER_NR_PAGES);
> }
>
> #ifdef CONFIG_SPARSEMEM
>
[PATCH 7/7] arm64: dts: Add mtcmos and pmic node for hi6220 HiKey board
Add dts node for hi665x pmic and hi6220 mtcmos driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 210 ++
1 file changed, 210 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..5e0b8260 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,215 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ mtcmos {
+ compatible = "hisilicon,hi6220-mtcmos-driver";
+ hisilicon,mtcmos-steady-us = <10>;
+ hisilicon,mtcmos-sc-on-base = <0xf780>;
+ hisilicon,mtcmos-acpu-on-base = <0xf65a>;
+
+ g3d_vdd: regulator@a1{
+ regulator-name = "G3D_PD_VDD";
+ regulator-compatible = "mtcmos1";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <1 0x1>;
+ };
+
+ soc_med: regulator@a2{
+ regulator-name = "SOC_MED";
+ regulator-compatible = "mtcmos2";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <2 0x1>;
+ };
+ };
+ };
+
+ pmic: pmic@f800 {
+ compatible = "hisilicon,hi655x-pmic-driver";
+ reg = <0x0 0xf800 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmic-gpios = <&gpio_pmu_irq_n>;
+ status = "okay";
+ ldo2: regulator@a21 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <320>;
+ regulator-valid-modes-mask = <0x02>;
+ regulator-initial-mode = <0x02>;
+ regulator-off-on-delay = <120>;
+ regulator-ctrl-regs = <0x029 0x02a 0x02b>;
+ regulator-ctrl-mask = <0x1>;
+ regulator-vset-regs = <0x072>;
+ regulator-vset-mask = <0x3>;
+ regulator-n-vol = <8>;
+ regulator-vset-table = <250>,<260>,
+ <270>,<280>,
+ <290>,<300>,
+ <310>,<320>;
+ };
+ ldo7: regulator@a26 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-initial-mode = <0x02>;
+ regulator-off-on-delay = <120>;
+ regulator-ctrl-regs = <0x029 0x02a 0x02b>;
+ regulator-ctrl-mask = <0x6>;
+ regulator-vset-regs = <0x078>;
+ regulator-vset-mask = <0x3>;
+ regulator-n-vol = <8>;
+ regulator-vset-table = <180>,<185>,
+ <285>,<290>,
+ <300>,<310>,
+ <320>,<330>;
+ };
+ ldo10: regulator@a29 {
+ compatible = "hisilicon,hi655x-regulator-pmic";
+ regulator-name = "ldo10";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <300>;
+ regulator-valid-modes-mask = <0x0a>;
+ regulator-initial-mode = <0x02>;
+ regulator-off-on-delay = <360>;
+ regulator-ctrl-regs = <0x02c 0x02d 0x02e&
[PATCH 4/7] mfd: hi655x: Add hi665x pmic driver
Add pmic driver to support hisilicon hi665x pmic.
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
drivers/mfd/Kconfig | 9 ++
drivers/mfd/Makefile| 1 +
drivers/mfd/hi655x-pmic.c | 315
include/linux/mfd/hi655x-pmic.h | 50 +++
4 files changed, 375 insertions(+)
create mode 100644 drivers/mfd/hi655x-pmic.c
create mode 100644 include/linux/mfd/hi655x-pmic.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 99d6367..c805071 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -273,6 +273,15 @@ config MFD_HI6421_PMIC
menus in order to enable them.
We communicate with the Hi6421 via memory-mapped I/O.
+config MFD_HI655X_PMIC
+bool "HiSilicon Hi655X series PMU/Codec IC"
+depends on ARCH_HISI
+depends on OF
+select MFD_CORE
+select REGMAP_MMIO
+help
+ Select this option to enable Hisilicon hi655x series pmic driver.
+
config HTC_EGPIO
bool "HTC EGPIO support"
depends on GPIOLIB && ARM
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a59e3fc..11ec427 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -185,6 +185,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o
obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
obj-$(CONFIG_MFD_MENF21BMC)+= menf21bmc.o
obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
+obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o
obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c
new file mode 100644
index 000..942f96e
--- /dev/null
+++ b/drivers/mfd/hi655x-pmic.c
@@ -0,0 +1,315 @@
+/*
+ * Device driver for PMIC DRIVER in HI655X IC
+ *
+ * Copyright (c) 2015 Hisilicon Co. Ltd
+ *
+ * Fei Wang
+ * Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const struct of_device_id of_hi655x_pmic_child_match_tbl[] = {
+ { .compatible = "hisilicon,hi655x-regulator-pmic", },
+ {},
+};
+
+static const struct of_device_id of_hi655x_pmic_match_tbl[] = {
+ { .compatible = "hisilicon,hi655x-pmic-driver", },
+ {},
+};
+
+static unsigned int hi655x_pmic_get_version(struct hi655x_pmic *pmic)
+{
+ u32 val;
+
+ regmap_read(pmic->regmap,
+ HI655X_REG_TO_BUS_ADDR(HI655X_VER_REG), &val);
+
+ return val;
+}
+
+static irqreturn_t hi655x_pmic_irq_handler(int irq, void *data)
+{
+ struct hi655x_pmic *pmic = (struct hi655x_pmic *)data;
+ u32 pending;
+ u32 ret = IRQ_NONE;
+ unsigned long offset;
+ int i;
+
+ for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
+ regmap_read(pmic->regmap,
+ HI655X_REG_TO_BUS_ADDR(i + HI655X_IRQ_STAT_BASE),
+ &pending);
+ if (pending)
+ pr_debug("pending[%d]=0x%x\n\r", i, pending);
+
+ /* clear pmic-sub-interrupt */
+ regmap_write(pmic->regmap,
+HI655X_REG_TO_BUS_ADDR(i + HI655X_IRQ_STAT_BASE),
+pending);
+
+ if (pending) {
+ for_each_set_bit(offset, (unsigned long *)&pending,
+HI655X_BITS)
+ generic_handle_irq(pmic->irqs[offset +
+ i * HI655X_BITS]);
+ ret = IRQ_HANDLED;
+ }
+ }
+ return ret;
+}
+
+static void hi655x_pmic_irq_mask(struct irq_data *d)
+{
+ u32 data, offset;
+ unsigned long pmic_spin_flag = 0;
+ struct hi655x_pmic *pmic = irq_data_get_irq_chip_data(d);
+
+ offset = ((irqd_to_hwirq(d) >> 3) + HI655X_IRQ_MASK_BASE);
+ spin_lock_irqsave(&pmic->ssi_hw_lock, pmic_spin_flag);
+ regmap_read(pmic->regmap, HI655X_REG_TO_BUS_ADDR(offset), &data);
+ data |= (1 << (irqd_to_hwirq(d) & 0x07));
+ regmap_write(pmic->regmap, HI655X_REG_TO_BUS_ADDR(offset), data);
+ spin_unlock_irqrestore(&pmic->ssi_hw_lock, pmi
[PATCH 1/7] doc:bindings:Add document for mfd hi665x PMIC
Add document for mfd driver hi655x pmic driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
.../devicetree/bindings/mfd/hisilicon,hi655x.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
new file mode 100644
index 000..afa2fa5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
@@ -0,0 +1,18 @@
+Hisilicon hi655x Power Management Integrated Circuit (PMIC)
+
+Required properties:
+- compatible: Should be "hisilicon,hi655x-pmic-driver"
+- reg: Base address of PMIC on hi6220 soc
+- #interrupt-cells: Should be 2, two cells are needed for irq.
+- interrupt-controller: hi655x has internal IRQs (has own IRQ domain).
+- pmu_irq_gpio: should be &gpio_pmu_irq_n, is the IRQ gpio of hi655x.
+
+Example:
+ pmic: pmic@f800 {
+ compatible = "hisilicon,hi655x-pmic-driver";
+ reg = <0x0 0xf800 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmic_gpios = <&gpio_pmu_irq_n>;
+ status = "okay";
+ }
--
1.9.1
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[PATCH 0/7] Add Support for Hi6220 PMIC Hi6553 MFD Core
The patch sets add support for Hi6220 PMIC Hi655x MFD core and its regulator driver. Current testing and support board is Hikey which is one of 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. This is hardware layout for access PMIC Hi655x from AP SoC Hi6220. Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. We can use memory-mapped I/O to communicate. ++ +-+ || | | |Hi6220 | SSI bus | Hi655x| ||-| | ||(REGMAP_MMIO)| | ++ +-+ The patch sets are based on 4.3-rc7. Chen Feng (7): doc:bindings:Add document for mfd hi665x PMIC doc:bindings:Document for mtcmos regulator on hi6220 SoC doc:bindings:Document for hi655x pmic driver mfd: hi655x: Add hi665x pmic driver regulator: add driver for mtcmos voltage regulator on hi6220 SoC regulator: hisilicon: Add hi655x pmic voltage regulator driver arm64: dts: Add mtcmos and pmic node for hi6220 HiKey board .../devicetree/bindings/mfd/hisilicon,hi655x.txt | 18 ++ .../bindings/regulator/hisilicon,hi6220-mtcmos.txt | 32 +++ .../regulator/hisilicon,hi655x-regulator.txt | 50 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 210 ++ drivers/mfd/Kconfig| 9 + drivers/mfd/Makefile | 1 + drivers/mfd/hi655x-pmic.c | 315 + drivers/regulator/Kconfig | 13 + drivers/regulator/Makefile | 2 + drivers/regulator/hi6220-mtcmos.c | 245 drivers/regulator/hi655x-regulator.c | 246 include/linux/mfd/hi655x-pmic.h| 50 include/linux/regulator/hi655x-regulator.h | 63 + 13 files changed, 1254 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt create mode 100644 Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt create mode 100644 Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt create mode 100644 drivers/mfd/hi655x-pmic.c create mode 100644 drivers/regulator/hi6220-mtcmos.c create mode 100644 drivers/regulator/hi655x-regulator.c create mode 100644 include/linux/mfd/hi655x-pmic.h create mode 100644 include/linux/regulator/hi655x-regulator.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/7] doc:bindings:Document for hi655x pmic driver
Add Document for hi655x pmic driver
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
.../regulator/hisilicon,hi655x-regulator.txt | 50 ++
1 file changed, 50 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
diff --git
a/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
new file mode 100644
index 000..66c6a73
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt
@@ -0,0 +1,50 @@
+Hisilicon Hi655x Voltage regulators
+
+Note:
+The hi655x regulator control is managed by hi655x Power IC.
+So the node of this regulator must be child node of hi655x
+pmic node.
+
+The driver uses the regulator core framework, so please also
+take the bindings of regulator.txt for reference.
+
+Required properties:
+- compatible: Must be "hisilicon,hi655x-regulator-pmic";
+- regulator-name: Regulator name in SoC.
+- regulator-min-microvolt: Smallest voltage support.
+- regulator-max-microvolt: Largest voltages support.
+- regulator-initial-mode: Init mode of this regulator.
+- regulator-valid-modes-mask: Valid support mode mask.
+- regulator-off-on-delay: The time wait for power steady
+- regulator-ctrl-regs: Registers offset of control register.
+ In turn with enable disable and status register offset.
+- regulator-ctrl-mask: The control mask of the register.
+- regulator-vset-regs: Voltage set register offset.
+- regulator-vset-mask: voltage set control mask.
+- regulator-n-vol: The num of support voltages.
+- regulator-vset-table: The table of support voltages.
+
+Example:
+pmic: pmic@f800 {
+compatible = "hisilicon,hi655x-pmic-driver";
+ ...
+ldo2: regulator@a21 {
+compatible = "hisilicon,hi655x-regulator-pmic";
+regulator-name = "ldo2";
+regulator-min-microvolt = <250>;
+regulator-max-microvolt = <320>;
+regulator-valid-modes-mask = <0x02>;
+regulator-initial-mode = <0x02>;
+regulator-off-on-delay = <120>;
+regulator-ctrl-regs = <0x029 0x02a 0x02b>;
+regulator-ctrl-mask = <0x1>;
+regulator-vset-regs = <0x072>;
+regulator-vset-mask = <0x3>;
+regulator-n-vol = <8>;
+regulator-vset-table = <250>,<260>,
+<270>,<280>,
+<290>,<300>,
+<310>,<320>;
+};
+ ...
+ }
--
1.9.1
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[PATCH 5/7] regulator: add driver for mtcmos voltage regulator on hi6220 SoC
Add driver to support mtcmos on hi6220
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
drivers/regulator/hi6220-mtcmos.c | 245 ++
1 file changed, 245 insertions(+)
create mode 100644 drivers/regulator/hi6220-mtcmos.c
diff --git a/drivers/regulator/hi6220-mtcmos.c
b/drivers/regulator/hi6220-mtcmos.c
new file mode 100644
index 000..c79ffc0
--- /dev/null
+++ b/drivers/regulator/hi6220-mtcmos.c
@@ -0,0 +1,245 @@
+/*
+ * Device driver for regulators in hi6220 mtcmos
+ *
+ * Copyright (c) 2015 Hisilicon.
+ *
+ * Fei Wang
+ * Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum {
+ HI6220_MTCMOS1,
+ HI6220_MTCMOS2,
+ HI6220_RG_MAX,
+};
+
+struct hi6220_mtcmos_ctrl_regs {
+ unsigned int enable_reg;
+ unsigned int disable_reg;
+ unsigned int status_reg;
+};
+
+struct hi6220_mtcmos_ctrl_data {
+ int shift;
+ unsigned int mask;
+};
+
+struct hi6220_mtcmos_info {
+ struct regulator_desc rdesc;
+ struct hi6220_mtcmos_ctrl_regs ctrl_regs;
+ struct hi6220_mtcmos_ctrl_data ctrl_data;
+};
+
+struct hi6220_mtcmos {
+ struct regulator_dev *rdev[HI6220_RG_MAX];
+ void __iomem *sc_on_regs;
+};
+
+static int hi6220_mtcmos_is_on(struct hi6220_mtcmos *mtcmos,
+ unsigned int regs, unsigned int mask, int shift)
+{
+ unsigned int ret;
+
+ ret = readl(mtcmos->sc_on_regs + regs);
+ ret &= (mask << shift);
+
+ return ret;
+}
+
+static int hi6220_mtcmos_is_enabled(struct regulator_dev *rdev)
+{
+ int ret;
+ struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev);
+ struct platform_device *pdev =
+ container_of(rdev->dev.parent, struct platform_device, dev);
+ struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev);
+ struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs;
+ struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data;
+
+ ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg,
+ ctrl_data->mask, ctrl_data->shift);
+ return ret;
+}
+
+static int hi6220_mtcmos_op(struct hi6220_mtcmos *mtcmos,
+ unsigned int regs, unsigned int mask, int shift)
+{
+ writel(mask << shift, mtcmos->sc_on_regs + regs);
+
+ return 0;
+}
+
+static int hi6220_mtcmos_enable(struct regulator_dev *rdev)
+{
+ int ret;
+ struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev);
+ struct platform_device *pdev =
+ container_of(rdev->dev.parent, struct platform_device, dev);
+ struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev);
+ struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs;
+ struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data;
+
+ hi6220_mtcmos_op(mtcmos, ctrl_regs->enable_reg,
+ctrl_data->mask, ctrl_data->shift);
+ ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg,
+ ctrl_data->mask, ctrl_data->shift)
+ return ret;
+}
+
+static int hi6220_mtcmos_disable(struct regulator_dev *rdev)
+{
+ int ret;
+ struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev);
+ struct platform_device *pdev =
+ container_of(rdev->dev.parent, struct platform_device, dev);
+ struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev);
+ struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs;
+ struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data;
+
+ ret = hi6220_mtcmos_op(mtcmos, ctrl_regs->disable_reg,
+ ctrl_data->mask, ctrl_data->shift);
+
+ return ret;
+}
+
+static struct regulator_ops hi6220_mtcmos_mtcmos_rops = {
+ .is_enabled = hi6220_mtcmos_is_enabled,
+ .enable = hi6220_mtcmos_enable,
+ .disable = hi6220_mtcmos_disable,
+};
+
+#define HI6220_MTCMOS(vreg) \
+{ \
+ .rdesc = { \
+ .name = #vreg, \
+ .ops= &hi6220_mtcmos_mtcmos_rops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }, \
+}
+
+static struct hi6220_mtcmos_info hi6220_mtcmos_info[] = {
+ HI6220_MTCMOS(MTCMOS1),
+ HI6220_MTCMOS(MTCMOS2),
+};
+
+static struct of_regulator_match hi6220_mt
[PATCH 6/7] regulator: hisilicon: Add hi655x pmic voltage regulator driver
Add driver support for HiSilicon Hi655x voltage regulators.
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
drivers/regulator/Kconfig | 13 ++
drivers/regulator/Makefile | 2 +
drivers/regulator/hi655x-regulator.c | 246 +
include/linux/regulator/hi655x-regulator.h | 63
4 files changed, 324 insertions(+)
create mode 100644 drivers/regulator/hi655x-regulator.c
create mode 100644 include/linux/regulator/hi655x-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 64bccff..9bbd43c 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -261,6 +261,19 @@ config REGULATOR_HI6421
21 general purpose LDOs, 3 dedicated LDOs, and 5 BUCKs. All
of them come with support to either ECO (idle) or sleep mode.
+config REGULATOR_HI6220_MTCMOS
+bool "Hisilicon Hi6220 mtcmos support"
+depends on ARCH_HISI
+help
+ This driver provides support for the mtcmos regulators of Hi6220 Soc.
+
+config REGULATOR_HI655X
+bool "HiSilicon Hi655x PMIC voltage regulator support"
+depends on ARCH_HISI
+help
+ This driver provides support for the voltage regulators on the
+ HiSilicon hi655x PMIC.
+
config REGULATOR_ISL9305
tristate "Intersil ISL9305 regulator"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 0f81749..7345d43 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -34,6 +34,8 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o
obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
+obj-$(CONFIG_REGULATOR_HI6220_MTCMOS) += hi6220-mtcmos.o
+obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o
obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
diff --git a/drivers/regulator/hi655x-regulator.c
b/drivers/regulator/hi655x-regulator.c
new file mode 100644
index 000..b06c810
--- /dev/null
+++ b/drivers/regulator/hi655x-regulator.c
@@ -0,0 +1,246 @@
+/*
+ * Device driver for regulators in hi655x IC
+ *
+ * Copyright (c) 2015 Hisilicon.
+ *
+ * Fei Wang
+ * Chen Feng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int hi655x_is_enabled(struct regulator_dev *rdev)
+{
+ unsigned int value = 0;
+
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = ®ulator->ctrl_regs;
+
+ regmap_read(rdev->regmap, ctrl_regs->status_reg, &value);
+ return (value & BIT(regulator->ctrl_mask));
+}
+
+static int hi655x_enable(struct regulator_dev *rdev)
+{
+ int ret = 0;
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = ®ulator->ctrl_regs;
+
+ ret = regmap_update_bits(rdev->regmap, ctrl_regs->enable_reg,
+regulator->ctrl_mask, regulator->ctrl_mask);
+ return ret;
+}
+
+static int hi655x_disable(struct regulator_dev *rdev)
+{
+ int ret = 0;
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ if (!regulator) {
+ pr_err("get driver data error!\n");
+ return -ENODEV;
+ }
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = ®ulator->ctrl_regs;
+
+ ret = regmap_update_bits(rdev->regmap, ctrl_regs->disable_reg,
+regulator->ctrl_mask, regulator->ctrl_mask);
+ return ret;
+}
+
+static int hi655x_get_voltage(struct regulator_dev *rdev)
+{
+ unsigned int value = 0;
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ if (!regulator) {
+ pr_err("get driver data error!\n");
+ return -ENODEV;
+ }
+ struct hi655x_regulator_vset_regs *vset_regs = ®ulator->vset_regs;
+
+ regmap_read(rdev->regmap, vset_regs->vset_reg, &value);
+
+ return regulator->vset_table[value];
+}
+
+static int hi655x_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ int i = 0;
+ int ret = 0;
+ int vol = 0;
+ struct hi655x_regulator *regulator = rdev_get_drvdata(rdev);
+
+ if (!regulator) {
+ pr_er
[PATCH 2/7] doc:bindings:Document for mtcmos regulator on hi6220 SoC
Add Document for mtcmos driver on hi6220 SoC
Signed-off-by: Chen Feng
Signed-off-by: Fei Wang
---
.../bindings/regulator/hisilicon,hi6220-mtcmos.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt
diff --git
a/Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt
b/Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt
new file mode 100644
index 000..bb06e1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt
@@ -0,0 +1,32 @@
+Hi6220 mtcmos Voltage regulators
+
+Required parent device properties:
+- compatible: Must be "hisilicon,hi6220-mtcmos-driver"
+- hisilicon,mtcmos-steady-us: The time to wait for power steady
+- hisilicon,mtcmos-sc-on-base: address of mtcmos on hi6220 SoC
+
+Required child device properties:
+- regulator-name: The name of mtcmos
+- hisilicon,ctrl-regs: Offset of ctrl-regs
+- hisilicon,ctrl-data: The bit to ctrl the regulator
+
+Example:
+mtcmos {
+compatible = "hisilicon,hi6220-mtcmos-driver";
+hisilicon,mtcmos-steady-us = <10>;
+hisilicon,mtcmos-sc-on-base = <0xf780>;
+hisilicon,mtcmos-acpu-on-base = <0xf65a>;
+
+mtcmos1: regulator@a1{
+regulator-name = "G3D_PD_VDD";
+regulator-compatible = "mtcmos1";
+hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+hisilicon,ctrl-data = <1 0x1>;
+};
+mtcmos2: regulator@a2{
+regulator-name = "SOC_MED";
+regulator-compatible = "mtcmos2";
+hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+hisilicon,ctrl-data = <2 0x1>;
+};
+};
--
1.9.1
--
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