Re: [PATCH v3 09/33] nds32: Cache and TLB routines
On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > I think it should be fine if an interruption between mtsr_dsb and > tlbop_rwr because this is a optimization by sw. Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the vaddr, it will get wrong data unless the entry has been replaced out.
Re: [PATCH v3 09/33] nds32: Cache and TLB routines
On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote:
> 2017-12-13 16:19 GMT+08:00 Guo Ren <ren_...@c-sky.com>:
> > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
> >
> >> I think it should be fine if an interruption between mtsr_dsb and
> >> tlbop_rwr because this is a optimization by sw.
> >
> > Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will
> > break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the
> > vaddr, it will get wrong data unless the entry has been replaced out.
>
> Hi, Guo Ren:
>
> Thanks. I get your point.
> It is needed to be protected.
> I will fix it in the next version patch.
>
> if (vma->vm_mm == current->active_mm) {
> local_irq_save(flags);
> __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
> __nds32__tlbop_rwr(*pte);
> __nds32__isb();
> local_irq_restore(flags);
> }
If hardware tlbop_rwr could invalid NDS32_SR_TLB_VPN, then you needn't
protect.
I mean:
mtsr addr1 NDS32_SR_TLB_VPN
mtsr addr2 NDS32_SR_TLB_VPN
tlbop_rwr(*pte) // OK, and it will hit a hardware invalid bit internal.
tlbop_rwr(*pte) // SR_TLB_VPN invalided, then it will not cause problem.
:) How my idea?
Re: [PATCH v3 09/33] nds32: Cache and TLB routines
Hello, CPU team could improve the tlbop_*. Eg: Design a hardware internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr SR_TLB_VPN will valid it. So: On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote: > mtsr addr1 NDS32_SR_TLB_VPN > interrupt coming > mtsr addr2 NDS32_SR_TLB_VPN <- TLB_VPN has been set to addr2 mtsr SR_TLB_VPN will valid the flag bit > tlbop_rwr(*pte); tlbop_rwr will invalid SR_TLB_VPN flag bit > interrupt finish > tlbop_rwr(*pte); <- it will use the wrong TLB_VPN Because SR_TLB_VPN is in a invalid state, no operation happen on tlbop_rwr. Then they are atomic safe ,no spin_lock_irq need. :) Guo Ren
Re: [PATCH v3 07/33] nds32: MMU initialization
Hi Greentime,
On Fri, Dec 08, 2017 at 05:11:50PM +0800, Greentime Hu wrote:
[...]
>
> diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
[...]
> +void *kmap(struct page *page)
> +{
> + unsigned long vaddr;
> + might_sleep();
> + if (!PageHighMem(page))
> + return page_address(page);
> + vaddr = (unsigned long)kmap_high(page);
Here should invalid the cpu_mmu_tlb's entry, Or invalid it in the
set_pte().
eg:
vaddr0 = kmap(page0)
*vaddr0 = val0 //It will cause tlb-miss, and hard-refill to MMU-tlb
kunmap(page0)
vaddr1 = kmap(page1) // Mostly vaddr1 = vaddr0
val = vaddr1; //No tlb-miss and it will get page0's val not page1, because
last expired vaddr0's entry is left in CPU-MMU-tlb.
Best Regards
Guo Ren
Re: [PATCH v3 07/33] nds32: MMU initialization
On Mon, Dec 18, 2017 at 07:21:30PM +0800, Greentime Hu wrote:
> Hi, Guo Ren:
>
> 2017-12-18 17:08 GMT+08:00 Guo Ren <ren_...@c-sky.com>:
> > Hi Greentime,
> >
> > On Fri, Dec 08, 2017 at 05:11:50PM +0800, Greentime Hu wrote:
> > [...]
> >>
> >> diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
> > [...]
> >> +void *kmap(struct page *page)
> >> +{
> >> + unsigned long vaddr;
> >> + might_sleep();
> >> + if (!PageHighMem(page))
> >> + return page_address(page);
> >> + vaddr = (unsigned long)kmap_high(page);
> > Here should invalid the cpu_mmu_tlb's entry, Or invalid it in the
> > set_pte().
> >
> > eg:
> > vaddr0 = kmap(page0)
> > *vaddr0 = val0 //It will cause tlb-miss, and hard-refill to MMU-tlb
> > kunmap(page0)
> > vaddr1 = kmap(page1) // Mostly vaddr1 = vaddr0
> > val = vaddr1; //No tlb-miss and it will get page0's val not page1, because
> > last expired vaddr0's entry is left in CPU-MMU-tlb.
> >
>
> Thanks.
> I will add __nds32__tlbop_inv(vaddr); to invalidate this mapping
> before retrun vaddr.
Sorry, perhaps I'm wrong. See
kmap->kmap_high->map_new_virtual->get_next_pkmap_nr(color).
Seems pkmap will return the vaddr by vaddr + 1 until
no_more_pkmaps(), and then flush_all_zero_pkmaps.
Just kmap_atomic need it, and you've done.
But I don't know why mips need flush_tlb_one in
arch/mips/mm/highmem.c:kmap(). VIPT? but kmap give the get_pkmap_color
for aliasing.
Best Regards
Guo Ren
Re: [PATCH v3 09/33] nds32: Cache and TLB routines
On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greent...@andestech.com>
[...]
> diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
[...]
> +#ifndef CONFIG_CPU_CACHE_ALIASING
> +void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
> + pte_t * pte)
[...]
> + if (vma->vm_mm == current->active_mm) {
> +
> + __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
> + __nds32__tlbop_rwr(*pte);
> + __nds32__isb();
If there is an interruption between "mtsr_dsb" and "tlbop_rwr" and a
update_mmu_cache() is invoked again, then an error page mapping is
set up in your tlb-buffer when tlbop_rwr is excuted from interrupt.
Because it's another addr in NDS32_SR_TLB_VPN.
It seems that tlb-hardrefill can help build tlb-buffer mapping, why you
update it in this software way?
Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
Hi Randy, On Sun, Jul 01, 2018 at 02:01:52PM -0700, Randy Dunlap wrote: > Hi, > Just a few comments... > Thx for your review. I'll fixup all of you mentioned and self-check again. Guo Ren
Re: [PATCH V2 07/19] csky: MMU and page table management
On Mon, Jul 02, 2018 at 06:29:15AM -0700, Christoph Hellwig wrote: > This commit is missing an explanation. The patch is for abiv1 & abiv2 CPU series' MMU support. - abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem. - abiv2 CPUs are all PIPT cache and they could support highmem. We seperate abiv1 and abiv2 into two direcotries for coding convention. > For the dma-mapping code please use the generic kernel/dma/noncoherent.c > code instead of duplicating it. Thx for the tips and I think you mean the lib/dma-noncoherent.c in the lastest kernel source and not in linux-4.16.2. I'll rebase on the newest RC version of linux in next version patch and reuse the code in lib/dma-noncoherent.c. Current csky_dma_alloc implementation is not good, it use 512MB uncached area to mirror the Normal cachable-512MB area. In next version patch, we will increase the max-Normal memory zone to (1GB + 768MB). In csky_dma_alloc we will seperate the atomic_dma and non-atomic_dma and reserve the area in fixmap area. Here is my memory layout plan in next version patch: Fixmap : 0xffc02000 – 0xf000 (4 MB - 12KB) kmap_atomic, dma_atomic ... Pkmap: 0xff80 – 0xffc0 (4 MB)PTR_PER_PTE = 1024 Vmalloc : 0xf020 – 0xff00 (238 MB) max: 238MB + 256MB + 1GB Lowmem : 0x8000 – 0xf000 (1G + 768 MB) Guo Ren
Re: [PATCH V2 19/19] irqchip: add C-SKY irqchip drivers
On Mon, Jul 02, 2018 at 09:27:13PM -0600, Rob Herring wrote: > Commit message needed. Ok > Do you mean "legacy"? Yes, it's from arch/csky/Kconfig.debug, and I'll correct it in next version patch. > It would be better to make this run-time so you can support multiple > platforms in one build. You should be able to determine this from DT. The CSKY_VECIRQ_LEGACY means when cpu receive the IRQ, it will directly enter into the exception vector entry indexed by IRQ number. Just some old SOC need the feature. We reserve it just as we've mentioned in arch/csky/Kconfig.debug: config CSKY_VECIRQ_LEGENCY bool "Use legency IRQ vector for interrupt, it's for SOC bugfix." help It's a deprecated method for arch/csky. Don't use it, unless your SOC has bug. As we need this config to setup the vector tables in arch/csky/kernel/traps.c, "determine this from DT" isn't suitable for us. > > +IRQCHIP_DECLARE(csky_intc_v1, "csky,intc-v1", csky_intc_v1_init); > > DT bindings must be documented. And the vendor prefix must also be > registered in vendor-prefixes.txt. Ok, thx for the tips. I'll follow the rules. > > +IRQCHIP_DECLARE(csky_intc_v2, "csky,intc-v2", csky_intc_v2_init); > > And this one. Use of v1, v2, etc. is generally discouraged unless > there is some strict versioning behind it. Most bindings use > implementation specific compatible strings (which typically means the > SoC name/number as part of it). > > +IRQCHIP_DECLARE(nationalchip_intc_v1_ave, "nationalchip,intc-v1,ave", > > intc_init); > > Here too. And your timers as well. "csky,intc-v1/v2" are used in many SOCs, just like "arm,gic-v2/v3". So may I change them like these?: csky,intc-v1 >>> csky,ck807-intc csky,ck810-intc csky,ck860-intc csky,intc-v2 >>> csky,ck860-mpintc nationalchip,intc-v1,ave >>> nationalchip,ck610-gx6605s-intc > You'll also need to do cpu bindings as well especially for SMP. Ok, thx for tips.
Re: [PATCH V2 02/19] csky: defconfig
On Mon, Jul 02, 2018 at 09:16:27PM -0600, Rob Herring wrote: > > Are these configs mutually exclusive? We try to have one kernel build > serve many platforms. So you'd probably want to divide things between > the 2 ABIs. Yes, they are mutually exclusive, and may I prepare defconfigs like these: abiv1_defconfig abiv2_defconfig (ck807 ck810 ck860 are also mutually exclusive in -mcpu=ck807/ck810/ck860, you need "make menuconfig" to select correct CPU, so they couldn't be determined from DT. just like ARMv5, ARMv7-A and ARMv7-M) > It looks like you still have lots of options enabled that I wouldn't > expect you to need. Start with something more minimal for what you > need to boot and support upstream. Ok, I'll clean them up in next version patch. > For a full config, you can use allmodconfig at least to build test. Thx for the tip. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On Mon, Jul 02, 2018 at 09:33:51PM -0600, Rob Herring wrote: > > +config CSKY_BUILTIN_DTB > > + bool "Use kernel builtin dtb" > > + > > +config CSKY_BUILTIN_DTB_NAME > > + string "kernel builtin dtb name" > > + depends on CSKY_BUILTIN_DTB > > +endmenu > > These options generally exist for backwards compatibility with legacy > bootloaders that don't support DT which shouldn't apply here given > this is a new arch. If we need this for other reasons, it should not > be an architecture specific option. We want the BUILTIN_DTB for some boards and they don't need change dtb at all. And I just follow other archs BUILTIN_DTB in their Kconfig. eg: xtensa, h8300, mips, nds32, sh, openrisc, arc ... I just keep this in Kconfig.debug and it's not a recommended method. Guo Ren
[PATCH V2 04/19] csky: Exception handling
Signed-off-by: Guo Ren
---
arch/csky/abiv1/alignment.c | 332
arch/csky/abiv1/inc/abi/entry.h | 152 +++
arch/csky/abiv2/inc/abi/entry.h | 149 +++
arch/csky/include/asm/traps.h | 39
arch/csky/include/asm/unistd.h | 4 +
arch/csky/kernel/cpu-probe.c| 83
arch/csky/kernel/entry.S| 407
arch/csky/kernel/traps.c| 167 +
arch/csky/mm/fault.c| 223 ++
9 files changed, 1556 insertions(+)
create mode 100644 arch/csky/abiv1/alignment.c
create mode 100644 arch/csky/abiv1/inc/abi/entry.h
create mode 100644 arch/csky/abiv2/inc/abi/entry.h
create mode 100644 arch/csky/include/asm/traps.h
create mode 100644 arch/csky/include/asm/unistd.h
create mode 100644 arch/csky/kernel/cpu-probe.c
create mode 100644 arch/csky/kernel/entry.S
create mode 100644 arch/csky/kernel/traps.c
create mode 100644 arch/csky/mm/fault.c
diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c
new file mode 100644
index 000..5acc86f
--- /dev/null
+++ b/arch/csky/abiv1/alignment.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+
+static int align_enable = 1;
+static int align_count = 0;
+
+static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
+{
+ return *((int *)&(regs->a0) - 2 + rx);
+}
+
+static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
+{
+ *((int *)&(regs->a0) - 2 + rx) = val;
+}
+
+/*
+ * Get byte-value from addr and set it to *valp.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldb_asm(uint32_t addr, uint32_t *valp)
+{
+ uint32_t val;
+ int err;
+
+ if (!access_ok(VERIFY_READ, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "ldb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err), "=r"(val)
+ : "r" (addr)
+ );
+
+ *valp = val;
+
+ return err;
+}
+
+/*
+ * Put byte-value to addr.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static volatile int stb_asm(uint32_t addr, uint32_t val)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "stb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err)
+ : "r"(val), "r" (addr)
+ );
+
+ return err;
+}
+
+/*
+ * Get half-word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ if (ldb_asm(addr, ))
+ return 1;
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store half-word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ byte0 = byte1 = get_ptreg(regs, rz);
+
+ byte0 &= 0xff;
+
+ if (stb_asm(addr, byte0))
+ return 1;
+
+ addr += 1;
+ byte1 = (byte1 >> 8) & 0xff;
+ if (stb_asm(addr, byte1))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Get word from [rx + imm]
+ *
+ * Success: retur
[PATCH V2 14/19] csky: User access
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 397
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 668 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..81063c3
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void * addr, unsigned long size)
+{
+return (((unsigned long)addr < current_thread_info()->addr_limit.seg) &&
+ ((unsigned long)(addr + size) <
current_thread_info()->addr_limit.seg));
+}
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr,0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x,ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x,ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x,ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size)\
+({ \
+ long __pu_err=0;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if(__pu_addr){ \
+ __put_user_size(__pu_val, (__pu_addr), (size), __pu_err); \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x,ptr,size)\
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x,ptr,size,retval) \
+do {\
+ retval = 0; \
+ switch (size) { \
+ case 1: __put_user_asm_b(x, ptr, retval); break;\
+ case 2: __put_user_asm_h(x, ptr, retval); break;\
+ case 4: __put_user_asm_w(x, ptr, retval); break;\
+ case 8: __put_user_asm_64(x, ptr, retval); break; \
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about,
[PATCH V2 09/19] csky: VDSO and rt_sigreturn
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/vdso.h | 17
arch/csky/abiv2/inc/abi/vdso.h | 18 +
arch/csky/include/asm/vdso.h | 12 ++
arch/csky/kernel/vdso.c| 89 ++
4 files changed, 136 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/vdso.h
create mode 100644 arch/csky/abiv2/inc/abi/vdso.h
create mode 100644 arch/csky/include/asm/vdso.h
create mode 100644 arch/csky/kernel/vdso.c
diff --git a/arch/csky/abiv1/inc/abi/vdso.h b/arch/csky/abiv1/inc/abi/vdso.h
new file mode 100644
index 000..a99f0e4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/vdso.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r1, 127 */
+ err |= __put_user(0x67f1, ptr + 0);
+ /* addi r1, (139 - 127) */
+ err |= __put_user(0x20b1, ptr + 1);
+ /* trap 0 */
+ err |= __put_user(0x0008, ptr + 2);
+
+ return err;
+}
diff --git a/arch/csky/abiv2/inc/abi/vdso.h b/arch/csky/abiv2/inc/abi/vdso.h
new file mode 100644
index 000..aa2d489
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/vdso.h
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r7, 173 */
+ err |= __put_user(0xea07, ptr);
+ err |= __put_user(0x008b, ptr+1);
+
+ /* trap 0 */
+ err |= __put_user(0xc000, ptr+2);
+ err |= __put_user(0x2020, ptr+3);
+
+ return err;
+}
diff --git a/arch/csky/include/asm/vdso.h b/arch/csky/include/asm/vdso.h
new file mode 100644
index 000..b275440
--- /dev/null
+++ b/arch/csky/include/asm/vdso.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_VDSO_H
+#define __ASM_CSKY_VDSO_H
+
+#include
+
+struct csky_vdso {
+ unsigned short rt_signal_retcode[4];
+};
+
+#endif /* __ASM_CSKY_VDSO_H */
diff --git a/arch/csky/kernel/vdso.c b/arch/csky/kernel/vdso.c
new file mode 100644
index 000..dd59aae
--- /dev/null
+++ b/arch/csky/kernel/vdso.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+static struct page *vdso_page;
+
+static int __init init_vdso(void)
+{
+ struct csky_vdso *vdso;
+ int err = 0;
+
+ vdso_page = alloc_page(GFP_KERNEL);
+ if (!vdso_page)
+ panic("Cannot allocate vdso");
+
+ vdso = vmap(_page, 1, 0, PAGE_KERNEL);
+ if (!vdso)
+ panic("Cannot map vdso");
+
+ clear_page(vdso);
+
+ /*
+* __NR_rt_sigreturn must be 173
+* Because gcc/config/csky/linux-unwind.h use hard code to parse
rt_sigframe.
+*/
+ err = setup_vdso_page(vdso->rt_signal_retcode);
+ if (err) panic("Cannot set signal return code, err: %x.", err);
+
+ dcache_wb_range((unsigned long)vdso, (unsigned long)vdso + 16);
+
+ vunmap(vdso);
+
+ return 0;
+}
+subsys_initcall(init_vdso);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ int ret;
+ unsigned long addr;
+ struct mm_struct *mm = current->mm;
+
+ down_write(>mmap_sem);
+
+ addr = get_unmapped_area(NULL, STACK_TOP, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(
+ mm,
+ addr,
+ PAGE_SIZE,
+ VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+ _page);
+ if (ret)
+ goto up_fail;
+
+ mm->context.vdso = (void *)addr;
+
+up_fail:
+ up_write(>mmap_sem);
+ return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm == NULL)
+ return NULL;
+
+ if (vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+ else
+ return NULL;
+}
+
--
2.7.4
[PATCH V2 01/19] csky: Build infrastructure
Signed-off-by: Guo Ren --- arch/csky/Kconfig | 211 + arch/csky/Kconfig.debug| 29 + arch/csky/Makefile | 92 ++ arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 4 + arch/csky/boot/Makefile| 25 arch/csky/boot/dts/Makefile| 14 +++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 72 +++ arch/csky/include/uapi/asm/Kbuild | 33 ++ arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 ++ 13 files changed, 511 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..cfeb312 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,211 @@ +config CSKY + bool + default y + select ARCH_USE_BUILTIN_BSWAP + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_PERF_EVENTS + select HAVE_C_RECORDMCOUNT + select HAVE_KPROBES + select HAVE_KRETPROBES + select HAVE_DMA_API_DEBUG + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP cpu need "ldex" instrcutions to keep atomic. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause a illegal + instruction exception. + In kernel we parse the *regs->pc to determine wether send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config HZ + int + default 100 + +config GENERIC_CSUM + bool + default y + +config GENERIC_HWEIGHT + bool + default y + +config MMU + bool + default y + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config TIME_LOW_RES + bool + default y + +config TRACE_IRQFLAGS_SUPPORT + bool + default y + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +comment "Processor type" + +choice + prompt "CPU MODEL" + default CPU_CK610 + +config CPU_CK610 + bool "CSKY CPU ck610" + select CPU_NEED_TLBSYNC + select CPU_NEED_SOFTALIGN + select CPU_NO_USER_BKPT + +config CPU_CK810 + bool "CSKY CPU ck810" + select CPU_HAS_HILO + select CPU_NEED_TLBSYNC + +config CPU_CK807 + bool "CSKY CPU ck807" + select CPU_HAS_HILO + +config CPU_CK860 + bool "CSKY CPU ck860" + select CPU_HAS_TLBI + select CPU_HAS_CACHEV2 + select CPU_HAS_LDSTEX +endchoice + +config CPU_TLB_SIZE + int + default "128" if(CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if(CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if(CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"
[PATCH V2 08/19] csky: Process management and Signal
Signed-off-by: Guo Ren
---
arch/csky/abiv2/fpu.c | 242 ++
arch/csky/abiv2/inc/abi/fpu.h | 219
arch/csky/include/asm/mmu_context.h | 158 ++
arch/csky/include/asm/processor.h | 123 +++
arch/csky/include/asm/thread_info.h | 73 +++
arch/csky/include/uapi/asm/sigcontext.h | 13 ++
arch/csky/kernel/process.c | 134
arch/csky/kernel/signal.c | 350
arch/csky/kernel/time.c | 12 ++
9 files changed, 1324 insertions(+)
create mode 100644 arch/csky/abiv2/fpu.c
create mode 100644 arch/csky/abiv2/inc/abi/fpu.h
create mode 100644 arch/csky/include/asm/mmu_context.h
create mode 100644 arch/csky/include/asm/processor.h
create mode 100644 arch/csky/include/asm/thread_info.h
create mode 100644 arch/csky/include/uapi/asm/sigcontext.h
create mode 100644 arch/csky/kernel/process.c
create mode 100644 arch/csky/kernel/signal.c
create mode 100644 arch/csky/kernel/time.c
diff --git a/arch/csky/abiv2/fpu.c b/arch/csky/abiv2/fpu.c
new file mode 100644
index 000..330a908
--- /dev/null
+++ b/arch/csky/abiv2/fpu.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+
+#define MTCR_MASK 0xFC00FFE0
+#define MFCR_MASK 0xFC00FFE0
+#define MTCR_DIST 0xC0006420
+#define MFCR_DIST 0xC0006020
+
+void __init init_fpu(void)
+{
+ mtcr("cr<1, 2>", 0);
+}
+
+/*
+ * fpu_libc_helper() is to help libc to excute:
+ * - mfcr %a, cr<1, 2>
+ * - mfcr %a, cr<2, 2>
+ * - mtcr %a, cr<1, 2>
+ * - mtcr %a, cr<2, 2>
+ */
+int fpu_libc_helper(struct pt_regs * regs)
+{
+ int fault;
+ unsigned long instrptr, regx = 0;
+ unsigned long index = 0, tmp = 0;
+ unsigned long tinstr = 0;
+ u16 instr_hi, instr_low;
+
+ instrptr = instruction_pointer(regs);
+ if (instrptr & 1) return 0;
+
+ fault = __get_user(instr_low, (u16 *)instrptr);
+ if (fault) return 0;
+
+ fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
+ if (fault) return 0;
+
+ tinstr = instr_hi | ((unsigned long)instr_low << 16);
+
+ if (((tinstr >> 21) & 0x1F) != 2) return 0;
+
+ if ((tinstr & MTCR_MASK) == MTCR_DIST)
+ {
+ index = (tinstr >> 16) & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = tinstr & 0x1F;
+ if (tmp > 2) return 0;
+
+ regx = *(>a0 + index);
+
+ if(tmp == 1)
+ mtcr("cr<1, 2>", regx);
+ else if (tmp == 2)
+ mtcr("cr<2, 2>", regx);
+ else
+ return 0;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ if ((tinstr & MFCR_MASK) == MFCR_DIST) {
+ index = tinstr & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = ((tinstr >> 16) & 0x1F);
+ if (tmp > 2) return 0;
+
+ if (tmp == 1)
+ regx = mfcr("cr<1, 2>");
+ else if (tmp == 2)
+ regx = mfcr("cr<2, 2>");
+ else
+ return 0;
+
+ *(>a0 + index) = regx;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ return 0;
+}
+
+void fpu_fpe(struct pt_regs * regs)
+{
+ int sig;
+ unsigned int fesr;
+ siginfo_t info;
+ asm volatile("mfcr %0, cr<2, 2>":"=r"(fesr));
+
+ if(fesr & FPE_ILLE){
+ info.si_code = ILL_ILLOPC;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_IDC){
+ info.si_code = ILL_ILLOPN;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_FEC){
+ sig = SIGFPE;
+ if(fesr & FPE_IOC){
+ info.si_code = FPE_FLTINV;
+ }
+ else if(fesr & FPE_DZC){
+ info.si_code = FPE_FLTDIV;
+ }
+ else if(fesr & FPE_UFC){
+ info.si_code = FPE_FLTUND;
+ }
+ else if(fesr & FPE_OFC){
+ info.si_code = FPE_FLTOVF;
+ }
+ else if(fesr & FPE_IXC){
+ info.si_code = FPE_FLTRES;
+ }
+ else {
+ info.si_code = NSIGFPE;
+ }
+ }
+ else {
+ info.si_code = NSIGFPE;
+ sig = SIGFPE;
+ }
+ info.si_signo = SIGFPE;
+ info.si_errno = 0;
+ info.si_addr = (void *)regs->p
[PATCH V2 19/19] irqchip: add C-SKY irqchip drivers
Signed-off-by: Guo Ren
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-csky-v1.c | 126
drivers/irqchip/irq-csky-v2.c | 191 +
drivers/irqchip/irq-nationalchip.c | 131 +
4 files changed, 449 insertions(+)
create mode 100644 drivers/irqchip/irq-csky-v1.c
create mode 100644 drivers/irqchip/irq-csky-v2.c
create mode 100644 drivers/irqchip/irq-nationalchip.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d27e3e3..51e7316 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o
obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
+obj-$(CONFIG_CSKY) += irq-csky-v1.o irq-csky-v2.o
irq-nationalchip.o
diff --git a/drivers/irqchip/irq-csky-v1.c b/drivers/irqchip/irq-csky-v1.c
new file mode 100644
index 000..64ea564
--- /dev/null
+++ b/drivers/irqchip/irq-csky-v1.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_CSKY_VECIRQ_LEGENCY
+#include
+#endif
+
+static void __iomem *reg_base;
+
+#define INTC_ICR 0x00
+#define INTC_ISR 0x00
+#define INTC_NEN31_00 0x10
+#define INTC_NEN63_32 0x28
+#define INTC_IFR31_00 0x08
+#define INTC_IFR63_32 0x20
+#define INTC_SOURCE0x40
+
+#define INTC_IRQS 64
+
+#define INTC_ICR_AVE BIT(31)
+
+#define VEC_IRQ_BASE 32
+
+static struct irq_domain *root_domain;
+
+static void __init ck_set_gc(void __iomem *reg_base, u32 irq_base,
+u32 mask_reg)
+{
+ struct irq_chip_generic *gc;
+
+ gc = irq_get_domain_generic_chip(root_domain, irq_base);
+ gc->reg_base = reg_base;
+ gc->chip_types[0].regs.mask = mask_reg;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
+}
+
+static struct irq_domain *root_domain;
+static void ck_irq_handler(struct pt_regs *regs)
+{
+#ifdef CONFIG_CSKY_VECIRQ_LEGENCY
+ irq_hw_number_t irq = ((mfcr("psr") >> 16) & 0xff) - VEC_IRQ_BASE;
+#else
+ irq_hw_number_t irq = readl_relaxed(reg_base + INTC_ISR) & 0x3f;
+#endif
+ handle_domain_irq(root_domain, irq, regs);
+}
+
+#define expand_byte_to_word(i) (i|(i<<8)|(i<<16)|(i<<24))
+static inline void setup_irq_channel(void __iomem *reg_base)
+{
+ int i;
+
+ /*
+* There are 64 irq nums and irq-channels and one byte per channel.
+* Setup every channel with the same hwirq num.
+*/
+ for (i = 0; i < INTC_IRQS; i += 4) {
+ writel_relaxed(expand_byte_to_word(i) + 0x00010203,
+ reg_base + INTC_SOURCE + i);
+ }
+}
+
+static int __init
+csky_intc_v1_init(struct device_node *node, struct device_node *parent)
+{
+ u32 clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+ int ret;
+
+ if (parent) {
+ pr_err("C-SKY Intc not a root irq controller\n");
+ return -EINVAL;
+ }
+
+ reg_base = of_iomap(node, 0);
+ if (!reg_base) {
+ pr_err("C-SKY Intc unable to map: %p.\n", node);
+ return -EINVAL;
+ }
+
+ writel_relaxed(0, reg_base + INTC_NEN31_00);
+ writel_relaxed(0, reg_base + INTC_NEN63_32);
+
+#ifndef CONFIG_CSKY_VECIRQ_LEGENCY
+ writel_relaxed(INTC_ICR_AVE, reg_base + INTC_ICR);
+#else
+ writel_relaxed(0, reg_base + INTC_ICR);
+#endif
+
+ setup_irq_channel(reg_base);
+
+ root_domain = irq_domain_add_linear(node, INTC_IRQS,
_generic_chip_ops, NULL);
+ if (!root_domain) {
+ pr_err("C-SKY Intc irq_domain_add failed.\n");
+ return -ENOMEM;
+ }
+
+ ret = irq_alloc_domain_generic_chips(root_domain, 32, 1,
+"csky_intc_v1", handle_level_irq,
+clr, 0, 0);
+ if (ret) {
+ pr_err("C-SKY Intc irq_alloc_gc failed.\n");
+ return -ENOMEM;
+ }
+
+ ck_set_gc(reg_base, 0, INTC_NEN31_00);
+ ck_set_gc(reg_base, 32, INTC_NEN63_32);
+
+ set_handle_irq(ck_irq_handler);
+
+ return 0;
+}
+IRQCHIP_DECLARE(csky_intc_v1, "csky,intc-v1", csky_intc_v1_init);
+
diff --git a/drivers/irqchip/irq-csky-v2.c b/drivers/irqchip/irq-csky-v2.c
new file mode 100644
index 000..b588364
--- /dev/null
+++ b/drivers/irqchip/irq-csky-v2.c
@@ -0,0 +1,191 @@
+// SPDX-License-Ident
[PATCH V2 00/19] C-SKY(csky) Linux Kernel Port
fix compile error with CONFIG_AUDIT 1989292 csky: revert some back with cleanup unistd.h f1454fe csky: cleanup unistd.h 5d2985f csky: cleanup Kconfig and Makefile. 423d97e csky: cancel subdirectories cae2af4 csky: use asm-generic/fcntl.h Guo Ren (19): csky: Build infrastructure csky: defconfig csky: Kernel booting csky: Exception handling csky: System Call csky: Cache and TLB routines csky: MMU and page table management csky: Process management and Signal csky: VDSO and rt_sigreturn csky: IRQ handling csky: Atomic operations csky: ELF and module probe csky: Library functions csky: User access csky: Debug and Ptrace GDB csky: SMP support csky: Misc headers clocksource: add C-SKY clocksource drivers irqchip: add C-SKY irqchip drivers arch/csky/Kconfig| 211 arch/csky/Kconfig.debug | 29 ++ arch/csky/Makefile | 92 ++ arch/csky/abiv1/Makefile | 8 + arch/csky/abiv1/alignment.c | 332 +++ arch/csky/abiv1/bswapdi.c| 18 + arch/csky/abiv1/bswapsi.c| 15 + arch/csky/abiv1/cacheflush.c | 51 +++ arch/csky/abiv1/inc/abi/cacheflush.h | 42 +++ arch/csky/abiv1/inc/abi/ckmmu.h | 80 + arch/csky/abiv1/inc/abi/entry.h | 152 + arch/csky/abiv1/inc/abi/page.h | 26 ++ arch/csky/abiv1/inc/abi/pgtable-bits.h | 36 ++ arch/csky/abiv1/inc/abi/reg_ops.h| 47 +++ arch/csky/abiv1/inc/abi/regdef.h | 15 + arch/csky/abiv1/inc/abi/tlb.h| 11 + arch/csky/abiv1/inc/abi/vdso.h | 17 + arch/csky/abiv1/memcpy.S | 344 +++ arch/csky/abiv1/mmap.c | 65 arch/csky/abiv2/Makefile | 4 + arch/csky/abiv2/cacheflush.c | 55 arch/csky/abiv2/fpu.c| 242 ++ arch/csky/abiv2/inc/abi/cacheflush.h | 38 +++ arch/csky/abiv2/inc/abi/ckmmu.h | 88 + arch/csky/abiv2/inc/abi/entry.h | 149 + arch/csky/abiv2/inc/abi/fpu.h| 219 arch/csky/abiv2/inc/abi/page.h | 14 + arch/csky/abiv2/inc/abi/pgtable-bits.h | 36 ++ arch/csky/abiv2/inc/abi/reg_ops.h| 38 +++ arch/csky/abiv2/inc/abi/regdef.h | 15 + arch/csky/abiv2/inc/abi/tlb.h| 12 + arch/csky/abiv2/inc/abi/vdso.h | 18 + arch/csky/abiv2/memcpy.c | 43 +++ arch/csky/boot/Makefile | 25 ++ arch/csky/boot/dts/Makefile | 14 + arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/configs/gx66xx_defconfig | 549 +++ arch/csky/configs/qemu_ck807_defconfig | 541 ++ arch/csky/include/asm/Kbuild | 72 arch/csky/include/asm/addrspace.h| 10 + arch/csky/include/asm/barrier.h | 19 ++ arch/csky/include/asm/bitops.h | 277 arch/csky/include/asm/cache.h| 29 ++ arch/csky/include/asm/cacheflush.h | 9 + arch/csky/include/asm/checksum.h | 77 + arch/csky/include/asm/cmpxchg.h | 68 arch/csky/include/asm/dma-mapping.h | 13 + arch/csky/include/asm/elf.h | 149 + arch/csky/include/asm/fixmap.h | 65 arch/csky/include/asm/highmem.h | 50 +++ arch/csky/include/asm/io.h | 23 ++ arch/csky/include/asm/irq.h | 10 + arch/csky/include/asm/irqflags.h | 49 +++ arch/csky/include/asm/mmu.h | 11 + arch/csky/include/asm/mmu_context.h | 158 + arch/csky/include/asm/page.h | 104 ++ arch/csky/include/asm/pgalloc.h | 108 ++ arch/csky/include/asm/pgtable.h | 301 + arch/csky/include/asm/processor.h| 123 +++ arch/csky/include/asm/reg_ops.h | 16 + arch/csky/include/asm/segment.h | 18 + arch/csky/include/asm/shmparam.h | 10 + arch/csky/include/asm/smp.h | 26 ++ arch/csky/include/asm/spinlock.h | 174 ++ arch/csky/include/asm/spinlock_types.h | 20 ++ arch/csky/include/asm/string.h | 19 ++ arch/csky/include/asm/syscall.h | 69 arch/csky/include/asm/syscalls.h | 14 + arch/csky/include/asm/thread_info.h | 73 arch/csky/include/asm/tlb.h | 19 ++ arch/csky/include/asm/tlbflush.h | 22 ++ arch/csky/include/asm/traps.h| 39 +++ arch/csky/include/asm/uaccess.h | 397 ++ arch/csky/include/asm/unistd.h | 4 + arch/csky/include/asm/vdso.h | 12 + arch/csky/include/uapi/asm/Kbuild| 33 ++ arch/csky/include/uapi/asm/byteorder.h | 14 + arch/csky/include/uapi/asm/cachectl.h| 13 +
[PATCH V2 07/19] csky: MMU and page table management
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/ckmmu.h| 80 +
arch/csky/abiv1/inc/abi/page.h | 26 +++
arch/csky/abiv1/inc/abi/pgtable-bits.h | 36
arch/csky/abiv1/mmap.c | 65 +++
arch/csky/abiv2/inc/abi/ckmmu.h| 88 ++
arch/csky/abiv2/inc/abi/page.h | 14 ++
arch/csky/abiv2/inc/abi/pgtable-bits.h | 36
arch/csky/include/asm/addrspace.h | 10 ++
arch/csky/include/asm/fixmap.h | 65 +++
arch/csky/include/asm/highmem.h| 50 ++
arch/csky/include/asm/mmu.h| 11 ++
arch/csky/include/asm/page.h | 104
arch/csky/include/asm/pgalloc.h| 108
arch/csky/include/asm/pgtable.h| 301 +
arch/csky/include/asm/segment.h| 18 ++
arch/csky/include/asm/shmparam.h | 10 ++
arch/csky/mm/dma-mapping.c | 216 +++
arch/csky/mm/highmem.c | 210 +++
arch/csky/mm/init.c| 122 +
arch/csky/mm/ioremap.c | 49 ++
20 files changed, 1619 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv1/inc/abi/page.h
create mode 100644 arch/csky/abiv1/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/abiv1/mmap.c
create mode 100644 arch/csky/abiv2/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv2/inc/abi/page.h
create mode 100644 arch/csky/abiv2/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/include/asm/addrspace.h
create mode 100644 arch/csky/include/asm/fixmap.h
create mode 100644 arch/csky/include/asm/highmem.h
create mode 100644 arch/csky/include/asm/mmu.h
create mode 100644 arch/csky/include/asm/page.h
create mode 100644 arch/csky/include/asm/pgalloc.h
create mode 100644 arch/csky/include/asm/pgtable.h
create mode 100644 arch/csky/include/asm/segment.h
create mode 100644 arch/csky/include/asm/shmparam.h
create mode 100644 arch/csky/mm/dma-mapping.c
create mode 100644 arch/csky/mm/highmem.c
create mode 100644 arch/csky/mm/init.c
create mode 100644 arch/csky/mm/ioremap.c
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h
new file mode 100644
index 000..e8e7d43
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/ckmmu.h
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_CKMMUV1_H
+#define __ASM_CSKY_CKMMUV1_H
+#include
+
+static inline void select_mmu_cp(void)
+{
+asm volatile("cpseti cp15\n");
+}
+
+static inline int read_mmu_index(void)
+{
+ return cprcr("cpcr0");
+}
+
+static inline void write_mmu_index(int value)
+{
+ cpwcr("cpcr0", value);
+}
+
+static inline int read_mmu_entrylo0(void)
+{
+ return cprcr("cpcr2") << 6;
+}
+
+static inline int read_mmu_entrylo1(void)
+{
+ return cprcr("cpcr3") << 6;
+}
+
+static inline void write_mmu_pagemask(int value)
+{
+ cpwcr("cpcr6", value);
+}
+
+static inline int read_mmu_entryhi(void)
+{
+ return cprcr("cpcr4");
+}
+
+static inline void write_mmu_entryhi(int value)
+{
+ cpwcr("cpcr4", value);
+}
+
+/*
+ * TLB operations.
+ */
+static inline void tlb_probe(void)
+{
+ cpwcr("cpcr8", 0x8000);
+}
+
+static inline void tlb_read(void)
+{
+ cpwcr("cpcr8", 0x4000);
+}
+
+static inline void tlb_invalid_all(void)
+{
+ cpwcr("cpcr8", 0x0400);
+}
+
+static inline void tlb_invalid_indexed(void)
+{
+ cpwcr("cpcr8", 0x0200);
+}
+
+static inline void setup_pgd(unsigned long pgd)
+{
+ cpwcr("cpcr29", pgd);
+}
+
+static inline unsigned long get_pgd(void)
+{
+ return cprcr("cpcr29");
+}
+#endif /* __ASM_CSKY_CKMMUV1_H */
+
diff --git a/arch/csky/abiv1/inc/abi/page.h b/arch/csky/abiv1/inc/abi/page.h
new file mode 100644
index 000..b0d2122
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/page.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+extern unsigned long shm_align_mask;
+extern void flush_dcache_page(struct page *);
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+ unsigned long addr2)
+{
+ return (addr1 ^ addr2) & shm_align_mask;
+}
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
+ struct page *page)
+{
+ clear_page(addr);
+ if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
+ flush_dcache_page(page);
+}
+
+static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
+ struct page *page)
+{
+ copy_page(to, from);
+ if (pages_do_alias((unsigned
[PATCH V2 11/19] csky: Atomic operations
Signed-off-by: Guo Ren
---
arch/csky/include/asm/cmpxchg.h| 68 +
arch/csky/include/asm/spinlock.h | 174 +
arch/csky/include/asm/spinlock_types.h | 20
arch/csky/kernel/atomic.S | 87 +
4 files changed, 349 insertions(+)
create mode 100644 arch/csky/include/asm/cmpxchg.h
create mode 100644 arch/csky/include/asm/spinlock.h
create mode 100644 arch/csky/include/asm/spinlock_types.h
create mode 100644 arch/csky/kernel/atomic.S
diff --git a/arch/csky/include/asm/cmpxchg.h b/arch/csky/include/asm/cmpxchg.h
new file mode 100644
index 000..1c30a28
--- /dev/null
+++ b/arch/csky/include/asm/cmpxchg.h
@@ -0,0 +1,68 @@
+#ifndef __ASM_CSKY_CMPXCHG_H
+#define __ASM_CSKY_CMPXCHG_H
+
+#ifdef CONFIG_CPU_HAS_LDSTEX
+#include
+#include
+
+#define __xchg(new, ptr, size) \
+({ \
+ __typeof__(ptr) __ptr = (ptr); \
+ __typeof__(new) __new = (new); \
+ __typeof__(*(ptr)) __ret; \
+ unsigned long tmp; \
+ switch (size) { \
+ case 4: \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " mov %1, %2 \n"\
+ " stex.w %1, (%3) \n"\
+ " bez %1, 1b \n"\
+ : "=" (__ret), "=" (tmp)\
+ : "r" (__new), "r"(__ptr) \
+ : "memory");\
+ smp_mb(); \
+ break; \
+ default:\
+ BUILD_BUG();\
+ } \
+ __ret; \
+})
+
+#define xchg(ptr, x) (__xchg((x), (ptr), sizeof(*(ptr
+
+#define __cmpxchg(ptr, old, new, size) \
+({ \
+ __typeof__(ptr) __ptr = (ptr); \
+ __typeof__(new) __new = (new); \
+ __typeof__(new) __tmp; \
+ __typeof__(old) __old = (old); \
+ __typeof__(*(ptr)) __ret; \
+ switch (size) { \
+ case 4: \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " cmpne %0, %4 \n"\
+ " bt 2f \n"\
+ " mov %1, %2 \n"\
+ " stex.w %1, (%3) \n"\
+ " bez %1, 1b \n"\
+ "2: \n"\
+ : "=" (__ret), "=" (__tmp) \
+ : "r" (__new), "r"(__ptr), "r"(__old) \
+ : "memory");\
+ smp_mb(); \
+ break; \
+ default:\
+ BUILD_BUG();\
+ } \
+ __ret; \
+})
+
+#define cmpxchg(ptr, o, n) \
+ (__cmpxchg((ptr), (o), (n), sizeof(*(ptr
+#else
+#include
+#endif
+
+#endif /* __ASM_CSKY_CMPXCHG_H */
diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
new file mode 100644
index 000..ca10d0e
--- /dev/null
+++ b/arch/csky/include/asm/spinlock.h
@@ -0,0 +1,174 @@
+#ifndef __ASM_CSKY_SPINLOCK_H
+#define __ASM_CSKY_SPINLOCK_H
+
+#include
+#include
+
+#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
+
+/** spin lock/unlock/trylock **/
+static inline void arch_spin_lock(arch_spinlock_t *lock)
+{
+ unsigned int *p = >lock;
+ unsigned int tmp;
+
+ asm volatile (
+
[PATCH V2 16/19] csky: SMP support
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 256
2 files changed, 282 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..9a53abf
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long));
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..42308cd
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,256 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPI_IRQ15
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ /* Order bit clearing and data access. */
+ mb();
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+
+ /* Order data access and bit testing. */
+ mb();
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const unsigned long *mask, unsigned long irq) =
NULL;
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long))
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ mb();
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ mb();
+ send_arch_ipi(cpumask_bits(to_whom), IPI_IRQ);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+static int ipi_dummy_dev;
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(IPI_IRQ, 0);
+}
+
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ irq_create_mapping(NULL, IPI_IRQ);
+
+ rc = request_percpu_irq(IPI_IRQ, handle_ipi, "IPI Interrupt",
_dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+static int csky_of_cpu(struct device_node *node)
+{
+ const char *status;
+ int cpu;
+
+ if (of_property_read_u32(node, "reg", ))
+ goto error;
+
+ if (cpu >= NR_CPUS)
+ goto error;
+
+ if (of_property_read_string(node, "status", ))
+ status = "enable";
+
+ if (strcmp(status, "disable") == 0)
+ goto error;
+
+ return cpu;
+error:
+ return -ENODEV;
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ cpu = csky_of_cpu(node);
+ if (cpu >= 0) {
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
+ }
+ }
+}
+
+extern void _start_smp_secondary(void);
+
+static
[PATCH V2 05/19] csky: System Call
Signed-off-by: Guo Ren
---
arch/csky/include/asm/syscall.h | 69 +
arch/csky/include/asm/syscalls.h| 14
arch/csky/include/uapi/asm/unistd.h | 63 +
arch/csky/kernel/syscall.c | 63 +
arch/csky/kernel/syscall_table.c| 12 +++
5 files changed, 221 insertions(+)
create mode 100644 arch/csky/include/asm/syscall.h
create mode 100644 arch/csky/include/asm/syscalls.h
create mode 100644 arch/csky/include/uapi/asm/unistd.h
create mode 100644 arch/csky/kernel/syscall.c
create mode 100644 arch/csky/kernel/syscall_table.c
diff --git a/arch/csky/include/asm/syscall.h b/arch/csky/include/asm/syscall.h
new file mode 100644
index 000..8966739
--- /dev/null
+++ b/arch/csky/include/asm/syscall.h
@@ -0,0 +1,69 @@
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include
+#include
+#include
+
+static inline int
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs_syscallid(regs);
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->a0 = regs->orig_a0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->a0;
+
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->a0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+int error, long val)
+{
+ regs->a0 = (long) error ?: val;
+}
+
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ args[0] = regs->orig_a0;
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+}
+
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, const unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+if (i == 0) {
+ regs->orig_a0 = args[0];
+ args++;
+ i++;
+ n--;
+}
+ memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+}
+
+#endif /* __ASM_SYSCALL_H */
diff --git a/arch/csky/include/asm/syscalls.h b/arch/csky/include/asm/syscalls.h
new file mode 100644
index 000..c478830
--- /dev/null
+++ b/arch/csky/include/asm/syscalls.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_SYSCALLS_H
+#define __ASM_CSKY_SYSCALLS_H
+
+#include
+
+long sys_cacheflush(void __user *, unsigned long, int);
+
+long sys_set_thread_area(unsigned long addr);
+
+long sys_csky_fadvise64_64(int fd, int advice, loff_t offset, loff_t len);
+
+#endif /* __ASM_CSKY_SYSCALLS_H */
diff --git a/arch/csky/include/uapi/asm/unistd.h
b/arch/csky/include/uapi/asm/unistd.h
new file mode 100644
index 000..0ea9b5a
--- /dev/null
+++ b/arch/csky/include/uapi/asm/unistd.h
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_RENAMEAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_CLONE
+#define __ARCH_WANT_SYS_FORK
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_IPC
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_VFORK
+#define __ARCH_WANT_SYS_WAITPID
+
+#include
+
+/*
+ * other define
+ */
+#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
+#define __NR_ipc (__NR_arch_specific_syscall + 1)
+__SYSCALL(__NR_ipc, sys_ipc)
+#define __NR_socketcall(__NR_arch_specific_syscall + 2)
+__SYSCALL(__NR_socketcall, sys_socketcall)
+#define __NR_ugetrlimit(__NR_arch_specific_syscall + 3)
+__SYSCALL(__NR_ugetrlimit, sys_getrlimit)
+#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
+#define __NR_sysfs (__NR_arch_specific_syscall + 5)
+__SYSCALL(__NR_sysfs, sys_sysfs)
+
+__SYSCALL(__NR_fadvise64_64, sys_csky_fadvise64_64)
+
+#define __NR_setgroups32
[PATCH V2 03/19] csky: Kernel booting
Signed-off-by: Guo Ren
---
arch/csky/kernel/head.S| 81 ++
arch/csky/kernel/setup.c | 148 +
arch/csky/kernel/vmlinux.lds.S | 65 ++
3 files changed, 294 insertions(+)
create mode 100644 arch/csky/kernel/head.S
create mode 100644 arch/csky/kernel/setup.c
create mode 100644 arch/csky/kernel/vmlinux.lds.S
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S
new file mode 100644
index 000..3f0be9a
--- /dev/null
+++ b/arch/csky/kernel/head.S
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+
+__HEAD
+ENTRY(_start)
+ /* set super user mode */
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, init_thread_union + THREAD_SIZE
+ mov sp, a3
+
+ jmpicsky_start
+END(_start)
+
+#ifdef CONFIG_SMP
+.align 10
+ENTRY(_start_smp_secondary)
+ /* Invalid I/Dcache BTB BHT */
+ movia3, 7
+ lslia3, 16
+ addia3, (1<<4) | 3
+ mtcra3, cr17
+
+ tlbi.all
+
+ /* setup PAGEMASK */
+ movia3, 0
+ mtcra3, cr<6, 15>
+
+ /* setup MEL0/MEL1 */
+ grs a0, _start_smp_pc
+_start_smp_pc:
+ bmaski a1, 13
+ andna0, a1
+ movia1, 0x0006
+ movia2, 0x1006
+ or a1, a0
+ or a2, a0
+ mtcra1, cr<2, 15>
+ mtcra2, cr<3, 15>
+
+ /* setup MEH */
+ mtcra0, cr<4, 15>
+
+ /* write TLB */
+ bgeni a3, 28
+ mtcra3, cr<8, 15>
+
+ /* setup msa0 & msa1 */
+ lrw a3, PHYS_OFFSET | 0x8e
+ mtcra3, cr<30, 15>
+ lrw a3, PHYS_OFFSET | 0x26
+ mtcra3, cr<31, 15>
+
+ /* enable MMU */
+ movia3, 1
+ mtcra3, cr18
+
+ jmpi_goto_mmu_on
+_goto_mmu_on:
+ movia3, 0xaa
+
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, secondary_stack
+ ld.wa3, (a3, 0)
+ mov sp, a3
+
+ jmpicsky_start_secondary
+END(_start_smp_secondary)
+#endif
diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c
new file mode 100644
index 000..b7e14c8
--- /dev/null
+++ b/arch/csky/kernel/setup.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+phys_addr_t __init_memblock memblock_end_of_REG0(void)
+{
+ return (memblock.memory.regions[0].base +
memblock.memory.regions[0].size);
+}
+
+phys_addr_t __init_memblock memblock_start_of_REG1(void)
+{
+ return memblock.memory.regions[1].base;
+}
+
+size_t __init_memblock memblock_size_of_REG1(void)
+{
+ return memblock.memory.regions[1].size;
+}
+
+static void __init csky_memblock_init(void)
+{
+ unsigned long zone_size[MAX_NR_ZONES];
+ unsigned long zhole_size[MAX_NR_ZONES];
+ signed long size;
+
+ memblock_reserve(__pa(_stext), _end - _stext);
+#ifdef CONFIG_BLK_DEV_INITRD
+ memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+
+ memset(zone_size, 0, sizeof(zone_size));
+ memset(zhole_size, 0, sizeof(zhole_size));
+
+ min_low_pfn = PFN_UP(memblock_start_of_DRAM());
+ max_low_pfn = PFN_UP(memblock_end_of_REG0());
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+
+ size = max_pfn - min_low_pfn;
+
+ if (memblock.memory.cnt > 1) {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
min_low_pfn;
+ zhole_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
max_low_pfn;
+ } else {
+ if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
+ zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
+ else {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
+ }
+ }
+
+#ifdef CONFIG_HIGHMEM
+ size = 0;
+ if(memblock.memory.cnt > 1) {
+ size = PFN_DOWN(memblock_size_of_REG1());
+ highstart_pfn = PFN_DOWN(memblock_start_of_REG1());
+ } else {
+ size = max_pfn - min_low_pfn - PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ highstart_pfn = min_low_pfn + PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ }
+
+ if (size > 0)
+ zone_siz
[PATCH V2 15/19] csky: Debug and Ptrace GDB
Signed-off-by: Guo Ren
---
arch/csky/include/uapi/asm/ptrace.h | 105 +
arch/csky/kernel/dumpstack.c| 65
arch/csky/kernel/ptrace.c | 288
3 files changed, 458 insertions(+)
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..f5228dd
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[64];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+unsigned long r5;
+unsigned long r6;
+unsigned long r7;
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+#else
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+unsigned long r12;
+unsigned long r13;
+unsigned long r14;
+#endif
+unsigned long r15;
+#if defined(__CSKYABIV2__)
+unsigned long r16;
+unsigned long r17;
+unsigned long r26;
+unsigned long r27;
+unsigned long r28;
+unsigned long r29;
+unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+void show_regs(struct pt_regs *);
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..d4be08a
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memory, it *may* be the address of a calling
+* routine; if so, print it so that someone tracing
+* down the cause of the crash will be able to figure
+* out the call path that was taken.
+*/
+ if (__kernel_text_address(addr)) {
+#ifndef CONFIG_KALLSYMS
+ if (i % 5 == 0)
+ pr_cont("\n ");
+#endif
+ pr_cont(" [<%08lx>] %pS\n", addr, (void *)addr);
+ i++;
+ }
+ }
+ pr_cont("\n");
+}
+
+void show_stack(struct task_struct *task, unsigned long *stack)
+{
+ unsigned long *p;
+ unsigned long *endstack;
+ int i;
+
+ if (!stack) {
+ if (task)
+ stack = (unsigned long *)task->thread.esp0
[PATCH V2 18/19] clocksource: add C-SKY clocksource drivers
Signed-off-by: Guo Ren
---
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-csky-v1.c | 169 +++
drivers/clocksource/timer-nationalchip.c | 165 ++
3 files changed, 335 insertions(+)
create mode 100644 drivers/clocksource/timer-csky-v1.c
create mode 100644 drivers/clocksource/timer-nationalchip.c
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index d6dec44..bbc567b 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
obj-$(CONFIG_H8300_TPU)+= h8300_tpu.o
obj-$(CONFIG_CLKSRC_ST_LPC)+= clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_CSKY) += timer-csky-v1.o timer-nationalchip.o
diff --git a/drivers/clocksource/timer-csky-v1.c
b/drivers/clocksource/timer-csky-v1.c
new file mode 100644
index 000..f3a822a
--- /dev/null
+++ b/drivers/clocksource/timer-csky-v1.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou NationalChip Science & Technology Co.,Ltd.
+#include
+#include
+#include
+#include
+#include
+
+#include "timer-of.h"
+
+#define PTIM_CTLR "cr<0, 14>"
+#define PTIM_TSR "cr<1, 14>"
+#define PTIM_CCVR_HI "cr<2, 14>"
+#define PTIM_CCVR_LO "cr<3, 14>"
+#define PTIM_LVR "cr<6, 14>"
+
+#define BITS_CSKY_TIMER56
+
+DECLARE_PER_CPU(struct timer_of, csky_to);
+
+static int csky_timer_irq;
+static int csky_timer_rate;
+
+static inline u64 get_ccvr(void)
+{
+ u32 lo, hi, t;
+
+ do {
+ hi = mfcr(PTIM_CCVR_HI);
+ lo = mfcr(PTIM_CCVR_LO);
+ t = mfcr(PTIM_CCVR_HI);
+ } while(t != hi);
+
+ return ((u64)hi << 32) | lo;
+}
+
+static irqreturn_t timer_interrupt(int irq, void *dev)
+{
+ struct timer_of *to = this_cpu_ptr(_to);
+
+ mtcr(PTIM_TSR, 0);
+
+ to->clkevt.event_handler(>clkevt);
+
+ return IRQ_HANDLED;
+}
+
+static int csky_timer_set_next_event(unsigned long delta, struct
clock_event_device *ce)
+{
+ mtcr(PTIM_LVR, delta);
+
+ return 0;
+}
+
+static int csky_timer_shutdown(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 0);
+
+ return 0;
+}
+
+static int csky_timer_oneshot(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 1);
+
+ return 0;
+}
+
+static int csky_timer_oneshot_stopped(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 0);
+
+ return 0;
+}
+
+DEFINE_PER_CPU(struct timer_of, csky_to) = {
+ .flags = TIMER_OF_CLOCK | TIMER_OF_IRQ,
+
+ .clkevt = {
+ .name = "C-SKY SMP Timer V1",
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERCPU | CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = csky_timer_shutdown,
+ .set_state_oneshot = csky_timer_oneshot,
+ .set_state_oneshot_stopped = csky_timer_oneshot_stopped,
+ .set_next_event = csky_timer_set_next_event,
+ },
+
+ .of_irq = {
+ .handler = timer_interrupt,
+ .flags = IRQF_TIMER,
+ .percpu = 1,
+ },
+};
+
+/*** clock event for percpu ***/
+static int csky_timer_starting_cpu(unsigned int cpu)
+{
+ struct timer_of *to = this_cpu_ptr(_to);
+
+ to->clkevt.cpumask = cpumask_of(smp_processor_id());
+
+ clockevents_config_and_register(>clkevt, csky_timer_rate, 0,
ULONG_MAX);
+
+ enable_percpu_irq(csky_timer_irq, 0);
+
+ return 0;
+}
+
+static int csky_timer_dying_cpu(unsigned int cpu)
+{
+ disable_percpu_irq(csky_timer_irq);
+
+ return 0;
+}
+
+/*** clock source ***/
+static u64 sched_clock_read(void)
+{
+ return get_ccvr();
+}
+
+static u64 clksrc_read(struct clocksource *c)
+{
+ return get_ccvr();
+}
+
+struct clocksource csky_clocksource = {
+ .name = "csky_timer_v1_clksrc",
+ .rating = 400,
+ .mask = CLOCKSOURCE_MASK(BITS_CSKY_TIMER),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = clksrc_read,
+};
+
+static void csky_clksrc_init(void)
+{
+ clocksource_register_hz(_clocksource, csky_timer_rate);
+
+ sched_clock_register(sched_clock_read, BITS_CSKY_TIMER,
csky_timer_rate);
+}
+
+static int __init csky_timer_v1_init(struct device_node *np)
+{
+ int ret;
+ struct timer_of *to = this_cpu_ptr(_to);
+
+ ret = timer_of_init(np, to);
+ if (ret)
+ return ret;
+
+ csky_timer_irq = to->of_irq.irq;
+ csky_timer_rate = timer_of_rate(to);
+
+ ret = cpuhp_setup_state(CPUHP_AP_DUMMY_TIMER_STARTING,
+ "clockevents/csky/time
[PATCH V2 02/19] csky: defconfig
Signed-off-by: Guo Ren --- arch/csky/configs/gx66xx_defconfig | 549 + arch/csky/configs/qemu_ck807_defconfig | 541 2 files changed, 1090 insertions(+) create mode 100644 arch/csky/configs/gx66xx_defconfig create mode 100644 arch/csky/configs/qemu_ck807_defconfig diff --git a/arch/csky/configs/gx66xx_defconfig b/arch/csky/configs/gx66xx_defconfig new file mode 100644 index 000..7f2a987 --- /dev/null +++ b/arch/csky/configs/gx66xx_defconfig @@ -0,0 +1,549 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="github.com/c-sky" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_RELAY=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_AIO is not set +CONFIG_USERFAULTFD=y +CONFIG_EMBEDDED=y +# CONFIG_PERF_EVENTS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +CONFIG_ACORN_PARTITION_ICS=y +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_AIX_PARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_FB_NATIONALCHIP=y +CONFIG_RAM_BASE=0x1000 +# CONFIG_SUSPEND is not set +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_IPV6 is not set +CONFIG_CFG80211=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_DEBUGFS=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VIRTIO_BLK=y +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_DUMMY_IRQ=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +CONFIG_USB_SWITCH_FSA9480=m +CONFIG_SRAM=y +CONFIG_C2PORT=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_ECHO=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_USB_RTL8150=y +CONFIG_USB_RTL8152=y +CONFIG_USB_USBNET=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +CONFIG_MT7601U=m +# CONFIG_WLAN_VENDOR_RALINK is not set +CONFIG_RTL8187=y +CONFIG_RTL8XXXU=y +CONFIG_RTL8XXXU_UNTESTED=y +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_
[PATCH V2 06/19] csky: Cache and TLB routines
Signed-off-by: Guo Ren
---
arch/csky/abiv1/cacheflush.c | 51 +
arch/csky/abiv1/inc/abi/cacheflush.h | 42 +++
arch/csky/abiv1/inc/abi/tlb.h | 11 ++
arch/csky/abiv2/cacheflush.c | 55 +
arch/csky/abiv2/inc/abi/cacheflush.h | 38 ++
arch/csky/abiv2/inc/abi/tlb.h | 12 ++
arch/csky/include/asm/barrier.h | 19 +++
arch/csky/include/asm/cache.h | 29 +
arch/csky/include/asm/cacheflush.h| 9 ++
arch/csky/include/asm/dma-mapping.h | 13 +++
arch/csky/include/asm/io.h| 23
arch/csky/include/asm/tlb.h | 19 +++
arch/csky/include/asm/tlbflush.h | 22
arch/csky/include/uapi/asm/cachectl.h | 13 +++
arch/csky/mm/cachev1.c| 132 +
arch/csky/mm/cachev2.c| 97
arch/csky/mm/syscache.c | 29 +
arch/csky/mm/tlb.c| 210 ++
18 files changed, 824 insertions(+)
create mode 100644 arch/csky/abiv1/cacheflush.c
create mode 100644 arch/csky/abiv1/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv1/inc/abi/tlb.h
create mode 100644 arch/csky/abiv2/cacheflush.c
create mode 100644 arch/csky/abiv2/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv2/inc/abi/tlb.h
create mode 100644 arch/csky/include/asm/barrier.h
create mode 100644 arch/csky/include/asm/cache.h
create mode 100644 arch/csky/include/asm/cacheflush.h
create mode 100644 arch/csky/include/asm/dma-mapping.h
create mode 100644 arch/csky/include/asm/io.h
create mode 100644 arch/csky/include/asm/tlb.h
create mode 100644 arch/csky/include/asm/tlbflush.h
create mode 100644 arch/csky/include/uapi/asm/cachectl.h
create mode 100644 arch/csky/mm/cachev1.c
create mode 100644 arch/csky/mm/cachev2.c
create mode 100644 arch/csky/mm/syscache.c
create mode 100644 arch/csky/mm/tlb.c
diff --git a/arch/csky/abiv1/cacheflush.c b/arch/csky/abiv1/cacheflush.c
new file mode 100644
index 000..cb176f4
--- /dev/null
+++ b/arch/csky/abiv1/cacheflush.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+ unsigned long addr;
+
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_arch_1, &(page)->flags);
+ return;
+ }
+
+ /*
+* We could delay the flush for the !page_mapping case too. But that
+* case is for exec env/arg pages and those are %99 certainly going to
+* get faulted into the tlb (and thus flushed) anyways.
+*/
+ addr = (unsigned long) page_address(page);
+ dcache_wbinv_range(addr, addr + PAGE_SIZE);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t
*pte)
+{
+ unsigned long addr;
+ struct page *page;
+ unsigned long pfn;
+
+ pfn = pte_pfn(*pte);
+ if (unlikely(!pfn_valid(pfn)))
+ return;
+
+ page = pfn_to_page(pfn);
+ addr = (unsigned long) page_address(page);
+
+ if (vma->vm_flags & VM_EXEC ||
+ pages_do_alias(addr, address & PAGE_MASK))
+ cache_wbinv_all();
+
+ clear_bit(PG_arch_1, &(page)->flags);
+}
+
diff --git a/arch/csky/abiv1/inc/abi/cacheflush.h
b/arch/csky/abiv1/inc/abi/cacheflush.h
new file mode 100644
index 000..3f99f25
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/cacheflush.h
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_CSKY_CACHEFLUSH_H
+#define __ABI_CSKY_CACHEFLUSH_H
+
+#include
+#include
+#include
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+#define flush_cache_mm(mm) cache_wbinv_all()
+#define flush_cache_page(vma,page,pfn) cache_wbinv_all()
+#define flush_cache_dup_mm(mm) cache_wbinv_all()
+
+#define flush_cache_range(mm,start,end)cache_wbinv_range(start, end)
+#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
+#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_page(vma, page) cache_wbinv_all()
+#define flush_icache_range(start, end) cache_wbinv_range(start, end)
+#define flush_icache_user_range(vma,pg,adr,len)cache_wbinv_range(adr,
adr + len)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+ icache_inv_all(); \
+}while(0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+}while(0)
+
+#define flush_dcache_mmap_lock(mapping)
[PATCH V2 12/19] csky: ELF and module probe
Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 149 arch/csky/kernel/module.c | 82 2 files changed, 231 insertions(+) create mode 100644 arch/csky/include/asm/elf.h create mode 100644 arch/csky/kernel/module.c diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h new file mode 100644 index 000..9a7967c --- /dev/null +++ b/arch/csky/include/asm/elf.h @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. +#ifndef __ASMCSKY_ELF_H +#define __ASMCSKY_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +#define ELF_ARCH 39 + +/* CSKY Relocations */ +#define R_CSKY_NONE 0 +#define R_CSKY_32 1 +#define R_CSKY_PCIMM8BY4 2 +#define R_CSKY_PCIMM11BY2 3 +#define R_CSKY_PCIMM4BY2 4 +#define R_CSKY_PC32 5 +#define R_CSKY_PCRELJSR_IMM11BY2 6 +#define R_CSKY_GNU_VTINHERIT 7 +#define R_CSKY_GNU_VTENTRY8 +#define R_CSKY_RELATIVE 9 +#define R_CSKY_COPY 10 +#define R_CSKY_GLOB_DAT 11 +#define R_CSKY_JUMP_SLOT 12 +#define R_CSKY_ADDR_HI16 24 +#define R_CSKY_ADDR_LO16 25 +#define R_CSKY_PCRELJSR_IMM26BY2 40 + +typedef unsigned long elf_greg_t; + +typedef struct user_fp elf_fpregset_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) + +/* + * These are used to set parameters in the core dumps. + */ +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 +#define ELF_CLASS ELFCLASS32 +#define ELF_PLAT_INIT(_r, load_addr) _r->a0 = 0 + +#ifdef __cskyBE__ +#define ELF_DATA ELFDATA2MSB +#else +#define ELF_DATA ELFDATA2LSB +#endif + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE0x0UL + +/* The member sort in array pr_reg[x] is pc, r1, r0, psr, r2, r3,r4, + r5, r6.. Because GDB difine */ +#if defined(__CSKYABIV2__) + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->a1; \ +pr_reg[2] = regs->a0; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a2; \ +pr_reg[5] = regs->a3; \ +pr_reg[6] = regs->regs[0]; \ +pr_reg[7] = regs->regs[1]; \ +pr_reg[8] = regs->regs[2]; \ +pr_reg[9] = regs->regs[3]; \ +pr_reg[10] = regs->regs[4]; \ +pr_reg[11] = regs->regs[5]; \ +pr_reg[12] = regs->regs[6]; \ +pr_reg[13] = regs->regs[7]; \ +pr_reg[14] = regs->regs[8]; \ +pr_reg[15] = regs->regs[9]; \ +pr_reg[16] = regs->usp;\ +pr_reg[17] = regs->lr; \ +pr_reg[18] = regs->exregs[0]; \ +pr_reg[19] = regs->exregs[1]; \ +pr_reg[20] = regs->exregs[2]; \ +pr_reg[21] = regs->exregs[3]; \ +pr_reg[22] = regs->exregs[4]; \ +pr_reg[23] = regs->exregs[5]; \ +pr_reg[24] = regs->exregs[6]; \ +pr_reg[25] = regs->exregs[7]; \ +pr_reg[26] = regs->exregs[8]; \ +pr_reg[27] = regs->exregs[9]; \ +pr_reg[28] = regs->exregs[10]; \ +pr_reg[29] = regs->exregs[11]; \ +pr_reg[30] = regs->exregs[12]; \ +pr_reg[31] = regs->exregs[13]; \ +pr_reg[32] = regs->exregs[14]; \ +pr_reg[33] = regs->tls; +#else + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->regs[9]; \ +pr_reg[2] = regs->usp; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a0; \ +pr_reg[5] = regs->a1; \ +pr_reg[6] = regs->a2; \ +pr_reg[7] = regs->a3; \ +pr_reg[8] = regs->regs[0]; \ +pr_reg[9] = regs->re
[PATCH V2 17/19] csky: Misc headers
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/reg_ops.h | 47 ++
arch/csky/abiv1/inc/abi/regdef.h | 15 ++
arch/csky/abiv2/inc/abi/reg_ops.h | 38 +
arch/csky/abiv2/inc/abi/regdef.h | 15 ++
arch/csky/include/asm/bitops.h | 277 +
arch/csky/include/asm/checksum.h | 77 +
arch/csky/include/asm/reg_ops.h| 16 ++
arch/csky/include/uapi/asm/byteorder.h | 14 ++
8 files changed, 499 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv1/inc/abi/regdef.h
create mode 100644 arch/csky/abiv2/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv2/inc/abi/regdef.h
create mode 100644 arch/csky/include/asm/bitops.h
create mode 100644 arch/csky/include/asm/checksum.h
create mode 100644 arch/csky/include/asm/reg_ops.h
create mode 100644 arch/csky/include/uapi/asm/byteorder.h
diff --git a/arch/csky/abiv1/inc/abi/reg_ops.h
b/arch/csky/abiv1/inc/abi/reg_ops.h
new file mode 100644
index 000..7c31ac3
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/reg_ops.h
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+#define cprcr(reg) \
+({ \
+ unsigned int tmp; \
+ asm volatile("cprcr %0, "reg"\n":"=b"(tmp));\
+ tmp;\
+})
+
+#define cpwcr(reg, val)\
+({ \
+ asm volatile("cpwcr %0, "reg"\n"::"b"(val));\
+})
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr30");
+}
+
+static inline unsigned int mfcr_msa0(void)
+{
+ return cprcr("cpcr30");
+}
+
+static inline void mtcr_msa0(unsigned int value)
+{
+ cpwcr("cpcr30", value);
+}
+
+static inline unsigned int mfcr_msa1(void)
+{
+ return cprcr("cpcr31");
+}
+
+static inline void mtcr_msa1(unsigned int value)
+{
+ cpwcr("cpcr31", value);
+}
+
+static inline unsigned int mfcr_ccr2(void){return 0;}
+
+#endif /* __ABI_REG_OPS_H */
+
diff --git a/arch/csky/abiv1/inc/abi/regdef.h b/arch/csky/abiv1/inc/abi/regdef.h
new file mode 100644
index 000..0c3596d
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/regdef.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r1
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[9]
+
+#define DEFAULT_PSR_VALUE 0x8f00
+
+#define SYSTRACE_SAVENUM 2
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/abiv2/inc/abi/reg_ops.h
b/arch/csky/abiv2/inc/abi/reg_ops.h
new file mode 100644
index 000..a8b2a52
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/reg_ops.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr31");
+}
+
+static inline unsigned int mfcr_ccr2(void)
+{
+ return mfcr("cr23");
+}
+
+static inline unsigned int mfcr_msa0(void)
+{
+ return mfcr("cr<30, 15>");
+}
+
+static inline void mtcr_msa0(unsigned int value)
+{
+ mtcr("cr<30, 15>", value);
+}
+
+static inline unsigned int mfcr_msa1(void)
+{
+ return mfcr("cr<31, 15>");
+}
+
+static inline void mtcr_msa1(unsigned int value)
+{
+ mtcr("cr<31, 15>", value);
+}
+
+#endif /* __ABI_REG_OPS_H */
+
diff --git a/arch/csky/abiv2/inc/abi/regdef.h b/arch/csky/abiv2/inc/abi/regdef.h
new file mode 100644
index 000..2c36d60
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/regdef.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r7
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[3]
+
+#define DEFAULT_PSR_VALUE 0x8f000200
+
+#define SYSTRACE_SAVENUM 5
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/include/asm/bitops.h b/arch/csky/include/asm/bitops.h
new file mode 100644
index 000..b2460c5
--- /dev/null
+++ b/arch/csky/include/asm/bitops.h
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_BITOPS_H
+#define __ASM_CSKY_BITOPS_H
+
+#include
+
+/*
+ * asm-generic/bitops/ffs.h
+ */
+static inline int ffs(int x)
+{
+
[PATCH V2 10/19] csky: IRQ handling
Signed-off-by: Guo Ren
---
arch/csky/include/asm/irq.h | 10
arch/csky/include/asm/irqflags.h | 49
arch/csky/kernel/irq.c | 31 +
3 files changed, 90 insertions(+)
create mode 100644 arch/csky/include/asm/irq.h
create mode 100644 arch/csky/include/asm/irqflags.h
create mode 100644 arch/csky/kernel/irq.c
diff --git a/arch/csky/include/asm/irq.h b/arch/csky/include/asm/irq.h
new file mode 100644
index 000..9390cb0
--- /dev/null
+++ b/arch/csky/include/asm/irq.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQ_H
+#define __ASM_CSKY_IRQ_H
+
+#include
+
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+
+#endif /* __ASM_CSKY_IRQ_H */
diff --git a/arch/csky/include/asm/irqflags.h b/arch/csky/include/asm/irqflags.h
new file mode 100644
index 000..5216ec0
--- /dev/null
+++ b/arch/csky/include/asm/irqflags.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQFLAGS_H
+#define __ASM_CSKY_IRQFLAGS_H
+#include
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+
+ flags = mfcr("psr");
+ asm volatile("psrclr ie\n");
+ return flags;
+}
+#define arch_local_irq_save arch_local_irq_save
+
+static inline void arch_local_irq_enable(void)
+{
+ asm volatile("psrset ee, ie\n");
+}
+#define arch_local_irq_enable arch_local_irq_enable
+
+static inline void arch_local_irq_disable(void)
+{
+ asm volatile("psrclr ie\n");
+}
+#define arch_local_irq_disable arch_local_irq_disable
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ return mfcr("psr");
+}
+#define arch_local_save_flags arch_local_save_flags
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ mtcr("psr", flags);
+}
+#define arch_local_irq_restore arch_local_irq_restore
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !(flags & (1<<6));
+}
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include
+
+#endif /* __ASM_CSKY_IRQFLAGS_H */
diff --git a/arch/csky/kernel/irq.c b/arch/csky/kernel/irq.c
new file mode 100644
index 000..ef2600d
--- /dev/null
+++ b/arch/csky/kernel/irq.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+
+static void (*handle_arch_irq)(struct pt_regs *regs) = NULL;
+
+void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
+{
+ if (handle_arch_irq)
+ return;
+
+ handle_arch_irq = handle_irq;
+}
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+#ifdef CONFIG_SMP
+ setup_smp_ipi();
+#endif
+}
+
+asmlinkage void __irq_entry csky_do_IRQ(struct pt_regs *regs)
+{
+ handle_arch_irq(regs);
+}
--
2.7.4
[PATCH V2 13/19] csky: Library functions
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c | 18 +++
arch/csky/abiv1/bswapsi.c | 15 ++
arch/csky/abiv1/memcpy.S | 344 +
arch/csky/abiv2/memcpy.c | 43 ++
arch/csky/include/asm/string.h | 19 +++
arch/csky/kernel/asm-offsets.c | 85 ++
arch/csky/kernel/cskyksyms.c | 31
arch/csky/kernel/platform.c| 18 +++
arch/csky/kernel/power.c | 31
arch/csky/lib/delay.c | 40 +
arch/csky/lib/memset.c | 38 +
11 files changed, 682 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv2/memcpy.c
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/asm-offsets.c
create mode 100644 arch/csky/kernel/cskyksyms.c
create mode 100644 arch/csky/kernel/platform.c
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
create mode 100644 arch/csky/lib/memset.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..7346252
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return (((u) & 0xff00ull) >> 56) |
+ (((u) & 0x00ffull) >> 40) |
+ (((u) & 0xff00ull) >> 24) |
+ (((u) & 0x00ffull) >> 8) |
+ (((u) & 0xff00ull) << 8) |
+ (((u) & 0x00ffull) << 24) |
+ (((u) & 0xff00ull) << 40) |
+ (((u) & 0x00ffull) << 56);
+}
+
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..21958ca
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return (((u) & 0xff00) >> 24) |
+ (((u) & 0x00ff) >> 8) |
+ (((u) & 0xff00) << 8) |
+ (((u) & 0x00ff) << 24);
+}
+
+EXPORT_SYMBOL(__bswapsi2);
+
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..f86ad75
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4 /* If len less than 4
bytes */
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned /* If dest is not 4
bytes aligned */
+ mov r6, r3
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_aligned_but_src_not_aligned /* If dest is aligned,
but src is not aligned */
+.L0:
+ cmplti r4, 16
+ jbt .L_aligned_and_len_less_16bytes /* If len less than 16
bytes */
+ subisp, 8
+ stw r8, (sp, 0)
+.L_aligned_and_len_larger_16bytes: /* src and dst are all
aligned, and len > 16 bytes */
+ ldw r1, (r3, 0)
+ ldw r5, (r3, 4)
+ ldw r8, (r3, 8)
+ stw r1, (r7, 0)
+ ldw r1, (r3, 12)
+ stw r5, (r7, 4)
+ stw r8, (r7, 8)
+ stw r1, (r7, 12)
+ subir4, 16
+ addir3, 16
+ addir7, 16
+ cmplti r4, 16
+ jbf .L_aligned_and_len_larger_16bytes
+ ldw r8, (sp, 0)
+ addisp, 8
+ cmpnei r4, 0/* If len == 0, return, else goto
.L_aligned_and_len_less_16bytes */
+ jbf .L_return
+
+.L_aligned_and_len_less_16bytes:
+ cmplti r4, 4
+ bt .L_copy_by_byte
+.L1:
+ ldw r1, (r3, 0)
+ stw r1, (r7, 0)
+ subir4, 4
+ addir3, 4
+ addir7, 4
+ cmplti r4, 4
+ jbf .L1
+ br .L_copy_by_byte
+
+.L_return:
+ rts
+
+.L_copy_by_byte: /* len less than 4 bytes */
+ cmpnei r4, 0
+ jbf .L_return
+.L4:
+ ldb r1, (r3, 0)
+ stb
Re: [PATCH V2 19/19] irqchip: add C-SKY irqchip drivers
k an empty newline here for separation
Ok
> > + static void __iomem *reg_base;
> > + irq_hw_number_t hwirq;
> > +
> > + reg_base = *this_cpu_ptr(_reg);
>
> Wheee!
>
> static void __iomem *reg_base = this_cpu_read(intcl_reg);
> irq_hw_number_t hwirq;
>
> Hmm?
Thx for the tips and I'll use this_cpu_read() without static.
void __iomem *reg_base = this_cpu_read(intcl_reg);
> > + writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + (4*(d->hwirq -
> > COMM_IRQ_BASE)));
>
> Spaces between '4' and '*' and '(d->)' please. And to avoid the overly long
> line use a local variable to calculate the value.
Ok.
> > + } else
> > + irq_set_chip_and_handler(irq, _irq_chip,
> > handle_fasteoi_irq);
>
> The else path wants curly braces as well.
Ok.
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (C) 2018 Hangzhou NationalChip Science & Technology Co.,Ltd.
>
> See above
Ok, stick an empty newline
> > + writel_relaxed(expand_byte_to_word(i) + 0x03020100,
>
> This magic number is the reverse of the above magic. Is that intentional.
>
> > + reg_base + INTC_SOURCE + i);
> > + }
>
> See above.
No magic number and use inline func.
> > +static int __init
> > +intc_init(struct device_node *node, struct device_node *parent)
> > +{
> > + u32 clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> > + int ret;
>
> Aside of that the whole thing might share the code with the other one, but
> it might not be worth it. At least this wants to be documented in the
> changelog why sharing the code is not useful...
Do you mean merge irq-csky-v1.c irq-csky-v2.c irq-nationalchip.c into
one file eg: irq-csky.c?
Guo Ren
Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
On Wed, Sep 05, 2018 at 07:45:12PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../bindings/interrupt-controller/csky,mpintc.txt | 40
> > ++
> > 1 file changed, 40 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > new file mode 100644
> > index 000..49d1658
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
> > @@ -0,0 +1,40 @@
> > +===
> > +C-SKY Multi-processors Interrupt Controller
> > +===
> > +
> > +C-SKY Multi-processors Interrupt Controller is designed for
> > ck807/ck810/ck860
> > +SMP soc, and it also could be used in non-SMP system.
>
> How is it accessed? No mmio registers?
Mmio reg base is got from cpu-coprocessor register and I'll detail
it here in next version patch.
csky_mpintc_init(struct device_node *node, struct device_node *parent)
{
...
INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../interrupt-controller/csky,apb-intc.txt | 45
> > ++
> > 1 file changed, 45 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > new file mode 100644
> > index 000..faa482c
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
> > @@ -0,0 +1,45 @@
> > +==
> > +C-SKY APB Interrupt Controller
> > +==
> > +
> > +C-SKY APB Interrupt Controller is a simple soc interrupt controller
> > +on the apb bus and we only use it as root irq controller.
> > +
> > + - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64
> > irq nums.
> > + - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
>
> Can't this be described in DT as 2 csky,apb-intc nodes?
In detail, dual-apb-intc is not the same as two apb-intc, so I still want to
name them
separately, so I will keep this and it is clearer.
> > +- compatible
> > +Usage: required
> > +Value type:
> > +Definition: must be "csky,apb-intc"
> > + "csky,dual-apb-intc"
> > + "csky,gx6605s-intc"
> > +- interrupt-cells
>
> #interrupt-cells
Yes, I forgot #.
- #interrupt-cells
> > +Usage: required
> > +Value type:
> > +Definition: must be <1>
>
> No edge or level configuration?
No, also no support in hardware.
> > +
> > + intc: interrupt-controller {
>
> Needs a unit-address.
Ok, change it to:
intc: interrupt-controller@0x0050 {
Guo Ren
Re: [PATCH V3 18/26] dt-bindings: csky CPU Bindings
On Wed, Sep 05, 2018 at 07:37:50PM -0500, Rob Herring wrote: > On Wed, Sep 5, 2018 at 7:08 AM Guo Ren wrote: > > > > Signed-off-by: Guo Ren > > --- > > Documentation/devicetree/bindings/csky/cpus.txt | 70 > > + > > 1 file changed, 70 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/csky/cpus.txt > > Please make sure DT bindings are sent to DT list. Oh, I forgot add devicet...@vger.kernel.org. Thx for mentioned. Guo Ren
Re: [PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
On Wed, Sep 05, 2018 at 07:47:29PM -0500, Rob Herring wrote:
> On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote:
> >
> > Signed-off-by: Guo Ren
> > ---
> > .../bindings/timer/csky,gx6605s-timer.txt | 46
> > ++
> > 1 file changed, 46 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> >
> > diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > new file mode 100644
> > index 000..1136d9e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
> > @@ -0,0 +1,46 @@
> > +=
> > +gx6605s SOC Timer
> > +=
> > +
> > +The timer is used in gx6605s soc as system timer and the driver
> > +contain clk event and clk source.
> > +
> > +==
> > +timer node bindings definition
> > +==
> > +
> > +Description: Describes gx6605s SOC timer
> > +
> > +PROPERTIES
> > +
> > +- compatible
> > +Usage: required
> > +Value type:
> > +Definition: must be "csky,gx6605s"
>
> -timer?
Yes, thx. must be "csky,gx6605s-timer"
>
> > + - reg
> > + Usage: required
> > + Value type:
> > + Definition: in soc from cpu view
> > + - clocks
> > + Usage: required
> > + Value type:
>
> phandle + clock specifier cells
Sorry, I don't got it. Do you mean:
Value type:
?
>
> > + Definition: must be input clk node
> > +- interrupt
> > +Usage: required
> > +Value type:
> > +Definition: must be timer irq num defined by soc
> > +- interrupt-parent:
>
> This is implied. Don't need to document it here.
Ok, remove interrupt-parent
>
> > +Usage: required
> > + Value type:
> > +Definition: must be interrupt controller node
> > +
> > +Examples:
> > +-
> > +
> > + timer:timer {
>
> Needs a unit-address.
Ok, change to "timer0: timer@0x0020a000"
>
> > + compatible = "csky,gx6605s-timer";
> > + reg = <0x0020a000 0x400>;
> > + clocks = <_apb_clk>;
> > + interrupts = <10>;
> > + interrupt-parent = <>;
> > + };
> > --
> > 2.7.4
> >
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > diff --git a/arch/csky/include/asm/io.h b/arch/csky/include/asm/io.h > > new file mode 100644 > > index 000..fcb2142 > > --- /dev/null > > +++ b/arch/csky/include/asm/io.h > > @@ -0,0 +1,23 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. > > +#ifndef __ASM_CSKY_IO_H > > +#define __ASM_CSKY_IO_H > > + > > +#include > > +#include > > +#include > > + > > +extern void __iomem *ioremap(phys_addr_t offset, size_t size); > > + > > +extern void iounmap(void *addr); > > + > > +extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr, > > + size_t size, unsigned long flags); > > + > > +#define ioremap_nocache(phy, sz) ioremap(phy, sz) > > +#define ioremap_wc ioremap_nocache > > +#define ioremap_wt ioremap_nocache > > + > > +#include > > It is very unusual for an architecture to not need special handling in > asm/io.h, > to do the proper barriers etc. > > Can you describe how C-Sky hardware implements MMIO? Our mmio is uncachable and strong-order address, so there is no need barriers for access these io addr. #define ioremap_wc ioremap_nocache #define ioremap_wt ioremap_nocache Current ioremap_wc and ioremap_wt implementation are too simple and we'll improve it in future. > In particular: > > - Is a read from uncached memory always serialized with DMA, and with > other CPUs doing MMIO access to a different address? CPU use ld.w to get data from uncached strong order memory. Other CPUs use the same mmio vaddr to access the uncachable strong order memory paddr. > - How does endianess work? Are there any buses that flip bytes around > when running big-endian, or do you always do that in software? Currently we only support little-endian and soc will follow it. Guo Ren
Re: [PATCH V3 09/26] csky: VDSO and rt_sigreturn
On Thu, Sep 06, 2018 at 04:02:42PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > +
> > + /*
> > +* __NR_rt_sigreturn must be 173
> > +* Because gcc/config/csky/linux-unwind.h use hard code to parse
> > rt_sigframe.
> > +*/
> > + err = setup_vdso_page(vdso->rt_signal_retcode);
> > + if (err) panic("Cannot set signal return code, err: %x.", err);
>
> __NR_rt_sigreturn is 139
Yes, we've changed to use asm-generic define, and I forgot to update the
comment.
Guo Ren
Re: [PATCH V3 02/26] csky: defconfig
On Thu, Sep 06, 2018 at 03:58:51PM +0200, Arnd Bergmann wrote: > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > > Signed-off-by: Guo Ren > > --- > > arch/csky/configs/defconfig | 76 > > + > > +CONFIG_USELIB=y > > CONFIG_USELIB seems misplaced here, very few architectures can even > call that, and it's not in the asm-generic/unistd.h file. Ok, remove it. > > +CONFIG_RELAY=y > > relay is selected by drivers that need it, you should not need to turn > it on here. Ok, remove it. > > +CONFIG_SYSCTL_SYSCALL=y > > Also not in the asm-generic syscall table. We should probably hide the > CONFIG_USELIB and CONFIG_SYSCTL_SYSCALL options so they > only appear on architectures that can use them (patches welcome). Ok, remove it. > > > +CONFIG_KALLSYMS_ALL=y > > While useful for debugging, this is also something I would not expect > in the defconfig file Ok, remove it. > > +CONFIG_USERFAULTFD=y > > Probably not needed either, unless you have a specific use > case. Ok, remove it. > > +CONFIG_EMBEDDED=y > > This (and CONFIG_EXPERT) is mostly there to expose options > that are otherwise hidden for good reasons. Is there any option > you tweak that depends on this? If not, then remove this as well. Ok, remove it. > > +CONFIG_PROFILING=y > > This is only for oprofile, which new architectures should generally > no longer implement. Better implement PERF only. Ok, remove it and we will only implement perf in future. > > +CONFIG_BLK_DEV_INTEGRITY=y > > This is also fairly unusual. Ok, remove it. > > +CONFIG_EXT2_FS=y > > +CONFIG_EXT2_FS_XATTR=y > > +CONFIG_EXT2_FS_POSIX_ACL=y > > +CONFIG_EXT2_FS_SECURITY=y > > +CONFIG_EXT3_FS=y > > +CONFIG_EXT3_FS_POSIX_ACL=y > > +CONFIG_EXT3_FS_SECURITY=y > > Better enable only EXT4 and drop EXT2/EXT3. Ok. > > +CONFIG_UNUSED_SYMBOLS=y > > You should only need this to work around bugs, so > I'd turn it off. Ok, remove it. Guo Ren
Re: [PATCH V3 05/26] csky: System Call
On Thu, Sep 06, 2018 at 04:10:49PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > +SYSCALL_DEFINE6(mmap2,
> > + unsigned long, addr,
> > + unsigned long, len,
> > + unsigned long, prot,
> > + unsigned long, flags,
> > + unsigned long, fd,
> > + off_t, offset)
> > +{
> > + if (unlikely(offset & (~PAGE_MASK >> 12)))
> > + return -EINVAL;
> > + return sys_mmap_pgoff(addr, len, prot, flags, fd,
> > + offset >> (PAGE_SHIFT - 12));
> > +}
>
> Please call ksys_mmap_pgoff() instead of sys_mmap_pgoff() here.
Ok.
> The prototype in include/asm-generic/syscalls.h uses 'unsigned long'
> for the last argument as well, not off_t.
Ok, unsigned long for last argument.
> > +struct mmap_arg_struct {
> > + unsigned long addr;
> > + unsigned long len;
> > + unsigned long prot;
> > + unsigned long flags;
> > + unsigned long fd;
> > + unsigned long offset;
> > +};
> > +
> > +SYSCALL_DEFINE1(mmap,
> > + struct mmap_arg_struct *, arg)
>
> Something is still wrong here, there should be no way to
> call sys_mmap(), since it's not in the syscall table.
You are right, remove it.
> > + return sys_fadvise64_64(fd, offset, len, advice);
> > +}
>
> And call ksys_fadvise64_64() here.
Ok.
Guo Ren
Re: [PATCH V3 00/26] C-SKY(csky) Linux Kernel Port
On Thu, Sep 06, 2018 at 07:08:18PM -0700, Guenter Roeck wrote: > Hi, > > On Wed, Sep 05, 2018 at 08:07:39PM +0800, Guo Ren wrote: > > This is the 3th version patchset to add the Linux kernel port for > > C-SKY(csky). > > Thanks to everyone who provided feedback on the previous version. > > > > This patchset adds architecture support to Linux for C-SKY's 32-bit embedded > > CPU cores and the patches are based on linux-4.18.4 > > > > There are two ABI versions with several CPU cores in this patchset: > > ABIv1: ck610 (16-bit instruction, 32-bit data path, VIPT Cache ...) > > ABIv2: ck807 ck810 ck860 (16/32-bit variable length instruction, PIPT > > Cache, > > SMP ...) > > > > My key question is about upstream toolchain support. > The buildroot clone tells me > > $ git describe csky/master > 2017.11-2111-ge9cc5a5 > > and > > $ git log --oneline origin/master..csky/master | wc >11807436 57104 > > with > $ git remote -v > csky https://gitlab.com/c-sky/buildroot.git > origingit://git.buildroot.net/buildroot > > So it looks like there are more thasn a thousand patches on top of > buildroot. Adding an architecture to buildroot should only take a > single patch, or maybe a few, but not more than a thousand. > This strongly suggests that a lot of changes are not upstream > but only available in the buildroot clone. csky https://gitlab.com/c-sky/buildroot.git is our CI environment based on buildroot and it's so miscellaneous. We won't upstream it directly and we'll prepare another patch set for buildroot.org update after kernel, glibc upstreamed. > When are we going to see all those changes in upstream gcc, binutils, > and qemu ? I don't really want to dig through more than a thousand > patches in a buildroot clone to find out details about the status > of upstream toolchain support. Ok, you want to use upstream gcc, binutils to build the kernel. I'll give the tips in next version patch. Best Regards Guo Ren
Re: [PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
On Thu, Sep 06, 2018 at 10:02:29AM +0800, Guo Ren wrote: > On Wed, Sep 05, 2018 at 07:47:29PM -0500, Rob Herring wrote: > > On Wed, Sep 5, 2018 at 7:09 AM Guo Ren wrote: > > > > > > Signed-off-by: Guo Ren > > > --- > > > .../bindings/timer/csky,gx6605s-timer.txt | 46 > > > ++ > > > 1 file changed, 46 insertions(+) > Ok, change to "timer0: timer@0x0020a000" Ok, change to "timer0: timer@20a000"
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Fri, Sep 07, 2018 at 10:14:38AM +0200, Arnd Bergmann wrote: > On Fri, Sep 7, 2018 at 5:04 AM Guo Ren wrote: > > > > On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > > > > Can you describe how C-Sky hardware implements MMIO? > > Our mmio is uncachable and strong-order address, so there is no need > > barriers for access these io addr. > > > > #define ioremap_wc ioremap_nocache > > #define ioremap_wt ioremap_nocache > > > > Current ioremap_wc and ioremap_wt implementation are too simple and > > we'll improve it in future. > > > > > In particular: > > > > > > - Is a read from uncached memory always serialized with DMA, and with > > > other CPUs doing MMIO access to a different address? > > CPU use ld.w to get data from uncached strong order memory. > > Other CPUs use the same mmio vaddr to access the uncachable strong order > > memory paddr. > > Ok, but what about the DMA? The most common requirement for > serialization here is with a DMA transfer, where you first write > into a buffer in memory, then write to an MMIO register to trigger > a DMA-load, and then the device reads the data from memory. > Without a barrier before the MMIO, the data may still be in a > store queue of the CPU, and the DMA gets stale data. > > Similarly, an MMIO read may be used to see if a DMA has completed > and the device register tells you that the DMA has left the device, > but without a barrier, the CPU may have prefetched the DMA > data while waiting for the MMIO-read to complete. The __io_ar() > barrier() in asm-generic/io.h prevents the compiler from reordering > the two reads, but if an weakly ordered read (in coherent DMA buffer) > can bypass a strongly ordered read (MMIO), then it's still still > broken. __io_ar() barrier()? not rmb() ?! I've defined the rmb in asm/barrier, So I got rmb() here not barrier(). Only __io_br() is barrier(). > > > - How does endianess work? Are there any buses that flip bytes around > > > when running big-endian, or do you always do that in software? > > Currently we only support little-endian and soc will follow it. > > Ok, that makes it easier. If you think that you won't even need big-endian > support in the long run, you could also remove your asm/byteorder.h > header. If you're not sure, it doesn't hurt to keep it of course. Em... I'm not sure, so let me keep it for a while. Best Regards Guo Ren
Re: [PATCH V3 17/26] csky: Misc headers
On Fri, Sep 07, 2018 at 10:01:03AM +0200, Arnd Bergmann wrote:
> On Fri, Sep 7, 2018 at 7:17 AM Guo Ren wrote:
> >
> > On Thu, Sep 06, 2018 at 04:16:30PM +0200, Arnd Bergmann wrote:
> > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
> > >
> > > > diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> > > > new file mode 100644
> > > > index 000..d36e4cd
> > > > --- /dev/null
> > > > +++ b/arch/csky/boot/dts/qemu.dts
> > > > @@ -0,0 +1,77 @@
> > > > +/dts-v1/;
> > > > +/ {
> > > > + compatible = "csky,qemu";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + interrupt-parent = <>;
> > >
> > > Ideally, qemu would supply a dtb file that matches the current
> > > configuration,
> > > as we do for instance on the ARM 'virt' machine. This allows you
> > > much more flexibility in running all kinds of options, as well as
> > > extending
> > > qemu later with new features.
> > So, I should remove qemu.dts in next version patch?
>
> It's up to you really. If you won't have a version of qemu that can do this
> by itself, it may make sense to keep it around for a while. You might
> want to include the version of your current qemu port is based on
> qemu-2.x but not upstream, you could include a qemu-2.x.dts file
> here, and have the future 3.x port provide its own.
Ok, thx for the tips.
Guo Ren
Re: [PATCH V3 13/26] csky: Library functions
On Thu, Sep 06, 2018 at 04:24:59PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > --- /dev/null
> > +++ b/arch/csky/abiv1/memset.c
> > @@ -0,0 +1,38 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
> > +#include
> > +
> > +void *memset(void *dest, int c, size_t l)
> > +{
> > + char *d = dest;
> > + int ch = c;
> > + int tmp;
> > +
> > + if ((long)d & 0x3)
> > + while (l--) *d++ = ch;
> > + else {
> > + ch &= 0xff;
> > + tmp = (ch | ch << 8 | ch << 16 | ch << 24);
> > +
> > + while (l >= 16) {
> > + *(((long *)d)) = tmp;
> > + *(((long *)d)+1) = tmp;
> > + *(((long *)d)+2) = tmp;
> > + *(((long *)d)+3) = tmp;
> > + l -= 16;
> > + d += 16;
> > + }
> > +
> > + while (l > 3) {
> > + *(((long *)d)) = tmp;
> > + d = d + 4;
> > + l -= 4;
> > + }
> > +
> > + while (l) {
> > + *d++ = ch;
> > + l--;
> > + }
> > + }
> > + return dest;
> > +}
>
> I see that we have a trivial memset() implementation in lib/string.c, but
> yours
> seems to be better optimized. Where did you get it from?
We write it for our ck610 to improve the performance, but I think a lot
of other arch done it in asm style.
> Is this a version
> that works particularly well on C-Sky, or is this a generic optimized memset
> that others could use as well?
We only test it on C-SKY, but I think it will also work better on other
arch CPU than current lib/string.c memset implement.
I see that in lib/string.c:
void *memset(void *s, int c, size_t count)
{
char *xs = s;
while (count--)
*xs++ = c;
return s;
}
The most problem is "char *xs;" and it will cause "st.b" in asm.
"st.b" is very slow.
Our key improvement is:
> > + *(((long *)d)) = tmp;
> > + *(((long *)d)+1) = tmp;
> > + *(((long *)d)+2) = tmp;
> > + *(((long *)d)+3) = tmp;
It will cause SOC AXI burst transfer.
> In the latter case, we could add it to
> lib/string.c and let architectures select it in place of the triivial version.
Good idea.
Guo Ren
Re: [PATCH V3 13/26] csky: Library functions
On Thu, Sep 06, 2018 at 05:50:02PM +0200, Geert Uytterhoeven wrote: > On Thu, Sep 6, 2018 at 4:25 PM Arnd Bergmann wrote: > > On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > > > --- /dev/null > > > +++ b/arch/csky/abiv1/memset.c > > > @@ -0,0 +1,38 @@ > > > + if ((long)d & 0x3) > > > + while (l--) *d++ = ch; > > while ((uintptr_t)d & 0x3) && l--) > *d++ =ch; > > and remove the else below? Ok > > > + *(((long *)d)+3) = tmp; > > s/long/u32/ Ok Thx Guo Ren
Re: [PATCH V3 17/26] csky: Misc headers
On Thu, Sep 06, 2018 at 04:16:30PM +0200, Arnd Bergmann wrote:
> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote:
>
> > diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
> > new file mode 100644
> > index 000..d36e4cd
> > --- /dev/null
> > +++ b/arch/csky/boot/dts/qemu.dts
> > @@ -0,0 +1,77 @@
> > +/dts-v1/;
> > +/ {
> > + compatible = "csky,qemu";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + interrupt-parent = <>;
>
> Ideally, qemu would supply a dtb file that matches the current configuration,
> as we do for instance on the ARM 'virt' machine. This allows you
> much more flexibility in running all kinds of options, as well as extending
> qemu later with new features.
So, I should remove qemu.dts in next version patch?
> > +
> > + timer0: timer@0xd000 {
> > + compatible = "snps,dw-apb-timer";
> > + reg = <0xd000 0x1000>;
> > + clocks = <_apb>;
> > + clock-names = "timer";
> > + interrupts = <1>;
> > + };
> > +
> > + timer1: timer@0xd014 {
>
> Drop the leading '0x' in the unit-address here (in all devices)
Ok
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Thu, Sep 06, 2018 at 03:05:38PM +0200, Arnd Bergmann wrote:
> On Thu, Sep 6, 2018 at 4:13 AM Guo Ren wrote:
> >
> > On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> > > On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> > > >
> > > > Signed-off-by: Guo Ren
> > > > +
> > > > + intc: interrupt-controller {
> > >
> > > Needs a unit-address.
> > Ok, change it to:
> > intc: interrupt-controller@0x00500000 {
>
> The unit address has no leading 0x or leading zeroes, so
> interrupt-controller@50
Ok
Guo Ren
Re: [PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
On Thu, Sep 06, 2018 at 03:03:16PM +0200, Arnd Bergmann wrote:
> > INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE);
>
> It that reliable? I remember a similar situation with some registers on ARM
> that are usually identified through a special CPU register, but in some
> cases the SoC integrator put the wrong address in there, so we need to
> look up the address in DT anyway.
Yes, it's reliable. This interrupt is combined with CPU and not on AXI
or APB. Soc just give a hole in the address space and tell the CPU where
the address is with 20 wire-signals.
Guo Ren
Re: [PATCH V3 10/26] csky: IRQ handling
On Thu, Sep 06, 2018 at 03:39:01PM +0200, Thomas Gleixner wrote:
> On Wed, 5 Sep 2018, Guo Ren wrote:
>
> > +static void (*handle_arch_irq)(struct pt_regs *regs) = NULL;
> > +
> > +void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
> > +{
> > + if (handle_arch_irq)
> > + return;
> > +
> > + handle_arch_irq = handle_irq;
> > +}
>
> Please don't introduce yet another variant of that. Please use
> CONFIG_GENERIC_IRQ_MULTI_HANDLER which provides that in the generic code.
Ok.
>
> Btw, some of your patches have tab vs. space inconsistencies, e.g.
>
> +siginfo_t info;
> + int fault;
> + unsigned long address = mmu_meh & PAGE_MASK
Thx, I'll re-check.
Best Regards
Guo Ren
Re: [PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
On Fri, Sep 07, 2018 at 10:13:13AM -0500, Rob Herring wrote:
> On Thu, Sep 6, 2018 at 8:05 AM Arnd Bergmann wrote:
> >
> > On Thu, Sep 6, 2018 at 4:13 AM Guo Ren wrote:
> > >
> > > On Wed, Sep 05, 2018 at 07:43:10PM -0500, Rob Herring wrote:
> > > > On Wed, Sep 5, 2018 at 7:10 AM Guo Ren wrote:
> > > > >
> > > > > Signed-off-by: Guo Ren
> > > > > +
> > > > > + intc: interrupt-controller {
> > > >
> > > > Needs a unit-address.
> > > Ok, change it to:
> > > intc: interrupt-controller@0x0050 {
> >
> > The unit address has no leading 0x or leading zeroes, so
> > interrupt-controller@500000
>
> Please build your dts files with W=12 and it will tell you this and
> other errors. And then update any examples based on that.
Got it, thx for the tip.
Guo Ren
Re: [PATCH V3 06/26] csky: Cache and TLB routines
On Fri, Sep 07, 2018 at 04:13:35PM +0200, Arnd Bergmann wrote: > On Fri, Sep 7, 2018 at 2:55 PM Guo Ren wrote: > > > > On Fri, Sep 07, 2018 at 10:14:38AM +0200, Arnd Bergmann wrote: > > > On Fri, Sep 7, 2018 at 5:04 AM Guo Ren wrote: > > > > On Thu, Sep 06, 2018 at 04:31:16PM +0200, Arnd Bergmann wrote: > > > Similarly, an MMIO read may be used to see if a DMA has completed > > > and the device register tells you that the DMA has left the device, > > > but without a barrier, the CPU may have prefetched the DMA > > > data while waiting for the MMIO-read to complete. The __io_ar() > > > barrier() in asm-generic/io.h prevents the compiler from reordering > > > the two reads, but if an weakly ordered read (in coherent DMA buffer) > > > can bypass a strongly ordered read (MMIO), then it's still still > > > broken. > > __io_ar() barrier()? not rmb() ?! I've defined the rmb in asm/barrier, So > > I got rmb() here not barrier(). > > > > Only __io_br() is barrier(). > > Ah right, I misremembered the defaults. It's probably ok then. Thx for the review and comments. These let me re-consider the mmio issues and help to improve the csky asm/io.h in future. > > > > > > - How does endianess work? Are there any buses that flip bytes around > > > > > when running big-endian, or do you always do that in software? > > > > Currently we only support little-endian and soc will follow it. > > > > > > Ok, that makes it easier. If you think that you won't even need big-endian > > > support in the long run, you could also remove your asm/byteorder.h > > > header. If you're not sure, it doesn't hurt to keep it of course. > > Em... I'm not sure, so let me keep it for a while. > > Ok. I think overall the trend is to be little-endian only for most > architectures: powerpc64 moved from big-endian only to little-endian > by default, ARM rarely uses big-endian (basically only for legacy > applications ported from BE MIPS or ppc), and all new architectures > we added in the last years are little-endian (OpenRISC being the > main exception). Good news, I really don't want to support big-endian and it makes CI double. Best Regards Guo Ren
[PATCH V3 18/26] dt-bindings: csky CPU Bindings
Signed-off-by: Guo Ren
---
Documentation/devicetree/bindings/csky/cpus.txt | 70 +
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/csky/cpus.txt
diff --git a/Documentation/devicetree/bindings/csky/cpus.txt
b/Documentation/devicetree/bindings/csky/cpus.txt
new file mode 100644
index 000..ee3901d
--- /dev/null
+++ b/Documentation/devicetree/bindings/csky/cpus.txt
@@ -0,0 +1,70 @@
+==
+C-SKY CPU Bindings
+==
+
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+
+Only SMP system need to care about the cpus node and single processor
+needn't define cpus node at all.
+
+=
+cpus and cpu node bindings definition
+=
+
+- cpus node
+
+Description: Container of cpu nodes
+
+The node name must be "cpus".
+
+A cpus node must define the following properties:
+
+- #address-cells
+Usage: required
+Value type:
+Definition: must be set to 1
+- #size-cells
+Usage: required
+Value type:
+Definition: must be set to 0
+
+- cpu node
+
+Description: Describes one of SMP cores
+
+PROPERTIES
+
+- device_type
+Usage: required
+Value type:
+Definition: must be "cpu"
+- reg
+Usage: required
+Value type:
+Definition: CPU index
+- status:
+Usage: required
+Value type:
+Definition: "ok" means enable the cpu-core
+"disabled" means disable the cpu-core
+
+Example:
+
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "ok";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "ok";
+ };
+ };
--
2.7.4
[PATCH V3 01/26] csky: Build infrastructure
Signed-off-by: Guo Ren --- arch/csky/Kconfig | 230 + arch/csky/Kconfig.debug| 14 ++ arch/csky/Makefile | 93 + arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 10 ++ arch/csky/boot/Makefile| 24 arch/csky/boot/dts/Makefile| 13 ++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 69 ++ arch/csky/include/uapi/asm/Kbuild | 33 + arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 ++ 13 files changed, 517 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..8659458 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,230 @@ +config CSKY + def_bool y + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_USE_BUILTIN_BSWAP + select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2 + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select DMA_NONCOHERENT_OPS + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + select GENERIC_LIB_MULDI3 + select GENERIC_LIB_CMPDI2 + select GENERIC_LIB_UCMPDI2 + select GENERIC_ALLOCATOR + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_C_RECORDMCOUNT + select HAVE_DMA_API_DEBUG + select HAVE_DMA_CONTIGUOUS + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_FPUV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP, CPU needs "ldex" instrcutions to atomic operations. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause an illegal + instruction exception. + In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config GENERIC_CSUM + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config MMU + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config TIME_LOW_RES + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +config CPU_TLB_SIZE + int + default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if (CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if (CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if (CPU_CK610) + default "5" if (CPU_CK807 || CPU_CK810) + default "6" if (CPU_CK860) + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +choice + prompt "CPU MODEL" + default CPU_CK610 + +config CPU_CK610 + bool "CSKY CPU ck610" + select CPU_
[PATCH V3 08/26] csky: Process management and Signal
Signed-off-by: Guo Ren
---
arch/csky/abiv2/fpu.c | 281 +
arch/csky/abiv2/inc/abi/fpu.h | 66 ++
arch/csky/include/asm/mmu_context.h | 148 ++
arch/csky/include/asm/processor.h | 120 +++
arch/csky/include/asm/switch_to.h | 35
arch/csky/include/asm/thread_info.h | 74 +++
arch/csky/include/uapi/asm/sigcontext.h | 13 ++
arch/csky/kernel/process.c | 134
arch/csky/kernel/signal.c | 350
arch/csky/kernel/time.c | 11 +
10 files changed, 1232 insertions(+)
create mode 100644 arch/csky/abiv2/fpu.c
create mode 100644 arch/csky/abiv2/inc/abi/fpu.h
create mode 100644 arch/csky/include/asm/mmu_context.h
create mode 100644 arch/csky/include/asm/processor.h
create mode 100644 arch/csky/include/asm/switch_to.h
create mode 100644 arch/csky/include/asm/thread_info.h
create mode 100644 arch/csky/include/uapi/asm/sigcontext.h
create mode 100644 arch/csky/kernel/process.c
create mode 100644 arch/csky/kernel/signal.c
create mode 100644 arch/csky/kernel/time.c
diff --git a/arch/csky/abiv2/fpu.c b/arch/csky/abiv2/fpu.c
new file mode 100644
index 000..8de6b2b
--- /dev/null
+++ b/arch/csky/abiv2/fpu.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#define MTCR_MASK 0xFC00FFE0
+#define MFCR_MASK 0xFC00FFE0
+#define MTCR_DIST 0xC0006420
+#define MFCR_DIST 0xC0006020
+
+void __init init_fpu(void)
+{
+ mtcr("cr<1, 2>", 0);
+}
+
+/*
+ * fpu_libc_helper() is to help libc to excute:
+ * - mfcr %a, cr<1, 2>
+ * - mfcr %a, cr<2, 2>
+ * - mtcr %a, cr<1, 2>
+ * - mtcr %a, cr<2, 2>
+ */
+int fpu_libc_helper(struct pt_regs * regs)
+{
+ int fault;
+ unsigned long instrptr, regx = 0;
+ unsigned long index = 0, tmp = 0;
+ unsigned long tinstr = 0;
+ u16 instr_hi, instr_low;
+
+ instrptr = instruction_pointer(regs);
+ if (instrptr & 1) return 0;
+
+ fault = __get_user(instr_low, (u16 *)instrptr);
+ if (fault) return 0;
+
+ fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
+ if (fault) return 0;
+
+ tinstr = instr_hi | ((unsigned long)instr_low << 16);
+
+ if (((tinstr >> 21) & 0x1F) != 2) return 0;
+
+ if ((tinstr & MTCR_MASK) == MTCR_DIST)
+ {
+ index = (tinstr >> 16) & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = tinstr & 0x1F;
+ if (tmp > 2) return 0;
+
+ regx = *(>a0 + index);
+
+ if(tmp == 1)
+ mtcr("cr<1, 2>", regx);
+ else if (tmp == 2)
+ mtcr("cr<2, 2>", regx);
+ else
+ return 0;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ if ((tinstr & MFCR_MASK) == MFCR_DIST) {
+ index = tinstr & 0x1F;
+ if(index > 13) return 0;
+
+ tmp = ((tinstr >> 16) & 0x1F);
+ if (tmp > 2) return 0;
+
+ if (tmp == 1)
+ regx = mfcr("cr<1, 2>");
+ else if (tmp == 2)
+ regx = mfcr("cr<2, 2>");
+ else
+ return 0;
+
+ *(>a0 + index) = regx;
+
+ regs->pc +=4;
+ return 1;
+ }
+
+ return 0;
+}
+
+void fpu_fpe(struct pt_regs * regs)
+{
+ int sig;
+ unsigned int fesr;
+ siginfo_t info;
+
+ fesr = mfcr("cr<2, 2>");
+
+ if(fesr & FPE_ILLE){
+ info.si_code = ILL_ILLOPC;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_IDC){
+ info.si_code = ILL_ILLOPN;
+ sig = SIGILL;
+ }
+ else if(fesr & FPE_FEC){
+ sig = SIGFPE;
+ if(fesr & FPE_IOC){
+ info.si_code = FPE_FLTINV;
+ }
+ else if(fesr & FPE_DZC){
+ info.si_code = FPE_FLTDIV;
+ }
+ else if(fesr & FPE_UFC){
+ info.si_code = FPE_FLTUND;
+ }
+ else if(fesr & FPE_OFC){
+ info.si_code = FPE_FLTOVF;
+ }
+ else if(fesr & FPE_IXC){
+ info.si_code = FPE_FLTRES;
+ }
+ else {
+ info.si_code = NSIGFPE;
+ }
+ }
+ else {
+ info.si_code = NSIGFPE;
+ sig = SIGFPE;
+ }
+ info.si_signo = SI
[PATCH V3 03/26] csky: Kernel booting
Signed-off-by: Guo Ren
---
arch/csky/kernel/head.S| 78 +
arch/csky/kernel/setup.c | 150 +
arch/csky/kernel/vmlinux.lds.S | 64 ++
3 files changed, 292 insertions(+)
create mode 100644 arch/csky/kernel/head.S
create mode 100644 arch/csky/kernel/setup.c
create mode 100644 arch/csky/kernel/vmlinux.lds.S
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S
new file mode 100644
index 000..80bb9c6
--- /dev/null
+++ b/arch/csky/kernel/head.S
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+
+__HEAD
+ENTRY(_start)
+ /* set super user mode */
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ SETUP_MMU a3
+
+ /* set stack point */
+ lrw a3, init_thread_union + THREAD_SIZE
+ mov sp, a3
+
+ jmpicsky_start
+END(_start)
+
+#ifdef CONFIG_SMP
+.align 10
+ENTRY(_start_smp_secondary)
+ /* Invalid I/Dcache BTB BHT */
+ movia3, 7
+ lslia3, 16
+ addia3, (1<<4) | 3
+ mtcra3, cr17
+
+ tlbi.alls
+
+ /* setup PAGEMASK */
+ movia3, 0
+ mtcra3, cr<6, 15>
+
+ /* setup MEL0/MEL1 */
+ grs a0, _start_smp_pc
+_start_smp_pc:
+ bmaski a1, 13
+ andna0, a1
+ movia1, 0x0006
+ movia2, 0x1006
+ or a1, a0
+ or a2, a0
+ mtcra1, cr<2, 15>
+ mtcra2, cr<3, 15>
+
+ /* setup MEH */
+ mtcra0, cr<4, 15>
+
+ /* write TLB */
+ bgeni a3, 28
+ mtcra3, cr<8, 15>
+
+ SETUP_MMU a3
+
+ /* enable MMU */
+ movia3, 1
+ mtcra3, cr18
+
+ jmpi_goto_mmu_on
+_goto_mmu_on:
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, secondary_stack
+ ld.wa3, (a3, 0)
+ mov sp, a3
+
+ jmpicsky_start_secondary
+END(_start_smp_secondary)
+#endif
diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c
new file mode 100644
index 000..44606fa
--- /dev/null
+++ b/arch/csky/kernel/setup.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+phys_addr_t __init_memblock memblock_end_of_REG0(void)
+{
+ return (memblock.memory.regions[0].base +
memblock.memory.regions[0].size);
+}
+
+phys_addr_t __init_memblock memblock_start_of_REG1(void)
+{
+ return memblock.memory.regions[1].base;
+}
+
+size_t __init_memblock memblock_size_of_REG1(void)
+{
+ return memblock.memory.regions[1].size;
+}
+
+static void __init csky_memblock_init(void)
+{
+ unsigned long zone_size[MAX_NR_ZONES];
+ unsigned long zhole_size[MAX_NR_ZONES];
+ signed long size;
+
+ memblock_reserve(__pa(_stext), _end - _stext);
+#ifdef CONFIG_BLK_DEV_INITRD
+ memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+
+ memset(zone_size, 0, sizeof(zone_size));
+ memset(zhole_size, 0, sizeof(zhole_size));
+
+ min_low_pfn = PFN_UP(memblock_start_of_DRAM());
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+
+ max_low_pfn = PFN_UP(memblock_end_of_REG0());
+ if (max_low_pfn == 0)
+ max_low_pfn = max_pfn;
+
+ size = max_pfn - min_low_pfn;
+
+ if (memblock.memory.cnt > 1) {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
min_low_pfn;
+ zhole_size[ZONE_NORMAL] = PFN_DOWN(memblock_start_of_REG1()) -
max_low_pfn;
+ } else {
+ if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
+ zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
+ else {
+ zone_size[ZONE_NORMAL] = PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
+ }
+ }
+
+#ifdef CONFIG_HIGHMEM
+ size = 0;
+ if(memblock.memory.cnt > 1) {
+ size = PFN_DOWN(memblock_size_of_REG1());
+ highstart_pfn = PFN_DOWN(memblock_start_of_REG1());
+ } else {
+ size = max_pfn - min_low_pfn - PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ highstart_pfn = min_low_pfn + PFN_DOWN(LOWMEM_LIMIT -
PHYS_OFFSET_OFFSET);
+ }
+
+ if (size > 0)
+ zone_size[ZONE_HIGHMEM] = size;
+
+ highend_pfn = max_pfn;
+#endif
+
[PATCH V3 02/26] csky: defconfig
Signed-off-by: Guo Ren --- arch/csky/configs/defconfig | 76 + 1 file changed, 76 insertions(+) create mode 100644 arch/csky/configs/defconfig diff --git a/arch/csky/configs/defconfig b/arch/csky/configs/defconfig new file mode 100644 index 000..c6a5a40 --- /dev/null +++ b/arch/csky/configs/defconfig @@ -0,0 +1,76 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="csky" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_RELAY=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_USERFAULTFD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_CPU_CK807=y +CONFIG_CPU_HAS_FPU=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_CSKY_MPTIMER=y +CONFIG_GX6605S_TIMER=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_GENERIC_PHY=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y -- 2.7.4
[PATCH V3 24/26] clocksource: add C-SKY SMP timer
This timer is used by SMP system and use mfcr/mtcr instruction
to access the regs.
Changelog:
- Support csky mp timer alpha version.
- Just use low-counter with 32bit width as clocksource.
- Coding convention with upstream feed-back.
Signed-off-by: Guo Ren
---
drivers/clocksource/csky_mptimer.c | 178 +
1 file changed, 178 insertions(+)
create mode 100644 drivers/clocksource/csky_mptimer.c
diff --git a/drivers/clocksource/csky_mptimer.c
b/drivers/clocksource/csky_mptimer.c
new file mode 100644
index 000..da2b239
--- /dev/null
+++ b/drivers/clocksource/csky_mptimer.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+
+#include "timer-of.h"
+
+#define PTIM_CCVR "cr<3, 14>"
+#define PTIM_CTLR "cr<0, 14>"
+#define PTIM_LVR "cr<6, 14>"
+#define PTIM_TSR "cr<1, 14>"
+
+static int csky_mptimer_set_next_event(unsigned long delta, struct
clock_event_device *ce)
+{
+ mtcr(PTIM_LVR, delta);
+
+ return 0;
+}
+
+static int csky_mptimer_shutdown(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 0);
+
+ return 0;
+}
+
+static int csky_mptimer_oneshot(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 1);
+
+ return 0;
+}
+
+static int csky_mptimer_oneshot_stopped(struct clock_event_device *ce)
+{
+ mtcr(PTIM_CTLR, 0);
+
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct timer_of, csky_to) = {
+ .flags = TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERCPU |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = csky_mptimer_shutdown,
+ .set_state_oneshot = csky_mptimer_oneshot,
+ .set_state_oneshot_stopped = csky_mptimer_oneshot_stopped,
+ .set_next_event = csky_mptimer_set_next_event,
+ },
+ .of_irq = {
+ .flags = IRQF_TIMER,
+ .percpu = 1,
+ },
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev)
+{
+ struct timer_of *to = this_cpu_ptr(_to);
+
+ mtcr(PTIM_TSR, 0);
+
+ to->clkevt.event_handler(>clkevt);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * clock event for percpu
+ */
+static int csky_mptimer_starting_cpu(unsigned int cpu)
+{
+ struct timer_of *to = per_cpu_ptr(_to, cpu);
+
+ to->clkevt.cpumask = cpumask_of(cpu);
+
+ clockevents_config_and_register(>clkevt, timer_of_rate(to), 2,
ULONG_MAX);
+
+ enable_percpu_irq(timer_of_irq(to), 0);
+
+ return 0;
+}
+
+static int csky_mptimer_dying_cpu(unsigned int cpu)
+{
+ struct timer_of *to = per_cpu_ptr(_to, cpu);
+
+ disable_percpu_irq(timer_of_irq(to));
+
+ return 0;
+}
+
+/*
+ * clock source
+ */
+static u64 sched_clock_read(void)
+{
+ return (u64) mfcr(PTIM_CCVR);
+}
+
+static u64 clksrc_read(struct clocksource *c)
+{
+ return (u64) mfcr(PTIM_CCVR);
+}
+
+struct clocksource csky_clocksource = {
+ .name = "csky",
+ .rating = 400,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = clksrc_read,
+};
+
+#define CPUHP_AP_CSKY_TIMER_STARTING CPUHP_AP_DUMMY_TIMER_STARTING
+
+static int __init csky_mptimer_init(struct device_node *np)
+{
+ int ret, cpu;
+ struct timer_of *to;
+ int rate = 0;
+ int irq = 0;
+
+ /*
+* Csky_mptimer is designed for C-SKY SMP multi-processors and
+* every core has it's own private irq and regs for clkevt and
+* clksrc.
+*
+* The regs is accessed by cpu instruction: mfcr/mtcr instead of
+* mmio map style. So we needn't mmio-address in dts, but we still
+* need to give clk and irq number.
+*
+* We use private irq for the mptimer and irq number is the same
+* for every core. So we use request_percpu_irq() in timer_of_init.
+*/
+
+ for_each_possible_cpu(cpu) {
+ to = per_cpu_ptr(_to, cpu);
+
+ if (cpu == 0) {
+ to->flags |= TIMER_OF_IRQ;
+ to->of_irq.handler = timer_interrupt;
+
+ ret = timer_of_init(np, to);
+ if (ret)
+ return ret;
+
+ rate= timer_of_rate(to);
+ irq = to->of_irq.irq;
+ } else {
+ ret = timer_of_init(np, to);
+ if (ret)
+ re
[PATCH V3 16/26] csky: SMP support
Signed-off-by: Guo Ren
---
arch/csky/include/asm/smp.h | 26 +
arch/csky/kernel/smp.c | 234
2 files changed, 260 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..9a53abf
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long));
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..522c73f
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,234 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IPI_IRQ15
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const unsigned long *mask, unsigned long irq) =
NULL;
+
+void __init set_send_ipi(void (*func)(const unsigned long *, unsigned long))
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(cpumask_bits(to_whom), IPI_IRQ);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+static int ipi_dummy_dev;
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(IPI_IRQ, 0);
+}
+
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ irq_create_mapping(NULL, IPI_IRQ);
+
+ rc = request_percpu_irq(IPI_IRQ, handle_ipi, "IPI Interrupt",
_dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+ if (cpu >= NR_CPUS)
+ continue;
+
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
+ }
+}
+
+extern void _start_smp_secondary(void);
+
+volatile unsigned int secondary_hint;
+volatile unsigned int secondary_ccr;
+volatile unsigned int secondary_stack;
+
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
+{
+ unsigned int tmp;
+
+ secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE;
+
+ secondary_hint = mfcr("cr31");
+
+ secondary_ccr = mfcr("cr18");
+
+ /* Flush dcache */
+ mtcr("cr17", 0x22);
+
+ /* Enable cpu in SMP reset ctrl reg */
+ tmp = mfcr(&q
[PATCH V3 19/26] dt-bindings: timer: gx6605s SOC timer
Signed-off-by: Guo Ren
---
.../bindings/timer/csky,gx6605s-timer.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
new file mode 100644
index 000..1136d9e
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
@@ -0,0 +1,46 @@
+=
+gx6605s SOC Timer
+=
+
+The timer is used in gx6605s soc as system timer and the driver
+contain clk event and clk source.
+
+==
+timer node bindings definition
+==
+
+Description: Describes gx6605s SOC timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,gx6605s"
+ - reg
+ Usage: required
+ Value type:
+ Definition: in soc from cpu view
+ - clocks
+ Usage: required
+ Value type:
+ Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+- interrupt-parent:
+Usage: required
+ Value type:
+Definition: must be interrupt controller node
+
+Examples:
+-
+
+ timer:timer {
+ compatible = "csky,gx6605s-timer";
+ reg = <0x0020a000 0x400>;
+ clocks = <_apb_clk>;
+ interrupts = <10>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V3 26/26] irqchip: add C-SKY irqchip drivers
This patch add C-SKY two interrupt conrollers.
- irq-csky-apb-intc is a simple SOC interrupt controller which is
used in a lot of C-SKY SOC products.
- irq-csky-mpintc is C-SKY smp system interrupt controller and it
could support 16 soft irqs, 16 private irqs, and 992 irqs.
Changelog:
- change name with upstream feed-back.
- remove CSKY_VECIRQ_LEGENCY.
- change irq map, reserve soft_irq_irq space.
- add License and Copyright
- change to generic irq chip framework.
- support set_affinity for irq balance in SMP
- add INTC_IFR to clear irq-pending
- use irq_domain_add_linear instead of leagcy.
- add set_handle_irq(), ref from openrisc & arm.
Signed-off-by: Guo Ren
---
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-csky-apb-intc.c | 243
drivers/irqchip/irq-csky-mpintc.c | 191
3 files changed, 435 insertions(+)
create mode 100644 drivers/irqchip/irq-csky-apb-intc.c
create mode 100644 drivers/irqchip/irq-csky-mpintc.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 15f268f..4838546 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -87,3 +87,4 @@ obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
obj-$(CONFIG_NDS32)+= irq-ativic32.o
obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
+obj-$(CONFIG_CSKY) += irq-csky-mpintc.o irq-csky-apb-intc.o
diff --git a/drivers/irqchip/irq-csky-apb-intc.c
b/drivers/irqchip/irq-csky-apb-intc.c
new file mode 100644
index 000..2c869ab
--- /dev/null
+++ b/drivers/irqchip/irq-csky-apb-intc.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define INTC_IRQS 64
+
+#define CK_INTC_ICR0x00
+#define CK_INTC_PEN31_00 0x14
+#define CK_INTC_PEN63_32 0x2c
+#define CK_INTC_NEN31_00 0x10
+#define CK_INTC_NEN63_32 0x28
+#define CK_INTC_IFR31_00 0x08
+#define CK_INTC_IFR63_32 0x20
+#define CK_INTC_SOURCE 0x40
+#define CK_INTC_DUAL_BASE 0x100
+
+#define GX_INTC_PEN31_00 0x00
+#define GX_INTC_PEN63_32 0x04
+#define GX_INTC_NEN31_00 0x40
+#define GX_INTC_NEN63_32 0x44
+#define GX_INTC_NMASK31_00 0x50
+#define GX_INTC_NMASK63_32 0x54
+#define GX_INTC_SOURCE 0x60
+
+static void __iomem *reg_base;
+static struct irq_domain *root_domain;
+
+static int nr_irq = INTC_IRQS;
+
+static void __init ck_set_gc(void __iomem *reg_base, u32 mask_reg, u32
irq_base)
+{
+ struct irq_chip_generic *gc;
+
+ gc = irq_get_domain_generic_chip(root_domain, irq_base);
+ gc->reg_base = reg_base;
+ gc->chip_types[0].regs.mask = mask_reg;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
+}
+
+static inline u32 build_channel_val(u32 idx, u32 magic)
+{
+ u32 res;
+
+ /*
+* Set the same index for each channel
+*/
+ res = idx | (idx << 8) | (idx << 16) | (idx << 24);
+
+ /*
+* Set the channel magic number in descending order.
+* The magic is 0x00010203 for ck-intc
+* The magic is 0x03020100 for gx6605s-intc
+*/
+ return res | magic;
+}
+
+static inline void setup_irq_channel(u32 magic, void __iomem *reg_addr)
+{
+ u32 i;
+
+ /* Setup 64 channel slots */
+ for (i = 0; i < INTC_IRQS; i += 4) {
+ writel_relaxed(build_channel_val(i, magic), reg_addr + i);
+ }
+}
+
+static int __init
+ck_intc_init_comm(struct device_node *node, struct device_node *parent)
+{
+ int ret;
+
+ if (parent) {
+ pr_err("C-SKY Intc not a root irq controller\n");
+ return -EINVAL;
+ }
+
+ reg_base = of_iomap(node, 0);
+ if (!reg_base) {
+ pr_err("C-SKY Intc unable to map: %p.\n", node);
+ return -EINVAL;
+ }
+
+ root_domain = irq_domain_add_linear(node, nr_irq,
_generic_chip_ops, NULL);
+ if (!root_domain) {
+ pr_err("C-SKY Intc irq_domain_add failed.\n");
+ return -ENOMEM;
+ }
+
+ ret = irq_alloc_domain_generic_chips(root_domain, 32, 1,
+"csky_intc", handle_level_irq,
+IRQ_NOREQUEST | IRQ_NOPROBE |
IRQ_NOAUTOEN,
+0, 0);
+ if (ret) {
+ pr_err("C-SKY Intc irq_alloc_gc failed.\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static inline int handle_irq_perbit(struc
[PATCH V3 25/26] clocksource: add C-SKY timers' build infrastructure
Signed-off-by: Guo Ren --- drivers/clocksource/Kconfig | 15 +++ drivers/clocksource/Makefile | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index dec0dd8..6ff0a25 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -609,4 +609,19 @@ config ATCPIT100_TIMER help This option enables support for the Andestech ATCPIT100 timers. +config CSKY_MPTIMER + bool "C-SKY mptimer driver" + depends on CSKY + select TIMER_OF + help + This option enables support for C-SKY mptimer. + +config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s timer. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 00caf37..764a45a 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -78,3 +78,5 @@ obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC)+= clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o +obj-$(CONFIG_CSKY_MPTIMER) += csky_mptimer.o +obj-$(CONFIG_GX6605S_TIMER)+= timer-gx6605s.o -- 2.7.4
[PATCH V3 09/26] csky: VDSO and rt_sigreturn
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/vdso.h | 17
arch/csky/abiv2/inc/abi/vdso.h | 24
arch/csky/include/asm/vdso.h | 12 ++
arch/csky/kernel/vdso.c| 88 ++
4 files changed, 141 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/vdso.h
create mode 100644 arch/csky/abiv2/inc/abi/vdso.h
create mode 100644 arch/csky/include/asm/vdso.h
create mode 100644 arch/csky/kernel/vdso.c
diff --git a/arch/csky/abiv1/inc/abi/vdso.h b/arch/csky/abiv1/inc/abi/vdso.h
new file mode 100644
index 000..a99f0e4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/vdso.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r1, 127 */
+ err |= __put_user(0x67f1, ptr + 0);
+ /* addi r1, (139 - 127) */
+ err |= __put_user(0x20b1, ptr + 1);
+ /* trap 0 */
+ err |= __put_user(0x0008, ptr + 2);
+
+ return err;
+}
diff --git a/arch/csky/abiv2/inc/abi/vdso.h b/arch/csky/abiv2/inc/abi/vdso.h
new file mode 100644
index 000..2b5f43b
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/vdso.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_VDSO_H
+#define __ABI_CSKY_VDSO_H
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r7, 173 */
+ err |= __put_user(0xea07, ptr);
+ err |= __put_user(0x008b, ptr+1);
+
+ /* trap 0 */
+ err |= __put_user(0xc000, ptr+2);
+ err |= __put_user(0x2020, ptr+3);
+
+ return err;
+}
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/include/asm/vdso.h b/arch/csky/include/asm/vdso.h
new file mode 100644
index 000..b275440
--- /dev/null
+++ b/arch/csky/include/asm/vdso.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_VDSO_H
+#define __ASM_CSKY_VDSO_H
+
+#include
+
+struct csky_vdso {
+ unsigned short rt_signal_retcode[4];
+};
+
+#endif /* __ASM_CSKY_VDSO_H */
diff --git a/arch/csky/kernel/vdso.c b/arch/csky/kernel/vdso.c
new file mode 100644
index 000..9090f12
--- /dev/null
+++ b/arch/csky/kernel/vdso.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+static struct page *vdso_page;
+
+static int __init init_vdso(void)
+{
+ struct csky_vdso *vdso;
+ int err = 0;
+
+ vdso_page = alloc_page(GFP_KERNEL);
+ if (!vdso_page)
+ panic("Cannot allocate vdso");
+
+ vdso = vmap(_page, 1, 0, PAGE_KERNEL);
+ if (!vdso)
+ panic("Cannot map vdso");
+
+ clear_page(vdso);
+
+ /*
+* __NR_rt_sigreturn must be 173
+* Because gcc/config/csky/linux-unwind.h use hard code to parse
rt_sigframe.
+*/
+ err = setup_vdso_page(vdso->rt_signal_retcode);
+ if (err) panic("Cannot set signal return code, err: %x.", err);
+
+ dcache_wb_range((unsigned long)vdso, (unsigned long)vdso + 16);
+
+ vunmap(vdso);
+
+ return 0;
+}
+subsys_initcall(init_vdso);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ int ret;
+ unsigned long addr;
+ struct mm_struct *mm = current->mm;
+
+ down_write(>mmap_sem);
+
+ addr = get_unmapped_area(NULL, STACK_TOP, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(
+ mm,
+ addr,
+ PAGE_SIZE,
+ VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+ _page);
+ if (ret)
+ goto up_fail;
+
+ mm->context.vdso = (void *)addr;
+
+up_fail:
+ up_write(>mmap_sem);
+ return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm == NULL)
+ return NULL;
+
+ if (vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+ else
+ return NULL;
+}
--
2.7.4
[PATCH V3 14/26] csky: User access
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 396
arch/csky/lib/usercopy.c| 271 +++
2 files changed, 667 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..d949847
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void * addr, unsigned long size)
+{
+return (((unsigned long)addr < current_thread_info()->addr_limit.seg) &&
+ ((unsigned long)(addr + size) <
current_thread_info()->addr_limit.seg));
+}
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr,0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x,ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x,ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x,ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size)\
+({ \
+ long __pu_err=0;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if(__pu_addr){ \
+ __put_user_size(__pu_val, (__pu_addr), (size), __pu_err); \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x,ptr,size)\
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x,ptr,size,retval) \
+do {\
+ retval = 0; \
+ switch (size) { \
+ case 1: __put_user_asm_b(x, ptr, retval); break;\
+ case 2: __put_user_asm_h(x, ptr, retval); break;\
+ case 4: __put_user_asm_w(x, ptr, retval); break;\
+ case 8: __put_user_asm_64(x, ptr, retval); break; \
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about,
[PATCH V3 00/26] C-SKY(csky) Linux Kernel Port
ignal's api 7501771 csky: bugfix forget restore usp. 923e2ca csky: re-struct the pt_regs for regset. 2a1e499 csky: fixup config. ada81ec csky: bugfix abiv1 compile error. e34acb9 csky: bugfix abiv1 couldn't support -mno-stack-size. ec53560 csky: change irq map, reserve soft_irq_irq space. c7576f7 csky: bugfix modpost warning with -mno-stack-size c8ff9d4 csky: support csky mp timer alpha version. deabaaf csky: update .gitignore. 574815c csky: bugfix compile error with abiv1 in 4.15 0b426a7 csky: bugfix format of cpu verion id. 083435f csky: irq-csky-v2 alpha init. 21209e5 csky: add .gitignore 73e19b4 csky: remove FMFS_FPU_REGS/FMTS_FPU_REGS 07e8fac csky: add fpu regset in ptrace.c cac779d csky: add CSKY_VECIRQ_LEGENCY for SOC bug. 54bab1d csky: move usp into pt_regs. b167422 csky: support regset for ptrace. a098d4c csky: remove ARCH_WANT_IPC_PARSE_VERSION fe61a84 csky: add timer-of support. 27702e2 csky: bugfix boot error. ebe3edb csky: bugfix gx6605s boot failed - add __HEAD to head.section for head.S - move INIT_SECTION together to fix compile warning. 7138cae csky: coding convension for timer-nationalchip.c fa7f9bb csky: use ffs instead of fls. ddc9e81 csky: change to generic irq chip for irq-csky.c e9be8b9 irqchip: add generic irq chip for irq-nationalchip 2ee83fe csky: add set_handle_irq(), ref from openrisc & arm. 74181d6 csky: use irq_domain_add_linear instead of leagcy. fa45ae4 csky: bugfix setup stroge order for uncached. eb8030f csky: add HIGHMEM config in Kconfig 4f983d4 csky: remove "default n" in Kconfig 2467575 csky: use asm-generic/signal.h 77438e5 csky: coding conventions for irq.c 2e4a2b4 csky: optimize the cache flush ops. 96e1c58 csky: add CONFIG_CPU_ASID_BITS. 9339666 csky: add cprcr() cpwcr() for abiv1 ff05be4 csky: add THREAD_SHIFT define in asm/page.h 52ab022 csky: add mfcr() mtcr() in asm/reg_ops.h bdcd8f3 csky: revert back Kconfig select. 590c7e6 csky: bugfix compile error with CONFIG_AUDIT 1989292 csky: revert some back with cleanup unistd.h f1454fe csky: cleanup unistd.h 5d2985f csky: cleanup Kconfig and Makefile. 423d97e csky: cancel subdirectories cae2af4 csky: use asm-generic/fcntl.h Guo Ren (26): csky: Build infrastructure csky: defconfig csky: Kernel booting csky: Exception handling csky: System Call csky: Cache and TLB routines csky: MMU and page table management csky: Process management and Signal csky: VDSO and rt_sigreturn csky: IRQ handling csky: Atomic operations csky: ELF and module probe csky: Library functions csky: User access csky: Debug and Ptrace GDB csky: SMP support csky: Misc headers dt-bindings: csky CPU Bindings dt-bindings: timer: gx6605s SOC timer dt-bindings: timer: C-SKY Multi-processor timer dt-bindings: interrupt-controller: C-SKY APB intc dt-bindings: interrupt-controller: C-SKY SMP intc clocksource: add gx6605s SOC system timer clocksource: add C-SKY SMP timer clocksource: add C-SKY timers' build infrastructure irqchip: add C-SKY irqchip drivers Documentation/devicetree/bindings/csky/cpus.txt| 70 .../interrupt-controller/csky,apb-intc.txt | 45 +++ .../bindings/interrupt-controller/csky,mpintc.txt | 40 +++ .../bindings/timer/csky,gx6605s-timer.txt | 46 +++ .../devicetree/bindings/timer/csky,mptimer.txt | 46 +++ arch/csky/Kconfig | 230 arch/csky/Kconfig.debug| 14 + arch/csky/Makefile | 93 + arch/csky/abiv1/Makefile | 8 + arch/csky/abiv1/alignment.c| 331 + arch/csky/abiv1/bswapdi.c | 18 + arch/csky/abiv1/bswapsi.c | 14 + arch/csky/abiv1/cacheflush.c | 50 +++ arch/csky/abiv1/inc/abi/cacheflush.h | 41 +++ arch/csky/abiv1/inc/abi/ckmmu.h| 74 arch/csky/abiv1/inc/abi/entry.h| 159 + arch/csky/abiv1/inc/abi/page.h | 26 ++ arch/csky/abiv1/inc/abi/pgtable-bits.h | 36 ++ arch/csky/abiv1/inc/abi/reg_ops.h | 26 ++ arch/csky/abiv1/inc/abi/regdef.h | 25 ++ arch/csky/abiv1/inc/abi/string.h | 13 + arch/csky/abiv1/inc/abi/tlb.h | 11 + arch/csky/abiv1/inc/abi/vdso.h | 17 + arch/csky/abiv1/memcpy.S | 344 ++ arch/csky/abiv1/memset.c | 38 ++ arch/csky/abiv1/mmap.c | 65 arch/csky/abiv1/strksyms.c | 7 + arch/csky/abiv2/Makefile | 10 + arch/csky/abiv2/cacheflush.c | 54 +++ arch/csky/abiv2/fpu.c | 281 +++ arch/csky/abiv2/inc/abi/cacheflush.h |
[PATCH V3 20/26] dt-bindings: timer: C-SKY Multi-processor timer
Signed-off-by: Guo Ren
---
.../devicetree/bindings/timer/csky,mptimer.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/csky,mptimer.txt
diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt
b/Documentation/devicetree/bindings/timer/csky,mptimer.txt
new file mode 100644
index 000..0d7369f
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/csky,mptimer.txt
@@ -0,0 +1,46 @@
+
+C-SKY Multi-processors Timer
+
+
+C-SKY multi-processors timer is designed for C-SKY SMP system and the
+regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
+
+ - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
+ - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
+ - PTIM_CCVR "cr<3, 14>" Current counter value reg.
+ - PTIM_LVR "cr<6, 14>" Window value reg to triger next event.
+
+==
+timer node bindings definition
+==
+
+Description: Describes SMP timer
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,mptimer"
+ - clocks
+ Usage: required
+ Value type:
+Definition: must be input clk node
+- interrupt
+Usage: required
+Value type:
+Definition: must be timer irq num defined by soc
+- interrupt-parent:
+Usage: required
+ Value type:
+Definition: must be interrupt controller node
+
+Examples:
+-
+
+ timer: timer {
+ compatible = "csky,mptimer";
+ clocks = <_apb_clk>;
+ interrupts = <16>;
+ interrupt-parent = <>;
+ };
--
2.7.4
[PATCH V3 11/26] csky: Atomic operations
Signed-off-by: Guo Ren
---
arch/csky/include/asm/atomic.h | 215 +
arch/csky/include/asm/cmpxchg.h| 70
arch/csky/include/asm/spinlock.h | 286 +
arch/csky/include/asm/spinlock_types.h | 35
arch/csky/kernel/atomic.S | 86 ++
5 files changed, 692 insertions(+)
create mode 100644 arch/csky/include/asm/atomic.h
create mode 100644 arch/csky/include/asm/cmpxchg.h
create mode 100644 arch/csky/include/asm/spinlock.h
create mode 100644 arch/csky/include/asm/spinlock_types.h
create mode 100644 arch/csky/kernel/atomic.S
diff --git a/arch/csky/include/asm/atomic.h b/arch/csky/include/asm/atomic.h
new file mode 100644
index 000..82a124e
--- /dev/null
+++ b/arch/csky/include/asm/atomic.h
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_ATOMIC_H
+#define __ASM_CSKY_ATOMIC_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CPU_HAS_LDSTEX
+
+#define __atomic_add_unless __atomic_add_unless
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+ unsigned long tmp, ret;
+
+ smp_mb();
+
+ asm volatile (
+ "1: ldex.w %0, (%3) \n"
+ " mov %1, %0 \n"
+ " cmpne %0, %4 \n"
+ " bf 2f \n"
+ " add %0, %2 \n"
+ " stex.w %0, (%3) \n"
+ " bez %0, 1b \n"
+ "2: \n"
+ : "=" (tmp), "=" (ret)
+ : "r" (a), "r"(>counter), "r"(u)
+ : "memory");
+
+ if (ret != u)
+ smp_mb();
+
+ return ret;
+}
+
+#define ATOMIC_OP(op, c_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ unsigned long tmp; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%2) \n"\
+ " " #op " %0, %1 \n"\
+ " stex.w %0, (%2) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+}
+
+#define ATOMIC_OP_RETURN(op, c_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " " #op " %0, %2 \n"\
+ " mov %1, %0 \n"\
+ " stex.w %0, (%3) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp), "=" (ret) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+ \
+ return ret; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op) \
+static inline int atomic_fetch_##op(int i, atomic_t *v)
\
+{ \
+ unsigned long tmp, ret; \
+
[PATCH V3 15/26] csky: Debug and Ptrace GDB
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 103
arch/csky/kernel/dumpstack.c| 64
arch/csky/kernel/ptrace.c | 317
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..10b9028
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel (char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..499f7ef
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+unsigned long r5;
+unsigned long r6;
+unsigned long r7;
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+#else
+ unsigned long r8;
+unsigned long r9;
+unsigned long r10;
+unsigned long r11;
+unsigned long r12;
+unsigned long r13;
+unsigned long r14;
+#endif
+unsigned long r15;
+#if defined(__CSKYABIV2__)
+unsigned long r16;
+unsigned long r17;
+unsigned long r26;
+unsigned long r27;
+unsigned long r28;
+unsigned long r29;
+unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..e25d9d3
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memo
[PATCH V3 12/26] csky: ELF and module probe
Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 149 arch/csky/kernel/module.c | 82 2 files changed, 231 insertions(+) create mode 100644 arch/csky/include/asm/elf.h create mode 100644 arch/csky/kernel/module.c diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h new file mode 100644 index 000..9eef4a1 --- /dev/null +++ b/arch/csky/include/asm/elf.h @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. +#ifndef __ASMCSKY_ELF_H +#define __ASMCSKY_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +#define ELF_ARCH 252 + +/* CSKY Relocations */ +#define R_CSKY_NONE 0 +#define R_CSKY_32 1 +#define R_CSKY_PCIMM8BY4 2 +#define R_CSKY_PCIMM11BY2 3 +#define R_CSKY_PCIMM4BY2 4 +#define R_CSKY_PC32 5 +#define R_CSKY_PCRELJSR_IMM11BY2 6 +#define R_CSKY_GNU_VTINHERIT 7 +#define R_CSKY_GNU_VTENTRY8 +#define R_CSKY_RELATIVE 9 +#define R_CSKY_COPY 10 +#define R_CSKY_GLOB_DAT 11 +#define R_CSKY_JUMP_SLOT 12 +#define R_CSKY_ADDR_HI16 24 +#define R_CSKY_ADDR_LO16 25 +#define R_CSKY_PCRELJSR_IMM26BY2 40 + +typedef unsigned long elf_greg_t; + +typedef struct user_fp elf_fpregset_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) + +/* + * These are used to set parameters in the core dumps. + */ +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 +#define ELF_CLASS ELFCLASS32 +#define ELF_PLAT_INIT(_r, load_addr) _r->a0 = 0 + +#ifdef __cskyBE__ +#define ELF_DATA ELFDATA2MSB +#else +#define ELF_DATA ELFDATA2LSB +#endif + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE0x0UL + +/* The member sort in array pr_reg[x] is pc, r1, r0, psr, r2, r3,r4, + r5, r6.. Because GDB difine */ +#if defined(__CSKYABIV2__) + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->a1; \ +pr_reg[2] = regs->a0; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a2; \ +pr_reg[5] = regs->a3; \ +pr_reg[6] = regs->regs[0]; \ +pr_reg[7] = regs->regs[1]; \ +pr_reg[8] = regs->regs[2]; \ +pr_reg[9] = regs->regs[3]; \ +pr_reg[10] = regs->regs[4]; \ +pr_reg[11] = regs->regs[5]; \ +pr_reg[12] = regs->regs[6]; \ +pr_reg[13] = regs->regs[7]; \ +pr_reg[14] = regs->regs[8]; \ +pr_reg[15] = regs->regs[9]; \ +pr_reg[16] = regs->usp;\ +pr_reg[17] = regs->lr; \ +pr_reg[18] = regs->exregs[0]; \ +pr_reg[19] = regs->exregs[1]; \ +pr_reg[20] = regs->exregs[2]; \ +pr_reg[21] = regs->exregs[3]; \ +pr_reg[22] = regs->exregs[4]; \ +pr_reg[23] = regs->exregs[5]; \ +pr_reg[24] = regs->exregs[6]; \ +pr_reg[25] = regs->exregs[7]; \ +pr_reg[26] = regs->exregs[8]; \ +pr_reg[27] = regs->exregs[9]; \ +pr_reg[28] = regs->exregs[10]; \ +pr_reg[29] = regs->exregs[11]; \ +pr_reg[30] = regs->exregs[12]; \ +pr_reg[31] = regs->exregs[13]; \ +pr_reg[32] = regs->exregs[14]; \ +pr_reg[33] = regs->tls; +#else + #define ELF_CORE_COPY_REGS(pr_reg, regs) \ +pr_reg[0] = regs->pc; \ +pr_reg[1] = regs->regs[9]; \ +pr_reg[2] = regs->usp; \ +pr_reg[3] = regs->sr; \ +pr_reg[4] = regs->a0; \ +pr_reg[5] = regs->a1; \ +pr_reg[6] = regs->a2; \ +pr_reg[7] = regs->a3; \ +pr_reg[8] = regs->regs[0]; \ +pr_reg[9] = regs->
[PATCH V3 22/26] dt-bindings: interrupt-controller: C-SKY SMP intc
Signed-off-by: Guo Ren
---
.../bindings/interrupt-controller/csky,mpintc.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
new file mode 100644
index 000..49d1658
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
@@ -0,0 +1,40 @@
+===
+C-SKY Multi-processors Interrupt Controller
+===
+
+C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
+SMP soc, and it also could be used in non-SMP system.
+
+Interrupt number definition:
+
+ 0-15 : software irq, and we use 15 as our IPI_IRQ.
+ 16-31 : private irq, and we use 16 as the co-processor timer.
+ 31-1024: common irq for soc ip.
+
+=
+intc node bindings definition
+=
+
+ Description: Describes SMP interrupt controller
+
+ PROPERTIES
+
+- compatible
+ Usage: required
+Value type:
+Definition: must be "csky,mpintc"
+- interrupt-cells
+Usage: required
+Value type:
+Definition: must be <1>
+- interrupt-controller:
+Usage: required
+
+Examples:
+-
+
+ intc: interrupt-controller {
+ compatible = "csky,mpintc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
--
2.7.4
[PATCH V3 17/26] csky: Misc headers
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/reg_ops.h | 26 +++
arch/csky/abiv1/inc/abi/regdef.h | 25 +++
arch/csky/abiv2/inc/abi/reg_ops.h | 17 ++
arch/csky/abiv2/inc/abi/regdef.h | 26 +++
arch/csky/boot/dts/qemu.dts| 77 +
arch/csky/include/asm/bitops.h | 281 +
arch/csky/include/asm/checksum.h | 54 +++
arch/csky/include/asm/compat.h | 11 ++
arch/csky/include/asm/reg_ops.h| 22 +++
arch/csky/include/uapi/asm/byteorder.h | 14 ++
arch/csky/kernel/asm-offsets.c | 85 ++
11 files changed, 638 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv1/inc/abi/regdef.h
create mode 100644 arch/csky/abiv2/inc/abi/reg_ops.h
create mode 100644 arch/csky/abiv2/inc/abi/regdef.h
create mode 100644 arch/csky/boot/dts/qemu.dts
create mode 100644 arch/csky/include/asm/bitops.h
create mode 100644 arch/csky/include/asm/checksum.h
create mode 100644 arch/csky/include/asm/compat.h
create mode 100644 arch/csky/include/asm/reg_ops.h
create mode 100644 arch/csky/include/uapi/asm/byteorder.h
create mode 100644 arch/csky/kernel/asm-offsets.c
diff --git a/arch/csky/abiv1/inc/abi/reg_ops.h
b/arch/csky/abiv1/inc/abi/reg_ops.h
new file mode 100644
index 000..c5d2ff4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/reg_ops.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+#define cprcr(reg) \
+({ \
+ unsigned int tmp; \
+ asm volatile("cprcr %0, "reg"\n":"=b"(tmp));\
+ tmp;\
+})
+
+#define cpwcr(reg, val)\
+({ \
+ asm volatile("cpwcr %0, "reg"\n"::"b"(val));\
+})
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr30");
+}
+
+static inline unsigned int mfcr_ccr2(void){return 0;}
+
+#endif /* __ABI_REG_OPS_H */
diff --git a/arch/csky/abiv1/inc/abi/regdef.h b/arch/csky/abiv1/inc/abi/regdef.h
new file mode 100644
index 000..cc4cebd
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/regdef.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r1
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[9]
+
+/*
+ * PSR format:
+ * | 31 | 30-24 | 23-16 | 15 14 | 13-0 |
+ * S CPID VEC TM
+ *
+ *S: Super Mode
+ * CPID: Coprocessor id, only 15 for MMU
+ * VEC: Exception Number
+ * TM: Trace Mode
+ */
+#define DEFAULT_PSR_VALUE 0x8f00
+
+#define SYSTRACE_SAVENUM 2
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/abiv2/inc/abi/reg_ops.h
b/arch/csky/abiv2/inc/abi/reg_ops.h
new file mode 100644
index 000..ffe4fc9
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/reg_ops.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr31");
+}
+
+static inline unsigned int mfcr_ccr2(void)
+{
+ return mfcr("cr23");
+}
+#endif /* __ABI_REG_OPS_H */
diff --git a/arch/csky/abiv2/inc/abi/regdef.h b/arch/csky/abiv2/inc/abi/regdef.h
new file mode 100644
index 000..676e74a
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/regdef.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_REGDEF_H
+#define __ASM_CSKY_REGDEF_H
+
+#define syscallid r7
+#define r11_sigr11
+
+#define regs_syscallid(regs) regs->regs[3]
+
+/*
+ * PSR format:
+ * | 31 | 30-24 | 23-16 | 15 14 | 13-10 | 9 | 8-0 |
+ * S VEC TMMM
+ *
+ * S: Super Mode
+ * VEC: Exception Number
+ * TM: Trace Mode
+ * MM: Memory unaligned addr access
+ */
+#define DEFAULT_PSR_VALUE 0x8200
+
+#define SYSTRACE_SAVENUM 5
+
+#endif /* __ASM_CSKY_REGDEF_H */
diff --git a/arch/csky/boot/dts/qemu.dts b/arch/csky/boot/dts/qemu.dts
new file mode 100644
index 000..d36e4cd
--- /dev/null
+++ b/arch/csky/boot/dts/qemu.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+/ {
+ compatible = "csky,qemu";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path =
+ };
+
+ memory@0 {
+
[PATCH V3 05/26] csky: System Call
Signed-off-by: Guo Ren
---
arch/csky/include/asm/syscall.h | 69 +
arch/csky/include/asm/syscalls.h| 14
arch/csky/include/uapi/asm/unistd.h | 10 ++
arch/csky/kernel/syscall.c | 63 +
arch/csky/kernel/syscall_table.c| 13 +++
5 files changed, 169 insertions(+)
create mode 100644 arch/csky/include/asm/syscall.h
create mode 100644 arch/csky/include/asm/syscalls.h
create mode 100644 arch/csky/include/uapi/asm/unistd.h
create mode 100644 arch/csky/kernel/syscall.c
create mode 100644 arch/csky/kernel/syscall_table.c
diff --git a/arch/csky/include/asm/syscall.h b/arch/csky/include/asm/syscall.h
new file mode 100644
index 000..8966739
--- /dev/null
+++ b/arch/csky/include/asm/syscall.h
@@ -0,0 +1,69 @@
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include
+#include
+#include
+
+static inline int
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs_syscallid(regs);
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->a0 = regs->orig_a0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->a0;
+
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->a0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+int error, long val)
+{
+ regs->a0 = (long) error ?: val;
+}
+
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ args[0] = regs->orig_a0;
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+}
+
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, const unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+if (i == 0) {
+ regs->orig_a0 = args[0];
+ args++;
+ i++;
+ n--;
+}
+ memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+}
+
+#endif /* __ASM_SYSCALL_H */
diff --git a/arch/csky/include/asm/syscalls.h b/arch/csky/include/asm/syscalls.h
new file mode 100644
index 000..c478830
--- /dev/null
+++ b/arch/csky/include/asm/syscalls.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_SYSCALLS_H
+#define __ASM_CSKY_SYSCALLS_H
+
+#include
+
+long sys_cacheflush(void __user *, unsigned long, int);
+
+long sys_set_thread_area(unsigned long addr);
+
+long sys_csky_fadvise64_64(int fd, int advice, loff_t offset, loff_t len);
+
+#endif /* __ASM_CSKY_SYSCALLS_H */
diff --git a/arch/csky/include/uapi/asm/unistd.h
b/arch/csky/include/uapi/asm/unistd.h
new file mode 100644
index 000..6fc1448
--- /dev/null
+++ b/arch/csky/include/uapi/asm/unistd.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#define __ARCH_WANT_SYS_CLONE
+#include
+
+#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
+#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/csky/kernel/syscall.c b/arch/csky/kernel/syscall.c
new file mode 100644
index 000..f0a1294
--- /dev/null
+++ b/arch/csky/kernel/syscall.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
+{
+ struct thread_info *ti = task_thread_info(current);
+ struct pt_regs *reg = current_pt_regs();
+
+ reg->tls = addr;
+ ti->tp_value = addr;
+
+ return 0;
+}
+
+SYSCALL_DEFINE6(mmap2,
+ unsigned long, addr,
+ unsigned long, len,
+ unsigned long, prot,
+ unsigned long, flags,
+ unsigned long, fd,
+ off_t, offset)
+{
+ if (unlikely(offset & (~PAGE_MASK >> 12)))
+ return -EINVAL;
+ return sys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - 12));
+}
+
+struct mmap_arg_struct {
+ unsigned long addr;
+ unsigned long len;
+ unsigned long prot;
+ unsigned long flags;
+ unsigned long fd;
+ unsigned long offset;
+};
+
+SYSCALL_DEFINE1(mmap,
+ struct mmap_arg_struct *, arg)
+{
+ struct mmap_arg_struct a;
+
+
[PATCH V3 23/26] clocksource: add gx6605s SOC system timer
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren
---
drivers/clocksource/timer-gx6605s.c | 150
1 file changed, 150 insertions(+)
create mode 100644 drivers/clocksource/timer-gx6605s.c
diff --git a/drivers/clocksource/timer-gx6605s.c
b/drivers/clocksource/timer-gx6605s.c
new file mode 100644
index 000..10194c9
--- /dev/null
+++ b/drivers/clocksource/timer-gx6605s.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#include "timer-of.h"
+
+#define CLKSRC_OFFSET 0x40
+
+#define TIMER_STATUS 0x00
+#define TIMER_VALUE0x04
+#define TIMER_CONTRL 0x10
+#define TIMER_CONFIG 0x20
+#define TIMER_DIV 0x24
+#define TIMER_INI 0x28
+
+#define GX6605S_STATUS_CLR BIT(0)
+#define GX6605S_CONTRL_RST BIT(0)
+#define GX6605S_CONTRL_START BIT(1)
+#define GX6605S_CONFIG_EN BIT(0)
+#define GX6605S_CONFIG_IRQ_EN BIT(1)
+
+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
+{
+ struct clock_event_device *ce = (struct clock_event_device *) dev;
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* reset and stop counter */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* enable with irq and start */
+ writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, base +
TIMER_CONFIG);
+
+ return 0;
+}
+
+static int gx6605s_timer_set_next_event(unsigned long delta, struct
clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* use reset to pause timer */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* config next timeout value */
+ writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ return 0;
+}
+
+static int gx6605s_timer_shutdown(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(0, base + TIMER_CONTRL);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_DYNIRQ |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = gx6605s_timer_shutdown,
+ .set_state_oneshot = gx6605s_timer_set_oneshot,
+ .set_next_event = gx6605s_timer_set_next_event,
+ .cpumask= cpu_possible_mask,
+ },
+ .of_irq = {
+ .handler= gx6605s_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static u64 notrace gx6605s_sched_clock_read(void)
+{
+ void __iomem *base;
+
+ base = timer_of_base() + CLKSRC_OFFSET;
+
+ return (u64) readl_relaxed(base + TIMER_VALUE);
+}
+
+static void gx6605s_clkevt_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ clockevents_config_and_register(, timer_of_rate(), 2,
ULONG_MAX);
+}
+
+static int gx6605s_clksrc_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_INI);
+
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
+
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate());
+
+ return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s",
timer_of_rate(),
+200, 32, clocksource_mmio_readl_up);
+}
+
+static int __init gx6605s_timer_init(struct device_node *np)
+{
+ int ret;
+
+ /*
+* The timer driver is for nationalchip gx6605s SOC and there are two
same timer
+* in gx6605s. We use one for clkevt and another for clksrc.
+*
+* The timer is mmio map to access, so we need give mmio addres in dts.
+*
+* It provides a 32bit countup timer and interrupt will be caused by
count-overflow.
+* So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
+*
+* The counter at 0x0 offset is clock event.
+* The counter at 0x40 offset is clock source.
+
[PATCH V3 10/26] csky: IRQ handling
Signed-off-by: Guo Ren
---
arch/csky/include/asm/irq.h | 10
arch/csky/include/asm/irqflags.h | 49
arch/csky/kernel/irq.c | 31 +
3 files changed, 90 insertions(+)
create mode 100644 arch/csky/include/asm/irq.h
create mode 100644 arch/csky/include/asm/irqflags.h
create mode 100644 arch/csky/kernel/irq.c
diff --git a/arch/csky/include/asm/irq.h b/arch/csky/include/asm/irq.h
new file mode 100644
index 000..9390cb0
--- /dev/null
+++ b/arch/csky/include/asm/irq.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQ_H
+#define __ASM_CSKY_IRQ_H
+
+#include
+
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+
+#endif /* __ASM_CSKY_IRQ_H */
diff --git a/arch/csky/include/asm/irqflags.h b/arch/csky/include/asm/irqflags.h
new file mode 100644
index 000..bd55b21
--- /dev/null
+++ b/arch/csky/include/asm/irqflags.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_IRQFLAGS_H
+#define __ASM_CSKY_IRQFLAGS_H
+#include
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+
+ flags = mfcr("psr");
+ asm volatile("psrclr ie\n":::"memory");
+ return flags;
+}
+#define arch_local_irq_save arch_local_irq_save
+
+static inline void arch_local_irq_enable(void)
+{
+ asm volatile("psrset ee, ie\n":::"memory");
+}
+#define arch_local_irq_enable arch_local_irq_enable
+
+static inline void arch_local_irq_disable(void)
+{
+ asm volatile("psrclr ie\n":::"memory");
+}
+#define arch_local_irq_disable arch_local_irq_disable
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ return mfcr("psr");
+}
+#define arch_local_save_flags arch_local_save_flags
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ mtcr("psr", flags);
+}
+#define arch_local_irq_restore arch_local_irq_restore
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !(flags & (1<<6));
+}
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include
+
+#endif /* __ASM_CSKY_IRQFLAGS_H */
diff --git a/arch/csky/kernel/irq.c b/arch/csky/kernel/irq.c
new file mode 100644
index 000..ef2600d
--- /dev/null
+++ b/arch/csky/kernel/irq.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+
+static void (*handle_arch_irq)(struct pt_regs *regs) = NULL;
+
+void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
+{
+ if (handle_arch_irq)
+ return;
+
+ handle_arch_irq = handle_irq;
+}
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+#ifdef CONFIG_SMP
+ setup_smp_ipi();
+#endif
+}
+
+asmlinkage void __irq_entry csky_do_IRQ(struct pt_regs *regs)
+{
+ handle_arch_irq(regs);
+}
--
2.7.4
[PATCH V3 04/26] csky: Exception handling
Signed-off-by: Guo Ren
---
arch/csky/abiv1/alignment.c | 331 +
arch/csky/abiv1/inc/abi/entry.h | 159
arch/csky/abiv2/inc/abi/entry.h | 157
arch/csky/include/asm/traps.h | 39
arch/csky/include/asm/unistd.h | 3 +
arch/csky/kernel/cpu-probe.c| 78
arch/csky/kernel/entry.S| 396
arch/csky/kernel/traps.c| 168 +
arch/csky/mm/fault.c| 220 ++
9 files changed, 1551 insertions(+)
create mode 100644 arch/csky/abiv1/alignment.c
create mode 100644 arch/csky/abiv1/inc/abi/entry.h
create mode 100644 arch/csky/abiv2/inc/abi/entry.h
create mode 100644 arch/csky/include/asm/traps.h
create mode 100644 arch/csky/include/asm/unistd.h
create mode 100644 arch/csky/kernel/cpu-probe.c
create mode 100644 arch/csky/kernel/entry.S
create mode 100644 arch/csky/kernel/traps.c
create mode 100644 arch/csky/mm/fault.c
diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c
new file mode 100644
index 000..b8764d2
--- /dev/null
+++ b/arch/csky/abiv1/alignment.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+
+static int align_enable = 1;
+static int align_count = 0;
+
+static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
+{
+ return *((int *)&(regs->a0) - 2 + rx);
+}
+
+static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
+{
+ *((int *)&(regs->a0) - 2 + rx) = val;
+}
+
+/*
+ * Get byte-value from addr and set it to *valp.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldb_asm(uint32_t addr, uint32_t *valp)
+{
+ uint32_t val;
+ int err;
+
+ if (!access_ok(VERIFY_READ, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "ldb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err), "=r"(val)
+ : "r" (addr)
+ );
+
+ *valp = val;
+
+ return err;
+}
+
+/*
+ * Put byte-value to addr.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static volatile int stb_asm(uint32_t addr, uint32_t val)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0 \n"
+ "1: \n"
+ "stb%1, (%2)\n"
+ "br 3f \n"
+ "2: \n"
+ "movi %0, 1 \n"
+ "br 3f \n"
+ ".section __ex_table,\"a\" \n"
+ ".align 2 \n"
+ ".long 1b, 2b \n"
+ ".previous \n"
+ "3: \n"
+ : "="(err)
+ : "r"(val), "r" (addr)
+ );
+
+ return err;
+}
+
+/*
+ * Get half-word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ if (ldb_asm(addr, ))
+ return 1;
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store half-word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ byte0 = byte1 = get_ptreg(regs, rz);
+
+ byte0 &= 0xff;
+
+ if (stb_asm(addr, byte0))
+ return 1;
+
+ addr += 1;
+ byte1 = (byte1 >> 8) & 0xff;
+ if (stb_asm(addr, byte1))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Get word from [rx
[PATCH V3 07/26] csky: MMU and page table management
- abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
- abiv2 CPUs are all PIPT cache and they could support highmem.
Here is our memory layout plan:
Fixmap : 0xffc02000 – 0xf000 (4 MB - 12KB)
Pkmap: 0xff80 – 0xffc0 (4 MB)
Vmalloc : 0xf020 – 0xff00 (238 MB)
Lowmem : 0x8000 – 0xc000 (1GB)
Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
page-table for it.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/ckmmu.h| 74
arch/csky/abiv1/inc/abi/page.h | 26 +++
arch/csky/abiv1/inc/abi/pgtable-bits.h | 36
arch/csky/abiv1/mmap.c | 65 +++
arch/csky/abiv2/inc/abi/ckmmu.h| 87 ++
arch/csky/abiv2/inc/abi/page.h | 14 ++
arch/csky/abiv2/inc/abi/pgtable-bits.h | 37
arch/csky/include/asm/addrspace.h | 10 ++
arch/csky/include/asm/fixmap.h | 26 +++
arch/csky/include/asm/highmem.h| 50 ++
arch/csky/include/asm/mmu.h| 11 ++
arch/csky/include/asm/page.h | 101 +++
arch/csky/include/asm/pgalloc.h| 108
arch/csky/include/asm/pgtable.h| 299 +
arch/csky/include/asm/segment.h| 18 ++
arch/csky/include/asm/shmparam.h | 10 ++
arch/csky/mm/dma-mapping.c | 254
arch/csky/mm/highmem.c | 195 +
arch/csky/mm/init.c| 116 +
arch/csky/mm/ioremap.c | 48 ++
20 files changed, 1585 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv1/inc/abi/page.h
create mode 100644 arch/csky/abiv1/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/abiv1/mmap.c
create mode 100644 arch/csky/abiv2/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv2/inc/abi/page.h
create mode 100644 arch/csky/abiv2/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/include/asm/addrspace.h
create mode 100644 arch/csky/include/asm/fixmap.h
create mode 100644 arch/csky/include/asm/highmem.h
create mode 100644 arch/csky/include/asm/mmu.h
create mode 100644 arch/csky/include/asm/page.h
create mode 100644 arch/csky/include/asm/pgalloc.h
create mode 100644 arch/csky/include/asm/pgtable.h
create mode 100644 arch/csky/include/asm/segment.h
create mode 100644 arch/csky/include/asm/shmparam.h
create mode 100644 arch/csky/mm/dma-mapping.c
create mode 100644 arch/csky/mm/highmem.c
create mode 100644 arch/csky/mm/init.c
create mode 100644 arch/csky/mm/ioremap.c
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h
new file mode 100644
index 000..5954ebb
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/ckmmu.h
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ASM_CSKY_CKMMUV1_H
+#define __ASM_CSKY_CKMMUV1_H
+#include
+
+static inline int read_mmu_index(void)
+{
+ return cprcr("cpcr0");
+}
+
+static inline void write_mmu_index(int value)
+{
+ cpwcr("cpcr0", value);
+}
+
+static inline int read_mmu_entrylo0(void)
+{
+ return cprcr("cpcr2") << 6;
+}
+
+static inline int read_mmu_entrylo1(void)
+{
+ return cprcr("cpcr3") << 6;
+}
+
+static inline void write_mmu_pagemask(int value)
+{
+ cpwcr("cpcr6", value);
+}
+
+static inline int read_mmu_entryhi(void)
+{
+ return cprcr("cpcr4");
+}
+
+static inline void write_mmu_entryhi(int value)
+{
+ cpwcr("cpcr4", value);
+}
+
+/*
+ * TLB operations.
+ */
+static inline void tlb_probe(void)
+{
+ cpwcr("cpcr8", 0x8000);
+}
+
+static inline void tlb_read(void)
+{
+ cpwcr("cpcr8", 0x4000);
+}
+
+static inline void tlb_invalid_all(void)
+{
+ cpwcr("cpcr8", 0x0400);
+}
+
+static inline void tlb_invalid_indexed(void)
+{
+ cpwcr("cpcr8", 0x0200);
+}
+
+static inline void setup_pgd(unsigned long pgd, bool kernel)
+{
+ cpwcr("cpcr29", pgd);
+}
+
+static inline unsigned long get_pgd(void)
+{
+ return cprcr("cpcr29");
+}
+#endif /* __ASM_CSKY_CKMMUV1_H */
diff --git a/arch/csky/abiv1/inc/abi/page.h b/arch/csky/abiv1/inc/abi/page.h
new file mode 100644
index 000..b0d2122
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/page.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+extern unsigned long shm_align_mask;
+extern void flush_dcache_page(struct page *);
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+ unsigned long addr2)
+{
+ return (addr1 ^ addr2) & shm_align_mask;
+}
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
[PATCH V3 13/26] csky: Library functions
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 18 ++
arch/csky/abiv1/bswapsi.c| 14 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 344 +++
arch/csky/abiv1/memset.c | 38 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 28
arch/csky/abiv2/memcmp.S | 151 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memcpy.c | 40 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 29
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/platform.c | 17 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 40 +
21 files changed, 1483 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memcpy.c
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/platform.c
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..7346252
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return (((u) & 0xff00ull) >> 56) |
+ (((u) & 0x00ffull) >> 40) |
+ (((u) & 0xff00ull) >> 24) |
+ (((u) & 0x00ffull) >> 8) |
+ (((u) & 0xff00ull) << 8) |
+ (((u) & 0x00ffull) << 24) |
+ (((u) & 0xff00ull) << 40) |
+ (((u) & 0x00ffull) << 56);
+}
+
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..6e26b7e
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return (((u) & 0xff00) >> 24) |
+ (((u) & 0x00ff) >> 8) |
+ (((u) & 0xff00) << 8) |
+ (((u) & 0x00ff) << 24);
+}
+
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..60d4fc4
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..f86ad75
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4 /* If len less than 4
bytes */
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
[PATCH V3 06/26] csky: Cache and TLB routines
Signed-off-by: Guo Ren
---
arch/csky/abiv1/cacheflush.c | 50
arch/csky/abiv1/inc/abi/cacheflush.h | 41 +++
arch/csky/abiv1/inc/abi/tlb.h | 11 ++
arch/csky/abiv2/cacheflush.c | 54 +
arch/csky/abiv2/inc/abi/cacheflush.h | 38 ++
arch/csky/abiv2/inc/abi/tlb.h | 12 ++
arch/csky/include/asm/barrier.h | 45 +++
arch/csky/include/asm/cache.h | 28 +
arch/csky/include/asm/cacheflush.h| 8 ++
arch/csky/include/asm/io.h| 23
arch/csky/include/asm/tlb.h | 19 +++
arch/csky/include/asm/tlbflush.h | 22
arch/csky/include/uapi/asm/cachectl.h | 13 +++
arch/csky/mm/cachev1.c| 126
arch/csky/mm/cachev2.c| 79 +
arch/csky/mm/syscache.c | 28 +
arch/csky/mm/tlb.c| 214 ++
17 files changed, 811 insertions(+)
create mode 100644 arch/csky/abiv1/cacheflush.c
create mode 100644 arch/csky/abiv1/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv1/inc/abi/tlb.h
create mode 100644 arch/csky/abiv2/cacheflush.c
create mode 100644 arch/csky/abiv2/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv2/inc/abi/tlb.h
create mode 100644 arch/csky/include/asm/barrier.h
create mode 100644 arch/csky/include/asm/cache.h
create mode 100644 arch/csky/include/asm/cacheflush.h
create mode 100644 arch/csky/include/asm/io.h
create mode 100644 arch/csky/include/asm/tlb.h
create mode 100644 arch/csky/include/asm/tlbflush.h
create mode 100644 arch/csky/include/uapi/asm/cachectl.h
create mode 100644 arch/csky/mm/cachev1.c
create mode 100644 arch/csky/mm/cachev2.c
create mode 100644 arch/csky/mm/syscache.c
create mode 100644 arch/csky/mm/tlb.c
diff --git a/arch/csky/abiv1/cacheflush.c b/arch/csky/abiv1/cacheflush.c
new file mode 100644
index 000..4c6fede
--- /dev/null
+++ b/arch/csky/abiv1/cacheflush.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+ unsigned long addr;
+
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_arch_1, &(page)->flags);
+ return;
+ }
+
+ /*
+* We could delay the flush for the !page_mapping case too. But that
+* case is for exec env/arg pages and those are %99 certainly going to
+* get faulted into the tlb (and thus flushed) anyways.
+*/
+ addr = (unsigned long) page_address(page);
+ dcache_wb_range(addr, addr + PAGE_SIZE);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t
*pte)
+{
+ unsigned long addr;
+ struct page *page;
+ unsigned long pfn;
+
+ pfn = pte_pfn(*pte);
+ if (unlikely(!pfn_valid(pfn)))
+ return;
+
+ page = pfn_to_page(pfn);
+ addr = (unsigned long) page_address(page);
+
+ if (vma->vm_flags & VM_EXEC ||
+ pages_do_alias(addr, address & PAGE_MASK))
+ cache_wbinv_all();
+
+ clear_bit(PG_arch_1, &(page)->flags);
+}
diff --git a/arch/csky/abiv1/inc/abi/cacheflush.h
b/arch/csky/abiv1/inc/abi/cacheflush.h
new file mode 100644
index 000..ba5071e
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/cacheflush.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+#ifndef __ABI_CSKY_CACHEFLUSH_H
+#define __ABI_CSKY_CACHEFLUSH_H
+
+#include
+#include
+#include
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+#define flush_cache_mm(mm) cache_wbinv_all()
+#define flush_cache_page(vma,page,pfn) cache_wbinv_all()
+#define flush_cache_dup_mm(mm) cache_wbinv_all()
+
+#define flush_cache_range(mm,start,end)cache_wbinv_range(start, end)
+#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
+#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_page(vma, page) cache_wbinv_all()
+#define flush_icache_range(start, end) cache_wbinv_range(start, end)
+#define flush_icache_user_range(vma,pg,adr,len)cache_wbinv_range(adr,
adr + len)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+ icache_inv_all(); \
+}while(0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do{ \
+ cache_wbinv_all(); \
+ memcpy(dst, src, len); \
+}while(0)
+
+#define flush_dcache_mmap_lock(mapping)do{}while(0)
+#define flush_dcache_mmap_unlock(mapping) do{}while(0)
+
+#endif /* __ABI_CSKY_CACHE
[PATCH V3 21/26] dt-bindings: interrupt-controller: C-SKY APB intc
Signed-off-by: Guo Ren
---
.../interrupt-controller/csky,apb-intc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
new file mode 100644
index 000..faa482c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
@@ -0,0 +1,45 @@
+==
+C-SKY APB Interrupt Controller
+==
+
+C-SKY APB Interrupt Controller is a simple soc interrupt controller
+on the apb bus and we only use it as root irq controller.
+
+ - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq
nums.
+ - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
+ - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq
nums.
+
+=
+intc node bindings definition
+=
+
+Description: Describes APB interrupt controller
+
+PROPERTIES
+
+- compatible
+Usage: required
+Value type:
+Definition: must be "csky,apb-intc"
+ "csky,dual-apb-intc"
+ "csky,gx6605s-intc"
+- interrupt-cells
+Usage: required
+Value type:
+Definition: must be <1>
+ - reg
+ Usage: required
+ Value type:
+Definition: in soc from cpu view
+- interrupt-controller:
+Usage: required
+
+Examples:
+-
+
+ intc: interrupt-controller {
+ compatible = "csky,apb-intc";
+ #interrupt-cells = <1>;
+ reg = <0x0050 0x400>;
+ interrupt-controller;
+ };
--
2.7.4
Re: [PATCH V2 18/19] clocksource: add C-SKY clocksource drivers
On Wed, Jul 04, 2018 at 04:35:43PM +0200, Thomas Gleixner wrote:
> On Wed, 4 Jul 2018, Guo Ren wrote:
> > On Tue, Jul 03, 2018 at 11:39:05AM +0200, Thomas Gleixner wrote:
> > > > +static inline u64 get_ccvr(void)
> > > > +{
> > > > + u32 lo, hi, t;
> > > > +
> > > > + do {
> > > > + hi = mfcr(PTIM_CCVR_HI);
> > > > + lo = mfcr(PTIM_CCVR_LO);
> > > > + t = mfcr(PTIM_CCVR_HI);
> > > > + } while(t != hi);
> > >
> > > No idea which frequency this timer ticks at, but if the 32 bit wrap does
> > > not come too fast, then you really should avoid that loop. That function
> > > is
> > > called very frequently.
> >
> > 006c :
> > hi = mfcr(PTIM_CCVR_HI);
> > 6c: c1c26023mfcrr3, cr<2, 14>
> > lo = mfcr(PTIM_CCVR_LO);
> > 70: c1c36021mfcrr1, cr<3, 14>
> > t = mfcr(PTIM_CCVR_HI);
> > 74: c1c26022mfcrr2, cr<2, 14>
> > } while(t != hi);
> > 78: 648ecmpne r3, r2
> > 7a: 0bf9bt 0x6c// 6c
> >
> > When two read cr<2, 14> is not equal, we'll retry. So only when
> > CCVR_LO is at 0x between the two read of CCVR_HI. That's very
> > very small probability event for "bt 0x6c".
> >
> > Don't worry about the "do {...} whie(t != hi)", it's no performance issue.
>
> But _three_ mfcr plus a conditional jump which _cannot_ be predicted are a
> performance issue. When you can replace that with a single mfcr, then you
> win a lot, really. The time keeping and the sched clock code can handle
> that nicely unless you really have fast wrap arounds on the LO word.
Timer's frequency is about 50Mhz-100Mhz and LO word wrap arounds timer is
about 42s ~ 84s.
Our Branch prediction buffer will let the CPU speculative execute
continually. So the "bt" won't be the performance issue.
And I could modify it like this:
static inline u64 get_ccvr(void)
{
u32 lo, hi, t;
t = mfcr(PTIM_CCVR_LO);
hi = mfcr(PTIM_CCVR_HI);
lo = mfcr(PTIM_CCVR_LO);
if (lo < t) hi++;
return ((u64)hi << 32) | lo;
}
t = mfcr(PTIM_CCVR_LO);
50: c1c36023mfcrr3, cr<3, 14>
hi = mfcr(PTIM_CCVR_HI);
54: c1c26021mfcr r1, cr<2, 14>
lo = mfcr(PTIM_CCVR_LO);
58: c1c3602cmfcrr12, cr<3, 14>
if (lo < t) hi++;
5c: 64f0cmphs r12, r3
5e: c4210c21incfr1, r1, 1
return ((u64)hi << 32) | lo;
62: 3200movir2, 0
Hmm? (No jump at all)
Guo Ren
Re: [PATCH V2 05/19] csky: System Call
On Wed, Jul 04, 2018 at 11:04:37PM +0200, Arnd Bergmann wrote: > Right, I do understand what it's used for, my point was that you > don't really need a separate system call number for it, just redirect > the entry point using the same trick that nds32 has in > arch/nds32/kernel/syscall_table.c: > > #define sys_fadvise64_64 csky_fadvise64_64 Thx for the tip :) Guo Ren
Re: [PATCH V2 18/19] clocksource: add C-SKY clocksource drivers
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC |
> > + CLOCK_EVT_FEAT_ONESHOT,
> > + .set_state_shutdown = nc_timer_shutdown,
> > + .set_state_periodic = nc_timer_set_periodic,
> > + .set_next_event = nc_timer_set_next_event,
>
> set_oneshot ?
Yes oneshort, but also could support periodic. But in fact, it only
works with oneshort.
> > + .cpumask = cpu_possible_mask,
> > + },
> > +
> > + .of_irq = {
> > + .handler = timer_interrupt,
> > + .flags = IRQF_TIMER | IRQF_IRQPOLL,
> > + },
> > +};
> > +
> > +static u64 notrace nc_sched_clock_read(void)
> > +{
> > + void __iomem *base;
> > +
> > + base = timer_of_base() + CLKSRC_OFFSET;
> > +
> > + return (u64) readl_relaxed(base + TIMER_VALUE);
> > +}
> > +
> > +static void nc_timer_set_div(void __iomem *base)
> > +{
> > + unsigned int div;
> > +
> > + div = timer_of_rate()/TIMER_FREQ - 1;
>
> space ' / '
>
> Is it
> (timer_of_rate() / TIMER_FREQ) - 1
> or
> timer_of_rate() / (TIMER_FREQ - 1)
>
> ?
Thx, I'll modify it like this:
div = (timer_of_rate() / TIMER_FREQ) - 1;
> > + clocksource_mmio_init(base + TIMER_VALUE, "nationalchip", TIMER_FREQ,
> > 200, 32,
> > + clocksource_mmio_readl_up);
>
> return code check ?
Ok, add return code check.
> > +TIMER_OF_DECLARE(nc_timer, "nationalchip,timer-v1", nc_timer_init);
>
> same comment than cksy timer.
Ok.
Guo Ren
Re: [PATCH V2 19/19] irqchip: add C-SKY irqchip drivers
On Wed, Jul 04, 2018 at 08:43:29AM +0200, Thomas Gleixner wrote: > > Do you mean merge irq-csky-v1.c irq-csky-v2.c irq-nationalchip.c into > > one file eg: irq-csky.c? > > Yes, but only if there is enough code to share without creating an ifdef > mess. But that looks doable Ok, I'll try. Guo Ren
Re: [PATCH V2 13/19] csky: Library functions
On Tue, Jul 03, 2018 at 10:04:57PM +0200, Arnd Bergmann wrote: > It's better to avoid relying on libgcc here. Please use the > CONFIG_GENERIC_LIB_ASHLDI3/ASHRDI3/LSHRDI3/etc > helpers that we already have in the kernel. Ok, I'll try Guo Ren
Re: [PATCH V2 05/19] csky: System Call
On Tue, Jul 03, 2018 at 09:53:48PM +0200, Arnd Bergmann wrote:
> We really need all new architectures to use the generic syscall ABI,
> see below for the details.
Ok, follow the rules.
> > +#define __ARCH_WANT_OLD_READDIR
> > +#define __ARCH_WANT_RENAMEAT
> > +#define __ARCH_WANT_STAT64
> > +#define __ARCH_WANT_SYS_ALARM
> > +#define __ARCH_WANT_SYS_CLONE
> > +#define __ARCH_WANT_SYS_FORK
> > +#define __ARCH_WANT_SYS_GETHOSTNAME
> > +#define __ARCH_WANT_SYS_GETPGRP
> > +#define __ARCH_WANT_SYS_IPC
> > +#define __ARCH_WANT_SYS_LLSEEK
> > +#define __ARCH_WANT_SYS_NICE
> > +#define __ARCH_WANT_SYS_OLD_GETRLIMIT
> > +#define __ARCH_WANT_SYS_OLDUMOUNT
> > +#define __ARCH_WANT_SYS_PAUSE
> > +#define __ARCH_WANT_SYS_SIGNAL
> > +#define __ARCH_WANT_SYS_SIGPENDING
> > +#define __ARCH_WANT_SYS_SIGPROCMASK
> > +#define __ARCH_WANT_SYS_SOCKETCALL
> > +#define __ARCH_WANT_SYS_TIME
> > +#define __ARCH_WANT_SYS_UTIME
> > +#define __ARCH_WANT_SYS_VFORK
> > +#define __ARCH_WANT_SYS_WAITPID
>
> I think these all need to be removed, with the exception of
> __ARCH_WANT_SYS_CLONE. It would be nice though to change
> the imlpementation in the kernel so we no longer need to set that
> either.
Ok.
> > +#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
> > +__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
> > +#define __NR_ipc (__NR_arch_specific_syscall + 1)
> > +__SYSCALL(__NR_ipc, sys_ipc)
> > +#define __NR_socketcall(__NR_arch_specific_syscall + 2)
> > +__SYSCALL(__NR_socketcall, sys_socketcall)
> > +#define __NR_ugetrlimit(__NR_arch_specific_syscall + 3)
> > +__SYSCALL(__NR_ugetrlimit, sys_getrlimit)
> > +#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
> > +__SYSCALL(__NR_cacheflush, sys_cacheflush)
> > +#define __NR_sysfs (__NR_arch_specific_syscall + 5)
> > +__SYSCALL(__NR_sysfs, sys_sysfs)
> > +
> > +__SYSCALL(__NR_fadvise64_64, sys_csky_fadvise64_64)
>
> We definitely don't want ipc, socketcall, ugetrlimit, or sysfs.
Ok, remove them.
> For fadvise64_64, please redefine the symbol name so the
> table points at the right entry.
We need exchange the args for abiv1. loff_t is 64bit and abiv1 need
8-bytes align in args.
/*
* for abiv1 the 64bits args should be even th, So we need mov the advice
forward.
*/
SYSCALL_DEFINE4(csky_fadvise64_64,
int, fd,
int, advice,
loff_t, offset,
loff_t, len)
{
return sys_fadvise64_64(fd, offset, len, advice);
}
>
> I'm not completely sure about set_thread_area, can you explain
> what you need that for?
In abiv1 there is no tls register, so we use "trap 3" for csky_get_tls
defined in arch/csky/kernel/entry.S to get tls.
Also we use set_thread_area to set tls in kernel.
For abiv2 it has r31 for tls-reg, but we still keep the mechanism.
> > +#define __NR_setgroups32 __NR_setgroups
> > +#define __NR_getgid32 __NR_getgid
> > +#define __NR_getgroups32 __NR_getgroups
> > +#define __NR_setuid32 __NR_setuid
> > +#define __NR_setgid32 __NR_setgid
> > +#define __NR_getresgid32 __NR_getresgid
> > +#define __NR_setfsuid32__NR_setfsuid
> > +#define __NR_setfsgid32__NR_setfsgid
> > +#define __NR_fchown32 __NR_fchown
> > +#define __NR_geteuid32 __NR_geteuid
> > +#define __NR_getegid32 __NR_getegid
> > +#define __NR_getresuid32 __NR_getresuid
> > +#define __NR_setresuid32 __NR_setresuid
> > +#define __NR_setresgid32 __NR_setresgid
> > +#define __NR_setreuid32__NR_setreuid
> > +#define __NR_setregid32__NR_setregid
> > +#define __NR__llseek __NR_llseek
>
> These should also get removed.
Ok.
> > +struct mmap_arg_struct {
> > + unsigned long addr;
> > + unsigned long len;
> > + unsigned long prot;
> > + unsigned long flags;
> > + unsigned long fd;
> > + unsigned long offset;
> > +};
> > +
> > +SYSCALL_DEFINE1(mmap,
> > + struct mmap_arg_struct *, arg)
> > +{
> > + struct mmap_arg_struct a;
> > +
> > + if (copy_from_user(, arg, sizeof(a)))
> > + return -EINVAL;
> > +
> > + if (unlikely(a.offset & ~PAGE_MASK))
> > + return -EINVAL;
> > +
> > + return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
> > a.offset >> PAGE_SHIFT);
> > +}
>
> This can be removed since there is mmap2()
Ok.
Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On Tue, Jul 03, 2018 at 06:03:04PM +0200, Arnd Bergmann wrote: > It looks like the CK8xx CPUs are basically compatible, so it would > be nice to have a way to configure a kernel that can run on all > of them, picking a safe default for options that depend on a > particular CPU. E.g. when only CK860 supports SMP, you might > start out by making SMP "depend on !(CPU_CK807 || CPU_CK810)", > as an alternative to implementing a way for an SMP-enabled kernel > to run on non-SMP CPUs (arm has that, but it's probably too complex > for your needs). > > Similarly, you can set L1_CACHE_BYTES to the largest possible > size, and make things like CPU_TLB_SIZE dynamically detected. We talked about this topic in the last patchsets. Ck807/810/860 are mutually incompatible in kernel level but both can run user space programs in ck807/810. On Wed, Mar 28, 2018 at 09:40:49AM +0200, Arnd Bergmann wrote: > Ok, thanks for the clarification. Obviously if they are mutually incompatible, > there is no point in using a common kernel, so your current version is > absolutely fine, and this is similar to how we cannot have a common kernel > between ARMv5, ARMv7-A and ARMv7-M, which are all incompatible > at the kernel level. Yes. > One more question for my understanding: Are the three types of ck8xx > CPUs mutually incompatible in user space as well, or are the differences > only for the kernel? For the ARM example, ARMv5 and ARMv7 > fundamentally require separate kernels, but both can run user space > programs built for ARMv5. -mcpu=ck807 app could run on ck807, ck810, ck860. -mcpu=ck810 app could run on ck807, ck810, ck860. -mcpu=ck860 app only run on ck860. They are all incompatible at the kernel level. > > +menu "C-SKY Debug Options" > > +config CSKY_DEBUG_INFO > > + bool "Compile the kernel with debug info, just add -g" > > + depends on !DEBUG_INFO > > + help > > + DEBUG_INFO and COMPILE_TEST is conflict, so we provide > > + another way to support -g. > > + Some drivers eg: DW_MMC need COMPILE_TEST for new cpu > > + arch :( > > Just send a patch to change those dependencies, there is no reason > not to apply those. Generally speaking, the kernel should not contain > workarounds for particular (mis-)features of the kernel, when you can > just change those. Ok. > > +generic-y += atomic.h > > The asm-generic version of atomic.h is a bit inefficient, > you might want to provide an optimized version for your > architecture. Ok. > > +generic-y += auxvec.h > > You should not need asm/auxvec.h or uapi/asm/auxvec.h Ok. > > +generic-y += bug.h > > providing your own bug.h might be helpful too. > Have a look Ok. > > +generic-y += cputime.h > > asm-generic/cputime.h no loinger exists Ok, remove it. > > +generic-y += kvm_para.h > > Do you support KVM? No, remove it, thx. > > +generic-y += sizes.h > > Deprecated and should not be needed Ok, remove it. Guo Ren
Re: [PATCH V2 18/19] clocksource: add C-SKY clocksource drivers
On Tue, Jul 03, 2018 at 11:39:05AM +0200, Thomas Gleixner wrote:
> -EEMPTYCHANGELOG
Ok
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (C) 2018 Hangzhou NationalChip Science & Technology Co.,Ltd.
>
> newline please
Ok
> > +#define BITS_CSKY_TIMER56
> > +
> > +DECLARE_PER_CPU(struct timer_of, csky_to);
>
> static?
Ok.
>
> > +
> > +static int csky_timer_irq;
> > +static int csky_timer_rate;
> > +
> > +static inline u64 get_ccvr(void)
> > +{
> > + u32 lo, hi, t;
> > +
> > + do {
> > + hi = mfcr(PTIM_CCVR_HI);
> > + lo = mfcr(PTIM_CCVR_LO);
> > + t = mfcr(PTIM_CCVR_HI);
> > + } while(t != hi);
>
> No idea which frequency this timer ticks at, but if the 32 bit wrap does
> not come too fast, then you really should avoid that loop. That function is
> called very frequently.
006c :
hi = mfcr(PTIM_CCVR_HI);
6c: c1c26023mfcrr3, cr<2, 14>
lo = mfcr(PTIM_CCVR_LO);
70: c1c36021mfcrr1, cr<3, 14>
t = mfcr(PTIM_CCVR_HI);
74: c1c26022mfcrr2, cr<2, 14>
} while(t != hi);
78: 648ecmpne r3, r2
7a: 0bf9bt 0x6c// 6c
When two read cr<2, 14> is not equal, we'll retry. So only when
CCVR_LO is at 0x between the two read of CCVR_HI. That's very
very small probability event for "bt 0x6c".
Don't worry about the "do {...} whie(t != hi)", it's no performance issue.
> > +DEFINE_PER_CPU(struct timer_of, csky_to) = {
>
> static
Ok.
> > + .flags = TIMER_OF_CLOCK | TIMER_OF_IRQ,
> > +
> > + .clkevt = {
> > + .name = "C-SKY SMP Timer V1",
> > + .rating = 300,
> > + .features = CLOCK_EVT_FEAT_PERCPU | CLOCK_EVT_FEAT_ONESHOT,
> > + .set_state_shutdown = csky_timer_shutdown,
> > + .set_state_oneshot = csky_timer_oneshot,
> > + .set_state_oneshot_stopped = csky_timer_oneshot_stopped,
> > + .set_next_event = csky_timer_set_next_event,
> > + },
> > +
> > + .of_irq = {
> > + .handler = timer_interrupt,
> > + .flags = IRQF_TIMER,
> > + .percpu = 1,
>
> This is inconsistent. You made it half tabular and half not. Please use
> tabular style consistently.
Ok.
.clkevt = {
.name = "C-SKY SMP Timer V1",
.features = CLOCK_EVT_FEAT_PERCPU |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_state_shutdown = csky_timer_shutdown,
.set_state_oneshot = csky_timer_oneshot,
.set_state_oneshot_stopped = csky_timer_oneshot_stopped,
.set_next_event = csky_timer_set_next_event,
},
.of_irq = {
.handler= timer_interrupt,
.flags = IRQF_TIMER,
.percpu = 1,
> > +/*** clock event for percpu ***/
>
> Please refrain from inventing new horrible comment styles.
Ok.
/* clock event for percpu */
> > +struct clocksource csky_clocksource = {
> > + .name = "csky_timer_v1_clksrc",
> > + .rating = 400,
> > + .mask = CLOCKSOURCE_MASK(BITS_CSKY_TIMER),
> > + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> > + .read = clksrc_read,
>
> tabular style please
Ok.
> > + ret = cpuhp_setup_state(CPUHP_AP_DUMMY_TIMER_STARTING,
> > + "clockevents/csky/timer:starting",
> > + csky_timer_starting_cpu,
> > + csky_timer_dying_cpu);
>
> Oh no. Just picking a random hotplug event is not how it works. Add your
> own please and make sure it's at the proper place.
like this?
include/linux/cpuhotplug.h:
CPUHP_AP_KVM_ARM_TIMER_STARTING,
+ CPUHP_AP_CSKY_TIMER_STARTING,
/* Must be the last timer callback */
CPUHP_AP_DUMMY_TIMER_STARTING,
> > + struct clock_event_device *ce = (struct clock_event_device *) dev;
>
> Pointless type cast.
Ok.
struct clock_event_device *ce = dev;
> > + .flags = IRQF_TIMER | IRQF_IRQPOLL,
> > + },
>
> See above
Ok, tabular
Guo Ren
Re: [PATCH V2 16/19] csky: SMP support
On Fri, Jul 06, 2018 at 06:24:33AM +0100, Mark Rutland wrote:
> > + if (cpu >= NR_CPUS)
> > + goto error;
> > +
> > + if (of_property_read_string(node, "status", ))
> > + status = "enable";
> > +
> > + if (strcmp(status, "disable") == 0)
> > + goto error;
>
> Please use of_device_is_available(node);
Ok.
> "enable" is not a sensible value for
> the status property, and "disable" (rather than "disabled") is simply unusual.
>
> Neither "enable" nor "disable" are correct values for the status property.
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "on";
};
cpu@1 {
device_type = "cpu";
reg = <1>;
status = "off";
};
};
> What is the value in the reg property, exactly?
See above, I'll remove the reg property and it's no use.
> Is there a unique ID in
> hardware for each CPU in the system?
There is no unique ID in current CPU: ck860.
>
> It would be good to document this, e.g. as arm does in
> Documentation/devicetree/bindings/arm/cpus.txt
Ok.
> > +
> > + return cpu;
> > +error:
> > + return -ENODEV;
> > +}
> > +
> > +void __init setup_smp(void)
> > +{
> > + struct device_node *node = NULL;
> > + int cpu;
> > +
> > + while ((node = of_find_node_by_type(node, "cpu"))) {
> > + cpu = csky_of_cpu(node);
> > + if (cpu >= 0) {
> > + set_cpu_possible(cpu, true);
> > + set_cpu_present(cpu, true);
> > + }
> > + }
> > +}
>
> What happens if/when the value in the reg property is larger than NR_CPUS?
Bug. I'll add NR_CPUS limit.
> > +int __cpu_up(unsigned int cpu, struct task_struct *tidle)
> > +{
> > + unsigned int tmp;
> > +
> > + secondary_stack = (unsigned int)tidle->stack + THREAD_SIZE;
> > +
> > + secondary_hint = mfcr("cr31");
> > +
> > + secondary_ccr = mfcr("cr18");
> > +
> > + pr_info("%s: CPU%u\n", __func__, cpu);
> > +
> > + tmp = mfcr("cr<29, 0>");
> > + tmp |= 1 << cpu;
> > + mtcr("cr<29, 0>", tmp);
> > +
> > + while (!cpu_online(cpu));
> > +
> > + secondary_stack = 0;
> > +
> > + return 0;
> > +}
>
> I don't see a start address being setup here, so I assume that CPUs branch to
> a
> fixed address out-of-reset. Does that mean that the kernel has to be loaded at
> a particular physical address on a given platform?
No, not a fixed address. I put it arch/csky/kernel/traps.c:79-83
trap_init()
#ifdef CONFIG_SMP
mtcr("cr<28, 0>", virt_to_phys(vec_base));
VEC_INIT(VEC_RESET, (void *)virt_to_phys(_start_smp_secondary));
#endi
Guo Ren
Re: [PATCH V2 11/19] csky: Atomic operations
On Thu, Jul 05, 2018 at 08:00:08PM +0200, Peter Zijlstra wrote: > On Mon, Jul 02, 2018 at 01:30:14AM +0800, Guo Ren wrote: > > +#ifdef CONFIG_CPU_HAS_LDSTEX > > +ENTRY(csky_cmpxchg) > > + USPTOKSP > > + mfcra3, epc > > + INCTRAP a3 > > + > > + subisp, 8 > > + stw a3, (sp, 0) > > + mfcra3, epsr > > + stw a3, (sp, 4) > > + > > + psrset ee > > +1: > > + ldexa3, (a2) > > + cmpne a0, a3 > > + bt162f > > + mov a3, a1 > > + stexa3, (a2) > > + bez a3, 1b > > +2: > > + sync.is > > + mvc a0 > > + ldw a3, (sp, 0) > > + mtcra3, epc > > + ldw a3, (sp, 4) > > + mtcra3, epsr > > + addisp, 8 > > + KSPTOUSP > > + rte > > +END(csky_cmpxchg) > > +#else > > Please explain... if the CPU has LDEX/STEX, then _why_ do you need this? Our libc use csky_cmpxchg and we want it compatible. Of course, we'll also implement the ldex/stex atomic operations in libs in future. Guo Ren
Re: [PATCH V2 11/19] csky: Atomic operations
On Thu, Jul 05, 2018 at 07:50:59PM +0200, Peter Zijlstra wrote:
> On Mon, Jul 02, 2018 at 01:30:14AM +0800, Guo Ren wrote:
>
> > +#include
> > +
> > +#define __xchg(new, ptr, size) \
> > +({ \
> > + __typeof__(ptr) __ptr = (ptr); \
> > + __typeof__(new) __new = (new); \
> > + __typeof__(*(ptr)) __ret; \
> > + unsigned long tmp; \
> > + switch (size) { \
> > + case 4: \
> > + asm volatile ( \
> > + "1: ldex.w %0, (%3) \n"\
> > + " mov %1, %2 \n"\
> > + " stex.w %1, (%3) \n"\
> > + " bez %1, 1b \n"\
> > + : "=" (__ret), "=" (tmp)\
> > + : "r" (__new), "r"(__ptr) \
> > + : "memory");\
> > + smp_mb(); \
> > + break; \
> > + default:\
> > + BUILD_BUG();\
> > + } \
> > + __ret; \
> > +})
> > +
> > +#define xchg(ptr, x) (__xchg((x), (ptr), sizeof(*(ptr
> > +
> > +#define __cmpxchg(ptr, old, new, size) \
> > +({ \
> > + __typeof__(ptr) __ptr = (ptr); \
> > + __typeof__(new) __new = (new); \
> > + __typeof__(new) __tmp; \
> > + __typeof__(old) __old = (old); \
> > + __typeof__(*(ptr)) __ret; \
> > + switch (size) { \
> > + case 4: \
> > + asm volatile ( \
> > + "1: ldex.w %0, (%3) \n"\
> > + " cmpne %0, %4 \n"\
> > + " bt 2f \n"\
> > + " mov %1, %2 \n"\
> > + " stex.w %1, (%3) \n"\
> > + " bez %1, 1b \n"\
> > + "2: \n"\
> > + : "=" (__ret), "=" (__tmp) \
> > + : "r" (__new), "r"(__ptr), "r"(__old) \
> > + : "memory");\
> > + smp_mb(); \
> > + break; \
> > + default:\
> > + BUILD_BUG();\
> > + } \
> > + __ret; \
> > +})
> > +
> > +#define cmpxchg(ptr, o, n) \
> > + (__cmpxchg((ptr), (o), (n), sizeof(*(ptr
>
> What's the memory ordering rules for your LDEX/STEX ?
Every CPU has a local exclusive monitor.
"Ldex rz, (rx, #off)" will add an entry into the local monitor, and the
entry is composed of a address tag and a exclusive flag (inited with 1).
Any stores (include other cores') will break the exclusive flag to 0 in
the entry which could be indexed by the address tag.
"Stex rz, (rx, #off)" has two condition:
1. Store Success: When the entry's exclusive flag is 1, it will store rz
to the [rx + off] address and the rz will be set to 1.
2. Store Failure: When the entry's exclusive flag is 0, just rz will be
set to 0.
> The mandated semantics for xchg() / cmpxchg() is an effective smp_mb()
> before _and_ after.
switch (size) { \
case 4: \
Re: [PATCH V2 11/19] csky: Atomic operations
On Thu, Jul 05, 2018 at 07:59:02PM +0200, Peter Zijlstra wrote:
> On Mon, Jul 02, 2018 at 01:30:14AM +0800, Guo Ren wrote:
>
> > +static inline void arch_spin_lock(arch_spinlock_t *lock)
> > +{
> > + unsigned int *p = >lock;
> > + unsigned int tmp;
> > +
> > + asm volatile (
> > + "1: ldex.w %0, (%1) \n"
> > + " bnez%0, 1b \n"
> > + " movi%0, 1\n"
> > + " stex.w %0, (%1) \n"
> > + " bez %0, 1b \n"
> > + : "=" (tmp)
> > + : "r"(p)
> > + : "memory");
> > + smp_mb();
> > +}
>
> Test-and-set with MB acting as ACQUIRE, ok.
Em ... Ok, I'll try to use test-and-set function instead of it.
> > +static inline void arch_spin_unlock(arch_spinlock_t *lock)
> > +{
> > + unsigned int *p = >lock;
> > + unsigned int tmp;
> > +
> > + smp_mb();
> > + asm volatile (
> > + "1: ldex.w %0, (%1) \n"
> > + " movi%0, 0\n"
> > + " stex.w %0, (%1) \n"
> > + " bez %0, 1b \n"
> > + : "=" (tmp)
> > + : "r"(p)
> > + : "memory");
> > +}
>
> MB acting for RELEASE, but _why_ are you using a LDEX/STEX to clear the
> lock word? Would not a normal store work?
Normal store is enough, I'll fixup it in next version patch.
> Also, the fact that you need MB for release implies your LDEX does not
> in fact imply anything and your xchg/cmpxchg implementation is broken.
xchg/cmxchg broken without 1th smp_mb()? Why we need protect the
instructions flow before the ldex.w?
> > +static inline int arch_spin_trylock(arch_spinlock_t *lock)
> > +{
> > + unsigned int *p = >lock;
> > + unsigned int tmp;
> > +
> > + asm volatile (
> > + "1: ldex.w %0, (%1) \n"
> > + " bnez%0, 2f \n"
> > + " movi%0, 1\n"
> > + " stex.w %0, (%1) \n"
> > + " bez %0, 1b \n"
> > + " movi%0, 0\n"
> > + "2: \n"
> > + : "=" (tmp)
> > + : "r"(p)
> > + : "memory");
> > + smp_mb();
> > +
> > + return !tmp;
> > +}
>
> Strictly speaking you can avoid the MB on failure. You only need to
> provide ACQUIRE semantics on success.
>
> That said, I would really suggest you implement a ticket lock instead of
> a test-and-set lock. They're not really all that complicated and do
> provide better worst case behaviour.
Ok, I'll try to implement ticket lock in next version patch.
>
>
> > +/** read lock/unlock/trylock **/
>
> Please have a look at using qrwlock -- esp. if you implement a ticket
> lock, then the rwlock comes for 'free'.
Ok, I'll try it.
Guo Ren
Re: [PATCH V2 16/19] csky: SMP support
On Fri, Jul 06, 2018 at 11:39:32AM +0200, Peter Zijlstra wrote: > On Fri, Jul 06, 2018 at 02:07:40PM +0800, Guo Ren wrote: > > > > Please explain those mb()'s... I'm thinking you meant to use smp_mb(). > > Yes, smp_mb(). Current smp_mb()() is the same: sync.is. > > > > In next version patch, I'll seperate smp_mb() and mb() and use ld/st.barrier > > instead of sync.is. Sync.is is expensive that it flush cpu's pipeline. > > I'll second my own call for documentation, because now there's three > memory ordering instructions: > > "SYNC", "SYNC.IS" and "LD/ST.BARRIER" > > None of which have yet been explained. In C-SKY there are: sync:completion barrier sync.s: completion barrier and shareable to other cores sync.i: completion barrier with flush cpu pipeline sync.is: completion barrier with flush cpu pipeline and shareable to other cores bar.brwarw: ordering barrier for all load/store instructions before it bar.brwarws: ordering barrier for all load/store instructions before it and shareable to other cores bar.brar:ordering barrier for all load instructions before it bar.brars: ordering barrier for all load instructions before it and shareable to other cores bar.bwaw:ordering barrier for all store instructions before it bar.bwaws: ordering barrier for all store instructions before it and shareable to other cores
Re: [PATCH V2 11/19] csky: Atomic operations
On Fri, Jul 06, 2018 at 02:05:32PM +0200, Peter Zijlstra wrote: > On Fri, Jul 06, 2018 at 07:48:12PM +0800, Guo Ren wrote: > > On Thu, Jul 05, 2018 at 08:00:08PM +0200, Peter Zijlstra wrote: > > > On Mon, Jul 02, 2018 at 01:30:14AM +0800, Guo Ren wrote: > > > > +#ifdef CONFIG_CPU_HAS_LDSTEX > > > > +ENTRY(csky_cmpxchg) > > > > + USPTOKSP > > > > + mfcra3, epc > > > > + INCTRAP a3 > > > > + > > > > + subisp, 8 > > > > + stw a3, (sp, 0) > > > > + mfcra3, epsr > > > > + stw a3, (sp, 4) > > > > + > > > > + psrset ee > > > > +1: > > > > + ldexa3, (a2) > > > > + cmpne a0, a3 > > > > + bt162f > > > > + mov a3, a1 > > > > + stexa3, (a2) > > > > + bez a3, 1b > > > > +2: > > > > + sync.is > > > > + mvc a0 > > > > + ldw a3, (sp, 0) > > > > + mtcra3, epc > > > > + ldw a3, (sp, 4) > > > > + mtcra3, epsr > > > > + addisp, 8 > > > > + KSPTOUSP > > > > + rte > > > > +END(csky_cmpxchg) > > > > +#else > > > > > > Please explain... if the CPU has LDEX/STEX, then _why_ do you need this? > > Our libc use csky_cmpxchg and we want it compatible. Of course, we'll > > also implement the ldex/stex atomic operations in libs in future. > > I would strongly suggest not providing this syscall on SMP systems from > the get go. There is no point in starting with legacy problems without > an actual legacy. Ok.
Re: [PATCH V2 11/19] csky: Atomic operations
On Fri, Jul 06, 2018 at 02:03:23PM +0200, Peter Zijlstra wrote: > > > Test-and-set with MB acting as ACQUIRE, ok. > > Em ... Ok, I'll try to use test-and-set function instead of it. > > "test-and-set" is just the name of this type of spinlock implementation. > > You _could_ use the linux test_and_set bitop, but those are defined on > unsigned long and spinlock_t is generally assumed to be of unsigned int > size. > > Go with the ticket locks as per below. Ok, I'll learn it. > > Ok, I'll try to implement ticket lock in next version patch. > > If you need inspiration, look at: > arch/arm/include/asm/spinlock.h > > Or look at the current version of that file and ignore the LSE version. > > Note that unlock is a store half-word (u16), not having seen your arch > manual yet I don't know if you even have that. Nice tips, thank you very much. Guo Ren
Re: [PATCH V2 16/19] csky: SMP support
On Fri, Jul 06, 2018 at 12:43:52PM +0100, Mark Rutland wrote:
> Please see the devicetree spec [1], section 2.3.4. Valid values are:
>
> * "okay" // equivalent to no status property present
> * "disabled"
> * "fail"
> * "fail-sss"
Nice tip, thx.
> I'm a bit confused. You write (1 << cpu) into cv<29, 0>, to enable a
> particular CPU, so I assume that bit uniquely identifies a CPU,
Yes, you're right and cr<29, 0>'s bit uniquely identifies a cpu.
> and
> therefore the reg is some unique ID for the CPU.
static int csky_of_cpu(struct device_node *node)
{
const char *status;
if (of_property_read_string(node, "status", ))
status = "okay";
if (strcmp(status, "disabled") == 0)
goto error;
return 1;
error:
return 0;
}
void __init setup_smp(void)
{
struct device_node *node = NULL;
int i = 0;
while ((node = of_find_node_by_type(node, "cpu"))) {
if (!csky_of_cpu(node))
continue;
set_cpu_possible(i, true);
set_cpu_present(i, true);
i++;
}
}
Hmm?
No in next version patch, it's no use.
> I see.
>
> Is this SMP bringup mechanism architectual, or are you likely to need
> another mechanism to turn on CPUs on future chips?
It's the only SMP bringup mechanism architectual for C-SKY SMP. There is
no another way in future and SOC vendor couldn't change it.
> You probably want to use an enable-method property to describe this.
No, thx.
Guo Ren
Re: [PATCH V2 11/19] csky: Atomic operations
On Fri, Jul 06, 2018 at 01:56:14PM +0200, Peter Zijlstra wrote:
> That's how LL/SC works. What I was asking is if they have any effect on
> memory ordering. Some architectures have LL/SC imply memory ordering,
> most do not.
>
> Going by your spinlock implementation they don't imply any memory
> ordering.
ldex/stex don't imply any memory ordering.
>
> > > The mandated semantics for xchg() / cmpxchg() is an effective smp_mb()
> > > before _and_ after.
> >
> > switch (size) { \
> > case 4: \
> > smp_mb(); \
> > asm volatile ( \
> > "1: ldex.w %0, (%3) \n"\
> > " mov %1, %2 \n"\
> > " stex.w %1, (%3) \n"\
> > " bez %1, 1b \n"\
> > : "=" (__ret), "=" (tmp)\
> > : "r" (__new), "r"(__ptr) \
> > : "memory");\
> > smp_mb(); \
> > break; \
> > Hmm?
> > But I couldn't undertand what's wrong without the 1th smp_mb()?
> > 1th smp_mb will make all ld/st finish before ldex.w. Is it necessary?
>
> Yes.
>
> CPU0CPU1
>
> r1 = READ_ONCE(x); WRITE_ONCE(y, 1);
> r2 = xchg(, 2); smp_store_release(, 1);
>
> must not allow: r1==1 && r2==0
CPU1 smp_store_release could be finished before WRITE_ONCE, so r1=1 &&
r2=0?
> > > The above implementation suggests LDEX implies a SYNC.IS, is this
> > > correct?
> > No, ldex doesn't imply a sync.is.
>
> Right, as per the spinlock emails, then your proposed primitives are
> incorrect.
Yes, approve.
Guo Ren
Re: [PATCH V2 11/19] csky: Atomic operations
On Fri, Jul 06, 2018 at 02:17:16PM +0200, Peter Zijlstra wrote: > > > > CPU0CPU1 > > > > r1 = READ_ONCE(x); WRITE_ONCE(y, 1); > > r2 = xchg(, 2); smp_store_release(, 1); > > > > must not allow: r1==1 && r2==0 > > Also, since you said "SYNC.IS" is a pipeline flush, those > instruction-sync primitives normally do not imply a store-buffer flush, > does yours? If not it is not a valid smp_mb() implementation. Sync.is will flush pipeline and store-buffer. "sync" means completion memory barrier. "i" means flush cpu pipeline. "s" means sharable to other cpus. > > Notably: > > CPU0CPU1 > > WRITE_ONCE(x, 1); WRITE_ONCE(y, 1); > smp_mb(); smp_mb(); > r0 = READ_ONCE(y); r1 = READ_ONCE(x); > > must not allow: r0==0 && r1==0 > > Which would be possible with a regular instruction-sync barrier, but > must absolutely not be true with a full memory barrier. > > (and you can replace the smp_mb(); r = READ_ONCE(); with r = xchg() to > again see why you need that first smp_mb()). CPU0CPU1 WRITE_ONCE(x, 1)WRITE_ONCE(y, 1) r0 = xchg(, 2)r1 = xchg(, 2) must not allow: r0==0 && r1==0 So we must add a smp_mb between WRITE_ONCE() and xchg(), right? Guo Ren
Re: [PATCH V2 16/19] csky: SMP support
On Fri, Jul 06, 2018 at 05:21:00PM +0100, Mark Rutland wrote:
> Please don't open-code this. Use of_device_is_available(), which checks
> the status property itself. e.g.
>
> void __init setup_smp(void)
> {
> struct device_node *node = NULL;
>
> while ((node = of_find_node_by_type(node, "cpu"))) {
> if (!of_device_is_available(node))
> continue;
>
> ...
> }
> }
Ok, approve.
> Please use the reg property, you need it to describe which particular
> CPUs are available.
>
> You probably also want a mapping from Linux logical CPU id to your
> physical CPU id, and a sanity check on this. See arm64 for an example.
Yes, you are right. Reg property could determine which bit of CPU in
cr<0, 29> could be booted.
Thx for the tips.
Guo Ren
Re: [PATCH V2 06/19] csky: Cache and TLB routines
On Thu, Jul 05, 2018 at 07:40:25PM +0200, Peter Zijlstra wrote:
> > +#ifdef CONFIG_SMP
> > +#define mb() asm volatile ("sync.is":::"memory")
> > +#else
> > +#define mb() asm volatile ("sync":::"memory")
> > +#endif
>
> This is very suspect, please elaborate.
>
> What I would've expected is:
>
> #define mb() asm volatile ("sync" ::: "memory")
>
> #ifdef CONFIG_SMP
> #define __smp_mb() asm volatile ("sync.is" ::: "memory")
> #endif
>
> Is that in fact what you meant?
>
> Do you have a reference to your architecture manual and memory model
> description somewhere?
I'll fixup it in next version patch.
Re: [PATCH V2 18/19] clocksource: add C-SKY clocksource drivers
On Thu, Jul 05, 2018 at 11:23:36AM +0200, Daniel Lezcano wrote: > > So I still need "for_each_cpu(cpu, cpu_possible_mask)" to init every > > csky_to ... > > That is what is unclear for me. percpu or IRQF_PERCPU ? IRQF_PERCPU > Have a look at the commit 9995f4f184613fb02ee73092b03545520a72b104, > changelog and the comment in the init function. > > Can you give a similar description for this timer ? Ok, thx for the tip. > > #define STATUS_CLR BIT(0) > > > > #define CONTRL_RST BIT(0) > > #define CONTRL_STARTBIT(1) > > > > #define CONFIG_EN BIT(0) > > #define CONFIG_IRQ_EN BIT(1) > > NATCHIP_STATUS_CLR > NATCHIP_CONTROL_RST > NATCHIP_CONTROL_START > > NATCHIP_CONFIG_EN > NATCHIP_CONFIG_IRQ_EN Ok > >>> + .rating = 300, > >>> + .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC | > >>> + CLOCK_EVT_FEAT_ONESHOT, > >>> + .set_state_shutdown = nc_timer_shutdown, > >>> + .set_state_periodic = nc_timer_set_periodic, > >>> + .set_next_event = nc_timer_set_next_event, > >> > >> set_oneshot ? > > Yes oneshort, but also could support periodic. But in fact, it only > > works with oneshort. > > In the flags, it is specified periodic and oneshot but only the > set_periodic ops is set. Got it, add set_oneshot. > > Thx, I'll modify it like this: > > div = (timer_of_rate() / TIMER_FREQ) - 1; > > I wanted to be sure it wasn't the latter. In this case, you don't need > parenthesis, so just add the spaces around the '/' operator. Ok Guo Ren
