[PATCH 3/3] spi: spi-xilinx: Add run run-time endian detection
Do not load endian value from platform data
and rather autodetect it.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/mfd/timberdale.c | 1 -
drivers/spi/spi-xilinx.c | 29 +
include/linux/spi/xilinx_spi.h | 1 -
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/mfd/timberdale.c b/drivers/mfd/timberdale.c
index 59e0ee2..0c1fcbc 100644
--- a/drivers/mfd/timberdale.c
+++ b/drivers/mfd/timberdale.c
@@ -145,7 +145,6 @@ static struct spi_board_info
timberdale_spi_8bit_board_info[] = {
static struct xspi_platform_data timberdale_xspi_platform_data = {
.num_chipselect = 3,
- .little_endian = true,
/* bits per word and devices will be filled in runtime depending
* on the HW config
*/
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index d690756..0b7b8d7 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -30,6 +30,7 @@
*/
#define XSPI_CR_OFFSET 0x60/* Control Register */
+#define XSPI_CR_LOOP 0x01
#define XSPI_CR_ENABLE 0x02
#define XSPI_CR_MASTER_MODE0x04
#define XSPI_CR_CPOL 0x08
@@ -355,11 +356,12 @@ static const struct of_device_id xilinx_spi_of_match[] = {
MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
- u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word)
+ u32 irq, s16 bus_num, int num_cs, int bits_per_word)
{
struct spi_master *master;
struct xilinx_spi *xspi;
int ret;
+ u32 tmp;
master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
if (!master)
@@ -395,13 +397,25 @@ struct spi_master *xilinx_spi_init(struct device *dev,
struct resource *mem,
xspi-mem = *mem;
xspi-irq = irq;
- if (little_endian) {
- xspi-read_fn = xspi_read32;
- xspi-write_fn = xspi_write32;
- } else {
+
+ /*
+* Detect endianess on the IP via loop bit in CR. Detection
+* must be done before reset is sent because incorrect reset
+* value generates error interrupt.
+* Setup little endian helper functions first and try to use them
+* and check if bit was correctly setup or not.
+*/
+ xspi-read_fn = xspi_read32;
+ xspi-write_fn = xspi_write32;
+
+ xspi-write_fn(XSPI_CR_LOOP, xspi-regs + XSPI_CR_OFFSET);
+ tmp = xspi-read_fn(xspi-regs + XSPI_CR_OFFSET);
+ tmp = XSPI_CR_LOOP;
+ if (tmp != XSPI_CR_LOOP) {
xspi-read_fn = xspi_read32_be;
xspi-write_fn = xspi_write32_be;
}
+
xspi-bits_per_word = bits_per_word;
if (xspi-bits_per_word == 8) {
xspi-tx_fn = xspi_tx8;
@@ -465,14 +479,13 @@ static int xilinx_spi_probe(struct platform_device *dev)
{
struct xspi_platform_data *pdata;
struct resource *r;
- int irq, num_cs = 0, little_endian = 0, bits_per_word = 8;
+ int irq, num_cs = 0, bits_per_word = 8;
struct spi_master *master;
u8 i;
pdata = dev-dev.platform_data;
if (pdata) {
num_cs = pdata-num_chipselect;
- little_endian = pdata-little_endian;
bits_per_word = pdata-bits_per_word;
}
@@ -504,7 +517,7 @@ static int xilinx_spi_probe(struct platform_device *dev)
return -ENXIO;
master = xilinx_spi_init(dev-dev, r, irq, dev-id, num_cs,
-little_endian, bits_per_word);
+bits_per_word);
if (!master)
return -ENODEV;
diff --git a/include/linux/spi/xilinx_spi.h b/include/linux/spi/xilinx_spi.h
index 6f17278..333ecdf 100644
--- a/include/linux/spi/xilinx_spi.h
+++ b/include/linux/spi/xilinx_spi.h
@@ -11,7 +11,6 @@
*/
struct xspi_platform_data {
u16 num_chipselect;
- bool little_endian;
u8 bits_per_word;
struct spi_board_info *devices;
u8 num_devices;
--
1.8.2.3
pgp4zx6GvmF9b.pgp
Description: PGP signature
[PATCH 2/3] spi: spi-xilinx: Clear dma_mask for xilinx spi controller
From: Michal Simek mon...@monstr.eu mmc_spi driver tests if dma is available through spi-master-dev.parent-dma_mask. Microblaze supports DMA but xilinx_spi IP doesn't. That's why clear dma_mask in the driver. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/spi/spi-xilinx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index 34d18dc..d690756 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c @@ -365,6 +365,9 @@ struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem, if (!master) return NULL; + /* clear the dma_mask, to try to disable use of dma */ + master-dev.dma_mask = 0; + /* the spi-mode bits understood by this driver: */ master-mode_bits = SPI_CPOL | SPI_CPHA; -- 1.8.2.3 pgptNwupE2hBG.pgp Description: PGP signature
[PATCH 1/3] spi: spi-xilinx: Remove ISR race condition
From: Peter Crosthwaite peter.crosthwa...@petalogix.com
The ISR currently consumes the rx buffer data and re-enables transmission
from within interrupt context. This is bad because if the interrupt
occurs again before the ISR exits, the new interrupt will be erroneously
cleared by the still completing ISR.
Simplified the ISR by just setting the completion variable and exiting with
no action. Then just looped the transmit functionality in
xilinx_spi_txrx_bufs().
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/spi/spi-xilinx.c | 74 +++-
1 file changed, 35 insertions(+), 39 deletions(-)
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index e1d7696..34d18dc 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -267,7 +267,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi,
struct spi_transfer *t)
{
struct xilinx_spi *xspi = spi_master_get_devdata(spi-master);
u32 ipif_ier;
- u16 cr;
/* We get here with transmitter inhibited */
@@ -276,7 +275,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi,
struct spi_transfer *t)
xspi-remaining_bytes = t-len;
INIT_COMPLETION(xspi-done);
- xilinx_spi_fill_tx_fifo(xspi);
/* Enable the transmit empty interrupt, which we use to determine
* progress on the transmission.
@@ -285,12 +283,41 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi,
struct spi_transfer *t)
xspi-write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
xspi-regs + XIPIF_V123B_IIER_OFFSET);
- /* Start the transfer by not inhibiting the transmitter any longer */
- cr = xspi-read_fn(xspi-regs + XSPI_CR_OFFSET)
- ~XSPI_CR_TRANS_INHIBIT;
- xspi-write_fn(cr, xspi-regs + XSPI_CR_OFFSET);
+ for (;;) {
+ u16 cr;
+ u8 sr;
+
+ xilinx_spi_fill_tx_fifo(xspi);
+
+ /* Start the transfer by not inhibiting the transmitter any
+* longer
+*/
+ cr = xspi-read_fn(xspi-regs + XSPI_CR_OFFSET)
+ ~XSPI_CR_TRANS_INHIBIT;
+ xspi-write_fn(cr, xspi-regs + XSPI_CR_OFFSET);
+
+ wait_for_completion(xspi-done);
+
+ /* A transmit has just completed. Process received data and
+* check for more data to transmit. Always inhibit the
+* transmitter while the Isr refills the transmit register/FIFO,
+* or make sure it is stopped if we're done.
+*/
+ cr = xspi-read_fn(xspi-regs + XSPI_CR_OFFSET);
+ xspi-write_fn(cr | XSPI_CR_TRANS_INHIBIT,
+ xspi-regs + XSPI_CR_OFFSET);
+
+ /* Read out all the data from the Rx FIFO */
+ sr = xspi-read_fn(xspi-regs + XSPI_SR_OFFSET);
+ while ((sr XSPI_SR_RX_EMPTY_MASK) == 0) {
+ xspi-rx_fn(xspi);
+ sr = xspi-read_fn(xspi-regs + XSPI_SR_OFFSET);
+ }
- wait_for_completion(xspi-done);
+ /* See if there is more data to send */
+ if (!xspi-remaining_bytes 0)
+ break;
+ }
/* Disable the transmit empty interrupt */
xspi-write_fn(ipif_ier, xspi-regs + XIPIF_V123B_IIER_OFFSET);
@@ -314,38 +341,7 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
xspi-write_fn(ipif_isr, xspi-regs + XIPIF_V123B_IISR_OFFSET);
if (ipif_isr XSPI_INTR_TX_EMPTY) {/* Transmission completed */
- u16 cr;
- u8 sr;
-
- /* A transmit has just completed. Process received data and
-* check for more data to transmit. Always inhibit the
-* transmitter while the Isr refills the transmit register/FIFO,
-* or make sure it is stopped if we're done.
-*/
- cr = xspi-read_fn(xspi-regs + XSPI_CR_OFFSET);
- xspi-write_fn(cr | XSPI_CR_TRANS_INHIBIT,
- xspi-regs + XSPI_CR_OFFSET);
-
- /* Read out all the data from the Rx FIFO */
- sr = xspi-read_fn(xspi-regs + XSPI_SR_OFFSET);
- while ((sr XSPI_SR_RX_EMPTY_MASK) == 0) {
- xspi-rx_fn(xspi);
- sr = xspi-read_fn(xspi-regs + XSPI_SR_OFFSET);
- }
-
- /* See if there is more data to send */
- if (xspi-remaining_bytes 0) {
- xilinx_spi_fill_tx_fifo(xspi);
- /* Start the transfer by not inhibiting the
-* transmitter any longer
-*/
- xspi-write_fn(cr, xspi-regs + XSPI_CR_OFFSET);
- } else
Re: [PATCH 2/3] spi: spi-xilinx: Clear dma_mask for xilinx spi controller
On 06/04/2013 07:36 PM, Mark Brown wrote: On Tue, Jun 04, 2013 at 04:02:35PM +0200, Michal Simek wrote: From: Michal Simek mon...@monstr.eu mmc_spi driver tests if dma is available through spi-master-dev.parent-dma_mask. Microblaze supports DMA but xilinx_spi IP doesn't. That's why clear dma_mask in the driver. +/* clear the dma_mask, to try to disable use of dma */ +master-dev.dma_mask = 0; + This looks like a bodge in the wrong place. Either the device registration is incorrect in that it advertises DMA when none is available or the SPI driver ought to be offering the MMC driver a more sensible way of advertising this limitation. My first thought is the former but I didn't check where dma_mask is getting set. I have looked at history of this change and we have done it 3 years ago based on one custom configuration. It is shame that I don't have hw to test this but there was something wrong in connection to mmc_spi.c. I will try to find out hw for this to test but probably won't be available. :-( And I will just revert this change in my tree. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH] audit: Fix decimal constant description
Hi guys,
any comment on this?
Geert: I fixes one warning reported in your regression log.
Thanks,
Michal
On 05/23/2013 08:03 AM, Michal Simek wrote:
Use proper decimal type for comparison with u32.
Compilation warning was introduced by:
audit: Make testing for a valid loginuid explicit.
(sha1: 780a7654cee8d61819512385e778e4827db4bfbc)
Warning:
kernel/auditfilter.c: In function 'audit_data_to_entry':
kernel/auditfilter.c:426:3: warning: this decimal constant
is unsigned only in ISO C90 [enabled by default]
if ((f-type == AUDIT_LOGINUID) (f-val == 4294967295)) {
Signed-off-by: Michal Simek michal.si...@xilinx.com
CC: Al Viro v...@zeniv.linux.org.uk
CC: Eric Paris epa...@redhat.com
---
kernel/auditfilter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/auditfilter.c b/kernel/auditfilter.c
index 83a2970..cfa1f73 100644
--- a/kernel/auditfilter.c
+++ b/kernel/auditfilter.c
@@ -423,7 +423,7 @@ static struct audit_entry *audit_data_to_entry(struct
audit_rule_data *data,
f-lsm_rule = NULL;
/* Support legacy tests for a valid loginuid */
- if ((f-type == AUDIT_LOGINUID) (f-val == 4294967295)) {
+ if ((f-type == AUDIT_LOGINUID) (f-val == ~0U)) {
f-type = AUDIT_LOGINUID_SET;
f-val = 0;
}
--
1.8.2.3
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Description: OpenPGP digital signature
Re: [PATCH] of: Export of_irq_count for using in modules
On 06/06/2013 10:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 18:45 Fri 31 May , Michal Simek wrote:
On 05/31/2013 05:16 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:57 Fri 31 May , Michal Simek wrote:
On 05/31/2013 01:00 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 10:14 Fri 31 May , Michal Simek wrote:
Hi Jean-Christophe,
On 05/30/2013 10:17 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:49 Thu 30 May , Michal Simek wrote:
Export of_irq_count for modules.
can you explain why do you need to call of_irq_count
I need to count number of irq written in the DTS node.
It is not fixed size that's why I need to proper way how to
find it out.
I am using this loop.
count = of_irq_count(pdev-dev.of_node);
/* Alloc IRQ based on DTS to be sure that no other driver will use it */
while (count--) {
tmp-irq = irq_of_parse_and_map(pdev-dev.of_node, count);
dev_info(pdev-dev, %d: Alloc irq: %d\n, count, tmp-irq);
ret = request_irq(tmp-irq, zynq_remoteproc_interrupt, 0,
dev_name(pdev-dev), pdev-dev);
if (ret) {
...
}
}
But of course if you think that this is incorrect to export it
I can use what it is in of_irq_count body
368 int of_irq_count(struct device_node *dev)
369 {
370 int nr = 0;
371
372 while (of_irq_to_resource(dev, nr, NULL))
373 nr++;
374
375 return nr;
376 }
Because of_irq_to_resource is exported for modules.
Or is there any better way how to loop over all interrupts in DT node?
can just explain me why you need to call irq_of_parse_and_map in your
driver?
as the irq will be provided in the resources normally
It is quite a long time I have written this driver on v3.1 or 3.3.
But is this better?
struct resource *res;
int i = 0;
do {
res = platform_get_resource(pdev, IORESOURCE_IRQ, i++);
if (res)
do something
} while(res);
Also what about of_irq_to_resource()? Is it deprecated and all drivers
shouldn't use it?
I have no problem to rewrite the driver to use platform_get_resource.
yeah it's better but be aware there is a but in DT that I'm working on to
fix
if you use irq that are registered by a pdev this will not work
I hope to fix it for 3.11
and already send an RFC that fix it
ok. good to know. Btw: Let's return to my origin point why not to
export of_irq_count for modules?
Or opposite question if platform_get_resource is correct way
why to export of_irq_to_resource for modules?
for old ppc drivers that are not converted yet to pdev
if you can do so just use pdev resource I should have fix the pb or irq_domain
hopefully for 3.11
ok. It means it is currently deprecated.
I just wanted to be sure that I understand it correctly.
I have changed my drivers not to use this function and using resources as
we discussed.
btw: I have sent one email to device-tree ML about describing missing
connection between cpu and the first interrupt controller.
Can you please look at it and comment it?
https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-May/033955.html
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [PATCH] of: Export of_irq_count for using in modules
On 06/06/2013 01:55 PM, Grant Likely wrote: On Thu, Jun 6, 2013 at 9:39 AM, Michal Simek mon...@monstr.eu wrote: On 06/06/2013 10:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote: On 18:45 Fri 31 May , Michal Simek wrote: ok. good to know. Btw: Let's return to my origin point why not to export of_irq_count for modules? Or opposite question if platform_get_resource is correct way why to export of_irq_to_resource for modules? for old ppc drivers that are not converted yet to pdev if you can do so just use pdev resource I should have fix the pb or irq_domain hopefully for 3.11 ok. It means it is currently deprecated. I just wanted to be sure that I understand it correctly. It's deprecated for platform_devices, but should still be used for other bus types that don't provide the device driver with a list of irqs. For platform devices it is best to use the platform_bus irq table since that is portable regardless of how the device is instantiated. As for not exporting of_irq_count(), I don't have a problem with it, but only if there is a user. It sounds like with the rework you discussed with Jean-Christophe that it is no longer the case. We have talked about out of tree driver anyway because it targets arm-arm remoteproc AMP which is not in mainline yet. I have changed my drivers and using resource tables. Interesting thing was that long interrupt list is translated to resource table entry per cell and res-end is not used to cover bigger ranges. interrupts = 0 29 0 0 30 0 0 31 0 0 32 0 0 33 0 0 34 0 0 35 0 0 36 0 0 52 0 0 53 0 0 54 0 0 55 0 0 56 0 0 57 0 0 58 0 0 59 0 0 37 0 0 38 0 0 39 0; BTW: can you please look at my microblaze email around interrupt handlers? Thanks, Michal -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 6/6] DT: Add documentation for gpio-xilinx
Hi Linus, On 06/17/2013 11:13 AM, Linus Walleij wrote: On Mon, Jun 17, 2013 at 8:21 AM, Michal Simek mon...@monstr.eu wrote: On 06/17/2013 07:50 AM, Linus Walleij wrote: On Mon, Jun 3, 2013 at 2:31 PM, Michal Simek michal.si...@xilinx.com wrote: +- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode +- xlnx,is-dual : if 1, controller also uses the second channel If is present, xlnx,is-dual; + xlnx,is-dual = 0x1; xlnx,is-dual; I'm not giving up on this suggestion. I have commented this in the v1. I commented your comment on v1, and said I think you can support both bindings. in 2/6 you have applied that dual support for this driver and that's why please add this binding description to your repo because it reflects actual binding for this driver. As I wrote you I am working on interrupt support for this IP and in connection to this I will introduce new binding as we discussed in v1. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH] microblaze: Don't mark arch_kgdb_ops as const.
Hi Graeme,
On 06/23/2013 11:16 PM, Graeme Smecher wrote:
Hi Michal,
On 08/06/13 01:58 PM, Graeme Smecher wrote:
Hi all,
On 08/06/13 09:52 AM, Graeme Smecher wrote:
Other architectures don't do it, and it conflicts with the extern'd
definition
in include/linux/kgdb.h.
Signed-off-by: Graeme Smechergsmec...@threespeedlogic.com
CC: Michal Simekmon...@monstr.eu
CC:linux-kernel@vger.kernel.org
---
arch/microblaze/kernel/kgdb.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/microblaze/kernel/kgdb.c b/arch/microblaze/kernel/kgdb.c
index 8adc9244..09a5e82 100644
--- a/arch/microblaze/kernel/kgdb.c
+++ b/arch/microblaze/kernel/kgdb.c
@@ -141,7 +141,7 @@ void kgdb_arch_exit(void)
/*
* Global data
*/
-const struct kgdb_arch arch_kgdb_ops = {
+struct kgdb_arch arch_kgdb_ops = {
#ifdef __MICROBLAZEEL__
.gdb_bpt_instr = {0x18, 0x00, 0x0c, 0xba}, /* brki r16, 0x18 */
#else
It's worth noting that this patch is flagged by checkpatch:
WARNING: struct kgdb_arch should normally be const
#25: FILE: arch/microblaze/kernel/kgdb.c:144:
+struct kgdb_arch arch_kgdb_ops = {
total: 0 errors, 1 warnings, 8 lines checked
However, without it, my kernel fails to compile:
CC arch/microblaze/kernel/kgdb.o
arch/microblaze/kernel/kgdb.c:144:24: error: conflicting type
qualifiers for 'arch_kgdb_ops'
include/linux/kgdb.h:284:26: note: previous declaration of
'arch_kgdb_ops' was here
make[1]: *** [arch/microblaze/kernel/kgdb.o] Error 1
make: *** [arch/microblaze/kernel] Error 2
The checkpatch test was a response to this (rejected) patch series:
http://lkml.indiana.edu/hypermail/linux/kernel/0912.1/02659.html
I'm the lucky victim, here, since I'm using gcc 4.6.4 (which notices the
conflicting qualifiers), while other Microblaze users are still working with
gcc 4.1.2 (which didn't care.) All other architectures (including mn10300,
arc, and hexagon, which were accepted after the checkpatch commit) ignore
the checkpatch rule and declare arch_kgdb_ops non-const.
In any case, I wanted to point out (a) that the patch fails checkpatch, (b)
that I'm submitting it anyway, and (c) that I'm utterly ambivalent about how
the struct is declared, provided I can compile working kernels on Microblaze.
Can you give me an update on including this patch in linux-2.6-microblaze? I
realize the const was added as a result of a checkpatch.pl complaint (see
6bd55f0bbaebb79b39e147aa864401fd0c94db82), but it seems like a non-compiling
kernel (even for trivial reasons) is worse than a noisy Perl script.
Sorry for delay.
Yes, you are right. I will extend description to connect it with that cleanup
patch
and will also create follow up to enable kgdb in defconfig to be sure that it
is tested regularly.
Applied.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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[PATCH v3 1/2] uio: Use of_match_ptr() macro in uio_pdrv_genirq.c
This eliminates having an #ifdef returning NULL for the case
when OF is disabled.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- Rebased on Pavel's UIO patch
UIO: allow binding uio_pdrv_genirq.c to devices using command line option
(sha1: 05c3e0bb5629b897b0459e4bfb1b93d729033b99)
Changes in v2:
- s/Use Use/Use/ from patch subject
drivers/uio/uio_pdrv_genirq.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/uio/uio_pdrv_genirq.c b/drivers/uio/uio_pdrv_genirq.c
index bcd72f3..ad77450 100644
--- a/drivers/uio/uio_pdrv_genirq.c
+++ b/drivers/uio/uio_pdrv_genirq.c
@@ -274,8 +274,6 @@ MODULE_DEVICE_TABLE(of, uio_of_genirq_match);
module_param_string(of_id, uio_of_genirq_match[0].compatible, 128, 0);
MODULE_PARM_DESC(of_id, Openfirmware id of the device to be handled by uio);
-#else
-# define uio_of_genirq_match NULL
#endif
static struct platform_driver uio_pdrv_genirq = {
@@ -285,7 +283,7 @@ static struct platform_driver uio_pdrv_genirq = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.pm = uio_pdrv_genirq_dev_pm_ops,
- .of_match_table = uio_of_genirq_match,
+ .of_match_table = of_match_ptr(uio_of_genirq_match),
},
};
--
1.8.2.3
pgpEPrVYSczbw.pgp
Description: PGP signature
[PATCH v3 2/2] uio: Remove uio_pdrv and use uio_pdrv_genirq instead
The patch UIO: fix uio_pdrv_genirq with device tree but no interrupt
(sha1: e3a3c3a205554e564751cd9c0276b2af813d7a92)
add support to use this driver with no interrupts.
uio_pdrv_genirq also supports device-tree binding
which is not available in uio_pdrv.
That's why this uio_pdrv driver can be just removed.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- Rebased on the latest char-misc with some UIO patches
- Change patch description
Changes in v2: None
drivers/uio/Kconfig| 7 ---
drivers/uio/Makefile | 1 -
drivers/uio/uio_pdrv.c | 113 -
3 files changed, 121 deletions(-)
delete mode 100644 drivers/uio/uio_pdrv.c
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index 5295be0..a81d163 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -23,13 +23,6 @@ config UIO_CIF
To compile this driver as a module, choose M here: the module
will be called uio_cif.
-config UIO_PDRV
- tristate Userspace I/O platform driver
- help
- Generic platform driver for Userspace I/O devices.
-
- If you don't know what to do here, say N.
-
config UIO_PDRV_GENIRQ
tristate Userspace I/O platform driver with generic IRQ handling
help
diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
index b354c53..ea015a2 100644
--- a/drivers/uio/Makefile
+++ b/drivers/uio/Makefile
@@ -1,6 +1,5 @@
obj-$(CONFIG_UIO) += uio.o
obj-$(CONFIG_UIO_CIF) += uio_cif.o
-obj-$(CONFIG_UIO_PDRV) += uio_pdrv.o
obj-$(CONFIG_UIO_PDRV_GENIRQ) += uio_pdrv_genirq.o
obj-$(CONFIG_UIO_DMEM_GENIRQ) += uio_dmem_genirq.o
obj-$(CONFIG_UIO_AEC) += uio_aec.o
diff --git a/drivers/uio/uio_pdrv.c b/drivers/uio/uio_pdrv.c
deleted file mode 100644
index 39be9e0..000
--- a/drivers/uio/uio_pdrv.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * drivers/uio/uio_pdrv.c
- *
- * Copyright (C) 2008 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include linux/platform_device.h
-#include linux/uio_driver.h
-#include linux/stringify.h
-#include linux/module.h
-#include linux/slab.h
-
-#define DRIVER_NAME uio_pdrv
-
-struct uio_platdata {
- struct uio_info *uioinfo;
-};
-
-static int uio_pdrv_probe(struct platform_device *pdev)
-{
- struct uio_info *uioinfo = pdev-dev.platform_data;
- struct uio_platdata *pdata;
- struct uio_mem *uiomem;
- int ret = -ENODEV;
- int i;
-
- if (!uioinfo || !uioinfo-name || !uioinfo-version) {
- dev_dbg(pdev-dev, %s: err_uioinfo\n, __func__);
- goto err_uioinfo;
- }
-
- pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
- if (!pdata) {
- ret = -ENOMEM;
- dev_dbg(pdev-dev, %s: err_alloc_pdata\n, __func__);
- goto err_alloc_pdata;
- }
-
- pdata-uioinfo = uioinfo;
-
- uiomem = uioinfo-mem[0];
-
- for (i = 0; i pdev-num_resources; ++i) {
- struct resource *r = pdev-resource[i];
-
- if (r-flags != IORESOURCE_MEM)
- continue;
-
- if (uiomem = uioinfo-mem[MAX_UIO_MAPS]) {
- dev_warn(pdev-dev, device has more than
- __stringify(MAX_UIO_MAPS)
-I/O memory resources.\n);
- break;
- }
-
- uiomem-memtype = UIO_MEM_PHYS;
- uiomem-addr = r-start;
- uiomem-size = resource_size(r);
- uiomem-name = r-name;
- ++uiomem;
- }
-
- while (uiomem uioinfo-mem[MAX_UIO_MAPS]) {
- uiomem-size = 0;
- ++uiomem;
- }
-
- pdata-uioinfo-priv = pdata;
-
- ret = uio_register_device(pdev-dev, pdata-uioinfo);
-
- if (ret) {
- kfree(pdata);
-err_alloc_pdata:
-err_uioinfo:
- return ret;
- }
-
- platform_set_drvdata(pdev, pdata);
-
- return 0;
-}
-
-static int uio_pdrv_remove(struct platform_device *pdev)
-{
- struct uio_platdata *pdata = platform_get_drvdata(pdev);
-
- uio_unregister_device(pdata-uioinfo);
-
- kfree(pdata);
-
- return 0;
-}
-
-static struct platform_driver uio_pdrv = {
- .probe = uio_pdrv_probe,
- .remove = uio_pdrv_remove,
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-module_platform_driver(uio_pdrv);
-
-MODULE_AUTHOR(Uwe Kleine-Koenig);
-MODULE_DESCRIPTION(Userspace I/O platform driver);
-MODULE_LICENSE(GPL v2);
-MODULE_ALIAS(platform: DRIVER_NAME);
--
1.8.2.3
pgp88Re9XrdU3.pgp
Description: PGP signature
Re: [PATCH] clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes
On 06/24/2013 05:58 PM, Sören Brinkmann wrote: ping? On Mon, Jun 17, 2013 at 03:47:40PM -0700, Soren Brinkmann wrote: Zynq's Ethernet clocks are created by the following hierarchy: mux0 --- div0 --- div1 --- mux1 --- gate Rate change requests on the gate have to propagate all the way up to div0 to properly leverage all dividers. Mux1 was missing the CLK_SET_RATE_PARENT flag, which is required to achieve this. Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com --- drivers/clk/zynq/clkc.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 515a573..089d3e3 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -365,8 +365,9 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, gem0clk_lock); -clk = clk_register_mux(NULL, gem0_emio_mux, gem0_mux_parents, 2, 0, -SLCR_GEM0_CLK_CTRL, 6, 1, 0, gem0clk_lock); +clk = clk_register_mux(NULL, gem0_emio_mux, gem0_mux_parents, 2, +CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0, +gem0clk_lock); clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], gem0_emio_mux, CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 0, 0, gem0clk_lock); @@ -387,8 +388,9 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, gem1clk_lock); -clk = clk_register_mux(NULL, gem1_emio_mux, gem1_mux_parents, 2, 0, -SLCR_GEM1_CLK_CTRL, 6, 1, 0, gem1clk_lock); +clk = clk_register_mux(NULL, gem1_emio_mux, gem1_mux_parents, 2, +CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0, +gem1clk_lock); clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], gem1_emio_mux, CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 0, 0, gem1clk_lock); -- 1.8.3.1 Applied. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH] clk/zynq/clkc: Add dedicated spinlock for the SWDT
On 06/24/2013 05:58 PM, Sören Brinkmann wrote: ping? On Mon, Jun 17, 2013 at 03:03:46PM -0700, Soren Brinkmann wrote: The clk_mux for the system watchdog timer reused the register lock dedicated to the Ethernet module - for no apparent reason. Add a lock dedicated to the SWDT's clock register to remove this wrong dependency. Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com --- I don't know how this slipped in... Anyway, the fix depends on armsoc/zynq/clk. Sören drivers/clk/zynq/clkc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 5c205b6..515a573 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(armpll_lock); static DEFINE_SPINLOCK(ddrpll_lock); static DEFINE_SPINLOCK(iopll_lock); static DEFINE_SPINLOCK(armclk_lock); +static DEFINE_SPINLOCK(swdtclk_lock); static DEFINE_SPINLOCK(ddrclk_lock); static DEFINE_SPINLOCK(dciclk_lock); static DEFINE_SPINLOCK(gem0clk_lock); @@ -293,7 +294,7 @@ static void __init zynq_clk_setup(struct device_node *np) } clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, -SLCR_SWDT_CLK_SEL, 0, 1, 0, gem0clk_lock); +SLCR_SWDT_CLK_SEL, 0, 1, 0, swdtclk_lock); /* DDR clocks */ clk = clk_register_divider(NULL, ddr2x_div, ddrpll, 0, -- 1.8.3.1 Applied. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v4 0/7] xilinxfb changes
On 06/17/2013 11:07 PM, Arnd Bergmann wrote: On Monday 17 June 2013, Michal Simek wrote: On 06/17/2013 10:56 AM, Jean-Christophe PLAGNIOL-VILLARD wrote: On 07:23 Mon 17 Jun , Michal Simek wrote: On 06/06/2013 06:23 PM, Jean-Christophe PLAGNIOL-VILLARD wrote: On 12:13 Mon 03 Jun , Michal Simek wrote: Hi, Arnd can you take look on it again please I'll take a look on it next week Any update on this? look ok but I want the Ack from Arnd Sorry for the delay, everything looks good to me. Acked-by: Arnd Bergmann a...@arndb.de Jean-Christophe: Will you apply this series? Or should I take it through my microblaze tree? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v3 1/2] uio: Use of_match_ptr() macro in uio_pdrv_genirq.c
On 06/26/2013 12:00 PM, Sachin Kamat wrote: On 26 June 2013 15:22, Michal Simek michal.si...@xilinx.com wrote: This eliminates having an #ifdef returning NULL for the case when OF is disabled. Signed-off-by: Michal Simek michal.si...@xilinx.com I have already submitted a similar patch for doing this: https://lkml.org/lkml/2013/3/14/169 Ok. I don't care about it. Greg: Can you please add any of this patch to your char-misc tree? For Sachin patch. Acked-by: Michal Simek mon...@monstr.eu Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v3 1/2] uio: Use of_match_ptr() macro in uio_pdrv_genirq.c
On 06/26/2013 12:51 PM, Sachin Kamat wrote: On 26 June 2013 15:51, Michal Simek mon...@monstr.eu wrote: On 06/26/2013 12:00 PM, Sachin Kamat wrote: On 26 June 2013 15:22, Michal Simek michal.si...@xilinx.com wrote: This eliminates having an #ifdef returning NULL for the case when OF is disabled. Signed-off-by: Michal Simek michal.si...@xilinx.com I have already submitted a similar patch for doing this: https://lkml.org/lkml/2013/3/14/169 Ok. I don't care about it. Greg: Can you please add any of this patch to your char-misc tree? For Sachin patch. Acked-by: Michal Simek mon...@monstr.eu Thanks Michal. Since Hans wasn't active the patch has been pending since some time. The latest rebased version has been posted [1] for Greg to apply. [1] https://lkml.org/lkml/2013/6/25/7 Yeah. As I said I really don't care which version will be applied. It is just necessary to have progress on this. Here is the first version I have sent http://lkml.org/lkml/2013/5/23/311 btw: do you agree about removing that uio_pdrv because all functionality is already in uio_pdrv_genirq driver and make no sense to have two drivers for the same thing? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v3 1/2] uio: Use of_match_ptr() macro in uio_pdrv_genirq.c
On 06/26/2013 01:13 PM, Sachin Kamat wrote: On 26 June 2013 16:34, Michal Simek mon...@monstr.eu wrote: On 06/26/2013 12:51 PM, Sachin Kamat wrote: On 26 June 2013 15:51, Michal Simek mon...@monstr.eu wrote: On 06/26/2013 12:00 PM, Sachin Kamat wrote: On 26 June 2013 15:22, Michal Simek michal.si...@xilinx.com wrote: This eliminates having an #ifdef returning NULL for the case when OF is disabled. Signed-off-by: Michal Simek michal.si...@xilinx.com I have already submitted a similar patch for doing this: https://lkml.org/lkml/2013/3/14/169 Ok. I don't care about it. Greg: Can you please add any of this patch to your char-misc tree? For Sachin patch. Acked-by: Michal Simek mon...@monstr.eu Thanks Michal. Since Hans wasn't active the patch has been pending since some time. The latest rebased version has been posted [1] for Greg to apply. [1] https://lkml.org/lkml/2013/6/25/7 Yeah. As I said I really don't care which version will be applied. It is just necessary to have progress on this. Here is the first version I have sent http://lkml.org/lkml/2013/5/23/311 btw: do you agree about removing that uio_pdrv because all functionality is already in uio_pdrv_genirq driver and make no sense to have two drivers for the same thing? Sorry, I have'nt seen much of this code other than the obvious cleanup for which I had sent the patch. ok. Fair enough. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v4 0/7] xilinxfb changes
On 06/26/2013 01:41 PM, Tomi Valkeinen wrote: Hi, On 26/06/13 13:02, Michal Simek wrote: On 06/17/2013 11:07 PM, Arnd Bergmann wrote: On Monday 17 June 2013, Michal Simek wrote: On 06/17/2013 10:56 AM, Jean-Christophe PLAGNIOL-VILLARD wrote: On 07:23 Mon 17 Jun , Michal Simek wrote: On 06/06/2013 06:23 PM, Jean-Christophe PLAGNIOL-VILLARD wrote: On 12:13 Mon 03 Jun , Michal Simek wrote: Hi, Arnd can you take look on it again please I'll take a look on it next week Any update on this? look ok but I want the Ack from Arnd Sorry for the delay, everything looks good to me. Acked-by: Arnd Bergmann a...@arndb.de Jean-Christophe: Will you apply this series? Or should I take it through my microblaze tree? I've added this to my fbdev-3.11 branch. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH] dma-mapping: Add BUG_ON for uninitialized dma_ops
On 06/19/2013 05:20 PM, Arnd Bergmann wrote: On Friday 14 June 2013, James Bottomley wrote: This is the MMAP_PAGE_ZERO exploit. The original exploit relied on a leaky personality capability clearing mask and was fixed in 2.6.31 by commit f9fabcb58a6d26d6efde842d1703ac7cfa9427b6 Author: Julien Tinnes j...@cr0.org Date: Fri Jun 26 20:27:40 2009 +0200 personality: fix PER_CLEAR_ON_SETID So it's not really relevant to 3.x kernels, is it? Probably not. There is always a risk that something like this can turn into an exploit, but it needs a combination with a couple of other bugs. ok. Let me refresh this thread. We have middle solution where some functions have this checking and some not. Based on get_maintainer scripts Arnd should do that decision to accept or reject this patch. Arnd: Can you please decide if you want it or not? Based on that you can just add this one or we can create new one which remove BUG_ON(!ops) from that file. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v2 0/2] Xilinx watchdog changes
On 06/10/2013 11:10 AM, Michal Simek wrote: Hi Wim On 05/31/2013 07:56 AM, Michal Simek wrote: The patchset fixes license header and add 1.00.a IP to compatible list. Thanks for your review, Michal Remove the 3rd patch from this series which incorrectly tried to support set timeout feature. Changes in v2: - Extend compatible list with 1.00.a instead of replacing 1.01.a reported by Guenter Roeck li...@roeck-us.net Michal Simek (2): watchdog: xilinx: Fix driver header watchdog: xilinx: Setup the origin compatible string drivers/watchdog/of_xilinx_wdt.c | 31 +++ 1 file changed, 11 insertions(+), 20 deletions(-) Can you please add these two patches to your tree? Wim: I can't see these patches in linux-next that's why I expect you haven't added them to your branch. Can you please look at it? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v3 1/2] uio: Use of_match_ptr() macro in uio_pdrv_genirq.c
On 06/26/2013 05:00 PM, Greg Kroah-Hartman wrote: On Wed, Jun 26, 2013 at 12:21:27PM +0200, Michal Simek wrote: On 06/26/2013 12:00 PM, Sachin Kamat wrote: On 26 June 2013 15:22, Michal Simek michal.si...@xilinx.com wrote: This eliminates having an #ifdef returning NULL for the case when OF is disabled. Signed-off-by: Michal Simek michal.si...@xilinx.com I have already submitted a similar patch for doing this: https://lkml.org/lkml/2013/3/14/169 Ok. I don't care about it. Greg: Can you please add any of this patch to your char-misc tree? I did that yesterday, can't you see it in there already, or did I mess something up? You have applied drivers: uio_dmem_genirq: Use of_match_ptr() macro (sha1: 077797117dfa209717e1f3f1416c1101c0e047f0) which is for uio_dmem_genirq.c and there is one more for uio_pdrv_genirq.c driver which we have talked about with Sachin. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
[PATCH 1/2] GPIO: Add support for dual channel in gpio-xilinx.c
Supporting the second channel in the driver.
Offset is 0x8 and both channnels share the same
IRQ.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/gpio/gpio-xilinx.c | 93 --
1 file changed, 81 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 9ae7aa8..385dcb0 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -1,7 +1,7 @@
/*
- * Xilinx gpio driver
+ * Xilinx gpio driver for xps/axi_gpio IP.
*
- * Copyright 2008 Xilinx, Inc.
+ * Copyright 2008 - 2013 Xilinx, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
@@ -26,10 +26,17 @@
#define XGPIO_DATA_OFFSET (0x0) /* Data register */
#define XGPIO_TRI_OFFSET(0x4) /* I/O direction register */
+#define XGPIO_CHANNEL_OFFSET 0x8
+
+/* Read/Write access to the GPIO registers */
+#define xgpio_readreg(offset) __raw_readl(offset)
+#define xgpio_writereg(offset, val)__raw_writel(val, offset)
+
struct xgpio_instance {
struct of_mm_gpio_chip mmchip;
u32 gpio_state; /* GPIO state shadow register */
u32 gpio_dir; /* GPIO direction shadow register */
+ u32 offset;
spinlock_t gpio_lock; /* Lock used for synchronization */
};
@@ -44,8 +51,12 @@ struct xgpio_instance {
static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct xgpio_instance *chip =
+ container_of(mm_gc, struct xgpio_instance, mmchip);
+
+ void __iomem *regs = mm_gc-regs + chip-offset;
- return (in_be32(mm_gc-regs + XGPIO_DATA_OFFSET) gpio) 1;
+ return (xgpio_readreg(regs + XGPIO_DATA_OFFSET) gpio) 1;
}
/**
@@ -63,6 +74,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int
gpio, int val)
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
+ void __iomem *regs = mm_gc-regs;
spin_lock_irqsave(chip-gpio_lock, flags);
@@ -71,7 +83,9 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int
gpio, int val)
chip-gpio_state |= 1 gpio;
else
chip-gpio_state = ~(1 gpio);
- out_be32(mm_gc-regs + XGPIO_DATA_OFFSET, chip-gpio_state);
+
+ xgpio_writereg(regs + chip-offset + XGPIO_DATA_OFFSET,
+chip-gpio_state);
spin_unlock_irqrestore(chip-gpio_lock, flags);
}
@@ -91,12 +105,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int
gpio)
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
+ void __iomem *regs = mm_gc-regs;
spin_lock_irqsave(chip-gpio_lock, flags);
/* Set the GPIO bit in shadow register and set direction as input */
chip-gpio_dir |= (1 gpio);
- out_be32(mm_gc-regs + XGPIO_TRI_OFFSET, chip-gpio_dir);
+ xgpio_writereg(regs + chip-offset + XGPIO_TRI_OFFSET, chip-gpio_dir);
spin_unlock_irqrestore(chip-gpio_lock, flags);
@@ -119,6 +134,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int
gpio, int val)
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
+ void __iomem *regs = mm_gc-regs;
spin_lock_irqsave(chip-gpio_lock, flags);
@@ -127,11 +143,12 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned
int gpio, int val)
chip-gpio_state |= 1 gpio;
else
chip-gpio_state = ~(1 gpio);
- out_be32(mm_gc-regs + XGPIO_DATA_OFFSET, chip-gpio_state);
+ xgpio_writereg(regs + chip-offset + XGPIO_DATA_OFFSET,
+ chip-gpio_state);
/* Clear the GPIO bit in shadow register and set direction as output */
chip-gpio_dir = (~(1 gpio));
- out_be32(mm_gc-regs + XGPIO_TRI_OFFSET, chip-gpio_dir);
+ xgpio_writereg(regs + chip-offset + XGPIO_TRI_OFFSET, chip-gpio_dir);
spin_unlock_irqrestore(chip-gpio_lock, flags);
@@ -147,8 +164,10 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
- out_be32(mm_gc-regs + XGPIO_DATA_OFFSET, chip-gpio_state);
- out_be32(mm_gc-regs + XGPIO_TRI_OFFSET, chip-gpio_dir);
+ xgpio_writereg(mm_gc-regs + chip-offset + XGPIO_DATA_OFFSET,
+ chip-gpio_state);
+ xgpio_writereg(mm_gc-regs + chip-offset + XGPIO_TRI_OFFSET,
+chip-gpio_dir
[PATCH 2/2] DT: Add documentation for gpio-xilinx
Describe gpio-xilinx binding.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
.../devicetree/bindings/gpio/gpio-xilinx.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
new file mode 100644
index 000..65bf386
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
@@ -0,0 +1,43 @@
+Xilinx plb/axi GPIO controller
+
+Required properties:
+- compatible : Should be xlnx,xps-gpio-1.00.a
+- reg : Address and length of the register set for the device
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters (currently unused).
+- gpio-controller : Marks the device node as a GPIO controller.
+
+Optional properties:
+- interrupts : Interrupt mapping for GPIO IRQ.
+- interrupt-parent : Phandle for the interrupt controller that
+ services interrupts for this device.
+- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
+- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
+- xlnx,gpio-width : gpio width
+- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode
+- xlnx,is-dual : if 1, controller also uses the second channel
+- xlnx,all-inputs-2 : as above but for the second channel
+- xlnx,dout-default-2 : as above but the second channel
+- xlnx,gpio2-width : as above but for the second channel
+- xlnx,tri-default-2 : as above but for the second channel
+
+
+Example:
+gpio: gpio@4000 {
+ #gpio-cells = 2;
+ compatible = xlnx,xps-gpio-1.00.a;
+ gpio-controller ;
+ interrupt-parent = microblaze_0_intc;
+ interrupts = 6 2 ;
+ reg = 0x4000 0x1 ;
+ xlnx,all-inputs = 0x0;
+ xlnx,all-inputs-2 = 0x0;
+ xlnx,dout-default = 0x0;
+ xlnx,dout-default-2 = 0x0;
+ xlnx,gpio-width = 0x2;
+ xlnx,gpio2-width = 0x2;
+ xlnx,interrupt-present = 0x1;
+ xlnx,is-dual = 0x1;
+ xlnx,tri-default = 0x;
+ xlnx,tri-default-2 = 0x;
+} ;
--
1.8.2.3
pgp6VUfgxc1uf.pgp
Description: PGP signature
Re: [RFC PATCH 2/2] uio: Add two platform uio drivers to one
Hi Hans,
any comment on this?
Thanks,
Michal
On 05/23/2013 04:01 PM, Michal Simek wrote:
- Remove Userspace I/O platform driver without IRQ support
but add this functionality to genirq driver
- Remove code duplication from OF binding
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
The main reason for this change is to have one
compatibility string for UIO with and without IRQ.
---
drivers/uio/Kconfig | 7 ---
drivers/uio/Makefile | 1 -
drivers/uio/uio_pdrv.c| 113
--
drivers/uio/uio_pdrv_genirq.c | 30 ---
4 files changed, 9 insertions(+), 142 deletions(-)
delete mode 100644 drivers/uio/uio_pdrv.c
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index e92eeaf..2ff4c90 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -23,13 +23,6 @@ config UIO_CIF
To compile this driver as a module, choose M here: the module
will be called uio_cif.
-config UIO_PDRV
- tristate Userspace I/O platform driver
- help
- Generic platform driver for Userspace I/O devices.
-
- If you don't know what to do here, say N.
-
config UIO_PDRV_GENIRQ
tristate Userspace I/O platform driver with generic IRQ handling
help
diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
index b354c53..ea015a2 100644
--- a/drivers/uio/Makefile
+++ b/drivers/uio/Makefile
@@ -1,6 +1,5 @@
obj-$(CONFIG_UIO)+= uio.o
obj-$(CONFIG_UIO_CIF)+= uio_cif.o
-obj-$(CONFIG_UIO_PDRV) += uio_pdrv.o
obj-$(CONFIG_UIO_PDRV_GENIRQ)+= uio_pdrv_genirq.o
obj-$(CONFIG_UIO_DMEM_GENIRQ)+= uio_dmem_genirq.o
obj-$(CONFIG_UIO_AEC)+= uio_aec.o
diff --git a/drivers/uio/uio_pdrv.c b/drivers/uio/uio_pdrv.c
deleted file mode 100644
index 39be9e0..000
--- a/drivers/uio/uio_pdrv.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * drivers/uio/uio_pdrv.c
- *
- * Copyright (C) 2008 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
by
- * the Free Software Foundation.
- */
-#include linux/platform_device.h
-#include linux/uio_driver.h
-#include linux/stringify.h
-#include linux/module.h
-#include linux/slab.h
-
-#define DRIVER_NAME uio_pdrv
-
-struct uio_platdata {
- struct uio_info *uioinfo;
-};
-
-static int uio_pdrv_probe(struct platform_device *pdev)
-{
- struct uio_info *uioinfo = pdev-dev.platform_data;
- struct uio_platdata *pdata;
- struct uio_mem *uiomem;
- int ret = -ENODEV;
- int i;
-
- if (!uioinfo || !uioinfo-name || !uioinfo-version) {
- dev_dbg(pdev-dev, %s: err_uioinfo\n, __func__);
- goto err_uioinfo;
- }
-
- pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
- if (!pdata) {
- ret = -ENOMEM;
- dev_dbg(pdev-dev, %s: err_alloc_pdata\n, __func__);
- goto err_alloc_pdata;
- }
-
- pdata-uioinfo = uioinfo;
-
- uiomem = uioinfo-mem[0];
-
- for (i = 0; i pdev-num_resources; ++i) {
- struct resource *r = pdev-resource[i];
-
- if (r-flags != IORESOURCE_MEM)
- continue;
-
- if (uiomem = uioinfo-mem[MAX_UIO_MAPS]) {
- dev_warn(pdev-dev, device has more than
- __stringify(MAX_UIO_MAPS)
- I/O memory resources.\n);
- break;
- }
-
- uiomem-memtype = UIO_MEM_PHYS;
- uiomem-addr = r-start;
- uiomem-size = resource_size(r);
- uiomem-name = r-name;
- ++uiomem;
- }
-
- while (uiomem uioinfo-mem[MAX_UIO_MAPS]) {
- uiomem-size = 0;
- ++uiomem;
- }
-
- pdata-uioinfo-priv = pdata;
-
- ret = uio_register_device(pdev-dev, pdata-uioinfo);
-
- if (ret) {
- kfree(pdata);
-err_alloc_pdata:
-err_uioinfo:
- return ret;
- }
-
- platform_set_drvdata(pdev, pdata);
-
- return 0;
-}
-
-static int uio_pdrv_remove(struct platform_device *pdev)
-{
- struct uio_platdata *pdata = platform_get_drvdata(pdev);
-
- uio_unregister_device(pdata-uioinfo);
-
- kfree(pdata);
-
- return 0;
-}
-
-static struct platform_driver uio_pdrv = {
- .probe = uio_pdrv_probe,
- .remove = uio_pdrv_remove,
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-module_platform_driver(uio_pdrv);
-
-MODULE_AUTHOR(Uwe Kleine-Koenig);
-MODULE_DESCRIPTION(Userspace I/O platform driver);
-MODULE_LICENSE(GPL v2);
-MODULE_ALIAS(platform: DRIVER_NAME);
diff --git a/drivers/uio/uio_pdrv_genirq.c b/drivers/uio
[PATCH 03/11] phy: Use macros instead of hardcoded values in marvell phy driver
Use macros from linux/marvell_phy.h instead of duplicate
magic phy ID in the driver.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/phy/marvell.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 202fe1f..371353c 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -958,15 +958,15 @@ module_init(marvell_init);
module_exit(marvell_exit);
static struct mdio_device_id __maybe_unused marvell_tbl[] = {
- { 0x01410c60, 0xfff0 },
- { 0x01410c90, 0xfff0 },
- { 0x01410cc0, 0xfff0 },
- { 0x01410e10, 0xfff0 },
- { 0x01410cb0, 0xfff0 },
- { 0x01410cd0, 0xfff0 },
- { 0x01410e50, 0xfff0 },
- { 0x01410e30, 0xfff0 },
- { 0x01410e90, 0xfff0 },
+ { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
{ }
};
--
1.8.2.3
pgp1FYreZ3t_m.pgp
Description: PGP signature
[PATCH 05/11] phy: Add Marvell 88E1510 phy ID
Add support for this new phy ID.
Signed-off-by: Rick Hoover rhoo...@digilentinc.com
Signed-off-by: Steven Wang steven.w...@digilentinc.com
Signed-off-by: Lars-Peter Clausen l...@metafoo.de
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/phy/marvell.c | 25 +
include/linux/marvell_phy.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index df5a9f6..2e91477 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -374,6 +374,17 @@ static int m88e1318_config_aneg(struct phy_device *phydev)
return m88e1121_config_aneg(phydev);
}
+static int m88e1510_config_aneg(struct phy_device *phydev)
+{
+ int err;
+
+ err = m88e1318_config_aneg(phydev);
+ if (err 0)
+ return err;
+
+ return marvell_of_reg_init(phydev);
+}
+
static int m88e1116r_config_init(struct phy_device *phydev)
{
int temp;
@@ -1004,6 +1015,19 @@ static struct phy_driver marvell_drivers[] = {
.config_intr = marvell_config_intr,
.driver = { .owner = THIS_MODULE },
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E1510,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = Marvell 88E1510,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_aneg = m88e1510_config_aneg,
+ .read_status = marvell_read_status,
+ .ack_interrupt = marvell_ack_interrupt,
+ .config_intr = marvell_config_intr,
+ .did_interrupt = m88e1121_did_interrupt,
+ .driver = { .owner = THIS_MODULE },
+ },
};
static int __init marvell_init(void)
@@ -1032,6 +1056,7 @@ static struct mdio_device_id __maybe_unused marvell_tbl[]
= {
{ MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
{ }
};
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index ec41025..8e9a029 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -15,6 +15,7 @@
#define MARVELL_PHY_ID_88E1240 0x01410e30
#define MARVELL_PHY_ID_88E1318S0x01410e90
#define MARVELL_PHY_ID_88E1116R0x01410e40
+#define MARVELL_PHY_ID_88E1510 0x01410dd0
/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x0001
--
1.8.2.3
pgpfA4XOmS94O.pgp
Description: PGP signature
[PATCH 08/11] net: emaclite: Let's make xemaclite_adjust_link static
xemaclite_adjust_link is used locally.
It removes sparse warning:
drivers/net/ethernet/xilinx/xilinx_emaclite.c:916:6: warning:
symbol 'xemaclite_adjust_link' was not declared. Should it be static?
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index fcd1e0b..93bb14e 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -913,7 +913,7 @@ err_register:
* There's nothing in the Emaclite device to be configured when the link
* state changes. We just print the status.
*/
-void xemaclite_adjust_link(struct net_device *ndev)
+static void xemaclite_adjust_link(struct net_device *ndev)
{
struct net_local *lp = netdev_priv(ndev);
struct phy_device *phy = lp-phy_dev;
--
1.8.2.3
pgp5slIaucuQx.pgp
Description: PGP signature
[PATCH 07/11] net: emaclite: Support multiple phys connected to one MDIO bus
For system which contains at least two ethernet IP where
one IP manage MDIO bus with several PHYs.
Example dts node:
ethernet_mac0: ethernet@8100 {
compatible = xlnx,xps-ethernetlite-1.00.a;
device_type = network;
interrupt-parent = xps_intc_0;
interrupts = 1 0 ;
local-mac-address = [ 00 0a 35 00 db bb ];
phy-handle = ethernet_mac0_phy0;
reg = 0x8100 0x1 ;
xlnx,duplex = 0x1;
xlnx,family = spartan3e;
xlnx,include-internal-loopback = 0x0;
xlnx,include-mdio = 0x1;
xlnx,rx-ping-pong = 0x0;
xlnx,tx-ping-pong = 0x0;
ethernet_mac0_mdio {
#address-cells = 1;
#size-cells = 0;
ethernet_mac0_phy0: phy@1 {
reg = 0x1;
} ;
ethernet_mac0_phy1: phy@3 {
reg = 0x3;
} ;
} ;
} ;
ethernet_mac2: ethernet@8104 {
compatible = xlnx,xps-ethernetlite-1.00.a;
device_type = network;
interrupt-parent = xps_intc_0;
interrupts = 11 0 ;
local-mac-address = [ 00 0a 35 00 db bb ];
phy-handle = ethernet_mac0_phy1;
reg = 0x8104 0x1 ;
xlnx,duplex = 0x1;
xlnx,family = spartan3e;
xlnx,include-internal-loopback = 0x0;
xlnx,include-mdio = 0x0;
xlnx,rx-ping-pong = 0x0;
xlnx,tx-ping-pong = 0x0;
} ;
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index a16dc35..fcd1e0b 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -848,6 +848,7 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
int rc;
struct resource res;
struct device_node *np = of_get_parent(lp-phy_node);
+ struct device_node *npp;
/* Don't register the MDIO bus if the phy_node or its parent node
* can't be found.
@@ -856,6 +857,17 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
dev_err(dev, Failed to register mdio bus.\n);
return -ENODEV;
}
+ npp = of_get_parent(np);
+
+ of_address_to_resource(npp, 0, res);
+ if (lp-ndev-mem_start != res.start) {
+ struct phy_device *phydev;
+ phydev = of_phy_find_device(lp-phy_node);
+ if (!phydev)
+ dev_info(dev,
+MDIO of the phy is not registered yet\n);
+ return 0;
+ }
/* Enable the MDIO bus by asserting the enable bit in MDIO Control
* register.
@@ -869,7 +881,6 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
return -ENOMEM;
}
- of_address_to_resource(np, 0, res);
snprintf(bus-id, MII_BUS_ID_SIZE, %.8llx,
(unsigned long long)res.start);
bus-priv = lp;
--
1.8.2.3
pgp52J4EEqO1L.pgp
Description: PGP signature
[PATCH 11/11] net: emaclite: Update driver header
Corrent email address and years. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 0d8515b..af12314 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -2,9 +2,9 @@ * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. * * This is a new flat driver which is based on the original emac_lite - * driver from John Williams john.willi...@petalogix.com. + * driver from John Williams john.willi...@xilinx.com. * - * 2007-2009 (c) Xilinx, Inc. + * 2007 - 2013 (c) Xilinx, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the -- 1.8.2.3 pgpUyMaVsBS9w.pgp Description: PGP signature
[PATCH 10/11] net: emaclite: Enable emaclite for Xilinx Arm Zynq platform
Enable emaclite for Xilinx ARM Zynq platform. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/net/ethernet/xilinx/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xilinx/Kconfig index 122d60c..7b90a5e 100644 --- a/drivers/net/ethernet/xilinx/Kconfig +++ b/drivers/net/ethernet/xilinx/Kconfig @@ -5,7 +5,7 @@ config NET_VENDOR_XILINX bool Xilinx devices default y - depends on PPC || PPC32 || MICROBLAZE + depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ ---help--- If you have a network (Ethernet) card belonging to this class, say Y and read the Ethernet-HOWTO, available from @@ -20,7 +20,7 @@ if NET_VENDOR_XILINX config XILINX_EMACLITE tristate Xilinx 10/100 Ethernet Lite support - depends on (PPC32 || MICROBLAZE) + depends on (PPC32 || MICROBLAZE || ARCH_ZYNQ) select PHYLIB ---help--- This driver supports the 10/100 Ethernet Lite from Xilinx. -- 1.8.2.3 pgpQUj46eo3TR.pgp Description: PGP signature
[PATCH 09/11] net: emaclite: Do not use microblaze and ppc IO functions
Emaclite can be used on ARM zynq where in_be32/out_be32 IO
functions are not present. Use standard __raw_readl/__raw_writel
IO functions instead.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 100 +-
1 file changed, 51 insertions(+), 49 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 93bb14e..0d8515b 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -159,34 +159,34 @@ static void xemaclite_enable_interrupts(struct net_local
*drvdata)
u32 reg_data;
/* Enable the Tx interrupts for the first Buffer */
- reg_data = in_be32(drvdata-base_addr + XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_TSR_OFFSET,
+ reg_data = __raw_readl(drvdata-base_addr + XEL_TSR_OFFSET);
+ __raw_writel(drvdata-base_addr + XEL_TSR_OFFSET,
reg_data | XEL_TSR_XMIT_IE_MASK);
/* Enable the Tx interrupts for the second Buffer if
* configured in HW */
if (drvdata-tx_ping_pong != 0) {
- reg_data = in_be32(drvdata-base_addr +
+ reg_data = __raw_readl(drvdata-base_addr +
XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ __raw_writel(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_TSR_OFFSET,
reg_data | XEL_TSR_XMIT_IE_MASK);
}
/* Enable the Rx interrupts for the first buffer */
- out_be32(drvdata-base_addr + XEL_RSR_OFFSET,
+ __raw_writel(drvdata-base_addr + XEL_RSR_OFFSET,
XEL_RSR_RECV_IE_MASK);
/* Enable the Rx interrupts for the second Buffer if
* configured in HW */
if (drvdata-rx_ping_pong != 0) {
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ __raw_writel(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_RSR_OFFSET,
XEL_RSR_RECV_IE_MASK);
}
/* Enable the Global Interrupt Enable */
- out_be32(drvdata-base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+ __raw_writel(drvdata-base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
}
/**
@@ -201,35 +201,35 @@ static void xemaclite_disable_interrupts(struct net_local
*drvdata)
u32 reg_data;
/* Disable the Global Interrupt Enable */
- out_be32(drvdata-base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+ __raw_writel(drvdata-base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
/* Disable the Tx interrupts for the first buffer */
- reg_data = in_be32(drvdata-base_addr + XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_TSR_OFFSET,
+ reg_data = __raw_readl(drvdata-base_addr + XEL_TSR_OFFSET);
+ __raw_writel(drvdata-base_addr + XEL_TSR_OFFSET,
reg_data (~XEL_TSR_XMIT_IE_MASK));
/* Disable the Tx interrupts for the second Buffer
* if configured in HW */
if (drvdata-tx_ping_pong != 0) {
- reg_data = in_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ reg_data = __raw_readl(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ __raw_writel(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_TSR_OFFSET,
reg_data (~XEL_TSR_XMIT_IE_MASK));
}
/* Disable the Rx interrupts for the first buffer */
- reg_data = in_be32(drvdata-base_addr + XEL_RSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_RSR_OFFSET,
+ reg_data = __raw_readl(drvdata-base_addr + XEL_RSR_OFFSET);
+ __raw_writel(drvdata-base_addr + XEL_RSR_OFFSET,
reg_data (~XEL_RSR_RECV_IE_MASK));
/* Disable the Rx interrupts for the second buffer
* if configured in HW */
if (drvdata-rx_ping_pong != 0) {
- reg_data = in_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ reg_data = __raw_readl(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_RSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ __raw_writel(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_RSR_OFFSET,
reg_data (~XEL_RSR_RECV_IE_MASK));
}
@@ -351,7 +351,7 @@ static int xemaclite_send_data(struct net_local *drvdata,
u8 *data,
byte_count = ETH_FRAME_LEN;
/* Check if the expected buffer is available */
- reg_data = in_be32(addr + XEL_TSR_OFFSET);
+ reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
if ((reg_data (XEL_TSR_XMIT_BUSY_MASK |
XEL_TSR_XMIT_ACTIVE_MASK)) == 0
[PATCH 01/11] phy: Clean coding style in vitesse phy
- Remove trailing white space
- Remove spaces before tag
- Fix comments
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/phy/vitesse.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 3492b53..d6e988f 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -44,12 +44,12 @@
#define MII_VSC8244_ISTAT_DUPLEX 0x1000
/* Vitesse Auxiliary Control/Status Register */
-#define MII_VSC8244_AUX_CONSTAT0x1c
-#define MII_VSC8244_AUXCONSTAT_INIT0x
-#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
-#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
-#define MII_VSC8244_AUXCONSTAT_GBIT0x0010
-#define MII_VSC8244_AUXCONSTAT_100 0x0008
+#define MII_VSC8244_AUX_CONSTAT0x1c
+#define MII_VSC8244_AUXCONSTAT_INIT0x
+#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
+#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
+#define MII_VSC8244_AUXCONSTAT_GBIT0x0010
+#define MII_VSC8244_AUXCONSTAT_100 0x0008
#define MII_VSC8221_AUXCONSTAT_INIT0x0004 /* need to set this bit? */
#define MII_VSC8221_AUXCONSTAT_RESERVED0x0004
@@ -100,9 +100,8 @@ static int vsc824x_config_init(struct phy_device *phydev)
static int vsc824x_ack_interrupt(struct phy_device *phydev)
{
int err = 0;
-
- /*
-* Don't bother to ACK the interrupts if interrupts
+
+ /* Don't bother to ACK the interrupts if interrupts
* are disabled. The 824x cannot clear the interrupts
* if they are disabled.
*/
@@ -122,8 +121,7 @@ static int vsc82xx_config_intr(struct phy_device *phydev)
MII_VSC8244_IMASK_MASK :
MII_VSC8221_IMASK_MASK);
else {
- /*
-* The Vitesse PHY cannot clear the interrupt
+ /* The Vitesse PHY cannot clear the interrupt
* once it has disabled them, so we clear them first
*/
err = phy_read(phydev, MII_VSC8244_ISTAT);
@@ -146,7 +144,8 @@ static int vsc8221_config_init(struct phy_device *phydev)
return err;
/* Perhaps we should set EXT_CON1 based on the interface?
- Options are 802.3Z SerDes or SGMII */
+* Options are 802.3Z SerDes or SGMII
+*/
}
/* Vitesse 824x */
--
1.8.2.3
pgpWKIXlrvp3D.pgp
Description: PGP signature
[PATCH 04/11] phy: Add Marvell 88E1116R phy ID
This phy is on Xilinx ZC702 zynq development board.
Signed-off-by: Anirudha Sarangi anir...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/phy/marvell.c | 65 +
include/linux/marvell_phy.h | 1 +
2 files changed, 66 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 371353c..df5a9f6 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -116,6 +116,8 @@
#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_STATUS_LINK 0x0400
+#define MII_M1116R_CONTROL_REG_MAC 21
+
MODULE_DESCRIPTION(Marvell PHY driver);
MODULE_AUTHOR(Andy Fleming);
@@ -372,6 +374,55 @@ static int m88e1318_config_aneg(struct phy_device *phydev)
return m88e1121_config_aneg(phydev);
}
+static int m88e1116r_config_init(struct phy_device *phydev)
+{
+ int temp;
+ int err;
+
+ temp = phy_read(phydev, MII_BMCR);
+ temp |= BMCR_RESET;
+ err = phy_write(phydev, MII_BMCR, temp);
+ if (err 0)
+ return err;
+
+ mdelay(500);
+
+ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
+ if (err 0)
+ return err;
+
+ temp = phy_read(phydev, MII_M1011_PHY_SCR);
+ temp |= (7 12); /* max number of gigabit attempts */
+ temp |= (1 11); /* enable downshift */
+ temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
+ err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
+ if (err 0)
+ return err;
+
+ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
+ if (err 0)
+ return err;
+ temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
+ temp |= (1 5);
+ temp |= (1 4);
+ err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
+ if (err 0)
+ return err;
+ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
+ if (err 0)
+ return err;
+
+ temp = phy_read(phydev, MII_BMCR);
+ temp |= BMCR_RESET;
+ err = phy_write(phydev, MII_BMCR, temp);
+ if (err 0)
+ return err;
+
+ mdelay(500);
+
+ return 0;
+}
+
static int m88e_config_init(struct phy_device *phydev)
{
int err;
@@ -940,6 +991,19 @@ static struct phy_driver marvell_drivers[] = {
.config_intr = marvell_config_intr,
.driver = { .owner = THIS_MODULE },
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E1116R,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = Marvell 88E1116R,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = m88e1116r_config_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = marvell_ack_interrupt,
+ .config_intr = marvell_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ },
};
static int __init marvell_init(void)
@@ -967,6 +1031,7 @@ static struct mdio_device_id __maybe_unused marvell_tbl[]
= {
{ MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
{ }
};
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index dd3c34e..ec41025 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -14,6 +14,7 @@
#define MARVELL_PHY_ID_88E1149R0x01410e50
#define MARVELL_PHY_ID_88E1240 0x01410e30
#define MARVELL_PHY_ID_88E1318S0x01410e90
+#define MARVELL_PHY_ID_88E1116R0x01410e40
/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x0001
--
1.8.2.3
pgpKgY5Uw7G8u.pgp
Description: PGP signature
[PATCH 06/11] net: emaclite: Report failures in mdio setup
Be more verbose when any problem happens.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 919b983..a16dc35 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -852,8 +852,10 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
/* Don't register the MDIO bus if the phy_node or its parent node
* can't be found.
*/
- if (!np)
+ if (!np) {
+ dev_err(dev, Failed to register mdio bus.\n);
return -ENODEV;
+ }
/* Enable the MDIO bus by asserting the enable bit in MDIO Control
* register.
@@ -862,8 +864,10 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
XEL_MDIOCTRL_MDIOEN_MASK);
bus = mdiobus_alloc();
- if (!bus)
+ if (!bus) {
+ dev_err(dev, Failed to allocal mdiobus\n);
return -ENOMEM;
+ }
of_address_to_resource(np, 0, res);
snprintf(bus-id, MII_BUS_ID_SIZE, %.8llx,
@@ -879,8 +883,10 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
lp-mii_bus = bus;
rc = of_mdiobus_register(bus, np);
- if (rc)
+ if (rc) {
+ dev_err(dev, Failed to register mdio bus.\n);
goto err_register;
+ }
return 0;
--
1.8.2.3
pgp51rUFFjh9A.pgp
Description: PGP signature
[PATCH 02/11] phy: Add Vitesse 8211 phy ID
Phy is compatible with Vitesse 8221.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/phy/vitesse.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index d6e988f..69b482b 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -56,6 +56,7 @@
#define PHY_ID_VSC8244 0x000fc6c0
#define PHY_ID_VSC8221 0x000fc550
+#define PHY_ID_VSC8211 0x000fc4b0
MODULE_DESCRIPTION(Vitesse PHY driver);
MODULE_AUTHOR(Kriston Carson);
@@ -175,6 +176,19 @@ static struct phy_driver vsc82xx_driver[] = {
.ack_interrupt = vsc824x_ack_interrupt,
.config_intr= vsc82xx_config_intr,
.driver = { .owner = THIS_MODULE,},
+}, {
+ /* Vitesse 8211 */
+ .phy_id = PHY_ID_VSC8211,
+ .phy_id_mask= 0x0000,
+ .name = Vitesse VSC8211,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init= vsc8221_config_init,
+ .config_aneg= genphy_config_aneg,
+ .read_status= genphy_read_status,
+ .ack_interrupt = vsc824x_ack_interrupt,
+ .config_intr= vsc82xx_config_intr,
+ .driver = { .owner = THIS_MODULE,},
} };
static int __init vsc82xx_init(void)
@@ -195,6 +209,7 @@ module_exit(vsc82xx_exit);
static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
{ PHY_ID_VSC8244, 0x000fffc0 },
{ PHY_ID_VSC8221, 0x0000 },
+ { PHY_ID_VSC8211, 0x0000 },
{ }
};
--
1.8.2.3
pgpw_hetMFMm2.pgp
Description: PGP signature
Re: [PATCH 09/11] net: emaclite: Do not use microblaze and ppc IO functions
On 05/29/2013 05:33 PM, Michal Simek wrote: Emaclite can be used on ARM zynq where in_be32/out_be32 IO functions are not present. Use standard __raw_readl/__raw_writel IO functions instead. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 100 +- 1 file changed, 51 insertions(+), 49 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 93bb14e..0d8515b 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -159,34 +159,34 @@ static void xemaclite_enable_interrupts(struct net_local *drvdata) u32 reg_data; /* Enable the Tx interrupts for the first Buffer */ - reg_data = in_be32(drvdata-base_addr + XEL_TSR_OFFSET); - out_be32(drvdata-base_addr + XEL_TSR_OFFSET, + reg_data = __raw_readl(drvdata-base_addr + XEL_TSR_OFFSET); + __raw_writel(drvdata-base_addr + XEL_TSR_OFFSET, reg_data | XEL_TSR_XMIT_IE_MASK); oou - this is completely wrong. Will do v2. Sorry for that. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
[PATCH 1/3] video: xilinxfb: Fix OF probing on little-endian systems
From: Michal Simek mon...@monstr.eu DTB is always big-endian that's why is necessary to convert it. Signed-off-by: Michal Simek mon...@monstr.eu Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/video/xilinxfb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index af0b4fd..5af341e 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -428,7 +428,7 @@ static int xilinxfb_of_probe(struct platform_device *op) * interface and initialize the tft_access accordingly. */ p = (u32 *)of_get_property(op-dev.of_node, xlnx,dcr-splb-slave-if, NULL); - tft_access = p ? *p : 0; + tft_access = p ? be32_to_cpup(p) : 0; /* * Fill the resource structure if its direct PLB interface -- 1.8.2.3 pgpJUXhcophGq.pgp Description: PGP signature
[PATCH 3/3] video: xilinxfb: Use driver for Xilinx ARM Zynq
From: Michal Simek mon...@monstr.eu Enable this driver for all Xilinx platforms. Signed-off-by: Michal Simek mon...@monstr.eu Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2e937bd..2c301f8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2188,7 +2188,7 @@ config FB_PS3_DEFAULT_SIZE_M config FB_XILINX tristate Xilinx frame buffer support - depends on FB (XILINX_VIRTEX || MICROBLAZE) + depends on FB (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.8.2.3 pgp7sfe4INCdo.pgp Description: PGP signature
[PATCH 2/3] video: xilinxfb: Do not use out_be32 IO function
out_be32 IO function is not supported by ARM.
It is only available for PPC and Microblaze.
Remove all out_be32 references and start to use __raw_writel
function.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/video/xilinxfb.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 5af341e..dcf0552 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -57,7 +57,7 @@
* In case of direct PLB access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
- * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
+ * xilinx_fb_out32 where it left shifts the offset 2 times in case of
* direct PLB access.
*/
#define NUM_REGS 2
@@ -150,11 +150,11 @@ struct xilinxfb_drvdata {
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
-static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
if (drvdata-flags PLB_ACCESS_FLAG)
- out_be32(drvdata-regs + (offset 2), val);
+ __raw_writel(val, drvdata-regs + (offset 2));
#ifdef CONFIG_PPC_DCR
else
dcr_write(drvdata-dcr_host, offset, val);
@@ -197,7 +197,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* turn on panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
+ xilinx_fb_out32(drvdata, REG_CTRL, drvdata-reg_ctrl_default);
break;
case FB_BLANK_NORMAL:
@@ -205,7 +205,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
/* turn off panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
default:
break;
@@ -280,13 +280,13 @@ static int xilinxfb_assign(struct device *dev,
memset_io((void __iomem *)drvdata-fb_virt, 0, fbsize);
/* Tell the hardware where the frame buffer is */
- xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
/* Turn on the display */
drvdata-reg_ctrl_default = REG_CTRL_ENABLE;
if (pdata-rotate_screen)
drvdata-reg_ctrl_default |= REG_CTRL_ROTATE;
- xilinx_fb_out_be32(drvdata, REG_CTRL,
+ xilinx_fb_out32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
/* Fill struct fb_info */
@@ -345,7 +345,7 @@ err_cmap:
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
err_fbmem:
if (drvdata-flags PLB_ACCESS_FLAG)
@@ -381,7 +381,7 @@ static int xilinxfb_release(struct device *dev)
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
if (drvdata-flags PLB_ACCESS_FLAG) {
--
1.8.2.3
pgpq2p2wC5AFf.pgp
Description: PGP signature
Re: [PATCH 11/11] net: emaclite: Update driver header
On 05/29/2013 07:11 PM, Sergei Shtylyov wrote: Hello. On 05/29/2013 07:33 PM, Michal Simek wrote: Corrent email address and years. s/Corrent/Correct/. Perhaps the committer can fix. I will fix it in v2, one patch is broken anyway. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
[PATCH v2 1/3] video: xilinxfb: Fix OF probing on little-endian systems
From: Michal Simek mon...@monstr.eu
DTB is always big-endian that's why is necessary
to convert it.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- use of_property_read_u32 helper function
drivers/video/xilinxfb.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index af0b4fd..aecd15d 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -406,8 +406,7 @@ static int xilinxfb_release(struct device *dev)
static int xilinxfb_of_probe(struct platform_device *op)
{
const u32 *prop;
- u32 *p;
- u32 tft_access;
+ u32 tft_access = 0;
struct xilinxfb_platform_data pdata;
struct resource res;
int size, rc;
@@ -427,8 +426,8 @@ static int xilinxfb_of_probe(struct platform_device *op)
* To check whether the core is connected directly to DCR or PLB
* interface and initialize the tft_access accordingly.
*/
- p = (u32 *)of_get_property(op-dev.of_node, xlnx,dcr-splb-slave-if,
NULL);
- tft_access = p ? *p : 0;
+ of_property_read_u32(op-dev.of_node, xlnx,dcr-splb-slave-if,
+tft_access);
/*
* Fill the resource structure if its direct PLB interface
--
1.8.2.3
pgprxPzMgDxpW.pgp
Description: PGP signature
[PATCH v2 2/3] video: xilinxfb: Do not use out_be32 IO function
out_be32 IO function is not supported by ARM.
It is only available for PPC and Microblaze.
Remove all out_be32 references and start to use __raw_writel
function.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/video/xilinxfb.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index aecd15d..000185a 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -57,7 +57,7 @@
* In case of direct PLB access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
- * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
+ * xilinx_fb_out32 where it left shifts the offset 2 times in case of
* direct PLB access.
*/
#define NUM_REGS 2
@@ -150,11 +150,11 @@ struct xilinxfb_drvdata {
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
-static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
if (drvdata-flags PLB_ACCESS_FLAG)
- out_be32(drvdata-regs + (offset 2), val);
+ __raw_writel(val, drvdata-regs + (offset 2));
#ifdef CONFIG_PPC_DCR
else
dcr_write(drvdata-dcr_host, offset, val);
@@ -197,7 +197,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* turn on panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
+ xilinx_fb_out32(drvdata, REG_CTRL, drvdata-reg_ctrl_default);
break;
case FB_BLANK_NORMAL:
@@ -205,7 +205,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
/* turn off panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
default:
break;
@@ -280,13 +280,13 @@ static int xilinxfb_assign(struct device *dev,
memset_io((void __iomem *)drvdata-fb_virt, 0, fbsize);
/* Tell the hardware where the frame buffer is */
- xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
/* Turn on the display */
drvdata-reg_ctrl_default = REG_CTRL_ENABLE;
if (pdata-rotate_screen)
drvdata-reg_ctrl_default |= REG_CTRL_ROTATE;
- xilinx_fb_out_be32(drvdata, REG_CTRL,
+ xilinx_fb_out32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
/* Fill struct fb_info */
@@ -345,7 +345,7 @@ err_cmap:
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
err_fbmem:
if (drvdata-flags PLB_ACCESS_FLAG)
@@ -381,7 +381,7 @@ static int xilinxfb_release(struct device *dev)
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
if (drvdata-flags PLB_ACCESS_FLAG) {
--
1.8.2.3
pgp0hqygYyCAI.pgp
Description: PGP signature
[PATCH v2 3/3] video: xilinxfb: Use driver for Xilinx ARM Zynq
From: Michal Simek mon...@monstr.eu Enable this driver for all Xilinx platforms. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: None drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2e937bd..2c301f8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2188,7 +2188,7 @@ config FB_PS3_DEFAULT_SIZE_M config FB_XILINX tristate Xilinx frame buffer support - depends on FB (XILINX_VIRTEX || MICROBLAZE) + depends on FB (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.8.2.3 pgpTdPmUnzoUT.pgp Description: PGP signature
[PATCH v2 0/6] Emaclite patches
I have separated these emaclite patches from phy patches because it is easier for creating new versions. Thanks, Michal Changes in v2: - Fix __raw_iowrite() to pass correct parameters - s/Corrent/Correct/ in patch description Michal Simek (6): net: emaclite: Report failures in mdio setup net: emaclite: Support multiple phys connected to one MDIO bus net: emaclite: Let's make xemaclite_adjust_link static net: emaclite: Do not use microblaze and ppc IO functions net: emaclite: Enable emaclite for Xilinx Arm Zynq platform net: emaclite: Update driver header drivers/net/ethernet/xilinx/Kconfig | 4 +- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 169 ++ 2 files changed, 95 insertions(+), 78 deletions(-) -- 1.8.2.3 pgp2wSMP1xUH2.pgp Description: PGP signature
[PATCH v2 1/6] net: emaclite: Report failures in mdio setup
Be more verbose when any problem happens.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 919b983..a16dc35 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -852,8 +852,10 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
/* Don't register the MDIO bus if the phy_node or its parent node
* can't be found.
*/
- if (!np)
+ if (!np) {
+ dev_err(dev, Failed to register mdio bus.\n);
return -ENODEV;
+ }
/* Enable the MDIO bus by asserting the enable bit in MDIO Control
* register.
@@ -862,8 +864,10 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
XEL_MDIOCTRL_MDIOEN_MASK);
bus = mdiobus_alloc();
- if (!bus)
+ if (!bus) {
+ dev_err(dev, Failed to allocal mdiobus\n);
return -ENOMEM;
+ }
of_address_to_resource(np, 0, res);
snprintf(bus-id, MII_BUS_ID_SIZE, %.8llx,
@@ -879,8 +883,10 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
lp-mii_bus = bus;
rc = of_mdiobus_register(bus, np);
- if (rc)
+ if (rc) {
+ dev_err(dev, Failed to register mdio bus.\n);
goto err_register;
+ }
return 0;
--
1.8.2.3
pgp50jI4XMstK.pgp
Description: PGP signature
[PATCH v2 3/6] net: emaclite: Let's make xemaclite_adjust_link static
xemaclite_adjust_link is used locally.
It removes sparse warning:
drivers/net/ethernet/xilinx/xilinx_emaclite.c:916:6: warning:
symbol 'xemaclite_adjust_link' was not declared. Should it be static?
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index fcd1e0b..93bb14e 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -913,7 +913,7 @@ err_register:
* There's nothing in the Emaclite device to be configured when the link
* state changes. We just print the status.
*/
-void xemaclite_adjust_link(struct net_device *ndev)
+static void xemaclite_adjust_link(struct net_device *ndev)
{
struct net_local *lp = netdev_priv(ndev);
struct phy_device *phy = lp-phy_dev;
--
1.8.2.3
pgpzMJ52cDLNu.pgp
Description: PGP signature
[PATCH v2 2/6] net: emaclite: Support multiple phys connected to one MDIO bus
For system which contains at least two ethernet IP where
one IP manage MDIO bus with several PHYs.
Example dts node:
ethernet_mac0: ethernet@8100 {
compatible = xlnx,xps-ethernetlite-1.00.a;
device_type = network;
interrupt-parent = xps_intc_0;
interrupts = 1 0 ;
local-mac-address = [ 00 0a 35 00 db bb ];
phy-handle = ethernet_mac0_phy0;
reg = 0x8100 0x1 ;
xlnx,duplex = 0x1;
xlnx,family = spartan3e;
xlnx,include-internal-loopback = 0x0;
xlnx,include-mdio = 0x1;
xlnx,rx-ping-pong = 0x0;
xlnx,tx-ping-pong = 0x0;
ethernet_mac0_mdio {
#address-cells = 1;
#size-cells = 0;
ethernet_mac0_phy0: phy@1 {
reg = 0x1;
} ;
ethernet_mac0_phy1: phy@3 {
reg = 0x3;
} ;
} ;
} ;
ethernet_mac2: ethernet@8104 {
compatible = xlnx,xps-ethernetlite-1.00.a;
device_type = network;
interrupt-parent = xps_intc_0;
interrupts = 11 0 ;
local-mac-address = [ 00 0a 35 00 db bb ];
phy-handle = ethernet_mac0_phy1;
reg = 0x8104 0x1 ;
xlnx,duplex = 0x1;
xlnx,family = spartan3e;
xlnx,include-internal-loopback = 0x0;
xlnx,include-mdio = 0x0;
xlnx,rx-ping-pong = 0x0;
xlnx,tx-ping-pong = 0x0;
} ;
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index a16dc35..fcd1e0b 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -848,6 +848,7 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
int rc;
struct resource res;
struct device_node *np = of_get_parent(lp-phy_node);
+ struct device_node *npp;
/* Don't register the MDIO bus if the phy_node or its parent node
* can't be found.
@@ -856,6 +857,17 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
dev_err(dev, Failed to register mdio bus.\n);
return -ENODEV;
}
+ npp = of_get_parent(np);
+
+ of_address_to_resource(npp, 0, res);
+ if (lp-ndev-mem_start != res.start) {
+ struct phy_device *phydev;
+ phydev = of_phy_find_device(lp-phy_node);
+ if (!phydev)
+ dev_info(dev,
+MDIO of the phy is not registered yet\n);
+ return 0;
+ }
/* Enable the MDIO bus by asserting the enable bit in MDIO Control
* register.
@@ -869,7 +881,6 @@ static int xemaclite_mdio_setup(struct net_local *lp,
struct device *dev)
return -ENOMEM;
}
- of_address_to_resource(np, 0, res);
snprintf(bus-id, MII_BUS_ID_SIZE, %.8llx,
(unsigned long long)res.start);
bus-priv = lp;
--
1.8.2.3
pgpjeTQ15GyBF.pgp
Description: PGP signature
[PATCH v2 6/6] net: emaclite: Update driver header
Correct email address and years. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: - s/Corrent/Correct/ in patch description drivers/net/ethernet/xilinx/xilinx_emaclite.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 9227ed7..aa14d8a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -2,9 +2,9 @@ * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. * * This is a new flat driver which is based on the original emac_lite - * driver from John Williams john.willi...@petalogix.com. + * driver from John Williams john.willi...@xilinx.com. * - * 2007-2009 (c) Xilinx, Inc. + * 2007 - 2013 (c) Xilinx, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the -- 1.8.2.3 pgpDRy2flyvPb.pgp Description: PGP signature
[PATCH v2 5/6] net: emaclite: Enable emaclite for Xilinx Arm Zynq platform
Enable emaclite for Xilinx ARM Zynq platform. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: None drivers/net/ethernet/xilinx/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xilinx/Kconfig index 122d60c..7b90a5e 100644 --- a/drivers/net/ethernet/xilinx/Kconfig +++ b/drivers/net/ethernet/xilinx/Kconfig @@ -5,7 +5,7 @@ config NET_VENDOR_XILINX bool Xilinx devices default y - depends on PPC || PPC32 || MICROBLAZE + depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ ---help--- If you have a network (Ethernet) card belonging to this class, say Y and read the Ethernet-HOWTO, available from @@ -20,7 +20,7 @@ if NET_VENDOR_XILINX config XILINX_EMACLITE tristate Xilinx 10/100 Ethernet Lite support - depends on (PPC32 || MICROBLAZE) + depends on (PPC32 || MICROBLAZE || ARCH_ZYNQ) select PHYLIB ---help--- This driver supports the 10/100 Ethernet Lite from Xilinx. -- 1.8.2.3 pgpi_jyZFtCAf.pgp Description: PGP signature
[PATCH v2 4/6] net: emaclite: Do not use microblaze and ppc IO functions
Emaclite can be used on ARM zynq where in_be32/out_be32 IO
functions are not present. Use standard __raw_readl/__raw_writel
IO functions instead.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Fix __raw_iowrite() to pass correct parameters
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 138 +-
1 file changed, 69 insertions(+), 69 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 93bb14e..9227ed7 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -159,34 +159,32 @@ static void xemaclite_enable_interrupts(struct net_local
*drvdata)
u32 reg_data;
/* Enable the Tx interrupts for the first Buffer */
- reg_data = in_be32(drvdata-base_addr + XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_TSR_OFFSET,
-reg_data | XEL_TSR_XMIT_IE_MASK);
+ reg_data = __raw_readl(drvdata-base_addr + XEL_TSR_OFFSET);
+ __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
+drvdata-base_addr + XEL_TSR_OFFSET);
/* Enable the Tx interrupts for the second Buffer if
* configured in HW */
if (drvdata-tx_ping_pong != 0) {
- reg_data = in_be32(drvdata-base_addr +
+ reg_data = __raw_readl(drvdata-base_addr +
XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
-XEL_TSR_OFFSET,
-reg_data | XEL_TSR_XMIT_IE_MASK);
+ __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
+drvdata-base_addr + XEL_BUFFER_OFFSET +
+XEL_TSR_OFFSET);
}
/* Enable the Rx interrupts for the first buffer */
- out_be32(drvdata-base_addr + XEL_RSR_OFFSET,
-XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata-base_addr + XEL_RSR_OFFSET);
/* Enable the Rx interrupts for the second Buffer if
* configured in HW */
if (drvdata-rx_ping_pong != 0) {
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
-XEL_RSR_OFFSET,
-XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata-base_addr +
+XEL_BUFFER_OFFSET + XEL_RSR_OFFSET);
}
/* Enable the Global Interrupt Enable */
- out_be32(drvdata-base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+ __raw_writel(XEL_GIER_GIE_MASK, drvdata-base_addr + XEL_GIER_OFFSET);
}
/**
@@ -201,37 +199,37 @@ static void xemaclite_disable_interrupts(struct net_local
*drvdata)
u32 reg_data;
/* Disable the Global Interrupt Enable */
- out_be32(drvdata-base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+ __raw_writel(XEL_GIER_GIE_MASK, drvdata-base_addr + XEL_GIER_OFFSET);
/* Disable the Tx interrupts for the first buffer */
- reg_data = in_be32(drvdata-base_addr + XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_TSR_OFFSET,
-reg_data (~XEL_TSR_XMIT_IE_MASK));
+ reg_data = __raw_readl(drvdata-base_addr + XEL_TSR_OFFSET);
+ __raw_writel(reg_data (~XEL_TSR_XMIT_IE_MASK),
+drvdata-base_addr + XEL_TSR_OFFSET);
/* Disable the Tx interrupts for the second Buffer
* if configured in HW */
if (drvdata-tx_ping_pong != 0) {
- reg_data = in_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ reg_data = __raw_readl(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_TSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
-XEL_TSR_OFFSET,
-reg_data (~XEL_TSR_XMIT_IE_MASK));
+ __raw_writel(reg_data (~XEL_TSR_XMIT_IE_MASK),
+drvdata-base_addr + XEL_BUFFER_OFFSET +
+XEL_TSR_OFFSET);
}
/* Disable the Rx interrupts for the first buffer */
- reg_data = in_be32(drvdata-base_addr + XEL_RSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_RSR_OFFSET,
-reg_data (~XEL_RSR_RECV_IE_MASK));
+ reg_data = __raw_readl(drvdata-base_addr + XEL_RSR_OFFSET);
+ __raw_writel(reg_data (~XEL_RSR_RECV_IE_MASK),
+drvdata-base_addr + XEL_RSR_OFFSET);
/* Disable the Rx interrupts for the second buffer
* if configured in HW */
if (drvdata-rx_ping_pong != 0) {
- reg_data = in_be32(drvdata-base_addr + XEL_BUFFER_OFFSET +
+ reg_data = __raw_readl(drvdata-base_addr + XEL_BUFFER_OFFSET +
XEL_RSR_OFFSET);
- out_be32(drvdata-base_addr + XEL_BUFFER_OFFSET
[PATCH 1/3] watchdog: xilinx: Fix driver header
- Remove reference for IP version - Fix header coding style - Remove notes which are visible from the code - Fix driver license according to header Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 30 ++ 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 2761ddb..d4a35ab 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -1,23 +1,13 @@ /* -* of_xilinx_wdt.c 1.01 A Watchdog Device Driver for Xilinx xps_timebase_wdt -* -* (C) Copyright 2011 (Alejandro Cabrera ald...@gmail.com) -* -* --- -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version -* 2 of the License, or (at your option) any later version. -* -* --- -* 30-May-2011 Alejandro Cabrera ald...@gmail.com -* - If xlnx,wdt-enable-once wasn't found on device tree the -*module will use CONFIG_WATCHDOG_NOWAYOUT -* - If the device tree parameters (clock-frequency and -*xlnx,wdt-interval) wasn't found the driver won't -*know the wdt reset interval -*/ + * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt + * + * (C) Copyright 2011 (Alejandro Cabrera ald...@gmail.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ #define pr_fmt(fmt) KBUILD_MODNAME : fmt @@ -413,5 +403,5 @@ module_platform_driver(xwdt_driver); MODULE_AUTHOR(Alejandro Cabrera ald...@gmail.com); MODULE_DESCRIPTION(Xilinx Watchdog driver); -MODULE_LICENSE(GPL); +MODULE_LICENSE(GPL v2); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- 1.8.2.3 pgpXPQSEEHfPL.pgp Description: PGP signature
[PATCH 2/3] watchdog: xilinx: Setup the origin compatible string
Watchdog 1.01.a is also compatible with 1.00.a.
Setup the origin version to compatible list.
If you want to use newer watchdog version, please
extend your compatible list.
For example:
compatible = xlnx,xps-timebase-wdt-1.02.a, xlnx,xps-timebase-wdt-1.00.a;
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/watchdog/of_xilinx_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index d4a35ab..79f358c 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -384,7 +384,7 @@ static int xwdt_remove(struct platform_device *dev)
/* Match table for of_platform binding */
static struct of_device_id xwdt_of_match[] = {
- { .compatible = xlnx,xps-timebase-wdt-1.01.a, },
+ { .compatible = xlnx,xps-timebase-wdt-1.00.a, },
{},
};
MODULE_DEVICE_TABLE(of, xwdt_of_match);
--
1.8.2.3
pgpFQ2zQgdih8.pgp
Description: PGP signature
[PATCH 3/3] watchdog: xilinx: Add WDIOC_SETTIMEOUT ioctl function
Standard watchdog programs try to setup timeout via ioctl and this functionality should be implemented. Timeout value is hardcoded in the hardware but based on Documentation/watchdog/watchdog-api.txt can return the real timeout used in the same variable. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 79f358c..a3bbe72 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -253,6 +253,7 @@ static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) xwdt_keepalive(); return 0; + case WDIOC_SETTIMEOUT: case WDIOC_GETTIMEOUT: if (no_timeout) return -ENOTTY; -- 1.8.2.3 pgpoul6MzcpNE.pgp Description: PGP signature
Re: [PATCH 1/3] watchdog: xilinx: Fix driver header
On 05/30/2013 02:30 PM, Venu Byravarasu wrote: -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- ow...@vger.kernel.org] On Behalf Of Michal Simek Sent: Thursday, May 30, 2013 5:56 PM To: linux-kernel@vger.kernel.org Cc: Michal Simek; Michal Simek; Wim Van Sebroeck; linux- watch...@vger.kernel.org Subject: [PATCH 1/3] watchdog: xilinx: Fix driver header * PGP Signed by an unknown key - Remove reference for IP version - Fix header coding style - Remove notes which are visible from the code - Fix driver license according to header Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 30 ++ 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 2761ddb..d4a35ab 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -1,23 +1,13 @@ /* -* of_xilinx_wdt.c 1.01 A Watchdog Device Driver for Xilinx xps_timebase_wdt -* -* (C) Copyright 2011 (Alejandro Cabrera ald...@gmail.com) -* -* --- -*/ + * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt + * + * (C) Copyright 2011 (Alejandro Cabrera ald...@gmail.com) Should year not be updated? This is just header fixup. I think he is not working/maintaining this driver for a long time. I would write there Xilinx copyright but I really don't care. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
[PATCH] of: Export of_irq_count for using in modules
Export of_irq_count for modules. Signed-off-by: Michal Simek michal.si...@xilinx.com --- We are using this function in remoteproc module drivers. There is also drivers/gpio/gpio-mvebu.c in the tree which use this function but this driver can't be compiled as module. This could be also the reason why is not this driver as module. --- drivers/of/irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index a3c1c5a..c918dde 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -374,6 +374,7 @@ int of_irq_count(struct device_node *dev) return nr; } +EXPORT_SYMBOL_GPL(of_irq_count); /** * of_irq_to_resource_table - Fill in resource table with node's IRQ info -- 1.8.2.3 pgpFQBBM8amt9.pgp Description: PGP signature
Re: [PATCH 2/3] watchdog: xilinx: Setup the origin compatible string
On 05/30/2013 04:00 PM, Guenter Roeck wrote:
On Thu, May 30, 2013 at 02:26:03PM +0200, Michal Simek wrote:
Watchdog 1.01.a is also compatible with 1.00.a.
Setup the origin version to compatible list.
If you want to use newer watchdog version, please
extend your compatible list.
For example:
compatible = xlnx,xps-timebase-wdt-1.02.a, xlnx,xps-timebase-wdt-1.00.a;
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/watchdog/of_xilinx_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c
b/drivers/watchdog/of_xilinx_wdt.c
index d4a35ab..79f358c 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -384,7 +384,7 @@ static int xwdt_remove(struct platform_device *dev)
/* Match table for of_platform binding */
static struct of_device_id xwdt_of_match[] = {
-{ .compatible = xlnx,xps-timebase-wdt-1.01.a, },
+{ .compatible = xlnx,xps-timebase-wdt-1.00.a, },
Is this really a good idea ? It means every existing device tree binding which
specifies 1.01a will now fail. If the code is compatible to 1.00a, I think it
would make more sense to add that to the driver as additional entry instead of
deleting the existing entry for 1.01a.
The most of users/I believe all of them are using device-tree generator
which generate DTS directly from Xilinx design tools because it is almost
impossible to write DTS for any xilinx fpga plaform and
1.00.a is setup as backward compatible property.
But if you think that it is worth to keep there 1.01.a I have no problem
with that I will keep there 1.01.a and add 1.00.a.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
Re: [PATCH 3/3] watchdog: xilinx: Add WDIOC_SETTIMEOUT ioctl function
On 05/30/2013 04:07 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 02:26:04PM +0200, Michal Simek wrote: Standard watchdog programs try to setup timeout via ioctl and this functionality should be implemented. Timeout value is hardcoded in the hardware but based on Documentation/watchdog/watchdog-api.txt can return the real timeout used in the same variable. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 79f358c..a3bbe72 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -253,6 +253,7 @@ static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) xwdt_keepalive(); return 0; +case WDIOC_SETTIMEOUT: case WDIOC_GETTIMEOUT: if (no_timeout) return -ENOTTY; Watchdog programs should check ident.options before trying to set the timeout. If they don't, there is an application bug. I don't think it is a good idea to start hacking the kernel to work around application bugs. Based on Documentation/watchdog/watchdog-api.txt For some drivers it is possible to modify the watchdog timeout on the fly with the SETTIMEOUT ioctl, those drivers have the WDIOF_SETTIMEOUT flag set in their option field. The argument is an integer representing the timeout in seconds. The driver returns the real timeout used in the same variable, and this timeout might differ from the requested one due to limitation of the hardware. int timeout = 45; ioctl(fd, WDIOC_SETTIMEOUT, timeout); printf(The timeout was set to %d seconds\n, timeout); This example might actually print The timeout was set to 60 seconds if the device has a granularity of minutes for its timeout. should be completely fine that user application is trying to setup timeout and driver should return value based on it. And yes, user application should check return value from ioctl call but still based on documentation driver can properly support it too. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH 3/3] watchdog: xilinx: Add WDIOC_SETTIMEOUT ioctl function
On 05/30/2013 04:21 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 04:15:45PM +0200, Michal Simek wrote: On 05/30/2013 04:07 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 02:26:04PM +0200, Michal Simek wrote: Standard watchdog programs try to setup timeout via ioctl and this functionality should be implemented. Timeout value is hardcoded in the hardware but based on Documentation/watchdog/watchdog-api.txt can return the real timeout used in the same variable. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 79f358c..a3bbe72 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -253,6 +253,7 @@ static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) xwdt_keepalive(); return 0; + case WDIOC_SETTIMEOUT: case WDIOC_GETTIMEOUT: if (no_timeout) return -ENOTTY; Watchdog programs should check ident.options before trying to set the timeout. If they don't, there is an application bug. I don't think it is a good idea to start hacking the kernel to work around application bugs. Based on Documentation/watchdog/watchdog-api.txt For some drivers it is possible to modify the watchdog timeout on the fly with the SETTIMEOUT ioctl, those drivers have the WDIOF_SETTIMEOUT flag set in their option field. The argument is an integer Yes, but WDIOF_SETTIMEOUT is not set in the driver's option field. ok. It means I should probably enable it. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH 3/3] watchdog: xilinx: Add WDIOC_SETTIMEOUT ioctl function
On 05/30/2013 05:03 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 04:34:02PM +0200, Michal Simek wrote: On 05/30/2013 04:21 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 04:15:45PM +0200, Michal Simek wrote: On 05/30/2013 04:07 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 02:26:04PM +0200, Michal Simek wrote: Standard watchdog programs try to setup timeout via ioctl and this functionality should be implemented. Timeout value is hardcoded in the hardware but based on Documentation/watchdog/watchdog-api.txt can return the real timeout used in the same variable. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 79f358c..a3bbe72 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -253,6 +253,7 @@ static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) xwdt_keepalive(); return 0; +case WDIOC_SETTIMEOUT: case WDIOC_GETTIMEOUT: if (no_timeout) return -ENOTTY; Watchdog programs should check ident.options before trying to set the timeout. If they don't, there is an application bug. I don't think it is a good idea to start hacking the kernel to work around application bugs. Based on Documentation/watchdog/watchdog-api.txt For some drivers it is possible to modify the watchdog timeout on the fly with the SETTIMEOUT ioctl, those drivers have the WDIOF_SETTIMEOUT flag set in their option field. The argument is an integer Yes, but WDIOF_SETTIMEOUT is not set in the driver's option field. ok. It means I should probably enable it. I am missing your point. Applications should not try to write the timeout since WDIOF_SETTIMEOUT is not set. Any application doing it anyway is buggy and should be fixed. I fully understand your points and 100% agree with you 1. the application is broken and should be fixed 2. also the kernel shouldn't fix any problem with stupid application But based on documentation the driver can support setup timeout and based on description the driver returns the real timeout used in the same variable and this timeout might differ from the requested one due to limitation of the hardware Based on this I still think that the driver can support set timeout feature and if the driver supports this option then WDIOF_SETTIMEOUT should be set in driver's option field. And I would add this to v2. Can you see my point now? Or my point of view is completely incorrect that this driver can't support set timeout option. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v2 0/5] Zynq: revised CCF code
On 05/30/2013 08:44 PM, Mike Turquette wrote: Quoting Michal Simek (2013-05-17 05:14:47) Hi Mike, I have sent email to Greg to take this patch from this series though his serial tree because it is unrelated to this clock stuff. Can you please give me your ACK for these patches or add them to your CLK tree? For the four clock-related patches: Acked-by: Mike Turquette mturque...@linaro.org I have already sent pull request to Arnd and Olof. Or is it you who should take these patches through your tree? Thanks. Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH 1/2] GPIO: Add support for dual channel in gpio-xilinx.c
Hi Linus,
On 05/30/2013 09:46 PM, Linus Walleij wrote:
On Wed, May 29, 2013 at 1:27 PM, Michal Simek michal.si...@xilinx.com wrote:
Supporting the second channel in the driver.
Offset is 0x8 and both channnels share the same
IRQ.
Signed-off-by: Michal Simek michal.si...@xilinx.com
(...)
+/* Read/Write access to the GPIO registers */
+#define xgpio_readreg(offset) __raw_readl(offset)
+#define xgpio_writereg(offset, val)__raw_writel(val, offset)
So you're swithing in_be32/out_be32 to the CPU-dependent
__raw_readl/__raw_writel functions? Why?
The reason is that this driver can be used on ARM where in_be32/out_be32
is not implemented.
Can you explain exactly why you are using __raw_* accessors
rather than e.g. atleast readl_relaxed()/writel_relaxed()
or even plain readl/writel so you know the writes will hit
the hardware as immediately as possible?
Using __raw* function ensure that it is working on all
cpus. Microblaze big/little endian, PPC big endian and ARM little endian.
The correct way how to implement this is based on my previous
discussion to detect endians directly on IP.
But for this gpio case without interrupt connected(it means without
interrupt logic) there are just 2 registers data and tristate
(http://www.xilinx.com/support/documentation/ip_documentation/axi_gpio/v1_01_b/ds744_axi_gpio.pdf)
and auto detection can't be done.
I'd prefer this step to be a separate patch.
ok. Will do based on my discussion around xilinxfb.
struct xgpio_instance {
struct of_mm_gpio_chip mmchip;
u32 gpio_state; /* GPIO state shadow register */
u32 gpio_dir; /* GPIO direction shadow register */
+ u32 offset;
spinlock_t gpio_lock; /* Lock used for synchronization */
};
Why not take this opportunity to move the comments out to
kerneldoc above this struct, plus document what offset
means.
Good point. Will fix.
- return (in_be32(mm_gc-regs + XGPIO_DATA_OFFSET) gpio) 1;
+ return (xgpio_readreg(regs + XGPIO_DATA_OFFSET) gpio) 1;
Another way would be:
#include linux/bitops.h
return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET BIT(gpio));
+
+ pr_info(XGpio: %s: registered, base is %d\n, np-full_name,
+
chip-mmchip.gc.base);
+
+ tree_info = of_get_property(np, xlnx,is-dual, NULL);
This looks like you want to use of_property_read_bool().
Ah yeah.
Have you documented these new bindings? It doesn't seem so.
Documentation/devicetree/bindings/gpio/*...
If it's undocumented so far, this is a good oppotunity to add it.
Isn't it enough what it is in 2/2?
Or do you want to describe current binding in the first patch
and then extend it in this patch when dual channel is added?
+ if (tree_info be32_to_cpup(tree_info)) {
+ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ /* Add dual channel offset */
+ chip-offset = XGPIO_CHANNEL_OFFSET;
+
+ /* Update GPIO state shadow register with default value */
+ tree_info = of_get_property(np, xlnx,dout-default-2, NULL);
+ if (tree_info)
+ chip-gpio_state = be32_to_cpup(tree_info);
This is basically a jam table (hardware set-up) in the device tree.
Not sure what you mean by that. Xilinx GPIO is soft IP which can be configured
to different configurations before bitstream is generated.
At the end you will get different setting/addresses setup for every pin
which is described by these xlnx,X descriptions.
I don't exactly like this. Is this necessary?
If you mean names or values in there that all of them are autogenerated
from design tools and they are reflect IP hardware description and all
configuration options which you can have there.
It means that all these values give you exact hardware description.
Do I answer your question?
+ /* Update GPIO direction shadow register with default value
*/
+ /* By default, all pins are inputs */
+ chip-gpio_dir = 0x;
+ tree_info = of_get_property(np, xlnx,tri-default-2, NULL);
+ if (tree_info)
+ chip-gpio_dir = be32_to_cpup(tree_info);
Dito.
+ /* Check device node and parent device node for device width
*/
+ /* By default assume full GPIO controller */
+ chip-mmchip.gc.ngpio = 32;
+ tree_info = of_get_property(np, xlnx,gpio2-width, NULL);
+ if (tree_info)
+ chip-mmchip.gc.ngpio = be32_to_cpup(tree_info);
Seems fine, but document it in the binding.
I will look at new fdt function to shorten this code to look better.
Thanks for your review,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p
Re: [PATCH 3/3] watchdog: xilinx: Add WDIOC_SETTIMEOUT ioctl function
On 05/31/2013 12:08 AM, Wim Van Sebroeck wrote: Hi All, On Thu, May 30, 2013 at 05:12:24PM +0200, Michal Simek wrote: On 05/30/2013 05:03 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 04:34:02PM +0200, Michal Simek wrote: On 05/30/2013 04:21 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 04:15:45PM +0200, Michal Simek wrote: On 05/30/2013 04:07 PM, Guenter Roeck wrote: On Thu, May 30, 2013 at 02:26:04PM +0200, Michal Simek wrote: Standard watchdog programs try to setup timeout via ioctl and this functionality should be implemented. Timeout value is hardcoded in the hardware but based on Documentation/watchdog/watchdog-api.txt can return the real timeout used in the same variable. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/watchdog/of_xilinx_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 79f358c..a3bbe72 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -253,6 +253,7 @@ static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) xwdt_keepalive(); return 0; + case WDIOC_SETTIMEOUT: case WDIOC_GETTIMEOUT: if (no_timeout) return -ENOTTY; Watchdog programs should check ident.options before trying to set the timeout. If they don't, there is an application bug. I don't think it is a good idea to start hacking the kernel to work around application bugs. Based on Documentation/watchdog/watchdog-api.txt For some drivers it is possible to modify the watchdog timeout on the fly with the SETTIMEOUT ioctl, those drivers have the WDIOF_SETTIMEOUT flag set in their option field. The argument is an integer Yes, but WDIOF_SETTIMEOUT is not set in the driver's option field. ok. It means I should probably enable it. I am missing your point. Applications should not try to write the timeout since WDIOF_SETTIMEOUT is not set. Any application doing it anyway is buggy and should be fixed. I fully understand your points and 100% agree with you 1. the application is broken and should be fixed 2. also the kernel shouldn't fix any problem with stupid application But based on documentation the driver can support setup timeout and based on description the driver returns the real timeout used in the same variable and this timeout might differ from the requested one due to limitation of the hardware Based on this I still think that the driver can support set timeout feature and if the driver supports this option then WDIOF_SETTIMEOUT should be set in driver's option field. And I would add this to v2. Can you see my point now? No. The driver doesn't support setting the timeout. You just want it to falsely claim that it does to work around an application problem. With your logic, _every_ watchdog driver would support setting the timeout. I don't want to falsely claim anything. I am just saying this is written in the documentation and it is my understanding that this can be implemented it this way for this xilinx device and behaviour of the driver will be correct according to documentation which I copied to this thread. If Wim says that if device doesn't support setting timeout in HW then this ioctl can't be implemented in this way I am definitely OK with it. And I will remove this patch and will also remove this change from our xilinx repo. The main purpose for me is to cleanup our repo and push all changes to the mainline. Of course if this change goes against watchdog logic and it is broken I will the first who will revert it in our repo and will have proper description based on our discussion. I really appreciate your inputs for this discussion and both resolution ACK/NACK are OK because I will know what's the correct way and I can fix it in mainline or our repo and both will be in sync. Logic is: if device supports setting timeout values, then and only then you indicate this by setting the WDIOF_SETTIMEOUT flag and adding the code for it. And then you can do minor adjustments if needed and report this back. But that's only to make sure that some roundings (like a timer in minutes gives back 60 or 120 seconds if you would set a new timeout of 70 seconds). So in this case: the HW doesn't support setting timeout values, so we don't add the WDIOF_SETTIMEOUT flag and thus we don't add the ioctl call neither. So NACK on this patch. ok. Good. I will revert this change in our tree and will send v2 without it. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
[PATCH v2 0/2] Xilinx watchdog changes
The patchset fixes license header and add 1.00.a IP to compatible list. Thanks for your review, Michal Remove the 3rd patch from this series which incorrectly tried to support set timeout feature. Changes in v2: - Extend compatible list with 1.00.a instead of replacing 1.01.a reported by Guenter Roeck li...@roeck-us.net Michal Simek (2): watchdog: xilinx: Fix driver header watchdog: xilinx: Setup the origin compatible string drivers/watchdog/of_xilinx_wdt.c | 31 +++ 1 file changed, 11 insertions(+), 20 deletions(-) -- 1.8.2.3 pgp1hHJVTULbz.pgp Description: PGP signature
[PATCH v2 1/2] watchdog: xilinx: Fix driver header
- Remove reference for IP version - Fix header coding style - Remove notes which are visible from the code - Fix driver license according to header Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: None drivers/watchdog/of_xilinx_wdt.c | 30 ++ 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c index 2761ddb..d4a35ab 100644 --- a/drivers/watchdog/of_xilinx_wdt.c +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -1,23 +1,13 @@ /* -* of_xilinx_wdt.c 1.01 A Watchdog Device Driver for Xilinx xps_timebase_wdt -* -* (C) Copyright 2011 (Alejandro Cabrera ald...@gmail.com) -* -* --- -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version -* 2 of the License, or (at your option) any later version. -* -* --- -* 30-May-2011 Alejandro Cabrera ald...@gmail.com -* - If xlnx,wdt-enable-once wasn't found on device tree the -*module will use CONFIG_WATCHDOG_NOWAYOUT -* - If the device tree parameters (clock-frequency and -*xlnx,wdt-interval) wasn't found the driver won't -*know the wdt reset interval -*/ + * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt + * + * (C) Copyright 2011 (Alejandro Cabrera ald...@gmail.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ #define pr_fmt(fmt) KBUILD_MODNAME : fmt @@ -413,5 +403,5 @@ module_platform_driver(xwdt_driver); MODULE_AUTHOR(Alejandro Cabrera ald...@gmail.com); MODULE_DESCRIPTION(Xilinx Watchdog driver); -MODULE_LICENSE(GPL); +MODULE_LICENSE(GPL v2); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- 1.8.2.3 pgpAN_631E_Zq.pgp Description: PGP signature
[PATCH v2 2/2] watchdog: xilinx: Setup the origin compatible string
Watchdog 1.01.a is also compatible with 1.00.a.
Add the origin version to compatible list.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Extend compatible list with 1.00.a instead of replacing 1.01.a
reported by Guenter Roeck li...@roeck-us.net
drivers/watchdog/of_xilinx_wdt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index d4a35ab..4dd281f 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -384,6 +384,7 @@ static int xwdt_remove(struct platform_device *dev)
/* Match table for of_platform binding */
static struct of_device_id xwdt_of_match[] = {
+ { .compatible = xlnx,xps-timebase-wdt-1.00.a, },
{ .compatible = xlnx,xps-timebase-wdt-1.01.a, },
{},
};
--
1.8.2.3
pgpbydtlPcv7T.pgp
Description: PGP signature
[PATCH v2 0/5] Phylib changes
We have these changes in our tree for quite a long time and I would like to ask you for review. All phys are used on xilinx zynq boards. Thanks, Michal v2: Resent these phy patches without emaclite changes Changes in v2: - None Michal Simek (5): phy: Clean coding style in vitesse phy phy: Add Vitesse 8211 phy ID phy: Use macros instead of hardcoded values in marvell phy driver phy: Add Marvell 88E1116R phy ID phy: Add Marvell 88E1510 phy ID drivers/net/phy/marvell.c | 108 drivers/net/phy/vitesse.c | 38 +++- include/linux/marvell_phy.h | 2 + 3 files changed, 127 insertions(+), 21 deletions(-) -- 1.8.2.3 pgpFXymEZvt_h.pgp Description: PGP signature
[PATCH v2 3/5] phy: Use macros instead of hardcoded values in marvell phy driver
Use macros from linux/marvell_phy.h instead of duplicate
magic phy ID in the driver.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/phy/marvell.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 202fe1f..371353c 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -958,15 +958,15 @@ module_init(marvell_init);
module_exit(marvell_exit);
static struct mdio_device_id __maybe_unused marvell_tbl[] = {
- { 0x01410c60, 0xfff0 },
- { 0x01410c90, 0xfff0 },
- { 0x01410cc0, 0xfff0 },
- { 0x01410e10, 0xfff0 },
- { 0x01410cb0, 0xfff0 },
- { 0x01410cd0, 0xfff0 },
- { 0x01410e50, 0xfff0 },
- { 0x01410e30, 0xfff0 },
- { 0x01410e90, 0xfff0 },
+ { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
{ }
};
--
1.8.2.3
pgpkvHuFSjwFb.pgp
Description: PGP signature
[PATCH v2 4/5] phy: Add Marvell 88E1116R phy ID
This phy is on Xilinx ZC702 zynq development board.
Signed-off-by: Anirudha Sarangi anir...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/phy/marvell.c | 65 +
include/linux/marvell_phy.h | 1 +
2 files changed, 66 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 371353c..df5a9f6 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -116,6 +116,8 @@
#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_STATUS_LINK 0x0400
+#define MII_M1116R_CONTROL_REG_MAC 21
+
MODULE_DESCRIPTION(Marvell PHY driver);
MODULE_AUTHOR(Andy Fleming);
@@ -372,6 +374,55 @@ static int m88e1318_config_aneg(struct phy_device *phydev)
return m88e1121_config_aneg(phydev);
}
+static int m88e1116r_config_init(struct phy_device *phydev)
+{
+ int temp;
+ int err;
+
+ temp = phy_read(phydev, MII_BMCR);
+ temp |= BMCR_RESET;
+ err = phy_write(phydev, MII_BMCR, temp);
+ if (err 0)
+ return err;
+
+ mdelay(500);
+
+ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
+ if (err 0)
+ return err;
+
+ temp = phy_read(phydev, MII_M1011_PHY_SCR);
+ temp |= (7 12); /* max number of gigabit attempts */
+ temp |= (1 11); /* enable downshift */
+ temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
+ err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
+ if (err 0)
+ return err;
+
+ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
+ if (err 0)
+ return err;
+ temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
+ temp |= (1 5);
+ temp |= (1 4);
+ err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
+ if (err 0)
+ return err;
+ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
+ if (err 0)
+ return err;
+
+ temp = phy_read(phydev, MII_BMCR);
+ temp |= BMCR_RESET;
+ err = phy_write(phydev, MII_BMCR, temp);
+ if (err 0)
+ return err;
+
+ mdelay(500);
+
+ return 0;
+}
+
static int m88e_config_init(struct phy_device *phydev)
{
int err;
@@ -940,6 +991,19 @@ static struct phy_driver marvell_drivers[] = {
.config_intr = marvell_config_intr,
.driver = { .owner = THIS_MODULE },
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E1116R,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = Marvell 88E1116R,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = m88e1116r_config_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = marvell_ack_interrupt,
+ .config_intr = marvell_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ },
};
static int __init marvell_init(void)
@@ -967,6 +1031,7 @@ static struct mdio_device_id __maybe_unused marvell_tbl[]
= {
{ MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
{ }
};
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index dd3c34e..ec41025 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -14,6 +14,7 @@
#define MARVELL_PHY_ID_88E1149R0x01410e50
#define MARVELL_PHY_ID_88E1240 0x01410e30
#define MARVELL_PHY_ID_88E1318S0x01410e90
+#define MARVELL_PHY_ID_88E1116R0x01410e40
/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x0001
--
1.8.2.3
pgpaDJlHQEQou.pgp
Description: PGP signature
[PATCH v2 5/5] phy: Add Marvell 88E1510 phy ID
Add support for this new phy ID.
Signed-off-by: Rick Hoover rhoo...@digilentinc.com
Signed-off-by: Steven Wang steven.w...@digilentinc.com
Signed-off-by: Lars-Peter Clausen l...@metafoo.de
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- None
drivers/net/phy/marvell.c | 25 +
include/linux/marvell_phy.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index df5a9f6..2e91477 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -374,6 +374,17 @@ static int m88e1318_config_aneg(struct phy_device *phydev)
return m88e1121_config_aneg(phydev);
}
+static int m88e1510_config_aneg(struct phy_device *phydev)
+{
+ int err;
+
+ err = m88e1318_config_aneg(phydev);
+ if (err 0)
+ return err;
+
+ return marvell_of_reg_init(phydev);
+}
+
static int m88e1116r_config_init(struct phy_device *phydev)
{
int temp;
@@ -1004,6 +1015,19 @@ static struct phy_driver marvell_drivers[] = {
.config_intr = marvell_config_intr,
.driver = { .owner = THIS_MODULE },
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E1510,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = Marvell 88E1510,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_aneg = m88e1510_config_aneg,
+ .read_status = marvell_read_status,
+ .ack_interrupt = marvell_ack_interrupt,
+ .config_intr = marvell_config_intr,
+ .did_interrupt = m88e1121_did_interrupt,
+ .driver = { .owner = THIS_MODULE },
+ },
};
static int __init marvell_init(void)
@@ -1032,6 +1056,7 @@ static struct mdio_device_id __maybe_unused marvell_tbl[]
= {
{ MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
{ }
};
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index ec41025..8e9a029 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -15,6 +15,7 @@
#define MARVELL_PHY_ID_88E1240 0x01410e30
#define MARVELL_PHY_ID_88E1318S0x01410e90
#define MARVELL_PHY_ID_88E1116R0x01410e40
+#define MARVELL_PHY_ID_88E1510 0x01410dd0
/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x0001
--
1.8.2.3
pgpr2ffY9IJdS.pgp
Description: PGP signature
[PATCH v2 2/5] phy: Add Vitesse 8211 phy ID
Phy is compatible with Vitesse 8221.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/phy/vitesse.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index d6e988f..69b482b 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -56,6 +56,7 @@
#define PHY_ID_VSC8244 0x000fc6c0
#define PHY_ID_VSC8221 0x000fc550
+#define PHY_ID_VSC8211 0x000fc4b0
MODULE_DESCRIPTION(Vitesse PHY driver);
MODULE_AUTHOR(Kriston Carson);
@@ -175,6 +176,19 @@ static struct phy_driver vsc82xx_driver[] = {
.ack_interrupt = vsc824x_ack_interrupt,
.config_intr= vsc82xx_config_intr,
.driver = { .owner = THIS_MODULE,},
+}, {
+ /* Vitesse 8211 */
+ .phy_id = PHY_ID_VSC8211,
+ .phy_id_mask= 0x0000,
+ .name = Vitesse VSC8211,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init= vsc8221_config_init,
+ .config_aneg= genphy_config_aneg,
+ .read_status= genphy_read_status,
+ .ack_interrupt = vsc824x_ack_interrupt,
+ .config_intr= vsc82xx_config_intr,
+ .driver = { .owner = THIS_MODULE,},
} };
static int __init vsc82xx_init(void)
@@ -195,6 +209,7 @@ module_exit(vsc82xx_exit);
static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
{ PHY_ID_VSC8244, 0x000fffc0 },
{ PHY_ID_VSC8221, 0x0000 },
+ { PHY_ID_VSC8211, 0x0000 },
{ }
};
--
1.8.2.3
pgpATbmSfPx1S.pgp
Description: PGP signature
[PATCH v2 1/5] phy: Clean coding style in vitesse phy
- Remove trailing white space
- Remove spaces before tag
- Fix comments
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/net/phy/vitesse.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 3492b53..d6e988f 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -44,12 +44,12 @@
#define MII_VSC8244_ISTAT_DUPLEX 0x1000
/* Vitesse Auxiliary Control/Status Register */
-#define MII_VSC8244_AUX_CONSTAT0x1c
-#define MII_VSC8244_AUXCONSTAT_INIT0x
-#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
-#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
-#define MII_VSC8244_AUXCONSTAT_GBIT0x0010
-#define MII_VSC8244_AUXCONSTAT_100 0x0008
+#define MII_VSC8244_AUX_CONSTAT0x1c
+#define MII_VSC8244_AUXCONSTAT_INIT0x
+#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
+#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
+#define MII_VSC8244_AUXCONSTAT_GBIT0x0010
+#define MII_VSC8244_AUXCONSTAT_100 0x0008
#define MII_VSC8221_AUXCONSTAT_INIT0x0004 /* need to set this bit? */
#define MII_VSC8221_AUXCONSTAT_RESERVED0x0004
@@ -100,9 +100,8 @@ static int vsc824x_config_init(struct phy_device *phydev)
static int vsc824x_ack_interrupt(struct phy_device *phydev)
{
int err = 0;
-
- /*
-* Don't bother to ACK the interrupts if interrupts
+
+ /* Don't bother to ACK the interrupts if interrupts
* are disabled. The 824x cannot clear the interrupts
* if they are disabled.
*/
@@ -122,8 +121,7 @@ static int vsc82xx_config_intr(struct phy_device *phydev)
MII_VSC8244_IMASK_MASK :
MII_VSC8221_IMASK_MASK);
else {
- /*
-* The Vitesse PHY cannot clear the interrupt
+ /* The Vitesse PHY cannot clear the interrupt
* once it has disabled them, so we clear them first
*/
err = phy_read(phydev, MII_VSC8244_ISTAT);
@@ -146,7 +144,8 @@ static int vsc8221_config_init(struct phy_device *phydev)
return err;
/* Perhaps we should set EXT_CON1 based on the interface?
- Options are 802.3Z SerDes or SGMII */
+* Options are 802.3Z SerDes or SGMII
+*/
}
/* Vitesse 824x */
--
1.8.2.3
pgpJxdTBFfTaF.pgp
Description: PGP signature
Re: [PATCH v2 0/5] Zynq: revised CCF code
On 05/31/2013 08:32 AM, Mike Turquette wrote: Quoting Michal Simek (2013-05-30 22:17:59) On 05/30/2013 08:44 PM, Mike Turquette wrote: Quoting Michal Simek (2013-05-17 05:14:47) Hi Mike, I have sent email to Greg to take this patch from this series though his serial tree because it is unrelated to this clock stuff. Can you please give me your ACK for these patches or add them to your CLK tree? For the four clock-related patches: Acked-by: Mike Turquette mturque...@linaro.org I have already sent pull request to Arnd and Olof. Or is it you who should take these patches through your tree? Either way is fine. Since you have already sent the pull request to the arm-soc tree then that is probably the best path. ok. I will keep my eyes on it. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH 1/2] GPIO: Add support for dual channel in gpio-xilinx.c
On 05/31/2013 09:14 AM, Linus Walleij wrote: On Fri, May 31, 2013 at 7:43 AM, Michal Simek mon...@monstr.eu wrote: On 05/30/2013 09:46 PM, Linus Walleij wrote: (...) +/* Read/Write access to the GPIO registers */ +#define xgpio_readreg(offset) __raw_readl(offset) +#define xgpio_writereg(offset, val)__raw_writel(val, offset) So you're swithing in_be32/out_be32 to the CPU-dependent __raw_readl/__raw_writel functions? Why? The reason is that this driver can be used on ARM where in_be32/out_be32 is not implemented. OK I buy this (and the following explanation). I think readl/writel is always in LE (PCI) endianness anyway, which is likely not what you want. (I suspect the next point was about that.) readl/writel yes it is all the time little endian but __raw_readl/__raw_writel is just *(u32 *)ptr access without any endian checking and barriers. Probably the best way how to handle is to write #ifdef ARCH_ZYNQ # define xgpio_readreg(offset) readl(offset) # define xgpio_writereg(offset, val)writel(val, offset) #else # define xgpio_readreg(offset) __raw_readl(offset) # define xgpio_writereg(offset, val)__raw_writel(val, offset) #endif But still it is not correct in sense that I shouldn't pretend that __raw_readl is ok to run on ppc and microblaze big endian. But using another ifdef BIG_ENDIAN or ARCH don't improve it. If there is one more register which I can use for autodetection, it will be easy to choose but that's not this case. Have you documented these new bindings? It doesn't seem so. Documentation/devicetree/bindings/gpio/*... If it's undocumented so far, this is a good oppotunity to add it. Isn't it enough what it is in 2/2? I didn't see 2/2, I guess I wasn't on CC... Anyway I guess it's this: http://marc.info/?l=linux-kernelm=136982686732560w=2 Yes. it is. I am using patman and you are probably not listed in MAINTAINERS for this folder to automatically add you. Will add you manually. It's OK, but fix the boolean member so as to just needing to be present: xlnx,is-dual; Rather than xlnx,is-dual = 1; Surely I can do it but it means to change our BSP and because this IP is used on Microblaze from beginning this change breaks all DTSes from past. That's why I would prefer not to change logic here because it just breaks all Microblaze DTSes which were generated till this change (All of them contains xlnx,is-dual = 0 if dual channel is not used). I will definitely look at dt function in the whole driver and use the Or do you want to describe current binding in the first patch and then extend it in this patch when dual channel is added? Nah. 2/2 is fine. ok. This is basically a jam table (hardware set-up) in the device tree. Not sure what you mean by that. Xilinx GPIO is soft IP which can be configured to different configurations before bitstream is generated. At the end you will get different setting/addresses setup for every pin which is described by these xlnx,X descriptions. I don't exactly like this. Is this necessary? If you mean names or values in there that all of them are autogenerated from design tools and they are reflect IP hardware description and all configuration options which you can have there. It means that all these values give you exact hardware description. Do I answer your question? Yes, this is OK, I buy that explanation. I thought it was something else. ok I think the overall problem is that I do not understand what a channel is in this context, and thus it is hard to understand the patch as a whole. 2/2 could add some more verbose explanation about the HW IP so I get comfortable and can understand the whole hardware block... ok. Good. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v2 2/3] video: xilinxfb: Do not use out_be32 IO function
On 05/31/2013 12:04 AM, Arnd Bergmann wrote:
On Thursday 30 May 2013 11:41:01 Michal Simek wrote:
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
-static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
if (drvdata-flags PLB_ACCESS_FLAG)
- out_be32(drvdata-regs + (offset 2), val);
+ __raw_writel(val, drvdata-regs + (offset 2));
#ifdef CONFIG_PPC_DCR
else
dcr_write(drvdata-dcr_host, offset, val);
This is probably missing barriers, and is wrong on systems on which
the endianess of the device is different from the CPU.
You already have an indirection in there, so I guess it won't hurt
to create a third case for little-endian registers and add
another bit in drvdata-flags, or make it depend on the architecture,
if the endianess of the device registers is known at compile time.
The PLB_ACCESS_FLAGS is incorrectly named. It means BUS_ACCESS.
But I will find a way how to autodetect endianess directly on IP
as I have done it for uartlite and will send v3.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
Re: [PATCH] of: Export of_irq_count for using in modules
Hi Jean-Christophe,
On 05/30/2013 10:17 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:49 Thu 30 May , Michal Simek wrote:
Export of_irq_count for modules.
can you explain why do you need to call of_irq_count
I need to count number of irq written in the DTS node.
It is not fixed size that's why I need to proper way how to
find it out.
I am using this loop.
count = of_irq_count(pdev-dev.of_node);
/* Alloc IRQ based on DTS to be sure that no other driver will use it */
while (count--) {
tmp-irq = irq_of_parse_and_map(pdev-dev.of_node, count);
dev_info(pdev-dev, %d: Alloc irq: %d\n, count, tmp-irq);
ret = request_irq(tmp-irq, zynq_remoteproc_interrupt, 0,
dev_name(pdev-dev), pdev-dev);
if (ret) {
...
}
}
But of course if you think that this is incorrect to export it
I can use what it is in of_irq_count body
368 int of_irq_count(struct device_node *dev)
369 {
370 int nr = 0;
371
372 while (of_irq_to_resource(dev, nr, NULL))
373 nr++;
374
375 return nr;
376 }
Because of_irq_to_resource is exported for modules.
Or is there any better way how to loop over all interrupts in DT node?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
[PATCH v3 0/8] xilinxfb changes
Hi, I have done more changes in the driver to support probing on little and big endian system where detection is done directly on the hardware. I have also done some cleanups to get it to the better shape. Thanks for your review, Michal Changes in v3: - Remove out_be IO name from function name - Change patch subject from Do not use out_be32 IO function to Do not name out_be32 in function name - New patch in this patchset based on discussions - New patch in this patchset based on discussions - New patch in this patchset - New patch in this patchset based on discussions - New patch in this patchset Changes in v2: - use of_property_read_u32 helper function Series-changes: 3 - fix commit message Michal Simek (8): video: xilinxfb: Fix OF probing on little-endian systems video: xilinxfb: Do not name out_be32 in function name video: xilinxfb: Rename PLB_ACCESS_FLAG to BUS_ACCESS_FLAG video: xilinxfb: Use drvdata-regs_phys instead of physaddr video: xilinxfb: Group bus initialization video: xilinxfb: Add support for little endian accesses video: xilinxfb: Fix sparse warnings video: xilinxfb: Use driver for Xilinx ARM Zynq drivers/video/Kconfig| 2 +- drivers/video/xilinxfb.c | 157 --- 2 files changed, 81 insertions(+), 78 deletions(-) -- 1.8.2.3 pgpXShAapng0o.pgp Description: PGP signature
[PATCH v3 2/8] video: xilinxfb: Do not name out_be32 in function name
out_be32 IO function is not supported by ARM.
It is only available for PPC and Microblaze.
Because this driver can be used on ARM let's
remove out_be32 from function name.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- Remove out_be IO name from function name
- Change patch subject from Do not use out_be32 IO function
to Do not name out_be32 in function name
Changes in v2: None
drivers/video/xilinxfb.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index aecd15d..c9b442b 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -57,7 +57,7 @@
* In case of direct PLB access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
- * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
+ * xilinx_fb_out32 where it left shifts the offset 2 times in case of
* direct PLB access.
*/
#define NUM_REGS 2
@@ -150,7 +150,7 @@ struct xilinxfb_drvdata {
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
-static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
if (drvdata-flags PLB_ACCESS_FLAG)
@@ -197,7 +197,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* turn on panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
+ xilinx_fb_out32(drvdata, REG_CTRL, drvdata-reg_ctrl_default);
break;
case FB_BLANK_NORMAL:
@@ -205,7 +205,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
/* turn off panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
default:
break;
@@ -280,13 +280,13 @@ static int xilinxfb_assign(struct device *dev,
memset_io((void __iomem *)drvdata-fb_virt, 0, fbsize);
/* Tell the hardware where the frame buffer is */
- xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
/* Turn on the display */
drvdata-reg_ctrl_default = REG_CTRL_ENABLE;
if (pdata-rotate_screen)
drvdata-reg_ctrl_default |= REG_CTRL_ROTATE;
- xilinx_fb_out_be32(drvdata, REG_CTRL,
+ xilinx_fb_out32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
/* Fill struct fb_info */
@@ -345,7 +345,7 @@ err_cmap:
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
err_fbmem:
if (drvdata-flags PLB_ACCESS_FLAG)
@@ -381,7 +381,7 @@ static int xilinxfb_release(struct device *dev)
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
if (drvdata-flags PLB_ACCESS_FLAG) {
--
1.8.2.3
pgppN2Vb1bULU.pgp
Description: PGP signature
[PATCH v3 8/8] video: xilinxfb: Use driver for Xilinx ARM Zynq
From: Michal Simek mon...@monstr.eu Enable this driver for all Xilinx platforms. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v3: None Changes in v2: None drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2e937bd..2c301f8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2188,7 +2188,7 @@ config FB_PS3_DEFAULT_SIZE_M config FB_XILINX tristate Xilinx frame buffer support - depends on FB (XILINX_VIRTEX || MICROBLAZE) + depends on FB (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.8.2.3 pgpYw_GZk9bXf.pgp Description: PGP signature
[PATCH v3 1/8] video: xilinxfb: Fix OF probing on little-endian systems
From: Michal Simek mon...@monstr.eu
DTB is always big-endian that's why it is necessary
to properly convert value (*p).
It is automatically done in of_property_read_u32().
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3: None
Changes in v2:
- use of_property_read_u32 helper function
Series-changes: 3
- fix commit message
drivers/video/xilinxfb.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index af0b4fd..aecd15d 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -406,8 +406,7 @@ static int xilinxfb_release(struct device *dev)
static int xilinxfb_of_probe(struct platform_device *op)
{
const u32 *prop;
- u32 *p;
- u32 tft_access;
+ u32 tft_access = 0;
struct xilinxfb_platform_data pdata;
struct resource res;
int size, rc;
@@ -427,8 +426,8 @@ static int xilinxfb_of_probe(struct platform_device *op)
* To check whether the core is connected directly to DCR or PLB
* interface and initialize the tft_access accordingly.
*/
- p = (u32 *)of_get_property(op-dev.of_node, xlnx,dcr-splb-slave-if,
NULL);
- tft_access = p ? *p : 0;
+ of_property_read_u32(op-dev.of_node, xlnx,dcr-splb-slave-if,
+tft_access);
/*
* Fill the resource structure if its direct PLB interface
--
1.8.2.3
pgpQ4YPAhStRO.pgp
Description: PGP signature
[PATCH v3 3/8] video: xilinxfb: Rename PLB_ACCESS_FLAG to BUS_ACCESS_FLAG
Using only PLB name is wrong for a long time because
the same access functions are also used for AXI.
s/PLB/BUS/g
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this patchset based on discussions
Changes in v2: None
drivers/video/xilinxfb.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index c9b442b..d94c992 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -44,7 +44,7 @@
/*
- * Xilinx calls it PLB TFT LCD Controller though it can also be used for
+ * Xilinx calls it TFT LCD Controller though it can also be used for
* the VGA port on the Xilinx ML40x board. This is a hardware display
* controller for a 640x480 resolution TFT or VGA screen.
*
@@ -54,11 +54,11 @@
* don't start thinking about scrolling). The second allows the LCD to
* be turned on or off as well as rotated 180 degrees.
*
- * In case of direct PLB access the second control register will be at
+ * In case of direct BUS access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
* xilinx_fb_out32 where it left shifts the offset 2 times in case of
- * direct PLB access.
+ * direct BUS access.
*/
#define NUM_REGS 2
#define REG_FB_ADDR0
@@ -116,7 +116,7 @@ static struct fb_var_screeninfo xilinx_fb_var = {
};
-#define PLB_ACCESS_FLAG0x1 /* 1 = PLB, 0 = DCR */
+#define BUS_ACCESS_FLAG0x1 /* 1 = BUS, 0 = DCR */
struct xilinxfb_drvdata {
@@ -146,14 +146,14 @@ struct xilinxfb_drvdata {
container_of(_info, struct xilinxfb_drvdata, info)
/*
- * The XPS TFT Controller can be accessed through PLB or DCR interface.
+ * The XPS TFT Controller can be accessed through BUS or DCR interface.
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
out_be32(drvdata-regs + (offset 2), val);
#ifdef CONFIG_PPC_DCR
else
@@ -235,10 +235,10 @@ static int xilinxfb_assign(struct device *dev,
int rc;
int fbsize = pdata-xvirt * pdata-yvirt * BYTES_PER_PIXEL;
- if (drvdata-flags PLB_ACCESS_FLAG) {
+ if (drvdata-flags BUS_ACCESS_FLAG) {
/*
* Map the control registers in if the controller
-* is on direct PLB interface.
+* is on direct BUS interface.
*/
if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
dev_err(dev, Couldn't lock memory region at 0x%08lX\n,
@@ -270,7 +270,7 @@ static int xilinxfb_assign(struct device *dev,
if (!drvdata-fb_virt) {
dev_err(dev, Could not allocate frame buffer memory\n);
rc = -ENOMEM;
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
goto err_fbmem;
else
goto err_region;
@@ -323,7 +323,7 @@ static int xilinxfb_assign(struct device *dev,
goto err_regfb;
}
- if (drvdata-flags PLB_ACCESS_FLAG) {
+ if (drvdata-flags BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
dev_dbg(dev, regs: phys=%lx, virt=%p\n, physaddr,
drvdata-regs);
@@ -348,11 +348,11 @@ err_cmap:
xilinx_fb_out32(drvdata, REG_CTRL, 0);
err_fbmem:
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
iounmap(drvdata-regs);
err_map:
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
release_mem_region(physaddr, 8);
err_region:
@@ -384,7 +384,7 @@ static int xilinxfb_release(struct device *dev)
xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
- if (drvdata-flags PLB_ACCESS_FLAG) {
+ if (drvdata-flags BUS_ACCESS_FLAG) {
iounmap(drvdata-regs);
release_mem_region(drvdata-regs_phys, 8);
}
@@ -423,18 +423,18 @@ static int xilinxfb_of_probe(struct platform_device *op)
}
/*
-* To check whether the core is connected directly to DCR or PLB
+* To check whether the core is connected directly to DCR or BUS
* interface and initialize the tft_access accordingly.
*/
of_property_read_u32(op-dev.of_node, xlnx,dcr-splb-slave-if,
tft_access);
/*
-* Fill the resource
[PATCH v3 6/8] video: xilinxfb: Add support for little endian accesses
Dynamically detect endianess on IP and use
ioread/iowrite functions instead of powerpc and microblaze
specific out_be32.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this patchset based on discussions
Changes in v2: None
drivers/video/xilinxfb.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index bd3b85d..f3d4a69 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -117,6 +117,7 @@ static struct fb_var_screeninfo xilinx_fb_var = {
#define BUS_ACCESS_FLAG0x1 /* 1 = BUS, 0 = DCR */
+#define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */
struct xilinxfb_drvdata {
@@ -153,14 +154,33 @@ struct xilinxfb_drvdata {
static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
- if (drvdata-flags BUS_ACCESS_FLAG)
- out_be32(drvdata-regs + (offset 2), val);
+ if (drvdata-flags BUS_ACCESS_FLAG) {
+ if (drvdata-flags LITTLE_ENDIAN_ACCESS)
+ iowrite32(val, drvdata-regs + (offset 2));
+ else
+ iowrite32be(val, drvdata-regs + (offset 2));
+ }
#ifdef CONFIG_PPC_DCR
else
dcr_write(drvdata-dcr_host, offset, val);
#endif
}
+static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
+{
+ if (drvdata-flags BUS_ACCESS_FLAG) {
+ if (drvdata-flags LITTLE_ENDIAN_ACCESS)
+ return ioread32(drvdata-regs + (offset 2));
+ else
+ return ioread32be(drvdata-regs + (offset 2));
+ }
+#ifdef CONFIG_PPC_DCR
+ else
+ return dcr_read(drvdata-dcr_host, offset);
+#endif
+ return 0;
+}
+
static int
xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned
blue,
unsigned transp, struct fb_info *fbi)
@@ -271,6 +291,12 @@ static int xilinxfb_assign(struct platform_device *pdev,
/* Tell the hardware where the frame buffer is */
xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
+ /* Endianess detection */
+ if (rc != drvdata-fb_phys) {
+ drvdata-flags |= LITTLE_ENDIAN_ACCESS;
+ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ }
/* Turn on the display */
drvdata-reg_ctrl_default = REG_CTRL_ENABLE;
--
1.8.2.3
pgpkMk5xr8DsT.pgp
Description: PGP signature
[PATCH v3 7/8] video: xilinxfb: Fix sparse warnings
Use proper casting for fb_virt variable.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this patchset
Changes in v2: None
drivers/video/xilinxfb.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index f3d4a69..e27a4f6 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -131,7 +131,7 @@ struct xilinxfb_drvdata {
dcr_host_t dcr_host;
unsigned intdcr_len;
#endif
- void*fb_virt; /* virt. address of the frame buffer */
+ void __iomem*fb_virt; /* virt. address of the frame buffer */
dma_addr_t fb_phys;/* phys. address of the frame buffer */
int fb_alloced; /* Flag, was the fb memory alloced? */
@@ -273,8 +273,10 @@ static int xilinxfb_assign(struct platform_device *pdev,
drvdata-fb_virt = ioremap(pdata-fb_phys, fbsize);
} else {
drvdata-fb_alloced = 1;
- drvdata-fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
- drvdata-fb_phys, GFP_KERNEL);
+ drvdata-fb_virt = (__force void __iomem *)
+ dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
+ drvdata-fb_phys,
+ GFP_KERNEL);
}
if (!drvdata-fb_virt) {
@@ -287,7 +289,7 @@ static int xilinxfb_assign(struct platform_device *pdev,
}
/* Clear (turn to black) the framebuffer */
- memset_io((void __iomem *)drvdata-fb_virt, 0, fbsize);
+ memset_io(drvdata-fb_virt, 0, fbsize);
/* Tell the hardware where the frame buffer is */
xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
@@ -307,7 +309,7 @@ static int xilinxfb_assign(struct platform_device *pdev,
/* Fill struct fb_info */
drvdata-info.device = dev;
- drvdata-info.screen_base = (void __iomem *)drvdata-fb_virt;
+ drvdata-info.screen_base = drvdata-fb_virt;
drvdata-info.fbops = xilinxfb_ops;
drvdata-info.fix = xilinx_fb_fix;
drvdata-info.fix.smem_start = drvdata-fb_phys;
@@ -341,8 +343,8 @@ static int xilinxfb_assign(struct platform_device *pdev,
if (drvdata-flags BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
- dev_dbg(dev, regs: phys=%x, virt=%p\n, drvdata-regs_phys,
- drvdata-regs);
+ dev_dbg(dev, regs: phys=%x, virt=%p\n,
+ (u32)drvdata-regs_phys, drvdata-regs);
}
/* Put a banner in the log (for DEBUG) */
dev_dbg(dev, fb: phys=%llx, virt=%p, size=%x\n,
@@ -355,8 +357,9 @@ err_regfb:
err_cmap:
if (drvdata-fb_alloced)
- dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata-fb_virt,
- drvdata-fb_phys);
+ dma_free_coherent(dev, PAGE_ALIGN(fbsize),
+ (__force void *)drvdata-fb_virt,
+ drvdata-fb_phys);
else
iounmap(drvdata-fb_virt);
@@ -388,7 +391,8 @@ static int xilinxfb_release(struct device *dev)
if (drvdata-fb_alloced)
dma_free_coherent(dev, PAGE_ALIGN(drvdata-info.fix.smem_len),
- drvdata-fb_virt, drvdata-fb_phys);
+ (__force void *)drvdata-fb_virt,
+ drvdata-fb_phys);
else
iounmap(drvdata-fb_virt);
--
1.8.2.3
pgpgesMmxsgdE.pgp
Description: PGP signature
[PATCH v3 5/8] video: xilinxfb: Group bus initialization
Move of_address_to_resource() to xilinxfb_assign()
which simplify driver probing.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this patchset
Changes in v2: None
drivers/video/xilinxfb.c | 56 +---
1 file changed, 15 insertions(+), 41 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 1b55f18..bd3b85d 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -227,33 +227,23 @@ static struct fb_ops xilinxfb_ops =
* Bus independent setup/teardown
*/
-static int xilinxfb_assign(struct device *dev,
+static int xilinxfb_assign(struct platform_device *pdev,
struct xilinxfb_drvdata *drvdata,
- unsigned long physaddr,
struct xilinxfb_platform_data *pdata)
{
int rc;
+ struct device *dev = pdev-dev;
int fbsize = pdata-xvirt * pdata-yvirt * BYTES_PER_PIXEL;
if (drvdata-flags BUS_ACCESS_FLAG) {
- /*
-* Map the control registers in if the controller
-* is on direct BUS interface.
-*/
- if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
- dev_err(dev, Couldn't lock memory region at 0x%08lX\n,
- physaddr);
- rc = -ENODEV;
- goto err_region;
- }
+ struct resource *res;
- drvdata-regs_phys = physaddr;
- drvdata-regs = ioremap(physaddr, 8);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drvdata-regs_phys = res-start;
+ drvdata-regs = devm_request_and_ioremap(pdev-dev, res);
if (!drvdata-regs) {
- dev_err(dev, Couldn't lock memory region at 0x%08lX\n,
- physaddr);
- rc = -ENODEV;
- goto err_map;
+ rc = -EADDRNOTAVAIL;
+ goto err_region;
}
}
@@ -349,11 +339,7 @@ err_cmap:
err_fbmem:
if (drvdata-flags BUS_ACCESS_FLAG)
- iounmap(drvdata-regs);
-
-err_map:
- if (drvdata-flags BUS_ACCESS_FLAG)
- release_mem_region(drvdata-regs_phys, 8);
+ devm_iounmap(dev, drvdata-regs);
err_region:
kfree(drvdata);
@@ -384,10 +370,8 @@ static int xilinxfb_release(struct device *dev)
xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
- if (drvdata-flags BUS_ACCESS_FLAG) {
- iounmap(drvdata-regs);
- release_mem_region(drvdata-regs_phys, 8);
- }
+ if (drvdata-flags BUS_ACCESS_FLAG)
+ devm_iounmap(dev, drvdata-regs);
#ifdef CONFIG_PPC_DCR
else
dcr_unmap(drvdata-dcr_host, drvdata-dcr_len);
@@ -408,8 +392,7 @@ static int xilinxfb_of_probe(struct platform_device *op)
const u32 *prop;
u32 tft_access = 0;
struct xilinxfb_platform_data pdata;
- struct resource res;
- int size, rc;
+ int size;
struct xilinxfb_drvdata *drvdata;
/* Copy with the default pdata (not a ptr reference!) */
@@ -435,22 +418,17 @@ static int xilinxfb_of_probe(struct platform_device *op)
*/
if (tft_access) {
drvdata-flags |= BUS_ACCESS_FLAG;
- rc = of_address_to_resource(op-dev.of_node, 0, res);
- if (rc) {
- dev_err(op-dev, invalid address\n);
- goto err;
- }
}
#ifdef CONFIG_PPC_DCR
else {
int start;
- res.start = 0;
start = dcr_resource_start(op-dev.of_node, 0);
drvdata-dcr_len = dcr_resource_len(op-dev.of_node, 0);
drvdata-dcr_host = dcr_map(op-dev.of_node, start,
drvdata-dcr_len);
if (!DCR_MAP_OK(drvdata-dcr_host)) {
dev_err(op-dev, invalid DCR address\n);
- goto err;
+ kfree(drvdata);
+ return -ENODEV;
}
}
#endif
@@ -477,11 +455,7 @@ static int xilinxfb_of_probe(struct platform_device *op)
pdata.rotate_screen = 1;
dev_set_drvdata(op-dev, drvdata);
- return xilinxfb_assign(op-dev, drvdata, res.start, pdata);
-
- err:
- kfree(drvdata);
- return -ENODEV;
+ return xilinxfb_assign(op, drvdata, pdata);
}
static int xilinxfb_of_remove(struct platform_device *op)
--
1.8.2.3
pgpnFsR9ViWfB.pgp
Description: PGP signature
[PATCH v3 4/8] video: xilinxfb: Use drvdata-regs_phys instead of physaddr
physaddr will be remove in the next patch.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this patchset based on discussions
Changes in v2: None
drivers/video/xilinxfb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index d94c992..1b55f18 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -325,7 +325,7 @@ static int xilinxfb_assign(struct device *dev,
if (drvdata-flags BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
- dev_dbg(dev, regs: phys=%lx, virt=%p\n, physaddr,
+ dev_dbg(dev, regs: phys=%x, virt=%p\n, drvdata-regs_phys,
drvdata-regs);
}
/* Put a banner in the log (for DEBUG) */
@@ -353,7 +353,7 @@ err_fbmem:
err_map:
if (drvdata-flags BUS_ACCESS_FLAG)
- release_mem_region(physaddr, 8);
+ release_mem_region(drvdata-regs_phys, 8);
err_region:
kfree(drvdata);
--
1.8.2.3
pgpUbOqIENBBY.pgp
Description: PGP signature
Re: [PATCH v3 1/8] video: xilinxfb: Fix OF probing on little-endian systems
On 05/31/2013 03:05 PM, Timur Tabi wrote: On 05/31/2013 07:55 AM, Michal Simek wrote: -p = (u32 *)of_get_property(op-dev.of_node, xlnx,dcr-splb-slave-if, NULL); -tft_access = p ? *p : 0; +of_property_read_u32(op-dev.of_node, xlnx,dcr-splb-slave-if, + tft_access); This is okay, but just FYI, you could instead have just used be32_to_cpup(). yep. I was there in v1 but then Soren suggested to use of_property_read_u32 http://lkml.org/lkml/2013/5/29/365 Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH v3 7/8] video: xilinxfb: Fix sparse warnings
On 05/31/2013 03:26 PM, Timur Tabi wrote:
On 05/31/2013 07:55 AM, Michal Simek wrote:
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index f3d4a69..e27a4f6 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -131,7 +131,7 @@ struct xilinxfb_drvdata {
dcr_host_t dcr_host;
unsigned intdcr_len;
#endif
-void*fb_virt; /* virt. address of the frame buffer */
+void __iomem*fb_virt; /* virt. address of the frame buffer */
dma_addr_t fb_phys;/* phys. address of the frame buffer */
int fb_alloced; /* Flag, was the fb memory alloced? */
@@ -273,8 +273,10 @@ static int xilinxfb_assign(struct platform_device *pdev,
drvdata-fb_virt = ioremap(pdata-fb_phys, fbsize);
} else {
drvdata-fb_alloced = 1;
-drvdata-fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
-drvdata-fb_phys, GFP_KERNEL);
+drvdata-fb_virt = (__force void __iomem *)
+ dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
+ drvdata-fb_phys,
+ GFP_KERNEL);
I think this is wrong. At least, it would be on PowerPC.
dma_alloc_coherent() allocates regular RAM, not I/O memory. So it
should not be __iomem.
The same is for Microblaze. Driver shares fb_virt for IO memory
and for allocated memory. The purpose of this driver wasn't
to change the driver logic just resolved sparse warnings.
The other way is also wrong.
I have compiled this driver with ppc toolchain and it should
remove sparse warnings for PPC.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
Re: [PATCH] of: Export of_irq_count for using in modules
On 05/31/2013 01:00 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 10:14 Fri 31 May , Michal Simek wrote:
Hi Jean-Christophe,
On 05/30/2013 10:17 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:49 Thu 30 May , Michal Simek wrote:
Export of_irq_count for modules.
can you explain why do you need to call of_irq_count
I need to count number of irq written in the DTS node.
It is not fixed size that's why I need to proper way how to
find it out.
I am using this loop.
count = of_irq_count(pdev-dev.of_node);
/* Alloc IRQ based on DTS to be sure that no other driver will use it */
while (count--) {
tmp-irq = irq_of_parse_and_map(pdev-dev.of_node, count);
dev_info(pdev-dev, %d: Alloc irq: %d\n, count, tmp-irq);
ret = request_irq(tmp-irq, zynq_remoteproc_interrupt, 0,
dev_name(pdev-dev), pdev-dev);
if (ret) {
...
}
}
But of course if you think that this is incorrect to export it
I can use what it is in of_irq_count body
368 int of_irq_count(struct device_node *dev)
369 {
370 int nr = 0;
371
372 while (of_irq_to_resource(dev, nr, NULL))
373 nr++;
374
375 return nr;
376 }
Because of_irq_to_resource is exported for modules.
Or is there any better way how to loop over all interrupts in DT node?
can just explain me why you need to call irq_of_parse_and_map in your driver?
as the irq will be provided in the resources normally
It is quite a long time I have written this driver on v3.1 or 3.3.
But is this better?
struct resource *res;
int i = 0;
do {
res = platform_get_resource(pdev, IORESOURCE_IRQ, i++);
if (res)
do something
} while(res);
Also what about of_irq_to_resource()? Is it deprecated and all drivers
shouldn't use it?
I have no problem to rewrite the driver to use platform_get_resource.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
Re: [PATCH v3 7/8] video: xilinxfb: Fix sparse warnings
On 05/31/2013 03:41 PM, Timur Tabi wrote:
On 05/31/2013 08:37 AM, Michal Simek wrote:
The same is for Microblaze. Driver shares fb_virt for IO memory
and for allocated memory. The purpose of this driver wasn't
to change the driver logic just resolved sparse warnings.
The other way is also wrong.
I have compiled this driver with ppc toolchain and it should
remove sparse warnings for PPC.
But it's not I/O memory. It's regular memory. __iomem is for
memory-mapped I/O, which is limited to a specific range of memory locations.
If sometimes you use regular memory for the framebuffer, and other times
you use real I/O memory for the framebuffer, then you should have two
different pointers.
I agree with you and if you like I can change it.
But there will be at least one retype because dma_alloc_coherent returns void *
but struct fb_info expects that pointer is __iomem (char __iomem *screen_base).
Patch is below.
Thanks,
Michal
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index f3d4a69..885f294 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -132,8 +132,8 @@ struct xilinxfb_drvdata {
unsigned intdcr_len;
#endif
void*fb_virt; /* virt. address of the frame buffer */
+ void __iomem*fb_virt_io;/* virt. address of the frame buffer */
dma_addr_t fb_phys;/* phys. address of the frame buffer */
- int fb_alloced; /* Flag, was the fb memory alloced? */
u8 flags; /* features of the driver */
@@ -270,24 +270,36 @@ static int xilinxfb_assign(struct platform_device *pdev,
/* Allocate the framebuffer memory */
if (pdata-fb_phys) {
drvdata-fb_phys = pdata-fb_phys;
- drvdata-fb_virt = ioremap(pdata-fb_phys, fbsize);
+ drvdata-fb_virt_io = ioremap(pdata-fb_phys, fbsize);
+
+ if (!drvdata-fb_virt_io) {
+ dev_err(dev, Could not allocate frame buffer
memory\n);
+ rc = -ENOMEM;
+ if (drvdata-flags BUS_ACCESS_FLAG)
+ goto err_fbmem;
+ else
+ goto err_region;
+ }
+
+ /* Clear (turn to black) the framebuffer */
+ memset_io(drvdata-fb_virt_io, 0, fbsize);
} else {
- drvdata-fb_alloced = 1;
drvdata-fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
drvdata-fb_phys, GFP_KERNEL);
- }
- if (!drvdata-fb_virt) {
- dev_err(dev, Could not allocate frame buffer memory\n);
- rc = -ENOMEM;
- if (drvdata-flags BUS_ACCESS_FLAG)
- goto err_fbmem;
- else
- goto err_region;
+ if (!drvdata-fb_virt_io) {
+ dev_err(dev, Could not allocate frame buffer
memory\n);
+ rc = -ENOMEM;
+ if (drvdata-flags BUS_ACCESS_FLAG)
+ goto err_fbmem;
+ else
+ goto err_region;
+ memset(drvdata-fb_virt, 0, fbsize);
}
- /* Clear (turn to black) the framebuffer */
- memset_io((void __iomem *)drvdata-fb_virt, 0, fbsize);
+
/* Tell the hardware where the frame buffer is */
xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
@@ -307,7 +319,11 @@ static int xilinxfb_assign(struct platform_device *pdev,
/* Fill struct fb_info */
drvdata-info.device = dev;
- drvdata-info.screen_base = (void __iomem *)drvdata-fb_virt;
+ if (drvdata-fb_virt)
+ drvdata-info.screen_base = (__force void __iomem *)
+ drvdata-fb_virt;
+ else
+ drvdata-info.screen_base = drvdata-fb_virt_io;
drvdata-info.fbops = xilinxfb_ops;
drvdata-info.fix = xilinx_fb_fix;
drvdata-info.fix.smem_start = drvdata-fb_phys;
@@ -341,8 +357,8 @@ static int xilinxfb_assign(struct platform_device *pdev,
if (drvdata-flags BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
- dev_dbg(dev, regs: phys=%x, virt=%p\n, drvdata-regs_phys,
- drvdata-regs);
+ dev_dbg(dev, regs: phys=%x, virt=%p\n,
+ (u32)drvdata-regs_phys, drvdata-regs);
}
/* Put a banner in the log (for DEBUG) */
dev_dbg(dev, fb: phys=%llx, virt=%p, size=%x\n,
@@ -354,11 +370,11 @@ err_regfb:
fb_dealloc_cmap(drvdata-info.cmap);
err_cmap:
- if (drvdata-fb_alloced)
+ if (drvdata-fb_virt)
dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata-fb_virt,
drvdata-fb_phys);
else
Re: [PATCH v3 7/8] video: xilinxfb: Fix sparse warnings
On 05/31/2013 05:29 PM, Arnd Bergmann wrote: On Friday 31 May 2013 10:06:43 Timur Tabi wrote: On 05/31/2013 09:56 AM, Arnd Bergmann wrote: Yes, unfortunately, this is what all other frame buffer drivers do at the moment. It is technically not correct, but most architectures are able to call readl/writel on regular memory, or dereference __iomem tokens, so we often get away with it. It's probably not worth fixing it in the fbdev code base as that would be a huge change, and people are migrating to DRM/KMS. But why bother fixing this bug if it just makes things worse? Sparse is supposed to warn us about bad code. This patch doesn't fix the bug, it just masks the warnings! Yes, good point. It's probably best cast the ioremap() output to a regular pointer here, as that is actually just uncached RAM, not an MMIO register. ok. It means I will just remove this patch from this patchset. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH] of: Export of_irq_count for using in modules
On 05/31/2013 05:16 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:57 Fri 31 May , Michal Simek wrote:
On 05/31/2013 01:00 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 10:14 Fri 31 May , Michal Simek wrote:
Hi Jean-Christophe,
On 05/30/2013 10:17 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:49 Thu 30 May , Michal Simek wrote:
Export of_irq_count for modules.
can you explain why do you need to call of_irq_count
I need to count number of irq written in the DTS node.
It is not fixed size that's why I need to proper way how to
find it out.
I am using this loop.
count = of_irq_count(pdev-dev.of_node);
/* Alloc IRQ based on DTS to be sure that no other driver will use it */
while (count--) {
tmp-irq = irq_of_parse_and_map(pdev-dev.of_node, count);
dev_info(pdev-dev, %d: Alloc irq: %d\n, count, tmp-irq);
ret = request_irq(tmp-irq, zynq_remoteproc_interrupt, 0,
dev_name(pdev-dev), pdev-dev);
if (ret) {
...
}
}
But of course if you think that this is incorrect to export it
I can use what it is in of_irq_count body
368 int of_irq_count(struct device_node *dev)
369 {
370 int nr = 0;
371
372 while (of_irq_to_resource(dev, nr, NULL))
373 nr++;
374
375 return nr;
376 }
Because of_irq_to_resource is exported for modules.
Or is there any better way how to loop over all interrupts in DT node?
can just explain me why you need to call irq_of_parse_and_map in your
driver?
as the irq will be provided in the resources normally
It is quite a long time I have written this driver on v3.1 or 3.3.
But is this better?
struct resource *res;
int i = 0;
do {
res = platform_get_resource(pdev, IORESOURCE_IRQ, i++);
if (res)
do something
} while(res);
Also what about of_irq_to_resource()? Is it deprecated and all drivers
shouldn't use it?
I have no problem to rewrite the driver to use platform_get_resource.
yeah it's better but be aware there is a but in DT that I'm working on to fix
if you use irq that are registered by a pdev this will not work
I hope to fix it for 3.11
and already send an RFC that fix it
ok. good to know. Btw: Let's return to my origin point why not to
export of_irq_count for modules?
Or opposite question if platform_get_resource is correct way
why to export of_irq_to_resource for modules?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
[PATCH v4 0/7] xilinxfb changes
Hi, I have done more changes in the driver to support probing on little and big endian system where detection is done directly on the hardware. I have also done some cleanups to get it to the better shape. Thanks for your review, Michal Changes in v4: - Acked by Arnd - Remove video: xilinxfb: Fix sparse warnings patch because it is trying to fix incorrect API usage and sparse should warn about it. Changes in v3: - fix commit message - Remove out_be IO name from function name - Change patch subject from Do not use out_be32 IO function to Do not name out_be32 in function name - New patch in this patchset based on discussions - New patch in this patchset based on discussions - New patch in this patchset - New patch in this patchset based on discussions Changes in v2: - use of_property_read_u32 helper function Michal Simek (7): video: xilinxfb: Fix OF probing on little-endian systems video: xilinxfb: Do not name out_be32 in function name video: xilinxfb: Rename PLB_ACCESS_FLAG to BUS_ACCESS_FLAG video: xilinxfb: Use drvdata-regs_phys instead of physaddr video: xilinxfb: Group bus initialization video: xilinxfb: Add support for little endian accesses video: xilinxfb: Use driver for Xilinx ARM Zynq drivers/video/Kconfig| 2 +- drivers/video/xilinxfb.c | 135 +++ 2 files changed, 68 insertions(+), 69 deletions(-) -- 1.8.2.3 pgpeTbxFaxLc3.pgp Description: PGP signature
[PATCH v4 4/7] video: xilinxfb: Use drvdata-regs_phys instead of physaddr
physaddr will be remove in the next patch.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v4: None
Changes in v3:
- New patch in this patchset based on discussions
Changes in v2: None
drivers/video/xilinxfb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index d94c992..1b55f18 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -325,7 +325,7 @@ static int xilinxfb_assign(struct device *dev,
if (drvdata-flags BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
- dev_dbg(dev, regs: phys=%lx, virt=%p\n, physaddr,
+ dev_dbg(dev, regs: phys=%x, virt=%p\n, drvdata-regs_phys,
drvdata-regs);
}
/* Put a banner in the log (for DEBUG) */
@@ -353,7 +353,7 @@ err_fbmem:
err_map:
if (drvdata-flags BUS_ACCESS_FLAG)
- release_mem_region(physaddr, 8);
+ release_mem_region(drvdata-regs_phys, 8);
err_region:
kfree(drvdata);
--
1.8.2.3
pgpoSu4wJou4q.pgp
Description: PGP signature
[PATCH v4 1/7] video: xilinxfb: Fix OF probing on little-endian systems
From: Michal Simek mon...@monstr.eu
DTB is always big-endian that's why it is necessary
to properly convert value (*p).
It is automatically done in of_property_read_u32().
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v4: None
Changes in v3:
- fix commit message
Changes in v2:
- use of_property_read_u32 helper function
drivers/video/xilinxfb.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index af0b4fd..aecd15d 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -406,8 +406,7 @@ static int xilinxfb_release(struct device *dev)
static int xilinxfb_of_probe(struct platform_device *op)
{
const u32 *prop;
- u32 *p;
- u32 tft_access;
+ u32 tft_access = 0;
struct xilinxfb_platform_data pdata;
struct resource res;
int size, rc;
@@ -427,8 +426,8 @@ static int xilinxfb_of_probe(struct platform_device *op)
* To check whether the core is connected directly to DCR or PLB
* interface and initialize the tft_access accordingly.
*/
- p = (u32 *)of_get_property(op-dev.of_node, xlnx,dcr-splb-slave-if,
NULL);
- tft_access = p ? *p : 0;
+ of_property_read_u32(op-dev.of_node, xlnx,dcr-splb-slave-if,
+tft_access);
/*
* Fill the resource structure if its direct PLB interface
--
1.8.2.3
pgpEuVaFFlFn8.pgp
Description: PGP signature
[PATCH v4 5/7] video: xilinxfb: Group bus initialization
Move of_address_to_resource() to xilinxfb_assign()
which simplify driver probing.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v4: None
Changes in v3:
- New patch in this patchset
Changes in v2: None
drivers/video/xilinxfb.c | 56 +---
1 file changed, 15 insertions(+), 41 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 1b55f18..bd3b85d 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -227,33 +227,23 @@ static struct fb_ops xilinxfb_ops =
* Bus independent setup/teardown
*/
-static int xilinxfb_assign(struct device *dev,
+static int xilinxfb_assign(struct platform_device *pdev,
struct xilinxfb_drvdata *drvdata,
- unsigned long physaddr,
struct xilinxfb_platform_data *pdata)
{
int rc;
+ struct device *dev = pdev-dev;
int fbsize = pdata-xvirt * pdata-yvirt * BYTES_PER_PIXEL;
if (drvdata-flags BUS_ACCESS_FLAG) {
- /*
-* Map the control registers in if the controller
-* is on direct BUS interface.
-*/
- if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
- dev_err(dev, Couldn't lock memory region at 0x%08lX\n,
- physaddr);
- rc = -ENODEV;
- goto err_region;
- }
+ struct resource *res;
- drvdata-regs_phys = physaddr;
- drvdata-regs = ioremap(physaddr, 8);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drvdata-regs_phys = res-start;
+ drvdata-regs = devm_request_and_ioremap(pdev-dev, res);
if (!drvdata-regs) {
- dev_err(dev, Couldn't lock memory region at 0x%08lX\n,
- physaddr);
- rc = -ENODEV;
- goto err_map;
+ rc = -EADDRNOTAVAIL;
+ goto err_region;
}
}
@@ -349,11 +339,7 @@ err_cmap:
err_fbmem:
if (drvdata-flags BUS_ACCESS_FLAG)
- iounmap(drvdata-regs);
-
-err_map:
- if (drvdata-flags BUS_ACCESS_FLAG)
- release_mem_region(drvdata-regs_phys, 8);
+ devm_iounmap(dev, drvdata-regs);
err_region:
kfree(drvdata);
@@ -384,10 +370,8 @@ static int xilinxfb_release(struct device *dev)
xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
- if (drvdata-flags BUS_ACCESS_FLAG) {
- iounmap(drvdata-regs);
- release_mem_region(drvdata-regs_phys, 8);
- }
+ if (drvdata-flags BUS_ACCESS_FLAG)
+ devm_iounmap(dev, drvdata-regs);
#ifdef CONFIG_PPC_DCR
else
dcr_unmap(drvdata-dcr_host, drvdata-dcr_len);
@@ -408,8 +392,7 @@ static int xilinxfb_of_probe(struct platform_device *op)
const u32 *prop;
u32 tft_access = 0;
struct xilinxfb_platform_data pdata;
- struct resource res;
- int size, rc;
+ int size;
struct xilinxfb_drvdata *drvdata;
/* Copy with the default pdata (not a ptr reference!) */
@@ -435,22 +418,17 @@ static int xilinxfb_of_probe(struct platform_device *op)
*/
if (tft_access) {
drvdata-flags |= BUS_ACCESS_FLAG;
- rc = of_address_to_resource(op-dev.of_node, 0, res);
- if (rc) {
- dev_err(op-dev, invalid address\n);
- goto err;
- }
}
#ifdef CONFIG_PPC_DCR
else {
int start;
- res.start = 0;
start = dcr_resource_start(op-dev.of_node, 0);
drvdata-dcr_len = dcr_resource_len(op-dev.of_node, 0);
drvdata-dcr_host = dcr_map(op-dev.of_node, start,
drvdata-dcr_len);
if (!DCR_MAP_OK(drvdata-dcr_host)) {
dev_err(op-dev, invalid DCR address\n);
- goto err;
+ kfree(drvdata);
+ return -ENODEV;
}
}
#endif
@@ -477,11 +455,7 @@ static int xilinxfb_of_probe(struct platform_device *op)
pdata.rotate_screen = 1;
dev_set_drvdata(op-dev, drvdata);
- return xilinxfb_assign(op-dev, drvdata, res.start, pdata);
-
- err:
- kfree(drvdata);
- return -ENODEV;
+ return xilinxfb_assign(op, drvdata, pdata);
}
static int xilinxfb_of_remove(struct platform_device *op)
--
1.8.2.3
pgpWJblfv6Jdt.pgp
Description: PGP signature
[PATCH v4 7/7] video: xilinxfb: Use driver for Xilinx ARM Zynq
From: Michal Simek mon...@monstr.eu Enable this driver for all Xilinx platforms. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v4: - Remove video: xilinxfb: Fix sparse warnings patch because it is trying to fix incorrect API usage and sparse should warn about it. Changes in v3: None Changes in v2: None drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2e937bd..2c301f8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2188,7 +2188,7 @@ config FB_PS3_DEFAULT_SIZE_M config FB_XILINX tristate Xilinx frame buffer support - depends on FB (XILINX_VIRTEX || MICROBLAZE) + depends on FB (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.8.2.3 pgp39aXQ8gg6h.pgp Description: PGP signature
[PATCH v4 6/7] video: xilinxfb: Add support for little endian accesses
Dynamically detect endianess on IP and use
ioread/iowrite functions instead of powerpc and microblaze
specific out_be32.
Signed-off-by: Michal Simek michal.si...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes in v4:
- Acked by Arnd
Changes in v3:
- New patch in this patchset based on discussions
Changes in v2: None
drivers/video/xilinxfb.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index bd3b85d..f3d4a69 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -117,6 +117,7 @@ static struct fb_var_screeninfo xilinx_fb_var = {
#define BUS_ACCESS_FLAG0x1 /* 1 = BUS, 0 = DCR */
+#define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */
struct xilinxfb_drvdata {
@@ -153,14 +154,33 @@ struct xilinxfb_drvdata {
static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
- if (drvdata-flags BUS_ACCESS_FLAG)
- out_be32(drvdata-regs + (offset 2), val);
+ if (drvdata-flags BUS_ACCESS_FLAG) {
+ if (drvdata-flags LITTLE_ENDIAN_ACCESS)
+ iowrite32(val, drvdata-regs + (offset 2));
+ else
+ iowrite32be(val, drvdata-regs + (offset 2));
+ }
#ifdef CONFIG_PPC_DCR
else
dcr_write(drvdata-dcr_host, offset, val);
#endif
}
+static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
+{
+ if (drvdata-flags BUS_ACCESS_FLAG) {
+ if (drvdata-flags LITTLE_ENDIAN_ACCESS)
+ return ioread32(drvdata-regs + (offset 2));
+ else
+ return ioread32be(drvdata-regs + (offset 2));
+ }
+#ifdef CONFIG_PPC_DCR
+ else
+ return dcr_read(drvdata-dcr_host, offset);
+#endif
+ return 0;
+}
+
static int
xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned
blue,
unsigned transp, struct fb_info *fbi)
@@ -271,6 +291,12 @@ static int xilinxfb_assign(struct platform_device *pdev,
/* Tell the hardware where the frame buffer is */
xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
+ /* Endianess detection */
+ if (rc != drvdata-fb_phys) {
+ drvdata-flags |= LITTLE_ENDIAN_ACCESS;
+ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ }
/* Turn on the display */
drvdata-reg_ctrl_default = REG_CTRL_ENABLE;
--
1.8.2.3
pgpFVsDZJDdlY.pgp
Description: PGP signature
[PATCH v4 3/7] video: xilinxfb: Rename PLB_ACCESS_FLAG to BUS_ACCESS_FLAG
Using only PLB name is wrong for a long time because
the same access functions are also used for AXI.
s/PLB/BUS/g
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v4: None
Changes in v3:
- New patch in this patchset based on discussions
Changes in v2: None
drivers/video/xilinxfb.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index c9b442b..d94c992 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -44,7 +44,7 @@
/*
- * Xilinx calls it PLB TFT LCD Controller though it can also be used for
+ * Xilinx calls it TFT LCD Controller though it can also be used for
* the VGA port on the Xilinx ML40x board. This is a hardware display
* controller for a 640x480 resolution TFT or VGA screen.
*
@@ -54,11 +54,11 @@
* don't start thinking about scrolling). The second allows the LCD to
* be turned on or off as well as rotated 180 degrees.
*
- * In case of direct PLB access the second control register will be at
+ * In case of direct BUS access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
* xilinx_fb_out32 where it left shifts the offset 2 times in case of
- * direct PLB access.
+ * direct BUS access.
*/
#define NUM_REGS 2
#define REG_FB_ADDR0
@@ -116,7 +116,7 @@ static struct fb_var_screeninfo xilinx_fb_var = {
};
-#define PLB_ACCESS_FLAG0x1 /* 1 = PLB, 0 = DCR */
+#define BUS_ACCESS_FLAG0x1 /* 1 = BUS, 0 = DCR */
struct xilinxfb_drvdata {
@@ -146,14 +146,14 @@ struct xilinxfb_drvdata {
container_of(_info, struct xilinxfb_drvdata, info)
/*
- * The XPS TFT Controller can be accessed through PLB or DCR interface.
+ * The XPS TFT Controller can be accessed through BUS or DCR interface.
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
out_be32(drvdata-regs + (offset 2), val);
#ifdef CONFIG_PPC_DCR
else
@@ -235,10 +235,10 @@ static int xilinxfb_assign(struct device *dev,
int rc;
int fbsize = pdata-xvirt * pdata-yvirt * BYTES_PER_PIXEL;
- if (drvdata-flags PLB_ACCESS_FLAG) {
+ if (drvdata-flags BUS_ACCESS_FLAG) {
/*
* Map the control registers in if the controller
-* is on direct PLB interface.
+* is on direct BUS interface.
*/
if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
dev_err(dev, Couldn't lock memory region at 0x%08lX\n,
@@ -270,7 +270,7 @@ static int xilinxfb_assign(struct device *dev,
if (!drvdata-fb_virt) {
dev_err(dev, Could not allocate frame buffer memory\n);
rc = -ENOMEM;
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
goto err_fbmem;
else
goto err_region;
@@ -323,7 +323,7 @@ static int xilinxfb_assign(struct device *dev,
goto err_regfb;
}
- if (drvdata-flags PLB_ACCESS_FLAG) {
+ if (drvdata-flags BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
dev_dbg(dev, regs: phys=%lx, virt=%p\n, physaddr,
drvdata-regs);
@@ -348,11 +348,11 @@ err_cmap:
xilinx_fb_out32(drvdata, REG_CTRL, 0);
err_fbmem:
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
iounmap(drvdata-regs);
err_map:
- if (drvdata-flags PLB_ACCESS_FLAG)
+ if (drvdata-flags BUS_ACCESS_FLAG)
release_mem_region(physaddr, 8);
err_region:
@@ -384,7 +384,7 @@ static int xilinxfb_release(struct device *dev)
xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
- if (drvdata-flags PLB_ACCESS_FLAG) {
+ if (drvdata-flags BUS_ACCESS_FLAG) {
iounmap(drvdata-regs);
release_mem_region(drvdata-regs_phys, 8);
}
@@ -423,18 +423,18 @@ static int xilinxfb_of_probe(struct platform_device *op)
}
/*
-* To check whether the core is connected directly to DCR or PLB
+* To check whether the core is connected directly to DCR or BUS
* interface and initialize the tft_access accordingly.
*/
of_property_read_u32(op-dev.of_node, xlnx,dcr-splb-slave-if,
tft_access);
/*
-* Fill
[PATCH v4 2/7] video: xilinxfb: Do not name out_be32 in function name
out_be32 IO function is not supported by ARM.
It is only available for PPC and Microblaze.
Because this driver can be used on ARM let's
remove out_be32 from function name.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v4: None
Changes in v3:
- Remove out_be IO name from function name
- Change patch subject from Do not use out_be32 IO function
to Do not name out_be32 in function name
Changes in v2: None
drivers/video/xilinxfb.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index aecd15d..c9b442b 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -57,7 +57,7 @@
* In case of direct PLB access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
- * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
+ * xilinx_fb_out32 where it left shifts the offset 2 times in case of
* direct PLB access.
*/
#define NUM_REGS 2
@@ -150,7 +150,7 @@ struct xilinxfb_drvdata {
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
-static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
if (drvdata-flags PLB_ACCESS_FLAG)
@@ -197,7 +197,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* turn on panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
+ xilinx_fb_out32(drvdata, REG_CTRL, drvdata-reg_ctrl_default);
break;
case FB_BLANK_NORMAL:
@@ -205,7 +205,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
/* turn off panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
default:
break;
@@ -280,13 +280,13 @@ static int xilinxfb_assign(struct device *dev,
memset_io((void __iomem *)drvdata-fb_virt, 0, fbsize);
/* Tell the hardware where the frame buffer is */
- xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
+ xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata-fb_phys);
/* Turn on the display */
drvdata-reg_ctrl_default = REG_CTRL_ENABLE;
if (pdata-rotate_screen)
drvdata-reg_ctrl_default |= REG_CTRL_ROTATE;
- xilinx_fb_out_be32(drvdata, REG_CTRL,
+ xilinx_fb_out32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
/* Fill struct fb_info */
@@ -345,7 +345,7 @@ err_cmap:
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
err_fbmem:
if (drvdata-flags PLB_ACCESS_FLAG)
@@ -381,7 +381,7 @@ static int xilinxfb_release(struct device *dev)
iounmap(drvdata-fb_virt);
/* Turn off the display */
- xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
+ xilinx_fb_out32(drvdata, REG_CTRL, 0);
/* Release the resources, as allocated based on interface */
if (drvdata-flags PLB_ACCESS_FLAG) {
--
1.8.2.3
pgp1HcSUZso8J.pgp
Description: PGP signature
[PATCH v2 2/6] GPIO: xilinx: Add support for dual channel
Supporting the second channel in the driver.
Offset is 0x8 and both channnels share the same
IRQ.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Use kernel doc format - suggested by Linus Walleij
- Do not use __raw_readl/__raw_writel IO in this patch
- Use of_property_read_u32 helper function
- Use BIT()
- Change patch subject
drivers/gpio/gpio-xilinx.c | 103 +++--
1 file changed, 91 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 2aad534..626eaa8 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -1,7 +1,7 @@
/*
- * Xilinx gpio driver
+ * Xilinx gpio driver for xps/axi_gpio IP.
*
- * Copyright 2008 Xilinx, Inc.
+ * Copyright 2008 - 2013 Xilinx, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
@@ -12,6 +12,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include linux/bitops.h
#include linux/init.h
#include linux/errno.h
#include linux/module.h
@@ -26,11 +27,26 @@
#define XGPIO_DATA_OFFSET (0x0) /* Data register */
#define XGPIO_TRI_OFFSET(0x4) /* I/O direction register */
+#define XGPIO_CHANNEL_OFFSET 0x8
+
+/* Read/Write access to the GPIO registers */
+#define xgpio_readreg(offset) in_be32(offset)
+#define xgpio_writereg(offset, val)out_be32(offset, val)
+
+/**
+ * struct xgpio_instance - Stores information about GPIO device
+ * struct of_mm_gpio_chip mmchip: OF GPIO chip for memory mapped banks
+ * gpio_state: GPIO state shadow register
+ * gpio_dir: GPIO direction shadow register
+ * offset: GPIO channel offset
+ * gpio_lock: Lock used for synchronization
+ */
struct xgpio_instance {
struct of_mm_gpio_chip mmchip;
- u32 gpio_state; /* GPIO state shadow register */
- u32 gpio_dir; /* GPIO direction shadow register */
- spinlock_t gpio_lock; /* Lock used for synchronization */
+ u32 gpio_state;
+ u32 gpio_dir;
+ u32 offset;
+ spinlock_t gpio_lock;
};
/**
@@ -44,8 +60,12 @@ struct xgpio_instance {
static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct xgpio_instance *chip =
+ container_of(mm_gc, struct xgpio_instance, mmchip);
- return (in_be32(mm_gc-regs + XGPIO_DATA_OFFSET) gpio) 1;
+ void __iomem *regs = mm_gc-regs + chip-offset;
+
+ return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET) BIT(gpio));
}
/**
@@ -63,6 +83,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int
gpio, int val)
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
+ void __iomem *regs = mm_gc-regs;
spin_lock_irqsave(chip-gpio_lock, flags);
@@ -71,7 +92,9 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int
gpio, int val)
chip-gpio_state |= 1 gpio;
else
chip-gpio_state = ~(1 gpio);
- out_be32(mm_gc-regs + XGPIO_DATA_OFFSET, chip-gpio_state);
+
+ xgpio_writereg(regs + chip-offset + XGPIO_DATA_OFFSET,
+chip-gpio_state);
spin_unlock_irqrestore(chip-gpio_lock, flags);
}
@@ -91,12 +114,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int
gpio)
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
+ void __iomem *regs = mm_gc-regs;
spin_lock_irqsave(chip-gpio_lock, flags);
/* Set the GPIO bit in shadow register and set direction as input */
chip-gpio_dir |= (1 gpio);
- out_be32(mm_gc-regs + XGPIO_TRI_OFFSET, chip-gpio_dir);
+ xgpio_writereg(regs + chip-offset + XGPIO_TRI_OFFSET, chip-gpio_dir);
spin_unlock_irqrestore(chip-gpio_lock, flags);
@@ -119,6 +143,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int
gpio, int val)
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct xgpio_instance *chip =
container_of(mm_gc, struct xgpio_instance, mmchip);
+ void __iomem *regs = mm_gc-regs;
spin_lock_irqsave(chip-gpio_lock, flags);
@@ -127,11 +152,12 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned
int gpio, int val)
chip-gpio_state |= 1 gpio;
else
chip-gpio_state = ~(1 gpio);
- out_be32(mm_gc-regs + XGPIO_DATA_OFFSET, chip-gpio_state);
+ xgpio_writereg(regs + chip-offset + XGPIO_DATA_OFFSET,
+ chip-gpio_state);
/* Clear the GPIO bit in shadow register and set direction as output */
chip-gpio_dir = (~(1 gpio
[PATCH v2 4/6] GPIO: xilinx: Use BIT macro
Use BIT macro from linux/bitops.h. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: - New patch in this series suggested by Linus Valleij drivers/gpio/gpio-xilinx.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 791ddae..792a05a 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -94,9 +94,9 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) /* Write to GPIO signal and set its direction to output */ if (val) - chip-gpio_state |= 1 gpio; + chip-gpio_state |= BIT(gpio); else - chip-gpio_state = ~(1 gpio); + chip-gpio_state = ~BIT(gpio); xgpio_writereg(regs + chip-offset + XGPIO_DATA_OFFSET, chip-gpio_state); @@ -124,7 +124,7 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) spin_lock_irqsave(chip-gpio_lock, flags); /* Set the GPIO bit in shadow register and set direction as input */ - chip-gpio_dir |= (1 gpio); + chip-gpio_dir |= BIT(gpio); xgpio_writereg(regs + chip-offset + XGPIO_TRI_OFFSET, chip-gpio_dir); spin_unlock_irqrestore(chip-gpio_lock, flags); @@ -154,14 +154,14 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) /* Write state of GPIO signal */ if (val) - chip-gpio_state |= 1 gpio; + chip-gpio_state |= BIT(gpio); else - chip-gpio_state = ~(1 gpio); + chip-gpio_state = ~BIT(gpio); xgpio_writereg(regs + chip-offset + XGPIO_DATA_OFFSET, chip-gpio_state); /* Clear the GPIO bit in shadow register and set direction as output */ - chip-gpio_dir = (~(1 gpio)); + chip-gpio_dir = ~BIT(gpio); xgpio_writereg(regs + chip-offset + XGPIO_TRI_OFFSET, chip-gpio_dir); spin_unlock_irqrestore(chip-gpio_lock, flags); -- 1.8.2.3 pgpF03lNL8VNN.pgp Description: PGP signature
