Re: [RFC PATCH 0/4] Command Queueing Support in eMMC
On Fri, Dec 4, 2015 at 12:40 PM, Das, Asutosh (asd) <asuto...@codeaurora.org> wrote: > + Kostya > Hi Aisheng, > Yes, a colleague of mine is working on upstreaming it. It should be done > within a week or so. > Great! Thanks! Looking forward to it. Regards Dong Aisheng > > On 12/3/2015 9:12 AM, Dong Aisheng wrote: >> >> Hi Asutosh, >> >> On Tue, Dec 2, 2014 at 7:53 PM, Asutosh Das <asuto...@codeaurora.org> >> wrote: >>> >>> In this patch series, we propose a method to add support for >>> Command Queueing(CQ) feature added to eMMC-5.1 specification. >>> This feature includes new commands for issuing tasks to the >>> device and orders the execution of tasks to the device. It >>> also has task management functions. >>> >>> The initialization of CQ is decided based on the underlying >>> driver capability and the capability advertised by the card >>> through ext_csd. >>> >>> We have selectively adopted the scsi design of pulling in >>> requests from kernel block layer. >>> >>> In order to support queueing of multiple requests, we have >>> added a new issue function to mmc-queue. This selectively >>> pulls the requests and prepares and issues it to the underlying >>> driver. We have used the inherent tagging mechanism of kernel >>> block layer to keep track and map tags to the slots of underlying >>> driver. The current design doesn't block for the request to >>> complete. We have separated the issuing and completion path >>> of the request and tracking is done using the tag assigned to >>> the request. >>> >>> We have introduced a number of APIs to mmc block layer to >>> facilitate servicing of requests. >>> >>> The completion of requests is handled in a softirq registered >>> with the kernel block layer during initialization. The error >>> handling however would be done using a workqueue and is under >>> development. >>> >>> We have separated the legacy eMMC code from CQ code, so as to >>> make it more manageable. >>> >>> A new layer has been introduced to serve the CQ compliant drivers. >>> This layer (cq_hci) has all the standard functionality implemented. >>> It also has necessary hooks for convenience of platform drivers. >>> >>> Asutosh Das (4): >>>mmc: queue: initialization of command-queue support >>>mmc: card: Add eMMC command queuing support in mmc block layer >>>mmc: cmdq: support for command queue enabled host >>>mmc: sdhci: add command queue support to sdhci >>> >>> Sujit Reddy Thumma (1): >>>mmc: core: Add support to read command queue parameters >>> >>> drivers/mmc/card/block.c | 378 >>> - >>> drivers/mmc/card/queue.c | 160 ++- >>> drivers/mmc/card/queue.h | 9 +- >>> drivers/mmc/core/core.c| 87 +++ >>> drivers/mmc/core/mmc.c | 19 +++ >>> drivers/mmc/core/mmc_ops.c | 45 -- >>> drivers/mmc/host/Kconfig | 12 ++ >>> drivers/mmc/host/Makefile | 1 + >>> drivers/mmc/host/sdhci.c | 89 +++ >>> drivers/mmc/host/sdhci.h | 2 + >>> include/linux/mmc/card.h | 10 +- >>> include/linux/mmc/core.h | 14 ++ >>> include/linux/mmc/host.h | 72 + >>> include/linux/mmc/mmc.h| 9 ++ >>> include/linux/mmc/sdhci.h | 1 + >>> 15 files changed, 887 insertions(+), 21 deletions(-) >>> >> Are you still working on this? >> Is there a updated version and any upstream plan? >> I'm going to verify it. >> >> Regards >> Dong Aisheng >> >>> -- >>> 1.8.2.1 >>> >>> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >>> a Linux Foundation Collaborative Project >>> -- >>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in >>> the body of a message to majord...@vger.kernel.org >>> More majordomo info at http://vger.kernel.org/majordomo-info.html >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in >> the body of a message to majord...@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html > > -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] mmc: sdhci-esdhc-imx: move the setting of watermark level out of probe
On Thu, Nov 19, 2015 at 7:17 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
> On 10 November 2015 at 10:43, Haibo Chen <haibo.c...@freescale.com> wrote:
>> Currently, we config the watermark_level register only in probe.
>> This will cause the mmc write operation timeout issue after system
>> resume back in LPSR mode. Because in LPSR mode, after system resume
>> back, the watermark_level register(0x44) changes to 0x08000880, which
>> set the write watermark level as 0, and set the read watermark level
>> as 128. This value is incorrect.
>>
>> This patch move the setting of watermark level register out of probe,
>> so after system resume back, mmc driver can set this watermark level
>> register back to 0x10401040.
>
> This seems all reasonable! But...
>
>>
>> Signed-off-by: Haibo Chen <haibo.c...@freescale.com>
>> ---
>> drivers/mmc/host/sdhci-esdhc-imx.c | 14 --
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
>> b/drivers/mmc/host/sdhci-esdhc-imx.c
>> index 1f1582f..1508949 100644
>> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
>> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
>> @@ -584,6 +584,14 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8
>> val, int reg)
>> mask = 0x & ~(ESDHC_CTRL_BUSWIDTH_MASK |
>> ESDHC_CTRL_D3CD);
>>
>> esdhc_clrset_le(host, mask, new_val, reg);
>> +
>> + /*
>> +* The imx6q/imx7d ROM code will change the default watermark
>> +* level setting to something insane. Change it back here.
>> +*/
>> +if (esdhc_is_usdhc(imx_data))
>> +writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
>> +
>
> ... why don't keep setting the watermark in ->probe() and instead just
> add it at as additional task to do at system PM resume?
>
I guess the reason may be keep using common sdhci_pltfrm_suspend() function
instead of creating new one.
But i think it's a good suggestion that we can create a platform
specific suspend/resume
function and put pm stuff into there for better code organization.
Haibo, you may try Ulf's suggestion.
Regards
Dong Aisheng
>> return;
>> }
>> esdhc_clrset_le(host, 0xff, val, reg);
>> @@ -1155,13 +1163,7 @@ static int sdhci_esdhc_imx_probe(struct
>> platform_device *pdev)
>> host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
>> | SDHCI_QUIRK_BROKEN_ADMA;
>>
>> - /*
>> -* The imx6q ROM code will change the default watermark level setting
>> -* to something insane. Change it back here.
>> -*/
>> if (esdhc_is_usdhc(imx_data)) {
>> - writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
>> -
>> host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
>> host->mmc->caps |= MMC_CAP_1_8V_DDR;
>>
>> --
>> 1.9.1
>>
>
> Kind regards
> Uffe
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Re: [PATCH 2/2] mmc: sdhci-esdhc-imx: correct the tuning-step setting
Hi Ulf,
On Thu, Nov 19, 2015 at 7:20 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
> On 10 November 2015 at 10:43, Haibo Chen <haibo.c...@freescale.com> wrote:
>> Here we use '|=' to set the tuning-step, but before that, we should
>> clear the tuning-step, otherwise we could got the wrong setting.
>>
>> Signed-off-by: Haibo Chen <haibo.c...@freescale.com>
>> ---
>> drivers/mmc/host/sdhci-esdhc-imx.c | 7 +--
>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
>> b/drivers/mmc/host/sdhci-esdhc-imx.c
>> index 1508949..64275c7 100644
>> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
>> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
>> @@ -76,6 +76,7 @@
>> #define ESDHC_STD_TUNING_EN(1 << 24)
>> /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
>> #define ESDHC_TUNING_START_TAP 0x1
>> +#define ESDHC_TUNING_STEP_MASK 0x0007
>> #define ESDHC_TUNING_STEP_SHIFT16
>>
>> /* pinctrl state */
>> @@ -489,9 +490,11 @@ static void esdhc_writew_le(struct sdhci_host *host,
>> u16 val, int reg)
>> m |= ESDHC_MIX_CTRL_FBCLK_SEL;
>> tuning_ctrl = readl(host->ioaddr +
>> ESDHC_TUNING_CTRL);
>> tuning_ctrl |= ESDHC_STD_TUNING_EN |
>> ESDHC_TUNING_START_TAP;
>> - if (imx_data->boarddata.tuning_step)
>> + if (imx_data->boarddata.tuning_step) {
>> + tuning_ctrl &=
>> ~ESDHC_TUNING_STEP_MASK;
>> tuning_ctrl |=
>> imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
>> - writel(tuning_ctrl, host->ioaddr +
>> ESDHC_TUNING_CTRL);
>> + }
>> + writel(tuning_ctrl, host->ioaddr +
>> ESDHC_TUNING_CTRL);
>> } else {
>> v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
>> }
>> --
>> 1.9.1
>>
>
> Looks good to me, but is there a dependency to patch 1/2 that should
> prevent me from applying this one?
>
No dependency.
Acked-by: Dong Aisheng <aisheng.d...@freescale.com>
Regards
Dong Aisheng
> Kind regards
> Uffe
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Re: [PATCH v6 0/6] mmc: imx: a few fixes and new feature
On Tue, Aug 11, 2015 at 07:38:25PM +0800, Haibo Chen wrote: Changes for v6: -remove duplicate code in esdhc_set_uhs_signaling(). -fix a typo for patch-2. -make commit log of patch-3 more specific. Haibo Chen (6): mmc: sdhci-esdhc-imx: add imx7d support and support HS400 mmc: sdhci-esdhc-imx: add tuning-step setting support mmc: sdhci-esdhc-imx: add imx7d support in bingding doc ARM: dts: imx7d-sdb: add eMMC5.0 support mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1 mmc: sdhci-esdhc-imx: change default watermark level and burst length .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 6 ++ arch/arm/boot/dts/imx7d-sdb.dts| 13 +++ drivers/mmc/host/sdhci-esdhc-imx.c | 114 - include/linux/platform_data/mmc-esdhc-imx.h| 1 + 4 files changed, 130 insertions(+), 4 deletions(-) -- 1.9.1 The patch set looks good to me. Acked-by: Dong Aisheng aisheng.d...@freescale.com Regards Dong Aisheng -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+ writel(v, host-ioaddr + ESDHC_STROBE_DLL_CTRL);
+ /* wait 1us to make sure strobe dll status register stable */
+ udelay(1);
+ v = readl(host-ioaddr + ESDHC_STROBE_DLL_STATUS);
+ if (!(v ESDHC_STROBE_DLL_STS_REF_LOCK))
+ dev_warn(mmc_dev(host-mmc),
+ warning! HS400 strobe DLL status REF not
lock!\n);
+ if (!(v ESDHC_STROBE_DLL_STS_SLV_LOCK))
+ dev_warn(mmc_dev(host-mmc),
+ warning! HS400 strobe DLL status SLV not
lock!\n);
+ }
+}
+
static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
{
+ u32 m;
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct pltfm_imx_data *imx_data = pltfm_host-priv;
struct esdhc_platform_data *boarddata = imx_data-boarddata;
+ /* disable ddr mode and disable HS400 mode */
+ m = readl(host-ioaddr + ESDHC_MIX_CTRL);
+ m = ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
+ writel(m, host-ioaddr + ESDHC_MIX_CTRL);
Is this write really required?
+ imx_data-is_ddr = 0;
+
switch (timing) {
case MMC_TIMING_UHS_SDR12:
case MMC_TIMING_UHS_SDR25:
@@ -799,9 +871,9 @@ static void esdhc_set_uhs_signaling(struct sdhci_host
*host, unsigned timing)
break;
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_MMC_DDR52:
- writel(readl(host-ioaddr + ESDHC_MIX_CTRL) |
- ESDHC_MIX_CTRL_DDREN,
- host-ioaddr + ESDHC_MIX_CTRL);
+ m = readl(host-ioaddr + ESDHC_MIX_CTRL);
Can this line be droped if using the former readback mixctl value?
+ m |= ESDHC_MIX_CTRL_DDREN;
+ writel(m, host-ioaddr + ESDHC_MIX_CTRL);
imx_data-is_ddr = 1;
if (boarddata-delay_line) {
u32 v;
@@ -813,6 +885,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host
*host, unsigned timing)
writel(v, host-ioaddr + ESDHC_DLL_CTRL);
}
break;
+ case MMC_TIMING_MMC_HS400:
+ m = readl(host-ioaddr + ESDHC_MIX_CTRL);
ditto
Regards
Dong Aisheng
+ m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
+ writel(m, host-ioaddr + ESDHC_MIX_CTRL);
+ imx_data-is_ddr = 1;
+ esdhc_set_strobe_dll(host);
+ break;
}
esdhc_change_pinstate(host, timing);
@@ -1100,6 +1179,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
if (imx_data-socdata-flags ESDHC_FLAG_ERR004536)
host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+ if (imx_data-socdata-flags ESDHC_FLAG_HS400)
+ host-quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
+
if (of_id)
err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
else
--
1.9.1
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Re: [PATCH v5 2/6] mmc: sdhci-esdhc-imx: add tuning-step seting support
On Mon, Aug 10, 2015 at 04:18:04PM +0800, Haibo Chen wrote:
tuning-step is the delay cell steps in tuning procedure. The default value
of tuning-step is 1. Some boards or cards need another value to pass the
tuning procedure. For example, imx7d-sdb board need the tuning-step value
as 2, otherwise it can't pass the tuning procedure.
So this patch add the tuning-step setting in driver, so that user can set
the tuning-step value in dts.
Fix a typo.
For patch title:
mmc: sdhci-esdhc-imx: add tuning-step seting support
s/seting/setting
Regards
Dong Aisheng
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 9 +
include/linux/platform_data/mmc-esdhc-imx.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 2a816ad..03c9f33 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -75,6 +75,7 @@
#define ESDHC_STD_TUNING_EN (1 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP 0x1
+#define ESDHC_TUNING_STEP_SHIFT 16
/* pinctrl state */
#define ESDHC_PINCTRL_STATE_100MHZ state_100mhz
@@ -474,6 +475,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
} else if (imx_data-socdata-flags ESDHC_FLAG_STD_TUNING) {
u32 v = readl(host-ioaddr + SDHCI_ACMD12_ERR);
u32 m = readl(host-ioaddr + ESDHC_MIX_CTRL);
+ u32 tuning_ctrl;
if (val SDHCI_CTRL_TUNED_CLK) {
v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
} else {
@@ -484,6 +486,11 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
if (val SDHCI_CTRL_EXEC_TUNING) {
v |= ESDHC_MIX_CTRL_EXE_TUNE;
m |= ESDHC_MIX_CTRL_FBCLK_SEL;
+ tuning_ctrl = readl(host-ioaddr +
ESDHC_TUNING_CTRL);
+ tuning_ctrl |= ESDHC_STD_TUNING_EN |
ESDHC_TUNING_START_TAP;
+ if (imx_data-boarddata.tuning_step)
+ tuning_ctrl |=
imx_data-boarddata.tuning_step ESDHC_TUNING_STEP_SHIFT;
+ writel(tuning_ctrl, host-ioaddr +
ESDHC_TUNING_CTRL);
} else {
v = ~ESDHC_MIX_CTRL_EXE_TUNE;
}
@@ -965,6 +972,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
if (gpio_is_valid(boarddata-wp_gpio))
boarddata-wp_type = ESDHC_WP_GPIO;
+ of_property_read_u32(np, fsl,tuning-step, boarddata-tuning_step);
+
if (of_find_property(np, no-1-8-v, NULL))
boarddata-support_vsel = false;
else
diff --git a/include/linux/platform_data/mmc-esdhc-imx.h
b/include/linux/platform_data/mmc-esdhc-imx.h
index e1571ef..95ccab3 100644
--- a/include/linux/platform_data/mmc-esdhc-imx.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
@@ -45,5 +45,6 @@ struct esdhc_platform_data {
int max_bus_width;
bool support_vsel;
unsigned int delay_line;
+ unsigned int tuning_step; /* The delay cell steps in tuning
procedure */
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */
--
1.9.1
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Re: [PATCH v5 3/6] mmc: sdhci-esdhc-imx: add compatible string in bingding doc
On Mon, Aug 10, 2015 at 04:18:05PM +0800, Haibo Chen wrote: Add a required property fsl,imx7d-usdhc in binding doc. Add an optional property fsl,tuning-step in binding doc. Signed-off-by: Haibo Chen haibo.c...@freescale.com You missed my former comments. The patch title is too generous. Better to change to something like: mmc: sdhci-esdhc-imx: add imx7d support in bingding doc Regards Dong Aisheng --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 211e778..dca56d6 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -15,6 +15,7 @@ Required properties: fsl,imx6q-usdhc fsl,imx6sl-usdhc fsl,imx6sx-usdhc +fsl,imx7d-usdhc Optional properties: - fsl,wp-controller : Indicate to use controller internal write protection @@ -27,6 +28,11 @@ Optional properties: transparent level shifters on the outputs of the controller. Two cells are required, first cell specifies minimum slot voltage (mV), second cell specifies maximum slot voltage (mV). Several ranges could be specified. +- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. + The uSDHC use one delay cell as default increasing step to do tuning process. + This property allows user to change the tuning step to more than one delay + cells which is useful for some special boards or cards when the default + tuning step can't find the proper delay window within limited tuning retries. Examples: -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+ writel(v, host-ioaddr + ESDHC_STROBE_DLL_CTRL);
+ /* wait 1us to make sure strobe dll status register stable */
+ udelay(1);
+ v = readl(host-ioaddr + ESDHC_STROBE_DLL_STATUS);
+ if (!(v ESDHC_STROBE_DLL_STS_REF_LOCK))
+ dev_warn(mmc_dev(host-mmc),
+ warning! HS400 strobe DLL status REF not
lock!\n);
+ if (!(v ESDHC_STROBE_DLL_STS_SLV_LOCK))
+ dev_warn(mmc_dev(host-mmc),
+ warning! HS400 strobe DLL status SLV not
lock!\n);
+ }
+}
+
static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -795,7 +860,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host
*host, unsigned timing)
case MMC_TIMING_UHS_SDR25:
case MMC_TIMING_UHS_SDR50:
case MMC_TIMING_UHS_SDR104:
+ break;
case MMC_TIMING_MMC_HS200:
+ /* disable ddr mode and disable HS400 mode */
+ writel(readl(host-ioaddr + ESDHC_MIX_CTRL)
+ ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN),
+ host-ioaddr + ESDHC_MIX_CTRL);
+ imx_data-is_ddr = 0;
Can you please explain why need above code?
Any issues if not do it?
Regards
Dong Aisheng
break;
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_MMC_DDR52:
@@ -813,6 +884,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host
*host, unsigned timing)
writel(v, host-ioaddr + ESDHC_DLL_CTRL);
}
break;
+ case MMC_TIMING_MMC_HS400:
+ writel(readl(host-ioaddr + ESDHC_MIX_CTRL) |
+ ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN,
+ host-ioaddr + ESDHC_MIX_CTRL);
+ imx_data-is_ddr = 1;
+ esdhc_set_strobe_dll(host);
+ break;
}
esdhc_change_pinstate(host, timing);
@@ -1100,6 +1178,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
if (imx_data-socdata-flags ESDHC_FLAG_ERR004536)
host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+ if (imx_data-socdata-flags ESDHC_FLAG_HS400)
+ host-quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
+
if (of_id)
err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
else
--
1.9.1
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Re: [PATCH v4 6/6] mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1
On Wed, Aug 05, 2015 at 06:38:42PM +0800, Haibo Chen wrote: Currently we find that if a usdhc is choosed to boot system, then ROM code will set the burst length enable bit of this usdhc as 0. This will make performance drop a lot if this usdhc's burst length is configed. So this patch set back the burst_length_enable bit as 1, which is the default value, and means burst length is enabled for INCR. This patch should be put before patch 5 to avoid function break, right? [PATCH v4 5/6] mmc: sdhci-esdhc-imx: change default watermark level and burst length Other than that, this patch looks good to me. Regards Dong Aisheng Signed-off-by: Haibo Chen haibo.c...@freescale.com --- drivers/mmc/host/sdhci-esdhc-imx.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 97aa944..3334762 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ #include sdhci-esdhc.h #define ESDHC_CTRL_D3CD 0x08 +#define ESDHC_BURST_LEN_EN_INCR (1 27) /* VENDOR SPEC register */ #define ESDHC_VENDOR_SPEC0xc0 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK(1 1) @@ -1165,6 +1166,21 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; host-mmc-caps |= MMC_CAP_1_8V_DDR; + /* + * ROM code will change the bit burst_length_enable setting + * to zero if this usdhc is choosed to boot system. Change + * it back here, otherwise it will impact the performance a + * lot. This bit is used to enable/disable the burst length + * for the external AHB2AXI bridge, it's usefully especially + * for INCR transfer because without burst length indicator, + * the AHB2AXI bridge does not know the burst length in + * advance. And without burst length indicator, AHB INCR + * transfer can only be converted to singles on the AXI side. + */ + writel(readl(host-ioaddr + SDHCI_HOST_CONTROL) + | ESDHC_BURST_LEN_EN_INCR, + host-ioaddr + SDHCI_HOST_CONTROL); + if (!(imx_data-socdata-flags ESDHC_FLAG_HS200)) host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/6] mmc: sdhci-esdhc-imx: add tuning-step seting support
On Wed, Aug 05, 2015 at 06:38:38PM +0800, Haibo Chen wrote:
tuning-step is the delay cell steps in tuning procedure. The default value
of tuning-step is 1. Some boards or cards need another value to pass the
tuning procedure. For example, imx7d-sdb board need the tuning-step value
as 2, otherwise it can't pass the tuning procedure.
So this patch add the tuning-step setting in driver, so that user can set
the tuning-step value in dts.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 9 +
include/linux/platform_data/mmc-esdhc-imx.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 48f009c..803d24f 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -75,6 +75,7 @@
#define ESDHC_STD_TUNING_EN (1 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP 0x1
+#define ESDHC_TUNING_STEP_SHIFT 16
/* pinctrl state */
#define ESDHC_PINCTRL_STATE_100MHZ state_100mhz
@@ -474,6 +475,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
} else if (imx_data-socdata-flags ESDHC_FLAG_STD_TUNING) {
u32 v = readl(host-ioaddr + SDHCI_ACMD12_ERR);
u32 m = readl(host-ioaddr + ESDHC_MIX_CTRL);
+ u32 tuning_ctrl;
if (val SDHCI_CTRL_TUNED_CLK) {
v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
} else {
@@ -484,6 +486,11 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
if (val SDHCI_CTRL_EXEC_TUNING) {
v |= ESDHC_MIX_CTRL_EXE_TUNE;
m |= ESDHC_MIX_CTRL_FBCLK_SEL;
+ tuning_ctrl = readl(host-ioaddr +
ESDHC_TUNING_CTRL);
+ tuning_ctrl |= ESDHC_STD_TUNING_EN |
ESDHC_TUNING_START_TAP;
+ if (imx_data-boarddata.tuning_step)
+ tuning_ctrl |=
imx_data-boarddata.tuning_step ESDHC_TUNING_STEP_SHIFT;
+ writel(tuning_ctrl, host-ioaddr +
ESDHC_TUNING_CTRL);
Is there a code indent issue here?
Otherwise, the patch looks good to me.
Regards
Dong Aisheng
} else {
v = ~ESDHC_MIX_CTRL_EXE_TUNE;
}
@@ -964,6 +971,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
if (gpio_is_valid(boarddata-wp_gpio))
boarddata-wp_type = ESDHC_WP_GPIO;
+ of_property_read_u32(np, fsl,tuning-step, boarddata-tuning_step);
+
if (of_find_property(np, no-1-8-v, NULL))
boarddata-support_vsel = false;
else
diff --git a/include/linux/platform_data/mmc-esdhc-imx.h
b/include/linux/platform_data/mmc-esdhc-imx.h
index e1571ef..95ccab3 100644
--- a/include/linux/platform_data/mmc-esdhc-imx.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
@@ -45,5 +45,6 @@ struct esdhc_platform_data {
int max_bus_width;
bool support_vsel;
unsigned int delay_line;
+ unsigned int tuning_step; /* The delay cell steps in tuning
procedure */
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */
--
1.9.1
--
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Re: [PATCH v4 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
On Fri, Aug 07, 2015 at 05:53:01PM +0800, Chen Haibo-B51421 wrote:
-Original Message-
From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
Sent: Friday, August 07, 2015 3:39 PM
To: Chen Haibo-B51421
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; shawn...@kernel.org;
ker...@pengutronix.de; li...@arm.linux.org.uk; ulf.hans...@linaro.org;
johan.dery...@barco.com; m...@pengutronix.de; Estevam Fabio-R49496; Dong
Aisheng-B29396; devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; linux-mmc@vger.kernel.org
Subject: Re: [PATCH v4 1/6] mmc: sdhci-esdhc-imx: add imx7d support and
support HS400
On Wed, Aug 05, 2015 at 06:38:37PM +0800, Haibo Chen wrote:
The imx7d usdhc is derived from imx6sx, the difference is that imx7d
support HS400.
So introduce a new compatible string for imx7d and add HS400 support
for imx7d usdhc.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 81
++
1 file changed, 81 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index c6b9f64..48f009c 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -44,6 +44,7 @@
#define ESDHC_MIX_CTRL_EXE_TUNE (1 22)
#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 23)
#define ESDHC_MIX_CTRL_FBCLK_SEL(1 25)
+#define ESDHC_MIX_CTRL_HS400_EN (1 26)
/* Bits 3 and 6 are not SDHCI standard definitions */
#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
/* Tuning bits */
@@ -60,6 +61,16 @@
#define ESDHC_TUNE_CTRL_MIN 0
#define ESDHC_TUNE_CTRL_MAX ((1 7) - 1)
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 0)
+#define ESDHC_STROBE_DLL_CTRL_RESET (1 1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS 0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK(1 1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK0x1
+
#define ESDHC_TUNING_CTRL0xcc
#define ESDHC_STD_TUNING_EN (1 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ @@
-120,6 +131,11 @@
#define ESDHC_FLAG_ERR004536 BIT(7)
/* The IP supports HS200 mode */
#define ESDHC_FLAG_HS200 BIT(8)
+/* The IP supports HS400 mode */
+#define ESDHC_FLAG_HS400 BIT(9)
+
+/* A higher clock ferquency than this rate requires strobell dll
control */
+#define ESDHC_STROBE_DLL_CLK_FREQ1
struct esdhc_soc_data {
u32 flags;
@@ -156,6 +172,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, };
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -199,6 +221,7 @@ static const struct of_device_id imx_esdhc_dt_ids[]
= {
{ .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data = usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data = usdhc_imx6q_data, },
+ { .compatible = fsl,imx7d-usdhc, .data = usdhc_imx7d_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); @@ -274,6 +297,9 @@ static
u32 esdhc_readl_le(struct sdhci_host *host, int reg)
val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
| SDHCI_USE_SDR50_TUNING;
+
+ if (imx_data-socdata-flags ESDHC_FLAG_HS400)
+ val |= SDHCI_SUPPORT_HS400;
}
}
@@ -774,6 +800,7 @@ static int esdhc_change_pinstate(struct sdhci_host
*host,
break;
case MMC_TIMING_UHS_SDR104:
case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
pinctrl = imx_data-pins_200mhz;
break;
default:
@@ -784,6 +811,44 @@ static int esdhc_change_pinstate(struct sdhci_host
*host,
return pinctrl_select_state(imx_data-pinctrl, pinctrl); }
+/*
+ * For HS400 eMMC, there is a data_strobe line, this signal is
+generated
+ * by the device and used for data output and CRC status response
+output
+ * in HS400 mode. The frequency of this signal follows the frequency
+of
+ * CLK generated by host. Host receive the data which is aligned to
+the
+ * edge of data_strobe line. Due
Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
On Wed, Aug 05, 2015 at 03:39:29PM +0800, Chen Haibo-B51421 wrote:
-Original Message-
From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
Sent: Monday, August 03, 2015 8:10 PM
To: Chen Haibo-B51421
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; shawn...@kernel.org;
ker...@pengutronix.de; li...@arm.linux.org.uk; ulf.hans...@linaro.org;
johan.dery...@barco.com; Estevam Fabio-R49496; devicet...@vger.kernel.org;
linux-ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
linux-mmc@vger.kernel.org
Subject: Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and
support HS400
On Sun, Aug 02, 2015 at 04:59:04PM +0800, Chen Haibo-B51421 wrote:
-Original Message-
From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
Sent: Friday, July 31, 2015 10:15 PM
To: Chen Haibo-B51421
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org;
ijc+shawn...@kernel.org;
ker...@pengutronix.de; li...@arm.linux.org.uk;
ulf.hans...@linaro.org; johan.dery...@barco.com; Estevam
Fabio-R49496; Dong Aisheng-B29396; devicet...@vger.kernel.org;
linux-ker...@vger.kernel.org; linux-arm- ker...@lists.infradead.org;
linux-mmc@vger.kernel.org
Subject: Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support
and support HS400
On Wed, Jul 29, 2015 at 05:03:52PM +0800, Haibo Chen wrote:
The imx7d usdhc is derived from imx6sx, the difference is that
imx7d support HS400.
So introduce a new compatible string for imx7d and add HS400
support for imx7d usdhc.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 66
++
1 file changed, 66 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index c6b9f64..b441eed 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -44,6 +44,7 @@
#define ESDHC_MIX_CTRL_EXE_TUNE (1 22)
#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 23)
#define ESDHC_MIX_CTRL_FBCLK_SEL(1 25)
+#define ESDHC_MIX_CTRL_HS400_EN (1 26)
/* Bits 3 and 6 are not SDHCI standard definitions */
#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
/* Tuning bits */
@@ -60,6 +61,16 @@
#define ESDHC_TUNE_CTRL_MIN 0
#define ESDHC_TUNE_CTRL_MAX ((1 7) - 1)
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 0)
+#define ESDHC_STROBE_DLL_CTRL_RESET (1 1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS 0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK(1 1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK0x1
+
#define ESDHC_TUNING_CTRL0xcc
#define ESDHC_STD_TUNING_EN (1 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ @@
-120,6 +131,8 @@
#define ESDHC_FLAG_ERR004536 BIT(7)
/* The IP supports HS200 mode */
#define ESDHC_FLAG_HS200 BIT(8)
+/* The IP supports HS400 mode */
+#define ESDHC_FLAG_SUP_HS400 BIT(9)
struct esdhc_soc_data {
u32 flags;
@@ -156,6 +169,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data
= {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, };
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_SUP_HS400,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -199,6 +218,7 @@ static const struct of_device_id
imx_esdhc_dt_ids[]
= {
{ .compatible = fsl,imx6sx-usdhc, .data =
usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data =
usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data =
usdhc_imx6q_data, },
+ { .compatible = fsl,imx7d-usdhc, .data =
usdhc_imx7d_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); @@ -274,6 +294,10 @@
static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
val = SDHCI_SUPPORT_DDR50 |
SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
| SDHCI_USE_SDR50_TUNING;
+
+ /* imx7d does not have a support_hs400 register,
fake
one */
You could remove this line.
It's bit
Re: [v4, 6/6] mmc: esdhc: add eMMC DDR mode support
On Fri, Jul 31, 2015 at 11:55 AM, Yangbo Lu yangbo...@freescale.com wrote:
Add eMMC DDR mode support for Freescale SDHC adapter card.
The u-boot should provide device tree properties 'adapter-type'
and 'periperal-frequency' for this feature, if not, the card
would not use DDR mode.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
---
drivers/mmc/host/sdhci-esdhc.h| 24 +++
drivers/mmc/host/sdhci-of-esdhc.c | 132
--
2 files changed, 152 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index 163ac99..015ec01 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -28,10 +28,32 @@
#define ESDHC_CLOCK_MASK 0xfff0
#define ESDHC_PREDIV_SHIFT 8
#define ESDHC_DIVIDER_SHIFT4
+#define ESDHC_CLOCK_CRDEN 0x0008
#define ESDHC_CLOCK_PEREN 0x0004
#define ESDHC_CLOCK_HCKEN 0x0002
#define ESDHC_CLOCK_IPGEN 0x0001
+#define ESDHCI_PRESENT_STATE 0x24
+#define ESDHC_CLK_STABLE 0x0008
+
+#define ESDHC_CAPABILITIES_1 0x114
+#define ESDHC_MODE_MASK0x0007
+#define ESDHC_MODE_DDR50_SEL 0xfffc
+#define ESDHC_MODE_DDR50 0x0004
+
+#define ESDHC_CLOCK_CONTROL0x144
+#define ESDHC_CLKLPBK_EXTPIN 0x8000
+#define ESDHC_CMDCLK_SHIFTED 0x8000
+
+/* SDHC Adapter Card Type */
+#define ESDHC_ADAPTER_TYPE_EMMC45 0x1/* eMMC Card Rev4.5 */
+#define ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2/* SD/MMC Legacy Card */
+#define ESDHC_ADAPTER_TYPE_EMMC44 0x3/* eMMC Card Rev4.4 */
+#define ESDHC_ADAPTER_TYPE_RSV 0x4/* Reserved */
+#define ESDHC_ADAPTER_TYPE_MMC 0x5/* MMC Card */
+#define ESDHC_ADAPTER_TYPE_SD 0x6/* SD Card Rev2.0 Rev3.0 */
+#define ESDHC_NO_ADAPTER0x7/* No Card is Present*/
+
Hi Yangbo,
You could put those of_esdhc specific defines in of_esdhc driver since
sdhci-esdhc.h
is shared by both sdhci-imx-esdhc and sdhci-of-esdhc driver.
Or it may be time to remove such dependency that each driver uses its
own head file
separately since there's already a lot difference between them and no
reason to share
the headfile anymore.
The later one might be a more reasonable way to me.
Regards
Dong Aisheng
/* pltfm-specific */
#define ESDHC_HOST_CONTROL_LE 0x20
@@ -45,6 +67,8 @@
/* OF-specific */
#define ESDHC_DMA_SYSCTL 0x40c
#define ESDHC_DMA_SNOOP0x0040
+#define ESDHC_FLUSH_ASYNC_FIFO 0x0004
+#define ESDHC_USE_PERIPHERAL_CLK0x0008
#define ESDHC_HOST_CONTROL_RES 0x01
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index f1021d8..6d7e3f9 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -24,11 +24,30 @@
#define VENDOR_V_220x12
#define VENDOR_V_230x13
+
+static u32 adapter_type;
+static bool peripheral_clk_available;
+
static u32 esdhc_readl(struct sdhci_host *host, int reg)
{
u32 ret;
- ret = sdhci_32bs_readl(host, reg);
+ if (reg == SDHCI_CAPABILITIES_1) {
+ ret = sdhci_32bs_readl(host, ESDHC_CAPABILITIES_1);
+ switch (adapter_type) {
+ case ESDHC_ADAPTER_TYPE_EMMC44:
+ if (ret ESDHC_MODE_DDR50) {
+ ret = ESDHC_MODE_DDR50_SEL;
+ /* enable 1/8V DDR capable */
+ host-mmc-caps |= MMC_CAP_1_8V_DDR;
+ } else
+ ret = ~ESDHC_MODE_MASK;
+ break;
+ default:
+ ret = ~ESDHC_MODE_MASK;
+ }
+ } else
+ ret = sdhci_32bs_readl(host, reg);
/*
* The bit of ADMA flag in eSDHC is not compatible with standard
* SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
@@ -159,8 +178,11 @@ static void esdhc_writeb(struct sdhci_host *host, u8
val, int reg)
}
/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
- if (reg == SDHCI_HOST_CONTROL)
+ if (reg == SDHCI_HOST_CONTROL) {
val = ~ESDHC_HOST_CONTROL_RES;
+ val = ~SDHCI_CTRL_HISPD;
+ val |= (sdhci_32bs_readl(host, reg) SDHCI_CTRL_HISPD);
+ }
sdhci_clrsetbits(host, 0xff, val, reg);
}
@@ -307,6 +329,84 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
sdhci_writel(host, host-ier, SDHCI_SIGNAL_ENABLE);
}
+static void esdhc_clock_control(struct sdhci_host *host, bool enable)
+{
+ u32 value;
+ u32 time_out;
+
+ value = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
+
+ if (enable)
+ value |= ESDHC_CLOCK_CRDEN;
+ else
Re: [PATCH v3 6/6] mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1
On Mon, Aug 03, 2015 at 09:08:28AM +0800, Chen Haibo-B51421 wrote: -Original Message- From: Dong Aisheng [mailto:aisheng.d...@freescale.com] Sent: Friday, July 31, 2015 10:58 PM To: Chen Haibo-B51421 Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; shawn...@kernel.org; ker...@pengutronix.de; li...@arm.linux.org.uk; ulf.hans...@linaro.org; johan.dery...@barco.com; Estevam Fabio-R49496; Dong Aisheng-B29396; devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; linux-arm- ker...@lists.infradead.org; linux-mmc@vger.kernel.org Subject: Re: [PATCH v3 6/6] mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1 On Wed, Jul 29, 2015 at 05:03:57PM +0800, Haibo Chen wrote: Currently we find that if a usdhc is choosed to boot system, then ROM code will set the burst length enable bit of this usdhc as 0. This will make performance drop a lot if this usdhc's burst length is 16. So this patch set back the burst_length_enable bit as 1, which is the default value, and means burst length is enabled for INCR. Signed-off-by: Haibo Chen haibo.c...@freescale.com --- drivers/mmc/host/sdhci-esdhc-imx.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 37d0095..dd945e5 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ #include sdhci-esdhc.h #define ESDHC_CTRL_D3CD 0x08 +#define ESDHC_BURST_LEN_EN_INCR (1 27) /* VENDOR SPEC register */ #define ESDHC_VENDOR_SPEC0xc0 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK(1 1) @@ -1158,6 +1159,16 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; host-mmc-caps |= MMC_CAP_1_8V_DDR; + /* + * ROM code will change the burst_length_enable setting to + * zero if this usdhc is choosed to boot system. Change it + * back here, otherwise it will impact the performance a + * lot if the burst length is 16. Can you clarify a bit more on why performance drops a lot if burst length is 16? Caused by the burst length setting did not work due to ROM disabled it? [haibo] this bit is used to enable/disable the burst length for the external AHB2AXI bridge, It's useful especially for INCR transfer because without burst length indicator, the AHB2AXI bridge doesn't know the burst length in advance. And without burst length indicator, AHB INCR transfers can only be converted to singles on the AXI side. Seting this bit means burst length enabled for INCR. If this bit is not set, performance will drop a lot when burst length is 8 or 16. I will add this in the commit log. Thanks for clarify. One question: with this patch, can we set the default watermark level to 64 by default for all SoC types? If yes, we may not need patch 5 anymore. [PATCH v3 5/6] mmc: sdhci-esdhc-imx: config watermark level and burst length Regards Dong Aisheng Regards Dong Aisheng + */ + writel(readl(host-ioaddr + SDHCI_HOST_CONTROL) + | ESDHC_BURST_LEN_EN_INCR, + host-ioaddr + SDHCI_HOST_CONTROL); + if (!(imx_data-socdata-flags ESDHC_FLAG_HS200)) host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
On Sun, Aug 02, 2015 at 04:59:04PM +0800, Chen Haibo-B51421 wrote:
-Original Message-
From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
Sent: Friday, July 31, 2015 10:15 PM
To: Chen Haibo-B51421
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; shawn...@kernel.org;
ker...@pengutronix.de; li...@arm.linux.org.uk; ulf.hans...@linaro.org;
johan.dery...@barco.com; Estevam Fabio-R49496; Dong Aisheng-B29396;
devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-mmc@vger.kernel.org
Subject: Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and
support HS400
On Wed, Jul 29, 2015 at 05:03:52PM +0800, Haibo Chen wrote:
The imx7d usdhc is derived from imx6sx, the difference is that imx7d
support HS400.
So introduce a new compatible string for imx7d and add HS400 support
for imx7d usdhc.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 66
++
1 file changed, 66 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index c6b9f64..b441eed 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -44,6 +44,7 @@
#define ESDHC_MIX_CTRL_EXE_TUNE (1 22)
#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 23)
#define ESDHC_MIX_CTRL_FBCLK_SEL(1 25)
+#define ESDHC_MIX_CTRL_HS400_EN (1 26)
/* Bits 3 and 6 are not SDHCI standard definitions */
#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
/* Tuning bits */
@@ -60,6 +61,16 @@
#define ESDHC_TUNE_CTRL_MIN 0
#define ESDHC_TUNE_CTRL_MAX ((1 7) - 1)
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 0)
+#define ESDHC_STROBE_DLL_CTRL_RESET (1 1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS 0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK(1 1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK0x1
+
#define ESDHC_TUNING_CTRL0xcc
#define ESDHC_STD_TUNING_EN (1 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ @@
-120,6 +131,8 @@
#define ESDHC_FLAG_ERR004536 BIT(7)
/* The IP supports HS200 mode */
#define ESDHC_FLAG_HS200 BIT(8)
+/* The IP supports HS400 mode */
+#define ESDHC_FLAG_SUP_HS400 BIT(9)
struct esdhc_soc_data {
u32 flags;
@@ -156,6 +169,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, };
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_SUP_HS400,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -199,6 +218,7 @@ static const struct of_device_id imx_esdhc_dt_ids[]
= {
{ .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data = usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data = usdhc_imx6q_data, },
+ { .compatible = fsl,imx7d-usdhc, .data = usdhc_imx7d_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); @@ -274,6 +294,10 @@
static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
| SDHCI_USE_SDR50_TUNING;
+
+ /* imx7d does not have a support_hs400 register, fake
one */
You could remove this line.
It's bit, not register and i think no need such comment.
+ if (imx_data-socdata-flags ESDHC_FLAG_SUP_HS400)
+ val |= SDHCI_SUPPORT_HS400;
}
}
@@ -774,6 +798,7 @@ static int esdhc_change_pinstate(struct sdhci_host
*host,
break;
case MMC_TIMING_UHS_SDR104:
case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
pinctrl = imx_data-pins_200mhz;
break;
default:
@@ -784,6 +809,30 @@ static int esdhc_change_pinstate(struct sdhci_host
*host,
return pinctrl_select_state(imx_data-pinctrl, pinctrl); }
+static void esdhc_set_strobe_dll(struct sdhci_host *host)
It would be good if we can add some comments for this function for better
understand.
[haibo] okay, I will add comments here.
+{
+ u32 v;
+
+ /* force a reset on strobe dll */
+ writel(ESDHC_STROBE_DLL_CTRL_RESET, host-ioaddr
Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -795,7 +844,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) case MMC_TIMING_UHS_SDR25: case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104: + break; case MMC_TIMING_MMC_HS200: + /* disable ddr mode and disable HS400 mode */ + writel(readl(host-ioaddr + ESDHC_MIX_CTRL) + ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN), + host-ioaddr + ESDHC_MIX_CTRL); + imx_data-is_ddr = 0; break; case MMC_TIMING_UHS_DDR50: case MMC_TIMING_MMC_DDR52: @@ -813,6 +868,14 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) writel(v, host-ioaddr + ESDHC_DLL_CTRL); } break; + case MMC_TIMING_MMC_HS400: + writel(readl(host-ioaddr + ESDHC_MIX_CTRL) | + ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN, + host-ioaddr + ESDHC_MIX_CTRL); + imx_data-is_ddr = 1; + if (host-clock == 2) I can't remember, but could this be a range required by SoC? + esdhc_set_strobe_dll(host); + break; } esdhc_change_pinstate(host, timing); @@ -1100,6 +1163,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) if (imx_data-socdata-flags ESDHC_FLAG_ERR004536) host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + if (imx_data-socdata-flags ESDHC_FLAG_SUP_HS400) + host-quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; + if (of_id) err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); else -- 1.9.1 Regards Dong Aisheng -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 4/6] mmc: sdhci-esdhc-imx: add compatible string in bingding doc
On Wed, Jul 29, 2015 at 05:03:55PM +0800, Haibo Chen wrote: Add a required property fsl,imx7d-usdhc in binding doc. Add an optional property fsl,tuning-step in binding doc. Better change to: mmc: sdhci-esdhc-imx: add imx7d support in bingding doc Signed-off-by: Haibo Chen haibo.c...@freescale.com --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 211e778..c6624bc 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -15,6 +15,7 @@ Required properties: fsl,imx6q-usdhc fsl,imx6sl-usdhc fsl,imx6sx-usdhc +fsl,imx7d-usdhc Optional properties: - fsl,wp-controller : Indicate to use controller internal write protection @@ -27,6 +28,7 @@ Optional properties: transparent level shifters on the outputs of the controller. Two cells are required, first cell specifies minimum slot voltage (mV), second cell specifies maximum slot voltage (mV). Several ranges could be specified. +- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. we could add more explain about this property for better understanding: e.g. The uSDHC is using one delay cell as default increasing step to do tuning process. This property allows user to change the tuning step to more than one delay cells which is useful for some special boards or cards when the default tuning step can't find the proper delay window within limited tuning reties. Examples: -- 1.9.1 Regards Dong Aisheng -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 6/6] mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1
On Wed, Jul 29, 2015 at 05:03:57PM +0800, Haibo Chen wrote: Currently we find that if a usdhc is choosed to boot system, then ROM code will set the burst length enable bit of this usdhc as 0. This will make performance drop a lot if this usdhc's burst length is 16. So this patch set back the burst_length_enable bit as 1, which is the default value, and means burst length is enabled for INCR. Signed-off-by: Haibo Chen haibo.c...@freescale.com --- drivers/mmc/host/sdhci-esdhc-imx.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 37d0095..dd945e5 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ #include sdhci-esdhc.h #define ESDHC_CTRL_D3CD 0x08 +#define ESDHC_BURST_LEN_EN_INCR (1 27) /* VENDOR SPEC register */ #define ESDHC_VENDOR_SPEC0xc0 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK(1 1) @@ -1158,6 +1159,16 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; host-mmc-caps |= MMC_CAP_1_8V_DDR; + /* + * ROM code will change the burst_length_enable setting to + * zero if this usdhc is choosed to boot system. Change it + * back here, otherwise it will impact the performance a + * lot if the burst length is 16. Can you clarify a bit more on why performance drops a lot if burst length is 16? Caused by the burst length setting did not work due to ROM disabled it? Regards Dong Aisheng + */ + writel(readl(host-ioaddr + SDHCI_HOST_CONTROL) + | ESDHC_BURST_LEN_EN_INCR, + host-ioaddr + SDHCI_HOST_CONTROL); + if (!(imx_data-socdata-flags ESDHC_FLAG_HS200)) host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 5/6] mmc: sdhci-esdhc-imx: config watermark level and burst length
On Wed, Jul 29, 2015 at 05:03:56PM +0800, Haibo Chen wrote:
i.MX7D support eMMC HS400 mode, this mode can run in 8 bit,200MHZ
DDR mode. So the I/O speed improve a lot compare to SD3.0
The default burst length is 8, if we don't change this value, in
HS400 mode, when we do eMMC read operation, we can find that the
clock signal will stop for a period of time. This means the speed
of data moving on AHB bus is slower than I/O speed. So we should
improve the speed of data moving on AHB bus.
For imx7d usdhc, this patch set the burst length as 16, and set
watermark level as 64. The test result is the clock signal has
no stop during the eMMC HS400 operation. For other imx usdhc, remain
the default value: burst length as 8, watermark level as 16.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 158f93b..37d0095 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -239,6 +239,11 @@ static inline int is_imx6q_usdhc(struct pltfm_imx_data
*data)
return data-socdata == usdhc_imx6q_data;
}
+static inline int is_imx7d_usdhc(struct pltfm_imx_data *data)
+{
+ return data-socdata == usdhc_imx7d_data;
+}
Can we using flag to check instead of adding more is_imx_usdhc()?
+
static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
{
return !!(data-socdata-flags ESDHC_FLAG_USDHC);
@@ -1145,7 +1150,11 @@ static int sdhci_esdhc_imx_probe(struct
platform_device *pdev)
* to something insane. Change it back here.
*/
if (esdhc_is_usdhc(imx_data)) {
- writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
+ if (is_imx7d_usdhc(imx_data))
+ writel(0x10401040, host-ioaddr + ESDHC_WTMK_LVL);
+ else
+ writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
+
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
Regards
Dong Aisheng
--
1.9.1
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Re: [PATCH v3 3/6] ARM: dts: imx7d-sdb: add eMMC5.0 support
On Wed, Jul 29, 2015 at 05:03:54PM +0800, Haibo Chen wrote:
imx7d-sdb board has a eMMC5.0 on usdhc3. This eMMC support HS400.
This patch add usdhc3 support for HS400
It seems this patch should be after
[PATCH v3 4/6] mmc: sdhci-esdhc-imx: add compatible string in bingding doc
Regards
Dong Aisheng
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
arch/arm/boot/dts/imx7d-sdb.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index fdd1d7c..8059458 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -241,6 +241,19 @@
status = okay;
};
+usdhc3 {
+ pinctrl-names = default, state_100mhz, state_200mhz;
+ pinctrl-0 = pinctrl_usdhc3;
+ pinctrl-1 = pinctrl_usdhc3_100mhz;
+ pinctrl-2 = pinctrl_usdhc3_200mhz;
+ assigned-clocks = clks IMX7D_USDHC3_ROOT_CLK;
+ assigned-clock-rates = 4;
+ bus-width = 8;
+ fsl,tuning-step = 2;
+ non-removable;
+ status = okay;
+};
+
iomuxc {
pinctrl-names = default;
pinctrl-0 = pinctrl_hog;
--
1.9.1
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Re: [PATCH v3 5/6] mmc: sdhci-esdhc-imx: config watermark level and burst length
On Wed, Jul 29, 2015 at 05:03:56PM +0800, Haibo Chen wrote:
i.MX7D support eMMC HS400 mode, this mode can run in 8 bit,200MHZ
DDR mode. So the I/O speed improve a lot compare to SD3.0
The default burst length is 8, if we don't change this value, in
HS400 mode, when we do eMMC read operation, we can find that the
clock signal will stop for a period of time. This means the speed
of data moving on AHB bus is slower than I/O speed. So we should
improve the speed of data moving on AHB bus.
For imx7d usdhc, this patch set the burst length as 16, and set
watermark level as 64. The test result is the clock signal has
no stop during the eMMC HS400 operation. For other imx usdhc, remain
the default value: burst length as 8, watermark level as 16.
Add please change patch title a bit since this patch change is actually
for mx7d:
mmc: sdhci-esdhc-imx: change watermark level and burst length for imx7d
Regards
Dong Aisheng
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 158f93b..37d0095 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -239,6 +239,11 @@ static inline int is_imx6q_usdhc(struct pltfm_imx_data
*data)
return data-socdata == usdhc_imx6q_data;
}
+static inline int is_imx7d_usdhc(struct pltfm_imx_data *data)
+{
+ return data-socdata == usdhc_imx7d_data;
+}
+
static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
{
return !!(data-socdata-flags ESDHC_FLAG_USDHC);
@@ -1145,7 +1150,11 @@ static int sdhci_esdhc_imx_probe(struct
platform_device *pdev)
* to something insane. Change it back here.
*/
if (esdhc_is_usdhc(imx_data)) {
- writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
+ if (is_imx7d_usdhc(imx_data))
+ writel(0x10401040, host-ioaddr + ESDHC_WTMK_LVL);
+ else
+ writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
+
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
--
1.9.1
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Re: [PATCH v3 2/6] mmc: sdhci-esdhc-imx: add tuning-step seting support
On Thu, Jul 30, 2015 at 06:25:06PM +0200, Jan Lübbe wrote: On Mi, 2015-07-29 at 17:03 +0800, Haibo Chen wrote: tuning-step is the delay cell steps in tuning procedure. The default value of tuning-step is 1. For imx6 series usdhc, tuning procedure can be passed when the tuning-step value is 1. But imx7d usdhc need the tuning-step value as 2, otherwise it can't pass the tuning procedure. So this patch add the tuning-step setting in driver, so that user can set the tuning-step value in dts. From your description, the correct tuning-step value only depends on the SoC. Why not derive it from the compatible string? 'tuning-step' actually depends on board and card. The commit message should be reformed a bit. Regards Dong Aisheng Regards, Jan Lübbe -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/6] mmc: imx: a few fixes and new feature
On Wed, Jul 29, 2015 at 05:03:51PM +0800, Haibo Chen wrote: Changes for v3: -Add property describe in binding doc. Haibo Chen (6): mmc: sdhci-esdhc-imx: add imx7d support and support HS400 mmc: sdhci-esdhc-imx: add tuning-step seting support ARM: dts: imx7d-sdb: add eMMC5.0 support mmc: sdhci-esdhc-imx: add compatible string in bingding doc mmc: sdhci-esdhc-imx: config watermark level and burst length mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1 Hi Haibo, I'm a little busy these days. Will help review it ASAP, maybe can do it tomorrow. Regards Dong Aisheng .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 + arch/arm/boot/dts/imx7d-sdb.dts| 13 +++ drivers/mmc/host/sdhci-esdhc-imx.c | 97 +- include/linux/platform_data/mmc-esdhc-imx.h| 1 + 4 files changed, 112 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 00/11] mmc: sdhci-esdhci-imx: fix cd/wp regression
This is a rebase version of former two patch series: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/351167.html http://www.spinics.net/lists/arm-kernel/msg426156.html No other changes. Commit 8d86e4f mmc: sdhci-esdhc-imx: Call mmc_of_parse() seriously break the sd card detect/write protect function of most IMX platforms since a lot of GPIO flags of cd-gpios/wp-gpios are wrongly set in devicetree. It breaks the following things: 1) cd-gpio function enable Most IMX boards GPIO card detect function becomes unwork and using card polling mode instead by mistake. Openning CONFIG_MMC_DEBUG will easily see that. It is caused by the default quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION is not cleared for dt platform by commit 8d86e4f, then MMC_CAP_NEEDS_POLL is wrongly set. This is fixed by patch 6~7 2) cd-gpio/wp-gpio polarity Before commit 8d86e4f, we do not use GPIO flags passed from devicetree. But after it, GPIO flags specfied in dt becomes valid and will affect the normal cd/wp function. This is fixed by patch 1~5 3) max-frequency not work in sdhci mmc_of_parse will parse the max-frequency from devicetree, however, its value will be overwritten by common sdhci driver finnally,so it does not actually work. Patch 8 is to fix it. 4) patch 9~11 clear unneeded parsing code after switch to mmc_of_parse(). The series is based on ulf/next tree. I also CCed this patch series to all board maintainer related in this change, hope they can help test it. I only tested some freescale IMX boards. Dong Aisheng (11): dts: imx51: fix sd card gpio polarity specified in device tree dts: imx53: fix sd card gpio polarity specified in device tree dts: imx6: fix sd card gpio polarity specified in device tree dts: imx25: fix sd card gpio polarity specified in device tree dts: imx7: fix sd card gpio polarity specified in device tree mmc: sdhci-esdhc-imx: fix cd regression for dt platform mmc: sdhci-esdhc-imx: move all non dt probe code into one function mmc: sdhci: make max-frequency property in device tree work mmc: sdhci-esdhc-imx: remove duplicated dts parsing mmc: sdhci-esdhc-imx: clear f_max in boarddata dts: mmc: fsl-imx-esdhc: remove fsl,cd-controller support .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 - arch/arm/boot/dts/imx25-pdk.dts| 4 +- arch/arm/boot/dts/imx51-apf51dev.dts | 2 +- arch/arm/boot/dts/imx53-ard.dts| 4 +- arch/arm/boot/dts/imx53-m53evk.dts | 4 +- arch/arm/boot/dts/imx53-qsb-common.dtsi| 4 +- arch/arm/boot/dts/imx53-smd.dts| 4 +- arch/arm/boot/dts/imx53-tqma53.dtsi| 4 +- arch/arm/boot/dts/imx53-tx53.dtsi | 4 +- arch/arm/boot/dts/imx53-voipac-bsb.dts | 4 +- arch/arm/boot/dts/imx6dl-riotboard.dts | 8 +- arch/arm/boot/dts/imx6q-arm2.dts | 5 +- arch/arm/boot/dts/imx6q-gk802.dts | 3 +- arch/arm/boot/dts/imx6q-tbs2910.dts| 4 +- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi| 4 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-hummingboard.dtsi| 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 8 +- arch/arm/boot/dts/imx6qdl-rex.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 6 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 8 +- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 6 +- arch/arm/boot/dts/imx6sl-evk.dts | 10 +- arch/arm/boot/dts/imx6sx-sabreauto.dts | 4 +- arch/arm/boot/dts/imx6sx-sdb.dtsi | 4 +- arch/arm/boot/dts/imx7d-sdb.dts| 4 +- drivers/mmc/host/sdhci-esdhc-imx.c | 210 ++--- drivers/mmc/host/sdhci.c | 9 +- include/linux/platform_data/mmc-esdhc-imx.h| 1 - 37 files changed, 185 insertions(+), 179 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/6] mmc: sdhci-esdhci-imx: fix cd/wp regression
On Tue, Jul 14, 2015 at 07:25:09AM +0200, Soeren Moch wrote: On 13.07.2015 13:43, Dong Aisheng wrote: On Thu, Jul 09, 2015 at 09:27:36PM +0800, Shawn Guo wrote: On Thu, Jul 09, 2015 at 05:29:50PM +0800, Dong Aisheng wrote: I agree with you. One difference is that i'd like to fix it ASAP without reverting 8d86e4f due to more patches depends on it is already there as i mentioned above.. Revert it may need to revert a lot others. The pain is that v4.1 is left broken. Oh, crap! I thought it's been there with only v4.2-rc1, and did not know v4.1 is already broken. In that case, reverting 8d86e4f isn't the best option. I suggest you rebase the dts series on top of v4.2-rc1, and send it via mmc tree. Yes, will go that way. Then you may need help take care of new dts going through your tree to make sure no broken code in again. Dong, I use a microSD card (mmc0) with the root filesystem on a tbs2910 board. I cannot see any difference between linux-4.0 and linux-4.1 (vanilla kernel with corresponding dtb), there is absolutely no problem with card detect. Can you please explain what exactly is broken in linux-4.1? The CD function is broken. If you enable CONFIG_MMC_DEBUG, you will see the MMC core keep polling the card because MMC_CAP_NEEDS_POLL is wrongly set. You can refer to cover-letter for more detailed explaination. If you're using a non-removable card(having non-removable property in dts), you may not have this issue. Regards Dong Aisheng Thanks, Soeren Thanks Regards Dong Aisheng Shawn -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/6] mmc: sdhci-esdhci-imx: fix cd/wp regression
On Mon, Jul 20, 2015 at 02:44:07PM +0200, Ulf Hansson wrote: On 13 July 2015 at 13:43, Dong Aisheng b29...@freescale.com wrote: On Thu, Jul 09, 2015 at 09:27:36PM +0800, Shawn Guo wrote: On Thu, Jul 09, 2015 at 05:29:50PM +0800, Dong Aisheng wrote: I agree with you. One difference is that i'd like to fix it ASAP without reverting 8d86e4f due to more patches depends on it is already there as i mentioned above.. Revert it may need to revert a lot others. The pain is that v4.1 is left broken. Oh, crap! I thought it's been there with only v4.2-rc1, and did not know v4.1 is already broken. In that case, reverting 8d86e4f isn't the best option. I suggest you rebase the dts series on top of v4.2-rc1, and send it via mmc tree. Yes, will go that way. Then you may need help take care of new dts going through your tree to make sure no broken code in again. Dong, Shawn, I am happy to help out, I assume you want this to go as fixes for 4.2rc[n]. Correct me if I am wrong, you want me to apply the DTS patches prior the MMC patches. I tried applying the DTS patches on 4.2rc3 - it still works nicely so no re-base is needed. So, then I need an ack from Shawn for the DTS series... Hi Ulf, I have merged the two seris into one (dts changes is before controller changes) and rebase based on your ulf/next branch. The updated patch series is just sent out for review. Shawn, Please help review and ACK for Ulf to apply. Regards Dong Aisheng Kind regards Uffe -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 02/11] dts: imx53: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx53-ard.dts | 4 ++--
arch/arm/boot/dts/imx53-m53evk.dts | 4 ++--
arch/arm/boot/dts/imx53-qsb-common.dtsi | 4 ++--
arch/arm/boot/dts/imx53-smd.dts | 4 ++--
arch/arm/boot/dts/imx53-tqma53.dtsi | 4 ++--
arch/arm/boot/dts/imx53-tx53.dtsi | 4 ++--
arch/arm/boot/dts/imx53-voipac-bsb.dts | 4 ++--
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index e9337ad..3bc1883 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -103,8 +103,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio1 1 0;
- wp-gpios = gpio1 9 0;
+ cd-gpios = gpio1 1 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio1 9 GPIO_ACTIVE_HIGH;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts
b/arch/arm/boot/dts/imx53-m53evk.dts
index d0e0f57..53f4088 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -124,8 +124,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio1 1 0;
- wp-gpios = gpio1 9 0;
+ cd-gpios = gpio1 1 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio1 9 GPIO_ACTIVE_HIGH;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi
b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index ab4ba39..b0d5542 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -147,8 +147,8 @@
esdhc3 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc3;
- cd-gpios = gpio3 11 0;
- wp-gpios = gpio3 12 0;
+ cd-gpios = gpio3 11 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio3 12 GPIO_ACTIVE_HIGH;
bus-width = 8;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 1d32557..fc89ce1 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -41,8 +41,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio3 13 0;
- wp-gpios = gpio4 11 0;
+ cd-gpios = gpio3 13 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio4 11 GPIO_ACTIVE_HIGH;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi
b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 4f1f0e2..e03373a 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -41,8 +41,8 @@
pinctrl-0 = pinctrl_esdhc2,
pinctrl_esdhc2_cdwp;
vmmc-supply = reg_3p3v;
- wp-gpios = gpio1 2 0;
- cd-gpios = gpio1 4 0;
+ wp-gpios = gpio1 2 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio1 4 GPIO_ACTIVE_LOW;
status = disabled;
};
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi
b/arch/arm/boot/dts/imx53-tx53.dtsi
index 704bd72..d3e50b2 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -183,7 +183,7 @@
};
esdhc1 {
- cd-gpios = gpio3 24 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio3 24 GPIO_ACTIVE_LOW;
fsl,wp-controller;
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
@@ -191,7 +191,7 @@
};
esdhc2 {
- cd-gpios = gpio3 25 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio3 25 GPIO_ACTIVE_LOW;
fsl,wp-controller;
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc2;
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts
b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index c17d3ad..fc51b87 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -119,8 +119,8 @@
esdhc2 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc2;
- cd-gpios = gpio3 25 0;
- wp-gpios = gpio2 19 0;
+ cd-gpios = gpio3 25 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio2 19 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
};
--
1.9.1
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[PATCH V2 03/11] dts: imx6: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx6dl-riotboard.dts | 8
arch/arm/boot/dts/imx6q-arm2.dts | 5 +++--
arch/arm/boot/dts/imx6q-gk802.dts| 3 ++-
arch/arm/boot/dts/imx6q-tbs2910.dts | 4 ++--
arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 4 +++-
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi| 2 +-
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi| 2 +-
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi| 2 +-
arch/arm/boot/dts/imx6qdl-hummingboard.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi| 4 ++--
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 8
arch/arm/boot/dts/imx6qdl-rex.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 6 +++---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 8
arch/arm/boot/dts/imx6qdl-tx6.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 6 --
arch/arm/boot/dts/imx6sl-evk.dts | 10 +-
arch/arm/boot/dts/imx6sx-sabreauto.dts | 4 ++--
arch/arm/boot/dts/imx6sx-sdb.dtsi| 4 ++--
23 files changed, 55 insertions(+), 49 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts
b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 43cb3fd..5111f51 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -305,8 +305,8 @@
usdhc2 {
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc2;
- cd-gpios = gpio1 4 0;
- wp-gpios = gpio1 2 0;
+ cd-gpios = gpio1 4 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio1 2 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
};
@@ -314,8 +314,8 @@
usdhc3 {
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3;
- cd-gpios = gpio7 0 0;
- wp-gpios = gpio7 1 0;
+ cd-gpios = gpio7 0 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio7 1 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 78df05e..d6515f7 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -11,6 +11,7 @@
*/
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
#include imx6q.dtsi
/ {
@@ -196,8 +197,8 @@
};
usdhc3 {
- cd-gpios = gpio6 11 0;
- wp-gpios = gpio6 14 0;
+ cd-gpios = gpio6 11 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio6 14 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts
b/arch/arm/boot/dts/imx6q-gk802.dts
index 703539c..00bd63e 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
#include imx6q.dtsi
/ {
@@ -161,7 +162,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3;
bus-width = 4;
- cd-gpios = gpio6 11 0;
+ cd-gpios = gpio6 11 GPIO_ACTIVE_LOW;
vmmc-supply = reg_3p3v;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts
b/arch/arm/boot/dts/imx6q-tbs2910.dts
index a43abfa..5645d52 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -251,7 +251,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc2;
bus-width = 4;
- cd-gpios = gpio2 2 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio2 2 GPIO_ACTIVE_LOW;
vmmc-supply = reg_3p3v;
status = okay;
};
@@ -260,7 +260,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3;
bus-width = 4;
- cd-gpios = gpio2 0 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio2 0 GPIO_ACTIVE_LOW;
wp-gpios = gpio2 1 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index e6d9195..f4d6ae5 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -173,7 +173,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc1;
vmmc-supply = reg_3p3v;
- cd-gpios = gpio4 7 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio4 7 GPIO_ACTIVE_LOW;
status = okay;
};
@@ -181,7 +181,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc2;
vmmc-supply = reg_3p3v;
- cd-gpios = gpio4 8
[PATCH V2 01/11] dts: imx51: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx51-apf51dev.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts
b/arch/arm/boot/dts/imx51-apf51dev.dts
index 93d3ea1..0f3fe29 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -98,7 +98,7 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio2 29 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio2 29 GPIO_ACTIVE_LOW;
bus-width = 4;
status = okay;
};
--
1.9.1
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[PATCH V2 11/11] dts: mmc: fsl-imx-esdhc: remove fsl,cd-controller support
It's not supported by driver anymore after using runtime pm
and there's no user of it, so delete it now.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 5d0376b..211e778 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -17,7 +17,6 @@ Required properties:
fsl,imx6sx-usdhc
Optional properties:
-- fsl,cd-controller : Indicate to use controller internal card detection
- fsl,wp-controller : Indicate to use controller internal write protection
- fsl,delay-line : Specify the number of delay cells for override mode.
This is used to set the clock delay for DLL(Delay Line) on override mode
@@ -35,7 +34,6 @@ esdhc@70004000 {
compatible = fsl,imx51-esdhc;
reg = 0x70004000 0x4000;
interrupts = 1;
- fsl,cd-controller;
fsl,wp-controller;
};
--
1.9.1
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[PATCH V2 09/11] mmc: sdhci-esdhc-imx: remove duplicated dts parsing
After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()), we do not need those duplicated parsing anymore. Note: fsl,cd-controller is also deleted due to the driver does not support controller card detection anymore after switch to runtime pm. And there's no user of it right now in device tree. wp-gpios is kept because we're still support fsl,wp-controller, so we need a way to check if it's gpio wp or controller wp. Signed-off-by: Dong Aisheng aisheng.d...@freescale.com --- drivers/mmc/host/sdhci-esdhc-imx.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 10f03ee..1b0e618 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -884,27 +884,13 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, struct esdhc_platform_data *boarddata = imx_data-boarddata; int ret; - if (of_get_property(np, non-removable, NULL)) - boarddata-cd_type = ESDHC_CD_PERMANENT; - - if (of_get_property(np, fsl,cd-controller, NULL)) - boarddata-cd_type = ESDHC_CD_CONTROLLER; - if (of_get_property(np, fsl,wp-controller, NULL)) boarddata-wp_type = ESDHC_WP_CONTROLLER; - boarddata-cd_gpio = of_get_named_gpio(np, cd-gpios, 0); - if (gpio_is_valid(boarddata-cd_gpio)) - boarddata-cd_type = ESDHC_CD_GPIO; - boarddata-wp_gpio = of_get_named_gpio(np, wp-gpios, 0); if (gpio_is_valid(boarddata-wp_gpio)) boarddata-wp_type = ESDHC_WP_GPIO; - of_property_read_u32(np, bus-width, boarddata-max_bus_width); - - of_property_read_u32(np, max-frequency, boarddata-f_max); - if (of_find_property(np, no-1-8-v, NULL)) boarddata-support_vsel = false; else -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 10/11] mmc: sdhci-esdhc-imx: clear f_max in boarddata
After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()),
it's not used anymore.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 7 +--
include/linux/platform_data/mmc-esdhc-imx.h | 1 -
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 1b0e618..c6b9f64 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -581,13 +581,8 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8
val, int reg)
static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
- struct pltfm_imx_data *imx_data = pltfm_host-priv;
- struct esdhc_platform_data *boarddata = imx_data-boarddata;
- if (boarddata-f_max (boarddata-f_max pltfm_host-clock))
- return boarddata-f_max;
- else
- return pltfm_host-clock;
+ return pltfm_host-clock;
}
static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
diff --git a/include/linux/platform_data/mmc-esdhc-imx.h
b/include/linux/platform_data/mmc-esdhc-imx.h
index 75f70f6..e1571ef 100644
--- a/include/linux/platform_data/mmc-esdhc-imx.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
@@ -43,7 +43,6 @@ struct esdhc_platform_data {
enum wp_types wp_type;
enum cd_types cd_type;
int max_bus_width;
- unsigned int f_max;
bool support_vsel;
unsigned int delay_line;
};
--
1.9.1
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[PATCH V2 04/11] dts: imx25: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx25-pdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index dd45e69..faf252f 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -114,8 +114,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio2 1 0;
- wp-gpios = gpio2 0 0;
+ cd-gpios = gpio2 1 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio2 0 GPIO_ACTIVE_HIGH;
status = okay;
};
--
1.9.1
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[PATCH V2 06/11] mmc: sdhci-esdhc-imx: fix cd regression for dt platform
Current card detect probe process is that when driver finds a valid
ESDHC_CD_GPIO, it will clear the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION
which is set by default for all esdhc/usdhc controllers.
Then host driver will know there's a valid card detect function.
Commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse())
breaks GPIO CD function for dt platform that it will return directly
when find ESDHC_CD_GPIO for dt platform which result in the later wrongly
to keep SDHCI_QUIRK_BROKEN_CARD_DETECTION for all dt platforms.
Then MMC_CAP_NEEDS_POLL will be used instead even there's a valid
GPIO card detect.
This patch adds back this function and follows the original approach to
clear the quirk if find an valid CD GPIO for dt platforms.
Fixes: 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse())
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index faf0cb9..4815391 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -881,6 +881,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
struct esdhc_platform_data *boarddata)
{
struct device_node *np = pdev-dev.of_node;
+ int ret;
if (!np)
return -ENODEV;
@@ -917,7 +918,14 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
mmc_of_parse_voltage(np, host-ocr_mask);
/* call to generic mmc_of_parse to support additional capabilities */
- return mmc_of_parse(host-mmc);
+ ret = mmc_of_parse(host-mmc);
+ if (ret)
+ return ret;
+
+ if (!IS_ERR_VALUE(mmc_gpio_get_cd(host-mmc)))
+ host-quirks = ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+
+ return 0;
}
#else
static inline int
--
1.9.1
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[PATCH V2 08/11] mmc: sdhci: make max-frequency property in device tree work
Device tree provides option to specify the max freqency with property
max-frequency in dts and common parse function mmc_of_parse() will
parse it and use this value to set host-f_max to tell the MMC core
the maxinum frequency the host works.
However, current sdhci driver will finally overwrite this value with
host-max_clk regardless of the max-frequency property.
This patch makes sure not overwrite the max-frequency set from device
tree and do basic sanity check.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 947033d..c83d110 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2874,6 +2874,7 @@ int sdhci_add_host(struct sdhci_host *host)
u32 max_current_caps;
unsigned int ocr_avail;
unsigned int override_timeout_clk;
+ u32 max_clk;
int ret;
WARN_ON(host == NULL);
@@ -3058,18 +3059,22 @@ int sdhci_add_host(struct sdhci_host *host)
* Set host parameters.
*/
mmc-ops = sdhci_ops;
- mmc-f_max = host-max_clk;
+ max_clk = host-max_clk;
+
if (host-ops-get_min_clock)
mmc-f_min = host-ops-get_min_clock(host);
else if (host-version = SDHCI_SPEC_300) {
if (host-clk_mul) {
mmc-f_min = (host-max_clk * host-clk_mul) / 1024;
- mmc-f_max = host-max_clk * host-clk_mul;
+ max_clk = host-max_clk * host-clk_mul;
} else
mmc-f_min = host-max_clk / SDHCI_MAX_DIV_SPEC_300;
} else
mmc-f_min = host-max_clk / SDHCI_MAX_DIV_SPEC_200;
+ if (!mmc-f_max || (mmc-f_max (mmc-f_max max_clk)))
+ mmc-f_max = max_clk;
+
if (!(host-quirks SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
host-timeout_clk = (caps[0] SDHCI_TIMEOUT_CLK_MASK)
SDHCI_TIMEOUT_CLK_SHIFT;
--
1.9.1
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[PATCH V2 05/11] dts: imx7: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx7d-sdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 4d1a4b9..fdd1d7c 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -234,8 +234,8 @@
usdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc1;
- cd-gpios = gpio5 0 0;
- wp-gpios = gpio5 1 0;
+ cd-gpios = gpio5 0 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio5 1 GPIO_ACTIVE_HIGH;
enable-sdio-wakeup;
keep-power-in-suspend;
status = okay;
--
1.9.1
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[PATCH V2 07/11] mmc: sdhci-esdhc-imx: move all non dt probe code into one function
This is an incremental fix of commit
e62bd351b(mmc: sdhci-esdhc-imx: Do not break platform data boards).
After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()),
we do not need to run the check of boarddata-wp_type/cd_type/max_bus_width
again for dt platform since those are already handled by mmc_of_parse().
Current code only exclude the checking of wp_type for dt platform which
does not make sense.
This patch moves all non dt probe code into one function.
Besides, since we only support SD3.0/eMMC HS200 for dt platform, the
support_vsel checking and ultra high speed pinctrl state are also merged
into sdhci_esdhc_imx_probe_dt.
Then we have two separately probe function for dt and non dt type.
This can make the driver probe more clearly.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 179 +++--
1 file changed, 94 insertions(+), 85 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 4815391..10f03ee 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -878,14 +878,12 @@ static const struct sdhci_pltfm_data
sdhci_esdhc_imx_pdata = {
static int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
struct sdhci_host *host,
-struct esdhc_platform_data *boarddata)
+struct pltfm_imx_data *imx_data)
{
struct device_node *np = pdev-dev.of_node;
+ struct esdhc_platform_data *boarddata = imx_data-boarddata;
int ret;
- if (!np)
- return -ENODEV;
-
if (of_get_property(np, non-removable, NULL))
boarddata-cd_type = ESDHC_CD_PERMANENT;
@@ -917,6 +915,26 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
mmc_of_parse_voltage(np, host-ocr_mask);
+ /* sdr50 and sdr104 needs work on 1.8v signal voltage */
+ if ((boarddata-support_vsel) esdhc_is_usdhc(imx_data)
+ !IS_ERR(imx_data-pins_default)) {
+ imx_data-pins_100mhz = pinctrl_lookup_state(imx_data-pinctrl,
+ ESDHC_PINCTRL_STATE_100MHZ);
+ imx_data-pins_200mhz = pinctrl_lookup_state(imx_data-pinctrl,
+ ESDHC_PINCTRL_STATE_200MHZ);
+ if (IS_ERR(imx_data-pins_100mhz) ||
+ IS_ERR(imx_data-pins_200mhz)) {
+ dev_warn(mmc_dev(host-mmc),
+ could not get ultra high speed state, work on
normal mode\n);
+ /*
+* fall back to not support uhs by specify no 1.8v quirk
+*/
+ host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+ }
+ } else {
+ host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+ }
+
/* call to generic mmc_of_parse to support additional capabilities */
ret = mmc_of_parse(host-mmc);
if (ret)
@@ -931,22 +949,85 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
static inline int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
struct sdhci_host *host,
-struct esdhc_platform_data *boarddata)
+struct pltfm_imx_data *imx_data)
{
return -ENODEV;
}
#endif
+static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
+struct sdhci_host *host,
+struct pltfm_imx_data *imx_data)
+{
+ struct esdhc_platform_data *boarddata = imx_data-boarddata;
+ int err;
+
+ if (!host-mmc-parent-platform_data) {
+ dev_err(mmc_dev(host-mmc), no board data!\n);
+ return -EINVAL;
+ }
+
+ imx_data-boarddata = *((struct esdhc_platform_data *)
+ host-mmc-parent-platform_data);
+ /* write_protect */
+ if (boarddata-wp_type == ESDHC_WP_GPIO) {
+ err = mmc_gpio_request_ro(host-mmc, boarddata-wp_gpio);
+ if (err) {
+ dev_err(mmc_dev(host-mmc),
+ failed to request write-protect gpio!\n);
+ return err;
+ }
+ host-mmc-caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
+ }
+
+ /* card_detect */
+ switch (boarddata-cd_type) {
+ case ESDHC_CD_GPIO:
+ err = mmc_gpio_request_cd(host-mmc, boarddata-cd_gpio, 0);
+ if (err) {
+ dev_err(mmc_dev(host-mmc),
+ failed to request card-detect gpio!\n);
+ return err;
+ }
+ /* fall through */
+
+ case ESDHC_CD_CONTROLLER:
+ /* we have a working card_detect back */
+ host-quirks = ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
Re: [PATCH 0/6] mmc: sdhci-esdhci-imx: fix cd/wp regression
On Thu, Jul 09, 2015 at 09:27:36PM +0800, Shawn Guo wrote: On Thu, Jul 09, 2015 at 05:29:50PM +0800, Dong Aisheng wrote: I agree with you. One difference is that i'd like to fix it ASAP without reverting 8d86e4f due to more patches depends on it is already there as i mentioned above.. Revert it may need to revert a lot others. The pain is that v4.1 is left broken. Oh, crap! I thought it's been there with only v4.2-rc1, and did not know v4.1 is already broken. In that case, reverting 8d86e4f isn't the best option. I suggest you rebase the dts series on top of v4.2-rc1, and send it via mmc tree. Yes, will go that way. Then you may need help take care of new dts going through your tree to make sure no broken code in again. Thanks Regards Dong Aisheng Shawn -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/6] mmc: sdhci-esdhc-imx: remove duplicated dts parsing
On Thu, Jul 09, 2015 at 03:38:35PM +0800, Shawn Guo wrote: On Thu, Jun 18, 2015 at 02:05:35AM +0800, Dong Aisheng wrote: After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()), we do not need those duplicated parsing anymore. Note: fsl,cd-controller is also deleted due to the driver does not support controller card detection anymore after switch to runtime pm. And there's no user of it right now in device tree. wp-gpios is kept because we're still support fsl,wp-controller, so we need a way to check if it's gpio wp or controller wp. I do not remember the reason why controller based CD stops working after we switch to runtime PM. But if CD stops working for some reason, shouldn't controller based WP stop working for the same reason? The main reason may be CD/WP function needs controller clock on. But after enable runtime pm, the clock will be disabled. See below commit: commit dacf49223fc680e6d5b5ca4ea43dcd197c1814c5 Author: Sascha Hauer s.ha...@pengutronix.de Date: Fri May 23 14:33:04 2014 +0200 ARM: dts: imx51-babbage: Fix esdhc setup Since commit 89d7e5c13122 (mmc: sdhci-esdhc-imx: add runtime pm support), controller based card detection / write protection is not supported anymore by esdhc driver. Let's use GPIO for CD/WP on esdhc1 instead. While at it, fix cd gpio polarity for esdhc2. This is wrong and currently only works because the imx esdhc driver ignores the polarity. Signed-off-by: Sascha Hauer s.ha...@pengutronix.de Signed-off-by: Shawn Guo shawn@freescale.com WP is bit different since sdhci_get_ro will call runtime_pm_get to enable clocks. So i guess WP may still work. I did not test, but i did see there's still a lot users of fsl,wp_controller in device tree which is supposed to work. There's no fsl,cd-controller users anymore. Regards Dong Aisheng Shawn Signed-off-by: Dong Aisheng aisheng.d...@freescale.com -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/6] mmc: sdhci-esdhci-imx: fix cd/wp regression
On Thu, Jul 09, 2015 at 03:50:32PM +0800, Shawn Guo wrote: On Thu, Jun 18, 2015 at 02:05:31AM +0800, Dong Aisheng wrote: Commit 8d86e4f mmc: sdhci-esdhc-imx: Call mmc_of_parse() seriously break the sd card detect/write protect function of most IMX platforms since a lot of GPIO flags of cd-gpios/wp-gpios are wrongly set in devicetree. It breaks the following things: My opinion would be that we revert the commit 8d86e4f for v4.2, as it's so broken. It may be a bit difficult since there're a few successive patches already in Ulf's tree based on 8d86e4f. Most are also fixes for 8d86e4f by Fabio. 1) cd-gpio function enable Most IMX boards GPIO card detect function becomes unwork and using card polling mode instead by mistake. Openning CONFIG_MMC_DEBUG will easily see that. It is caused by the default quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION is not cleared for dt platform by commit 8d86e4f, then MMC_CAP_NEEDS_POLL is wrongly set. Patch 1~2 is to fix it. 2) cd-gpio/wp-gpio polarity Before commit 8d86e4f, we do not use GPIO flags passed from devicetree. But after it, GPIO flags specfied in dt becomes valid and will affect the normal cd/wp function. This is fixed by another dts fix patch series: [PATCH 0/5] dts: imx: fix sd card gpio polarity specified in device tree http://www.spinics.net/lists/arm-kernel/msg426156.html Since it needs to change a lot board dts files, so i cook the patch based on Shawn/for-next branch to make sure all board dts file are changed in the same time. The dts fix patches series should be picked before this series since the driver fixes depend on the correct dts(correct GPIO polarity) to work properly. So this is a device tree ABI breakage. All the existing DTBs already installed on devices will be broken with the new kernel. You can argue that the device trees are buggy and we're fixing bugs. But if a bugfix breaks things, we should be conservative. Here is my suggestion: I agree that it's a pain, but we may have to suffer. Your below suggestion can't eventually avoid this pain. The old dts will finally not work again if upgrade to new kernel. As currently dts and kernel tree are still not separated, it may be not a serious issue and usually user uses new kernel and dts together. 1. Revert commit 8d86e4f for v4.2 2. I queue up your dts fixing series for v4.2 3. Keep things as they are for a few releases and then consider to move to mmc_of_parse() with the hope that those buggy DTBs have been upgraded during that period. I agree with you. One difference is that i'd like to fix it ASAP without reverting 8d86e4f due to more patches depends on it is already there as i mentioned above.. Revert it may need to revert a lot others. The pain is that v4.1 is left broken. How about you queue dts fixing first for v4.2 rc1, then we can fix the driver in v4.2 rc2? Regards Dong Aisheng Shawn 3) max-frequency not work in sdhci mmc_of_parse will parse the max-frequency from devicetree, however, its value will be overwritten by common sdhci driver finnally,so it does not actually work. Patch 3 is to fix it. 4) patch 4~6 clear unneeded parsing code after switch to mmc_of_parse(). The series is based on ulf/next tree. I also CCed this patch series to all board maintainer related in this change, hope they can help test it. I only tested some freescale IMX boards. BTW, There's indeed a problem here that dts fix patch series needs to be picked before this series, but it can't go through Ulf tree since some board dts changed does not in Ulf's tree. And this patch series also can not go through Shawn's tree, since mmc part change depends on some patches in Ulf tree. Two series are cross dependant. Hope you guy can find a solution for it. Those two patch series is an important fix, hopefully can catch up the final 4.1 merge window. Dong Aisheng (6): mmc: sdhci-esdhc-imx: fix cd regression for dt platform mmc: sdhci-esdhc-imx: move all non dt probe code into one function mmc: sdhci: make max-frequency property in device tree work mmc: sdhci-esdhc-imx: remove duplicated dts parsing mmc: sdhci-esdhc-imx: clear f_max in boarddata dts: mmc: fsl-imx-esdhc: remove fsl,cd-controller support .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 - drivers/mmc/host/sdhci-esdhc-imx.c | 210 ++--- drivers/mmc/host/sdhci.c | 9 +- include/linux/platform_data/mmc-esdhc-imx.h| 1 - 4 files changed, 111 insertions(+), 111 deletions(-) -- 1.9.1 ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord
Re: [PATCH v2] mmc: core: Do not set mmc voltage to 1.8V when 'no-1-8-v' is present
need to teach mmc_select_hs_ddr() and mmc_select_card_type() about the above new possible configuration. Kind regards Uffe Regards Dong Aisheng -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] mmc: core: Do not set mmc voltage to 1.8V when 'no-1-8-v' is present
On Thu, Jun 18, 2015 at 09:58:43AM +0200, Ulf Hansson wrote: On 17 June 2015 at 18:25, Fabio Estevam feste...@gmail.com wrote: Hi Ulf, On Tue, Jun 16, 2015 at 6:31 AM, Ulf Hansson ulf.hans...@linaro.org wrote: I had a closer look, should have done that before. I think we need to decide what no-1-8-v should be used for. Currently the DT documentation is unclear and depending on what SDHCI variant, the binding has different purpose. It's a mess! Thanks for your feedback. sdhci-pltfm + sdhci-esdhc-imx use the no-1-8-v DT binding to enable the SDHCI_QUIRK2_NO_1_8_V. The sdhci driver uses this quirk to mask the bus speed modes for SD UHS cards. In this regards, consider the two below options. 1) We have DT bindings for SD UHS speed modes, which somehow makes the no-1-8-v binding redundant (or deprecated). 2) If you can model the VCCQ power supply as as a regulator, you could use regulator_is_supported_voltage() API to find out similar information used to set SDHCI_QUIRK2_NO_1_8_V. In fact, sdhci already does that to mask MMC_CAP2_HSX00_1_2V, unless 1.2V is supported. In a third case, sdhci-pxav3 use the no-1-8-v DT binding to mask SDHCI_CAN_VDD_180/SDHCI_CAN_VDD_330, which seems wrong, as it has nothing to do with the power to the card (VMMC). It's also used it to mask MMC_CAP_1_8V_DDR. The summary, is that I would rather see us to move away from using the no-1-8-v DT binding and use the proper SD UHS bus speed modes binding instead. Makes sense indeed. The challenge here is that we still need to keep the old dtb's working. We need to keep something that's been broken for ever to keep working. Huh, it prevents us from doing the correct solution. :-( How hard is it to update the DTBs in these cases? Motivation for this patch was a custom mx6sl board that works fine with 3.14, but after upgrading the kernel to 4.0 the eMMC no longer can mount the rootfs. This is a regression caused by commit 312449efd16bb06, which applies 1.8V to the eMMC card that can only operate at 3.3V. Same thing happens on imx6q-sabresd: we have 3.3V voltage being supplied to the eMMC, but now we are operating it at 1.8V, even though if we have 'no-1-8-v' property in the device tree. While I understand the need for improvement that you clearly described, I would also like that the old dtb's could still work 'as-is' with a modern kernel. The path I propose here was the minimal invasive method I could come up to allow the old dtb compatibility. No, I don't want to sprinkle the core with hacks to make host driver works. Those hacks will have to reside in host drivers instead. Unless updating the DTB is out of the questions I suggest the following instead. 1) Let's add MMC_CAP_3V_DDR and a corresponding DT binding for it. Adopt mmc_select_hs_ddr() and mmc_select_card_type() to know about this configuration. Yes, that's probably a quirk way to fix the issue. Host needs to consider the DDR mode support for both 3V and 1.8v way. If host does not support 1.8V VIO but it supports DDR, then we only claim 3V DDR support. It may be something like the treating way of MMC_CAP2_HSX00_1_2V in sdhci.c. 2) If we can assume that no-1-8-v for sdhci has the meaning of enabling MMC_CAP_3V_DDR, let's do that parsing in drivers/mmc/host/sdhci-pltfm.c. For me, no-1-8-v may be better only reflect the host VIO capability, no DDR functionality. 3) Update the DT documentation to better describe the no-1-8-v binding. Let's also move it to be a sdhci specific binding and not a generic mmc binding, to limit its use. 4) Update the DTB files in the kernel for imx to use new binding for MMC_CAP_3V_DDR where applicable. Moreover convert the DTB for imx to use the proper bindings for UHS bus speed modes. Thus imx should have moved away from the no-1-8-v for future DTB updates. Yes, i agree from a long term, we should move away from no-1-8-v since no-1-8-v is not well defined. Another issue of this way is that how about host also not support 1.2v? no-1-2-v? One different option for a long term fix may be adding VIO capability in device tree. Then each host could claim it's VIO capability in device tree. Then Host driver could select the correct DDR/UHS/HSxx mode based on VIO capability. Regards Dong Aisheng Kind regards Uffe -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] drivers: mmc: sdhci: update max frequency only if undefined
On Thu, Jun 18, 2015 at 12:57:07PM +0530, Suneel Garapati wrote:
f_max parameter of mmc structure is updated unconditionally.
If dt property max-frequency is assigned, this update is
overwriting the dt property value which is undesired.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
drivers/mmc/host/sdhci.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index bc14452..c2917d5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3047,7 +3047,10 @@ int sdhci_add_host(struct sdhci_host *host)
* Set host parameters.
*/
mmc-ops = sdhci_ops;
- mmc-f_max = host-max_clk;
+
+ if(!mmc-f_max)
+ mmc-f_max = host-max_clk;
+
This is probably not going to work properly.
mmc-f_max will be overwritten again if host-clk_mul enabled.
And you did not do sanity check if f_max from device tree is valid.
Please see:
http://www.spinics.net/lists/arm-kernel/msg426167.html
I already sent a proper fix.
Regards
Dong Aisheng
if (host-ops-get_min_clock)
mmc-f_min = host-ops-get_min_clock(host);
else if (host-version = SDHCI_SPEC_300) {
--
2.1.2
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[PATCH 3/5] dts: imx6: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx6dl-riotboard.dts | 8
arch/arm/boot/dts/imx6q-arm2.dts | 5 +++--
arch/arm/boot/dts/imx6q-gk802.dts| 3 ++-
arch/arm/boot/dts/imx6q-tbs2910.dts | 4 ++--
arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 4 +++-
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi| 2 +-
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi| 2 +-
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi| 2 +-
arch/arm/boot/dts/imx6qdl-hummingboard.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi| 4 ++--
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 8
arch/arm/boot/dts/imx6qdl-rex.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 6 +++---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 8
arch/arm/boot/dts/imx6qdl-tx6.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 6 --
arch/arm/boot/dts/imx6sl-evk.dts | 10 +-
arch/arm/boot/dts/imx6sx-sabreauto.dts | 4 ++--
arch/arm/boot/dts/imx6sx-sdb.dtsi| 4 ++--
23 files changed, 55 insertions(+), 49 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts
b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 43cb3fd..5111f51 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -305,8 +305,8 @@
usdhc2 {
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc2;
- cd-gpios = gpio1 4 0;
- wp-gpios = gpio1 2 0;
+ cd-gpios = gpio1 4 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio1 2 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
};
@@ -314,8 +314,8 @@
usdhc3 {
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3;
- cd-gpios = gpio7 0 0;
- wp-gpios = gpio7 1 0;
+ cd-gpios = gpio7 0 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio7 1 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 78df05e..d6515f7 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -11,6 +11,7 @@
*/
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
#include imx6q.dtsi
/ {
@@ -196,8 +197,8 @@
};
usdhc3 {
- cd-gpios = gpio6 11 0;
- wp-gpios = gpio6 14 0;
+ cd-gpios = gpio6 11 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio6 14 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts
b/arch/arm/boot/dts/imx6q-gk802.dts
index 703539c..00bd63e 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
#include imx6q.dtsi
/ {
@@ -161,7 +162,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3;
bus-width = 4;
- cd-gpios = gpio6 11 0;
+ cd-gpios = gpio6 11 GPIO_ACTIVE_LOW;
vmmc-supply = reg_3p3v;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts
b/arch/arm/boot/dts/imx6q-tbs2910.dts
index a43abfa..5645d52 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -251,7 +251,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc2;
bus-width = 4;
- cd-gpios = gpio2 2 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio2 2 GPIO_ACTIVE_LOW;
vmmc-supply = reg_3p3v;
status = okay;
};
@@ -260,7 +260,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc3;
bus-width = 4;
- cd-gpios = gpio2 0 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio2 0 GPIO_ACTIVE_LOW;
wp-gpios = gpio2 1 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index e6d9195..f4d6ae5 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -173,7 +173,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc1;
vmmc-supply = reg_3p3v;
- cd-gpios = gpio4 7 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio4 7 GPIO_ACTIVE_LOW;
status = okay;
};
@@ -181,7 +181,7 @@
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc2;
vmmc-supply = reg_3p3v;
- cd-gpios = gpio4 8
[PATCH 4/5] dts: imx25: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx25-pdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index dd45e69..faf252f 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -114,8 +114,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio2 1 0;
- wp-gpios = gpio2 0 0;
+ cd-gpios = gpio2 1 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio2 0 GPIO_ACTIVE_HIGH;
status = okay;
};
--
1.9.1
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[PATCH 6/6] dts: mmc: fsl-imx-esdhc: remove fsl,cd-controller support
It's not supported by driver anymore after using runtime pm
and there's no user of it, so delete it now.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 5d0376b..211e778 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -17,7 +17,6 @@ Required properties:
fsl,imx6sx-usdhc
Optional properties:
-- fsl,cd-controller : Indicate to use controller internal card detection
- fsl,wp-controller : Indicate to use controller internal write protection
- fsl,delay-line : Specify the number of delay cells for override mode.
This is used to set the clock delay for DLL(Delay Line) on override mode
@@ -35,7 +34,6 @@ esdhc@70004000 {
compatible = fsl,imx51-esdhc;
reg = 0x70004000 0x4000;
interrupts = 1;
- fsl,cd-controller;
fsl,wp-controller;
};
--
1.9.1
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[PATCH 0/5] dts: imx: fix sd card gpio polarity specified in device tree
Commit 8d86e4f mmc: sdhci-esdhc-imx: Call mmc_of_parse() serious break the sd card detect/write protect function since a lot of GPIO flags of cd-gpios/wp-gpios are wrongly set in devicetree. Before commit 8d86e4f, we do not use GPIO flags passed from devicetree. But after it, GPIO flags specfied in dt becomes valid and will affect the normal cd/wp function. This patch series fixes all wrongly set GPIO flags in devicetree. Because the eSDHC/uSDHC host driver only supports MMC_CAP2_RO_ACTIVE_HIGH and no MMC_CAP2_CD_ACTIVE_HIGH, so i changed the dts accordingly. It is supposed to not cause any function break since all boards affected work well before commit 8d86e4f with this type of CAPs. However, i still CCed each board maintainer affected by this change, Please help review and let me know if any wrong change. The series is based on shawn/for-next tree. Fixes: 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()) Dong Aisheng (5): dts: imx51: fix sd card gpio polarity specified in device tree dts: imx53: fix sd card gpio polarity specified in device tree dts: imx6: fix sd card gpio polarity specified in device tree dts: imx25: fix sd card gpio polarity specified in device tree dts: imx7: fix sd card gpio polarity specified in device tree arch/arm/boot/dts/imx25-pdk.dts | 4 ++-- arch/arm/boot/dts/imx51-apf51dev.dts | 2 +- arch/arm/boot/dts/imx53-ard.dts | 4 ++-- arch/arm/boot/dts/imx53-m53evk.dts | 4 ++-- arch/arm/boot/dts/imx53-qsb-common.dtsi | 4 ++-- arch/arm/boot/dts/imx53-smd.dts | 4 ++-- arch/arm/boot/dts/imx53-tqma53.dtsi | 4 ++-- arch/arm/boot/dts/imx53-tx53.dtsi| 4 ++-- arch/arm/boot/dts/imx53-voipac-bsb.dts | 4 ++-- arch/arm/boot/dts/imx6dl-riotboard.dts | 8 arch/arm/boot/dts/imx6q-arm2.dts | 5 +++-- arch/arm/boot/dts/imx6q-gk802.dts| 3 ++- arch/arm/boot/dts/imx6q-tbs2910.dts | 4 ++-- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 4 +++- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi| 2 +- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi| 2 +- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi| 2 +- arch/arm/boot/dts/imx6qdl-hummingboard.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi| 4 ++-- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 8 arch/arm/boot/dts/imx6qdl-rex.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 6 +++--- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 8 arch/arm/boot/dts/imx6qdl-tx6.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 6 -- arch/arm/boot/dts/imx6sl-evk.dts | 10 +- arch/arm/boot/dts/imx6sx-sabreauto.dts | 4 ++-- arch/arm/boot/dts/imx6sx-sdb.dtsi| 4 ++-- arch/arm/boot/dts/imx7d-sdb.dts | 4 ++-- 33 files changed, 74 insertions(+), 68 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/6] mmc: sdhci: make max-frequency property in device tree work
Device tree provides option to specify the max freqency with property
max-frequency in dts and common parse function mmc_of_parse() will
parse it and use this value to set host-f_max to tell the MMC core
the maxinum frequency the host works.
However, current sdhci driver will finally overwrite this value with
host-max_clk regardless of the max-frequency property.
This patch makes sure not overwrite the max-frequency set from device
tree and do basic sanity check.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index bc14452..0781c92 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2866,6 +2866,7 @@ int sdhci_add_host(struct sdhci_host *host)
u32 max_current_caps;
unsigned int ocr_avail;
unsigned int override_timeout_clk;
+ u32 max_clk;
int ret;
WARN_ON(host == NULL);
@@ -3047,18 +3048,22 @@ int sdhci_add_host(struct sdhci_host *host)
* Set host parameters.
*/
mmc-ops = sdhci_ops;
- mmc-f_max = host-max_clk;
+ max_clk = host-max_clk;
+
if (host-ops-get_min_clock)
mmc-f_min = host-ops-get_min_clock(host);
else if (host-version = SDHCI_SPEC_300) {
if (host-clk_mul) {
mmc-f_min = (host-max_clk * host-clk_mul) / 1024;
- mmc-f_max = host-max_clk * host-clk_mul;
+ max_clk = host-max_clk * host-clk_mul;
} else
mmc-f_min = host-max_clk / SDHCI_MAX_DIV_SPEC_300;
} else
mmc-f_min = host-max_clk / SDHCI_MAX_DIV_SPEC_200;
+ if (!mmc-f_max || (mmc-f_max (mmc-f_max max_clk)))
+ mmc-f_max = max_clk;
+
if (!(host-quirks SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
host-timeout_clk = (caps[0] SDHCI_TIMEOUT_CLK_MASK)
SDHCI_TIMEOUT_CLK_SHIFT;
--
1.9.1
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[PATCH 0/6] mmc: sdhci-esdhci-imx: fix cd/wp regression
Commit 8d86e4f mmc: sdhci-esdhc-imx: Call mmc_of_parse() seriously break the sd card detect/write protect function of most IMX platforms since a lot of GPIO flags of cd-gpios/wp-gpios are wrongly set in devicetree. It breaks the following things: 1) cd-gpio function enable Most IMX boards GPIO card detect function becomes unwork and using card polling mode instead by mistake. Openning CONFIG_MMC_DEBUG will easily see that. It is caused by the default quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION is not cleared for dt platform by commit 8d86e4f, then MMC_CAP_NEEDS_POLL is wrongly set. Patch 1~2 is to fix it. 2) cd-gpio/wp-gpio polarity Before commit 8d86e4f, we do not use GPIO flags passed from devicetree. But after it, GPIO flags specfied in dt becomes valid and will affect the normal cd/wp function. This is fixed by another dts fix patch series: [PATCH 0/5] dts: imx: fix sd card gpio polarity specified in device tree http://www.spinics.net/lists/arm-kernel/msg426156.html Since it needs to change a lot board dts files, so i cook the patch based on Shawn/for-next branch to make sure all board dts file are changed in the same time. The dts fix patches series should be picked before this series since the driver fixes depend on the correct dts(correct GPIO polarity) to work properly. 3) max-frequency not work in sdhci mmc_of_parse will parse the max-frequency from devicetree, however, its value will be overwritten by common sdhci driver finnally,so it does not actually work. Patch 3 is to fix it. 4) patch 4~6 clear unneeded parsing code after switch to mmc_of_parse(). The series is based on ulf/next tree. I also CCed this patch series to all board maintainer related in this change, hope they can help test it. I only tested some freescale IMX boards. BTW, There's indeed a problem here that dts fix patch series needs to be picked before this series, but it can't go through Ulf tree since some board dts changed does not in Ulf's tree. And this patch series also can not go through Shawn's tree, since mmc part change depends on some patches in Ulf tree. Two series are cross dependant. Hope you guy can find a solution for it. Those two patch series is an important fix, hopefully can catch up the final 4.1 merge window. Dong Aisheng (6): mmc: sdhci-esdhc-imx: fix cd regression for dt platform mmc: sdhci-esdhc-imx: move all non dt probe code into one function mmc: sdhci: make max-frequency property in device tree work mmc: sdhci-esdhc-imx: remove duplicated dts parsing mmc: sdhci-esdhc-imx: clear f_max in boarddata dts: mmc: fsl-imx-esdhc: remove fsl,cd-controller support .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 2 - drivers/mmc/host/sdhci-esdhc-imx.c | 210 ++--- drivers/mmc/host/sdhci.c | 9 +- include/linux/platform_data/mmc-esdhc-imx.h| 1 - 4 files changed, 111 insertions(+), 111 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/6] mmc: sdhci-esdhc-imx: remove duplicated dts parsing
After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()), we do not need those duplicated parsing anymore. Note: fsl,cd-controller is also deleted due to the driver does not support controller card detection anymore after switch to runtime pm. And there's no user of it right now in device tree. wp-gpios is kept because we're still support fsl,wp-controller, so we need a way to check if it's gpio wp or controller wp. Signed-off-by: Dong Aisheng aisheng.d...@freescale.com --- drivers/mmc/host/sdhci-esdhc-imx.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 10f03ee..1b0e618 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -884,27 +884,13 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, struct esdhc_platform_data *boarddata = imx_data-boarddata; int ret; - if (of_get_property(np, non-removable, NULL)) - boarddata-cd_type = ESDHC_CD_PERMANENT; - - if (of_get_property(np, fsl,cd-controller, NULL)) - boarddata-cd_type = ESDHC_CD_CONTROLLER; - if (of_get_property(np, fsl,wp-controller, NULL)) boarddata-wp_type = ESDHC_WP_CONTROLLER; - boarddata-cd_gpio = of_get_named_gpio(np, cd-gpios, 0); - if (gpio_is_valid(boarddata-cd_gpio)) - boarddata-cd_type = ESDHC_CD_GPIO; - boarddata-wp_gpio = of_get_named_gpio(np, wp-gpios, 0); if (gpio_is_valid(boarddata-wp_gpio)) boarddata-wp_type = ESDHC_WP_GPIO; - of_property_read_u32(np, bus-width, boarddata-max_bus_width); - - of_property_read_u32(np, max-frequency, boarddata-f_max); - if (of_find_property(np, no-1-8-v, NULL)) boarddata-support_vsel = false; else -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/6] mmc: sdhci-esdhc-imx: move all non dt probe code into one function
This is an incremental fix of commit
e62bd351b(mmc: sdhci-esdhc-imx: Do not break platform data boards).
After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()),
we do not need to run the check of boarddata-wp_type/cd_type/max_bus_width
again for dt platform since those are already handled by mmc_of_parse().
Current code only exclude the checking of wp_type for dt platform which
does not make sense.
This patch moves all non dt probe code into one function.
Besides, since we only support SD3.0/eMMC HS200 for dt platform, the
support_vsel checking and ultra high speed pinctrl state are also merged
into sdhci_esdhc_imx_probe_dt.
Then we have two separately probe function for dt and non dt type.
This can make the driver probe more clearly.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 179 +++--
1 file changed, 94 insertions(+), 85 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 4815391..10f03ee 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -878,14 +878,12 @@ static const struct sdhci_pltfm_data
sdhci_esdhc_imx_pdata = {
static int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
struct sdhci_host *host,
-struct esdhc_platform_data *boarddata)
+struct pltfm_imx_data *imx_data)
{
struct device_node *np = pdev-dev.of_node;
+ struct esdhc_platform_data *boarddata = imx_data-boarddata;
int ret;
- if (!np)
- return -ENODEV;
-
if (of_get_property(np, non-removable, NULL))
boarddata-cd_type = ESDHC_CD_PERMANENT;
@@ -917,6 +915,26 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
mmc_of_parse_voltage(np, host-ocr_mask);
+ /* sdr50 and sdr104 needs work on 1.8v signal voltage */
+ if ((boarddata-support_vsel) esdhc_is_usdhc(imx_data)
+ !IS_ERR(imx_data-pins_default)) {
+ imx_data-pins_100mhz = pinctrl_lookup_state(imx_data-pinctrl,
+ ESDHC_PINCTRL_STATE_100MHZ);
+ imx_data-pins_200mhz = pinctrl_lookup_state(imx_data-pinctrl,
+ ESDHC_PINCTRL_STATE_200MHZ);
+ if (IS_ERR(imx_data-pins_100mhz) ||
+ IS_ERR(imx_data-pins_200mhz)) {
+ dev_warn(mmc_dev(host-mmc),
+ could not get ultra high speed state, work on
normal mode\n);
+ /*
+* fall back to not support uhs by specify no 1.8v quirk
+*/
+ host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+ }
+ } else {
+ host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+ }
+
/* call to generic mmc_of_parse to support additional capabilities */
ret = mmc_of_parse(host-mmc);
if (ret)
@@ -931,22 +949,85 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
static inline int
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
struct sdhci_host *host,
-struct esdhc_platform_data *boarddata)
+struct pltfm_imx_data *imx_data)
{
return -ENODEV;
}
#endif
+static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
+struct sdhci_host *host,
+struct pltfm_imx_data *imx_data)
+{
+ struct esdhc_platform_data *boarddata = imx_data-boarddata;
+ int err;
+
+ if (!host-mmc-parent-platform_data) {
+ dev_err(mmc_dev(host-mmc), no board data!\n);
+ return -EINVAL;
+ }
+
+ imx_data-boarddata = *((struct esdhc_platform_data *)
+ host-mmc-parent-platform_data);
+ /* write_protect */
+ if (boarddata-wp_type == ESDHC_WP_GPIO) {
+ err = mmc_gpio_request_ro(host-mmc, boarddata-wp_gpio);
+ if (err) {
+ dev_err(mmc_dev(host-mmc),
+ failed to request write-protect gpio!\n);
+ return err;
+ }
+ host-mmc-caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
+ }
+
+ /* card_detect */
+ switch (boarddata-cd_type) {
+ case ESDHC_CD_GPIO:
+ err = mmc_gpio_request_cd(host-mmc, boarddata-cd_gpio, 0);
+ if (err) {
+ dev_err(mmc_dev(host-mmc),
+ failed to request card-detect gpio!\n);
+ return err;
+ }
+ /* fall through */
+
+ case ESDHC_CD_CONTROLLER:
+ /* we have a working card_detect back */
+ host-quirks = ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
[PATCH 5/6] mmc: sdhci-esdhc-imx: clear f_max in boarddata
After commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse()),
it's not used anymore.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 7 +--
include/linux/platform_data/mmc-esdhc-imx.h | 1 -
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 1b0e618..c6b9f64 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -581,13 +581,8 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8
val, int reg)
static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
- struct pltfm_imx_data *imx_data = pltfm_host-priv;
- struct esdhc_platform_data *boarddata = imx_data-boarddata;
- if (boarddata-f_max (boarddata-f_max pltfm_host-clock))
- return boarddata-f_max;
- else
- return pltfm_host-clock;
+ return pltfm_host-clock;
}
static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
diff --git a/include/linux/platform_data/mmc-esdhc-imx.h
b/include/linux/platform_data/mmc-esdhc-imx.h
index 75f70f6..e1571ef 100644
--- a/include/linux/platform_data/mmc-esdhc-imx.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
@@ -43,7 +43,6 @@ struct esdhc_platform_data {
enum wp_types wp_type;
enum cd_types cd_type;
int max_bus_width;
- unsigned int f_max;
bool support_vsel;
unsigned int delay_line;
};
--
1.9.1
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[PATCH 1/6] mmc: sdhci-esdhc-imx: fix cd regression for dt platform
Current card detect probe process is that when driver finds a valid
ESDHC_CD_GPIO, it will clear the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION
which is set by default for all esdhc/usdhc controllers.
Then host driver will know there's a valid card detect function.
Commit 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse())
breaks GPIO CD function for dt platform that it will return directly
when find ESDHC_CD_GPIO for dt platform which result in the later wrongly
to keep SDHCI_QUIRK_BROKEN_CARD_DETECTION for all dt platforms.
Then MMC_CAP_NEEDS_POLL will be used instead even there's a valid
GPIO card detect.
This patch adds back this function and follows the original approach to
clear the quirk if find an valid CD GPIO for dt platforms.
Fixes: 8d86e4fcccf6 (mmc: sdhci-esdhc-imx: Call mmc_of_parse())
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index faf0cb9..4815391 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -881,6 +881,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
struct esdhc_platform_data *boarddata)
{
struct device_node *np = pdev-dev.of_node;
+ int ret;
if (!np)
return -ENODEV;
@@ -917,7 +918,14 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
mmc_of_parse_voltage(np, host-ocr_mask);
/* call to generic mmc_of_parse to support additional capabilities */
- return mmc_of_parse(host-mmc);
+ ret = mmc_of_parse(host-mmc);
+ if (ret)
+ return ret;
+
+ if (!IS_ERR_VALUE(mmc_gpio_get_cd(host-mmc)))
+ host-quirks = ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+
+ return 0;
}
#else
static inline int
--
1.9.1
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[PATCH 1/5] dts: imx51: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx51-apf51dev.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts
b/arch/arm/boot/dts/imx51-apf51dev.dts
index 93d3ea1..0f3fe29 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -98,7 +98,7 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio2 29 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio2 29 GPIO_ACTIVE_LOW;
bus-width = 4;
status = okay;
};
--
1.9.1
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[PATCH 5/5] dts: imx7: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx7d-sdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 4d1a4b9..fdd1d7c 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -234,8 +234,8 @@
usdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_usdhc1;
- cd-gpios = gpio5 0 0;
- wp-gpios = gpio5 1 0;
+ cd-gpios = gpio5 0 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio5 1 GPIO_ACTIVE_HIGH;
enable-sdio-wakeup;
keep-power-in-suspend;
status = okay;
--
1.9.1
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[PATCH 2/5] dts: imx53: fix sd card gpio polarity specified in device tree
cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
arch/arm/boot/dts/imx53-ard.dts | 4 ++--
arch/arm/boot/dts/imx53-m53evk.dts | 4 ++--
arch/arm/boot/dts/imx53-qsb-common.dtsi | 4 ++--
arch/arm/boot/dts/imx53-smd.dts | 4 ++--
arch/arm/boot/dts/imx53-tqma53.dtsi | 4 ++--
arch/arm/boot/dts/imx53-tx53.dtsi | 4 ++--
arch/arm/boot/dts/imx53-voipac-bsb.dts | 4 ++--
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index e9337ad..3bc1883 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -103,8 +103,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio1 1 0;
- wp-gpios = gpio1 9 0;
+ cd-gpios = gpio1 1 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio1 9 GPIO_ACTIVE_HIGH;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts
b/arch/arm/boot/dts/imx53-m53evk.dts
index d0e0f57..53f4088 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -124,8 +124,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio1 1 0;
- wp-gpios = gpio1 9 0;
+ cd-gpios = gpio1 1 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio1 9 GPIO_ACTIVE_HIGH;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi
b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 181ae5e..1f55187 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -147,8 +147,8 @@
esdhc3 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc3;
- cd-gpios = gpio3 11 0;
- wp-gpios = gpio3 12 0;
+ cd-gpios = gpio3 11 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio3 12 GPIO_ACTIVE_HIGH;
bus-width = 8;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 1d32557..fc89ce1 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -41,8 +41,8 @@
esdhc1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
- cd-gpios = gpio3 13 0;
- wp-gpios = gpio4 11 0;
+ cd-gpios = gpio3 13 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio4 11 GPIO_ACTIVE_HIGH;
status = okay;
};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi
b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 4f1f0e2..e03373a 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -41,8 +41,8 @@
pinctrl-0 = pinctrl_esdhc2,
pinctrl_esdhc2_cdwp;
vmmc-supply = reg_3p3v;
- wp-gpios = gpio1 2 0;
- cd-gpios = gpio1 4 0;
+ wp-gpios = gpio1 2 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio1 4 GPIO_ACTIVE_LOW;
status = disabled;
};
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi
b/arch/arm/boot/dts/imx53-tx53.dtsi
index 704bd72..d3e50b2 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -183,7 +183,7 @@
};
esdhc1 {
- cd-gpios = gpio3 24 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio3 24 GPIO_ACTIVE_LOW;
fsl,wp-controller;
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc1;
@@ -191,7 +191,7 @@
};
esdhc2 {
- cd-gpios = gpio3 25 GPIO_ACTIVE_HIGH;
+ cd-gpios = gpio3 25 GPIO_ACTIVE_LOW;
fsl,wp-controller;
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc2;
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts
b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index c17d3ad..fc51b87 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -119,8 +119,8 @@
esdhc2 {
pinctrl-names = default;
pinctrl-0 = pinctrl_esdhc2;
- cd-gpios = gpio3 25 0;
- wp-gpios = gpio2 19 0;
+ cd-gpios = gpio3 25 GPIO_ACTIVE_LOW;
+ wp-gpios = gpio2 19 GPIO_ACTIVE_HIGH;
vmmc-supply = reg_3p3v;
status = okay;
};
--
1.9.1
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Re: [PATCH] mmc: sdhci-esdhc-imx: Do not set MMC_CAP_1_8V_DDR in the 'no-1-8-v' case
Hi Fabio,
On Thu, Jun 11, 2015 at 07:08:23PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Since commit e2997c944dbdff3f (mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR
for mx6) the driver sets the MMC_CAP_1_8V_DDR flag unconditionally on
mx6, but we should not do this when the 'no-1-8-v' property is passed via
device tree.
This causes the following errors when accessing eMMC on a mx6sl board:
mmc0: MAN_BKOPS_EN bit is not set
mmc0: power class selection to bus width 8 ddr 4 failed
mmc0: error -110 whilst initialising MMC card
So only set the MMC_CAP_1_8V_DDR flag when the 'no-1-8-v' property is
absent.
With this fix in place it is possible to successfully mount the rootfs
from the emmc on a mx6sl board which has 'no-1-8-v' property passed in the
device tree.
Fixes: e2997c944dbdff3f (mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR for mx6)
Cc: sta...@vger.kernel.org
Reported-by: Kevin Lemoi kevin.le...@savant.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
I think this patch will break the eMMC DDR 3.3v mode support.
Looking at EXT_CSD_CARD_TYPE_DDR_1_8V definition,
#define EXT_CSD_CARD_TYPE_DDR_1_8V (12) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
it means the card can run at DDR mode on either 3V or 1.8V IO.
This patch disable the DDR capability unconditionally if no 1.8v IO support.
But there's indeed some confusion in mmc core that comments of MMC_CAP_1_8V_DDR
only indicates 1.8V DDR mode support which probably could be improved.
#define MMC_CAP_1_8V_DDR(1 11) /* can support */
/* DDR mode at 1.8V */
I guess why you issue passed with this change is because the DDR
mode is disabled.
Probably you need figure out why 3.3V DDR mode can't work for the board
in the issue, usually it's caused by timing, io pad setting and etc.
Regards
Dong Aisheng
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index faf0cb9..b562faf 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1005,7 +1005,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
if (esdhc_is_usdhc(imx_data)) {
writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
- host-mmc-caps |= MMC_CAP_1_8V_DDR;
if (!(imx_data-socdata-flags ESDHC_FLAG_HS200))
host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
@@ -1094,6 +1093,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
/* sdr50 and sdr104 needs work on 1.8v signal voltage */
if ((boarddata-support_vsel) esdhc_is_usdhc(imx_data)
!IS_ERR(imx_data-pins_default)) {
+ host-mmc-caps |= MMC_CAP_1_8V_DDR;
imx_data-pins_100mhz = pinctrl_lookup_state(imx_data-pinctrl,
ESDHC_PINCTRL_STATE_100MHZ);
imx_data-pins_200mhz = pinctrl_lookup_state(imx_data-pinctrl,
--
1.9.1
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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
On Mon, Jun 01, 2015 at 01:38:47PM +0530, Suman Tripathi wrote: Hi Aisheng, On Wed, May 27, 2015 at 7:46 PM, Suman Tripathi [1]stripa...@apm.com wrote: On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson [2]ulf.hans...@linaro.org wrote: On 21 May 2015 at 10:43, Suman Tripathi [3]stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi [4]stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 I have no problem with this patch, except that it would be nice to get a few tested by to make sure it doesn't break UHS support for some SoCs. Kind regards Uffe Can anyone test this in some other SoC ? Appreciate your help .. Can you test this patch on imx SoC ? (Your email have some format issue.) I have tested this patch and it does not break imx SoC. You can add my tag. Tested-by: Dong Aisheng aisheng.d...@freescale.com However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD capabiliies, not IO voltage capability. SD3.0 cards require 1.8v IO voltage support. So should this bit affect SD3.0 support? e.g. some hosts can only work at VDD_330 (most VDD of SD slot on IMX boards is using external regulator and is fixed to 3.3v), but it can support 1.8v IO voltage, so it can support SD3.0 cards as well. Ulf, Can you help confirm it? Regards Dong Aisheng -- Thanks, with regards, Suman Tripathi -- Thanks, with regards, Suman Tripathi References Visible links 1. mailto:stripa...@apm.com 2. mailto:ulf.hans...@linaro.org 3. mailto:stripa...@apm.com 4. mailto:stripa...@apm.com perl: warning: Setting locale failed. perl: warning: Please check that your locale settings: LANGUAGE = (unset), LC_ALL = (unset), LC_TIME = zh_CN.UTF-8, LC_MONETARY = zh_CN.UTF-8, LC_ADDRESS = zh_CN.UTF-8, LC_TELEPHONE = zh_CN.UTF-8, LC_NAME = zh_CN.UTF-8, LC_MEASUREMENT = zh_CN.UTF-8, LC_IDENTIFICATION = zh_CN.UTF-8, LC_NUMERIC = zh_CN.UTF-8, LC_PAPER = zh_CN.UTF-8, LANG = en_US.UTF-8 are supported and installed on your system. perl: warning: Falling back to the standard locale (C). -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/6] mmc: sdhci-esdhc-imx: add imx6sx support
From: Dong Aisheng b29...@freescale.com
The imx6sx usdhc is derived from imx6sl, the difference is minor.
imx6sx have the errata ESDHC_FLAG_ERR004536 fixed.
So introduce a new compatible string for imx6sx to distinguish them.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index a3b82d1..bcb5673 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -148,6 +148,11 @@ static struct esdhc_soc_data usdhc_imx6sl_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
+static struct esdhc_soc_data usdhc_imx6sx_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -188,6 +193,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
{ .compatible = fsl,imx35-esdhc, .data = esdhc_imx35_data, },
{ .compatible = fsl,imx51-esdhc, .data = esdhc_imx51_data, },
{ .compatible = fsl,imx53-esdhc, .data = esdhc_imx53_data, },
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data = usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data = usdhc_imx6q_data, },
{ /* sentinel */ }
--
1.9.1
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[PATCH 4/6] mmc: sdhci-esdhc-imx: using specific compatible string in binding doc
From: Dong Aisheng b29...@freescale.com
Using specific compatible string in binding doc to make the binding
more clear.
It's also used to avoid checkpatch warning in the future like follows:
WARNING: DT compatible string fsl,imx6sx-usdhc appears un-documented --
check ./Documentation/devicetree/bindings/
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
total: 0 errors, 1 warnings, 18 lines checked
Signed-off-by: Dong Aisheng b29...@freescale.com
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 415c557..5d0376b 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -7,7 +7,14 @@ This file documents differences between the core properties
described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
Required properties:
-- compatible : Should be fsl,chip-esdhc
+- compatible : Should be fsl,chip-esdhc, the supported chips include
+ fsl,imx25-esdhc
+ fsl,imx35-esdhc
+ fsl,imx51-esdhc
+ fsl,imx53-esdhc
+ fsl,imx6q-usdhc
+ fsl,imx6sl-usdhc
+ fsl,imx6sx-usdhc
Optional properties:
- fsl,cd-controller : Indicate to use controller internal card detection
--
1.9.1
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Re: [PATCH v3 1/2] mmc: sdhci: fix abort due to missing runtime PM
On Thu, May 21, 2015 at 09:15:03AM +0200, Stefan Agner wrote:
When using i.MX ESDHC driver, while entering suspend while the device
is in runtime PM, the sdhci_(suspend|resume)_host function are called
with disabled clocks. Since this functions access the SDHC host
registers, this leads to an external abort on Vybrid SoC:
[ 37.772967] Unhandled fault: imprecise external abort (0x1c06) at
0x76f5f000
[ 37.780304] Internal error: : 1c06 [#1] ARM
[ 37.784670] Modules linked in:
[ 37.787908] CPU: 0 PID: 428 Comm: sh Not tainted
3.18.0-rc5-00119-geefd097-dirty #1540
[ 37.796142] task: 8e246c00 ti: 8ca6c000 task.ti: 8ca6c000
[ 37.801785] PC is at esdhc_writel_le+0x40/0xec
[ 37.806431] LR is at sdhci_set_card_detection+0xe0/0xe4
[ 37.811877] pc : [803f0584]lr : [803eaaa0]psr: 400f0013
[ 37.811877] sp : 8ca6dd28 ip : 0001 fp : 8ca6dd3c
[ 37.823766] r10: 807a233c r9 : r8 : 8e8b7210
[ 37.829194] r7 : 802d8a08 r6 : 8082e928 r5 : r4 : 0002
[ 37.835974] r3 : 8ea34e90 r2 : 0038 r1 : r0 : 8ea32ac0
...
Clocks need to be enabled to access the registers. Fix the issue by
add runtime PM enabled pltfm implementation of suspend/resume which
take care of clocks by using the runtime PM API properly.
Signed-off-by: Stefan Agner ste...@agner.ch
---
Changes since v2:
- Implement a generic pltfm suspend/resume function instead of a local
function in sdhci-esdhc-imx.c
- Convert sdhci-pxav3 to use the runtime PM enabled pltfm suspend/resume
function too
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
drivers/mmc/host/sdhci-pltfm.c | 36
drivers/mmc/host/sdhci-pltfm.h | 2 ++
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 82f512d..7b7b3a3 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1132,7 +1132,7 @@ static int sdhci_esdhc_runtime_resume(struct device
*dev)
#endif
static const struct dev_pm_ops sdhci_esdhc_pmops = {
- SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
+ SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_rpm_suspend, sdhci_pltfm_rpm_resume)
SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
sdhci_esdhc_runtime_resume, NULL)
};
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index a207f5a..38c03cd 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -31,6 +31,7 @@
#include linux/err.h
#include linux/module.h
#include linux/of.h
+#include linux/pm_runtime.h
#ifdef CONFIG_PPC
#include asm/machdep.h
#endif
@@ -256,6 +257,41 @@ const struct dev_pm_ops sdhci_pltfm_pmops = {
.resume = sdhci_pltfm_resume,
};
EXPORT_SYMBOL_GPL(sdhci_pltfm_pmops);
+
+int sdhci_pltfm_rpm_suspend(struct device *dev)
Why invent a new API?
Can't put into sdhci_pltfm_suspend?
Regards
Dong Aisheng
+{
+ int ret;
+ struct sdhci_host *host = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+ ret = sdhci_suspend_host(host);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+ if (ret)
+ return ret;
+
+ return pm_runtime_force_suspend(dev);
+}
+EXPORT_SYMBOL_GPL(sdhci_pltfm_rpm_suspend);
+
+int sdhci_pltfm_rpm_resume(struct device *dev)
+{
+ int ret;
+ struct sdhci_host *host = dev_get_drvdata(dev);
+
+ ret = pm_runtime_force_resume(dev);
+
+ if (ret)
+ return ret;
+
+ pm_runtime_get_sync(dev);
+ ret = sdhci_resume_host(host);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_pltfm_rpm_resume);
#endif /* CONFIG_PM */
static int __init sdhci_pltfm_drv_init(void)
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index 04bc248..ac5f6ea 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -114,6 +114,8 @@ static inline void *sdhci_pltfm_priv(struct
sdhci_pltfm_host *host)
extern int sdhci_pltfm_suspend(struct device *dev);
extern int sdhci_pltfm_resume(struct device *dev);
extern const struct dev_pm_ops sdhci_pltfm_pmops;
+extern int sdhci_pltfm_rpm_suspend(struct device *dev);
+extern int sdhci_pltfm_rpm_resume(struct device *dev);
#define SDHCI_PLTFM_PMOPS (sdhci_pltfm_pmops)
#else
#define SDHCI_PLTFM_PMOPS NULL
--
2.4.1
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[PATCH 3/6] mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix
The uSDHC has an ADMA Length Mismatch errata ERR004536 which may
cause ADMA work abnormally. The errata has already been fixed for
i.MX6Q TO1.2 and i.MX6DL TO1.1 by enable the bit 7 in 0x6c register.
Unfortunately this fix is not included in i.MX6SL.
So we disable ADMA for i.MX6SL and use SDMA instead.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index fda07eb..a3b82d1 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -112,6 +112,12 @@
#define ESDHC_FLAG_STD_TUNING BIT(5)
/* The IP has SDHCI_CAPABILITIES_1 register */
#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
+/*
+ * The IP has errata ERR004536
+ * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
+ * when reading data from the card
+ */
+#define ESDHC_FLAG_ERR004536 BIT(7)
struct esdhc_soc_data {
u32 flags;
@@ -139,7 +145,7 @@ static struct esdhc_soc_data usdhc_imx6q_data = {
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
struct pltfm_imx_data {
@@ -991,6 +997,13 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
+
+ /*
+ * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
+ * TO1.1, it's harmless for MX6SL
+ */
+ writel(readl(host-ioaddr + 0x6c) | BIT(7),
+ host-ioaddr + 0x6c);
}
if (imx_data-socdata-flags ESDHC_FLAG_MAN_TUNING)
@@ -1002,6 +1015,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
host-ioaddr + ESDHC_TUNING_CTRL);
+ if (imx_data-socdata-flags ESDHC_FLAG_ERR004536)
+ host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
boarddata = imx_data-boarddata;
if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) 0) {
if (!host-mmc-parent-platform_data) {
--
1.9.1
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[PATCH 0/6] mmc: imx: a few clean up and fixes
Patch 1 is a small clean up. Patch 2-4 and 6 are small fixes. Patch 5 add mx6sx support. Dong Aisheng (6): mmc: sdhci-esdhc-imx: merge the same register check into one place mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt issue mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix mmc: sdhci-esdhc-imx: using specific compatible string in binding doc mmc: sdhci-esdhc-imx: add imx6sx support mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdl .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 9 - drivers/mmc/host/sdhci-esdhc-imx.c | 44 +- 2 files changed, 43 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/6] mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdl
The iMX6Q/DL can not support HS200 mode while iMX6SL and iMX6SX can,
so introduce a new flag to distinguish them.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index bcb5673..faf0cb9 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -118,6 +118,8 @@
* when reading data from the card
*/
#define ESDHC_FLAG_ERR004536 BIT(7)
+/* The IP supports HS200 mode */
+#define ESDHC_FLAG_HS200 BIT(8)
struct esdhc_soc_data {
u32 flags;
@@ -145,12 +147,13 @@ static struct esdhc_soc_data usdhc_imx6q_data = {
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
+ | ESDHC_FLAG_HS200,
};
static struct esdhc_soc_data usdhc_imx6sx_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
};
struct pltfm_imx_data {
@@ -1004,6 +1007,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
+ if (!(imx_data-socdata-flags ESDHC_FLAG_HS200))
+ host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
+
/*
* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
* TO1.1, it's harmless for MX6SL
--
1.9.1
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[PATCH 2/6] mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt issue
The usdhc does not have missing card interrupt issue, so don't execute
workaround for usdhc.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 0c89293..fda07eb 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -298,7 +298,7 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
u32 data;
if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
- if (val SDHCI_INT_CARD_INT) {
+ if ((val SDHCI_INT_CARD_INT) !esdhc_is_usdhc(imx_data)) {
/*
* Clear and then set D3CD bit to avoid missing the
* card interrupt. This is a eSDHC controller problem
--
1.9.1
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[PATCH 1/6] mmc: sdhci-esdhc-imx: merge the same register check into one place
In esdhc_writel_le() function, there's duplicated checking of the same
register as follows:
if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)).
Merge them into one and remove the duplicated one.
Signed-off-by: Dong Aisheng aisheng.d...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index ef290a5..0c89293 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -313,6 +313,11 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
data |= ESDHC_CTRL_D3CD;
writel(data, host-ioaddr + SDHCI_HOST_CONTROL);
}
+
+ if (val SDHCI_INT_ADMA_ERROR) {
+ val = ~SDHCI_INT_ADMA_ERROR;
+ val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
+ }
}
if (unlikely((imx_data-socdata-flags ESDHC_FLAG_MULTIBLK_NO_INT)
@@ -333,13 +338,6 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
}
}
- if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
- if (val SDHCI_INT_ADMA_ERROR) {
- val = ~SDHCI_INT_ADMA_ERROR;
- val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
- }
- }
-
writel(val, host-ioaddr + reg);
}
--
1.9.1
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Re: [RFC] i.MX25/35/SDHCI: switch off DMA usage
On Tue, Apr 14, 2015 at 11:42:00AM +0200, Juergen Borleis wrote: Hi, On Friday 27 March 2015 12:44:03 Dong Aisheng wrote: On Fri, Mar 27, 2015 at 11:52:04AM +0100, Juergen Borleis wrote: DMA and the required overhead on very small data blocks seems an expensive operation. Due to erratum ENGCM07207 for i.MX25 and i.MX35 SoCs the support for multiblock transfers is disabled which results into a huge amount of single 512 byte sector transfers and interrupts. This slows down the transmission speed to below 500 kiB/s (even at 50 MHz SD card clock). Using PIO instead of DMA to avoid ENGCM07207 happens and re-enabling multiblock transfers again improve the transmission capability up to about 2.5 MiB/s. I'm still not sure if ENGCM07207 is related to DMA only and can not happen when PIO is used instead. Someone out there with experience regarding this topic? The errata does not state it's related to DMA only. http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdf I could double check with our IC guys to confirm it. Gentle ping. Hi Juergen, Got the info from our IC guy. PIO mode is not related to AHB access, so AHB hang is not exist. But, he supposes the incorrect state machine of IP after sending CMD12 should also exist on PIO mode. We may still needs reset the controller after sending CMD12.(Reset before sending CMD12 should also work) BTW the errata already indicates a workaround for AHB hang: To abort data transfers on the AHB, software can reset the eSDHC by writing 1 to SYSCTL[24] (RSTA). So the issue could be avoided by reset controller. And the current SDHCI driver already does reset if any error(cmd or data) happens, and current MMC core seems only sending stop command when meets error. (not sending stop during normal transfer). So it looks to me the issue may already be workarounded and can not be reproduced. I'm not sure if anyone really meets the issue. By googling the original post of this patch, it seems the patch owner also did not reproduce this issue. See: http://lists.infradead.org/pipermail/linux-arm-kernel/2010-October/029818.html I would suggest someone who has the MX35/MX25 boards, to run the test again by manually triggering a data error.(e.g: shorting data line to ground during transfer). Then to see if the controller can still work well. If can not reproduce, then we can remove this errata and back to DMA mode. Regards Dong Aisheng Regards, Juergen -- Pengutronix e.K.                | Juergen Borleis       | Industrial Linux Solutions    | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] i.MX25/35/SDHCI: switch off DMA usage
On Fri, Mar 27, 2015 at 11:52:04AM +0100, Juergen Borleis wrote: DMA and the required overhead on very small data blocks seems an expensive operation. Due to erratum ENGCM07207 for i.MX25 and i.MX35 SoCs the support for multiblock transfers is disabled which results into a huge amount of single 512 byte sector transfers and interrupts. This slows down the transmission speed to below 500 kiB/s (even at 50 MHz SD card clock). Using PIO instead of DMA to avoid ENGCM07207 happens and re-enabling multiblock transfers again improve the transmission capability up to about 2.5 MiB/s. I'm still not sure if ENGCM07207 is related to DMA only and can not happen when PIO is used instead. Someone out there with experience regarding this topic? The errata does not state it's related to DMA only. http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdf I could double check with our IC guys to confirm it. Regards Dong Aisheng --- drivers/mmc/host/sdhci-esdhc-imx.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 10ef8244a239..f5fd569a17c3 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -976,8 +976,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) if (imx_data-socdata-flags ESDHC_FLAG_ENGCM07207) /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ - host-quirks |= SDHCI_QUIRK_NO_MULTIBLOCK - | SDHCI_QUIRK_BROKEN_ADMA; + host-quirks |= + SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_DMA; /* * The imx6q ROM code will change the default watermark level setting -- 1.7.10.4 Juergen -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [patch] mmc: sdhci-esdhc-imx: silence a false curly braces warning
On Thu, Feb 26, 2015 at 11:37:55PM +0300, Dan Carpenter wrote:
Static checkers suggest that probably we intended to put curly braces
around the writel() to make it part of the else path. But, I think
actually the indenting is off and the code works fine as is.
The stray tab was introduced in 0322191e6298 ('mmc: sdhci-esdhc-imx: add
sd3.0 SDR clock tuning support')
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
Yes, that's a mistake.
Thanks for the finding.
Acked-by: Dong Aisheng b29...@freescale.com
Regards
Dong Aisheng
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 10ef824..9cce5cf 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -416,7 +416,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
else
new_val = ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
- writel(new_val, host-ioaddr + ESDHC_VENDOR_SPEC);
+ writel(new_val, host-ioaddr + ESDHC_VENDOR_SPEC);
return;
case SDHCI_HOST_CONTROL2:
new_val = readl(host-ioaddr + ESDHC_VENDOR_SPEC);
--
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Re: [PATCH] mmc: sdhci: use pipeline mmc requests to improve performance
On Tue, Dec 9, 2014 at 5:04 PM, Haibo Chen haibo.c...@freescale.com wrote:
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-
|| read speed | write speed |
|
| with this patch| ~76.7 MB/s | ~23.3 MB/s |
|
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-
|| read speed | write speed |
|
| with this patch| ~40.5 MB/s | ~15.6 MB/s |
|
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-
|| read speed | write speed |
|
| with this patch| ~22.7 MB/s | ~8.2 MB/s |
|
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-
|| read speed | write speed |
|
| with this patch| ~37.3 MB/s | ~10.5 MB/s |
|
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-
Signed-off-by: Haibo Chen haibo.c...@freescale.com
Can someone else test and see if can get the same performance improvement?
Regards
Dong Aisheng
---
drivers/mmc/host/sdhci.c | 100
--
include/linux/mmc/sdhci.h | 6 +++
2 files changed, 94 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ada1a3e..50f8a4f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -55,6 +55,9 @@ static void sdhci_finish_command(struct sdhci_host *);
static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
static void sdhci_tuning_timer(unsigned long data);
static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
+static int sdhci_pre_dma_transfer(struct sdhci_host *host,
+ struct mmc_data *data,
+ struct sdhci_host_next *next);
#ifdef CONFIG_PM_RUNTIME
static int sdhci_runtime_pm_get(struct sdhci_host *host);
@@ -494,9 +497,8 @@ static int sdhci_adma_table_pre(struct sdhci_host *host,
goto fail;
BUG_ON(host-align_addr 0x3);
- host-sg_count = dma_map_sg(mmc_dev(host-mmc),
- data-sg, data-sg_len, direction);
- if (host-sg_count == 0)
+ host-sg_count = sdhci_pre_dma_transfer(host, data, NULL);
+ if (host-sg_count 0)
goto unmap_align;
desc = host-adma_desc;
@@ -633,8 +635,9 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
}
}
- dma_unmap_sg(mmc_dev(host-mmc), data-sg,
- data-sg_len, direction);
+ if (!data-host_cookie)
+ dma_unmap_sg(mmc_dev(host-mmc), data-sg,
+ data-sg_len, direction);
}
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command
*cmd)
@@ -826,11 +829,7 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
} else {
int sg_cnt;
- sg_cnt = dma_map_sg(mmc_dev(host-mmc),
- data-sg
Re: [PATCH 1/4] mmc: sdhci-esdhc-imx: Convert to mmc_send_tuning()
On Mon, Dec 01, 2014 at 05:02:07PM +0100, Ulf Hansson wrote:
Instead of having a local function taking care of sending the tuning
command, let's use the common mmc_send_tuning() API provided by the mmc
core. In this way the request will be handled as any other request by
sdhci core.
As an effect of this change, the pm_runtime_get_sync() call at
esdhc_prepare_tuning() isn't needed any more.
This patch will also introduce another change in behavior, since before
the response pattern to the tuning command wasn't verified by
sdhci-esdhc-imx. The mmc_send_tuning() does that.
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
After applying your mmc_send_tuning() fix patch and it's usage update,
i tested it worked well on a imx6dl sabreauto board.
So you can add my tag when update the patch.
Tested-by: Dong Aisheng b29...@freescale.com
Acked-by: Dong Aisheng b29...@freescale.com
Regards
Dong Aisheng
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index a33d64c..12711ab 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -717,7 +717,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host,
u32 opcode)
min = ESDHC_TUNE_CTRL_MIN;
while (min ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, min);
- if (!mmc_send_tuning(host-mmc-card))
+ if (!mmc_send_tuning(host-mmc))
break;
min += ESDHC_TUNE_CTRL_STEP;
}
@@ -726,7 +726,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host,
u32 opcode)
max = min + ESDHC_TUNE_CTRL_STEP;
while (max ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, max);
- if (mmc_send_tuning(host-mmc-card)) {
+ if (mmc_send_tuning(host-mmc)) {
max -= ESDHC_TUNE_CTRL_STEP;
break;
}
@@ -736,7 +736,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host,
u32 opcode)
/* use average delay to get the best timing */
avg = (min + max) / 2;
esdhc_prepare_tuning(host, avg);
- ret = mmc_send_tuning(host-mmc-card);
+ ret = mmc_send_tuning(host-mmc);
esdhc_post_tuning(host);
dev_dbg(mmc_dev(host-mmc), tunning %s at 0x%x ret %d\n,
---
drivers/mmc/host/sdhci-esdhc-imx.c | 68
++
1 file changed, 3 insertions(+), 65 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 0135f00..a33d64c 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -65,8 +65,6 @@
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP 0x1
-#define ESDHC_TUNING_BLOCK_PATTERN_LEN 64
-
/* pinctrl state */
#define ESDHC_PINCTRL_STATE_100MHZ state_100mhz
#define ESDHC_PINCTRL_STATE_200MHZ state_200mhz
@@ -692,8 +690,6 @@ static void esdhc_prepare_tuning(struct sdhci_host *host,
u32 val)
/* FIXME: delay a bit for card to be ready for next tuning due to
errors */
mdelay(1);
- /* This is balanced by the runtime put in sdhci_tasklet_finish */
- pm_runtime_get_sync(host-mmc-parent);
reg = readl(host-ioaddr + ESDHC_MIX_CTRL);
reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
ESDHC_MIX_CTRL_FBCLK_SEL;
@@ -704,54 +700,6 @@ static void esdhc_prepare_tuning(struct sdhci_host
*host, u32 val)
val, readl(host-ioaddr + ESDHC_TUNE_CTRL_STATUS));
}
-static void esdhc_request_done(struct mmc_request *mrq)
-{
- complete(mrq-completion);
-}
-
-static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
- struct scatterlist *sg)
-{
- struct mmc_command cmd = {0};
- struct mmc_request mrq = {NULL};
- struct mmc_data data = {0};
-
- cmd.opcode = opcode;
- cmd.arg = 0;
- cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
-
- data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
- data.blocks = 1;
- data.flags = MMC_DATA_READ;
- data.sg = sg;
- data.sg_len = 1;
-
- mrq.cmd = cmd;
- mrq.cmd-mrq = mrq;
- mrq.data = data;
- mrq.data-mrq = mrq;
- mrq.cmd-data = mrq.data;
-
- mrq.done = esdhc_request_done;
- init_completion((mrq.completion));
-
- spin_lock_irq(host-lock);
- host-mrq = mrq;
-
- sdhci_send_command(host, mrq.cmd);
-
- spin_unlock_irq(host-lock);
-
- wait_for_completion(mrq.completion);
-
- if (cmd.error)
- return cmd.error;
- if (data.error)
- return data.error;
-
- return 0;
-}
-
static void esdhc_post_tuning(struct sdhci_host *host)
{
u32 reg;
@@ -763,21 +711,13 @@ static void esdhc_post_tuning(struct sdhci_host *host)
static
Re: [PATCH 0/4] mmc: Convert host drivers to mmc_send_tuning()
On Thu, Dec 04, 2014 at 12:50:02PM -0800, Stephen Boyd wrote: On 12/01/2014 08:02 AM, Ulf Hansson wrote: Due to commit mmc: core: add core-level function for sending tuning commands, the mmc core provides an API to send the tuning command and as well compare the response pattern. Convert those host drivers which implemented their own version for how to deal with this, into using the new API. Note, this patchset has currently only been compile tested. Any help in testing on HW is higly appreciated. I get a crash on boot with these patches. I think it's because host-card is not assigned until after we do the tuning in mmc_init_card(). I took these patches and applied them on top of the patch you mentioned above. I wonder why the mmc_send_tuning() function doesn't take the mmc_host structure instead? The card structure is only used to get the host anyway. I met the same crash with it. Regards Dong Aisheng [1.199844] Unable to handle kernel NULL pointer dereference at virtual address [1.199870] pgd = c0204000 [1.207008] [] *pgd= [1.212909] Internal error: Oops: 5 [#1] PREEMPT SMP ARM [1.213153] Modules linked in: [1.221397] CPU: 0 PID: 53 Comm: kworker/u8:1 Not tainted 3.18.0-rc4-00116-g5d5e4adeefc9 #114 [1.221500] Workqueue: kmmcd mmc_rescan [1.233632] task: ee368e40 ti: ee3d2000 task.ti: ee3d2000 [1.233819] PC is at mmc_send_tuning+0x90/0x1b4 [1.239201] LR is at sdhci_msm_execute_tuning+0x1ec/0x3c8 [1.243536] pc : [c059f900]lr : [c05b2c04]psr: 6113 [1.243536] sp : ee3d3c90 ip : fp : 082a7440 [1.249099] r10: ee3cb280 r9 : 07735940 r8 : c0a03d40 [1.260375] r7 : ee3cb000 r6 : r5 : r4 : [1.265585] r3 : r2 : r1 : 6113 r0 : [1.272183] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel [1.278695] Control: 10c5787d Table: 0020406a DAC: 0015 [1.285898] Process kworker/u8:1 (pid: 53, stack limit = 0xee3d2240) [1.291800] Stack: (0xee3d3c90 to 0xee3d4000) [1.298223] 3c80: c09a4a00 2de1c000 c0a28300 [1.302482] 3ca0: c0241668 c09a25d0 [1.310642] 3cc0: [1.318802] 3ce0: c06eb3e8 [1.326962] 3d00: 0001 [1.335120] 3d20: f00bc900 [1.343286] 3d40: ee3cb000 c0a03d40 07735940 ee3cb280 082a7440 c05b2c04 [1.351443] 3d60: c09a8100 ee3cb2a8 0003 08f0d180 09a7ec80 0a6e49c0 0b2564c0 [1.359603] 3d80: 0bebc200 00020007 01090302 ee3cb000 c0599c60 0001 ee3d2000 [1.367761] 3da0: ee3d3db4 ee3cb000 a113 ee3cb2a8 0015 ee3cb000 0001 ee3cb000 [1.375919] 3dc0: ee3cb000 c05af5a0 8b60 c059fca8 ee3cb280 0001 00fa [1.384079] 3de0: 0006 03b90201 0800 0001 ee3d2000 ee3d3e0c c0241544 [1.392238] 3e00: ee3cb280 ee3cb16c ee3cb2a8 c09ae444 6113 0080 0003 c05b0e1c [1.400408] 3e20: ee3cb000 ee3cb16c 0bebc200 ee29dc00 0024 c06ed9e4 8008 c059a3a8 [1.400415] 3e40: 8008 c059b1a0 c05ae3e8 ee3cb000 ee29dc00 ee3cb000 [1.400422] 3e60: 0001 ee3cb000 0024 c059e438 00fa 0001 0001 0001 [1.400428] 3e80: fa03 3d640fff 0020 c0ff8080 ed83a000 45010053 454d3136 [1.400435] 3ea0: 4706309b d1d35000 ee3cb000 ee3cb000 00061a80 c075e2ec [1.400442] 3ec0: ee223900 c059f354 00061a80 40ff8080 ee3cb1a4 [1.400449] 3ee0: c075e2e0 c059c1ec ee3cb1a4 ee2ff500 ee00e400 c09fb8f8 ee3d2000 c0235800 [1.400455] 3f00: 0001 ee089ed8 0001 ee00e414 ee3d2000 ee3d2000 [1.400462] 3f20: ee2ff518 ee2ff500 ee00e400 0088 ee00e400 c0235b20 ee3d2000 [1.400468] 3f40: ee3a2840 ee2ff500 c0235ae4 [1.400475] 3f60: c023a30c a8a2 ee2ff500 [1.400481] 3f80: ee3d3f80 ee3d3f80 ee3d3f90 ee3d3f90 ee3d3fac ee3a2840 [1.400488] 3fa0: c023a240 c020f198 [1.400494] 3fc0: [1.400500] 3fe0: 0013 aa8a2aa8 80a0 [1.400529] [c059f900] (mmc_send_tuning) from [c05b2c04] (sdhci_msm_execute_tuning+0x1ec/0x3c8) [1.400543] [c05b2c04] (sdhci_msm_execute_tuning
Re: [PATCH] mmc: sdhci: Fix FSL ESDHC reset handling quirk
On Fri, Dec 5, 2014 at 5:58 PM, Alessio Igor Bogani
alessio.bog...@elettra.eu wrote:
The commit 0718e59ae259 (mmc: sdhci: move FSL ESDHC reset handling quirk into
esdhc code) states that Freescale esdhc is the only controller which needs
the interrupt registers restored after a reset. So it moves
SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk handling code into the
esdhc-imx driver only. Unfortunately the same controller is used in
other boards which use the of-esdhc driver instead (like powerpc P2020).
This patch partially reverts the above mentioned commit and make
SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET dependency explicit in both drivers.
Signed-off-by: Alessio Igor Bogani alessio.bog...@elettra.eu
Personally i prefer to manually restore irq in sdhci-of-esdhc driver
too as imx esdhc driver
instead of reverting the patch to avoid adding new QUIRK in common
driver if it's only
for esdhc controller.
I think people hates to see a lot QUIRK in common driver...
Regards
Dong Aisheng
---
drivers/mmc/host/sdhci-esdhc-imx.c | 13 +++--
drivers/mmc/host/sdhci-of-esdhc.c | 1 +
drivers/mmc/host/sdhci.c | 5 +
include/linux/mmc/sdhci.h | 2 ++
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 587ee0e..216e765 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -872,14 +872,6 @@ static void esdhc_set_uhs_signaling(struct sdhci_host
*host, unsigned timing)
esdhc_change_pinstate(host, timing);
}
-static void esdhc_reset(struct sdhci_host *host, u8 mask)
-{
- sdhci_reset(host, mask);
-
- sdhci_writel(host, host-ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host-ier, SDHCI_SIGNAL_ENABLE);
-}
-
static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -912,14 +904,15 @@ static struct sdhci_ops sdhci_esdhc_ops = {
.set_timeout = esdhc_set_timeout,
.set_bus_width = esdhc_pltfm_set_bus_width,
.set_uhs_signaling = esdhc_set_uhs_signaling,
- .reset = esdhc_reset,
+ .reset = sdhci_reset,
};
static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
- | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
+ | SDHCI_QUIRK_BROKEN_CARD_DETECTION
+ | SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET,
.ops = sdhci_esdhc_ops,
};
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 8872c85..9121078 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -359,6 +359,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
* host control register
*/
host-quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
+ host-quirks |= SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET;
}
/* call to generic mmc_of_parse to support additional capabilities */
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ada1a3e..ac86775 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -205,6 +205,11 @@ static void sdhci_do_reset(struct sdhci_host *host, u8
mask)
host-ops-reset(host, mask);
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) {
+ sdhci_writel(host, host-ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host-ier, SDHCI_SIGNAL_ENABLE);
+ }
+
if (mask SDHCI_RESET_ALL) {
if (host-flags (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host-ops-enable_dma)
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index dba793e..201978d 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -59,6 +59,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (116)
/* Controller does not like fast PIO transfers */
#define SDHCI_QUIRK_PIO_NEEDS_DELAY(118)
+/* Controller losing signal/interrupt enable states after reset */
+#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (119)
/* Controller has to be forced to use block size of 2048 bytes */
#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (120)
/* Controller cannot do multi-block transfers */
--
2.1.3
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WARNING: at fs/fs-writeback.c when plug out SD card after system suspend/resume
Hi ALL, We met an filesystem issue when do stable kernel upgrade from 3.10.31 to 3.10.53. And we found it's caused by the following commit bf0972039 which introduced in 3.10.53. After applying this patch, after system suspend/resume, plug out a SD card will cause the following WARNING if SD card has a filesystem mounted. If revert it, no such WARNING shows. I also tried the latest linux-next tree, it also has such issue. Looks the patch is used to fixing a potential system crashing. We're not sure whether this WARNING is as expected and reasonable or a BUG because there's no such WARNING before this patch. Can someone explain about it? Reproduce step is as follows: root@imx6qdlsolo:~# mmc2: mmc_rescan_try_freq: trying to init card at 40 Hz mmc2: Problem setting current limit! mmc2: new ultra high speed DDR50 SDHC card at address mmcblk2: mmc2: SL32G 29.7 GiB mmcblk2: p1 p2 wm8962 3-001a: Failed to get supply 'DCVDD': -517 wm8962 3-001a: Failed to request supplies: -517 i2c 3-001a: Driver wm8962 requests probe deferral kjournald starting. Commit interval 5 seconds EXT3-fs (mmcblk2p2): using internal journal EXT3-fs (mmcblk2p2): recovery complete EXT3-fs (mmcblk2p2): mounted filesystem with ordered data mode FAT-fs (mmcblk2p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. root@imx6qdlsolo:~# root@imx6qdlsolo:~# echo mem /sys/power/state PM: Syncing filesystems ... done. Freezing user space processes ... (elapsed 0.01 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. Suspending console(s) (use no_console_suspend to debug) PM: suspend of devices complete after 45.436 msecs PM: suspend devices took 0.050 seconds PM: late suspend of devices complete after 0.599 msecs PM: noirq suspend of devices complete after 0.704 msecs Disabling non-boot CPUs ... Turn off M/F mix! PM: noirq resume of devices complete after 0.380 msecs PM: early resume of devices complete after 0.498 msecs imx-sdma 20ec000.sdma: loaded firmware 1.1 mmc2: Problem setting current limit! PM: resume of devices complete after 409.704 msecs PM: resume devices took 0.410 seconds Restarting tasks ... done. root@imx6qdlsolo:~# root@imx6qdlsolo:~# libphy: 2188000.ethernet:01 - Link is Up - 100/Full mmc2: card removed [ cut here ] WARNING: at fs/fs-writeback.c:1196 __mark_inode_dirty+0x1d0/0x1d4() bdi-block not registered Modules linked in: CPU: 0 PID: 927 Comm: umount Not tainted 3.10.53-02602-g89aa41e #751 [80013b00] (unwind_backtrace+0x0/0xf4) from [80011524] (show_stack+0x10/0x14) [80011524] (show_stack+0x10/0x14) from [8002c290] (warn_slowpath_common+0x54/0x6c) [8002c290] (warn_slowpath_common+0x54/0x6c) from [8002c2d8] (warn_slowpath_fmt+0x30/0x40) [8002c2d8] (warn_slowpath_fmt+0x30/0x40) from [800e8bbc] (__mark_inode_dirty+0x1d0/0x1d4) [800e8bbc] (__mark_inode_dirty+0x1d0/0x1d4) from [80131ba8] (ext3_put_super+0x20c/0x23c) [80131ba8] (ext3_put_super+0x20c/0x23c) from [800c88e0] (generic_shutdown_super+0x58/0xc4) [800c88e0] (generic_shutdown_super+0x58/0xc4) from [800c8b14] (kill_block_super+0x18/0x68) [800c8b14] (kill_block_super+0x18/0x68) from [800c8e60] (deactivate_locked_super+0x48/0x64) [800c8e60] (deactivate_locked_super+0x48/0x64) from [800e271c] (SyS_umount+0x94/0x38c) [800e271c] (SyS_umount+0x94/0x38c) from [8000e080] (ret_fast_syscall+0x0/0x30) ---[ end trace a52c980ef229d9da ]--- EXT3-fs (mmcblk2p2): I/O error while writing superblock Caused by following commit: commit bf0972039ddc483a9cb79edae73076c635876568 Author: Jan Kara j...@suse.cz Date: Thu Apr 3 14:46:23 2014 -0700 bdi: avoid oops on device removal commit 5acda9d12dcf1ad0d9a5a2a7c646de3472fa7555 upstream. After commit 839a8e8660b6 (writeback: replace custom worker pool implementation with unbound workqueue) when device is removed while we are writing to it we crash in bdi_writeback_workfn() - set_worker_desc() because bdi-dev is NULL. This can happen because even though bdi_unregister() cancels all pending flushing work, nothing really prevents new ones from being queued from balance_dirty_pages() or other places. Fix the problem by clearing BDI_registered bit in bdi_unregister() and checking it before scheduling of any flushing work. Fixes: 839a8e8660b6777e7fe4e80af1a048aebe2b5977 Reviewed-by: Tejun Heo t...@kernel.org Signed-off-by: Jan Kara j...@suse.cz Cc: Derek Basehore dbaseh...@chromium.org Cc: Jens Axboe ax...@kernel.dk Signed-off-by: Andrew Morton a...@linux-foundation.org Signed-off-by: Linus Torvalds torva...@linux-foundation.org Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org Regards Dong Aisheng -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/8] mmc: sdhci: do not enable card detect interrupt for gpio cd type
On Tue, Sep 23, 2014 at 09:27:49AM +0200, Ulf Hansson wrote:
On 22 September 2014 11:12, Dong Aisheng b29...@freescale.com wrote:
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE,
we also do not need to handle controller native card detect interrupt
for gpio as card detect case.
If we wrong enabled the card detect interrupt for gpio case,
it will cause a lot of unexpected card detect interrupts during data
transfer
which should not happen.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 7481bd8..85cbf45 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -136,9 +136,10 @@ static void sdhci_dumpregs(struct sdhci_host *host)
static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
u32 present;
+ int gpio_cd = mmc_gpio_get_cd(host-mmc);
if ((host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
- (host-mmc-caps MMC_CAP_NONREMOVABLE))
+ (host-mmc-caps MMC_CAP_NONREMOVABLE) ||
!IS_ERR_VALUE(gpio_cd))
If you have a properly working gpio_cd, then why does you also have
SDHCI_QUIRK_BROKEN_CARD_DETECTION set? Isn't that the actual problem?
SDHCI_QUIRK_BROKEN_CARD_DETECTION seems only for controller CD function.
Thus even we're using gpio_cd, we still have this quirk set for controller
to avoid enable controller cd interrupts.
Does it make sense?
Regards
Dong Aisheng
Kind regards
Uffe
return;
if (enable) {
--
1.7.8
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[PATCH v2 8/8] mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdl
The iMX6Q/DL can not support HS200 mode while iMX6SL and iMX6SX can,
so introduce a new flag to distinguish them.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 87179c4..16eff00 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -120,6 +120,8 @@
* when reading data from the card
*/
#define ESDHC_FLAG_ERR004536 BIT(7)
+/* The IP supports HS200 mode */
+#define ESDHC_FLAG_HS200 BIT(8)
struct esdhc_soc_data {
u32 flags;
@@ -147,12 +149,13 @@ static struct esdhc_soc_data usdhc_imx6q_data = {
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
+ | ESDHC_FLAG_HS200,
};
static struct esdhc_soc_data usdhc_imx6sx_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
};
struct pltfm_imx_data {
@@ -1063,6 +1066,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
+ if (!(imx_data-socdata-flags ESDHC_FLAG_HS200))
+ host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
+
/*
* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
* TO1.1, it's harmless for MX6SL
--
1.7.8
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[PATCH v2 0/8] mmc: sdhci/imx: a few clean up and fixes
Change since v1:
Add patch 6 which resolves a checkpatch warning like below in v1:
0005-mmc-sdhci-do-not-enable-card-cd-wakeup-for-gpio-case.patch has no obvious
style problems and is ready for submission.
WARNING: DT compatible string fsl,imx6sx-usdhc appears un-documented -- check
./Documentation/devicetree/bindings/
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
total: 0 errors, 1 warnings, 18 lines checked
Dong Aisheng (8):
mmc: sdhci-esdhc-imx: remove duplicated lines
mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt
issue
mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix
mmc: sdhci: do not enable card detect interrupt for gpio cd type
mmc: sdhci: do not enable card cd wakeup for gpio case
mmc: sdhci-esdhc-imx: using specific compatible string in binding doc
mmc: sdhci-esdhc-imx: add imx6sx support
mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdl
.../devicetree/bindings/mmc/fsl-imx-esdhc.txt |9 -
drivers/mmc/host/sdhci-esdhc-imx.c | 44
drivers/mmc/host/sdhci.c |8 +++-
3 files changed, 49 insertions(+), 12 deletions(-)
--
1.7.8
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[PATCH v2 5/8] mmc: sdhci: do not enable card cd wakeup for gpio case
Do not need to enable the controller card cd interrupt wakeup
if using GPIO as card detect since it's meaningless.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 85cbf45..2b5bba1 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2561,13 +2561,16 @@ static irqreturn_t sdhci_thread_irq(int irq, void
*dev_id)
void sdhci_enable_irq_wakeups(struct sdhci_host *host)
{
u8 val;
+ int gpio_cd = mmc_gpio_get_cd(host-mmc);
+
u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
| SDHCI_WAKE_ON_INT;
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
val |= mask ;
/* Avoid fake wake up */
- if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION ||
+ !IS_ERR_VALUE(gpio_cd))
val = ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
}
--
1.7.8
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[PATCH v2 3/8] mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix
The uSDHC has an ADMA Length Mismatch errata ERR004536 which may
cause ADMA work abnormally. The errata has already been fixed for
i.MX6Q TO1.2 and i.MX6DL TO1.1 by enable the bit 7 in 0x6c register.
Unfortunately this fix is not included in i.MX6SL.
So we disable ADMA for i.MX6SL and use SDMA instead.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 18 +-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 9594bf8..dc0e384 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -114,6 +114,12 @@
#define ESDHC_FLAG_STD_TUNING BIT(5)
/* The IP has SDHCI_CAPABILITIES_1 register */
#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
+/*
+ * The IP has errata ERR004536
+ * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
+ * when reading data from the card
+ */
+#define ESDHC_FLAG_ERR004536 BIT(7)
struct esdhc_soc_data {
u32 flags;
@@ -141,7 +147,7 @@ static struct esdhc_soc_data usdhc_imx6q_data = {
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
struct pltfm_imx_data {
@@ -1050,6 +1056,13 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
+
+ /*
+* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
+* TO1.1, it's harmless for MX6SL
+*/
+ writel(readl(host-ioaddr + 0x6c) | BIT(7),
+ host-ioaddr + 0x6c);
}
if (imx_data-socdata-flags ESDHC_FLAG_MAN_TUNING)
@@ -1061,6 +1074,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
host-ioaddr + ESDHC_TUNING_CTRL);
+ if (imx_data-socdata-flags ESDHC_FLAG_ERR004536)
+ host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
boarddata = imx_data-boarddata;
if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) 0) {
if (!host-mmc-parent-platform_data) {
--
1.7.8
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[PATCH v2 7/8] mmc: sdhci-esdhc-imx: add imx6sx support
The imx6sx usdhc is derived from imx6sl, the difference is minor.
imx6sx have the errata ESDHC_FLAG_ERR004536 fixed.
So introduce a new compatible string for imx6sx to distinguish them.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index dc0e384..87179c4 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -150,6 +150,11 @@ static struct esdhc_soc_data usdhc_imx6sl_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
+static struct esdhc_soc_data usdhc_imx6sx_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -190,6 +195,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
{ .compatible = fsl,imx35-esdhc, .data = esdhc_imx35_data, },
{ .compatible = fsl,imx51-esdhc, .data = esdhc_imx51_data, },
{ .compatible = fsl,imx53-esdhc, .data = esdhc_imx53_data, },
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data = usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data = usdhc_imx6q_data, },
{ /* sentinel */ }
--
1.7.8
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[PATCH v2 4/8] mmc: sdhci: do not enable card detect interrupt for gpio cd type
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE,
we also do not need to handle controller native card detect interrupt
for gpio as card detect case.
If we wrong enabled the card detect interrupt for gpio case,
it will cause a lot of unexpected card detect interrupts during data transfer
which should not happen.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 7481bd8..85cbf45 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -136,9 +136,10 @@ static void sdhci_dumpregs(struct sdhci_host *host)
static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
u32 present;
+ int gpio_cd = mmc_gpio_get_cd(host-mmc);
if ((host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
- (host-mmc-caps MMC_CAP_NONREMOVABLE))
+ (host-mmc-caps MMC_CAP_NONREMOVABLE) || !IS_ERR_VALUE(gpio_cd))
return;
if (enable) {
--
1.7.8
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[PATCH v2 6/8] mmc: sdhci-esdhc-imx: using specific compatible string in binding doc
Using specific compatible string in binding doc to make the binding
more clear.
It's also used to avoid checkpatch warning in the future like follows:
0005-mmc-sdhci-do-not-enable-card-cd-wakeup-for-gpio-case.patch has no obvious
style problems and is ready for submission.
WARNING: DT compatible string fsl,imx6sx-usdhc appears un-documented -- check
./Documentation/devicetree/bindings/
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
total: 0 errors, 1 warnings, 18 lines checked
Signed-off-by: Dong Aisheng b29...@freescale.com
---
.../devicetree/bindings/mmc/fsl-imx-esdhc.txt |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 9046ba06..c415d34 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -7,7 +7,14 @@ This file documents differences between the core properties
described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
Required properties:
-- compatible : Should be fsl,chip-esdhc
+- compatible : Should be fsl,chip-esdhc, the supported chips include
+ fsl,imx25-esdhc
+ fsl,imx35-esdhc
+ fsl,imx51-esdhc
+ fsl,imx53-esdhc
+ fsl,imx6q-usdhc
+ fsl,imx6sl-usdhc
+ fsl,imx6sx-usdhc
Optional properties:
- fsl,cd-controller : Indicate to use controller internal card detection
--
1.7.8
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[PATCH v2 1/8] mmc: sdhci-esdhc-imx: remove duplicated lines
There is already the same register check above, no need the later one.
Move them into one place and delete the later one.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 587ee0e..256c901 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -315,6 +315,11 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
data |= ESDHC_CTRL_D3CD;
writel(data, host-ioaddr + SDHCI_HOST_CONTROL);
}
+
+ if (val SDHCI_INT_ADMA_ERROR) {
+ val = ~SDHCI_INT_ADMA_ERROR;
+ val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
+ }
}
if (unlikely((imx_data-socdata-flags ESDHC_FLAG_MULTIBLK_NO_INT)
@@ -335,13 +340,6 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
}
}
- if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
- if (val SDHCI_INT_ADMA_ERROR) {
- val = ~SDHCI_INT_ADMA_ERROR;
- val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
- }
- }
-
writel(val, host-ioaddr + reg);
}
--
1.7.8
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[PATCH v2 2/8] mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt issue
The usdhc does not have missing card interrupt issue, so execute the
workaround conditionally.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 256c901..9594bf8 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -300,7 +300,7 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
u32 data;
if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
- if (val SDHCI_INT_CARD_INT) {
+ if ((val SDHCI_INT_CARD_INT) !esdhc_is_usdhc(imx_data)) {
/*
* Clear and then set D3CD bit to avoid missing the
* card interrupt. This is a eSDHC controller problem
--
1.7.8
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Re: [PATCH 6/7] mmc: sdhci-esdhc-imx: add imx6sx support
On Thu, Sep 18, 2014 at 12:29:52AM +0200, Ulf Hansson wrote:
On 3 September 2014 14:05, Dong Aisheng b29...@freescale.com wrote:
The imx6sx usdhc is derived from imx6sl, the difference is minor.
imx6sx have the errata ESDHC_FLAG_ERR004536 fixed.
So introduce a new compatible string for imx6sx to distinguish them.
Signed-off-by: Dong Aisheng b29...@freescale.com
Hi Dong,
This one has checkpatch errors due to missing DT documentation.
The original binding doc is writing in the format of:
Required properties:
-- compatible : Should be fsl,chip-esdhc
It just provides a rule and does not provide the specific compatible string.
So i did not update the doc before.
But i think it's better to fix it to avoid future warning again.
Can you help add below patch before this commit or do you need me
to resend the patch series again with this patch added?
From 467b84e5ffcba543b9ac88913b1d2dc1159dfa72 Mon Sep 17 00:00:00 2001
From: Dong Aisheng b29...@freescale.com
Date: Thu, 18 Sep 2014 13:11:03 +0800
Subject: [PATCH 6/8] mmc: sdhci-esdhc-imx: using specific compatible string
in binding doc
Using specific compatible string in binding doc to make the binding
more clear.
It's also used to avoid checkpatch warning in the future like follows:
0005-mmc-sdhci-do-not-enable-card-cd-wakeup-for-gpio-case.patch has no obvious
style problems and is ready for submission.
WARNING: DT compatible string fsl,imx6sx-usdhc appears un-documented -- check
./Documentation/devicetree/bindings/
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
total: 0 errors, 1 warnings, 18 lines checked
Signed-off-by: Dong Aisheng b29...@freescale.com
---
.../devicetree/bindings/mmc/fsl-imx-esdhc.txt |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 9046ba06..c415d34 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -7,7 +7,14 @@ This file documents differences between the core properties
described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
Required properties:
-- compatible : Should be fsl,chip-esdhc
+- compatible : Should be fsl,chip-esdhc, the supported chips include
+ fsl,imx25-esdhc
+ fsl,imx35-esdhc
+ fsl,imx51-esdhc
+ fsl,imx53-esdhc
+ fsl,imx6q-usdhc
+ fsl,imx6sl-usdhc
+ fsl,imx6sx-usdhc
Optional properties:
- fsl,cd-controller : Indicate to use controller internal card detection
--
1.7.8
Regards
Dong Aisheng
Kind regards
Uffe
---
drivers/mmc/host/sdhci-esdhc-imx.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index dc0e384..87179c4 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -150,6 +150,11 @@ static struct esdhc_soc_data usdhc_imx6sl_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
+static struct esdhc_soc_data usdhc_imx6sx_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -190,6 +195,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
{ .compatible = fsl,imx35-esdhc, .data = esdhc_imx35_data, },
{ .compatible = fsl,imx51-esdhc, .data = esdhc_imx51_data, },
{ .compatible = fsl,imx53-esdhc, .data = esdhc_imx53_data, },
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data = usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data = usdhc_imx6q_data, },
{ /* sentinel */ }
--
1.7.8
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Re: sdhci-esdhc-imx : cannot read eMMC
On Wed, Sep 3, 2014 at 11:11 PM, Jean-Michel Hautbois
jhautb...@gmail.com wrote:
2014-09-03 10:15 GMT+02:00 Dong Aisheng donga...@gmail.com:
Hi JM,
On Tue, Sep 2, 2014 at 11:10 PM, Jean-Michel Hautbois
jhautb...@gmail.com wrote:
2014-09-02 11:20 GMT+02:00 Jean-Michel Hautbois
jean-michel.hautb...@vodalys.com:
Hi there,
I start a new thread, as I have done lots of test and this will be clearer.
I have problems reading and writing eMMC on my i.MX6 board with 3.17-rc3.
Sometimes I don't have read errors explicitly in dmesg, but fdisk has
no effects.
I activated MMC debug in my config file, and here is an extract of
mmc0 register dump and all mmc1 part.
On Freescale kernel, I confirm it works well with the same board and
sample, I can write a partition on mmc1.
My iMX6Q SabreSD board seems ok.
What board did you use?
What reading/writing problems did you meet?
I did not see errors in your log.
Can you paste the error log?
When CONFIG_MMC_DEBUG=y there is no error.
When CONFIG_MMC_DEBUG=n then, I get :
[2.036958] SW2: Restricting voltage, 330-195uV
[2.036965] mmc1: Switching to 1.8V signalling voltage failed
[2.043714] mmc1: new DDR MMC card at address 0001
[2.044738] mmcblk1: mmc1:0001 SEM02G 1.82 GiB
[2.045007] mmcblk1rpmb: mmc1:0001 SEM02G partition 3 128 KiB
[2.048345] mmcblk1: error -84 transferring data, sector 0, nr 8,
cmd response 0x900, card status 0xb00
It seems you're using Sandisk eMMC chip, right?
We ever got an errata of Sandisk eMMC that it needs certain delay
befor sending cmd13
after cmd6.
We tried 1ms seems ok for such eMMC chip.
You may give a try.
e.g.
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 49f04bc..83d17a9 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -440,6 +440,12 @@ int __mmc_switch(struct mmc_card *card, u8 set,
u8 index, u8 value,
if (!use_busy_signal)
return 0;
+ /*
+* WORKAROUND: for Sandisk eMMC cards, it might need certain delay
+* before sending CMD13 after CMD6
+*/
+ mdelay(1);
+
/* Must check status to be sure of no errors */
timeout = jiffies + msecs_to_jiffies(MMC_OPS_TIMEOUT_MS);
do {
BTW, you should also make sure the signal quality is not bad which may
also cause such issue.
Regards
Dong Aisheng
[2.048352] mmcblk1: retrying using single block read
[2.048858] mmcblk1: error -84 transferring data, sector 0, nr 8,
cmd response 0x900, card status 0x0
[2.048933] end_request: I/O error, dev mmcblk1, sector 0
[2.049449] mmcblk1: error -84 transferring data, sector 1, nr 7,
cmd response 0x900, card status 0x0
[2.049459] end_request: I/O error, dev mmcblk1, sector 1
[2.049969] mmcblk1: error -84 transferring data, sector 2, nr 6,
cmd response 0x900, card status 0x0
[2.049978] end_request: I/O error, dev mmcblk1, sector 2
[2.050484] mmcblk1: error -84 transferring data, sector 3, nr 5,
cmd response 0x900, card status 0x0
[2.050493] end_request: I/O error, dev mmcblk1, sector 3
[2.050998] mmcblk1: error -84 transferring data, sector 4, nr 4,
cmd response 0x900, card status 0x0
[2.051008] end_request: I/O error, dev mmcblk1, sector 4
[2.051512] mmcblk1: error -84 transferring data, sector 5, nr 3,
cmd response 0x900, card status 0x0
[2.051521] end_request: I/O error, dev mmcblk1, sector 5
[2.052028] mmcblk1: error -84 transferring data, sector 6, nr 2,
cmd response 0x900, card status 0x0
[2.052038] end_request: I/O error, dev mmcblk1, sector 6
[2.052542] mmcblk1: error -84 transferring data, sector 7, nr 1,
cmd response 0x900, card status 0x0
[2.052551] end_request: I/O error, dev mmcblk1, sector 7
[2.052620] Buffer I/O error on device mmcblk1, logical block 0
[2.053338] mmcblk1: error -84 transferring data, sector 0, nr 8,
cmd response 0x900, card status 0xb00
[2.053345] mmcblk1: retrying using single block read
[2.053849] mmcblk1: error -84 transferring data, sector 0, nr 8,
cmd response 0x900, card status 0x0
[2.053859] end_request: I/O error, dev mmcblk1, sector 0
[2.054378] mmcblk1: error -84 transferring data, sector 1, nr 7,
cmd response 0x900, card status 0x0
[2.054388] end_request: I/O error, dev mmcblk1, sector 1
[2.054892] mmcblk1: error -84 transferring data, sector 2, nr 6,
cmd response 0x900, card status 0x0
[2.055403] mmcblk1: error -84 transferring data, sector 3, nr 5,
cmd response 0x900, card status 0x0
[2.055917] mmcblk1: error -84 transferring data, sector 4, nr 4,
cmd response 0x900, card status 0x0
[2.056428] mmcblk1: error -84 transferring data, sector 5, nr 3,
cmd response 0x900, card status 0x0
[2.056937] mmcblk1: error -84 transferring data, sector 6, nr 2,
cmd response 0x900, card status 0x0
[2.057446] mmcblk1: error -84 transferring data, sector 7, nr 1,
cmd response 0x900
Re: [PATCH 00/13] mmc: Improve busy detection for MMC_CAP_WAIT_WHILE_BUSY
Hi Ulf, On Thu, Jan 30, 2014 at 6:37 AM, Ulf Hansson ulf.hans...@linaro.org wrote: This patchset improves the handling around busy detection in the mmc core layer while operating on host supporting MMC_CAP_WAIT_WHILE_BUSY. A R1B response is for an mmc command, specified as and R1 but with an optional busy assertion on the DAT0 line. Hosts supporting MMC_CAP_WAIT_WHILE_BUSY, normally has a busy detection mechanism build in it's controller HW. Using such a feature decreases the need for polling of the card's status using CMD13, which is the fallback method used by the mmc core for hosts that don't support MMC_CAP_WAIT_WHILE_BUSY. Typcial commands that expects R1B responses are CMD6 (SWITCH), CMD12 (STOP), CMD38 (ERASE) and CMD5 (SLEEP). This patchset adresses CMD6, CMD5 and improves some parts where CMD12 are used. If the implemented approach becomes accepted, a future patchset for CMD38 can be based on top if this patchset. Do note, the final two patches implements support for busy detection for the mmci host driver, since some of it's HW variants do supports busy detection. Future suggested improvements related to this patchset: (Please, feel free to implement any of them :-) ). a) For CMD38, select a fixed number maximum blocks to accept for erase/discard/trim operations. Compute the needed timeout depending on each card's erase information provided through it's CSD/EXT_CSD registers. Then follow the same principle as for sending a CMD6. b) At least for CMD38, but likely for other commands as well, we could benefit from doing a _periodic_ CMD13 polling to handle the busy completion. This will also be useful for hosts supporting MMC_CAP_WAIT_WHILE_BUSY, in particular for cases where the host are unable to support the needed busy timeout. Do you have the plan to implement above two items? Since currently the max_discard_sectors is still calculated based on max_busy_timeout of host, it is possible that for some eMMC chips, the max_discard_sectors is 1, which then cause the erase operation terribly slow. Regards Dong Aisheng c) Handle timeouts while polling for card's status with CMD13 in cases where a CMD12 has been used to finalize a data DATA_WRITE transfer. Ulf Hansson (13): mmc: core: Rename max_discard_to to max_busy_timeout mmc: core: Rename cmd_timeout_ms to busy_timeout mmc: core: Add ignore_crc flag to __mmc_switch mmc: core: Minor simplifications to __mmc_switch mmc: core: Fixup busy detection for mmc switch operations mmc: core: Use generic CMD6 time while switching to eMMC HS200 mode mmc: core: Respect host's max_busy_timeout when sending sleep cmd mmc: block: Use R1 responses for stop cmds for read requests mmc: block: Implement card_busy_detect() for busy detection mmc: block: Respect hw busy detection in card_busy_detect() mmc: block: Fixup busy detection while invoking stop cmd at recovery mmc: mmci: Handle CMD irq before DATA irq mmc: mmci: Enable support for busy detection for ux500 variant drivers/mmc/card/block.c | 178 drivers/mmc/core/core.c| 11 +-- drivers/mmc/core/mmc.c | 34 ++--- drivers/mmc/core/mmc_ops.c | 64 ++-- drivers/mmc/host/mmci.c| 54 +++--- drivers/mmc/host/mmci.h|2 + drivers/mmc/host/sdhci.c | 10 +-- include/linux/mmc/core.h |4 +- include/linux/mmc/host.h |2 +- 9 files changed, 241 insertions(+), 118 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/13] mmc: Improve busy detection for MMC_CAP_WAIT_WHILE_BUSY
On Wed, Sep 03, 2014 at 09:32:35AM +0200, Ulf Hansson wrote: On 3 September 2014 08:51, Dong Aisheng donga...@gmail.com wrote: Hi Ulf, On Thu, Jan 30, 2014 at 6:37 AM, Ulf Hansson ulf.hans...@linaro.org wrote: This patchset improves the handling around busy detection in the mmc core layer while operating on host supporting MMC_CAP_WAIT_WHILE_BUSY. A R1B response is for an mmc command, specified as and R1 but with an optional busy assertion on the DAT0 line. Hosts supporting MMC_CAP_WAIT_WHILE_BUSY, normally has a busy detection mechanism build in it's controller HW. Using such a feature decreases the need for polling of the card's status using CMD13, which is the fallback method used by the mmc core for hosts that don't support MMC_CAP_WAIT_WHILE_BUSY. Typcial commands that expects R1B responses are CMD6 (SWITCH), CMD12 (STOP), CMD38 (ERASE) and CMD5 (SLEEP). This patchset adresses CMD6, CMD5 and improves some parts where CMD12 are used. If the implemented approach becomes accepted, a future patchset for CMD38 can be based on top if this patchset. Do note, the final two patches implements support for busy detection for the mmci host driver, since some of it's HW variants do supports busy detection. Future suggested improvements related to this patchset: (Please, feel free to implement any of them :-) ). a) For CMD38, select a fixed number maximum blocks to accept for erase/discard/trim operations. Compute the needed timeout depending on each card's erase information provided through it's CSD/EXT_CSD registers. Then follow the same principle as for sending a CMD6. b) At least for CMD38, but likely for other commands as well, we could benefit from doing a _periodic_ CMD13 polling to handle the busy completion. This will also be useful for hosts supporting MMC_CAP_WAIT_WHILE_BUSY, in particular for cases where the host are unable to support the needed busy timeout. Do you have the plan to implement above two items? Yes, it's on top of my TODO list for MMC. I really need to get this done asap. Thanks for pinging me about this. Great! Since currently the max_discard_sectors is still calculated based on max_busy_timeout of host, it is possible that for some eMMC chips, the max_discard_sectors is 1, which then cause the erase operation terribly slow. Yes! Another issue to fix is get MMC_CAP_ERASE removed - and that should be possible once the above described problem has been solved. Yes, seems MMC_CAP_ERASE is not needed anymore. Regards Dong Aisheng Kind regards Uffe -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: sdhci-esdhc-imx : cannot read eMMC
Hi JM, On Tue, Sep 2, 2014 at 11:10 PM, Jean-Michel Hautbois jhautb...@gmail.com wrote: 2014-09-02 11:20 GMT+02:00 Jean-Michel Hautbois jean-michel.hautb...@vodalys.com: Hi there, I start a new thread, as I have done lots of test and this will be clearer. I have problems reading and writing eMMC on my i.MX6 board with 3.17-rc3. Sometimes I don't have read errors explicitly in dmesg, but fdisk has no effects. I activated MMC debug in my config file, and here is an extract of mmc0 register dump and all mmc1 part. On Freescale kernel, I confirm it works well with the same board and sample, I can write a partition on mmc1. My iMX6Q SabreSD board seems ok. What board did you use? What reading/writing problems did you meet? I did not see errors in your log. Can you paste the error log? snip [3.099853] sdhci [sdhci_add_host()]: mmc1: Auto-CMD23 available [ 3.100143] sdhci-esdhc-imx 219c000.usdhc: No vqmmc regulator found I have set my vqmmc-supply in my DT, and it works well now... I don't really know why specifying vqmmc-supply is better, but I can assure it is : I can mount the partition created on the eMMC. The only remaining errors are on boot partitions reading. Maybe should we have a parameter in DT in order to tell if we want to get thse partitions or not, instead of the return value of mmc_boot_partition_access() which is always 1 (if I don't miss something) ? Currently I also can't see why specifying vqmmc-supply is better. You can measure if the voltage is different after using vqmmc-supply. If the error you see is CRC errors(-84), usually you may want to double check the pad setting, board layout, which could affect the signal quality, or capture the waveform of DATA signal and ask HW expert to help analyze whether it's good enough. Regards Dong Aisheng Thanks, JM -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: sdhci-esdhc-imx : cannot read eMMC
On Wed, Sep 3, 2014 at 4:40 PM, Jean-Michel Hautbois jhautb...@gmail.com wrote: 2014-09-03 10:39 GMT+02:00 Dong Aisheng donga...@gmail.com: On Wed, Sep 3, 2014 at 4:25 PM, Jean-Michel Hautbois jhautb...@gmail.com wrote: 2014-09-03 10:15 GMT+02:00 Dong Aisheng donga...@gmail.com: Hi JM, Hi Dong, On Tue, Sep 2, 2014 at 11:10 PM, Jean-Michel Hautbois jhautb...@gmail.com wrote: 2014-09-02 11:20 GMT+02:00 Jean-Michel Hautbois jean-michel.hautb...@vodalys.com: Hi there, I start a new thread, as I have done lots of test and this will be clearer. I have problems reading and writing eMMC on my i.MX6 board with 3.17-rc3. Sometimes I don't have read errors explicitly in dmesg, but fdisk has no effects. I activated MMC debug in my config file, and here is an extract of mmc0 register dump and all mmc1 part. On Freescale kernel, I confirm it works well with the same board and sample, I can write a partition on mmc1. My iMX6Q SabreSD board seems ok. What board did you use? What reading/writing problems did you meet? I did not see errors in your log. Can you paste the error log? This is a custom board. You are right, activating debug seems to make the problem disappear... I have CRC errors and my CMD signal is quite bad when this is happening. I asked an HW engineer to look at this. I also double checked the pads, and added the MX6QDL_PAD_NANDF_ALE__SD4_RESET pad, but the reset signal is always down when doing this, when it should go down then up... The sdhci-esdhc-imx driver does not implement hw_reset support via eMMC reset pin. OK, that is what I thought, let's add it then :) ? Yes, this feature needs to be added. Regards Dong Aisheng JM -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: sdhci-esdhc-imx : cannot read eMMC
On Wed, Sep 3, 2014 at 4:25 PM, Jean-Michel Hautbois jhautb...@gmail.com wrote: 2014-09-03 10:15 GMT+02:00 Dong Aisheng donga...@gmail.com: Hi JM, Hi Dong, On Tue, Sep 2, 2014 at 11:10 PM, Jean-Michel Hautbois jhautb...@gmail.com wrote: 2014-09-02 11:20 GMT+02:00 Jean-Michel Hautbois jean-michel.hautb...@vodalys.com: Hi there, I start a new thread, as I have done lots of test and this will be clearer. I have problems reading and writing eMMC on my i.MX6 board with 3.17-rc3. Sometimes I don't have read errors explicitly in dmesg, but fdisk has no effects. I activated MMC debug in my config file, and here is an extract of mmc0 register dump and all mmc1 part. On Freescale kernel, I confirm it works well with the same board and sample, I can write a partition on mmc1. My iMX6Q SabreSD board seems ok. What board did you use? What reading/writing problems did you meet? I did not see errors in your log. Can you paste the error log? This is a custom board. You are right, activating debug seems to make the problem disappear... I have CRC errors and my CMD signal is quite bad when this is happening. I asked an HW engineer to look at this. I also double checked the pads, and added the MX6QDL_PAD_NANDF_ALE__SD4_RESET pad, but the reset signal is always down when doing this, when it should go down then up... The sdhci-esdhc-imx driver does not implement hw_reset support via eMMC reset pin. Regards Dong Aisheng Thanks, JM -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/7] mmc: sdhci/imx: a few clean up and fixes
A few clean up and fixes. Dong Aisheng (7): mmc: sdhci-esdhc-imx: remove duplicated lines mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt issue mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix mmc: sdhci: do not enable card detect interrupt for gpio cd type mmc: sdhci: do not enable card cd wakeup for gpio case mmc: sdhci-esdhc-imx: add imx6sx support mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdl drivers/mmc/host/sdhci-esdhc-imx.c | 44 --- drivers/mmc/host/sdhci.c |8 +- 2 files changed, 41 insertions(+), 11 deletions(-) -- 1.7.8 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/7] mmc: sdhci: do not enable card cd wakeup for gpio case
Do not need to enable the controller card cd interrupt wakeup
if using GPIO as card detect since it's meaningless.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4d0b7b5..7aa98b9 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2548,13 +2548,16 @@ static irqreturn_t sdhci_thread_irq(int irq, void
*dev_id)
void sdhci_enable_irq_wakeups(struct sdhci_host *host)
{
u8 val;
+ int gpio_cd = mmc_gpio_get_cd(host-mmc);
+
u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
| SDHCI_WAKE_ON_INT;
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
val |= mask ;
/* Avoid fake wake up */
- if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION ||
+ !IS_ERR_VALUE(gpio_cd))
val = ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
}
--
1.7.8
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[PATCH 1/7] mmc: sdhci-esdhc-imx: remove duplicated lines
There is already the same register check above, no need the later one.
Move them into one place and delete the later one.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 587ee0e..256c901 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -315,6 +315,11 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
data |= ESDHC_CTRL_D3CD;
writel(data, host-ioaddr + SDHCI_HOST_CONTROL);
}
+
+ if (val SDHCI_INT_ADMA_ERROR) {
+ val = ~SDHCI_INT_ADMA_ERROR;
+ val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
+ }
}
if (unlikely((imx_data-socdata-flags ESDHC_FLAG_MULTIBLK_NO_INT)
@@ -335,13 +340,6 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
}
}
- if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
- if (val SDHCI_INT_ADMA_ERROR) {
- val = ~SDHCI_INT_ADMA_ERROR;
- val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
- }
- }
-
writel(val, host-ioaddr + reg);
}
--
1.7.8
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[PATCH 4/7] mmc: sdhci: do not enable card detect interrupt for gpio cd type
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE,
we also do not need to handle controller native card detect interrupt
for gpio as card detect case.
If we wrong enabled the card detect interrupt for gpio case,
it will cause a lot of unexpected card detect interrupts during data transfer
which should not happen.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f6a683b..4d0b7b5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -136,9 +136,10 @@ static void sdhci_dumpregs(struct sdhci_host *host)
static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
u32 present;
+ int gpio_cd = mmc_gpio_get_cd(host-mmc);
if ((host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
- (host-mmc-caps MMC_CAP_NONREMOVABLE))
+ (host-mmc-caps MMC_CAP_NONREMOVABLE) || !IS_ERR_VALUE(gpio_cd))
return;
if (enable) {
--
1.7.8
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[PATCH 7/7] mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdl
The iMX6Q/DL can not support HS200 mode while iMX6SL and iMX6SX can,
so introduce a new flag to distinguish them.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 87179c4..16eff00 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -120,6 +120,8 @@
* when reading data from the card
*/
#define ESDHC_FLAG_ERR004536 BIT(7)
+/* The IP supports HS200 mode */
+#define ESDHC_FLAG_HS200 BIT(8)
struct esdhc_soc_data {
u32 flags;
@@ -147,12 +149,13 @@ static struct esdhc_soc_data usdhc_imx6q_data = {
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
+ | ESDHC_FLAG_HS200,
};
static struct esdhc_soc_data usdhc_imx6sx_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
};
struct pltfm_imx_data {
@@ -1063,6 +1066,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
+ if (!(imx_data-socdata-flags ESDHC_FLAG_HS200))
+ host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
+
/*
* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
* TO1.1, it's harmless for MX6SL
--
1.7.8
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[PATCH 2/7] mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt issue
The usdhc does not have missing card interrupt issue, so execute the
workaround conditionally.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 256c901..9594bf8 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -300,7 +300,7 @@ static void esdhc_writel_le(struct sdhci_host *host, u32
val, int reg)
u32 data;
if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
- if (val SDHCI_INT_CARD_INT) {
+ if ((val SDHCI_INT_CARD_INT) !esdhc_is_usdhc(imx_data)) {
/*
* Clear and then set D3CD bit to avoid missing the
* card interrupt. This is a eSDHC controller problem
--
1.7.8
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[PATCH 6/7] mmc: sdhci-esdhc-imx: add imx6sx support
The imx6sx usdhc is derived from imx6sl, the difference is minor.
imx6sx have the errata ESDHC_FLAG_ERR004536 fixed.
So introduce a new compatible string for imx6sx to distinguish them.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index dc0e384..87179c4 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -150,6 +150,11 @@ static struct esdhc_soc_data usdhc_imx6sl_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
+static struct esdhc_soc_data usdhc_imx6sx_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -190,6 +195,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
{ .compatible = fsl,imx35-esdhc, .data = esdhc_imx35_data, },
{ .compatible = fsl,imx51-esdhc, .data = esdhc_imx51_data, },
{ .compatible = fsl,imx53-esdhc, .data = esdhc_imx53_data, },
+ { .compatible = fsl,imx6sx-usdhc, .data = usdhc_imx6sx_data, },
{ .compatible = fsl,imx6sl-usdhc, .data = usdhc_imx6sl_data, },
{ .compatible = fsl,imx6q-usdhc, .data = usdhc_imx6q_data, },
{ /* sentinel */ }
--
1.7.8
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Re: [PATCH 0/7] mmc: sdhci/imx: a few clean up and fixes
On Wed, Sep 03, 2014 at 09:34:28AM -0300, Fabio Estevam wrote: Hi Dong, On Wed, Sep 3, 2014 at 9:04 AM, Dong Aisheng b29...@freescale.com wrote: A few clean up and fixes. Usually it is a good idea to separate cleanup from fixes. Do any of the fixes should go to 3.17-rc or stable? Thanks for reminder. Most are tiny fixes and clean up. If to be strictly, Patch 3 mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix could go to stable although the issue is very very hard to reproduce as stated in errata. Regards Dong Aisheng Regards, Fabio Estevam -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix
The uSDHC has an ADMA Length Mismatch errata ERR004536 which may
cause ADMA work abnormally. The errata has already been fixed for
i.MX6Q TO1.2 and i.MX6DL TO1.1 by enable the bit 7 in 0x6c register.
Unfortunately this fix is not included in i.MX6SL.
So we disable ADMA for i.MX6SL and use SDMA instead.
Signed-off-by: Dong Aisheng b29...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 18 +-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 9594bf8..dc0e384 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -114,6 +114,12 @@
#define ESDHC_FLAG_STD_TUNING BIT(5)
/* The IP has SDHCI_CAPABILITIES_1 register */
#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
+/*
+ * The IP has errata ERR004536
+ * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
+ * when reading data from the card
+ */
+#define ESDHC_FLAG_ERR004536 BIT(7)
struct esdhc_soc_data {
u32 flags;
@@ -141,7 +147,7 @@ static struct esdhc_soc_data usdhc_imx6q_data = {
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1,
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
};
struct pltfm_imx_data {
@@ -1050,6 +1056,13 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host-mmc-caps |= MMC_CAP_1_8V_DDR;
+
+ /*
+* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
+* TO1.1, it's harmless for MX6SL
+*/
+ writel(readl(host-ioaddr + 0x6c) | BIT(7),
+ host-ioaddr + 0x6c);
}
if (imx_data-socdata-flags ESDHC_FLAG_MAN_TUNING)
@@ -1061,6 +1074,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
host-ioaddr + ESDHC_TUNING_CTRL);
+ if (imx_data-socdata-flags ESDHC_FLAG_ERR004536)
+ host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
boarddata = imx_data-boarddata;
if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) 0) {
if (!host-mmc-parent-platform_data) {
--
1.7.8
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