RE: [PATCH 2/5] omap2plus: prm: Trvial build break fix for undefined reference to 'omap2_prm_read_mod_reg'
-Original Message- From: Kevin Hilman [mailto:khil...@ti.com] Sent: Wednesday, January 05, 2011 6:02 AM To: Santosh Shilimkar Cc: Paul Walmsley; linux-omap@vger.kernel.org; t...@atomide.com; linux-arm-ker...@lists.infradead.org Subject: Re: [PATCH 2/5] omap2plus: prm: Trvial build break fix for undefined reference to 'omap2_prm_read_mod_reg' Santosh Shilimkar santosh.shilim...@ti.com writes: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, January 05, 2011 12:11 AM To: Santosh Shilimkar Cc: linux-omap@vger.kernel.org; khil...@ti.com; t...@atomide.com; linux-arm-ker...@lists.infradead.org Subject: Re: [PATCH 2/5] omap2plus: prm: Trvial build break fix for undefined reference to 'omap2_prm_read_mod_reg' Hi Santosh, On Tue, 4 Jan 2011, Santosh Shilimkar wrote: omap2plus_defocnfig build breaks when customised with only ARCH_OMAP4 selected. This is because common files make references to the functions which are defined only for omap2xxx and omap3xxx. LD .tmp_vmlinux1 arch/arm/mach-omap2/built-in.o: In function `pm_dbg_regset_store': arch/arm/mach-omap2/pm-debug.c:335: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/built-in.o: In function `omap2_pm_dump': arch/arm/mach-omap2/pm-debug.c:121: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/pm-debug.c:123: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/pm-debug.c:124: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/pm-debug.c:125: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/built-in.o: In function `omap_prcm_arch_reset': arch/arm/mach-omap2/prcm.c:106: undefined reference to `omap2_prm_set_mod_reg_bits' arch/arm/mach-omap2/prcm.c:108: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/built-in.o: In function `omap_prcm_get_reset_sources': arch/arm/mach-omap2/prcm.c:53: undefined reference to `omap2_prm_read_mod_reg' arch/arm/mach-omap2/built-in.o: In function `clkdm_clear_all_wkdeps': arch/arm/mach-omap2/clockdomain.c:545: undefined reference to `omap2_prm_clear_mod_reg_bits' arch/arm/mach-omap2/built-in.o: In function `clkdm_del_wkdep': arch/arm/mach-omap2/clockdomain.c:475: undefined reference to `omap2_prm_clear_mod_reg_bits' arch/arm/mach-omap2/built-in.o: In function `clkdm_read_wkdep': arch/arm/mach-omap2/clockdomain.c:511: undefined reference to `omap2_prm_read_mod_bits_shift' arch/arm/mach-omap2/built-in.o: In function `clkdm_add_wkdep': arch/arm/mach-omap2/clockdomain.c:440: undefined reference to `omap2_prm_set_mod_reg_bits' make: *** [.tmp_vmlinux1] Error 1 This patch adds stubs for these functions so that build continues to work. Probably alternately the build can be fixed as below but that not seems to be the right way. Since these functions now return 0, maybe it would be better to call WARN() or BUG() in these functions for OMAP4. Otherwise, they are going to silently do the wrong thing, and someone needs to fix any usage of these functions where they shouldn't be used. e.g., in mach- omap2/prcm.c or mach-omap2/pm-debug.c ... Good point. Will update the patch accordingly and repost. Please use WARN() instead of BUG() as this is not worthy of causing a panic() for the whole kernel. Yes. I plan to use WARN_ONCE() Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] OMAP: DMA: clear interrupt status correctly
From fffa19df17d73c1ed2e8c65c0b6604ee1dddff84 Mon Sep 17 00:00:00 2001
From: Adrian Hunter adrian.hun...@nokia.com
Date: Wed, 24 Nov 2010 13:23:21 +0200
Subject: [PATCH] OMAP: DMA: clear interrupt status correctly
When clearing the DMA channel, clear all status bits.
When handling a DMA interrupt, clear only the interrupt
status bits that have been read and are passed to the
channel's interrupt handler, not every status bit.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/dma.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c4b2b47..8536308 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -53,7 +53,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
#define OMAP_DMA_ACTIVE 0x01
-#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
+#define OMAP2_DMA_CSR_CLEAR_MASK 0x
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@@ -1873,7 +1873,7 @@ static int omap2_dma_handle_ch(int ch)
printk(KERN_INFO DMA misaligned error with device %d\n,
dma_chan[ch].dev_id);
- p-dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
+ p-dma_write(status, CSR, ch);
p-dma_write(1 ch, IRQSTATUS_L0, ch);
/* read back the register to flush the write */
p-dma_read(IRQSTATUS_L0, ch);
@@ -1893,10 +1893,9 @@ static int omap2_dma_handle_ch(int ch)
OMAP_DMA_CHAIN_INCQHEAD(chain_id);
status = p-dma_read(CSR, ch);
+ p-dma_write(status, CSR, ch);
}
- p-dma_write(status, CSR, ch);
-
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
--
1.7.0.4
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Re: [PATCH] staging: tidspbridge - configure full L1 MMU range
On Wed, Jan 5, 2011 at 8:20 AM, Fernando Guzman Lugo fernando.l...@ti.com wrote: Otherwise a virtual address beyond of the L1 size is used, the MMU hardware will look into a memory that does not belong to L1 translation tables. IOW; the MMU would allow to access any memory, configured or not. Reported-by: Felipe Contreras felipe.contre...@nokia.com Signed-off-by: Fernando Guzman Lugo fernando.l...@ti.com Signed-off-by: Felipe Contreras felipe.contre...@nokia.com People rarely use ' - ' in the commit summary: % git log --oneline -1000 | grep -e ' - ' | wc -l 32 Which means about only 3%. If you do the same on drivers/staging/tidspbridge, you'll see that the only commits that have that are from you. staging: tidspbridge: configure full L1 MMU range Other than that, I think this is is a critical bugfix, and should be applied ASAP. Cheers. -- Felipe Contreras -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] perf: add calls to suspend trace point
On Wed, Jan 5, 2011 at 12:01 AM, Rafael J. Wysocki r...@sisk.pl wrote:
On Tuesday, January 04, 2011, Jean Pihet wrote:
Hi,
On Tue, Jan 4, 2011 at 12:29 PM, Pavel Machek pa...@ucw.cz wrote:
Hi!
Uses the machine_suspend trace point, called from the
generic kernel suspend_enter function.
Signed-off-by: Jean Pihet j-pi...@ti.com
CC: Thomas Renninger tr...@suse.de
---
kernel/power/suspend.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index ecf7705..0650596 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -22,6 +22,7 @@
#include linux/mm.h
#include linux/slab.h
#include linux/suspend.h
+#include trace/events/power.h
#include power.h
@@ -164,7 +165,9 @@ static int suspend_enter(suspend_state_t state)
error = sysdev_suspend(PMSG_SUSPEND);
if (!error) {
if (!suspend_test(TEST_CORE) pm_check_wakeup_events()) {
+ trace_machine_suspend(state);
error = suspend_ops-enter(state);
+ trace_machine_suspend(PWR_EVENT_EXIT);
events_check_enabled = false;
}
sysdev_resume();
Ok... why this place?
This trace has been placed here because it traces the machine low
level mode enter.
I mean, perhaps suspend time should include
device suspend?
That makes sense. We have a few options here:
1) keep the traces as proposed to trace the low level machine code only,
2) move the traces to the entry and exit of suspend_enter so that it
includes the prepare and late_prepare (+ the associated wake-up)
callbacks as well,
3) move the traces to suspend_devices_and_enter so that it includes 2)
and the handling of the console and the devices,
4) move the traces to enter_state do that it includes 3), the call to
sys_sync and the user space freeze.
Note that the the SNAPSHOT_2RAM ioctl code also calls
suspend_devices_and_enter, so if only 4) is used no trace will be
generated in that case.
I am in favor of 3) of 4).
What do you think?
Why don't we keep the tracepoints as proposed _and_ add two additional
tracepoints around device suspend-resume?
I like the idea but that requires to extend the current API with
additional suspend tracepoints or device state change tracepoints.
That can be done once the current API is firmly in place.
Today the only trace API for suspend is machine_suspend(unsigned int
state), so I think the best option is 3) here above.
Unless there is an objection I am pushing 3) asap.
Thanks!
Jean
Rafael
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Re: [PATCH 1/3] perf: add calls to suspend trace point
On Wednesday, January 05, 2011, Jean Pihet wrote:
On Wed, Jan 5, 2011 at 12:01 AM, Rafael J. Wysocki r...@sisk.pl wrote:
On Tuesday, January 04, 2011, Jean Pihet wrote:
Hi,
On Tue, Jan 4, 2011 at 12:29 PM, Pavel Machek pa...@ucw.cz wrote:
Hi!
Uses the machine_suspend trace point, called from the
generic kernel suspend_enter function.
Signed-off-by: Jean Pihet j-pi...@ti.com
CC: Thomas Renninger tr...@suse.de
---
kernel/power/suspend.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index ecf7705..0650596 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -22,6 +22,7 @@
#include linux/mm.h
#include linux/slab.h
#include linux/suspend.h
+#include trace/events/power.h
#include power.h
@@ -164,7 +165,9 @@ static int suspend_enter(suspend_state_t state)
error = sysdev_suspend(PMSG_SUSPEND);
if (!error) {
if (!suspend_test(TEST_CORE) pm_check_wakeup_events())
{
+ trace_machine_suspend(state);
error = suspend_ops-enter(state);
+ trace_machine_suspend(PWR_EVENT_EXIT);
events_check_enabled = false;
}
sysdev_resume();
Ok... why this place?
This trace has been placed here because it traces the machine low
level mode enter.
I mean, perhaps suspend time should include
device suspend?
That makes sense. We have a few options here:
1) keep the traces as proposed to trace the low level machine code only,
2) move the traces to the entry and exit of suspend_enter so that it
includes the prepare and late_prepare (+ the associated wake-up)
callbacks as well,
3) move the traces to suspend_devices_and_enter so that it includes 2)
and the handling of the console and the devices,
4) move the traces to enter_state do that it includes 3), the call to
sys_sync and the user space freeze.
Note that the the SNAPSHOT_2RAM ioctl code also calls
suspend_devices_and_enter, so if only 4) is used no trace will be
generated in that case.
I am in favor of 3) of 4).
What do you think?
Why don't we keep the tracepoints as proposed _and_ add two additional
tracepoints around device suspend-resume?
I like the idea but that requires to extend the current API with
additional suspend tracepoints or device state change tracepoints.
That can be done once the current API is firmly in place.
Today the only trace API for suspend is machine_suspend(unsigned int
state), so I think the best option is 3) here above.
Unless there is an objection I am pushing 3) asap.
Fine by me.
Thanks,
Rafael
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Re: [PATCH] OMAP: GPIO: fix _set_gpio_triggering() for OMAP2+
Kevin, On Wed, Jan 5, 2011 at 04:47, Tony Lindgren t...@atomide.com wrote: * Kevin Hilman khil...@ti.com [110104 14:45]: On Tue, 2011-01-04 at 09:52 -0800, Kevin Hilman wrote: Mika Westerberg ext-mika.1.westerb...@nokia.com writes: In case on OMAP2+ we call set_24xx_gpio_triggering() instead of updating reg and l values. However, at the end of the function we perform a write: __raw_writel(l, reg); So on OMAP2+ we end up writing 0 to the bank-base which is not correct (typically this points to GPIO_REVISION register). Fix this by returning immediately after call to set_24xx_gpio_triggering(). Signed-off-by: Mika Westerberg ext-mika.1.westerb...@nokia.com Acked-by: Kevin Hilman khil...@ti.com Tony, this should be added to omap-for-linus as it fixes a problem in the recently merged GPIO omap_device/hwmod conversion. One clarification - This problem should be existing since the following commit 92105bb70634abacc08bbe12bf6f888fbd7dad38 which was introduced on Sep 7, 2005 FYI, this part of the code remained untouched during GPIO omap_device/hwmod conversion. -V Charulatha On second thought, it's a bit late for the main 2.6.38 window, so will queue this in my pm-fixes branch for the .38-rc cycle. Yeah let's not mess with omap-for-linus right now, but instead start queueing up fixes for -rc1. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex
-Original Message-
From: Menon, Nishanth
Sent: Monday, January 03, 2011 9:22 PM
To: Gopinath, Thara
Cc: linux-omap@vger.kernel.org; khil...@deeprootsystems.com;
p...@pwsan.com; Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand
Subject: Re: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex
Thara Gopinath had written, on 12/31/2010 02:07 AM, the following:
The smartreflex bit on twl4030 needs to be enabled by default
irrespective
of whether smartreflex module is enabled on the OMAP side or not.
This is because without this bit enabled the voltage scaling through
vp forceupdate does not function properly on OMAP3.
s/does not function properly/ does not function ;)
SR I2C is used for forceupdate/vc bypass modes - so neither will
function without switching t2 mode.
T2 voltages could be set in quiet a few methods:
a) Synchronized Scaling Hardware Strategy (ENABLE_VMODE = 1) (for OMAP2
and I had worked on one OMAP3430 product which used this as well) using
VDD1_VFLOOR and VDD1_VROOF
b) Direct Strategy Software Scaling Mode (ENABLE_VMODE = 0) (Smart
reflex disabled) - VDD1_VSEL
c) using smart reflex - as done below - allows OMAP with smart reflex
hardware wired to the twl to use that functionality.
Blindly setting it to smartreflex mode is not correct IMHO. It might
work on SDP and few TI and non-TI platforms, but not all.
Yes you are right. The SR I2C needs to be enabled for vp force update
and vc bypass method of voltage scaling as well as for smartreflex
feature. Are you telling that there are platforms out there using OMAP3
and T2 and still using VMODE or VSEL. As far as I am aware our h/w folks
themselves do not recommend these methods.
Regards
Thara
Signed-off-by: Thara Gopinath th...@ti.com
---
This patch is against LO master and has been
tested on OMAP3430 SDP and OMAP2430 SDP.
arch/arm/mach-omap2/omap_twl.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-
omap2/omap_twl.c
index 15f8c6c..a59f36b 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -58,7 +58,9 @@
static bool is_offset_valid;
static u8 smps_offset;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -256,6 +258,7 @@ int __init omap4_twl_init(void)
int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
+ u8 temp;
if (!cpu_is_omap34xx())
return -ENODEV;
@@ -267,6 +270,19 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 needs to be enabled by
+* default irrespective of whether smartreflex module is
+* enabled on the OMAP side or not. This is because without
+* this bit enabled the voltage scaling through
+* vp forceupdate does not function properly on OMAP3.
+*/
+ twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ temp |= SMARTREFLEX_ENABLE;
+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
--
Regards,
Nishanth Menon
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Re: [PATCH v3 06/17] OMAP2,3 DSS2 Move DSS driver register from board file to devices.c
Hi, On Mon, 2011-01-03 at 18:20 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com omap_display_init function is introduced in devices.c to do the DSS driver registration. So replace platform_device_register or platform_add_devices of DSS with omap_display_init(). This and two previous patches are missing a color in the subject. I'm also ok with Kevin's suggestion to put display code in separate file. There's other stuff to add there also at some point, like changing pinmuxing. Also, I think it would be cleaner to first add the new code to devices.c (or display.c) and display.h in one patch, then in another patch change the board files to use this new display init. Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex
-Original Message-
From: Hilman, Kevin
Sent: Wednesday, January 05, 2011 4:18 AM
To: Gopinath, Thara
Cc: linux-omap@vger.kernel.org; p...@pwsan.com; Cousson, Benoit; Sripathy,
Vishwanath; Sawant, Anand; Menon, Nishanth
Subject: Re: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex
Thara Gopinath th...@ti.com writes:
The smartreflex bit on twl4030 needs to be enabled by default
irrespective
of whether smartreflex module is enabled on the OMAP side or not.
This is because without this bit enabled the voltage scaling through
vp forceupdate does not function properly on OMAP3.
Based on Nishanth's comments, the abofe statements need a little more
justification.
What is probably needed is some default setting (possibly this one) but
with the possibility of board code to disable this if needed.
Yes. If we need to support the other means of voltage scaling, we definitely
need to override this bit from board files. I am not so convinced that we need
to support them though. IMHO, this patch can still go in with change in the
comment and if needed, there can be another patch with an API in omap_twl.c
allowing overriding/ enabling-disabling of sr - i2c bit on
the T2 side.
Regards
Thara
Kevin
Signed-off-by: Thara Gopinath th...@ti.com
---
This patch is against LO master and has been
tested on OMAP3430 SDP and OMAP2430 SDP.
arch/arm/mach-omap2/omap_twl.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-
omap2/omap_twl.c
index 15f8c6c..a59f36b 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -58,7 +58,9 @@
static bool is_offset_valid;
static u8 smps_offset;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -256,6 +258,7 @@ int __init omap4_twl_init(void)
int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
+ u8 temp;
if (!cpu_is_omap34xx())
return -ENODEV;
@@ -267,6 +270,19 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 needs to be enabled by
+* default irrespective of whether smartreflex module is
+* enabled on the OMAP side or not. This is because without
+* this bit enabled the voltage scaling through
+* vp forceupdate does not function properly on OMAP3.
+*/
+ twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ temp |= SMARTREFLEX_ENABLE;
+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
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Re: [PATCH v3 06/17] OMAP2,3 DSS2 Move DSS driver register from board file to devices.c
Hi Tomi, On Wed, Jan 5, 2011 at 4:21 PM, Tomi Valkeinen tomi.valkei...@nokia.com wrote: Hi, On Mon, 2011-01-03 at 18:20 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com omap_display_init function is introduced in devices.c to do the DSS driver registration. So replace platform_device_register or platform_add_devices of DSS with omap_display_init(). This and two previous patches are missing a color in the subject. I'm also ok with Kevin's suggestion to put display code in separate file. There's other stuff to add there also at some point, like changing pinmuxing. Also, I think it would be cleaner to first add the new code to devices.c (or display.c) and display.h in one patch, then in another patch change the board files to use this new display init. Since Senthil is going to be out for some time, I am in the process of updating this patch-set based on Kevin's, Tony's and your comment. I should be able to give you the updated set pretty soon. Best regards, ~Sumit. Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] perf: add OMAP support for the new power events
On Tue, Jan 4, 2011 at 7:03 PM, Nishanth Menon n...@ti.com wrote: jean.pi...@newoldbits.com had written, on 01/04/2011 04:17 AM, the following: [..] diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0ec8a04..0ee0b0e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -29,6 +29,7 @@ #include linux/delay.h #include linux/slab.h #include linux/console.h +#include trace/events/power.h #include plat/sram.h #include plat/clockdomain.h @@ -506,8 +507,14 @@ static void omap3_pm_idle(void) if (omap_irq_pending() || need_resched()) goto out; + trace_power_start(POWER_CSTATE, 1, smp_processor_id()); + trace_cpu_idle(1, smp_processor_id()); + omap_sram_idle(); + trace_power_end(smp_processor_id()); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); Dumb question: it just tells me which C state was attempted - not if actually succeeded in hitting it rt? Does'nt this give us a false data? Yes this tracks the idle requests only. The actual hit state might be different depending on various factors: HW state, enabled clocks, power domains dependencies etc. Debugging the actual PM hit state requires other tools, which could use the trace API. There is definitely more to come on that topic. [..] diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index fc62fb5..7cbb09b 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c (from an offline discussion on a related topic): Would it also be nice to hook on mach-omap2/clock.c points as well to hook on indirect changes? [..] -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/5] omap2plus: voltage: Trivial linking fix 'undefined reference'
LD init/built-in.o
LD .tmp_vmlinux1
arch/arm/mach-omap2/built-in.o: In function `omap2_set_init_voltage':
arch/arm/mach-omap2/pm.c:181: undefined reference to
`omap_voltage_domain_lookup'
arch/arm/mach-omap2/built-in.o: In function `omap4_twl_init':
arch/arm/mach-omap2/omap_twl.c:244: undefined reference to
`omap_voltage_domain_lookup'
arch/arm/mach-omap2/omap_twl.c:247: undefined reference to
`omap_voltage_domain_lookup'
arch/arm/mach-omap2/omap_twl.c:250: undefined reference to
`omap_voltage_domain_lookup'
make: *** [.tmp_vmlinux1] Error 1
The error is reported when omap2plus_defconfig built with CONFIG_PM disabled
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Thara Gopinath th...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Nishanth Menon n...@ti.com
---
arch/arm/plat-omap/include/plat/voltage.h | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/voltage.h
b/arch/arm/plat-omap/include/plat/voltage.h
index 9943c66..4b02227 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -65,9 +65,6 @@ struct voltagedomain {
char *name;
};
-/* API to get the voltagedomain pointer */
-struct voltagedomain *omap_voltage_domain_lookup(char *name);
-
/**
* struct omap_volt_data - Omap voltage specific data.
* @voltage_nominal: The possible voltage value in uV
@@ -131,6 +128,9 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_volt_pmic_info *pmic_info);
void omap_change_voltscale_method(struct voltagedomain *voltdm,
int voltscale_method);
+/* API to get the voltagedomain pointer */
+struct voltagedomain *omap_voltage_domain_lookup(char *name);
+
int omap_voltage_late_init(void);
#else
static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
@@ -144,6 +144,10 @@ static inline int omap_voltage_late_init(void)
{
return -EINVAL;
}
+static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
+{
+ return ERR_PTR(-EINVAL);
+}
#endif
#endif
--
1.6.0.4
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[PATCH v2 2/5] omap2plus: prm: Trvial build break fix for undefined reference to 'omap2_prm_read_mod_reg'
omap2plus_defocnfig build breaks when customised with only ARCH_OMAP4
selected. This is because common files make references to the functions
which are defined only for omap2xxx and omap3xxx.
LD .tmp_vmlinux1
arch/arm/mach-omap2/built-in.o: In function `pm_dbg_regset_store':
arch/arm/mach-omap2/pm-debug.c:335: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `omap2_pm_dump':
arch/arm/mach-omap2/pm-debug.c:121: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/pm-debug.c:123: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/pm-debug.c:124: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/pm-debug.c:125: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `omap_prcm_arch_reset':
arch/arm/mach-omap2/prcm.c:106: undefined reference to
`omap2_prm_set_mod_reg_bits'
arch/arm/mach-omap2/prcm.c:108: undefined reference to `omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `omap_prcm_get_reset_sources':
arch/arm/mach-omap2/prcm.c:53: undefined reference to `omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `clkdm_clear_all_wkdeps':
arch/arm/mach-omap2/clockdomain.c:545: undefined reference to
`omap2_prm_clear_mod_reg_bits'
arch/arm/mach-omap2/built-in.o: In function `clkdm_del_wkdep':
arch/arm/mach-omap2/clockdomain.c:475: undefined reference to
`omap2_prm_clear_mod_reg_bits'
arch/arm/mach-omap2/built-in.o: In function `clkdm_read_wkdep':
arch/arm/mach-omap2/clockdomain.c:511: undefined reference to
`omap2_prm_read_mod_bits_shift'
arch/arm/mach-omap2/built-in.o: In function `clkdm_add_wkdep':
arch/arm/mach-omap2/clockdomain.c:440: undefined reference to
`omap2_prm_set_mod_reg_bits'
make: *** [.tmp_vmlinux1] Error 1
This patch adds stubs for these functions so that build continues to work.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/prm2xxx_3xxx.h | 63 +++-
1 files changed, 62 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h
b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 53d44f6..843f329 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -228,7 +228,67 @@
#ifndef __ASSEMBLER__
-
+/*
+ * Stub omap2xxx/omap3xxx functions so that common files
+ * continue to build when custom builds are used
+ */
+#if defined(CONFIG_ARCH_OMAP4) !(defined(CONFIG_ARCH_OMAP2) || \
+ defined(CONFIG_ARCH_OMAP3))
+static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+}
+static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
+ s16 module, s16 idx)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
+{
+ WARN_ONCE(1, prm: omap2xxx/omap3xxx specific function and
+ not suppose to be used on omap4\n);
+ return 0;
+}
+#else
/* Power/reset management domain register get/set */
extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
@@ -242,6 +302,7 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8
shift);
extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
[PATCH v2 5/5] omap2plus: voltage: Trivial linking fix for 'EINVAL' undeclared
CC arch/arm/mach-omap2/omap_hwmod_common_data.o In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38, from arch/arm/mach-omap2/omap_hwmod_common_data.c:20: arch/arm/plat-omap/include/plat/voltage.h: In function 'omap_voltage_late_init': arch/arm/plat-omap/include/plat/voltage.h:145: error: 'EINVAL' undeclared (first use in this function) arch/arm/plat-omap/include/plat/voltage.h:145: error: (Each undeclared identifier is reported only once arch/arm/plat-omap/include/plat/voltage.h:145: error: for each function it appears in.) make[1]: *** [arch/arm/mach-omap2/omap_hwmod_common_data.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 The error is reported when omap2plus_defconfig built with CONFIG_PM disabled Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com Cc: Thara Gopinath th...@ti.com Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Nishanth Menon n...@ti.com --- arch/arm/plat-omap/include/plat/voltage.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h index 4b02227..5bd204e 100644 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ b/arch/arm/plat-omap/include/plat/voltage.h @@ -14,6 +14,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H #define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H +#include linux/err.h + #define VOLTSCALE_VPFORCEUPDATE1 #define VOLTSCALE_VCBYPASS 2 -- 1.6.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/5] omap2plus: clockdomain: Trivial fix for build break because of clktrctrl_mask
struct clockdomain member clktrctrl_mask is available for only for OMAP2
and OMAP3 architectures. Technially it is also used only for these archs
but this breaks the build with custom OMAP4 configuration.
CC arch/arm/mach-omap2/clockdomain.o
arch/arm/mach-omap2/clockdomain.c: In function '_enable_hwsup':
arch/arm/mach-omap2/clockdomain.c:251: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c:254: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c: In function '_disable_hwsup':
arch/arm/mach-omap2/clockdomain.c:277: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c:280: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c: In function 'omap2_clkdm_sleep':
arch/arm/mach-omap2/clockdomain.c:744: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c: In function 'omap2_clkdm_wakeup':
arch/arm/mach-omap2/clockdomain.c:789: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c: In function 'omap2_clkdm_clk_enable':
arch/arm/mach-omap2/clockdomain.c:922: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c:926: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c: In function 'omap2_clkdm_clk_disable':
arch/arm/mach-omap2/clockdomain.c:994: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
arch/arm/mach-omap2/clockdomain.c:998: error: 'struct clockdomain' has no
member named 'clktrctrl_mask'
make[1]: *** [arch/arm/mach-omap2/clockdomain.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2
Fix the build break by dropping the #ifdef as suggested by Paul Walmsley
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/clockdomain.h |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.h
b/arch/arm/mach-omap2/clockdomain.h
index de3faa2..9b459c2 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -103,9 +103,7 @@ struct clockdomain {
const char *name;
struct powerdomain *ptr;
} pwrdm;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
const u16 clktrctrl_mask;
-#endif
const u8 flags;
const u8 dep_bit;
const u8 prcm_partition;
--
1.6.0.4
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[PATCH v2 3/5] omap2plus: voltage: Trivial warning fix 'no return statement'
Fix below build warnings
CC arch/arm/mach-omap2/common.o
CC arch/arm/mach-omap2/gpio.o
In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38,
from arch/arm/mach-omap2/gpio.c:25:
arch/arm/plat-omap/include/plat/voltage.h: In function
'omap_voltage_register_pmic':
arch/arm/plat-omap/include/plat/voltage.h:137: warning: no return statement in
function returning non-void
CC arch/arm/mach-omap2/dma.o
In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38,
from arch/arm/mach-omap2/dma.c:32:
arch/arm/plat-omap/include/plat/voltage.h: In function
'omap_voltage_register_pmic':
arch/arm/plat-omap/include/plat/voltage.h:137: warning: no return statement in
function returning non-void
CC arch/arm/mach-omap2/wd_timer.o
In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38,
from arch/arm/mach-omap2/wd_timer.c:15:
arch/arm/plat-omap/include/plat/voltage.h: In function
'omap_voltage_register_pmic':
arch/arm/plat-omap/include/plat/voltage.h:137: warning: no return statement in
function returning non-void
CC arch/arm/mach-omap2/prm44xx.o
CC arch/arm/mach-omap2/omap_hwmod.o
In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38,
from arch/arm/mach-omap2/omap_hwmod.c:145:
arch/arm/plat-omap/include/plat/voltage.h: In function
'omap_voltage_register_pmic':
arch/arm/plat-omap/include/plat/voltage.h:137: warning: no return statement in
function returning non-void
CC arch/arm/mach-omap2/omap_hwmod_common_data.o
In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38,
from arch/arm/mach-omap2/omap_hwmod_common_data.c:20:
arch/arm/plat-omap/include/plat/voltage.h: In function
'omap_voltage_register_pmic':
arch/arm/plat-omap/include/plat/voltage.h:137: warning: no return statement in
function returning non-void
The error is reported when omap2plus_defconfig built with CONFIG_PM disabled
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Thara Gopinath th...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Nishanth Menon n...@ti.com
---
arch/arm/plat-omap/include/plat/voltage.h |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/voltage.h
b/arch/arm/plat-omap/include/plat/voltage.h
index 0ff1233..9943c66 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -134,7 +134,10 @@ void omap_change_voltscale_method(struct voltagedomain
*voltdm,
int omap_voltage_late_init(void);
#else
static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
- struct omap_volt_pmic_info *pmic_info) {}
+ struct omap_volt_pmic_info *pmic_info)
+{
+ return -EINVAL;
+}
static inline void omap_change_voltscale_method(struct voltagedomain *voltdm,
int voltscale_method) {}
static inline int omap_voltage_late_init(void)
--
1.6.0.4
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RE: [PATCH 0/5] omap2plus: Trivial build break fixes
-Original Message- From: Kevin Hilman [mailto:khil...@ti.com] Sent: Wednesday, January 05, 2011 6:08 AM To: Santosh Shilimkar Cc: linux-omap@vger.kernel.org; t...@atomide.com; linux-arm- ker...@lists.infradead.org Subject: Re: [PATCH 0/5] omap2plus: Trivial build break fixes Santosh Shilimkar santosh.shilim...@ti.com writes: These are trivial build fixes which I found while doing some testing 'omap-for-linus' branch. The series is generated against the linux-omap 'omap-for-linus' branch and boot tested on OMAP4430 SDP and OMAP3630 ZOOM. Minor nit in your git-send-email config. Can you add the following to your ~/.gitconfig, or update to newer git where this is now the default: [sendemail] chainreplyto = false This will make all patches a reply to PATCH 0 instead of to the previous patch. Have tried this in v2 I posted but it didn't appear to be a reply for PATCH 0. May be I missed something. Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] perf: add OMAP support for the new power events
Hi Paul,
On Tue, Jan 4, 2011 at 7:48 PM, Paul Walmsley p...@pwsan.com wrote:
Hello Jean,
On Tue, 4 Jan 2011, jean.pi...@newoldbits.com wrote:
From: Jean Pihet j-pi...@ti.com
The patch adds the new power management trace points for
the OMAP architecture.
The trace points are for:
- default idle handler. Since the cpuidle framework is
instrumented in the generic way there is no need to
add trace points in the OMAP specific cpuidle handler;
- cpufreq (DVFS),
- clocks changes (enable, disable, set_rate),
A question about these. Are these only meant to track calls to these
functions from outside the clock code? Or meant to track actual hardware
clock changes?
The former: this is used to track the clock requests from outside the
clock framework.
If the latter, then it might make sense to put these
trace points into the functions that actually change the hardware
registers, e.g., omap2_dflt_clk_{enable,disable}(), etc., since a
clk_enable() on a leaf clock may result in many internal system clocks
being enabled up the clock tree.
I agree with you it is better to track the actual clock changes instead.
I propose to move the tracepoints to omap2_clk_{enable...} which
enables all the clocks irrespectively of the installed handler.
Note about the clock handlers: omap2_dflt_clk_enable happens to be the
handler for all controllable clocks but could that change in the
future?
- Paul
Thanks,
Jean
- change of power domains next power states.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 7 +++
arch/arm/mach-omap2/powerdomain.c | 3 +++
arch/arm/plat-omap/clock.c | 13 ++---
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0ec8a04..0ee0b0e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
#include linux/delay.h
#include linux/slab.h
#include linux/console.h
+#include trace/events/power.h
#include plat/sram.h
#include plat/clockdomain.h
@@ -506,8 +507,14 @@ static void omap3_pm_idle(void)
if (omap_irq_pending() || need_resched())
goto out;
+ trace_power_start(POWER_CSTATE, 1, smp_processor_id());
+ trace_cpu_idle(1, smp_processor_id());
+
omap_sram_idle();
+ trace_power_end(smp_processor_id());
+ trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+
out:
local_fiq_enable();
local_irq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 6527ec3..73cbe9a 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -23,6 +23,7 @@
#include linux/errno.h
#include linux/err.h
#include linux/io.h
+#include trace/events/power.h
#include asm/atomic.h
@@ -440,6 +441,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8
pwrst)
pr_debug(powerdomain: setting next powerstate for %s to %0x\n,
pwrdm-name, pwrst);
+ trace_power_domain_target(pwrdm-name, pwrst, smp_processor_id());
+
prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst OMAP_POWERSTATE_SHIFT),
pwrdm-prcm_offs, pwrstctrl_reg_offs);
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..7cbb09b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -21,6 +21,7 @@
#include linux/cpufreq.h
#include linux/debugfs.h
#include linux/io.h
+#include trace/events/power.h
#include plat/clock.h
@@ -43,8 +44,10 @@ int clk_enable(struct clk *clk)
return -EINVAL;
spin_lock_irqsave(clockfw_lock, flags);
- if (arch_clock-clk_enable)
+ if (arch_clock-clk_enable) {
+ trace_clock_enable(clk-name, 1, smp_processor_id());
ret = arch_clock-clk_enable(clk);
+ }
spin_unlock_irqrestore(clockfw_lock, flags);
return ret;
@@ -66,8 +69,10 @@ void clk_disable(struct clk *clk)
goto out;
}
- if (arch_clock-clk_disable)
+ if (arch_clock-clk_disable) {
+ trace_clock_disable(clk-name, 0, smp_processor_id());
arch_clock-clk_disable(clk);
+ }
out:
spin_unlock_irqrestore(clockfw_lock, flags);
@@ -120,8 +125,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
return ret;
spin_lock_irqsave(clockfw_lock, flags);
- if (arch_clock-clk_set_rate)
+ if (arch_clock-clk_set_rate) {
+ trace_clock_set_rate(clk-name, rate, smp_processor_id());
ret = arch_clock-clk_set_rate(clk, rate);
+ }
if (ret == 0) {
if (clk-recalc)
clk-rate = clk-recalc(clk);
--
1.7.2.3
- Paul
--
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Re: [PATCH v2 5/5] omap2plus: voltage: Trivial linking fix for 'EINVAL' undeclared
On Wed, Jan 05, 2011 at 04:27:04PM +0530, Santosh Shilimkar wrote: CC arch/arm/mach-omap2/omap_hwmod_common_data.o In file included from arch/arm/plat-omap/include/plat/omap_hwmod.h:38, from arch/arm/mach-omap2/omap_hwmod_common_data.c:20: arch/arm/plat-omap/include/plat/voltage.h: In function 'omap_voltage_late_init': arch/arm/plat-omap/include/plat/voltage.h:145: error: 'EINVAL' undeclared (first use in this function) arch/arm/plat-omap/include/plat/voltage.h:145: error: (Each undeclared identifier is reported only once arch/arm/plat-omap/include/plat/voltage.h:145: error: for each function it appears in.) make[1]: *** [arch/arm/mach-omap2/omap_hwmod_common_data.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 The correct include for this is linux/errno.h, not linux/err.h - you want the errno definitions, not the IS_ERR/PTR_ERR/ERR_PTR stuff. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] perf: add calls to suspend trace point
Hi! I am in favor of 3) of 4). What do you think? Why don't we keep the tracepoints as proposed _and_ add two additional tracepoints around device suspend-resume? I like the idea but that requires to extend the current API with additional suspend tracepoints or device state change tracepoints. That can be done once the current API is firmly in place. Today the only trace API for suspend is machine_suspend(unsigned int state), so I think the best option is 3) here above. Unless there is an objection I am pushing 3) asap. Fine by me. Why not... -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 08/17] OMAP2,3: DSS2: Create platform_driver for each DSS HW IP
Hi, On Mon, 2011-01-03 at 18:21 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. Platform driver of dsshw has to be registered before of dispc, rfbi, dsi1, venc and omapdisplay driver should be after all the HW IPs. Sequence it with arch_initcall and device_initcall_sync. Do you know if there some extra meaning for the _sync initcalls? The name would imply something else that just init ordering. I don't like using multiple initcall levels in the same driver. It's already quite complicated with omapdss, omapfb and the panel drivers. What were the dependencies here? Could we have just one initcall which would do the registration of platform drivers in the correct order? Does this even work if the DSS is compiled as a module? I have the recollection that a module can only have one initcall, and in this case omapdss would have many. Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 5/5] omap2plus: voltage: Trivial linking fix for'EINVAL' undeclared
-Original Message- From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk] Sent: Wednesday, January 05, 2011 4:50 PM To: Santosh Shilimkar Cc: linux-omap@vger.kernel.org; khil...@ti.com; Nishanth Menon; t...@atomide.com; Kevin Hilman; Thara Gopinath; linux-arm- ker...@lists.infradead.org Subject: Re: [PATCH v2 5/5] omap2plus: voltage: Trivial linking fix for'EINVAL' undeclared On Wed, Jan 05, 2011 at 04:27:04PM +0530, Santosh Shilimkar wrote: CC arch/arm/mach-omap2/omap_hwmod_common_data.o In file included from arch/arm/plat- omap/include/plat/omap_hwmod.h:38, from arch/arm/mach- omap2/omap_hwmod_common_data.c:20: arch/arm/plat-omap/include/plat/voltage.h: In function 'omap_voltage_late_init': arch/arm/plat-omap/include/plat/voltage.h:145: error: 'EINVAL' undeclared (first use in this function) arch/arm/plat-omap/include/plat/voltage.h:145: error: (Each undeclared identifier is reported only once arch/arm/plat-omap/include/plat/voltage.h:145: error: for each function it appears in.) make[1]: *** [arch/arm/mach-omap2/omap_hwmod_common_data.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 The correct include for this is linux/errno.h, not linux/err.h - you want the errno definitions, not the IS_ERR/PTR_ERR/ERR_PTR stuff. In this series, newly added stub of 'omap_voltage_domain_lookup' in [PATCH v2 4/5] make use of 'ERR_PTR' which needs linux/err.h. Regards Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 0/11] dmtimer adaptation to platform_driver
dmtimer adaptation to platform_driver.
This patch series is adaptation of dmtimer code to platform driver
using omap_device and omap_hwmod abstraction.
Tested on following platforms:
OMAP1710 H3 SDP
OMAP2420 SDP
OMAP2430 SDP
OMAP3430 SDP
OMAP3630 SDP
OMAP4430 SDP
Baseline:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
Branch: origin/omap-for-linus
v8:
(1) Baselined on Tony's tree in omap-for-linus branch
(2) The last patch in v7 series has been removed because it is fixed
by following patch:
commit: 78f26e872f77b6312273216de1a8f836c6f2e143
OMAP: hwmod: Set autoidle after smartidle during _sysc_enable
TODO:
(1) OFF Mode support
(2) Upgrade timeout implementation in low-level read/write access to return
error condition to EXPORT APIs. This is re-frained in the present implementation
because that would involve change to EXPORTED APIs. Besides, there is no clear
design as yet which is agreed upon by the community.
v7:
(1) In omap1_dm_timer_set_src(), the computation of shift value to respective
dmtimer clock source was corrected:
From:
int n = (pdev-id) 1;
To:
int n = (pdev-id - 1) 1;
This change is needed because dmtimer is indexed from 1 now instead of 0.
(2) In omap1_dm_timer_init(void) memory resource end address chnaged:
From:
res[0].end = base + 0xff;
To:
res[0].end = base + 0x46;
This was causing request_mem_region() failure in driver probe().
(3) In the export APIs there are some calls which are not applicable to OMAP1.
They have been made conditional now. They include following calls:
timer-fclk = clk_get(timer-pdev-dev, fck);
omap_dm_timer_enable()
omap_dm_timer_disable()
(4) Remove usage of cpu_is_omap16xx() and instead a flag has been added in
struct dmtimer_platform_data {
...
u32 is_omap16xx:1;
}
This flag is set to 1 in mach-omap1/dmtimer.c and set to 0 in
mach-omap2/dmtimer.c
This flag is used in plat-omap/dmtimer.c wherever it needs to distiguish
omap16xx.
(5) Remove #include plat/omap_device.h from mach-omap1/dmtimer.c
(6) Instead of using macros like INT_24XX_GPTIMERx, use the numbers
directly in OMAP2420, OMAP2430 and OMAP3xxx hwmod database.
(7) pm_runtime_get_sync() and pm_runtime_put_sync() return value check modified
from positive to negative value:
if (pm_runtime_get_sync(...) 0) {
...
}
v6:
(1) Removed reset functions to mach-omap1/dmtimer.c.
Access to reset function from plat-omap/dmtimer.c is provided by means
of function pointer.
(2) Remove multiple calls to omap_device_build() for registering timer devices
during early and regular initialization. Regular device registration is now done
by reading data from temporary list. This list is populated during early init
where timer data is read from hwmod database and corresponding memory allocated.
(3) kfree(pdata) under error condition since platform_device_unregister does
not free its pdata.
(4) Removed extra header inclusion in mach-omap2 and plat-omap
NOTE: omap_dm_timer.id field could not be removed because during regular boot
there is no mechanism to match the current pdev with corresponding entry in the
timer list which was partially initialized during early boot.
v4:
(1) clock aliases are renamed as 32k_ck, sys_ck and alt_ck
(2) incorporate missing clk_put() for corresponding clk_get()
(3) modified clk_get()/clk_put() to be called once once in platform driver.
(4) consistent header for new files
(5) check return value of omap_hwmod_for_each_by_class() in device init
routines.
(6) remove is_abe_timer field in dmtimer_platform_data structure. this is
no longer needed with new input clock source aliasing.
(7) proper splitting of patch series
(8) remove register map from hwmod database.
(9) remove clock source strings array from hwmod database and associated
structure declaration from plat/dmtimer.h. this is no longer needed.
(10) remove dev_attr from hwmod database. this is no longer needed.
(11) use register offsets to identify OMAP 4 registers instead of register map.
(12) remove clock source name strings from hwmod database.
(13) introduce new mechanism for getting struct clk associated with clock source
names. this is achieved by adding clock alisases for all supported clock
sources.
(14) remove clock setup functions in mach-omap2 for populating struct clk
associated with all input clock sources because this is no longer needed with
above implementation.
(15) device names changed from dmtimer to omap-timer
(16) device index starts from 1 instead of 0
(17) remove .init_name from hwmod database. this is not needed.
(18) introduce separate functions for reading/writing interrupt registers
instead of
doing all operations within a single function.
v3:
(1) multi-line comment error correction
(2) provision to allow any of the available dmtimers as early timers
instead of restricting them to millisecond timers only.
(3) in 'struct omap_dmtimer{}' is_initialized flag is redundant and
so must be removed. if the element is found in the list it is already
initialized.
(4) remove
[PATCH v8 2/11] OMAP2420: hwmod data: add dmtimer
From: Thara Gopinath th...@ti.com
Add dmtimer data.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 634
arch/arm/plat-omap/include/plat/dmtimer.h | 11 +
2 files changed, 645 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b85c630..93f0cf9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -18,6 +18,7 @@
#include plat/serial.h
#include plat/i2c.h
#include plat/gpio.h
+#include plat/dmtimer.h
#include omap_hwmod_common_data.h
@@ -279,6 +280,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+ .name = timer,
+ .sysc = omap2420_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2420_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+ { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+ {
+ .pa_start = 0x48028000,
+ .pa_end = 0x48028000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup - timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+ .master = omap2420_l4_wkup_hwmod,
+ .slave = omap2420_timer1_hwmod,
+ .clk= gpt1_ick,
+ .addr = omap2420_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+ omap2420_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2420_timer1_hwmod = {
+ .name = timer1,
+ .mpu_irqs = omap2420_timer1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+ .main_clk = gpt1_fck,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
+ .class = omap2420_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2420_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+ { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+ {
+ .pa_start = 0x4802a000,
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core - timer2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+ .master = omap2420_l4_core_hwmod,
+ .slave = omap2420_timer2_hwmod,
+ .clk= gpt2_ick,
+ .addr = omap2420_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+ omap2420_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2420_timer2_hwmod = {
+ .name = timer2,
+ .mpu_irqs = omap2420_timer2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+ .main_clk = gpt2_fck,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+ },
+ },
+ .slaves = omap2420_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
+ .class =
[PATCH v8 3/11] OMAP2430: hwmod data: add dmtimer
From: Thara Gopinath th...@ti.com
Add dmtimer data.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 633
1 files changed, 633 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8ecfbcd..7fb7811 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,6 +18,7 @@
#include plat/serial.h
#include plat/i2c.h
#include plat/gpio.h
+#include plat/dmtimer.h
#include omap_hwmod_common_data.h
@@ -278,6 +279,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+ .name = timer,
+ .sysc = omap2430_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2430_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+ { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+ {
+ .pa_start = 0x49018000,
+ .pa_end = 0x49018000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup - timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+ .master = omap2430_l4_wkup_hwmod,
+ .slave = omap2430_timer1_hwmod,
+ .clk= gpt1_ick,
+ .addr = omap2430_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+ omap2430_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2430_timer1_hwmod = {
+ .name = timer1,
+ .mpu_irqs = omap2430_timer1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+ .main_clk = gpt1_fck,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
+ .class = omap2430_timer_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2430_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+ { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+ {
+ .pa_start = 0x4802a000,
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core - timer2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+ .master = omap2430_l4_core_hwmod,
+ .slave = omap2430_timer2_hwmod,
+ .clk= gpt2_ick,
+ .addr = omap2430_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+ omap2430_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2430_timer2_hwmod = {
+ .name = timer2,
+ .mpu_irqs = omap2430_timer2_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+ .main_clk = gpt2_fck,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+ },
+ },
+ .slaves = omap2430_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
+ .class = omap2430_timer_hwmod_class,
+ .omap_chip =
[PATCH v8 4/11] OMAP3: hwmod data: add dmtimer
From: Thara Gopinath th...@ti.com
Add dmtimer data.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 675
1 files changed, 675 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d81813..d219522 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -22,6 +22,7 @@
#include plat/i2c.h
#include plat/gpio.h
#include plat/smartreflex.h
+#include plat/dmtimer.h
#include omap_hwmod_common_data.h
@@ -417,6 +418,667 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
+/* timer class */
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
+ .name = timer,
+ .sysc = omap3xxx_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+ .name = timer,
+ .sysc = omap3xxx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap3xxx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+ { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+ {
+ .pa_start = 0x48318000,
+ .pa_end = 0x48318000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup - timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+ .master = omap3xxx_l4_wkup_hwmod,
+ .slave = omap3xxx_timer1_hwmod,
+ .clk= gpt1_ick,
+ .addr = omap3xxx_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 master port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_masters[] = {
+ omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+ omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap3xxx_timer1_hwmod = {
+ .name = timer1,
+ .mpu_irqs = omap3xxx_timer1_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+ .main_clk = gpt1_fck,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
+ },
+ },
+ .masters= omap3xxx_timer1_masters,
+ .masters_cnt= ARRAY_SIZE(omap3xxx_timer1_masters),
+ .slaves = omap3xxx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
+ .class = omap3xxx_timer_1ms_hwmod_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap3xxx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+ { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+ {
+ .pa_start = 0x49032000,
+ .pa_end = 0x49032000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per - timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+ .master = omap3xxx_l4_per_hwmod,
+ .slave = omap3xxx_timer2_hwmod,
+ .clk= gpt2_ick,
+ .addr = omap3xxx_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 master port */
+static struct
[PATCH v8 11/11] OMAP: dmtimer: add timeout to low-level routines
The low-level read and write access routines wait on
write-pending register in posted mode to make sure that
previous write is complete on respective registers.
This waiting is done in an infinite while loop. Now it
is being modified to use timeout instead.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 32
1 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index da12597..9ec3dc1 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,7 @@
#include linux/err.h
#include linux/platform_device.h
#include plat/dmtimer.h
+#include plat/common.h
/* register offsets */
#define _OMAP_TIMER_ID_OFFSET 0x00
@@ -153,6 +154,7 @@
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR WPSHIFT))
+#define MAX_WRITE_PEND_WAIT1 /* 10ms timeout delay */
static LIST_HEAD(omap_timer_list);
static DEFINE_SPINLOCK(dm_timer_lock);
@@ -169,16 +171,23 @@ static DEFINE_SPINLOCK(dm_timer_lock);
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
{
struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+ int i = 0;
if (reg = OMAP_TIMER_WAKEUP_EN_REG)
reg += pdata-func_offset;
else if (reg = OMAP_TIMER_STAT_REG)
reg += pdata-intr_offset;
- if (timer-posted)
- while (readl(timer-io_base + (OMAP_TIMER_WRITE_PEND_REG
0xff))
-(reg WPSHIFT))
- cpu_relax();
+ if (timer-posted) {
+ omap_test_timeout(!(readl(timer-io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG +
+ pdata-func_offset) 0xff)) (reg WPSHIFT)),
+ MAX_WRITE_PEND_WAIT, i);
+
+ if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT))
+ pr_err(: read timeout\n);
+ }
+
return readl(timer-io_base + (reg 0xff));
}
@@ -196,16 +205,23 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer
*timer, u32 reg,
u32 value)
{
struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+ int i = 0;
if (reg = OMAP_TIMER_WAKEUP_EN_REG)
reg += pdata-func_offset;
else if (reg = OMAP_TIMER_STAT_REG)
reg += pdata-intr_offset;
- if (timer-posted)
- while (readl(timer-io_base + (OMAP_TIMER_WRITE_PEND_REG
0xff))
-(reg WPSHIFT))
- cpu_relax();
+ if (timer-posted) {
+ omap_test_timeout(!(readl(timer-io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG +
+ pdata-func_offset) 0xff)) (reg WPSHIFT)),
+ MAX_WRITE_PEND_WAIT, i);
+
+ if (WARN_ON(i == MAX_WRITE_PEND_WAIT))
+ pr_err(: write timeout\n);
+ }
+
writel(value, timer-io_base + (reg 0xff));
}
--
1.6.0.4
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[PATCH v8 5/11] OMAP4: hwmod data: add dmtimer
From: Cousson, Benoit b-cous...@ti.com
Add dmtimer data.
Signed-off-by: Cousson, Benoit b-cous...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 622
arch/arm/plat-omap/include/plat/dmtimer.h |2 +
2 files changed, 624 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd..fcaa7e9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -24,6 +24,7 @@
#include plat/cpu.h
#include plat/gpio.h
#include plat/dma.h
+#include plat/dmtimer.h
#include omap_hwmod_common_data.h
@@ -1639,6 +1640,614 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
};
/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
+ .name = timer,
+ .sysc = omap44xx_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+ .name = timer,
+ .sysc = omap44xx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_2,
+};
+
+/* timer1 */
+static struct omap_hwmod omap44xx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+ { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4a318000,
+ .pa_end = 0x4a31807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup - timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+ .master = omap44xx_l4_wkup_hwmod,
+ .slave = omap44xx_timer1_hwmod,
+ .clk= l4_wkup_clk_mux_ck,
+ .addr = omap44xx_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ omap44xx_l4_wkup__timer1,
+};
+
+static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = timer1,
+ .class = omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = timer1_fck,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer2 */
+static struct omap_hwmod omap44xx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+ { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per - timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+ .master = omap44xx_l4_per_hwmod,
+ .slave = omap44xx_timer2_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+ omap44xx_l4_per__timer2,
+};
+
+static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .name = timer2,
+ .class = omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
+ .main_clk =
[PATCH v8 9/11] OMAP: dmtimer: switch-over to platform device driver
switch-over to platform device driver through following changes:
(a) call to dmtimer initialization routine from timer-gp.c is
removed (b) initiate dmtimer early initialization from omap2_init_common_hw
in io.c (c) modify plat-omap/dmtimer routines to use new register map and
platform data.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/clock2420_data.c |2 +-
arch/arm/mach-omap2/clock2430_data.c |2 +-
arch/arm/mach-omap2/clock3xxx_data.c |2 +-
arch/arm/mach-omap2/clock44xx_data.c |2 +-
arch/arm/mach-omap2/dmtimer.c | 61 +
arch/arm/mach-omap2/dmtimer.h | 30 +++
arch/arm/mach-omap2/io.c |4 +-
arch/arm/mach-omap2/timer-gp.c|1 -
arch/arm/plat-omap/dmtimer.c | 349 -
arch/arm/plat-omap/include/plat/dmtimer.h |4 +-
10 files changed, 191 insertions(+), 266 deletions(-)
create mode 100644 arch/arm/mach-omap2/dmtimer.h
diff --git a/arch/arm/mach-omap2/clock2420_data.c
b/arch/arm/mach-omap2/clock2420_data.c
index 00c72a0..67f0133 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1801,7 +1801,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, virt_prcm_set, virt_prcm_set, CK_242X),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, gpt1_ick, gpt1_ick, CK_242X),
- CLK(NULL, gpt1_fck, gpt1_fck, CK_242X),
+ CLK(omap_timer.1, fck, gpt1_fck, CK_242X),
CLK(NULL, gpt2_ick, gpt2_ick, CK_242X),
CLK(omap_timer.2, fck, gpt2_fck, CK_242X),
CLK(NULL, gpt3_ick, gpt3_ick, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c
b/arch/arm/mach-omap2/clock2430_data.c
index 323b43e..dc62a53 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1905,7 +1905,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, virt_prcm_set, virt_prcm_set, CK_243X),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, gpt1_ick, gpt1_ick, CK_243X),
- CLK(NULL, gpt1_fck, gpt1_fck, CK_243X),
+ CLK(omap_timer.1, fck, gpt1_fck, CK_243X),
CLK(NULL, gpt2_ick, gpt2_ick, CK_243X),
CLK(omap_timer.2, fck, gpt2_fck, CK_243X),
CLK(NULL, gpt3_ick, gpt3_ick, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index 01e3977..055669b 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3369,7 +3369,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, usbhost_48m_fck, usbhost_48m_fck, CK_3430ES2PLUS |
CK_AM35XX | CK_36XX),
CLK(NULL, usbhost_ick, usbhost_ick, CK_3430ES2PLUS |
CK_AM35XX | CK_36XX),
CLK(NULL, usim_fck, usim_fck, CK_3430ES2PLUS |
CK_36XX),
- CLK(NULL, gpt1_fck, gpt1_fck, CK_3XXX),
+ CLK(omap_timer.1, fck, gpt1_fck, CK_3XXX),
CLK(NULL, wkup_32k_fck, wkup_32k_fck, CK_3XXX),
CLK(NULL, gpio1_dbck, gpio1_dbck,CK_3XXX),
CLK(omap_wdt, fck, wdt2_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index f319c69..2a6a6d3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3182,7 +3182,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, smartreflex_core_fck, smartreflex_core_fck,
CK_443X),
CLK(NULL, smartreflex_iva_fck, smartreflex_iva_fck,
CK_443X),
CLK(NULL, smartreflex_mpu_fck, smartreflex_mpu_fck,
CK_443X),
- CLK(NULL, gpt1_fck, timer1_fck,
CK_443X),
+ CLK(omap_timer.1, fck, timer1_fck,CK_443X),
CLK(omap_timer.10,fck, timer10_fck, CK_443X),
CLK(omap_timer.11,fck, timer11_fck, CK_443X),
CLK(omap_timer.2, fck, timer2_fck,CK_443X),
diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-omap2/dmtimer.c
index 90ddb88..1fec590 100644
--- a/arch/arm/mach-omap2/dmtimer.c
+++ b/arch/arm/mach-omap2/dmtimer.c
@@ -192,3 +192,64 @@ static int __init omap_timer_init(struct omap_hwmod *oh,
void *unused)
return ret;
}
+
+/**
+ * omap2_dm_timer_early_init - top level early timer initialization
+ * called in the last part of omap2_init_common_hw
+ *
+ * Uses dedicated hwmod api to parse through hwmod database for
+ * given class name and then build and register the timer device.
+ * At the end driver is registered and early probe initiated.
+ */
+void __init
[PATCH v8 8/11] OMAP: dmtimer: platform driver
From: Thara Gopinath th...@ti.com
Add dmtimer platform driver functions which include:
(1) platform driver initialization
(2) driver probe function
(3) driver remove function
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 169 -
arch/arm/plat-omap/include/plat/dmtimer.h |2 +
2 files changed, 170 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1bfaf09..4fde788 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,9 @@
#include linux/delay.h
#include linux/io.h
#include linux/module.h
+#include linux/slab.h
+#include linux/err.h
+#include linux/platform_device.h
#include mach/hardware.h
#include plat/dmtimer.h
#include mach/irqs.h
@@ -257,7 +260,8 @@ static struct omap_dm_timer *dm_timers;
static const char **dm_source_names;
static struct clk **dm_source_clocks;
-static spinlock_t dm_timer_lock;
+static LIST_HEAD(omap_timer_list);
+static DEFINE_SPINLOCK(dm_timer_lock);
/*
* Reads timer registers in posted and non-posted mode. The posted mode bit
@@ -689,6 +693,169 @@ int omap_dm_timers_active(void)
}
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
+/**
+ * omap_dm_timer_probe - probe function called for every registered device
+ * @pdev: pointer to current timer platform device
+ *
+ * Called by driver framework at the end of device registration for all
+ * timer devices.
+ */
+static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
+{
+ int ret;
+ unsigned long flags;
+ struct omap_dm_timer *timer;
+ struct resource *mem, *irq, *ioarea;
+ struct dmtimer_platform_data *pdata = pdev-dev.platform_data;
+
+ dev_dbg(pdev-dev, %s: +\n, __func__);
+
+ if (!pdata) {
+ dev_err(pdev-dev, %s: no platform data\n, __func__);
+ return -ENODEV;
+ }
+
+ spin_lock_irqsave(dm_timer_lock, flags);
+ list_for_each_entry(timer, omap_timer_list, node)
+ if (!pdata-is_early_init timer-id == pdev-id) {
+ timer-pdev = pdev;
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+ dev_dbg(pdev-dev, Regular Probed\n);
+ return 0;
+ }
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (unlikely(!irq)) {
+ dev_err(pdev-dev, %s: no IRQ resource\n, __func__);
+ ret = -ENODEV;
+ goto err_free_pdev;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!mem)) {
+ dev_err(pdev-dev, %s: no memory resource\n, __func__);
+ ret = -ENODEV;
+ goto err_free_pdev;
+ }
+
+ ioarea = request_mem_region(mem-start, resource_size(mem),
+ pdev-name);
+ if (!ioarea) {
+ dev_err(pdev-dev, %s: region already claimed\n, __func__);
+ ret = -EBUSY;
+ goto err_free_pdev;
+ }
+
+ timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+ if (!timer) {
+ dev_err(pdev-dev, %s: no memory for omap_dm_timer\n,
+ __func__);
+ ret = -ENOMEM;
+ goto err_release_ioregion;
+ }
+
+ timer-io_base = ioremap(mem-start, resource_size(mem));
+ if (!timer-io_base) {
+ dev_err(pdev-dev, %s: ioremap failed\n, __func__);
+ ret = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ /*
+* Following func pointers are required by OMAP1's reset code
+* in mach-omap1/dmtimer.c to access to low level read/write.
+*/
+ if (pdata-is_omap16xx) {
+ pdata-dm_timer_read_reg = omap_dm_timer_read_reg;
+ pdata-dm_timer_write_reg = omap_dm_timer_write_reg;
+ pdata-is_early_init = 0;
+ }
+
+ timer-id = pdev-id;
+ timer-irq = irq-start;
+ timer-pdev = pdev;
+ timer-reserved = 0;
+
+ /* add the timer element to the list */
+ spin_lock_irqsave(dm_timer_lock, flags);
+ list_add_tail(timer-node, omap_timer_list);
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+
+ dev_dbg(pdev-dev, Early Probed\n);
+
+ return 0;
+
+err_free_mem:
+ kfree(timer);
+
+err_release_ioregion:
+ release_mem_region(mem-start, resource_size(mem));
+
+err_free_pdev:
+ kfree(pdata);
+ platform_device_unregister(pdev);
+
+ return ret;
+}
+
+/**
+ * omap_dm_timer_remove - cleanup a registered timer device
+ * @pdev: pointer to current timer platform device
+ *
+ * Called by driver framework whenever a timer device is unregistered.
+ * In addition
[PATCH v8 10/11] OMAP: dmtimer: pm_runtime support
Add pm_runtime support to dmtimer. Since dmtimer is used during
early boot before pm_runtime is initialized completely there are
provisions to enable/disable clocks directly in the code during
early boot.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
[p-bas...@ti.com: added pm_runtime logic in probe()]
Signed-off-by: Partha Basak p-bas...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 60 +++--
1 files changed, 51 insertions(+), 9 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index f1d7a47..da12597 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -39,6 +39,7 @@
#include linux/delay.h
#include linux/io.h
#include linux/slab.h
+#include linux/pm_runtime.h
#include linux/err.h
#include linux/platform_device.h
#include plat/dmtimer.h
@@ -213,13 +214,16 @@ static void omap_dm_timer_prepare(struct omap_dm_timer
*timer)
{
struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
- timer-fclk = clk_get(timer-pdev-dev, fck);
- if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer-fclk))) {
- dev_err(timer-pdev-dev, : No fclk handle.\n);
- return;
+ if (!pdata-is_omap16xx) {
+ timer-fclk = clk_get(timer-pdev-dev, fck);
+ if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer-fclk))) {
+ dev_err(timer-pdev-dev, : No fclk handle.\n);
+ return;
+ }
}
- omap_dm_timer_enable(timer);
+ if (!pdata-is_omap16xx)
+ omap_dm_timer_enable(timer);
if (pdata-dm_timer_reset)
pdata-dm_timer_reset(timer);
@@ -294,10 +298,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free);
void omap_dm_timer_enable(struct omap_dm_timer *timer)
{
+ struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+
if (timer-enabled)
return;
- clk_enable(timer-fclk);
+ if (unlikely(pdata-is_early_init)) {
+ clk_enable(timer-fclk);
+ timer-enabled = 1;
+ return;
+ }
+
+ if (pm_runtime_get_sync(timer-pdev-dev) 0) {
+ dev_err(timer-pdev-dev, %s: pm_runtime_get_sync() FAILED\n,
+ __func__);
+ return;
+ }
timer-enabled = 1;
}
@@ -305,10 +321,22 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
+ struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+
if (!timer-enabled)
return;
- clk_disable(timer-fclk);
+ if (unlikely(pdata-is_early_init)) {
+ clk_disable(timer-fclk);
+ timer-enabled = 0;
+ return;
+ }
+
+ if (pm_runtime_put_sync(timer-pdev-dev) 0) {
+ dev_err(timer-pdev-dev, %s: pm_runtime_put_sync() FAILED\n,
+ __func__);
+ return;
+ }
timer-enabled = 0;
}
@@ -426,12 +454,14 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer,
int source)
if (source 0 || source = 3)
return -EINVAL;
- omap_dm_timer_disable(timer);
+ if (!pdata-is_omap16xx)
+ omap_dm_timer_disable(timer);
/* change the timer clock source */
ret = pdata-set_timer_src(timer-pdev, source);
- omap_dm_timer_enable(timer);
+ if (!pdata-is_omap16xx)
+ omap_dm_timer_enable(timer);
/*
* When the functional clock disappears, too quick writes seem
@@ -605,11 +635,21 @@ static int __devinit omap_dm_timer_probe(struct
platform_device *pdev)
return -ENODEV;
}
+ /* OMAP2+
+* Early timers are already registered and in list.
+* What we need to do during second phase of probe
+* is to assign the newly allocated/configured pdev
+* to timer-pdev. We also call pm_runtime_enable()
+* for each device because it could not be called
+* during early boot because pm_runtime framework
+* was not yet up and running.
+*/
spin_lock_irqsave(dm_timer_lock, flags);
list_for_each_entry(timer, omap_timer_list, node)
if (!pdata-is_early_init timer-id == pdev-id) {
timer-pdev = pdev;
spin_unlock_irqrestore(dm_timer_lock, flags);
+ pm_runtime_enable(pdev-dev);
dev_dbg(pdev-dev, Regular Probed\n);
return 0;
}
@@ -660,6 +700,8 @@ static int __devinit omap_dm_timer_probe(struct
platform_device *pdev)
pdata-dm_timer_read_reg = omap_dm_timer_read_reg;
pdata-dm_timer_write_reg = omap_dm_timer_write_reg;
[PATCH v8 7/11] OMAP2+: dmtimer: convert to platform devices
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver. It also provides
provision to access timers during early boot when pm_runtime framework
is not completely up and running.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +-
arch/arm/mach-omap2/dmtimer.c | 194 +
2 files changed, 195 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/dmtimer.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4ab82f6..0e6c2cd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
-common.o gpio.o dma.o wd_timer.o
+common.o gpio.o dma.o wd_timer.o dmtimer.o
omap-2-3-common= irq.o sdrc.o
hwmod-common = omap_hwmod.o \
diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-omap2/dmtimer.c
new file mode 100644
index 000..90ddb88
--- /dev/null
+++ b/arch/arm/mach-omap2/dmtimer.c
@@ -0,0 +1,194 @@
+/**
+ * OMAP2+ Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which extracts timers
+ * information from hwmod database and registers with linux device model.
+ * It also has low level function to change the timer input clock source.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma tarun.ka...@ti.com
+ * Thara Gopinath th...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/slab.h
+
+#include plat/dmtimer.h
+#include plat/omap_device.h
+
+/*
+ * OMAP4 IP revision has different register offsets
+ * for interrupt registers and functional registers.
+ */
+#define VERSION2_TIMER_WAKEUP_EN_REG_OFFSET0x14
+#define VERSION2_TIMER_STAT_REG_OFFSET 0x10
+
+static int early_timer_count __initdata = 1;
+
+struct dm_timer_data {
+ struct omap_device *od;
+ struct dmtimer_platform_data *pdata;
+ struct list_head node;
+};
+
+static __initdata LIST_HEAD(dm_timer_data_list);
+
+/**
+ * omap2_dm_timer_set_src - change the timer input clock source
+ * @pdev: timer platform device pointer
+ * @timer_clk: current clock source
+ * @source:array index of parent clock source
+ */
+static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
+{
+ int ret;
+ struct dmtimer_platform_data *pdata = pdev-dev.platform_data;
+ struct clk *fclk = clk_get(pdev-dev, fck);
+ struct clk *new_fclk;
+ char *fclk_name = 32k_ck; /* default name */
+
+ switch (source) {
+ case OMAP_TIMER_SRC_SYS_CLK:
+ fclk_name = sys_ck;
+ break;
+
+ case OMAP_TIMER_SRC_32_KHZ:
+ fclk_name = 32k_ck;
+ break;
+
+ case OMAP_TIMER_SRC_EXT_CLK:
+ if (pdata-timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
+ fclk_name = alt_ck;
+ break;
+ }
+ dev_err(pdev-dev, %s: %d: invalid clk src.\n,
+ __func__, __LINE__);
+ return -EINVAL;
+ }
+
+ if (IS_ERR_OR_NULL(fclk)) {
+ dev_err(pdev-dev, %s: %d: clk_get() FAILED\n,
+ __func__, __LINE__);
+ return -EINVAL;
+ }
+
+ new_fclk = clk_get(pdev-dev, fclk_name);
+ if (IS_ERR_OR_NULL(new_fclk)) {
+ dev_err(pdev-dev, %s: %d: clk_get() %s FAILED\n,
+ __func__, __LINE__, fclk_name);
+ clk_put(fclk);
+ return -EINVAL;
+ }
+
+ ret = clk_set_parent(fclk, new_fclk);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(pdev-dev, %s: clk_set_parent() to %s FAILED\n,
+ __func__, fclk_name);
+ ret = -EINVAL;
+ }
+
+ clk_put(new_fclk);
+ clk_put(fclk);
+
+ return ret;
+}
+
+struct omap_device_pm_latency omap2_dmtimer_latency[] = {
+ {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+
[PATCH v8 6/11] OMAP1: dmtimer: conversion to platform devices
From: Thara Gopinath th...@ti.com
Convert OMAP1 dmtimers into a platform devices and then registers with
device model framework so that it can be bound to corresponding driver.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap1/Makefile |2 +-
arch/arm/mach-omap1/dmtimer.c | 217 +
arch/arm/mach-omap1/timer32k.c|4 -
arch/arm/plat-omap/dmtimer.c | 64 +
arch/arm/plat-omap/include/plat/dmtimer.h | 24 +++-
5 files changed, 249 insertions(+), 62 deletions(-)
create mode 100644 arch/arm/mach-omap1/dmtimer.c
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 6ee1950..d271f87 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,7 +4,7 @@
# Common support
obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
-obj-y += clock.o clock_data.o opp_data.o
+obj-y += clock.o clock_data.o opp_data.o dmtimer.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/dmtimer.c b/arch/arm/mach-omap1/dmtimer.c
new file mode 100644
index 000..a4a5ff5
--- /dev/null
+++ b/arch/arm/mach-omap1/dmtimer.c
@@ -0,0 +1,217 @@
+/**
+ * OMAP1 Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which internally
+ * generates timer device information and registers with linux
+ * device model. It also has low level function to chnage the timer
+ * input clock source.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma tarun.ka...@ti.com
+ * Thara Gopinath th...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/err.h
+#include linux/slab.h
+#include linux/platform_device.h
+
+#include mach/irqs.h
+
+#include plat/dmtimer.h
+
+#define OMAP1610_GPTIMER1_BASE 0xfffb1400
+#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
+#define OMAP1610_GPTIMER3_BASE 0xfffb2400
+#define OMAP1610_GPTIMER4_BASE 0xfffb2c00
+#define OMAP1610_GPTIMER5_BASE 0xfffb3400
+#define OMAP1610_GPTIMER6_BASE 0xfffb3c00
+#define OMAP1610_GPTIMER7_BASE 0xfffb7400
+#define OMAP1610_GPTIMER8_BASE 0xfffbd400
+
+#define OMAP1_DM_TIMER_COUNT 8
+
+#define OMAP_TIMER_OCP_CFG_REG 0x10
+#define OMAP_TIMER_SYS_STAT_REG0x14
+#define OMAP_TIMER_IF_CTRL_REG 0x40
+
+static int omap1_dm_timer_set_src(struct platform_device *pdev,
+ int source)
+{
+ int n = (pdev-id - 1) 1;
+ u32 l;
+
+ l = omap_readl(MOD_CONF_CTRL_1) ~(0x03 n);
+ l |= source n;
+ omap_writel(l, MOD_CONF_CTRL_1);
+
+ return 0;
+}
+
+static void omap1_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
+{
+ int c;
+ struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+
+ c = 0;
+ while (!(pdata-dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) 1))
{
+ c++;
+ if (c 10) {
+ printk(KERN_ERR Timer failed to reset.\n);
+ return;
+ }
+ }
+}
+
+static void omap1_dm_timer_reset(struct omap_dm_timer *timer)
+{
+ u32 l;
+ struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+
+ if (timer-pdev-id != 1) {
+ pdata-dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
+ omap1_dm_timer_wait_for_reset(timer);
+ }
+
+ l = pdata-dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
+ l |= 0x02 3; /* Set to smart-idle mode */
+ l |= 0x2 8; /* Set clock activity to perserve f-clock on idle */
+ pdata-dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
+}
+
+
+int __init omap1_dm_timer_init(void)
+{
+ int i;
+ int ret;
+ struct dmtimer_platform_data *pdata;
+ struct platform_device *pdev;
+
+ pr_debug(%s: +\n, __func__);
+
+ if (!cpu_is_omap16xx())
+ return 0;
+
+ for (i = 1; i = OMAP1_DM_TIMER_COUNT; i++) {
+ struct resource res[2];
+ u32 base, irq;
+
+ switch (i) {
+ case 1:
+ base = OMAP1610_GPTIMER1_BASE;
+ irq = INT_1610_GPTIMER1;
+ break;
+ case 2:
+
[PATCH v8 1/11] OMAP2+: dmtimer: add device names to flck nodes
From: Thara Gopinath th...@ti.com
Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be
retrieved by doing a clk_get with the corresponding device pointers or
device names.
NOTE: gpt1_fck is modified in patch-10 when we switch to platform device
driver. This is to make sure that each patch compiles and boots.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/clock2420_data.c | 58 +++--
arch/arm/mach-omap2/clock2430_data.c | 58 +++--
arch/arm/mach-omap2/clock3xxx_data.c | 46 --
arch/arm/mach-omap2/clock44xx_data.c | 43 +++--
4 files changed, 162 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c
b/arch/arm/mach-omap2/clock2420_data.c
index ed1295f..00c72a0 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, gpt1_ick, gpt1_ick, CK_242X),
CLK(NULL, gpt1_fck, gpt1_fck, CK_242X),
CLK(NULL, gpt2_ick, gpt2_ick, CK_242X),
- CLK(NULL, gpt2_fck, gpt2_fck, CK_242X),
+ CLK(omap_timer.2, fck, gpt2_fck, CK_242X),
CLK(NULL, gpt3_ick, gpt3_ick, CK_242X),
- CLK(NULL, gpt3_fck, gpt3_fck, CK_242X),
+ CLK(omap_timer.3, fck, gpt3_fck, CK_242X),
CLK(NULL, gpt4_ick, gpt4_ick, CK_242X),
- CLK(NULL, gpt4_fck, gpt4_fck, CK_242X),
+ CLK(omap_timer.4, fck, gpt4_fck, CK_242X),
CLK(NULL, gpt5_ick, gpt5_ick, CK_242X),
- CLK(NULL, gpt5_fck, gpt5_fck, CK_242X),
+ CLK(omap_timer.5, fck, gpt5_fck, CK_242X),
CLK(NULL, gpt6_ick, gpt6_ick, CK_242X),
- CLK(NULL, gpt6_fck, gpt6_fck, CK_242X),
+ CLK(omap_timer.6, fck, gpt6_fck, CK_242X),
CLK(NULL, gpt7_ick, gpt7_ick, CK_242X),
- CLK(NULL, gpt7_fck, gpt7_fck, CK_242X),
+ CLK(omap_timer.7, fck, gpt7_fck, CK_242X),
CLK(NULL, gpt8_ick, gpt8_ick, CK_242X),
- CLK(NULL, gpt8_fck, gpt8_fck, CK_242X),
+ CLK(omap_timer.8, fck, gpt8_fck, CK_242X),
CLK(NULL, gpt9_ick, gpt9_ick, CK_242X),
- CLK(NULL, gpt9_fck, gpt9_fck, CK_242X),
+ CLK(omap_timer.9, fck, gpt9_fck, CK_242X),
CLK(NULL, gpt10_ick,gpt10_ick, CK_242X),
- CLK(NULL, gpt10_fck,gpt10_fck, CK_242X),
+ CLK(omap_timer.10,fck, gpt10_fck, CK_242X),
CLK(NULL, gpt11_ick,gpt11_ick, CK_242X),
- CLK(NULL, gpt11_fck,gpt11_fck, CK_242X),
+ CLK(omap_timer.11,fck, gpt11_fck, CK_242X),
CLK(NULL, gpt12_ick,gpt12_ick, CK_242X),
- CLK(NULL, gpt12_fck,gpt12_fck, CK_242X),
+ CLK(omap_timer.12,fck, gpt12_fck, CK_242X),
CLK(omap-mcbsp.1, ick, mcbsp1_ick,CK_242X),
CLK(omap-mcbsp.1, fck, mcbsp1_fck,CK_242X),
CLK(omap-mcbsp.2, ick, mcbsp2_ick,CK_242X),
@@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, pka_ick, pka_ick, CK_242X),
CLK(NULL, usb_fck, usb_fck, CK_242X),
CLK(musb_hdrc,fck, osc_ck,CK_242X),
+ CLK(omap_timer.1, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.2, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.3, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.4, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.5, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.6, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.7, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.8, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.9, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.10,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.11,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.12,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.1, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.2, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.3, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.4, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.5, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.6, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.7,
Re: [PATCH v3 08/17] OMAP2,3: DSS2: Create platform_driver for each DSS HW IP
Hi Tomi, On Wed, Jan 5, 2011 at 4:57 PM, Tomi Valkeinen tomi.valkei...@nokia.com wrote: Hi, On Mon, 2011-01-03 at 18:21 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. Platform driver of dsshw has to be registered before of dispc, rfbi, dsi1, venc and omapdisplay driver should be after all the HW IPs. Sequence it with arch_initcall and device_initcall_sync. Do you know if there some extra meaning for the _sync initcalls? The name would imply something else that just init ordering. [Sumit]:Looking at include/linux/init.h and some web-references [1] [2] [3], our understanding is that all inits called via device_initcall_sync() would be called later than the ones called by device_initcall() in an SMP environment. [1] points to the patch for enabling all probes on one level to finish before initcall for next level are processed. I don't like using multiple initcall levels in the same driver. It's already quite complicated with omapdss, omapfb and the panel drivers. What were the dependencies here? Could we have just one initcall which would do the registration of platform drivers in the correct order? [Sumit]: With this patchset, dss would have platform drivers for each of the DSS h/w IPs - core would only do panel registration and s/w inits (like dpi and sdi). dispc, dss, rfbi, venc each of these are separate platform drivers which will have their own init(). The idea was to order the inits like this: [bus, then h/w IPs, then s/w blocks]. So, omap_dss_bus_init first = core_initcall() then omap_dss for dss hw ip init = arch_initcall() then any of the other h/w IPs (dsi, rfbi, venc, dispc) in any order = device_initcall(). omap_display device in the end = device_initcall_sync(); this would also call s/w blocks init, and the panel devices. (this should wait for all others to have finished). omapfb is a lateinit call, so will happen after all other dss inits have happened. Does this even work if the DSS is compiled as a module? I have the recollection that a module can only have one initcall, and in this case omapdss would have many. [Sumit]: we haven't tried compiling DSS as module - I guess we will have to create each dss hw IP also as a separate module. About making one common initcall, then I think we would need to have all platform_driver related functions either as global or in one file. is this a better option than having each as a separate module? I guess I will send the updated patch series once we agree on this. [I have incorporated all other comments from Tony, Kevin and you on the other patches]. Best regards, ~Sumit. Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html [1]: http://readlist.com/lists/vger.kernel.org/linux-kernel/54/273365.html [2]: http://www.webservertalk.com/archive242-2006-10-1713467.html [3]: http://linux.derkeiler.com/Mailing-Lists/Kernel/2009-01/msg11683.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] OMAP: TWL: sparse fixes
Russell King - ARM Linux wrote, on 01/04/2011 06:25 PM: On Tue, Jan 04, 2011 at 02:37:23PM -0600, Nishanth Menon wrote: hmm.. minor nit (with codesourcery 2010.09-50 - 4.5.1): rm arch/arm/mach-omap2/*.o;make C=1 arch/arm/mach-omap2/ 2Kerr;make C=2 arch/arm/mach-omap2/ 2Kerr1;diff Kerr Kerr1 [..] 1,4d0 arch/arm/mach-omap2/mux.c: In function 'omap_mux_get_by_name': arch/arm/mach-omap2/mux.c:163:17: warning: 'found_mode' may be used uninitialized in this function arch/arm/mach-omap2/clkt_clksel.c: In function 'omap2_clksel_set_parent': arch/arm/mach-omap2/clkt_clksel.c:100:35: warning: 'max_clkr' may be used uninitialized in this function Kinda interesting to note that C=2 does'nt list all potential gcc warnings :( if one wanted a collated list of all warnings, rm .../*.o helps I guess. C=2 only runs sparse - so if you're committing patches to fix sparse warnings, that's what you should be interested in. I'd suggest that fixing sparse warnings and GCC warnings in a single patch is probably not the best thing to do - GCC warnings are less subjective than sparse warnings. I agree. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] omap: wd_timer: Fix crash frm wdt_probe when !CONFIG_RUNTIME_PM
-Original Message- From: Santosh Shilimkar [mailto:santosh.shilim...@ti.com] Sent: Wednesday, January 05, 2011 7:11 PM To: linux-omap@vger.kernel.org Cc: linux-arm-ker...@lists.infradead.org; Santosh Shilimkar; Paul Walmsley Subject: [PATCH] omap: wd_timer: Fix crash frm wdt_probe when !CONFIG_RUNTIME_PM (Removing unnecessary changes which got committed by mistake) From c9c34f9bcff789bb2354c299e2c47aa74c8c07ed Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar santosh.shilim...@ti.com Date: Wed, 5 Jan 2011 18:41:20 +0530 Subject: [PATCH] omap: wd_timer: Fix crash frm wdt_probe when !CONFIG_RUNTIME_PM Commit ff2516fb 'wd_timer: disable on boot via hwmod postsetup mechanism' introduced watchdog timer state state management using postsetup_state. This was done to allow some board files to support watchdog coverage throughout kernel initialization and it work as intended when RUNTIME_PM is enabled. With !CONFIG_RUNTIME_PM and no board is specifically requests watchdog to remain enabled the omap_wdt_probe crashesh. This is because hwmod in absense of runtime PM unable to turn watchdog clocks because it's state is set to be disabled. For rest of the device, the state is set as enabled in absense of RUNTIME_PM [1.372558] Unhandled fault: imprecise external abort (0x1406) at 0xad733eeb [1.379913] Internal error: : 1406 [#1] SMP [1.384277] last sysfs file: [1.387359] Modules linked in: [1.390563] CPU: 0Tainted: GW (2.6.37-rc7-00265-g4298a4c-dirty #23) [1.398468] PC is at omap_wdt_disable+0x2c/0x3c [1.403198] LR is at omap_wdt_probe+0x124/0x1e0 [1.407928] pc : [c02f5bf4]lr : [c03be10c]psr: 6013 [1.407958] sp : df833f00 ip : fp : [1.419921] r10: c0ac57ac r9 : df959e00 r8 : [1.425384] r7 : df959e08 r6 : df8000c0 r5 : df95bebc r4 : df87dde0 [1.432189] r3 : fc314000 r2 : r1 : fc314034 r0 : df87dde0 This patch make the default watchdog state to be enabled in case of !CONFIG_RUNTIME_PM. This fixes the crash Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com Cc: Paul Walmsley p...@pwsan.com --- Paul, I am not too sure if it breaks your _shutdown idea of watchdog timer. Patch generated against 'omap-for-linus' branch and boot tested on OMAP4 with and without CONFIG_OMAP_WATCHDOG. arch/arm/mach-omap2/io.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index e66687b..b879a16 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -378,7 +378,11 @@ void __init omap2_init_common_infrastructure(void) * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional */ +#ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_DISABLED; +#else + postsetup_state = _HWMOD_STATE_ENABLED; +#endif omap_hwmod_for_each_by_class(wd_timer, _set_hwmod_postsetup_state, postsetup_state); -- 1.6.0.4 0001-omap-wd_timer-Fix-crash-frm-wdt_probe-when-CONFIG.patch Description: Binary data
Re: [PATCH 1/5] ASoC: DMIC: Adding the OMAP DMIC driver
Mark,
On Tue, Dec 28, 2010 at 8:18 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Mon, Dec 27, 2010 at 10:17:02PM -0600, David Lambert wrote:
+ case 1920:
+ if (div == 5)
+ div_sel = 0x1;
+ else if (div == 8)
+ div_sel = 0x0;
+ break;
A switch statement for the valid div values would feel more natural,
together with a default case to report errors though that's handled
below so could be skipped.
+ /* Acknowledge irq event */
+ omap_dmic_write(dmic, OMAP_DMIC_IRQSTATUS, irq_status);
+ if (irq_status OMAP_DMIC_IRQ_FULL)
Blank line between these two.
+ dev_dbg(dmic-dev, DMIC FIFO error %x\n, irq_status);
+
+ if (irq_status OMAP_DMIC_IRQ_EMPTY)
+ dev_dbg(dmic-dev, DMIC FIFO error %x\n, irq_status);
I'd expect these errors to be displayed by default.
+ if (irq_status OMAP_DMIC_IRQ)
+ dev_dbg(dmic-dev, DMIC write request\n);
A comment explaining why we don't actually do anything with the request
would be helpful. Given that we're ignoring the event it'd seem better
to just leave it masked and not take the interrupt in the first place.
Since the IRQ handler isn't really doing anything in this driver,
would it better
to just not have one?
+static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
+
+ if (!dmic-active++)
+ pm_runtime_get_sync(dmic-dev);
The pm_runtime API does refcounting for you so you should be able to
just skip the active count check here, IIRC there's a pm_runtime API you
could use to query if the DMIC is enabled so you could skip the local
refcount entirely.
I haven't been able to find a an API to query it, but I could just
reference the count
directly with dmic-dev-power.usage_count.
+static int omap_dmic_dai_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
+ struct omap_dmic_link *link = dmic-link;
+ int ret = 0;
+
+ if (dmic-active == 1) {
+ ret = omap_dmic_close(dmic);
+ link-channels = 0;
+ }
I'd feel a bit more happy if this were done in the same place as the
drop of the refcount though this should actually be OK I think.
+ switch (freq) {
+ case 1920:
+ case 2400:
+ case 24576000:
+ case 1200:
+ dmic-clk_freq = freq;
+ break;
+ default:
+ dev_err(dai-dev, clk freq not supported %d\n, freq);
+ ret = -EINVAL;
+ goto err_freq;
+ }
Can't you ask the parent clock what rate it's set to?
Didn't really think there was a need for that on the audio driver.
There are clock API's available
to query that already.
+ ret = request_threaded_irq(dmic-irq, NULL, omap_dmic_irq_handler,
+ IRQF_ONESHOT, DMIC, (void *)dmic);
+ if (ret) {
+ dev_err(dmic-dev, irq request failed\n);
+ goto err_irq;
+ }
Does this really need to be a threaded IRQ - the IRQ was just reading
from CPU registers as far as I remember?
+MODULE_AUTHOR(David Lambert dlamb...@ti.com);
+MODULE_DESCRIPTION(OMAP DMIC SoC Interface);
+MODULE_LICENSE(GPL);
Should have a MODULE_ALIAS too in case it gets built modular.
--
David Lambert
OMAP™ Multimedia
214-567-5692
--
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[PATCH] arm: omap4: panda: remove usb_nop_xceiv_register(v1)
From: Ming Lei tom.leim...@gmail.com Panda uses both twl6030 otg phy(vbus, id) and internal phy(data lines, DP/DM), so removes usb_nop_xceiv_register to make twl6030 otg driver working since current otg code only supports one global transceiver. Otherwise, musb doesn't work without the remove. Reviewd-by: Felipe Balbi ba...@ti.com Signed-off-by: Ming Lei tom.leim...@gmail.com --- v1: fix commit log pointed by Felipe. --- arch/arm/mach-omap2/board-omap4panda.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 1ecd0a6..802ae20 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -374,8 +374,6 @@ static void __init omap4_panda_init(void) platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); - /* OMAP4 Panda uses internal transceiver so register nop transceiver */ - usb_nop_xceiv_register(); omap4_ehci_init(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) -- 1.7.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] ASoC: DMIC: Adding the OMAP DMIC driver
On Wed, Jan 05, 2011 at 07:56:13AM -0600, Lambert, David wrote: On Tue, Dec 28, 2010 at 8:18 AM, Mark Brown A comment explaining why we don't actually do anything with the request would be helpful. Given that we're ignoring the event it'd seem better to just leave it masked and not take the interrupt in the first place. Since the IRQ handler isn't really doing anything in this driver, would it better to just not have one? Possibly, if the hardware doesn't care. + dmic-clk_freq = freq; + break; + default: + dev_err(dai-dev, clk freq not supported %d\n, freq); + ret = -EINVAL; + goto err_freq; + } Can't you ask the parent clock what rate it's set to? Didn't really think there was a need for that on the audio driver. There are clock API's available to query that already. That's my point - you're requiring that the user pass in the rate rather than querying the clock API. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
OMAP4 panda gets stuck during reboot
Hi, It seems like there's a bug on flush_pmd_entry() for multicore ARM CPUs. I'm testing 2.6.37 with pandaboard and when running reboot it gets stuck on: asm(mcrp15, 0, %0, c7, c10, 1 @ flush_pmd : : r (pmd) : cc); I added a few printk()s around the code to find the specific spot where the reset sequence was getting stuck and here's the output: [ 112.497253] === kernel_restart (line 312) [ 112.501525] === kernel_restart_prepare (line 294) [ 112.506561] === device_shutdown (line 1661) [ 112.511871] === device_shutdown (line 1692) [ 112.516387] === sysdev_shutdown (line 323) [ 112.520782] === sysdev_shutdown (line 349) [ 112.525146] === kernel_restart_prepare (line 299) [ 112.530181] Restarting system. [ 112.533386] === machine_restart (line 254) [ 112.537750] === machine_shutdown (line 232) [ 112.542236] === machine_shutdown (line 236) [ 112.546722] === arm_machine_restart (line 96) [ 112.551391] === setup_mm_for_reboot (line 1059) [ 112.556213] === setup_mm_for_reboot (line 1066) [ 112.561035] === setup_mm_for_reboot (line 1071) [ 112.565856] === flush_pmd_entry (line 522) What could it be ? Any more debugging I could do to help ? -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] arm: omap4: panda: remove usb_nop_xceiv_register
Hi, On Wed, Jan 05, 2011 at 09:40:19PM +0800, Ming Lei wrote: Reviewed-by: Felipe Balbi ba...@ti.com This is ok, but can only go after 2.6.38 merge window. There are patches to add support for internal PHY. Ideally we would actually register both PHYs and it would work. They would have different capabilities, though. The current otg only supports one global transceiver, so we have to remove the nop on Panda. Yes, of course. I just pointed out your commit log is wrong and that ideally we would fix this limitation. Ideally we would we have some sort of framework for transceivers where we could add several of them. -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: OMAP4 panda gets stuck during reboot
-Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Felipe Balbi Sent: Wednesday, January 05, 2011 7:38 PM To: Russell King; Tony Lindgren Cc: Linux ARM Kernel Mailing List; Linux OMAP Mailing List Subject: OMAP4 panda gets stuck during reboot Hi, It seems like there's a bug on flush_pmd_entry() for multicore ARM CPUs. I'm testing 2.6.37 with pandaboard and when running reboot it gets stuck on: asm(mcr p15, 0, %0, c7, c10, 1 @ flush_pmd : : r (pmd) : cc); I added a few printk()s around the code to find the specific spot where the reset sequence was getting stuck and here's the output: [ 112.497253] === kernel_restart (line 312) [ 112.501525] === kernel_restart_prepare (line 294) [ 112.506561] === device_shutdown (line 1661) [ 112.511871] === device_shutdown (line 1692) [ 112.516387] === sysdev_shutdown (line 323) [ 112.520782] === sysdev_shutdown (line 349) [ 112.525146] === kernel_restart_prepare (line 299) [ 112.530181] Restarting system. [ 112.533386] === machine_restart (line 254) [ 112.537750] === machine_shutdown (line 232) [ 112.542236] === machine_shutdown (line 236) [ 112.546722] === arm_machine_restart (line 96) [ 112.551391] === setup_mm_for_reboot (line 1059) [ 112.556213] === setup_mm_for_reboot (line 1066) [ 112.561035] === setup_mm_for_reboot (line 1071) [ 112.565856] === flush_pmd_entry (line 522) What could it be ? Any more debugging I could do to help ? This is known and seems to OMAP specific issue. Test patch and relevant thread is here. http://www.spinics.net/lists/arm-kernel/msg103493.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP4 panda gets stuck during reboot
Hi, On Wed, Jan 05, 2011 at 07:44:31PM +0530, Santosh Shilimkar wrote: What could it be ? Any more debugging I could do to help ? This is known and seems to OMAP specific issue. Test patch and Doesn't look like omap-specific from patch description. Looks like like CPU1 is turned off and the instruction to flush PMD entry fails. Could it be that all ARM SMPs are affected ? -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: OMAP4 panda gets stuck during reboot
-Original Message- From: Felipe Balbi [mailto:ba...@ti.com] Sent: Wednesday, January 05, 2011 7:48 PM To: Santosh Shilimkar Cc: ba...@ti.com; Russell King; Tony Lindgren; Linux ARM Kernel Mailing List; Linux OMAP Mailing List Subject: Re: OMAP4 panda gets stuck during reboot Hi, On Wed, Jan 05, 2011 at 07:44:31PM +0530, Santosh Shilimkar wrote: What could it be ? Any more debugging I could do to help ? This is known and seems to OMAP specific issue. Test patch and Doesn't look like omap-specific from patch description. Looks like like CPU1 is turned off and the instruction to flush PMD entry fails. Could it be that all ARM SMPs are affected ? Thread is broken some how. There were more emails on this one... Russell confirmed that he don't see the issue on his A9 Versatile platform and no one else complained except OMAP. Copy pasting some last updates.. -Original Message- From: Catalin Marinas [mailto:catalin.mari...@arm.com] Sent: Wednesday, November 10, 2010 7:35 PM To: Russell King - ARM Linux Cc: Shilimkar, Santosh; linux-arm-ker...@lists.infradead.org; Gadiyar, Anand Subject: Re: [PATCH] ARM: Temporary fix for broken arch reboot On Wed, 2010-11-10 at 10:06 +, Russell King - ARM Linux wrote: On Wed, Nov 10, 2010 at 11:25:21AM +0530, Shilimkar, Santosh wrote: -Original Message- From: Catalin Marinas [mailto:catalin.mari...@arm.com] Sent: Tuesday, November 09, 2010 10:08 PM To: Russell King - ARM Linux Cc: Shilimkar, Santosh; linux-arm-ker...@lists.infradead.org; Gadiyar, Anand Subject: Re: [PATCH] ARM: Temporary fix for broken arch reboot On Tue, 2010-11-09 at 13:18 +, Russell King - ARM Linux wrote: On Tue, Nov 09, 2010 at 06:40:39PM +0530, Shilimkar, Santosh wrote: With commit 3d3f78d752bf, reboot seems to broken on ARM machines. CPU dies while doing flush_pmd_entry() as part of setup_mm_for_reboot() What do you mean by 'dies'? Can you still connect with a debugger or it got to some weird state? It goes to some weird state. Basically the emulation connection dies, and debugger gets disconnected. I know this is not the fix but intention is to report the issue and also provide temporary fix till it get fixed correctly So you're now rebooting with the secondary CPUs still running. I guess that the secondary CPUs end up crashing and don't restart. I think more the question is why the CP15 cache clean/flush is hanging with the other CPUs taken down. All the other CPUs will be doing is sitting in a loop doing nothing. I can't think of anything. Did the other CPUs print 'stopping'? No it doesn't not print anything. The processing of the IPI is asynchronous to the CPU which is rebooting continuing - which means that if there is some kind of bus lockup, you won't get anything from any of the CPUs. The printing only happens for SYSTEM_BOOTING or SYSTEM_RUNNING. I suspect in this case we have SYSTEM_RESTARTING and the condition in ipi_cpu_stop() is false, therefore no printing. It may be worth putting some printks outside the 'if' to see whether the secondary CPUs get there. While doing some experiments on this issue, one interesting observation I made. Looks like there is race between two Cores which makes system behave badly in reboot path. Just adding a delay in the ipi_cpu_stop() makes the reboot work as well diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 8c19595..f7dadbf 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -526,6 +526,8 @@ static void ipi_cpu_stop(unsigned int cpu) spin_unlock(stop_lock); } + udelay(500); + set_cpu_online(cpu, false); local_fiq_disable(); -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] OMAP: clockdomain: Arch specific funcs to handle deps
Define the following architecture specific funtions for omap2/3
.clkdm_add_wkdep
.clkdm_del_wkdep
.clkdm_read_wkdep
.clkdm_clear_all_wkdeps
.clkdm_add_sleepdep
.clkdm_del_sleepdep
.clkdm_read_sleepdep
.clkdm_clear_all_sleepdeps
Convert the platform-independent framework to call these functions.
With this also move the clkdm lookups for all wkdep_srcs and
sleepdep_srcs at clkdm_init.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/clockdomain.c| 80 ++-
arch/arm/mach-omap2/clockdomain.h|2 +
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 113 ++
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |2 +-
5 files changed, 150 insertions(+), 49 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4ab82f6..d28db0a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -102,8 +102,10 @@ obj-$(CONFIG_ARCH_OMAP4) +=
$(powerdomain-common) \
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
+ clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
+ clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomains44xx_data.o
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index 3e40184..c32480c 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -308,6 +308,7 @@ void clkdm_init(struct clockdomain **clkdms,
struct clockdomain **c = NULL;
struct clockdomain *clkdm;
struct clkdm_autodep *autodep = NULL;
+ struct clkdm_dep *cd;
if (!custom_funcs)
WARN(1, No custom clkdm functions registered\n);
@@ -333,7 +334,18 @@ void clkdm_init(struct clockdomain **clkdms,
else if (clkdm-flags CLKDM_CAN_DISABLE_AUTO)
omap2_clkdm_deny_idle(clkdm);
+ for (cd = clkdm-wkdep_srcs; cd cd-clkdm_name; cd++) {
+ if (!omap_chip_is(cd-omap_chip))
+ continue;
+ cd-clkdm = _clkdm_lookup(cd-clkdm_name);
+ }
clkdm_clear_all_wkdeps(clkdm);
+
+ for (cd = clkdm-sleepdep_srcs; cd cd-clkdm_name; cd++) {
+ if (!omap_chip_is(cd-omap_chip))
+ continue;
+ cd-clkdm = _clkdm_lookup(cd-clkdm_name);
+ }
clkdm_clear_all_sleepdeps(clkdm);
}
}
@@ -445,8 +457,8 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
pr_debug(clockdomain: hardware will wake up %s when %s wakes
up\n, clkdm1-name, clkdm2-name);
- omap2_prm_set_mod_reg_bits((1 clkdm2-dep_bit),
-clkdm1-pwrdm.ptr-prcm_offs, PM_WKDEP);
+ if (arch_clkdm arch_clkdm-clkdm_add_wkdep)
+ arch_clkdm-clkdm_add_wkdep(clkdm1, clkdm2);
}
return 0;
@@ -480,8 +492,8 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
pr_debug(clockdomain: hardware will no longer wake up %s
after %s wakes up\n, clkdm1-name, clkdm2-name);
- omap2_prm_clear_mod_reg_bits((1 clkdm2-dep_bit),
- clkdm1-pwrdm.ptr-prcm_offs, PM_WKDEP);
+ if (arch_clkdm arch_clkdm-clkdm_del_wkdep)
+ arch_clkdm-clkdm_del_wkdep(clkdm1, clkdm2);
}
return 0;
@@ -516,8 +528,10 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
}
/* XXX It's faster to return the atomic wkdep_usecount */
- return omap2_prm_read_mod_bits_shift(clkdm1-pwrdm.ptr-prcm_offs,
PM_WKDEP,
- (1 clkdm2-dep_bit));
+ if (arch_clkdm arch_clkdm-clkdm_read_wkdep)
+ return arch_clkdm-clkdm_read_wkdep(clkdm1, clkdm2);
+
+ return -EINVAL;
}
/**
@@ -532,25 +546,11 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
*/
int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
{
- struct clkdm_dep *cd;
- u32 mask = 0;
-
if (!clkdm)
return -EINVAL;
- for (cd = clkdm-wkdep_srcs; cd cd-clkdm_name; cd++) {
- if (!omap_chip_is(cd-omap_chip))
- continue;
-
-
[PATCH 5/5] OMAP: clockdomain: Arch specific funcs for clkdm_clk_enable/disable
Define the following architecture specific funtions for omap2/3/4
.clkdm_clk_enable
.clkdm_clk_disable
Convert the platform-independent framework to call these functions.
Also rename the api's by removing the omap2_ preamble.
Hence call omap2_clkdm_k_enable as clkdm_clk_enable and
omap2_clkdm_clk_disable as clkdm_clk_disable.a
Remove unused functions (_enable/_disable_hwsup) and unsed
headers from clockdomain.c file.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/clock.c|6 +-
arch/arm/mach-omap2/clockdomain.c | 125 ++--
arch/arm/mach-omap2/clockdomain.h |4 +-
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 69 +++
arch/arm/mach-omap2/clockdomain44xx.c | 28 ++
5 files changed, 110 insertions(+), 122 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 2a2f152..e9625fc 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -264,7 +264,7 @@ void omap2_clk_disable(struct clk *clk)
clk-ops-disable(clk);
if (clk-clkdm)
- omap2_clkdm_clk_disable(clk-clkdm, clk);
+ clkdm_clk_disable(clk-clkdm, clk);
if (clk-parent)
omap2_clk_disable(clk-parent);
@@ -304,7 +304,7 @@ int omap2_clk_enable(struct clk *clk)
}
if (clk-clkdm) {
- ret = omap2_clkdm_clk_enable(clk-clkdm, clk);
+ ret = clkdm_clk_enable(clk-clkdm, clk);
if (ret) {
WARN(1, clock: %s: could not enable clockdomain %s:
%d\n, clk-name, clk-clkdm-name, ret);
@@ -322,7 +322,7 @@ int omap2_clk_enable(struct clk *clk)
oce_err3:
if (clk-clkdm)
- omap2_clkdm_clk_disable(clk-clkdm, clk);
+ clkdm_clk_disable(clk-clkdm, clk);
oce_err2:
if (clk-parent)
omap2_clk_disable(clk-parent);
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index 1dafbb1..767579d 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -26,17 +26,8 @@
#include linux/bitops.h
-#include prm2xxx_3xxx.h
-#include prm-regbits-24xx.h
-#include cm2xxx_3xxx.h
-#include cm-regbits-24xx.h
-#include cminst44xx.h
-#include prcm44xx.h
-
#include plat/clock.h
-#include powerdomain.h
#include clockdomain.h
-#include plat/prcm.h
/* clkdm_list contains all registered struct clockdomains */
static LIST_HEAD(clkdm_list);
@@ -235,58 +226,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
}
}
-/**
- * _enable_hwsup - place a clockdomain into hardware-supervised idle
- * @clkdm: struct clockdomain *
- *
- * Place the clockdomain into hardware-supervised idle mode. No return
- * value.
- *
- * XXX Should this return an error if the clockdomain does not support
- * hardware-supervised idle mode?
- */
-static void _enable_hwsup(struct clockdomain *clkdm)
-{
- if (cpu_is_omap24xx())
- omap2xxx_cm_clkdm_enable_hwsup(clkdm-pwrdm.ptr-prcm_offs,
- clkdm-clktrctrl_mask);
- else if (cpu_is_omap34xx())
- omap3xxx_cm_clkdm_enable_hwsup(clkdm-pwrdm.ptr-prcm_offs,
- clkdm-clktrctrl_mask);
- else if (cpu_is_omap44xx())
- return omap4_cminst_clkdm_enable_hwsup(clkdm-prcm_partition,
- clkdm-cm_inst,
- clkdm-clkdm_offs);
- else
- BUG();
-}
-
-/**
- * _disable_hwsup - place a clockdomain into software-supervised idle
- * @clkdm: struct clockdomain *
- *
- * Place the clockdomain @clkdm into software-supervised idle mode.
- * No return value.
- *
- * XXX Should this return an error if the clockdomain does not support
- * software-supervised idle mode?
- */
-static void _disable_hwsup(struct clockdomain *clkdm)
-{
- if (cpu_is_omap24xx())
- omap2xxx_cm_clkdm_disable_hwsup(clkdm-pwrdm.ptr-prcm_offs,
- clkdm-clktrctrl_mask);
- else if (cpu_is_omap34xx())
- omap3xxx_cm_clkdm_disable_hwsup(clkdm-pwrdm.ptr-prcm_offs,
- clkdm-clktrctrl_mask);
- else if (cpu_is_omap44xx())
- return omap4_cminst_clkdm_disable_hwsup(clkdm-prcm_partition,
- clkdm-cm_inst,
- clkdm-clkdm_offs);
- else
- BUG();
-}
-
/* Public functions */
/**
@@ -820,7 +759,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
/* Clockdomain-to-clock framework interface code */
/**
- * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
+ * clkdm_clk_enable - add an enabled downstream clock to this
[PATCH 0/5] Clockdomain split series
This patch series is an effort to split the clockdomain framework into platform independent and platform specific parts as was done for the powerdomain framework. This certainlly helps remove the various cpu_is_* checks which exist today in the framework and makes the code more maintainable and readable. The series is boot tested on OMAP2430/3430/4430SDP platforms. Also on OMAP3430SDP, OFF mode in suspend path is validated using the omap3_pm_defconfig. This series is based on latest linux-omap master and can be found here git://gitorious.org/omap-pm/linux.git clockdomain-split Rajendra Nayak (5): OMAP: clockdomain: Infrastructure to put arch specific code OMAP: clockdomain: Arch specific funcs to handle deps OMAP: clockdomain: Arch specific funcs for sleep/wakeup of clkdm OMAP: clockdomain: Arch specific funcs for hwsup control of clkdm OMAP: clockdomain: Arch specific funcs for clkdm_clk_enable/disable arch/arm/mach-omap2/Makefile |3 + arch/arm/mach-omap2/clock.c |6 +- arch/arm/mach-omap2/clockdomain.c| 313 +- arch/arm/mach-omap2/clockdomain.h| 58 - arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 268 ++ arch/arm/mach-omap2/clockdomain44xx.c| 77 ++ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |9 +- arch/arm/mach-omap2/clockdomains44xx_data.c |2 +- arch/arm/mach-omap2/cpuidle34xx.c|4 +- arch/arm/mach-omap2/io.c |6 +- arch/arm/mach-omap2/pm.c |6 +- arch/arm/mach-omap2/pm24xx.c |8 +- arch/arm/mach-omap2/pm34xx.c |6 +- 13 files changed, 494 insertions(+), 272 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c create mode 100644 arch/arm/mach-omap2/clockdomain44xx.c -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] OMAP: clockdomain: Arch specific funcs for hwsup control of clkdm
Define the following architecture specific funtions for omap2/3/4
.clkdm_allow_idle
.clkdm_deny_idle
Convert the platform-independent framework to call these functions.
Also rename the api's by removing the omap2_ preamble.
Hence call omap2_clkdm_allow_idle as clkdm_allow_idle and
omap2_clkdm_deny_idle as clkdm_deny_idle.
Make the _clkdm_add_autodeps and _clkdm_del_autodeps as non-static
so they can be accessed from OMAP2/3 platform specific code.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/clockdomain.c | 46 +++
arch/arm/mach-omap2/clockdomain.h |6 ++-
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 40
arch/arm/mach-omap2/clockdomain44xx.c | 14
arch/arm/mach-omap2/cpuidle34xx.c |4 +-
arch/arm/mach-omap2/pm.c |2 +-
arch/arm/mach-omap2/pm24xx.c |2 +-
arch/arm/mach-omap2/pm34xx.c |4 +-
8 files changed, 76 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index ce55279..1dafbb1 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -178,7 +178,7 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
-static void _clkdm_add_autodeps(struct clockdomain *clkdm)
+void _clkdm_add_autodeps(struct clockdomain *clkdm)
{
struct clkdm_autodep *autodep;
@@ -212,7 +212,7 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
-static void _clkdm_del_autodeps(struct clockdomain *clkdm)
+void _clkdm_del_autodeps(struct clockdomain *clkdm)
{
struct clkdm_autodep *autodep;
@@ -332,7 +332,7 @@ void clkdm_init(struct clockdomain **clkdms,
if (clkdm-flags CLKDM_CAN_FORCE_WAKEUP)
clkdm_wakeup(clkdm);
else if (clkdm-flags CLKDM_CAN_DISABLE_AUTO)
- omap2_clkdm_deny_idle(clkdm);
+ clkdm_deny_idle(clkdm);
for (cd = clkdm-wkdep_srcs; cd cd-clkdm_name; cd++) {
if (!omap_chip_is(cd-omap_chip))
@@ -760,7 +760,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
}
/**
- * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
+ * clkdm_allow_idle - enable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Allow the hardware to automatically switch the clockdomain @clkdm into
@@ -769,7 +769,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
* framework, wkdep/sleepdep autodependencies are added; this is so
* device drivers can read and write to the device. No return value.
*/
-void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
+void clkdm_allow_idle(struct clockdomain *clkdm)
{
if (!clkdm)
return;
@@ -783,25 +783,14 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
pr_debug(clockdomain: enabling automatic idle transitions for %s\n,
clkdm-name);
- /*
-* XXX This should be removed once TI adds wakeup/sleep
-* dependency code and data for OMAP4.
-*/
- if (cpu_is_omap44xx()) {
- WARN_ONCE(1, clockdomain: OMAP4 wakeup/sleep dependency
- support is not yet implemented\n);
- } else {
- if (atomic_read(clkdm-usecount) 0)
- _clkdm_add_autodeps(clkdm);
+ if (arch_clkdm arch_clkdm-clkdm_allow_idle) {
+ arch_clkdm-clkdm_allow_idle(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
}
-
- _enable_hwsup(clkdm);
-
- pwrdm_clkdm_state_switch(clkdm);
}
/**
- * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
+ * clkdm_deny_idle - disable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Prevent the hardware from automatically switching the clockdomain
@@ -809,7 +798,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
* downstream clocks enabled in the clock framework, wkdep/sleepdep
* autodependencies are removed. No return value.
*/
-void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
+void clkdm_deny_idle(struct clockdomain *clkdm)
{
if (!clkdm)
return;
@@ -823,19 +812,8 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
pr_debug(clockdomain: disabling automatic idle transitions for %s\n,
clkdm-name);
- _disable_hwsup(clkdm);
-
- /*
-* XXX This should be removed once TI adds wakeup/sleep
-* dependency code and data for OMAP4.
-*/
- if (cpu_is_omap44xx()) {
- WARN_ONCE(1, clockdomain: OMAP4 wakeup/sleep dependency
- support is not yet implemented\n);
[PATCH 1/5] OMAP: clockdomain: Infrastructure to put arch specific code
Put infrastructure in place, so arch specific func pointers
can be hooked up to the platform-independent part of the
framework.
This is in preparation of splitting the clockdomain framework into
platform-independent part (for all omaps) and platform-specific
parts.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/clockdomain.c| 10 +-
arch/arm/mach-omap2/clockdomain.h| 37 +-
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |2 +-
arch/arm/mach-omap2/clockdomains44xx_data.c |2 +-
4 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index e20b986..3e40184 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -44,6 +44,7 @@ static LIST_HEAD(clkdm_list);
/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
static struct clkdm_autodep *autodeps;
+static struct clkdm_ops *arch_clkdm;
/* Private functions */
@@ -292,6 +293,7 @@ static void _disable_hwsup(struct clockdomain *clkdm)
* clkdm_init - set up the clockdomain layer
* @clkdms: optional pointer to an array of clockdomains to register
* @init_autodeps: optional pointer to an array of autodeps to register
+ * @custom_funcs: func pointers for arch specfic implementations
*
* Set up internal state. If a pointer to an array of clockdomains
* @clkdms was supplied, loop through the list of clockdomains,
@@ -300,12 +302,18 @@ static void _disable_hwsup(struct clockdomain *clkdm)
* @init_autodeps was provided, register those. No return value.
*/
void clkdm_init(struct clockdomain **clkdms,
- struct clkdm_autodep *init_autodeps)
+ struct clkdm_autodep *init_autodeps,
+ struct clkdm_ops *custom_funcs)
{
struct clockdomain **c = NULL;
struct clockdomain *clkdm;
struct clkdm_autodep *autodep = NULL;
+ if (!custom_funcs)
+ WARN(1, No custom clkdm functions registered\n);
+ else
+ arch_clkdm = custom_funcs;
+
if (clkdms)
for (c = clkdms; *c; c++)
_clkdm_register(*c);
diff --git a/arch/arm/mach-omap2/clockdomain.h
b/arch/arm/mach-omap2/clockdomain.h
index de3faa2..346efa2 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -118,7 +118,42 @@ struct clockdomain {
struct list_head node;
};
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
+/**
+ * struct clkdm_ops - Arch specfic function implementations
+ * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
+ * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
+ * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
+ * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
+ * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
+ * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
+ * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
+ * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk
domain
+ * @clkdm_sleep: Force a clockdomain to sleep
+ * @clkdm_wakeup: Force a clockdomain to wakeup
+ * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
+ * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
+ * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
+ * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
+ */
+struct clkdm_ops {
+ void(*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct
clockdomain *clkdm2);
+ void(*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct
clockdomain *clkdm2);
+ int (*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct
clockdomain *clkdm2);
+ void(*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
+ void(*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct
clockdomain *clkdm2);
+ void(*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct
clockdomain *clkdm2);
+ int (*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct
clockdomain *clkdm2);
+ void(*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
+ int (*clkdm_sleep)(struct clockdomain *clkdm);
+ int (*clkdm_wakeup)(struct clockdomain *clkdm);
+ void(*clkdm_allow_idle)(struct clockdomain *clkdm);
+ void(*clkdm_deny_idle)(struct clockdomain *clkdm);
+ int (*clkdm_clk_enable)(struct clockdomain *clkdm);
+ int (*clkdm_clk_disable)(struct clockdomain *clkdm);
+};
+
+void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
+ struct clkdm_ops *custom_funcs);
struct clockdomain *clkdm_lookup(const char *name);
int clkdm_for_each(int (*fn)(struct
[PATCH 3/5] OMAP: clockdomain: Arch specific funcs for sleep/wakeup of clkdm
Define the following architecture specific funtions for omap2/3/4
.clkdm_sleep
.clkdm_wakeup
Convert the platform-independent framework to call these functions.
Also rename the api's by removing the omap2_ preamble.
Hence call omap2_clkdm_wakeup as clkdm_wakeup and
omap2_clkdm_sleep as clkdm_sleep.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/Makefile |1 +
arch/arm/mach-omap2/clockdomain.c| 56 -
arch/arm/mach-omap2/clockdomain.h|9 ++-
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 46 ++
arch/arm/mach-omap2/clockdomain44xx.c| 35 +
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |7 ++-
arch/arm/mach-omap2/clockdomains44xx_data.c |2 +-
arch/arm/mach-omap2/io.c |6 +-
arch/arm/mach-omap2/pm.c |4 +-
arch/arm/mach-omap2/pm24xx.c |6 +-
arch/arm/mach-omap2/pm34xx.c |2 +-
11 files changed, 115 insertions(+), 59 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomain44xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d28db0a..9990d88 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_ARCH_OMAP3)+= clockdomain.o \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
+ clockdomain44xx.o \
clockdomains44xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index c32480c..ce55279 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -330,7 +330,7 @@ void clkdm_init(struct clockdomain **clkdms,
*/
list_for_each_entry(clkdm, clkdm_list, node) {
if (clkdm-flags CLKDM_CAN_FORCE_WAKEUP)
- omap2_clkdm_wakeup(clkdm);
+ clkdm_wakeup(clkdm);
else if (clkdm-flags CLKDM_CAN_DISABLE_AUTO)
omap2_clkdm_deny_idle(clkdm);
@@ -704,7 +704,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
}
/**
- * omap2_clkdm_sleep - force clockdomain sleep transition
+ * clkdm_sleep - force clockdomain sleep transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a sleep transition on the specified
@@ -712,7 +712,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
* clockdomain does not support software-initiated sleep; 0 upon
* success.
*/
-int omap2_clkdm_sleep(struct clockdomain *clkdm)
+int clkdm_sleep(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
@@ -725,31 +725,14 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
pr_debug(clockdomain: forcing sleep on %s\n, clkdm-name);
- if (cpu_is_omap24xx()) {
-
- omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
- clkdm-pwrdm.ptr-prcm_offs, OMAP2_PM_PWSTCTRL);
-
- } else if (cpu_is_omap34xx()) {
-
- omap3xxx_cm_clkdm_force_sleep(clkdm-pwrdm.ptr-prcm_offs,
- clkdm-clktrctrl_mask);
-
- } else if (cpu_is_omap44xx()) {
-
- omap4_cminst_clkdm_force_sleep(clkdm-prcm_partition,
- clkdm-cm_inst,
- clkdm-clkdm_offs);
-
- } else {
- BUG();
- };
+ if (arch_clkdm arch_clkdm-clkdm_sleep)
+ return arch_clkdm-clkdm_sleep(clkdm);
return 0;
}
/**
- * omap2_clkdm_wakeup - force clockdomain wakeup transition
+ * clkdm_wakeup - force clockdomain wakeup transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a wakeup transition on the specified
@@ -757,7 +740,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
* clockdomain does not support software-controlled wakeup; 0 upon
* success.
*/
-int omap2_clkdm_wakeup(struct clockdomain *clkdm)
+int clkdm_wakeup(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
@@ -770,25 +753,8 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
pr_debug(clockdomain: forcing wakeup on %s\n, clkdm-name);
- if (cpu_is_omap24xx()) {
-
- omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
- clkdm-pwrdm.ptr-prcm_offs, OMAP2_PM_PWSTCTRL);
-
- } else if (cpu_is_omap34xx()) {
-
- omap3xxx_cm_clkdm_force_wakeup(clkdm-pwrdm.ptr-prcm_offs,
-
Re: OMAP4 panda gets stuck during reboot
Hi, On Wed, Jan 05, 2011 at 07:52:34PM +0530, Santosh Shilimkar wrote: On Wed, Jan 05, 2011 at 07:44:31PM +0530, Santosh Shilimkar wrote: What could it be ? Any more debugging I could do to help ? This is known and seems to OMAP specific issue. Test patch and Doesn't look like omap-specific from patch description. Looks like like CPU1 is turned off and the instruction to flush PMD entry fails. Could it be that all ARM SMPs are affected ? Thread is broken some how. There were more emails on this one... Russell confirmed that he don't see the issue on his A9 Versatile platform and no one else complained except OMAP. I see... Copy pasting some last updates.. Just finished reading the thread. Quite a problem on our side :-( -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 08/17] OMAP2,3: DSS2: Create platform_driver for each DSS HW IP
On Wed, 2011-01-05 at 18:55 +0530, ext Semwal, Sumit wrote: Hi Tomi, On Wed, Jan 5, 2011 at 4:57 PM, Tomi Valkeinen tomi.valkei...@nokia.com wrote: Hi, Does this even work if the DSS is compiled as a module? I have the recollection that a module can only have one initcall, and in this case omapdss would have many. [Sumit]: we haven't tried compiling DSS as module - I guess we will have to create each dss hw IP also as a separate module. Having them as separate modules makes things quite complex: then you need to be able to load only the modules you want (eg. leave dsi.ko out). But you'd also need to be able to load the dsi.ko later, after you decide to use a dsi based panel. This would of course be very neat, but I don't believe it's a very easy task. For the time being I would keep the DSS as one module, and if needed, try dividing it into separate modules later as a separate task. About making one common initcall, then I think we would need to have all platform_driver related functions either as global or in one file. is this a better option than having each as a separate module? I'd say it's better in the sense that a) it would work and b) it would be much easier than dividing DSS into multiple modules. I'd say have the platform driver code in their respective files (dsi.c, venc.c etc), and call dsi_init_platform_driver() from the probe function. That would keep the code clean if we decide to split the DSS into multiple modules. Also, shouldn't there be platform_driver_unregister() calls somewhere? You should definitely also test with DSS as a module =). Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 09/17] OMAP2,3: DSS2: Move clocks from core driver to dss driver
On Mon, 2011-01-03 at 18:21 +0530, ext Guruswamy Senthilvadivu wrote:
From: Senthilvadivu Guruswamy svad...@ti.com
clks are moved to dss platform driver. clk_get/put APIs use dss device
instead
of core platform device. So the device name is changed from omap_display to
omap_dss in 2420, 2430, 3xxx clock database files. Now teh core driver
omap_display only takes care of panel registration with the custom bus.
dss driver would take care of the clocks needed by DISPC, RFBI, DSI, VENC.
TODO: The clock content would be adapted to omap_hwmod in a seperate series.
Signed-off-by: Senthilvadivu Guruswamy svad...@ti.com
snip
@@ -508,14 +192,7 @@ static int omap_dss_probe(struct platform_device *pdev)
dss_init_overlay_managers(pdev);
dss_init_overlays(pdev);
- r = dss_get_clocks();
- if (r)
- goto err_clocks;
-
- dss_clk_enable_all_no_ctx();
-
- core.ctx_id = dss_get_ctx_id();
- DSSDBG(initial ctx id %u\n, core.ctx_id);
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M);
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
/* DISPC_CONTROL */
@@ -589,7 +266,7 @@ static int omap_dss_probe(struct platform_device *pdev)
pdata-default_device = dssdev;
}
- dss_clk_disable_all();
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M);
Why are the calls dss_clk_enable_all_no_ctx() and dss_clk_disable_all()
changed?
/* DSS HW IP initialisation */
static int omap_dsshw_probe(struct platform_device *pdev)
{
- return 0;
+ int r;
+
+ dss.pdev = pdev;
+
+ r = dss_get_clocks();
+ if (r)
+ goto err_clocks;
+
+ dss_clk_enable_all_no_ctx();
+
+ dss.ctx_id = dss_get_ctx_id();
+ DSSDBG(initial ctx id %u\n, dss.ctx_id);
+
+ dss_clk_disable_all_no_ctx();
I don't think clock enable/disable are needed here. dss_get_ctx_id()
should work fine without DSS's clocks.
Tomi
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OMAP DVFS rebase
Hello All, I have rebased the available DVFS code for OMAP tree against LO master which contains the latest OMAP voltage layer and smartreflex changes and hosted it at http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=shortlog;h=refs/heads/pm-dvfs head - pm-dvfs Regards Thara -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 12/17] OMAP2,3: DSS2: RFBI Move init,exit to driver
On Mon, 2011-01-03 at 18:21 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com For hwmod adaptation, move init exit methods from core.c to its driver probe, remove. pdev member has to be maintained by its own drivers. Replace printk with dev_dbg for boot time optimization. Changing the printk to dev_dbg is a separate change. This is also done in the following patches. When moving code, never do any changes to the code being moved if not absolutely necessary. The version printks could be all put to one patch, which would change them for all components. Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] OMAP: Cpufreq: Clean up to support multi omap builds
This is an attempt to clean up the omap
cpufreq driver so that it functions properly even with
multi omap builds. The main changes involve removal of
static CONFIG_ARCH_X checks and introducing relevant
cpu_is_X checks instead.
Signed-off-by: Thara Gopinath th...@ti.com
---
This patch is agains pm-cpufreq branch of Kevin Hilman's
OMAP PM tree as rest of the cpufreq driver patches for OMAP
are staged there. To test this patch i have applied it against
my dvfs tree (details of which are mentioned below) and tested
dvfs on OMAP3.
http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=summary
head - pm-improved-dvfs
arch/arm/plat-omap/cpu-omap.c | 113 +++--
1 files changed, 74 insertions(+), 39 deletions(-)
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 1c1b80b..a5f787f 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -29,25 +29,20 @@
#include mach/hardware.h
#include plat/clock.h
-#include asm/system.h
-
-#if defined(CONFIG_ARCH_OMAP3) !defined(CONFIG_OMAP_PM_NONE)
-#include plat/omap-pm.h
#include plat/common.h
-#endif
+#include plat/omap-pm.h
+#include asm/system.h
#define VERY_HI_RATE 9
-static struct cpufreq_frequency_table *freq_table;
-
-#ifdef CONFIG_ARCH_OMAP1
-#define MPU_CLKmpu
-#elif defined(CONFIG_ARCH_OMAP3)
-#define MPU_CLKarm_fck
-#else
-#define MPU_CLKvirt_prcm_set
-#endif
+#define OMAP1_MPU_CLK mpu
+#define OMAP2_MPU_CLK virt_prcm_set
+#define OMAP3_MPU_CLK dpll1_ck
+static void (*arch_cpu_init) (void);
+static int (*arch_cpu_target) (unsigned long freq);
+static struct cpufreq_frequency_table *freq_table;
+static char *mpu_clk_name;
static struct clk *mpu_clk;
/* TODO: Add support for SDRAM timing changes */
@@ -81,17 +76,32 @@ static unsigned int omap_getspeed(unsigned int cpu)
return rate;
}
+static int omap1_cpu_target(unsigned long freq)
+{
+ return clk_set_rate(mpu_clk, freq);
+}
+
+static int omap2plus_cpu_target(unsigned long freq)
+{
+#ifndef CONFIG_OMAP_PM_NONE
+ struct device *mpu_dev = omap2_get_mpuss_device();
+
+ if (!mpu_dev) {
+ pr_warning(%s: unable to get the mpu device\n, __func__);
+ return -EINVAL;
+ }
+
+ if (opp_find_freq_ceil(mpu_dev, freq))
+ omap_pm_cpu_set_freq(freq);
+#endif
+ return 0;
+}
+
static int omap_target(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
-#ifdef CONFIG_ARCH_OMAP1
struct cpufreq_freqs freqs;
-#endif
-#if defined(CONFIG_ARCH_OMAP3) !defined(CONFIG_OMAP_PM_NONE)
- unsigned long freq;
- struct device *mpu_dev = omap2_get_mpuss_device();
-#endif
int ret = 0;
/* Ensure desired rate is within allowed range. Some govenors
@@ -101,33 +111,49 @@ static int omap_target(struct cpufreq_policy *policy,
if (target_freq policy-max)
target_freq = policy-max;
-#ifdef CONFIG_ARCH_OMAP1
freqs.old = omap_getspeed(0);
freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
freqs.cpu = 0;
-
if (freqs.old == freqs.new)
return ret;
+
cpufreq_notify_transition(freqs, CPUFREQ_PRECHANGE);
+
#ifdef CONFIG_CPU_FREQ_DEBUG
printk(KERN_DEBUG cpufreq-omap: transition: %u -- %u\n,
freqs.old, freqs.new);
#endif
- ret = clk_set_rate(mpu_clk, freqs.new * 1000);
- cpufreq_notify_transition(freqs, CPUFREQ_POSTCHANGE);
-#elif defined(CONFIG_ARCH_OMAP3) !defined(CONFIG_OMAP_PM_NONE)
- freq = target_freq * 1000;
- if (opp_find_freq_ceil(mpu_dev, freq))
- omap_pm_cpu_set_freq(freq);
-#endif
+
+ ret = arch_cpu_target(freqs.new * 1000);
+
+ if (!ret)
+ cpufreq_notify_transition(freqs, CPUFREQ_POSTCHANGE);
+
return ret;
}
+static void omap1_cpu_init(void)
+{
+ clk_init_cpufreq_table(freq_table);
+}
+
+static void omap3_cpu_init(void)
+{
+ struct device *mpu_dev = omap2_get_mpuss_device();
+
+ if (!mpu_dev) {
+ pr_warning(%s: unable to get the mpu device\n, __func__);
+ return;
+ }
+
+ opp_init_cpufreq_table(mpu_dev, freq_table);
+}
+
static int __init omap_cpu_init(struct cpufreq_policy *policy)
{
int result = 0;
- mpu_clk = clk_get(NULL, MPU_CLK);
+ mpu_clk = clk_get(NULL, mpu_clk_name);
if (IS_ERR(mpu_clk))
return PTR_ERR(mpu_clk);
@@ -136,13 +162,7 @@ static int __init omap_cpu_init(struct cpufreq_policy
*policy)
policy-cur = policy-min = policy-max = omap_getspeed(0);
- if (!cpu_is_omap34xx()) {
- clk_init_cpufreq_table(freq_table);
- } else {
- struct device *mpu_dev = omap2_get_mpuss_device();
-
-
[PATCH] arm: mach-omap2: mux: fix buffer overrun
memcpy() copies 8 bytes too much (omap_mux_entry vs. omap_mux). Correct
by replacing memcpy() with struct assignment, which is safer.
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
---
arch/arm/mach-omap2/mux.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 17bd639..df8d2f2 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -893,7 +893,7 @@ static struct omap_mux * __init omap_mux_list_add(
return NULL;
m = entry-mux;
- memcpy(m, src, sizeof(struct omap_mux_entry));
+ entry-mux = *src;
#ifdef CONFIG_OMAP_MUX
if (omap_mux_copy_names(src, m)) {
--
1.5.6.5
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Re: [PATCH] OMAP: GPIO: fix _set_gpio_triggering() for OMAP2+
Hi Charu, Varadarajan, Charulatha ch...@ti.com writes: On Wed, Jan 5, 2011 at 04:47, Tony Lindgren t...@atomide.com wrote: * Kevin Hilman khil...@ti.com [110104 14:45]: On Tue, 2011-01-04 at 09:52 -0800, Kevin Hilman wrote: Mika Westerberg ext-mika.1.westerb...@nokia.com writes: In case on OMAP2+ we call set_24xx_gpio_triggering() instead of updating reg and l values. However, at the end of the function we perform a write: __raw_writel(l, reg); So on OMAP2+ we end up writing 0 to the bank-base which is not correct (typically this points to GPIO_REVISION register). Fix this by returning immediately after call to set_24xx_gpio_triggering(). Signed-off-by: Mika Westerberg ext-mika.1.westerb...@nokia.com Acked-by: Kevin Hilman khil...@ti.com Tony, this should be added to omap-for-linus as it fixes a problem in the recently merged GPIO omap_device/hwmod conversion. One clarification - This problem should be existing since the following commit 92105bb70634abacc08bbe12bf6f888fbd7dad38 which was introduced on Sep 7, 2005 FYI, this part of the code remained untouched during GPIO omap_device/hwmod conversion. OK, thanks for the clarification. I had assumed it was recent changes since the patch didn't apply cleanly, but am glad to be wrong. :) Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] arm: omap: gpio: don't access irq_desc array directly
Felipe Balbi ba...@ti.com writes:
On Tue, Jan 04, 2011 at 04:24:58PM -0800, Kevin Hilman wrote:
Felipe Balbi ba...@ti.com writes:
Instead of accessing the irq_desc array directly
we can use irq_to_desc(irq). That will allow us to,
if wanted, select SPARSE_IRQ and irq_descs will be
added to a radix tree, instead of a array.
Signed-off-by: Felipe Balbi ba...@ti.com
Can you refresh this one against Tony's omap-for-linus branch. The GPIO
omap_device/hwmod conversion changed things around a bit and this patch
doesn't apply.
After that, you can send separately, and I'll queue this one along with
some other GPIO core fixes for the 2.6.38-rc series after -rc1 comes
out.
Sure, it's attached to this mail.
Thanks. Queueing for 2.6.38-rc
Kevin
From 8d216ccac14e4eebf259d5b40ed2d239248710e1 Mon Sep 17 00:00:00 2001
From: Felipe Balbi ba...@ti.com
Date: Wed, 5 Jan 2011 08:46:18 +0200
Subject: [PATCH] arm: omap: gpio: don't access irq_desc array directly
Organization: Texas Instruments\n
Instead of accessing the irq_desc array directly
we can use irq_to_desc(irq). That will allow us to,
if wanted, select SPARSE_IRQ and irq_descs will be
added to a radix tree, instead of a array.
Signed-off-by: Felipe Balbi ba...@ti.com
---
arch/arm/plat-omap/gpio.c | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 1f98e0b..197a6c0 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -756,8 +756,10 @@ static int gpio_irq_type(unsigned irq, unsigned type)
spin_lock_irqsave(bank-lock, flags);
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
if (retval == 0) {
- irq_desc[irq].status = ~IRQ_TYPE_SENSE_MASK;
- irq_desc[irq].status |= type;
+ struct irq_desc *d = irq_to_desc(irq);
+
+ d-status = ~IRQ_TYPE_SENSE_MASK;
+ d-status |= type;
}
spin_unlock_irqrestore(bank-lock, flags);
@@ -1671,7 +1673,9 @@ static void __init omap_gpio_chip_init(struct gpio_bank
*bank)
for (j = bank-virtual_irq_start;
j bank-virtual_irq_start + bank_width; j++) {
- lockdep_set_class(irq_desc[j].lock, gpio_lock_class);
+ struct irq_desc *d = irq_to_desc(j);
+
+ lockdep_set_class(d-lock, gpio_lock_class);
set_irq_chip_data(j, bank);
if (bank_is_mpuio(bank))
set_irq_chip(j, mpuio_irq_chip);
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Re: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex
Gopinath, Thara th...@ti.com writes: -Original Message- From: Hilman, Kevin Sent: Wednesday, January 05, 2011 4:18 AM To: Gopinath, Thara Cc: linux-omap@vger.kernel.org; p...@pwsan.com; Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand; Menon, Nishanth Subject: Re: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex Thara Gopinath th...@ti.com writes: The smartreflex bit on twl4030 needs to be enabled by default irrespective of whether smartreflex module is enabled on the OMAP side or not. This is because without this bit enabled the voltage scaling through vp forceupdate does not function properly on OMAP3. Based on Nishanth's comments, the abofe statements need a little more justification. What is probably needed is some default setting (possibly this one) but with the possibility of board code to disable this if needed. Yes. If we need to support the other means of voltage scaling, we definitely need to override this bit from board files. I am not so convinced that we need to support them though. IMHO, this patch can still go in with change in the comment and if needed, there can be another patch with an API in omap_twl.c allowing overriding/ enabling-disabling of sr - i2c bit on the T2 side. I'm OK with this. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] omap2plus: Trivial build break fixes
Santosh Shilimkar santosh.shilim...@ti.com writes: [...] Minor nit in your git-send-email config. Can you add the following to your ~/.gitconfig, or update to newer git where this is now the default: [sendemail] chainreplyto = false This will make all patches a reply to PATCH 0 instead of to the previous patch. Have tried this in v2 I posted but it didn't appear to be a reply for PATCH 0. You didn't have (or I didn't see) a PATCH 0 in your v2 version. After patch 1, all patches are replies to patch 1 (using In-Reply-To: and References:) resulting in proper threading. May be I missed something. I don't think so, it looks right now. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] OMAP: DMA: clear interrupt status correctly
Adrian Hunter adrian.hun...@nokia.com writes:
From fffa19df17d73c1ed2e8c65c0b6604ee1dddff84 Mon Sep 17 00:00:00 2001
From: Adrian Hunter adrian.hun...@nokia.com
Date: Wed, 24 Nov 2010 13:23:21 +0200
Subject: [PATCH] OMAP: DMA: clear interrupt status correctly
When clearing the DMA channel, clear all status bits.
When handling a DMA interrupt, clear only the interrupt
status bits that have been read and are passed to the
channel's interrupt handler, not every status bit.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Looks like a fix that should go into 2.6.38-rc2. Can you repost and Cc
linux-arm-kernel as well?
Thanks,
Kevin
---
arch/arm/plat-omap/dma.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c4b2b47..8536308 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -53,7 +53,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
#define OMAP_DMA_ACTIVE 0x01
-#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
+#define OMAP2_DMA_CSR_CLEAR_MASK 0x
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@@ -1873,7 +1873,7 @@ static int omap2_dma_handle_ch(int ch)
printk(KERN_INFO DMA misaligned error with device %d\n,
dma_chan[ch].dev_id);
-p-dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
+ p-dma_write(status, CSR, ch);
p-dma_write(1 ch, IRQSTATUS_L0, ch);
/* read back the register to flush the write */
p-dma_read(IRQSTATUS_L0, ch);
@@ -1893,10 +1893,9 @@ static int omap2_dma_handle_ch(int ch)
OMAP_DMA_CHAIN_INCQHEAD(chain_id);
status = p-dma_read(CSR, ch);
+ p-dma_write(status, CSR, ch);
}
-p-dma_write(status, CSR, ch);
-
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
--
1.7.0.4
--
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[PATCH 0/3] OMAP2PLUS: DSS: Generalize clock names
This patch series changes dss clock names to generic role names for all DSS clocks across clk APIs, hwmod data, dss driver. It also changes the enums used within DSS framework to refer to the clocks to make them generic and related to functionality than value. eg. DSS_CLK_TVFCK replaces DSS_CLK_54M, dss_tv_fck replaces dss_54m_fck This serves as the base for common hwmod DSS opt-clock roles across all OMAP platforms, and increases extendability. === Note: This is interim change set to enable DSS on OMAP2/3/4 platforms; there is an ongoing design discussion for de-centralizing the DSS clock framework handling in favour of using pm_runtime APIs directly in each DSS IP. Once a consensus is reached on that, much of this code will become cleaner, as each DSS IP block handles its own clocks using the common clocks framework. Patch Base: === url = git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git branch master Commit id: fa3b4e23ec20cfc944db7cc2b30b0d82c20e4472 Description: cbus: Fix retu_rtc_do_reset + hwmod patches under discussion: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg41534.html Archit Taneja (2): OMAP2PLUS: DSS2: Generalize naming of PRCM related clock enums in DSS driver OMAP2PLUS: DSS2: Generalize external clock names in struct dss of dss.c Sumit Semwal (1): OMAP2PLUS: opt-clocks: align dss clock roles and names arch/arm/mach-omap2/clock2420_data.c | 10 +- arch/arm/mach-omap2/clock2430_data.c | 10 +- arch/arm/mach-omap2/clock3xxx_data.c | 22 +++- arch/arm/mach-omap2/clock44xx_data.c |7 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |2 +- drivers/video/omap2/dss/core.c |4 +- drivers/video/omap2/dss/dispc.c| 10 +- drivers/video/omap2/dss/dpi.c | 16 ++-- drivers/video/omap2/dss/dsi.c | 18 ++-- drivers/video/omap2/dss/dss.c | 170 ++-- drivers/video/omap2/dss/dss.h | 10 +- drivers/video/omap2/dss/manager.c |4 +- drivers/video/omap2/dss/overlay.c |4 +- drivers/video/omap2/dss/rfbi.c | 10 +- drivers/video/omap2/dss/sdi.c |8 +- drivers/video/omap2/dss/venc.c |8 +- 16 files changed, 167 insertions(+), 146 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] OMAP2PLUS: opt-clocks: align dss clock roles and names
opt clocks require (NULL, act-clock-name) as entries in clock database,
so that hwmod can replace it with (dev, role) tuple during hwmod data init.
These role names are aligned to be same across OMAP2420, 2430, 3xxx, 44xx
platforms,
so clk_get/put/enable/disable APIs in dss can use uniform role names.
Signed-off-by: Sumit Semwal sumit.sem...@ti.com
---
arch/arm/mach-omap2/clock2420_data.c | 10 +++---
arch/arm/mach-omap2/clock2430_data.c | 10 +++---
arch/arm/mach-omap2/clock3xxx_data.c | 22 +++---
arch/arm/mach-omap2/clock44xx_data.c |7 ++-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |2 +-
5 files changed, 36 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c
b/arch/arm/mach-omap2/clock2420_data.c
index 7a56c67..7676e17 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1787,9 +1787,13 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, gfx_ick, gfx_ick, CK_242X),
/* DSS domain clocks */
CLK(omap_dss, ick, dss_ick, CK_242X),
- CLK(omap_dss, dss1_fck, dss1_fck, CK_242X),
- CLK(omap_dss, dss2_fck, dss2_fck, CK_242X),
- CLK(omap_dss, tv_fck, dss_54m_fck, CK_242X),
+ CLK(omap_dss, fck, dss1_fck, CK_242X),
+ /*
+* clocks handled via hwmod opt_clk mechanism need dev=NULL,
+* con=clock name as per actual clk structure, NOT role
+*/
+ CLK(NULL, dss2_fck, dss2_fck, CK_242X),
+ CLK(NULL, dss_54m_fck, dss_54m_fck, CK_242X),
/* L3 domain clocks */
CLK(NULL, core_l3_ck, core_l3_ck,CK_242X),
CLK(NULL, ssi_fck, ssi_ssr_sst_fck, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c
b/arch/arm/mach-omap2/clock2430_data.c
index 48d3437..406d4e7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1891,9 +1891,13 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, mdm_osc_ck, mdm_osc_ck,CK_243X),
/* DSS domain clocks */
CLK(omap_dss, ick, dss_ick, CK_243X),
- CLK(omap_dss, dss1_fck, dss1_fck, CK_243X),
- CLK(omap_dss, dss2_fck, dss2_fck, CK_243X),
- CLK(omap_dss, tv_fck, dss_54m_fck, CK_243X),
+ CLK(omap_dss, fck, dss1_fck, CK_243X),
+ /*
+* clocks handled via hwmod opt_clk mechanism need dev=NULL,
+* con=clock name as per actual clk structure, NOT role
+*/
+ CLK(NULL, dss2_fck, dss2_fck, CK_243X),
+ CLK(NULL, dss_54m_fck, dss_54m_fck, CK_243X),
/* L3 domain clocks */
CLK(NULL, core_l3_ck, core_l3_ck,CK_243X),
CLK(NULL, ssi_fck, ssi_ssr_sst_fck, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index be9077b..8207d43 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3355,13 +3355,21 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(omap_rng, ick, rng_ick, CK_34XX | CK_36XX),
CLK(NULL, sha11_ick,sha11_ick, CK_34XX | CK_36XX),
CLK(NULL, des1_ick, des1_ick, CK_34XX | CK_36XX),
- CLK(omap_dss, dss1_fck, dss1_alwon_fck_3430es1, CK_3430ES1),
- CLK(omap_dss, dss1_fck, dss1_alwon_fck_3430es2, CK_3430ES2PLUS
| CK_AM35XX | CK_36XX),
- CLK(omap_dss, tv_fck, dss_tv_fck,CK_3XXX),
- CLK(omap_dss, video_fck,dss_96m_fck, CK_3XXX),
- CLK(omap_dss, dss2_fck, dss2_alwon_fck, CK_3XXX),
- CLK(omap_dss, ick, dss_ick_3430es1, CK_3430ES1),
- CLK(omap_dss, ick, dss_ick_3430es2, CK_3430ES2PLUS
| CK_AM35XX | CK_36XX),
+ /* DSS clocks */
+ CLK(omap_dss, fck, dss1_alwon_fck_3430es1, CK_3430ES1),
+ CLK(omap_dss, fck, dss1_alwon_fck_3430es2, CK_3430ES2
+| CK_AM35XX),
+ CLK(omap_dss, ick, dss_ick_3430es1, CK_3430ES1),
+ CLK(omap_dss, ick, dss_ick_3430es2, CK_3430ES2
+| CK_AM35XX),
+ /*
+* clocks handled via hwmod opt_clk mechanism need dev=NULL,
+* con=clock name as per actual clk structure, NOT role
+*/
+ CLK(NULL, dss_tv_fck, dss_tv_fck,CK_3XXX),
+ CLK(NULL, dss_96m_fck, dss_96m_fck, CK_3XXX),
+ CLK(NULL, dss2_alwon_fck, dss2_alwon_fck, CK_3XXX),
+
CLK(NULL, cam_mclk, cam_mclk, CK_34XX | CK_36XX),
CLK(NULL, cam_ick, cam_ick, CK_34XX | CK_36XX),
CLK(NULL, csi2_96m_fck, csi2_96m_fck, CK_34XX | CK_36XX),
diff --git
[PATCH 2/3] OMAP2PLUS: DSS2: Generalize naming of PRCM related clock enums in DSS driver
From: Archit Taneja arc...@ti.com
enum dss_clock structure is replaced with generic names that
could be used across OMAP2420, 2430, 3xxx, 44xx platforms.
Signed-off-by: Archit Taneja arc...@ti.com
---
drivers/video/omap2/dss/core.c|4 +-
drivers/video/omap2/dss/dispc.c | 10 +++---
drivers/video/omap2/dss/dpi.c | 16 +-
drivers/video/omap2/dss/dsi.c | 18 +-
drivers/video/omap2/dss/dss.c | 62 ++--
drivers/video/omap2/dss/dss.h | 10 +++---
drivers/video/omap2/dss/manager.c |4 +-
drivers/video/omap2/dss/overlay.c |4 +-
drivers/video/omap2/dss/rfbi.c| 10 +++---
drivers/video/omap2/dss/sdi.c |8 ++--
drivers/video/omap2/dss/venc.c|8 ++--
11 files changed, 77 insertions(+), 77 deletions(-)
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index aadc580..21757ba 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -175,7 +175,7 @@ static int omap_dss_probe(struct platform_device *pdev)
dss_init_overlay_managers(pdev);
dss_init_overlays(pdev);
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M);
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK);
r = dpi_init(pdev);
if (r) {
@@ -213,7 +213,7 @@ static int omap_dss_probe(struct platform_device *pdev)
pdata-default_device = dssdev;
}
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M);
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK);
return 0;
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 8798e76..6e91ac1 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -506,9 +506,9 @@ void dispc_restore_context(void)
static inline void enable_clocks(bool enable)
{
if (enable)
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
else
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
}
bool dispc_go_busy(enum omap_channel channel)
@@ -2208,7 +2208,7 @@ unsigned long dispc_fclk_rate(void)
unsigned long r = 0;
if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
- r = dss_clk_get_rate(DSS_CLK_FCK1);
+ r = dss_clk_get_rate(DSS_CLK_FCK);
else
#ifdef CONFIG_OMAP2_DSS_DSI
r = dsi_get_dsi1_pll_rate();
@@ -2316,7 +2316,7 @@ void dispc_dump_regs(struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, %-35s %08x\n, #r, dispc_read_reg(r))
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
DUMPREG(DISPC_REVISION);
DUMPREG(DISPC_SYSCONFIG);
@@ -2453,7 +2453,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_VID_PRELOAD(0));
DUMPREG(DISPC_VID_PRELOAD(1));
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
#undef DUMPREG
}
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 960e977..470af3d 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -105,7 +105,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
bool is_tft;
int r = 0;
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
dispc_set_pol_freq(dssdev-panel.config, dssdev-panel.acbi,
dssdev-panel.acb);
@@ -135,7 +135,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
dispc_set_lcd_timings(t);
err0:
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
return r;
}
@@ -169,14 +169,14 @@ int omapdss_dpi_display_enable(struct omap_dss_device
*dssdev)
goto err1;
}
- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
r = dpi_basic_init(dssdev);
if (r)
goto err2;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- dss_clk_enable(DSS_CLK_FCK2);
+ dss_clk_enable(DSS_CLK_SYSCK);
r = dsi_pll_init(dssdev, 0, 1);
if (r)
goto err3;
@@ -195,10 +195,10 @@ err4:
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
dsi_pll_uninit();
err3:
- dss_clk_disable(DSS_CLK_FCK2);
+ dss_clk_disable(DSS_CLK_SYSCK);
#endif
err2:
- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
if (cpu_is_omap34xx())
regulator_disable(dpi.vdds_dsi_reg);
err1:
@@ -215,10 +215,10 @@ void omapdss_dpi_display_disable(struct omap_dss_device
*dssdev)
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
[PATCH 3/3] OMAP2PLUS: DSS2: Generalize external clock names in struct dss of dss.c
From: Archit Taneja arc...@ti.com
The dss struct in dss.c has omap2/3 specific clock names. Making them generic,
to increase readability and extendability.
Signed-off-by: Archit Taneja arc...@ti.com
---
drivers/video/omap2/dss/dss.c | 108
1 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 72c13dc..91f2fb1 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -66,10 +66,10 @@ static struct {
struct clk *dpll4_m4_ck;
struct clk *dss_ick;
- struct clk *dss1_fck;
- struct clk *dss2_fck;
- struct clk *dss_54m_fck;
- struct clk *dss_96m_fck;
+ struct clk *dss_fck;
+ struct clk *dss_sys_clk;
+ struct clk *dss_tv_fck;
+ struct clk *dss_video_fck;
unsignednum_clks_enabled;
unsigned long cache_req_pck;
@@ -747,28 +747,28 @@ static int dss_get_clocks(void)
int r;
dss.dss_ick = NULL;
- dss.dss1_fck = NULL;
- dss.dss2_fck = NULL;
- dss.dss_54m_fck = NULL;
- dss.dss_96m_fck = NULL;
+ dss.dss_fck = NULL;
+ dss.dss_sys_clk = NULL;
+ dss.dss_tv_fck = NULL;
+ dss.dss_video_fck = NULL;
r = dss_get_clock(dss.dss_ick, ick);
if (r)
goto err;
- r = dss_get_clock(dss.dss1_fck, dss1_fck);
+ r = dss_get_clock(dss.dss_fck, fck);
if (r)
goto err;
- r = dss_get_clock(dss.dss2_fck, dss2_fck);
+ r = dss_get_clock(dss.dss_sys_clk, sys_clk);
if (r)
goto err;
- r = dss_get_clock(dss.dss_54m_fck, tv_fck);
+ r = dss_get_clock(dss.dss_tv_fck, tv_clk);
if (r)
goto err;
- r = dss_get_clock(dss.dss_96m_fck, video_fck);
+ r = dss_get_clock(dss.dss_video_fck, video_clk);
if (r)
goto err;
@@ -777,25 +777,25 @@ static int dss_get_clocks(void)
err:
if (dss.dss_ick)
clk_put(dss.dss_ick);
- if (dss.dss1_fck)
- clk_put(dss.dss1_fck);
- if (dss.dss2_fck)
- clk_put(dss.dss2_fck);
- if (dss.dss_54m_fck)
- clk_put(dss.dss_54m_fck);
- if (dss.dss_96m_fck)
- clk_put(dss.dss_96m_fck);
+ if (dss.dss_fck)
+ clk_put(dss.dss_fck);
+ if (dss.dss_sys_clk)
+ clk_put(dss.dss_sys_clk);
+ if (dss.dss_tv_fck)
+ clk_put(dss.dss_tv_fck);
+ if (dss.dss_video_fck)
+ clk_put(dss.dss_video_fck);
return r;
}
static void dss_put_clocks(void)
{
- if (dss.dss_96m_fck)
- clk_put(dss.dss_96m_fck);
- clk_put(dss.dss_54m_fck);
- clk_put(dss.dss1_fck);
- clk_put(dss.dss2_fck);
+ if (dss.dss_video_fck)
+ clk_put(dss.dss_video_fck);
+ clk_put(dss.dss_tv_fck);
+ clk_put(dss.dss_fck);
+ clk_put(dss.dss_sys_clk);
clk_put(dss.dss_ick);
}
@@ -805,13 +805,13 @@ unsigned long dss_clk_get_rate(enum dss_clock clk)
case DSS_CLK_ICK:
return clk_get_rate(dss.dss_ick);
case DSS_CLK_FCK:
- return clk_get_rate(dss.dss1_fck);
+ return clk_get_rate(dss.dss_fck);
case DSS_CLK_SYSCK:
- return clk_get_rate(dss.dss2_fck);
+ return clk_get_rate(dss.dss_sys_clk);
case DSS_CLK_TVFCK:
- return clk_get_rate(dss.dss_54m_fck);
+ return clk_get_rate(dss.dss_tv_fck);
case DSS_CLK_VIDFCK:
- return clk_get_rate(dss.dss_96m_fck);
+ return clk_get_rate(dss.dss_video_fck);
}
BUG();
@@ -843,13 +843,13 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks)
if (clks DSS_CLK_ICK)
clk_enable(dss.dss_ick);
if (clks DSS_CLK_FCK)
- clk_enable(dss.dss1_fck);
+ clk_enable(dss.dss_fck);
if (clks DSS_CLK_SYSCK)
- clk_enable(dss.dss2_fck);
+ clk_enable(dss.dss_sys_clk);
if (clks DSS_CLK_TVFCK)
- clk_enable(dss.dss_54m_fck);
+ clk_enable(dss.dss_tv_fck);
if (clks DSS_CLK_VIDFCK)
- clk_enable(dss.dss_96m_fck);
+ clk_enable(dss.dss_video_fck);
dss.num_clks_enabled += num_clks;
}
@@ -871,13 +871,13 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks)
if (clks DSS_CLK_ICK)
clk_disable(dss.dss_ick);
if (clks DSS_CLK_FCK)
- clk_disable(dss.dss1_fck);
+ clk_disable(dss.dss_fck);
if (clks DSS_CLK_SYSCK)
- clk_disable(dss.dss2_fck);
+ clk_disable(dss.dss_sys_clk);
if (clks DSS_CLK_TVFCK)
- clk_disable(dss.dss_54m_fck);
+
Re: [PATCH v2 1/5] omap2plus: clockdomain: Trivial fix for build break because of clktrctrl_mask
Hi Santosh, Santosh Shilimkar santosh.shilim...@ti.com writes: struct clockdomain member clktrctrl_mask is available for only for OMAP2 and OMAP3 architectures. Technially it is also used only for these archs but this breaks the build with custom OMAP4 configuration. I'll queue patches 3-5 for the 2.6.38-rc fixes cycle. With Paul's ack, I can queue the others too, or Paul can decide to take them via his tree. Paul can decide. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] OMAP4: DSS OMAP4 hwmod support
This patch series enables support for OMAP4 DSS, and adds hwmod support for dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods. In OMAP4 there are severals IPs that can be reached by differents interconnect paths depending of the access initiator (MPU vs. SDMA). In the case of the DSS, both L3 direct path and L4 CFG path can be used to access all the DSS IPs. dss is also considered as an IP as dispc, rfbi, and named as dss_dss. TODO: This patch doesn't handle the opt clocks via hwmod - there will be a separate patch series which will take opt clock roles from hwmod, populate them in the device structure, so that the driver can ask for relevant opt-clocks. Also TBD is the migration to pm_runtime APIs, which need to be adapted a little for handling DSS-family of clocks completely. Patch Base: === url = git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git branch master Commit id: fa3b4e23ec20cfc944db7cc2b30b0d82c20e4472 Description: cbus: Fix retu_rtc_do_reset + hwmod patches under discussion: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg41534.html + patch series: OMAP2PLUS: DSS: Generalize clock names Benoit Cousson (1): OMAP4: hwmod data: add DSS DISPC DSI1,2 RFBI HDMI VENC Mayuresh Janorkar (1): OMAP2PLUS: DSS2: Add OMAP4 support Sumit Semwal (1): OMAP4: DSS2: Add hwmod device names for OMAP4. arch/arm/mach-omap2/display.c | 23 +- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 588 drivers/video/omap2/dss/Kconfig|6 +- drivers/video/omap2/omapfb/Kconfig |6 +- 4 files changed, 609 insertions(+), 14 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] OMAP2PLUS: DSS2: Add OMAP4 support
From: Mayuresh Janorkar ma...@ti.com Enable DSS2 and OMAPFB for OMAP4 Signed-off-by: Mayuresh Janorkar ma...@ti.com --- drivers/video/omap2/dss/Kconfig|6 +++--- drivers/video/omap2/omapfb/Kconfig |6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig index 43b6440..0d031b2 100644 --- a/drivers/video/omap2/dss/Kconfig +++ b/drivers/video/omap2/dss/Kconfig @@ -1,8 +1,8 @@ menuconfig OMAP2_DSS -tristate OMAP2/3 Display Subsystem support (EXPERIMENTAL) -depends on ARCH_OMAP2 || ARCH_OMAP3 + tristate OMAP2+ Display Subsystem support (EXPERIMENTAL) + depends on ARCH_OMAP2PLUS help - OMAP2/3 Display Subsystem support. + OMAP2+ Display Subsystem support. if OMAP2_DSS diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig index 65149b2..1da712e 100644 --- a/drivers/video/omap2/omapfb/Kconfig +++ b/drivers/video/omap2/omapfb/Kconfig @@ -1,5 +1,5 @@ menuconfig FB_OMAP2 -tristate OMAP2/3 frame buffer support (EXPERIMENTAL) +tristate OMAP2+ frame buffer support (EXPERIMENTAL) depends on FB OMAP2_DSS select OMAP2_VRAM @@ -8,10 +8,10 @@ menuconfig FB_OMAP2 select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT help - Frame buffer driver for OMAP2/3 based boards. + Frame buffer driver for OMAP2+ based boards. config FB_OMAP2_DEBUG_SUPPORT - bool Debug support for OMAP2/3 FB + bool Debug support for OMAP2+ FB default y depends on FB_OMAP2 help -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] OMAP4: hwmod data: add DSS DISPC DSI1,2 RFBI HDMI VENC
From: Benoit Cousson b-cous...@ti.com
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
++-- L3_MAIN --+ MPU
IP ||
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_dss.
Signed-off-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: Mayuresh Janorkar ma...@ti.com
Signed-off-by: Senthilvadivu Guruswamy svad...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 588
1 files changed, 588 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd..c53ed18 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -43,6 +43,13 @@
static struct omap_hwmod omap44xx_dma_system_hwmod;
static struct omap_hwmod omap44xx_dmm_hwmod;
static struct omap_hwmod omap44xx_dsp_hwmod;
+static struct omap_hwmod omap44xx_dss_dss_hwmod;
+static struct omap_hwmod omap44xx_dss_dispc_hwmod;
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
+static struct omap_hwmod omap44xx_dss_venc_hwmod;
static struct omap_hwmod omap44xx_emif_fw_hwmod;
static struct omap_hwmod omap44xx_iva_hwmod;
static struct omap_hwmod omap44xx_l3_instr_hwmod;
@@ -237,12 +244,21 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 =
{
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* dss - l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+ .master = omap44xx_dss_dss_hwmod,
+ .slave = omap44xx_l3_main_1_hwmod,
+ .clk= l3_div_ck,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l3_main_1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
omap44xx_dsp__l3_main_1,
omap44xx_l3_main_2__l3_main_1,
omap44xx_l4_cfg__l3_main_1,
omap44xx_mpu__l3_main_1,
+ omap44xx_dss__l3_main_1,
};
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
@@ -746,6 +762,569 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/* DSS related classes */
+ /*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
+ .name = dispc,
+ .sysc = omap44xx_dispc_sysc,
+};
+
+/* dss_dispc */
+static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+ { .irq = 25 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
+ { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+ {
+ .pa_start = 0x48041000,
+ .pa_end = 0x48041fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per - dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+ .master = omap44xx_l4_per_hwmod,
+ .slave = omap44xx_dss_dispc_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_dss_dispc_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+ {
+ .pa_start = 0x58001000,
+ .pa_end = 0x58001fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 - dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+ .master = omap44xx_l3_main_2_hwmod,
+ .slave = omap44xx_dss_dispc_hwmod,
+ .clk= l3_div_ck,
+ .addr = omap44xx_dss_dispc_dma_addrs,
+ .addr_cnt =
[PATCH 3/3] OMAP4: DSS2: Add hwmod device names for OMAP4.
Add hwmod device names for OMAP4; this enables device build for omap4 dss
hwmod IPs.
Signed-off-by: Sumit Semwal sumit.sem...@ti.com
---
arch/arm/mach-omap2/display.c | 23 +++
1 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 276b800..918956e 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -51,20 +51,27 @@ int __init omap_display_init(struct omap_dss_board_info
struct omap_device *od;
int i;
struct omap_display_platform_data pdata;
- char *oh_name[] = { dss_dss, /* omap2,3 */
- dss_dispc,/* omap2,3 */
- dss_rfbi, /* omap2,3 */
- dss_venc, /* omap2,3 */
- dss_dsi1 }; /* omap3 */
+ char *oh_name[] = { dss_dss, /* omap2,3,4 */
+ dss_dispc,/* omap2,3,4 */
+ dss_rfbi, /* omap2,3,4 */
+ dss_venc, /* omap2,3,4 */
+ dss_dsi1, /* omap3,4 */
+ dss_dsi2, /* omap4 */
+ dss_hdmi, /* omap4 */
+ };
+
char *dev_name[] = { omap_dss, omap_dispc, omap_rfbi,
omap_venc, omap_dsi1 };
int oh_count;
if (cpu_is_omap24xx()) {
- oh_count = ARRAY_SIZE(oh_name) - 1;
- /* last hwmod dev in oh_name is not available for omap2 */
- } else {
+ oh_count = ARRAY_SIZE(oh_name) - 3;
+ /* last 3 hwmod dev in oh_name not available for omap2 */
+ } else if (cpu_is_omap44xx()) {
oh_count = ARRAY_SIZE(oh_name);
+ } else {
+ oh_count = ARRAY_SIZE(oh_name) - 2;
+ /* last 2 hwmod dev in oh_name not available for omap3 */
}
pdata.board_data= board_data;
--
1.7.0.4
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Re: [PATCH] omap: wd_timer: Fix crash frm wdt_probe when !CONFIG_RUNTIME_PM
Santosh Shilimkar santosh.shilim...@ti.com writes: Commit ff2516fb 'wd_timer: disable on boot via hwmod postsetup mechanism' introduced watchdog timer state state management using postsetup_state. This was done to allow some board files to support watchdog coverage throughout kernel initialization and it work as intended when RUNTIME_PM is enabled. With !CONFIG_RUNTIME_PM and no board is specifically requests watchdog to remain enabled the omap_wdt_probe crashesh. This is because hwmod in absense of runtime PM unable to turn watchdog clocks because it's state is set to be disabled. For rest of the device, the state is set as enabled in absense of RUNTIME_PM [1.372558] Unhandled fault: imprecise external abort (0x1406) at 0xad733eeb [1.379913] Internal error: : 1406 [#1] SMP [1.384277] last sysfs file: [1.387359] Modules linked in: [1.390563] CPU: 0Tainted: GW (2.6.37-rc7-00265-g4298a4c-dirty #23) [1.398468] PC is at omap_wdt_disable+0x2c/0x3c [1.403198] LR is at omap_wdt_probe+0x124/0x1e0 [1.407928] pc : [c02f5bf4]lr : [c03be10c]psr: 6013 [1.407958] sp : df833f00 ip : fp : [1.419921] r10: c0ac57ac r9 : df959e00 r8 : [1.425384] r7 : df959e08 r6 : df8000c0 r5 : df95bebc r4 : df87dde0 [1.432189] r3 : fc314000 r2 : r1 : fc314034 r0 : df87dde0 This patch make the default watchdog state to be enabled in case of !CONFIG_RUNTIME_PM. This fixes the crash Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com Cc: Paul Walmsley p...@pwsan.com --- Paul, I am not too sure if it breaks your _shutdown idea of watchdog timer. Patch generated against 'omap-for-linus' branch and boot tested on OMAP4 with and without CONFIG_OMAP_WATCHDOG. arch/arm/mach-omap2/io.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index e66687b..b879a16 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -378,7 +378,11 @@ void __init omap2_init_common_infrastructure(void) * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional */ +#ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_DISABLED; +#else + postsetup_state = _HWMOD_STATE_ENABLED; +#endif You shouldn't need the 'else' part of this since the default a few lines above this code is already setting that for the !CONFIG_PM_RUNTIME case. Kevin omap_hwmod_for_each_by_class(wd_timer, _set_hwmod_postsetup_state, postsetup_state); -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] arm: omap: gpio: define .disable callback for gpio irq chip
Currently, if one calls disable_irq(gpio_irq), the irq
won't get disabled.
This is happening because the omap gpio code defines only
a .mask callback. And the default_disable function is just
a stub. The result is that, when someone calls disable_irq
for an irq in a gpio line, it will be kept enabled.
This patch solves this issue by setting the .disable
callback to point to the same .mask callback.
Signed-off-by: Eduardo Valentin eduardo.valen...@nokia.com
---
arch/arm/plat-omap/gpio.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index c05c653..033197f 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1433,6 +1433,7 @@ static struct irq_chip gpio_irq_chip = {
.shutdown = gpio_irq_shutdown,
.ack= gpio_ack_irq,
.mask = gpio_mask_irq,
+ .disable= gpio_mask_irq,
.unmask = gpio_unmask_irq,
.set_type = gpio_irq_type,
.set_wake = gpio_wake_enable,
@@ -1469,6 +1470,7 @@ static struct irq_chip mpuio_irq_chip = {
.name = MPUIO,
.ack= mpuio_ack_irq,
.mask = mpuio_mask_irq,
+ .disable= mpuio_mask_irq,
.unmask = mpuio_unmask_irq,
.set_type = gpio_irq_type,
#ifdef CONFIG_ARCH_OMAP16XX
--
1.6.3.GIT
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Re: [PATCH 1/1] arm: omap: gpio: define .disable callback for gpio irq chip
On Wed, Jan 05, 2011 at 07:58:03PM +0200, Eduardo Valentin wrote: Currently, if one calls disable_irq(gpio_irq), the irq won't get disabled. This is happening because the omap gpio code defines only a .mask callback. And the default_disable function is just a stub. The result is that, when someone calls disable_irq for an irq in a gpio line, it will be kept enabled. This patch solves this issue by setting the .disable callback to point to the same .mask callback. Amd this is a problem because? The way this works is that although it isn't disabled at that point, if it never triggers, then everything remains happy. However, if it does trigger, the genirq code will then mask the interrupt and won't call the handler. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] staging: tidspbridge - configure full L1 MMU range
Hi,
On Wed, Jan 5, 2011 at 12:20 AM, Fernando Guzman Lugo
fernando.l...@ti.com wrote:
Otherwise a virtual address beyond of the L1 size is used,
the MMU hardware will look into a memory that does not belong to
L1 translation tables. IOW; the MMU would allow to access any
memory, configured or not.
How about:
IVA MMU can manage up to 4GB of address space through its page tables,
given that it's L1 is divided into 1MB sections it requires at least
16KB for its table which represents 4096 entries of 32 bits each.
Previously, only 1GB was being handled by setting the page table size
to 4KB, any virtual address beyond of the L1 size used, would fall
into memory that does not belong to L1 translation tables, leading to
unpredictable results.
So, set the L1 table size to cover the entire MMU range (4GB) whether
is meant to be used or not.
Reported-by: Felipe Contreras felipe.contre...@nokia.com
Signed-off-by: Fernando Guzman Lugo fernando.l...@ti.com
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/core/tiomap3430.c | 6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c
b/drivers/staging/tidspbridge/core/tiomap3430.c
index 1be081f..ec96d1e 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -70,6 +70,7 @@
#define MMU_LARGE_PAGE_MASK 0x
#define MMU_SMALL_PAGE_MASK 0xF000
#define OMAP3_IVA2_BOOTADDR_MASK 0xFC00
+#define MMU_L1_SIZE 0x4000
#define PAGES_II_LVL_TABLE 512
#define PHYS_TO_PAGE(phys) pfn_to_page((phys) PAGE_SHIFT)
@@ -786,10 +787,7 @@ static int bridge_dev_create(struct bridge_dev_context
pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
if (pt_attrs != NULL) {
- /* Assuming that we use only DSP's memory map
- * until 0x4000: , we would need only 1024
- * L1 enties i.e L1 size = 4K */
- pt_attrs-l1_size = 0x1000;
+ pt_attrs-l1_size = MMU_L1_SIZE;
How about using SZ_16K instead, struct member name already specifies
it is L1 size, is the new define needed?
Regards,
Omar
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[PATCH 0/2] tools, perf: new power trace API
From: Jean Pihet j-pi...@ti.com Provides: . calls to machine_suspend trace point, . API Documentation The OMAP specific changes will be submitted separately on the linux-omap ML because: - the OMAP changes need to be rebased on the latest linux-omap 2.6.37 tree, - more feedback is needed from the linux-omap folks. Jean Pihet (2): perf: add calls to suspend trace point tools, perf: Documentation for the power events API Documentation/trace/events-power.txt | 90 ++ kernel/power/suspend.c |3 + 2 files changed, 93 insertions(+), 0 deletions(-) create mode 100644 Documentation/trace/events-power.txt -- 1.7.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] perf: add calls to suspend trace point
From: Jean Pihet j-pi...@ti.com
Uses the machine_suspend trace point, called from the
generic kernel suspend_devices_and_enter function.
Signed-off-by: Jean Pihet j-pi...@ti.com
CC: Thomas Renninger tr...@suse.de
Acked-by: Rafael J. Wysocki r...@sisk.pl
---
kernel/power/suspend.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index ecf7705..031d5e3 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -22,6 +22,7 @@
#include linux/mm.h
#include linux/slab.h
#include linux/suspend.h
+#include trace/events/power.h
#include power.h
@@ -201,6 +202,7 @@ int suspend_devices_and_enter(suspend_state_t state)
if (!suspend_ops)
return -ENOSYS;
+ trace_machine_suspend(state);
if (suspend_ops-begin) {
error = suspend_ops-begin(state);
if (error)
@@ -229,6 +231,7 @@ int suspend_devices_and_enter(suspend_state_t state)
Close:
if (suspend_ops-end)
suspend_ops-end();
+ trace_machine_suspend(PWR_EVENT_EXIT);
return error;
Recover_platform:
--
1.7.2.3
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[PATCH 2/2] tools, perf: Documentation for the power events API
From: Jean Pihet j-pi...@ti.com Provides documentation for the following: - the new power trace API, - the old (legacy) power trace API, - the DEPRECATED Kconfig option usage. Signed-off-by: Jean Pihet j-pi...@ti.com --- Documentation/trace/events-power.txt | 90 ++ 1 files changed, 90 insertions(+), 0 deletions(-) create mode 100644 Documentation/trace/events-power.txt diff --git a/Documentation/trace/events-power.txt b/Documentation/trace/events-power.txt new file mode 100644 index 000..96d87b6 --- /dev/null +++ b/Documentation/trace/events-power.txt @@ -0,0 +1,90 @@ + + Subsystem Trace Points: power + +The power tracing system captures events related to power transitions +within the kernel. Broadly speaking there are three major subheadings: + + o Power state switch which reports events related to suspend (S-states), + cpuidle (C-states) and cpufreq (P-states) + o System clock related changes + o Power domains related changes and transitions + +This document describes what each of the tracepoints is and why they +might be useful. + +Cf. include/trace/events/power.h for the events definitions. + +1. Power state switch events + + +1.1 New trace API +- + +A 'cpu' event class gathers the CPU-related events: cpuidle and +cpufreq. + +cpu_idle state=%lu cpu_id=%lu +cpu_frequency state=%lu cpu_id=%lu + +A suspend event is used to indicate the system going in and out of the +suspend mode: + +machine_suspendstate=%lu + + +Note: the value of '-1' or '4294967295' for state means an exit from the current state, +i.e. trace_cpu_idle(4, smp_processor_id()) means that the system +enters the idle state 4, while trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()) +means that the system exits the previous idle state. + +The event which has 'state=4294967295' in the trace is very important to the user +space tools which are using it to detect the end of the current state, and so to +correctly draw the states diagrams and to calculate accurate statistics etc. + +1.2 DEPRECATED trace API + + +A new Kconfig option CONFIG_EVENT_POWER_TRACING_DEPRECATED with the default value of +'y' has been created. This allows the legacy trace power API to be used conjointly +with the new trace API. +The Kconfig option, the old trace API (in include/trace/events/power.h) and the +old trace points will disappear in a future release (namely 2.6.41). + +power_starttype=%lu state=%lu cpu_id=%lu +power_frequencytype=%lu state=%lu cpu_id=%lu +power_end cpu_id=%lu + +The 'type' parameter takes one of those macros: + . POWER_NONE = 0, + . POWER_CSTATE= 1,/* C-State */ + . POWER_PSTATE= 2,/* Fequency change or DVFS */ + +The 'state' parameter is set depending on the type: + . Target C-state for type=POWER_CSTATE, + . Target frequency for type=POWER_PSTATE, + +power_end is used to indicate the exit of a state, corresponding to the latest +power_start event. + +2. Clocks events + +The clock events are used for clock enable/disable and for +clock rate change. + +clock_enable %s state=%lu cpu_id=%lu +clock_disable %s state=%lu cpu_id=%lu +clock_set_rate %s state=%lu cpu_id=%lu + +The first parameter gives the clock name (e.g. gpio1_iclk). +The second parameter is '1' for enable, '0' for disable, the target +clock rate for set_rate. + +3. Power domains events +=== +The power domain events are used for power domains transitions + +power_domain_target%s state=%lu cpu_id=%lu + +The first parameter gives the power domain name (e.g. mpu_pwrdm). +The second parameter is the power domain target state. + -- 1.7.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] arm: omap: gpio: define .disable callback for gpio irq chip
Hello Russell, On Wed, Jan 05, 2011 at 06:19:18PM +, Russell King wrote: On Wed, Jan 05, 2011 at 07:58:03PM +0200, Eduardo Valentin wrote: Currently, if one calls disable_irq(gpio_irq), the irq won't get disabled. This is happening because the omap gpio code defines only a .mask callback. And the default_disable function is just a stub. The result is that, when someone calls disable_irq for an irq in a gpio line, it will be kept enabled. This patch solves this issue by setting the .disable callback to point to the same .mask callback. Amd this is a problem because? errr.. because the interrupt is enabled when it was supposed to be disabled? The way this works is that although it isn't disabled at that point, if it never triggers, then everything remains happy. However, if it does trigger, the genirq code will then mask the interrupt and won't call the handler. Right.. I didn't see from this point. I will check how that gets unmasked. But even so, if I understood correctly what you described, it would still open a time window which the system would see at least 1 interrupt during the time it was not suppose to. And that can wakeup a system which is in deep sleep mode, either via dynamic idle or static suspend. It is unlikely, I know. But it can still happen. And can be avoided. Regards, -- Eduardo Valentin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] staging: tidspbridge - configure full L1 MMU range
On Wed, Jan 5, 2011 at 12:46 PM, Ramirez Luna, Omar omar.rami...@ti.com wrote:
Hi,
On Wed, Jan 5, 2011 at 12:20 AM, Fernando Guzman Lugo
fernando.l...@ti.com wrote:
Otherwise a virtual address beyond of the L1 size is used,
the MMU hardware will look into a memory that does not belong to
L1 translation tables. IOW; the MMU would allow to access any
memory, configured or not.
How about:
IVA MMU can manage up to 4GB of address space through its page tables,
given that it's L1 is divided into 1MB sections it requires at least
16KB for its table which represents 4096 entries of 32 bits each.
Previously, only 1GB was being handled by setting the page table size
to 4KB, any virtual address beyond of the L1 size used, would fall
into memory that does not belong to L1 translation tables, leading to
unpredictable results.
So, set the L1 table size to cover the entire MMU range (4GB) whether
is meant to be used or not.
looks good to me.
Reported-by: Felipe Contreras felipe.contre...@nokia.com
Signed-off-by: Fernando Guzman Lugo fernando.l...@ti.com
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/core/tiomap3430.c | 6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c
b/drivers/staging/tidspbridge/core/tiomap3430.c
index 1be081f..ec96d1e 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -70,6 +70,7 @@
#define MMU_LARGE_PAGE_MASK 0x
#define MMU_SMALL_PAGE_MASK 0xF000
#define OMAP3_IVA2_BOOTADDR_MASK 0xFC00
+#define MMU_L1_SIZE 0x4000
#define PAGES_II_LVL_TABLE 512
#define PHYS_TO_PAGE(phys) pfn_to_page((phys) PAGE_SHIFT)
@@ -786,10 +787,7 @@ static int bridge_dev_create(struct bridge_dev_context
pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
if (pt_attrs != NULL) {
- /* Assuming that we use only DSP's memory map
- * until 0x4000: , we would need only 1024
- * L1 enties i.e L1 size = 4K */
- pt_attrs-l1_size = 0x1000;
+ pt_attrs-l1_size = MMU_L1_SIZE;
How about using SZ_16K instead, struct member name already specifies
it is L1 size, is the new define needed?
Ok, maybe a comment to state why 16K is used should be good.
I will make the changes.
Regards,
Fernando.
Regards,
Omar
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Re: [PATCH 1/1] arm: omap: gpio: define .disable callback for gpio irq chip
On Wed, Jan 05, 2011 at 09:24:25PM +0200, Eduardo Valentin wrote: The way this works is that although it isn't disabled at that point, if it never triggers, then everything remains happy. However, if it does trigger, the genirq code will then mask the interrupt and won't call the handler. Right.. I didn't see from this point. I will check how that gets unmasked. But even so, if I understood correctly what you described, it would still open a time window which the system would see at least 1 interrupt during the time it was not suppose to. And that can wakeup a system which is in deep sleep mode, either via dynamic idle or static suspend. It is unlikely, I know. But it can still happen. And can be avoided. Maybe a system going into deep sleep mode should update the masked state of the interrupts to reflect the lazy-disable state? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] OMAP3: beagle xm: enable upto 800MHz OPP
Beagle XM uses 3730 and the board design allows enabling 800MHz and 1GHz
OPPs. However, We need Smart reflex class 1.5 and ABB to enable 1GHz safely.
For the moment, we tweak the default table to allow for 800Mhz OPP usage.
Reported-by: Koen Kooi k...@beagleboard.org
Tested-by: Koen Kooi k...@beagleboard.org
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/board-omap3beagle.c | 50 +++
1 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
b/arch/arm/mach-omap2/board-omap3beagle.c
index 6c12760..0b99b80 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -23,6 +23,7 @@
#include linux/gpio.h
#include linux/input.h
#include linux/gpio_keys.h
+#include linux/opp.h
#include linux/mtd/mtd.h
#include linux/mtd/partitions.h
@@ -44,10 +45,12 @@
#include plat/gpmc.h
#include plat/nand.h
#include plat/usb.h
+#include plat/omap_device.h
#include mux.h
#include hsmmc.h
#include timer-gp.h
+#include pm.h
#define NAND_BLOCK_SIZESZ_128K
@@ -556,6 +559,52 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
+static void __init beagle_opp_init(void)
+{
+ int r = 0;
+
+ /* Initialize the omap3 opp table */
+ if (omap3_opp_init()) {
+ pr_err(%s: opp default init failed\n, __func__);
+ return;
+ }
+
+ /* Custom OPP enabled for XM */
+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+ struct omap_hwmod *mh = omap_hwmod_lookup(mpu);
+ struct omap_hwmod *dh = omap_hwmod_lookup(iva);
+ struct device *dev;
+
+ if (!mh || !dh) {
+ pr_err(%s: Aiee.. no mpu/dsp devices? %p %p\n,
+ __func__, mh, dh);
+ r = -EINVAL;
+ } else {
+ /* Enable MPU 1GHz and lower opps */
+ dev = mh-od-pdev.dev;
+ r = opp_enable(dev, 8);
+ /* TODO: MPU 1GHz needs SR and ABB */
+
+ /* Enable IVA 800MHz and lower opps */
+ dev = dh-od-pdev.dev;
+ r |= opp_enable(dev, 66000);
+ /* TODO: DSP 800MHz needs SR and ABB */
+ }
+ if (r) {
+ pr_err(%s: failed to enable higher opp %d\n,
+ __func__, r);
+ /*
+* Cleanup - disable the higher freqs - we dont care
+* about the results
+*/
+ dev = mh-od-pdev.dev;
+ opp_disable(dev, 8);
+ dev = dh-od-pdev.dev;
+ opp_disable(dev, 66000);
+ }
+ }
+}
+
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -579,6 +628,7 @@ static void __init omap3_beagle_init(void)
omap_mux_init_signal(sdrc_cke1, OMAP_PIN_OUTPUT);
beagle_display_init();
+ beagle_opp_init();
}
MACHINE_START(OMAP3_BEAGLE, OMAP3 Beagle Board)
--
1.6.3.3
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[PATCH 0/2] OMAP3: Beagle: enable 800MHz for xm
Source: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git branch: omap-for-linus (dc69d1a omap2: Make OMAP2PLUS select OMAP_DM_TIMER) Nishanth Menon (2): omap3|4: opp: make omapx_opp_init non-static OMAP3: beagle xm: enable upto 800MHz OPP arch/arm/mach-omap2/board-omap3beagle.c | 52 +++ arch/arm/mach-omap2/opp3xxx_data.c |3 +- arch/arm/mach-omap2/opp4xxx_data.c |3 +- 3 files changed, 56 insertions(+), 2 deletions(-) Tested: Beagle XM with Angstrom Tested-by: Koen Kooi k...@beagleboard.org Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] omap3|4: opp: make omapx_opp_init non-static
omap3 and omap4 opp_init should be made non-static to allow
for platform specific opp table tweaking. making these static
conflicts with the definition in pm.h(global) as well.
we include pm.h as well to ensure that there are no such prototype
conflicts with actual implementation in the future.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/opp3xxx_data.c |3 ++-
arch/arm/mach-omap2/opp4xxx_data.c |3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c
b/arch/arm/mach-omap2/opp3xxx_data.c
index 0486fce..fd3a1af 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -21,6 +21,7 @@
#include plat/cpu.h
#include omap_opp_data.h
+#include pm.h
static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
/* MPU OPP1 */
@@ -88,7 +89,7 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[]
= {
/**
* omap3_opp_init() - initialize omap3 opp table
*/
-static int __init omap3_opp_init(void)
+int __init omap3_opp_init(void)
{
int r = -ENODEV;
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index a11fa56..f0e9939 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -22,6 +22,7 @@
#include plat/cpu.h
#include omap_opp_data.h
+#include pm.h
static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
@@ -42,7 +43,7 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[]
= {
/**
* omap4_opp_init() - initialize omap4 opp table
*/
-static int __init omap4_opp_init(void)
+int __init omap4_opp_init(void)
{
int r = -ENODEV;
--
1.6.3.3
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[PATCHv2] staging: tidspbridge: configure full L1 MMU range
From: Guzman Lugo, Fernando fernando.l...@ti.com
IVA MMU can manage up to 4GB of address space through its page tables,
given that it's L1 is divided into 1MB sections it requires at least
16KB for its table which represents 4096 entries of 32 bits each.
Previously, only 1GB was being handled by setting the page table size
to 4KB, any virtual address beyond of the L1 size used, would fall
into memory that does not belong to L1 translation tables, leading to
unpredictable results.
So, set the L1 table size to cover the entire MMU range (4GB) whether
is meant to be used or not.
Reported-by: Felipe Contreras felipe.contre...@nokia.com
Signed-off-by: Fernando Guzman Lugo fernando.l...@ti.com
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/core/tiomap3430.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c
b/drivers/staging/tidspbridge/core/tiomap3430.c
index cacd30e..7608822 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -784,10 +784,7 @@ static int bridge_dev_create(struct bridge_dev_context
pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
if (pt_attrs != NULL) {
- /* Assuming that we use only DSP's memory map
-* until 0x4000: , we would need only 1024
-* L1 enties i.e L1 size = 4K */
- pt_attrs-l1_size = 0x1000;
+ pt_attrs-l1_size = SZ_16K; /* 4096 entries of 32 bits */
align_size = pt_attrs-l1_size;
/* Align sizes are expected to be power of 2 */
/* we like to get aligned on L1 table size */
--
1.7.0.4
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Re: [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
On Tue, Jan 04, 2011 at 04:06:39PM +0300, Sergei Shtylyov wrote: Putting MUSB DMA enignes into drivers/dma/ is the same as taking *any* chip capable of bus-mastering DMA, separating its bus mastering related code from its driver and putting this code into drivers/dma/. This doesn't make sense, in my opinion. drivers/dma/ is for the dedicated DMA controllers (which can *optionally* serve the slave devices). Then why is it already separated into its own self-contained driver? If it's because the DMA engine is used for different peripherals (possibly re-used for different peripherals), then it does seem to make sense to have it separated via some API. And if possible that API might should be something generic instead of specific. Even more reason to do this is if the device being fed by the DMA has been re-used with different DMA hardware (which I believe is the case with MUSB.) What if this different DMA hardware then gets re-used for other devices? Should they all implement the same custom API or try for a generic API? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap: wd_timer: Fix crash frm wdt_probe when !CONFIG_RUNTIME_PM
On Wed, Jan 05, 2011 at 07:10:55PM +0530, Santosh Shilimkar wrote: Commit ff2516fb 'wd_timer: disable on boot via hwmod postsetup mechanism' introduced watchdog timer state state management using postsetup_state. This was done to allow some board files to support watchdog coverage throughout kernel initialization and it work as intended when RUNTIME_PM is enabled. With !CONFIG_RUNTIME_PM and no board is specifically requests watchdog to remain enabled the omap_wdt_probe crashesh. This is because hwmod in absense of runtime PM unable to turn watchdog clocks because it's state is set to be disabled. For rest of the device, the state is set as enabled in absense of RUNTIME_PM Err... wasn't this provoked by an attempt to fix the LDP issue, that is (I believe) because the boot loader enables the watchdog and pre-hwmod kernels used to disable it. Post-hwmod kernels stopped disabling the watchdog, resulting in a few seconds booting userspace before the system resets itself. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] arm: omap: gpio: define .disable callback for gpio irq chip
Eduardo Valentin eduardo.valen...@nokia.com writes: Hello Russell, On Wed, Jan 05, 2011 at 06:19:18PM +, Russell King wrote: On Wed, Jan 05, 2011 at 07:58:03PM +0200, Eduardo Valentin wrote: Currently, if one calls disable_irq(gpio_irq), the irq won't get disabled. This is happening because the omap gpio code defines only a .mask callback. And the default_disable function is just a stub. The result is that, when someone calls disable_irq for an irq in a gpio line, it will be kept enabled. This patch solves this issue by setting the .disable callback to point to the same .mask callback. Amd this is a problem because? errr.. because the interrupt is enabled when it was supposed to be disabled? As Russell pointed out, it's not actually supposed to be. With lazy disable, what disable_irq() does is prevent the *handler* from ever being called. If another interrupt arrives, it will be caught by the genirq core, marked as IRQ_PENDING and then masked. This don't disable unless we really have to is the desired behavior of the lazy disable feature. The way this works is that although it isn't disabled at that point, if it never triggers, then everything remains happy. However, if it does trigger, the genirq code will then mask the interrupt and won't call the handler. Right.. I didn't see from this point. I will check how that gets unmasked. But even so, if I understood correctly what you described, it would still open a time window which the system would see at least 1 interrupt during the time it was not suppose to. And that can wakeup a system which is in deep sleep mode, either via dynamic idle or static suspend. It is unlikely, I know. But it can still happen. And can be avoided. If the GPIO is configured as a wakeup source, then wouldn't you want activity on that GPIO to wake up the system? If you don't want wakeups on that GPIO, then the driver should probably be using disable_irq_wake(). Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] OMAP3: beagle xm: enable upto 800MHz OPP
Nishanth Menon n...@ti.com writes:
Beagle XM uses 3730 and the board design allows enabling 800MHz and 1GHz
OPPs. However, We need Smart reflex class 1.5 and ABB to enable 1GHz safely.
For the moment, we tweak the default table to allow for 800Mhz OPP usage.
Isn't this common to any board using 3730 (or 3630?)
IOW, what is Beagle specific about this?
Kevin
Reported-by: Koen Kooi k...@beagleboard.org
Tested-by: Koen Kooi k...@beagleboard.org
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/board-omap3beagle.c | 50
+++
1 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
b/arch/arm/mach-omap2/board-omap3beagle.c
index 6c12760..0b99b80 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -23,6 +23,7 @@
#include linux/gpio.h
#include linux/input.h
#include linux/gpio_keys.h
+#include linux/opp.h
#include linux/mtd/mtd.h
#include linux/mtd/partitions.h
@@ -44,10 +45,12 @@
#include plat/gpmc.h
#include plat/nand.h
#include plat/usb.h
+#include plat/omap_device.h
#include mux.h
#include hsmmc.h
#include timer-gp.h
+#include pm.h
#define NAND_BLOCK_SIZE SZ_128K
@@ -556,6 +559,52 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
+static void __init beagle_opp_init(void)
+{
+ int r = 0;
+
+ /* Initialize the omap3 opp table */
+ if (omap3_opp_init()) {
+ pr_err(%s: opp default init failed\n, __func__);
+ return;
+ }
+
+ /* Custom OPP enabled for XM */
+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+ struct omap_hwmod *mh = omap_hwmod_lookup(mpu);
+ struct omap_hwmod *dh = omap_hwmod_lookup(iva);
+ struct device *dev;
+
+ if (!mh || !dh) {
+ pr_err(%s: Aiee.. no mpu/dsp devices? %p %p\n,
+ __func__, mh, dh);
+ r = -EINVAL;
+ } else {
+ /* Enable MPU 1GHz and lower opps */
+ dev = mh-od-pdev.dev;
+ r = opp_enable(dev, 8);
+ /* TODO: MPU 1GHz needs SR and ABB */
+
+ /* Enable IVA 800MHz and lower opps */
+ dev = dh-od-pdev.dev;
+ r |= opp_enable(dev, 66000);
+ /* TODO: DSP 800MHz needs SR and ABB */
+ }
+ if (r) {
+ pr_err(%s: failed to enable higher opp %d\n,
+ __func__, r);
+ /*
+ * Cleanup - disable the higher freqs - we dont care
+ * about the results
+ */
+ dev = mh-od-pdev.dev;
+ opp_disable(dev, 8);
+ dev = dh-od-pdev.dev;
+ opp_disable(dev, 66000);
+ }
+ }
+}
+
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -579,6 +628,7 @@ static void __init omap3_beagle_init(void)
omap_mux_init_signal(sdrc_cke1, OMAP_PIN_OUTPUT);
beagle_display_init();
+ beagle_opp_init();
}
MACHINE_START(OMAP3_BEAGLE, OMAP3 Beagle Board)
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Re: [PATCH v8 6/11] OMAP1: dmtimer: conversion to platform devices
Hi Tarun,
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
From: Thara Gopinath th...@ti.com
Convert OMAP1 dmtimers into a platform devices and then registers with
device model framework so that it can be bound to corresponding driver.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
One minor nit...
[...]
+int __init omap1_dm_timer_init(void)
+{
+ int i;
+ int ret;
+ struct dmtimer_platform_data *pdata;
+ struct platform_device *pdev;
+
+ pr_debug(%s: +\n, __func__);
stray debug print?
Kevin
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RE: [PATCH v3 1/4] TI816X: Update common omap platform files
linux-omap-ow...@vger.kernel.org wrote on : Tony Lindgren wrote on Wednesday, January 05, 2011 4:56 AM: * Paul Walmsley p...@pwsan.com [110104 09:48]: On Tue, 4 Jan 2011, Pedanekar, Hemant wrote: Looking at above, it seems another config option like CONFIG_SOC_OMAP3XXX is also needed in addition to CONFIG_SOC_OMAPTI816X. We already have CONFIG_ARCH_OMAP3430, CONFIG_ARCH_OMAP2430, and CONFIG_ARCH_OMAP2420. I guess at some point those need to be renamed to CONFIG_SOC_*. Yes that's what I was thinking too. Keep CONFIG_ARCH_OMAP2, 3, and 4, and rename CONFIG_ARCH_OMAP3430 etc to CONFIG_SO_COMAP3430 and so on. Regards, Tony So I will add CONFIG_SOC_OMAPTI816X to handle TI816X specific variations. But I think without addition of corresponding CONFIG_SOC_OMAP3XXX, it would be difficult to handle 2nd case I mentioned (OMAP3 build for OMAP3xxx as well as TI816X SoCs). Will it be OK if we consider this 2nd case as invalid/unsupported for the moment - that is, 2nd case = 4th case (OMAP3 build for TI816X only)? Same applies for multi-omap case too. In short, if CONFIG_SOC_OMAPTI816X is selected, the build becomes specific to TI816X and not OMAP3xxx in all the cases (so keep CONFIG_SOC_OMAPTI816X disabled by default in multi-omap configuration). Tony, Does the above look ok? Also please let me know any other comments and I will send updated patches. Thanks - Hemant -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] PM: fix suspend_set_ops() to take const pointer
checkpatch warns that pointers for certain structs should be const,
and platform_suspend_ops is one of those structs. If you follow this
suggestion you trade a checkpatch warning for a compiler warning of
the form:
warning: passing argument 1 of 'suspend_set_ops' discards qualifiers from
pointer target type
Fix suspend_set_ops() to take a const pointer so everyone expects
const.
Signed-off-by: Kevin Hilman khil...@ti.com
---
Applies to v2.6.37, but also applies cleanly to suspend-2.6/linux-next
include/linux/suspend.h |4 ++--
kernel/power/suspend.c |2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index 2669751..bb98383 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -122,7 +122,7 @@ struct platform_suspend_ops {
* suspend_set_ops - set platform dependent suspend operations
* @ops: The new suspend operations to set.
*/
-extern void suspend_set_ops(struct platform_suspend_ops *ops);
+extern void suspend_set_ops(const struct platform_suspend_ops *ops);
extern int suspend_valid_only_mem(suspend_state_t state);
/**
@@ -147,7 +147,7 @@ extern int pm_suspend(suspend_state_t state);
#else /* !CONFIG_SUSPEND */
#define suspend_valid_only_mem NULL
-static inline void suspend_set_ops(struct platform_suspend_ops *ops) {}
+static inline void suspend_set_ops(const struct platform_suspend_ops *ops) {}
static inline int pm_suspend(suspend_state_t state) { return -ENOSYS; }
#endif /* !CONFIG_SUSPEND */
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index ecf7705..0c0af3d 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -36,7 +36,7 @@ static struct platform_suspend_ops *suspend_ops;
* suspend_set_ops - Set the global suspend method table.
* @ops: Pointer to ops structure.
*/
-void suspend_set_ops(struct platform_suspend_ops *ops)
+void suspend_set_ops(const struct platform_suspend_ops *ops)
{
mutex_lock(pm_mutex);
suspend_ops = ops;
--
1.7.3.4
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Re: [PATCH] arm: mach-omap2: pm: cleanup !CONFIG_SUSPEND handling
Hi Aaro,
Aaro Koskinen aaro.koski...@nokia.com writes:
Make !CONFIG_SUSPEND init declarations identical on all OMAPs and
eliminate some ifdefs.
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
I like this solution, but it introduces compiler warnings:
/opt/home/khilman/work.local/kernel/omap/pm/arch/arm/mach-omap2/pm44xx.c: In
function 'omap4_pm_init':
/opt/home/khilman/work.local/kernel/omap/pm/arch/arm/mach-omap2/pm44xx.c:119:
warning: passing argument 1 of 'suspend_set_ops' discards qualifiers from
pointer target type
/opt/home/khilman/work.local/kernel/omap/pm/include/linux/suspend.h:125: note:
expected 'struct platform_suspend_ops *' but argument is of type 'const struct
platform_suspend_ops *'
/opt/home/khilman/work.local/kernel/omap/pm/arch/arm/mach-omap2/pm24xx.c: In
function 'omap2_pm_init':
/opt/home/khilman/work.local/kernel/omap/pm/arch/arm/mach-omap2/pm24xx.c:585:
warning: passing argument 1 of 'suspend_set_ops' discards qualifiers from
pointer target type
/opt/home/khilman/work.local/kernel/omap/pm/include/linux/suspend.h:125: note:
expected 'struct platform_suspend_ops *' but argument is of type 'const struct
platform_suspend_ops *'
/opt/home/khilman/work.local/kernel/omap/pm/arch/arm/mach-omap2/pm34xx.c: In
function 'omap3_pm_init':
/opt/home/khilman/work.local/kernel/omap/pm/arch/arm/mach-omap2/pm34xx.c:1072:
warning: passing argument 1 of 'suspend_set_ops' discards qualifiers from
pointer target type
/opt/home/khilman/work.local/kernel/omap/pm/include/linux/suspend.h:125:
note: expected 'struct platform_suspend_ops *' but argument is of type
'const struct platform_suspend_ops *'
As you likely noticed, removing the const leads to checkpatch warnings:
WARNING: struct platform_suspend_ops should normally be const
so the choice is between a checkpatch warning or a bunch of compiler
warnings.
Alternatively, I just posted a patch[1] to linux-pm propsing to fix this
at the source. Let's see what happens there. Merging $SUBJECT patch
will depend on how this is fixed upstream.
Kevin
[1] https://patchwork.kernel.org/patch/455831/
---
arch/arm/mach-omap2/pm.h |4
arch/arm/mach-omap2/pm24xx.c | 16
arch/arm/mach-omap2/pm34xx.c | 16
arch/arm/mach-omap2/pm44xx.c | 17 +
4 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 1c1b0ab..704766b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -138,4 +138,8 @@ static inline int omap4_twl_init(void)
}
#endif
+#ifndef CONFIG_SUSPEND
+#define omap_pm_ops NULL
+#endif
+
#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index dac2d1d..e65b329 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -350,14 +350,14 @@ static void omap2_pm_end(void)
enable_hlt();
}
-static struct platform_suspend_ops omap_pm_ops = {
- .begin = omap2_pm_begin,
- .enter = omap2_pm_enter,
- .end= omap2_pm_end,
- .valid = suspend_valid_only_mem,
+static const struct platform_suspend_ops omap_pm_ops[] = {
+ {
+ .begin = omap2_pm_begin,
+ .enter = omap2_pm_enter,
+ .end= omap2_pm_end,
+ .valid = suspend_valid_only_mem,
+ }
};
-#else
-static const struct platform_suspend_ops __initdata omap_pm_ops;
#endif /* CONFIG_SUSPEND */
/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
@@ -582,7 +582,7 @@ static int __init omap2_pm_init(void)
omap24xx_cpu_suspend_sz);
}
- suspend_set_ops(omap_pm_ops);
+ suspend_set_ops(omap_pm_ops);
pm_idle = omap2_pm_idle;
return 0;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5b323f2..a4c9283 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -605,11 +605,13 @@ static void omap3_pm_end(void)
return;
}
-static struct platform_suspend_ops omap_pm_ops = {
- .begin = omap3_pm_begin,
- .end= omap3_pm_end,
- .enter = omap3_pm_enter,
- .valid = suspend_valid_only_mem,
+static const struct platform_suspend_ops omap_pm_ops[] = {
+ {
+ .begin = omap3_pm_begin,
+ .end= omap3_pm_end,
+ .enter = omap3_pm_enter,
+ .valid = suspend_valid_only_mem,
+ }
};
#endif /* CONFIG_SUSPEND */
@@ -1067,9 +1069,7 @@ static int __init omap3_pm_init(void)
core_clkdm = clkdm_lookup(core_clkdm);
omap_push_sram_idle();
-#ifdef CONFIG_SUSPEND
- suspend_set_ops(omap_pm_ops);
-#endif /* CONFIG_SUSPEND */
+ suspend_set_ops(omap_pm_ops);
pm_idle =
Re: [PATCH] OMAP3+: sr_device: include pm header
Nishanth Menon n...@ti.com writes: omap_enable_smartreflex_on_init is meant to be used by boards which would like to have SR enabled by default on the platform, while omap_devinit_smartreflex is used by pm code, the protos are defined in pm.h. This header should be included to ensure that sr_device function definitions match the prototypes. including pm.h fixes the sparse warnings (with CONFIG_OMAP_SMARTREFLEX=y): arch/arm/mach-omap2/sr_device.c:138:13: warning: symbol 'omap_enable_smartreflex_on_init' was not declared. Should it be static? arch/arm/mach-omap2/sr_device.c:143:12: warning: symbol 'omap_devinit_smartreflex' was not declared. Should it be static? Signed-off-by: Nishanth Menon n...@ti.com Thanks, will queue as a fix for 2.6.38-rc cycle. Kevin Based on: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git branch: omap-for-linus arch/arm/mach-omap2/sr_device.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 786d685..b1e0af1 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -27,6 +27,7 @@ #include plat/voltage.h #include control.h +#include pm.h static bool sr_enable_on_init; -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 4/11] OMAP3: hwmod data: add dmtimer
Tarun Kanti DebBarma tarun.ka...@ti.com writes: From: Thara Gopinath th...@ti.com Add dmtimer data. Signed-off-by: Thara Gopinath th...@ti.com Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com Acked-by: Cousson, Benoit b-cous...@ti.com This patch only adds GPT1-11. What about GPT12 which is not only accessible on GP devices, on Beagle it is used as the system timer. The result is this cannot boot on Beagle. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 0/11] dmtimer adaptation to platform_driver
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
dmtimer adaptation to platform_driver.
This patch series is adaptation of dmtimer code to platform driver
using omap_device and omap_hwmod abstraction.
Tested on following platforms:
OMAP1710 H3 SDP
OMAP2420 SDP
OMAP2430 SDP
OMAP3430 SDP
OMAP3630 SDP
OMAP4430 SDP
How exactly was this tested? Boot tested only? Do you have a test
that attempts to request/configure/enable all the timers? The timer-gp
code allows all the way to GPT12 which obviously will not work in this
series.
Also, testing with PM on 34xx/n900, I noticed that this series prevents
PER and CORE from hitting retention during suspend. I haven't debugged
why yet.
Kevin
Baseline:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
Branch: origin/omap-for-linus
v8:
(1) Baselined on Tony's tree in omap-for-linus branch
(2) The last patch in v7 series has been removed because it is fixed
by following patch:
commit: 78f26e872f77b6312273216de1a8f836c6f2e143
OMAP: hwmod: Set autoidle after smartidle during _sysc_enable
TODO:
(1) OFF Mode support
(2) Upgrade timeout implementation in low-level read/write access to return
error condition to EXPORT APIs. This is re-frained in the present
implementation
because that would involve change to EXPORTED APIs. Besides, there is no clear
design as yet which is agreed upon by the community.
v7:
(1) In omap1_dm_timer_set_src(), the computation of shift value to respective
dmtimer clock source was corrected:
From:
int n = (pdev-id) 1;
To:
int n = (pdev-id - 1) 1;
This change is needed because dmtimer is indexed from 1 now instead of 0.
(2) In omap1_dm_timer_init(void) memory resource end address chnaged:
From:
res[0].end = base + 0xff;
To:
res[0].end = base + 0x46;
This was causing request_mem_region() failure in driver probe().
(3) In the export APIs there are some calls which are not applicable to OMAP1.
They have been made conditional now. They include following calls:
timer-fclk = clk_get(timer-pdev-dev, fck);
omap_dm_timer_enable()
omap_dm_timer_disable()
(4) Remove usage of cpu_is_omap16xx() and instead a flag has been added in
struct dmtimer_platform_data {
...
u32 is_omap16xx:1;
}
This flag is set to 1 in mach-omap1/dmtimer.c and set to 0 in
mach-omap2/dmtimer.c
This flag is used in plat-omap/dmtimer.c wherever it needs to distiguish
omap16xx.
(5) Remove #include plat/omap_device.h from mach-omap1/dmtimer.c
(6) Instead of using macros like INT_24XX_GPTIMERx, use the numbers
directly in OMAP2420, OMAP2430 and OMAP3xxx hwmod database.
(7) pm_runtime_get_sync() and pm_runtime_put_sync() return value check
modified
from positive to negative value:
if (pm_runtime_get_sync(...) 0) {
...
}
v6:
(1) Removed reset functions to mach-omap1/dmtimer.c.
Access to reset function from plat-omap/dmtimer.c is provided by means
of function pointer.
(2) Remove multiple calls to omap_device_build() for registering timer devices
during early and regular initialization. Regular device registration is now
done
by reading data from temporary list. This list is populated during early init
where timer data is read from hwmod database and corresponding memory
allocated.
(3) kfree(pdata) under error condition since platform_device_unregister does
not free its pdata.
(4) Removed extra header inclusion in mach-omap2 and plat-omap
NOTE: omap_dm_timer.id field could not be removed because during regular
boot
there is no mechanism to match the current pdev with corresponding entry in
the
timer list which was partially initialized during early boot.
v4:
(1) clock aliases are renamed as 32k_ck, sys_ck and alt_ck
(2) incorporate missing clk_put() for corresponding clk_get()
(3) modified clk_get()/clk_put() to be called once once in platform driver.
(4) consistent header for new files
(5) check return value of omap_hwmod_for_each_by_class() in device init
routines.
(6) remove is_abe_timer field in dmtimer_platform_data structure. this is
no longer needed with new input clock source aliasing.
(7) proper splitting of patch series
(8) remove register map from hwmod database.
(9) remove clock source strings array from hwmod database and associated
structure declaration from plat/dmtimer.h. this is no longer needed.
(10) remove dev_attr from hwmod database. this is no longer needed.
(11) use register offsets to identify OMAP 4 registers instead of register
map.
(12) remove clock source name strings from hwmod database.
(13) introduce new mechanism for getting struct clk associated with clock
source
names. this is achieved by adding clock alisases for all supported clock
sources.
(14) remove clock setup functions in mach-omap2 for populating struct clk
associated with all input clock sources because this is no longer needed with
above implementation.
(15) device names changed from dmtimer to omap-timer
(16) device index starts
[PATCH 0/2] Add optional mtd nand alignment for subpage reading
Subpage reading already provides a certain degree of alignment in that it aligns the reads to 16-bits if the bus is 16-bits wide. For some situations this is not enough. For eample, the OMAP2 prefetch engine only works with u32 aligned buffers and read sizes. This patch set adds a mechanism to plug in an alignment function and provides an example using the omap2 nand driver. Comments welcome -- Charles -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] mtd: Add nand_base feature to align subpage read buffers
Some nand controllers (eg. omap2) need to have their buffers u32 aligned
to use high speed transfer mechanisms.
This commit provides a way to plug in an alignment function and provides a
32-bit algnment function.
Signed-off-by: Charles Manning cdhmann...@gmail.com
---
drivers/mtd/nand/nand_base.c | 22 +-
include/linux/mtd/nand.h |5 +++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 1f75a1b..e8c2432 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1156,6 +1156,22 @@ static int nand_read_page_swecc(struct mtd_info *mtd,
struct nand_chip *chip,
}
/**
+ * nand_align_subpage32 - function to align subpage read to 32-bits
+ * @mtd: mtd info structure
+ * @buf: pointer to pointer of buffer that needs to be aligned
+ * @len: pointer to length that needs to be aligned.
+ */
+
+void nand_align_subpage32(uint8_t **buf, int *len)
+{
+ int diff = (int)(*buf) 3;
+ *buf = *buf - diff;
+ *len = *len + diff;
+ *len = (*len + 3) ~3;
+}
+EXPORT_SYMBOL(nand_align_subpage32);
+
+/**
* nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
* @mtd: mtd info structure
* @chip: nand chip info structure
@@ -1169,6 +1185,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct
nand_chip *chip,
int start_step, end_step, num_steps;
uint32_t *eccpos = chip-ecc.layout-eccpos;
uint8_t *p;
+ uint8_t *b;
int data_col_addr, i, gaps = 0;
int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
int busw = (chip-options NAND_BUSWIDTH_16) ? 2 : 1;
@@ -1222,7 +1239,10 @@ static int nand_read_subpage(struct mtd_info *mtd,
struct nand_chip *chip,
chip-cmdfunc(mtd, NAND_CMD_RNDOUT,
mtd-writesize + aligned_pos, -1);
- chip-read_buf(mtd, chip-oob_poi[aligned_pos], aligned_len);
+ b = chip-oob_poi[aligned_pos];
+ if(chip-align_subpage)
+ chip-align_subpage(b, aligned_len);
+ chip-read_buf(mtd, b, aligned_len);
}
for (i = 0; i eccfrag_len; i++)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 63e17d0..6ea6177 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -474,6 +474,7 @@ struct nand_buffers {
* additional error status checks (determine if errors are
* correctable).
* @write_page:[REPLACEABLE] High-level page write function
+ * @align_subpage: [OPTIONAL] Aligns subpage read buffer.
*/
struct nand_chip {
@@ -501,7 +502,7 @@ struct nand_chip {
int status, int page);
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
const uint8_t *buf, int page, int cached, int raw);
-
+ void (*align_subpage)(uint8_t **buf, int *len);
int chip_delay;
unsigned int options;
@@ -597,7 +598,7 @@ extern int nand_erase_nand(struct mtd_info *mtd, struct
erase_info *instr,
int allowbbt);
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, uint8_t *buf);
-
+extern void nand_align_subpage32(uint8_t **buf, int *len);
/**
* struct platform_nand_chip - chip level device structure
* @nr_chips: max. number of chips to scan for
--
1.7.1.5.g49342
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[PATCH 2/2] omap2 nand: Align subpage reads.
Set align_subpage to align buffer to u32 to use the prefetch engine. Signed-off-by: Charles Manning cdhmann...@gmail.com --- drivers/mtd/nand/omap2.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index cd41c58..3630971 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -886,6 +886,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) #else info-nand.ecc.mode = NAND_ECC_SOFT; #endif + info-nand.align_subpage = nand_align_subpage32; /* DIP switches on some boards change between 8 and 16 bit * bus widths for flash. Try the other width if the first try fails. -- 1.7.1.5.g49342 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
