Re: [PATCH] mcspi: Add support for GPIO chip select lines
On Fri, Dec 24, 2010 at 01:05:56AM -0500, Ben Gamari wrote: On Thu, 23 Dec 2010 20:28:19 -0700, Grant Likely grant.lik...@secretlab.ca wrote: On Thu, Dec 23, 2010 at 09:27:20PM -0500, Ben Gamari wrote: I understand your concerns, but I'm not sure how to satisfy them without crippling the design's ability to accomodate my use-case. I can't pass a GPIO line per spi_board_info since in my case of a multiplexed CS configuration a single pin's state does not uniquely determine the desired CS. The only other option I can think of is that we somehow provide a list of GPIOs for each bus and map the CS numbers to permutations of GPIO states. Unfortunately, I don't know of any suitable structure to put this GPIO list in. Perhaps I'm missing something obvious? Close, but not quite. Assign one gpio number to each cs state, and write a gpio controller driver that maps the linux-gpio number to the physical gpio state permutation. The mapping from gpio# to ss# is 1:1, but the driver behind the gpio# can do whatever you need it to do. I see. I'm still not convinced that this is the route to take, however. It seems like this virtual gpio interface is not only pretty clunky (simple board file glue turns into an entire gpio chip driver), it seems like this is a very inaccurate and not very useful way to expose a multiplexed CS configuration; e.g. what is this chip driver to do if the user tries to set two CS pins at once? (Sorry for the really laggy reply) I don't see it being that big a deal. gpio drivers are pretty lightweight and it is fine to have domain-specific limitations on how gpios for a particular gpio controller behave. In your example, if the hardware doesn't support enabling 2 CS pins at once, then you make a choice, either setting one when the other is already set simply does not work; or it could reset the other state. Either choice would be fine. The SPI driver must do the right thing regardless and deselect the previous CS line before enabling a new one. The other alternative would be to implement a new SPI chipselect common infrastructure, but IMO, that would just end up looking like a duplication of the gpio infrastructure. Regardless, my point still stands, platform callbacks for what amounts to gpio manipulations doesn't make a whole lot of sense. Is there precedent for using the GPIO subsystem in this way? Yes, in drivers/spi look at mpc52xx_spi.c, davinci_spi.c, ath79_spi.c, atmel_spi.c, and many more. Grep for gpio in drivers/spi. g. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] omap4: Fix ULPI PHY init for ES1.0 SDP (Re: 4430SDP boot failure)
Tony, -Original Message- From: Santosh Shilimkar [mailto:santosh.shilim...@ti.com] Sent: Thursday, February 03, 2011 2:13 PM To: Tony Lindgren Cc: Anand Gadiyar; Russell King - ARM Linux; linux-arm- ker...@lists.infradead.org; linux-omap@vger.kernel.org; Keshava Munegowda; Felipe Balbi Subject: RE: [PATCH] omap4: Fix ULPI PHY init for ES1.0 SDP (Re: 4430SDP boot failure) -Original Message- From: Tony Lindgren [mailto:t...@atomide.com] Sent: Thursday, February 03, 2011 1:19 AM To: Santosh Shilimkar Cc: Anand Gadiyar; Russell King - ARM Linux; linux-arm- ker...@lists.infradead.org; linux-omap@vger.kernel.org; Keshava Munegowda; Felipe Balbi Subject: Re: [PATCH] omap4: Fix ULPI PHY init for ES1.0 SDP (Re: 4430SDP boot failure) * Santosh Shilimkar santosh.shilim...@ti.com [110201 22:04]: It's a ES1.0 blaze, with the patch below it reboots early during the boot. I also have to disable omap_l2_cache_init on this board to get it to boot. Do you still get this problem with 'omap_l2_cache_init' ? As reported earlier, we don't see this issue on ES1.0 SDP. Yeah I do, it rarely makes it to the userspace. Works reliably if I disable omap_l2_cache_init. Ok. I shall try few experiments and try to reproduce it Not sure if it's the same issue but I managed to reproduce the issue on ES2.0 itself. And after some experiments, it boiled down to the V6 and V7 issue. By disabling OMAP2 from the build, everything was fine again. Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/6] ARM: move cache/processor/fault glue to separate include files
On Fri, Feb 11, 2011 at 06:52:14PM -0800, Colin Cross wrote: Acked-by: Colin Cross ccr...@android.com Tested on Tegra 2. Thanks, I'll take these as Tested-by's. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] omap iommu: print module name on error messages
OMAP IOMMU generic layer doesn't need ot print function name during
error messages. Print module name instead which is more useful.
Signed-off-by: David Cohen daco...@gmail.com
---
arch/arm/plat-omap/iommu.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index b1107c0..f55f458 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -806,7 +806,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
iopgd = iopgd_offset(obj, da);
if (!iopgd_is_table(*iopgd)) {
- dev_err(obj-dev, %s: da:%08x pgd:%p *pgd:%08x\n, __func__,
+ dev_err(obj-dev, %s: da:%08x pgd:%p *pgd:%08x\n, obj-name,
da, iopgd, *iopgd);
return IRQ_NONE;
}
@@ -814,7 +814,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
iopte = iopte_offset(iopgd, da);
dev_err(obj-dev, %s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n,
- __func__, da, iopgd, *iopgd, iopte, *iopte);
+ obj-name, da, iopgd, *iopgd, iopte, *iopte);
return IRQ_NONE;
}
--
1.7.1
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Re: [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
On Fri, Feb 4, 2011 at 11:17, Shweta Gulati shweta.gul...@ti.com wrote:
From: Thara Gopinath th...@ti.com
Gentle ping - folks after 8 days no comments, does this rev address
all previous comments? if so, it might be good to get some acks ;)
Regards,
Nishanth Menon
Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
default expects that OMAP's I2C_SR is plugged in to TWL's I2C
and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected,
the board files are expected to call omap3_twl_set_sr_bit(false) to
ensure that I2C_SR path is not set for voltage control and prevent
the default behavior of omap3_twl_init.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
This patch is based on LO PM Branch and Smartreflex has been
tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
OMAP2430 SDP.
arch/arm/mach-omap2/omap_twl.c | 61
arch/arm/mach-omap2/pm.h | 1 +
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b..87e07da 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
static bool is_offset_valid;
static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool __initdata twl_sr_enable_autoinit;
+#define TWL4030_DCDC_GLOBAL_CFG 0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
static unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+ * The smartreflex bit on twl4030 specifies if the setting of voltage
+ * is done over the I2C_SR path. Since this setting is independent of
+ * the actual usage of smartreflex AVS module, we enable TWL SR bit
+ * by default irrespective of whether smartreflex AVS module is
enabled
+ * on the OMAP side or not. This is because without this bit enabled,
+ * the voltage scaling through vp forceupdate/bypass mechanism of
+ * voltage scaling will not function on TWL over I2C_SR.
+ */
+ if (!twl_sr_enable_autoinit)
+ omap3_twl_set_sr_bit(true);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
@@ -277,3 +296,45 @@ int __init omap3_twl_init(void)
return 0;
}
+
+/**
+ * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
+ * @enable: enable SR mode in twl or not
+ *
+ * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
+ * voltage scaling through OMAP SR works. Else, the smartreflex bit
+ * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
+ * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
+ * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared (enable = false).
+ *
+ * Returns 0 on sucess, error is returned if I2C read/write fails.
+ */
+int __init omap3_twl_set_sr_bit(bool enable)
+{
+ u8 temp;
+ int ret;
+ if (twl_sr_enable_autoinit)
+ pr_warning(%s: unexpected multiple calls\n, __func__);
+
+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (ret)
+ goto err;
+
+ if (enable)
+ temp |= SMARTREFLEX_ENABLE;
+ else
+ temp = ~SMARTREFLEX_ENABLE;
+
+ ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (!ret) {
+ twl_sr_enable_autoinit = true;
+ return 0;
+ }
+err:
+ pr_err(%s: Error access to TWL4030 (%d)\n, __func__, ret);
+ return ret;
+}
+
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 39580e6..797bfd1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void)
{}
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
--
1.7.0.4
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[RFC/PATCH 0/3] IOMMU fault callback support
Hi, These are RFC patches. They're intended to add fault callback support so IOMMU users can debug or react when a fault happens. IOMMU faults might be very difficult to reproduce and then to figure out the source of the problem. Currently IOMMU driver prints not so useful debug message and does not notice user about such issue. With a fault callback, IOMMU user may debug much more useful information and/or react to go back to a valid state or, in worse cases, to leave device in a state where it's still possible to use it and proceed with some investigation. Comments are welcome. Br, David --- David Cohen (3): OMAP: IOMMU: Add generic IOMMU errors code OMAP2+: IOMMU: change OMAP2+ error message to dev_dbg() OMAP: IOMMU: add support to callback during fault handling arch/arm/mach-omap2/iommu2.c| 23 ++--- arch/arm/plat-omap/include/plat/iommu.h | 15 ++- arch/arm/plat-omap/iommu.c | 41 --- 3 files changed, 70 insertions(+), 9 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC/PATCH 1/3] OMAP: IOMMU: Add generic IOMMU errors code
Generic IOMMU errors code are necessary to handle errors on generic
layer.
Signed-off-by: David Cohen daco...@gmail.com
---
arch/arm/plat-omap/include/plat/iommu.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/iommu.h
b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d6..71f369d 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -109,6 +109,13 @@ struct iommu_platform_data {
u32 da_end;
};
+/* IOMMU errors */
+#define OMAP_IOMMU_ERR_TLB_MISS(1 0)
+#define OMAP_IOMMU_ERR_TRANS_FAULT (1 1)
+#define OMAP_IOMMU_ERR_EMU_MISS(1 2)
+#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 3)
+#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 4)
+
#if defined(CONFIG_ARCH_OMAP1)
#error iommu for this processor not implemented yet
#else
--
1.7.1
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[RFC/PATCH 2/3] OMAP2+: IOMMU: change OMAP2+ error message to dev_dbg()
IOMMU upper layer is already printing error message. OMAP2+ specific
layer may print error message only for debug purpose.
Signed-off-by: David Cohen daco...@gmail.com
---
arch/arm/mach-omap2/iommu2.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 14ee686..641f54a 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -163,7 +163,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
da = iommu_read_reg(obj, MMU_FAULT_AD);
*ra = da;
- dev_err(obj-dev, %s:\tda:%08x , __func__, da);
+ dev_dbg(obj-dev, %s:\tda:%08x , __func__, da);
for (i = 0; i ARRAY_SIZE(err_msg); i++) {
if (stat (1 i))
--
1.7.1
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[RFC/PATCH 3/3] OMAP: IOMMU: add support to callback during fault handling
Add support to register a callback for IOMMU fault situations. Drivers using
IOMMU module might want to be informed when such errors happen in order to
debug it or react.
Signed-off-by: David Cohen daco...@gmail.com
---
arch/arm/mach-omap2/iommu2.c| 21 +--
arch/arm/plat-omap/include/plat/iommu.h |8 +-
arch/arm/plat-omap/iommu.c | 41 ---
3 files changed, 62 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 641f54a..d3f7871 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -143,10 +143,10 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool
on)
__iommu_set_twl(obj, false);
}
-static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
+static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra, u32 *iommu_errs)
{
int i;
- u32 stat, da;
+ u32 stat, da, errs;
const char *err_msg[] = {
tlb miss,
translation fault,
@@ -157,8 +157,10 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32
*ra)
stat = iommu_read_reg(obj, MMU_IRQSTATUS);
stat = MMU_IRQ_MASK;
- if (!stat)
+ if (!stat) {
+ *iommu_errs = 0;
return 0;
+ }
da = iommu_read_reg(obj, MMU_FAULT_AD);
*ra = da;
@@ -171,6 +173,19 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32
*ra)
}
printk(\n);
+ errs = 0;
+ if (stat MMU_IRQ_TLBMISS)
+ errs |= OMAP_IOMMU_ERR_TLB_MISS;
+ if (stat MMU_IRQ_TRANSLATIONFAULT)
+ errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
+ if (stat MMU_IRQ_EMUMISS)
+ errs |= OMAP_IOMMU_ERR_EMU_MISS;
+ if (stat MMU_IRQ_TABLEWALKFAULT)
+ errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
+ if (stat MMU_IRQ_MULTIHITFAULT)
+ errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
+ *iommu_errs = errs;
+
iommu_write_reg(obj, stat, MMU_IRQSTATUS);
return stat;
diff --git a/arch/arm/plat-omap/include/plat/iommu.h
b/arch/arm/plat-omap/include/plat/iommu.h
index 71f369d..9e8c104 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -31,6 +31,7 @@ struct iommu {
struct clk *clk;
void __iomem*regbase;
struct device *dev;
+ void*fault_cb_priv;
unsigned intrefcount;
struct mutexiommu_lock; /* global for this whole object */
@@ -48,6 +49,7 @@ struct iommu {
struct mutexmmap_lock; /* protect mmap */
int (*isr)(struct iommu *obj);
+ void (*fault_cb)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
void *ctx; /* iommu context: registres saved area */
u32 da_start;
@@ -83,7 +85,7 @@ struct iommu_functions {
int (*enable)(struct iommu *obj);
void (*disable)(struct iommu *obj);
void (*set_twl)(struct iommu *obj, bool on);
- u32 (*fault_isr)(struct iommu *obj, u32 *ra);
+ u32 (*fault_isr)(struct iommu *obj, u32 *ra, u32 *iommu_errs);
void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -166,6 +168,10 @@ extern size_t iopgtable_clear_entry(struct iommu *obj, u32
iova);
extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
extern struct iommu *iommu_get(const char *name);
extern void iommu_put(struct iommu *obj);
+extern int iommu_set_fault_callback(const char *name,
+ void (*fault_cb)(struct iommu *obj, u32 da,
+u32 errs, void *priv),
+ void *fault_cb_priv);
extern void iommu_save_ctx(struct iommu *obj);
extern void iommu_restore_ctx(struct iommu *obj);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index f55f458..7761eab 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -163,9 +163,9 @@ static u32 get_iopte_attr(struct iotlb_entry *e)
return arch_iommu-get_pte_attr(e);
}
-static u32 iommu_report_fault(struct iommu *obj, u32 *da)
+static u32 iommu_report_fault(struct iommu *obj, u32 *da, u32 *iommu_errs)
{
- return arch_iommu-fault_isr(obj, da);
+ return arch_iommu-fault_isr(obj, da, iommu_errs);
}
static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
@@ -780,7 +780,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
*/
static irqreturn_t iommu_fault_handler(int irq, void *data)
{
- u32 stat, da;
+ u32 stat, da, errs;
u32 *iopgd, *iopte;
int err = -EIO;
struct iommu *obj = data;
@@ -796,11 +796,17 @@ static irqreturn_t iommu_fault_handler(int irq, void
*data)
return IRQ_HANDLED;
How to enable dvfs in omap.
Hi all, I am using omap 2.6.37 running overo board. I have enabled the following option in the kernel menunconfig, CPU Power Management --- │ │ [*] CPU Frequency scaling │ │ [ ] Enable CPUfreq debugging │ │ * CPU frequency translation statistics │ │ [*] CPU frequency translation statistics details │ │ Default CPUFreq governor (ondemand) --- │ │ -*- 'performance' governor │ │ M 'powersave' governor │ │ * 'userspace' governor for userspace frequency scaling │ │ -*- 'ondemand' cpufreq policy governor │ │ * 'conservative' cpufreq governor │ │ [ ] CPU idle PM support but still I could find the sys and entry in /sys/devices/system/cpu/cpufreq/ directory. Could some one help me to enable DVFS. root@overo:/sys/devices/system/cpu# ls cpu0 kernel_max online possible cpufreq offline perf_events present root@overo:/sys/devices/system/cpu# cd cpu0/ root@overo:/sys/devices/system/cpu/cpu0# ls crash_notes root@overo:/sys/devices/system/cpu/cpu0# cd .. root@overo:/sys/devices/system/cpu# cd cpufreq/ root@overo:/sys/devices/system/cpu/cpufreq# ls root@overo:/sys/devices/system/cpu/cpufreq# -- Regards, Mohamed Thalib H -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: How to enable dvfs in omap.
-Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Mohamed Thalib H Sent: Saturday, February 12, 2011 4:20 PM To: OMAP-KML Subject: How to enable dvfs in omap. Hi all, I am using omap 2.6.37 running overo board. I have enabled the following option in the kernel menunconfig, CPU Power Management --- │ │ [*] CPU Frequency scaling │ │ [ ] Enable CPUfreq debugging │ │ * CPU frequency translation statistics │ │ [*] CPU frequency translation statistics details │ │ Default CPUFreq governor (ondemand) --- │ │ -*- 'performance' governor │ │ M 'powersave' governor │ │ * 'userspace' governor for userspace frequency scaling │ │ -*- 'ondemand' cpufreq policy governor │ │ * 'conservative' cpufreq governor │ │ [ ] CPU idle PM support but still I could find the sys and entry in /sys/devices/system/cpu/cpufreq/ directory. Could some one help me to enable DVFS. That's because tts not supported yet. You may want to look at this[1] series which is in progress to enable the support. Regards, Santosh [1] [PATCH 00/13] OMAP: Basic DVFS Framework http://www.spinics.net/lists/linux-omap/msg44393.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] OMAP: IOMMU: add missing function declaration
Function declaration 'iopgtable_lookup_entry' is missing from header file. Signed-off-by: David Cohen daco...@gmail.com --- arch/arm/plat-omap/include/plat/iommu.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 9e8c104..5a2475f 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -163,6 +163,8 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); extern void flush_iotlb_all(struct iommu *obj); extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); +extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, + u32 **ppte); extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: How to enable dvfs in omap.
Hi Santosh, Thanks for the help . Regareds, Mohamed Thalib H. On Saturday 12 February 2011 04:27 PM, Santosh Shilimkar wrote: -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Mohamed Thalib H Sent: Saturday, February 12, 2011 4:20 PM To: OMAP-KML Subject: How to enable dvfs in omap. Hi all, I am using omap 2.6.37 running overo board. I have enabled the following option in the kernel menunconfig, CPU Power Management --- │ │ [*] CPU Frequency scaling │ │ [ ] Enable CPUfreq debugging │ │* CPU frequency translation statistics │ │ [*] CPU frequency translation statistics details │ │ Default CPUFreq governor (ondemand) --- │ │ -*- 'performance' governor │ │M 'powersave' governor │ │* 'userspace' governor for userspace frequency scaling │ │ -*- 'ondemand' cpufreq policy governor │ │* 'conservative' cpufreq governor │ │ [ ] CPU idle PM support but still I could find the sys and entry in /sys/devices/system/cpu/cpufreq/ directory. Could some one help me to enable DVFS. That's because tts not supported yet. You may want to look at this[1] series which is in progress to enable the support. Regards, Santosh [1] [PATCH 00/13] OMAP: Basic DVFS Framework http://www.spinics.net/lists/linux-omap/msg44393.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] omap2plus: omap4: Set NR_CPU to 2 instead of default 4
The omap2plus_defconfig picks default NR_CPU value as 4 which isn't correct for OMAP4430. Available CPUs are ony 2, so fix the same. Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com --- arch/arm/configs/omap2plus_defconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index ae890ca..019fb7c 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y +CONFIG_NR_CPUS=2 # CONFIG_LOCAL_TIMERS is not set CONFIG_AEABI=y CONFIG_LEDS=y -- 1.6.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception
On OMAP4430 ES1.0 the local timers are gated by security. Enable the
CONFIG_LOCAL_TIMERS for omap2plus build and handle the OMAP4430 es1.0
exception case.
This patch has dependency on the first patch in this series.
ARM: smp: Select local timers vs dummy timer support runtime
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mach-omap2/timer-mpu.c |4
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1a2cf62..f285dd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,6 +44,7 @@ config ARCH_OMAP4
depends on ARCH_OMAP2PLUS
select CPU_V7
select ARM_GIC
+ select LOCAL_TIMERS
select PL310_ERRATA_588369
select ARM_ERRATA_720789
select ARCH_HAS_OPP
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 09c73dc..31c0ac4 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,6 +28,10 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+ /* Local timers are not supprted on OMAP4430 ES1.0 */
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ return -ENXIO;
+
evt-irq = OMAP44XX_IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
--
1.6.0.4
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[PATCH 5/5] omap4: Remove 'FIXME: omap44xx_sram_init not implemented'
The omap44xx_sram_init() implements functionality to push some
code on SRAM whenever the code can't be executed from external
memory. The low power and DVFS code can be executed from
external DDR itself thanks to OMAP4 memory controller hardware
support. So on OMAP4, sram_push kind of functionality isn't needed.
Hence remove the FIXME warning added for implementing sram push
feature on OMAP4.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/plat-omap/sram.c | 16
1 files changed, 0 insertions(+), 16 deletions(-)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e26e504..2d7bded 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
}
#endif
-#ifdef CONFIG_ARCH_OMAP4
-static int __init omap44xx_sram_init(void)
-{
- printk(KERN_ERR FIXME: %s not implemented\n, __func__);
-
- return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
- return 0;
-}
-#endif
-
int __init omap_sram_init(void)
{
omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
omap243x_sram_init();
else if (cpu_is_omap34xx())
omap34xx_sram_init();
- else if (cpu_is_omap44xx())
- omap44xx_sram_init();
return 0;
}
--
1.6.0.4
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[PATCH 0/5] ARM: omap4 related fixes for 2.6.39
The series mainly does below - Makes ARM local timers selection runtime instead of compile time. - Enables the LOCAL_TIMER support for OMAP4430 - Add and enable PL310 Errata for flush by Way - Fixes the NR_CPU value in omap2plus config - Removes the un-necessary omap44xx_sram_init FIXME Boot tested on OMAP4430 ES1.0 and ES2.X silicons. The following changes since commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d: Linus Torvalds (1): Linux 2.6.38-rc4 are available in the git repository at: git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base.git omap4-misc_for.39 Santosh Shilimkar (5): ARM: smp: Select local timers vs dummy timer support runtime omap4: Enable ARM local timers with OMAP4430 es1.0 exception ARM: l2x0: Errata fix for flush by Way operation can cause data corruption omap2plus: omap4: Set NR_CPU to 2 instead of default 4 omap4: Remove 'FIXME: omap44xx_sram_init not implemented' arch/arm/Kconfig | 11 +++ arch/arm/configs/omap2plus_defconfig |1 + arch/arm/include/asm/localtimer.h|8 +++- arch/arm/kernel/smp.c|7 +++ arch/arm/mach-msm/timer.c|3 ++- arch/arm/mach-omap2/Kconfig |2 ++ arch/arm/mach-omap2/timer-mpu.c |7 ++- arch/arm/mach-realview/localtimer.c |3 ++- arch/arm/mach-s5pv310/localtimer.c |3 ++- arch/arm/mach-shmobile/localtimer.c |3 ++- arch/arm/mach-tegra/localtimer.c |3 ++- arch/arm/mach-ux500/localtimer.c |3 ++- arch/arm/mach-vexpress/localtimer.c |3 ++- arch/arm/mm/cache-l2x0.c | 16 ++-- arch/arm/plat-omap/sram.c| 16 15 files changed, 54 insertions(+), 35 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption
PL310 implements the Clean Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean Invalidate
by Way operation.
Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/Kconfig| 11 +++
arch/arm/mach-omap2/Kconfig |1 +
arch/arm/mm/cache-l2x0.c| 16 ++--
3 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..2e6b879 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption of the
processor.
+config PL310_ERRATA_727915
+ bool Background Clean Invalidate by Way operation can cause data
corruption
+ depends on CACHE_L2X0 ARCH_OMAP4
+ help
+ PL310 implements the Clean Invalidate by Way L2 cache maintenance
+ operation (offset 0x7FC). This operation runs in background so that
+ PL310 can handle normal accesses while it is in progress. Under very
+ rare circumstances, due to this erratum, write data can be lost when
+ PL310 treats a cacheable write transaction during a Clean
+ Invalidate by Way operation Note that this errata uses Texas
+ Instrument's secure monitor api to implement the work around.
endmenu
source arch/arm/common/Kconfig
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..1f0ff75 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -46,6 +46,7 @@ config ARCH_OMAP4
select ARM_GIC
select LOCAL_TIMERS
select PL310_ERRATA_588369
+ select PL310_ERRATA_727915
select ARM_ERRATA_720789
select ARCH_HAS_OPP
select PM_OPP if PM
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..c7c8fbe 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,7 +67,7 @@ static inline void l2x0_inv_line(unsigned long addr)
writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
static void debug_writel(unsigned long val)
{
extern void omap_smc1(u32 fn, u32 arg);
@@ -78,7 +78,14 @@ static void debug_writel(unsigned long val)
*/
omap_smc1(0x100, val);
}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+#endif
+#ifdef CONFIG_PL310_ERRATA_588369
static inline void l2x0_flush_line(unsigned long addr)
{
void __iomem *base = l2x0_base;
@@ -91,11 +98,6 @@ static inline void l2x0_flush_line(unsigned long addr)
}
#else
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
static inline void l2x0_flush_line(unsigned long addr)
{
void __iomem *base = l2x0_base;
@@ -119,9 +121,11 @@ static void l2x0_flush_all(void)
/* clean all ways */
spin_lock_irqsave(l2x0_lock, flags);
+ debug_writel(0x03);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
cache_sync();
+ debug_writel(0x00);
spin_unlock_irqrestore(l2x0_lock, flags);
}
--
1.6.0.4
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[PATCH 1/5] ARM: smp: Select local timers vs dummy timer support runtime
The current code support of dummy timers in absence of local
timer is compile time. This is an attempt to convert it to runtime
so that on few SOC version if the local timers aren't supported
kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from
this limitation.
This patch should not have any functional impact on affected
files.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Russell King li...@arm.linux.org.uk
Cc: David Brown dav...@codeaurora.org
Cc: Daniel Walker dwal...@codeaurora.org
Cc: Bryan Huntsman bry...@codeaurora.org
Cc: Tony Lindgren t...@atomide.com
Cc: Kukjin Kim kgene@samsung.com
Cc: Paul Mundt let...@linux-sh.org
Cc: Magnus Damm magnus.d...@gmail.com
Cc: Colin Cross ccr...@android.com
Cc: Erik Gilling konk...@android.com
Cc: Srinidhi Kasagar srinidhi.kasa...@stericsson.com
Cc: Linus Walleij linus.wall...@stericsson.com
---
arch/arm/include/asm/localtimer.h |8 +++-
arch/arm/kernel/smp.c |7 +++
arch/arm/mach-msm/timer.c |3 ++-
arch/arm/mach-omap2/timer-mpu.c |3 ++-
arch/arm/mach-realview/localtimer.c |3 ++-
arch/arm/mach-s5pv310/localtimer.c |3 ++-
arch/arm/mach-shmobile/localtimer.c |3 ++-
arch/arm/mach-tegra/localtimer.c|3 ++-
arch/arm/mach-ux500/localtimer.c|3 ++-
arch/arm/mach-vexpress/localtimer.c |3 ++-
10 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/localtimer.h
b/arch/arm/include/asm/localtimer.h
index 6bc63ab..080d74f 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -44,8 +44,14 @@ int local_timer_ack(void);
/*
* Setup a local timer interrupt for a CPU.
*/
-void local_timer_setup(struct clock_event_device *);
+int local_timer_setup(struct clock_event_device *);
+#else
+
+static inline int local_timer_setup(struct clock_event_device *evt)
+{
+ return -ENXIO;
+}
#endif
#endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 4539ebc..7b9cc53 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -474,13 +474,12 @@ static void smp_timer_broadcast(const struct cpumask
*mask)
#define smp_timer_broadcastNULL
#endif
-#ifndef CONFIG_LOCAL_TIMERS
static void broadcast_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
}
-static void local_timer_setup(struct clock_event_device *evt)
+static void dummy_timer_setup(struct clock_event_device *evt)
{
evt-name = dummy_timer;
evt-features = CLOCK_EVT_FEAT_ONESHOT |
@@ -492,7 +491,6 @@ static void local_timer_setup(struct clock_event_device
*evt)
clockevents_register_device(evt);
}
-#endif
void __cpuinit percpu_timer_setup(void)
{
@@ -502,7 +500,8 @@ void __cpuinit percpu_timer_setup(void)
evt-cpumask = cpumask_of(cpu);
evt-broadcast = smp_timer_broadcast;
- local_timer_setup(evt);
+ if (local_timer_setup(evt))
+ dummy_timer_setup(evt);
}
#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index c105d28..ae85aa9 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -255,7 +255,7 @@ static void __init msm_timer_init(void)
}
#ifdef CONFIG_SMP
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
struct msm_clock *clock = msm_clocks[MSM_GLOBAL_TIMER];
@@ -287,6 +287,7 @@ void __cpuinit local_timer_setup(struct clock_event_device
*evt)
gic_enable_ppi(clock-irq.irq);
clockevents_register_device(evt);
+ return 0;
}
inline int local_timer_ack(void)
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 954682e..09c73dc 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -26,9 +26,10 @@
/*
* Setup the local clock events for a CPU.
*/
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
evt-irq = OMAP44XX_IRQ_LOCALTIMER;
twd_timer_setup(evt);
+ return 0;
}
diff --git a/arch/arm/mach-realview/localtimer.c
b/arch/arm/mach-realview/localtimer.c
index 60b4e11..aca29ce 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -19,8 +19,9 @@
/*
* Setup the local clock events for a CPU.
*/
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
evt-irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
+ return 0;
}
diff --git a/arch/arm/mach-s5pv310/localtimer.c
b/arch/arm/mach-s5pv310/localtimer.c
index 2784036..8239c6a 100644
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ b/arch/arm/mach-s5pv310/localtimer.c
@@ -18,8 +18,9 @@
/*
* Setup the local clock events for a CPU.
*/
-void __cpuinit
Re: How to enable dvfs in omap.
Mohamed Thalib H wrote, on 02/12/2011 04:42 PM: Hi Santosh, Thanks for the help . Regareds, Mohamed Thalib H. On Saturday 12 February 2011 04:27 PM, Santosh Shilimkar wrote: -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Mohamed Thalib H Sent: Saturday, February 12, 2011 4:20 PM To: OMAP-KML Subject: How to enable dvfs in omap. Hi all, I am using omap 2.6.37 running overo board. I have enabled the following option in the kernel menunconfig, CPU Power Management --- │ │ [*] CPU Frequency scaling │ │ [ ] Enable CPUfreq debugging │ │* CPU frequency translation statistics │ │ [*] CPU frequency translation statistics details │ │ Default CPUFreq governor (ondemand) --- │ │ -*- 'performance' governor │ │M 'powersave' governor │ │* 'userspace' governor for userspace frequency scaling │ │ -*- 'ondemand' cpufreq policy governor │ │* 'conservative' cpufreq governor │ │ [ ] CPU idle PM support but still I could find the sys and entry in /sys/devices/system/cpu/cpufreq/ directory. Could some one help me to enable DVFS. That's because tts not supported yet. You may want to look at this[1] series which is in progress to enable the support. Regards, Santosh [1] [PATCH 00/13] OMAP: Basic DVFS Framework http://www.spinics.net/lists/linux-omap/msg44393.html if you are interested, I rebased the last set with k.org and fixes from pm tree for development for smartreflex class 1.5 here: http://gitorious.org/linux-omap-nm-sr/linux-omap-sr/commits/dvfs git://gitorious.org/linux-omap-nm-sr/linux-omap-sr.git branch: dvfs -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: How to enable dvfs in omap.
On Saturday 12 February 2011 05:21 PM, Nishanth Menon wrote: Mohamed Thalib H wrote, on 02/12/2011 04:42 PM: Hi Santosh, Thanks for the help . Regareds, Mohamed Thalib H. On Saturday 12 February 2011 04:27 PM, Santosh Shilimkar wrote: -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Mohamed Thalib H Sent: Saturday, February 12, 2011 4:20 PM To: OMAP-KML Subject: How to enable dvfs in omap. Hi all, I am using omap 2.6.37 running overo board. I have enabled the following option in the kernel menunconfig, CPU Power Management --- │ │ [*] CPU Frequency scaling │ │ [ ] Enable CPUfreq debugging │ │* CPU frequency translation statistics │ │ [*] CPU frequency translation statistics details │ │ Default CPUFreq governor (ondemand) --- │ │ -*- 'performance' governor │ │M 'powersave' governor │ │* 'userspace' governor for userspace frequency scaling │ │ -*- 'ondemand' cpufreq policy governor │ │* 'conservative' cpufreq governor │ │ [ ] CPU idle PM support but still I could find the sys and entry in /sys/devices/system/cpu/cpufreq/ directory. Could some one help me to enable DVFS. That's because tts not supported yet. You may want to look at this[1] series which is in progress to enable the support. Regards, Santosh [1] [PATCH 00/13] OMAP: Basic DVFS Framework http://www.spinics.net/lists/linux-omap/msg44393.html if you are interested, I rebased the last set with k.org and fixes from pm tree for development for smartreflex class 1.5 here: http://gitorious.org/linux-omap-nm-sr/linux-omap-sr/commits/dvfs git://gitorious.org/linux-omap-nm-sr/linux-omap-sr.git branch: dvfs Thanks for your help Nishanth, Surely I will pull the git and checkout.. Regards, Thalib. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: State of LDP3430 platform
Another LDP3430 report... The LDP3430 seems to be getting there, but: 1. LCD screen seems wrong. The X display looks rather large, and flickery - looks like the LCD timing parameters are wrong. Some text disappears off the RHS. fbset reports: mode 240x320-510 # D: 48.001 MHz, H: 168.424 kHz, V: 510.375 Hz geometry 240 320 240 320 16 timings 20833 3 39 2 7 3 1 accel false rgba 5/11,6/5,5/0,0/0 kernel config: CONFIG_FB_OMAP=y CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 with the supplied kernel: mode 640x480-64 # D: 21.601 MHz, H: 31.396 kHz, V: 63.813 Hz geometry 640 480 640 640 16 timings 46295 40 4 8 2 4 2 accel false rgba 5/11,6/5,5/0,0/0 so the LCD timings in the kernel appear to be wrong for the panel on the LDP. What is 'CONFIG_FB_OMAP_LCD_VGA'? There's *no* help for this configuration option so god only knows what it's right setting should be. Please give it some help text to explain what it is and what it does. 2. Keyboard - numeric keys produce wrong ascii for their labelled function. This is from /dev/tty1 with X running: 1 gives nothing 2 gives 4 3 gives 7 4 gives 2 5 gives 5 6 gives 8 7 gives 3 8 gives nothing 9 gives 9 * gives nothing 0 gives E # gives nothing off-hook (green phone) gives 0 on-hook (red phone) gives 1b5b31397e Killing X and then running evtest on /dev/input/event1 doesn't return any events, neither does reading /dev/tty1 for the twl4030 keypad - the numeric keys are completely dead. /proc/interrupts shows no new interrupt counts when pressing the key for 'twl4030_keypad'. Unbinding/rebinding the twl4030 driver doesn't sort it out, neither does restarting X. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: State of LDP3430 platform
On Sat, Feb 12, 2011 at 04:02:16PM +, Russell King - ARM Linux wrote: Another LDP3430 report... The LDP3430 seems to be getting there, but: 1. LCD screen seems wrong. The X display looks rather large, and flickery - looks like the LCD timing parameters are wrong. Some text disappears off the RHS. fbset reports: mode 240x320-510 # D: 48.001 MHz, H: 168.424 kHz, V: 510.375 Hz geometry 240 320 240 320 16 timings 20833 3 39 2 7 3 1 accel false rgba 5/11,6/5,5/0,0/0 kernel config: CONFIG_FB_OMAP=y CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 with the supplied kernel: mode 640x480-64 # D: 21.601 MHz, H: 31.396 kHz, V: 63.813 Hz geometry 640 480 640 640 16 timings 46295 40 4 8 2 4 2 accel false rgba 5/11,6/5,5/0,0/0 so the LCD timings in the kernel appear to be wrong for the panel on the LDP. What is 'CONFIG_FB_OMAP_LCD_VGA'? There's *no* help for this configuration option so god only knows what it's right setting should be. Please give it some help text to explain what it is and what it does. LCD works better with FB_OMAP_LCD_VGA set, but why is this necessary? 2. Keyboard - numeric keys produce wrong ascii for their labelled function. This is from /dev/tty1 with X running: 1 gives nothing 2 gives 4 3 gives 7 4 gives 2 5 gives 5 6 gives 8 7 gives 3 8 gives nothing 9 gives 9 * gives nothing 0 gives E # gives nothing off-hook (green phone) gives 0 on-hook (red phone) gives 1b5b31397e Killing X and then running evtest on /dev/input/event1 doesn't return any events, neither does reading /dev/tty1 for the twl4030 keypad - the numeric keys are completely dead. /proc/interrupts shows no new interrupt counts when pressing the key for 'twl4030_keypad'. Unbinding/rebinding the twl4030 driver doesn't sort it out, neither does restarting X. 3. Touchscreen is dead, presumably because no devices are bound to ads7846 SPI driver. ls -al /sys/bus/spi/devices/ total 0 drwxr-xr-x 2 root root 0 Jan 1 01:02 . drwxr-xr-x 4 root root 0 Jan 1 01:02 .. lrwxrwxrwx 1 root root 0 Jan 1 01:02 spi1.0 - ../../../devices/platform/omap2_mcspi.1/spi1.0 is the only SPI device which appears, but is unbound. I'm sure this used to work at some point. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] Add recommended bpp for omap dss2 generic dpi panels
This series adds a mechanism for specifying a recommended bpp for generic dss2 dpi panels and adds a panel that uses this feature. The panel added is the 4.3 inch display that is sold with the Devkit8000. Daniel Morsing (2): omap: dss2: Add recommended bpp option for generic dpi panels omap3: devkit8000: Add and use 4.3 inch display arch/arm/mach-omap2/board-devkit8000.c |2 +- drivers/video/omap2/displays/panel-generic-dpi.c | 41 ++ 2 files changed, 42 insertions(+), 1 deletions(-) -- 1.7.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption
-Original Message- From: Andrei Warkentin [mailto:andr...@motorola.com] Sent: Saturday, February 12, 2011 11:20 PM To: Santosh Shilimkar Cc: linux-omap@vger.kernel.org; khil...@ti.com; t...@atomide.com; linux-arm-ker...@lists.infradead.org; Catalin Marinas Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption [] Can these PL310 errata fixes be made more generic? PL310 is present in non-OMAP platforms too, which lack the TI hypervisor. And these platforms might have the same PL310 rev, and suffer the same glitches. While ideally there is some kind of hypervisor_ops to modify the protected register, at the very least there should be the generic debug_write handling the I can write all PL310 regs case. If you're interested I have a patch someplace that tried to do this, hopefully I can still find it. They are kind of generic. If you look at it, the only change Which is arch specific is the implementation of debug_writel function. Today this code is not in generic PL310 code, but OMAP specific. May be we can make this as exported function pointer, which arch's can populate. Will that work for you ? Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption
On Sat, Feb 12, 2011 at 5:29 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
PL310 implements the Clean Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean Invalidate
by Way operation.
Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/Kconfig | 11 +++
arch/arm/mach-omap2/Kconfig | 1 +
arch/arm/mm/cache-l2x0.c | 16 ++--
3 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165..2e6b879 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,17 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption of the
processor.
+config PL310_ERRATA_727915
+ bool Background Clean Invalidate by Way operation can cause data
corruption
+ depends on CACHE_L2X0 ARCH_OMAP4
+ help
+ PL310 implements the Clean Invalidate by Way L2 cache maintenance
+ operation (offset 0x7FC). This operation runs in background so that
+ PL310 can handle normal accesses while it is in progress. Under very
+ rare circumstances, due to this erratum, write data can be lost when
+ PL310 treats a cacheable write transaction during a Clean
+ Invalidate by Way operation Note that this errata uses Texas
+ Instrument's secure monitor api to implement the work around.
endmenu
source arch/arm/common/Kconfig
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f285dd7..1f0ff75 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -46,6 +46,7 @@ config ARCH_OMAP4
select ARM_GIC
select LOCAL_TIMERS
select PL310_ERRATA_588369
+ select PL310_ERRATA_727915
select ARM_ERRATA_720789
select ARCH_HAS_OPP
select PM_OPP if PM
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..c7c8fbe 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,7 +67,7 @@ static inline void l2x0_inv_line(unsigned long addr)
writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
-#ifdef CONFIG_PL310_ERRATA_588369
+#if defined(CONFIG_PL310_ERRATA_588369) ||
defined(CONFIG_PL310_ERRATA_727915)
static void debug_writel(unsigned long val)
{
extern void omap_smc1(u32 fn, u32 arg);
@@ -78,7 +78,14 @@ static void debug_writel(unsigned long val)
*/
omap_smc1(0x100, val);
}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+#endif
+#ifdef CONFIG_PL310_ERRATA_588369
static inline void l2x0_flush_line(unsigned long addr)
{
void __iomem *base = l2x0_base;
@@ -91,11 +98,6 @@ static inline void l2x0_flush_line(unsigned long addr)
}
#else
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
static inline void l2x0_flush_line(unsigned long addr)
{
void __iomem *base = l2x0_base;
@@ -119,9 +121,11 @@ static void l2x0_flush_all(void)
/* clean all ways */
spin_lock_irqsave(l2x0_lock, flags);
+ debug_writel(0x03);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
cache_sync();
+ debug_writel(0x00);
spin_unlock_irqrestore(l2x0_lock, flags);
}
--
1.6.0.4
___
linux-arm-kernel mailing list
linux-arm-ker...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Can these PL310 errata fixes be made more generic? PL310 is present in
non-OMAP platforms too, which lack the TI hypervisor. And these
platforms might have the same PL310 rev, and suffer the same glitches.
While ideally there is some kind of hypervisor_ops to modify the
protected register, at the very least there should be the generic
debug_write handling the I can write all PL310 regs case. If
you're interested I have a patch someplace that tried to do this,
hopefully I can still find it.
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 3/3] OMAP4: clockdomain: Add wkup/sleep dependency support
On Fri, 11 Feb 2011, Rajendra Nayak wrote:
Does that sound okay to you?
Yep, that sounds better.
Here's an updated patch for the main code and the OMAP2/3 implementation.
Comments, testing welcome.
The stable integration tag with this change is
'integration-2.6.39-20110212-001' of git://git.pwsan.com/linux-integration
- Paul
From: Rajendra Nayak rna...@ti.com
Date: Tue, 8 Feb 2011 14:25:34 -0700
Subject: [PATCH] OMAP: clockdomain: Arch specific funcs to handle deps
Define the following architecture specific funtions for omap2/3
.clkdm_add_wkdep
.clkdm_del_wkdep
.clkdm_read_wkdep
.clkdm_clear_all_wkdeps
.clkdm_add_sleepdep
.clkdm_del_sleepdep
.clkdm_read_sleepdep
.clkdm_clear_all_sleepdeps
Convert the platform-independent framework to call these functions.
With this also move the clkdm lookups for all wkdep_srcs and
sleepdep_srcs at clkdm_init.
Signed-off-by: Rajendra Nayak rna...@ti.com
[p...@pwsan.com: fixed loop termination conditions in omap*_clkdm_clear_all_*();
thanks to Kevin Hilman for finding and helping fix those bugs; also
avoid re-resolving clockdomains during init; abstracted out clkdm_dep walk]
Cc: Kevin Hilman khil...@ti.com
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/clockdomain.c| 177 --
arch/arm/mach-omap2/clockdomain.h|6 +-
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 130
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |9 +-
arch/arm/mach-omap2/io.c |6 +-
6 files changed, 246 insertions(+), 84 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1c0c2b0..6b2824d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -102,8 +102,10 @@ obj-$(CONFIG_ARCH_OMAP4) +=
$(powerdomain-common) \
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
+ clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
+ clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomains44xx_data.o
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index f70b06a..895c153 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -287,6 +287,32 @@ static void _disable_hwsup(struct clockdomain *clkdm)
BUG();
}
+/**
+ * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
+ * @clkdm: clockdomain that we are resolving dependencies for
+ * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
+ *
+ * Iterates through @clkdm_deps, looking up the struct clockdomain named by
+ * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
+ * No return value.
+ */
+static void _resolve_clkdm_deps(struct clockdomain *clkdm,
+ struct clkdm_dep *clkdm_deps)
+{
+ struct clkdm_dep *cd;
+
+ for (cd = clkdm_deps; cd cd-clkdm_name; cd++) {
+ if (!omap_chip_is(cd-omap_chip))
+ continue;
+ if (cd-clkdm)
+ continue;
+ cd-clkdm = _clkdm_lookup(cd-clkdm_name);
+
+ WARN(!cd-clkdm, clockdomain: %s: could not find clkdm %s
while resolving dependencies - should never happen,
+clkdm-name, cd-clkdm_name);
+ }
+}
+
/* Public functions */
/**
@@ -333,7 +359,10 @@ void clkdm_init(struct clockdomain **clkdms,
else if (clkdm-flags CLKDM_CAN_DISABLE_AUTO)
omap2_clkdm_deny_idle(clkdm);
+ _resolve_clkdm_deps(clkdm, clkdm-wkdep_srcs);
clkdm_clear_all_wkdeps(clkdm);
+
+ _resolve_clkdm_deps(clkdm, clkdm-sleepdep_srcs);
clkdm_clear_all_sleepdeps(clkdm);
}
}
@@ -430,6 +459,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain
*clkdm)
int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
+ int ret = 0;
if (!cpu_is_omap24xx() !cpu_is_omap34xx()) {
pr_err(clockdomain: %s/%s: %s: not yet implemented\n,
@@ -441,21 +471,26 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct
clockdomain *clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1-wkdep_srcs);
- if (IS_ERR(cd)) {
+ if (IS_ERR(cd))
+ ret = PTR_ERR(cd);
+
+ if (!arch_clkdm || !arch_clkdm-clkdm_add_wkdep)
+ ret
RE: [PATCH 3/3] OMAP4: clockdomain: Add wkup/sleep dependency support
Here's the updated OMAP4 version.
The stable integration tag with this change is
'integration-2.6.39-20110212-002' of git://git.pwsan.com/linux-integration
- Paul
From: Rajendra Nayak rna...@ti.com
Date: Sat, 12 Feb 2011 15:32:47 -0700
Subject: [PATCH] OMAP4: clockdomain: Add wkup/sleep dependency support
Add OMAP4 platform specific implementation to support clkdm
wkup and sleep dependencies a.k.a static dependencies.
Signed-off-by: Rajendra Nayak rna...@ti.com
[p...@pwsan.com: removed comment about PRM; zero-prefixed STATICDEP
register offset; fixed loop termination condition in
omap4_clkdm_clear_all_wkup_sleep_deps(); thanks to Kevin Hilman for finding
and helping fix this bug]
Cc: Kevin Hilman khil...@deeprootsystems.com
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/clockdomain44xx.c | 60 +
arch/arm/mach-omap2/cm44xx.h |1 +
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c
b/arch/arm/mach-omap2/clockdomain44xx.c
index c0ccc47..a1a4ecd 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -12,8 +12,60 @@
* published by the Free Software Foundation.
*/
+#include linux/kernel.h
#include clockdomain.h
#include cminst44xx.h
+#include cm44xx.h
+
+static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
+ struct clockdomain *clkdm2)
+{
+ omap4_cminst_set_inst_reg_bits((1 clkdm2-dep_bit),
+ clkdm1-prcm_partition,
+ clkdm1-cm_inst, clkdm1-clkdm_offs +
+ OMAP4_CM_STATICDEP);
+ return 0;
+}
+
+static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
+ struct clockdomain *clkdm2)
+{
+ omap4_cminst_clear_inst_reg_bits((1 clkdm2-dep_bit),
+ clkdm1-prcm_partition,
+ clkdm1-cm_inst, clkdm1-clkdm_offs +
+ OMAP4_CM_STATICDEP);
+ return 0;
+}
+
+static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
+ struct clockdomain *clkdm2)
+{
+ return omap4_cminst_read_inst_reg_bits(clkdm1-prcm_partition,
+ clkdm1-cm_inst, clkdm1-clkdm_offs +
+ OMAP4_CM_STATICDEP,
+ (1 clkdm2-dep_bit));
+}
+
+static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
+{
+ struct clkdm_dep *cd;
+ u32 mask = 0;
+
+ for (cd = clkdm-wkdep_srcs; cd cd-clkdm_name; cd++) {
+ if (!omap_chip_is(cd-omap_chip))
+ continue;
+ if (!cd-clkdm)
+ continue; /* only happens if data is erroneous */
+
+ mask |= 1 cd-clkdm-dep_bit;
+ atomic_set(cd-wkdep_usecount, 0);
+ }
+
+ omap4_cminst_clear_inst_reg_bits(mask, clkdm-prcm_partition,
+ clkdm-cm_inst, clkdm-clkdm_offs +
+ OMAP4_CM_STATICDEP);
+ return 0;
+}
static int omap4_clkdm_sleep(struct clockdomain *clkdm)
{
@@ -68,6 +120,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain
*clkdm)
}
struct clkdm_ops omap4_clkdm_operations = {
+ .clkdm_add_wkdep= omap4_clkdm_add_wkup_sleep_dep,
+ .clkdm_del_wkdep= omap4_clkdm_del_wkup_sleep_dep,
+ .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
+ .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
+ .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
+ .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
+ .clkdm_read_sleepdep= omap4_clkdm_read_wkup_sleep_dep,
+ .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
.clkdm_sleep= omap4_clkdm_sleep,
.clkdm_wakeup = omap4_clkdm_wakeup,
.clkdm_allow_idle = omap4_clkdm_allow_idle,
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 48fc3f4..0b87ec8 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -21,6 +21,7 @@
#include cm.h
#define OMAP4_CM_CLKSTCTRL 0x
+#define OMAP4_CM_STATICDEP 0x0004
/* Function prototypes */
# ifndef __ASSEMBLER__
--
1.7.2.3
--
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Re: [PATCH 1/7] omap: clock: Check for enable/disable ops support
On Tue, 8 Feb 2011, Rajendra Nayak wrote: Check if enable/disable operations are supported for a given clock node before attempting to call them. Signed-off-by: Rajendra Nayak rna...@ti.com Thanks, queued in branch 'clk_a_2.6.39' of git://git.pwsan.com/linux-2.6. This patch is integrated as part of the tag 'tmp-integration-2.6.39-20110212-003' and the branch 'integration-2.6.39' of git://git.pwsan.com/linux-integration. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption
On Sat, Feb 12, 2011 at 11:59 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
-Original Message-
From: Andrei Warkentin [mailto:andr...@motorola.com]
Sent: Saturday, February 12, 2011 11:20 PM
To: Santosh Shilimkar
Cc: linux-omap@vger.kernel.org; khil...@ti.com; t...@atomide.com;
linux-arm-ker...@lists.infradead.org; Catalin Marinas
Subject: Re: [PATCH 3/5] ARM: l2x0: Errata fix for flush by Way
operation can cause data corruption
[]
Can these PL310 errata fixes be made more generic? PL310 is present
in
non-OMAP platforms too, which lack the TI hypervisor. And these
platforms might have the same PL310 rev, and suffer the same
glitches.
While ideally there is some kind of hypervisor_ops to modify the
protected register, at the very least there should be the generic
debug_write handling the I can write all PL310 regs case. If
you're interested I have a patch someplace that tried to do this,
hopefully I can still find it.
They are kind of generic. If you look at it, the only change
Which is arch specific is the implementation of debug_writel function.
Today this code is not in generic PL310 code, but
OMAP specific.
May be we can make this as exported function pointer, which
arch's can populate.
Will that work for you ?
Regards,
Santosh
Ie something like the following what do you think???
#define L2X0_DCR (0xF40)
static void debug_writel(unsigned long val)
{
#ifdef CONFIG_ARCH_OMAP4
omap_smc1(0x100, val);
#else
writel_relaxed(val, l2x0_base + L2X0_DCR);
#endif
}
...
...
/* clean all ways */
spin_lock_irqsave(l2x0_lock, flags);
#ifdef CONFIG_PL310_ERRATA_727915
debug_writel(DCR_DWB | DCR_DCL); not 0x3, but self-documenting
#endif
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
cache_sync();
#ifdef CONFIG_PL310_ERRATA_727915
debug_writel(0x00);
#endif
spin_unlock_irqrestore(l2x0_lock, flags);
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Re: [PATCH 2/7] omap3: dpll: Populate clkops for dpll1_ck
On Tue, 8 Feb 2011, Rajendra Nayak wrote: DPLL1 on omap3 is very similar to the rest of the non-core dpll's. Hence populate clkops_omap3_noncore_dpll_ops as the clkops for it, instead of the currently populated clkops_null. Signed-off-by: Rajendra Nayak rna...@ti.com Thanks, queued in branch 'clk_a_2.6.39' of git://git.pwsan.com/linux-2.6. This patch is integrated as part of the tag 'tmp-integration-2.6.39-20110212-003' and the branch 'integration-2.6.39' of git://git.pwsan.com/linux-integration. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops
Hi Rajendra
On Thu, 10 Feb 2011, Rajendra Nayak wrote:
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..6889c5a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
return ret;
}
+void omap_clk_enable_autoidle(void)
+{
+ struct clk *c;
+
+ mutex_lock(clocks_mutex);
With the current OMAP clock code, it isn't sufficient to use a mutex here.
Your underlying functions have to read, modify, and write a register that
is also touched by clock functions like clk_set_rate(), which take the
clockfw spinlock and not the mutex. This is potentially racy and could
result in inconsistencies between the internal clock tree data and the
hardware settings.
While it is true that these functions are currently only called during PM
init, I'd rather not commit code that is subject to known races into the
tree.
So, before applying this patch, the mutexes have been converted into
spinlocks. I would appreciate it if you could help test this. Updated
patch follows, which has been queued for 2.6.39 as part of the
'clk_autoidle_a_2.6.39' branch of git://git.pwsan.com/linux-2.6.
- Paul
From: Rajendra Nayak rna...@ti.com
Date: Thu, 10 Feb 2011 14:46:36 +0530
Subject: [PATCH] omap: clock: Add allow_idle/deny_idle support in clkops
On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.
These function pointers can be populated for any clock
node which supports hardware level autogating.
Also add 2 new functions (omap_clk_enable_auotidle and
omap_clk_disable_autoidle) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.
Signed-off-by: Rajendra Nayak rna...@ti.com
[p...@pwsan.com: use spinlock rather than mutex due to race]
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/plat-omap/clock.c | 28
arch/arm/plat-omap/include/plat/clock.h |6 ++
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..0cdac8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
return ret;
}
+void omap_clk_enable_autoidle(void)
+{
+ struct clk *c;
+ unsigned long flags;
+
+ spin_lock_irqsave(clockfw_lock, flags);
+
+ list_for_each_entry(c, clocks, node)
+ if (c-ops-allow_idle)
+ c-ops-allow_idle(c);
+
+ spin_lock_irqrestore(clockfw_lock, flags);
+}
+
+void omap_clk_disable_autoidle(void)
+{
+ struct clk *c;
+ unsigned long flags;
+
+ spin_lock_irqsave(clockfw_lock, flags);
+
+ list_for_each_entry(c, clocks, node)
+ if (c-ops-deny_idle)
+ c-ops-deny_idle(c);
+
+ spin_lock_irqrestore(clockfw_lock, flags);
+}
+
/*
* Low level helpers
*/
diff --git a/arch/arm/plat-omap/include/plat/clock.h
b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..167f1e0f 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
* @disable: fn ptr that enables the current clock in hardware
* @find_idlest: function returning the IDLEST register for the clock's IP blk
* @find_companion: function returning the companion clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
*
* A companion clk is an accompanying clock to the one being queried
* that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
u8 *, u8 *);
void(*find_companion)(struct clk *, void __iomem **,
u8 *);
+ void(*allow_idle)(struct clk *);
+ void(*deny_idle)(struct clk *);
};
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct
cpufreq_frequency_table **table);
extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#endif
extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle(void);
+extern void omap_clk_disable_autoidle(void);
extern const struct clkops clkops_null;
--
1.7.2.3
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Re: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops
On Sat, 12 Feb 2011, Paul Walmsley wrote:
On Thu, 10 Feb 2011, Rajendra Nayak wrote:
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..6889c5a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
return ret;
}
+void omap_clk_enable_autoidle(void)
I also renamed these functions to
omap_clk_enable_autoidle_all()
omap_clk_disable_autoidle_all()
since they operate on all clocks. Updated patch follows.
- Paul
From: Rajendra Nayak rna...@ti.com
Date: Thu, 10 Feb 2011 14:46:36 +0530
Subject: [PATCH] OMAP: clock: Add allow_idle/deny_idle support in clkops
On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.
These function pointers can be populated for any clock
node which supports hardware level autogating.
Also add 2 new functions (omap_clk_enable_autoidle_all and
omap_clk_disable_autoidle_all) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.
Signed-off-by: Rajendra Nayak rna...@ti.com
[p...@pwsan.com: use spinlock rather than mutex due to race; renamed functions]
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/plat-omap/clock.c | 28
arch/arm/plat-omap/include/plat/clock.h |6 ++
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..585533a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
return ret;
}
+void omap_clk_enable_autoidle_all(void)
+{
+ struct clk *c;
+ unsigned long flags;
+
+ spin_lock_irqsave(clockfw_lock, flags);
+
+ list_for_each_entry(c, clocks, node)
+ if (c-ops-allow_idle)
+ c-ops-allow_idle(c);
+
+ spin_lock_irqrestore(clockfw_lock, flags);
+}
+
+void omap_clk_disable_autoidle_all(void)
+{
+ struct clk *c;
+ unsigned long flags;
+
+ spin_lock_irqsave(clockfw_lock, flags);
+
+ list_for_each_entry(c, clocks, node)
+ if (c-ops-deny_idle)
+ c-ops-deny_idle(c);
+
+ spin_lock_irqrestore(clockfw_lock, flags);
+}
+
/*
* Low level helpers
*/
diff --git a/arch/arm/plat-omap/include/plat/clock.h
b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..8534f71 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
* @disable: fn ptr that enables the current clock in hardware
* @find_idlest: function returning the IDLEST register for the clock's IP blk
* @find_companion: function returning the companion clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
*
* A companion clk is an accompanying clock to the one being queried
* that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
u8 *, u8 *);
void(*find_companion)(struct clk *, void __iomem **,
u8 *);
+ void(*allow_idle)(struct clk *);
+ void(*deny_idle)(struct clk *);
};
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct
cpufreq_frequency_table **table);
extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#endif
extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle_all(void);
+extern void omap_clk_disable_autoidle_all(void);
extern const struct clkops clkops_null;
--
1.7.2.3
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Re: [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's
On Thu, 10 Feb 2011, Rajendra Nayak wrote: All OMAP3/4 dpll's support hardware level autogating. Populate allow_idle/deny_idle function pointers for all DPLL's in clkops. Signed-off-by: Rajendra Nayak rna...@ti.com Thanks, queued for 2.6.39. Two questions though. Was the OMAP4 autogeneration script updated? Also, any technical reason why you didn't add the OMAP2 DPLL? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot
On Thu, 10 Feb 2011, Rajendra Nayak wrote: Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3 already had dpll autoidle turned on, but was done using low level cm accessor apis). On OMAP3, replace the cm accessor apis doing this with the now available support for doing this in clock framework, using omap_clk_enable_autoidle(). I propose this patch instead. What do you think? Care to reply with a Reviewed-by: and/or Tested-by: ? - Paul From: Paul Walmsley p...@pwsan.com Date: Sat, 12 Feb 2011 17:36:38 -0600 Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible in OMAP2+-common PM code Attempt to enable autoidle for as many clocks as possible in the OMAP2+-common PM code. Currently, this only enables DPLL autoidle for OMAP3/4 DPLLs; but it should also eventually enable autoidle for other clocks and the OMAP2 DPLL/APLLs. Based on a patch by Rajendra Nayak rna...@ti.com that did this in the pm34xx.c/pm44xx.c code, rather than the common PM code. Signed-off-by: Paul Walmsley p...@pwsan.com --- arch/arm/mach-omap2/pm.c |8 arch/arm/mach-omap2/pm34xx.c | 17 - 2 files changed, 8 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index d5a102c..b507702 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -262,6 +262,14 @@ static int __init omap2_common_pm_late_init(void) /* Smartreflex device init */ omap_devinit_smartreflex(); + /* +* Set all OMAP3/4 DPLLs to autoidle. +* XXX TODO: Add all the iclk autoidles in here as well, +* the OMAP2 DPLL, the OMAP2 APLLs, and the AUTOEXTCLKMODE +* control here too. +*/ + omap_clk_enable_autoidle_all(); + return 0; } late_initcall(omap2_common_pm_late_init); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 2f864e4..1fe2e73 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void) omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); /* -* Set all plls to autoidle. This is needed until autoidle is -* enabled by clockfw -*/ - omap2_cm_write_mod_reg(1 OMAP3430_AUTO_IVA2_DPLL_SHIFT, -OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - omap2_cm_write_mod_reg(1 OMAP3430_AUTO_MPU_DPLL_SHIFT, -MPU_MOD, -CM_AUTOIDLE2); - omap2_cm_write_mod_reg((1 OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | -(1 OMAP3430_AUTO_CORE_DPLL_SHIFT), -PLL_MOD, -CM_AUTOIDLE); - omap2_cm_write_mod_reg(1 OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, -PLL_MOD, -CM_AUTOIDLE2); - - /* * Enable control of expternal oscillator through * sys_clkreq. In the long run clock framework should * take care of this. -- 1.7.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 6/7] omap4: dpll: Add dpll api to control GATE_CTRL
On Thu, 10 Feb 2011, Rajendra Nayak wrote:
On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.
Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.
NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.
Signed-off-by: Rajendra Nayak rna...@ti.com
Thanks, I moved the OMAP4-specific code to a file that is only compiled in
on OMAP4, and added some documentation, and queued it for 2.6.39 in the
'clk_autoidle_a_2.6.39' branch here. Updated version follows.
- Paul
From: Rajendra Nayak rna...@ti.com
Date: Thu, 10 Feb 2011 14:46:39 +0530
Subject: [PATCH] OMAP4: DPLL: Add dpll api to control GATE_CTRL
On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.
Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.
NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.
Signed-off-by: Rajendra Nayak rna...@ti.com
[p...@pwsan.com: moved OMAP4-specific DPLL control code to
mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2]
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/Makefile|2 +-
arch/arm/mach-omap2/clock.h |3 +
arch/arm/mach-omap2/dpll44xx.c | 78 +++
arch/arm/plat-omap/include/plat/clock.h | 14 +-
4 files changed, 95 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-omap2/dpll44xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9eeabaf..c21b3ae 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -120,7 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3)+= $(clock-common)
clock3xxx.o \
clock3517.o clock36xx.o \
dpll3xxx.o clock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
- dpll3xxx.o
+ dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old OPP data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2a939e5..c450d69 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
new file mode 100644
index 000..94a3592
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -0,0 +1,78 @@
+/*
+ * OMAP4-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/bitops.h
+
+#include plat/cpu.h
+#include plat/clock.h
+
+#include clock.h
+#include cm-regbits-44xx.h
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+ u32 v;
+ u32 mask;
+
+ if (!clk || !clk-clksel_reg || !cpu_is_omap44xx())
+ return -EINVAL;
+
+ mask = clk-flags CLOCK_CLKOUTX2 ?
+ OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+ OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+ v = __raw_readl(clk-clksel_reg);
+ v = mask;
+ v = __ffs(mask);
+
+ return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+ u32 v;
+ u32 mask;
+
+ if (!clk || !clk-clksel_reg || !cpu_is_omap44xx())
+ return;
+
+ mask = clk-flags CLOCK_CLKOUTX2 ?
+ OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+ OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+ v = __raw_readl(clk-clksel_reg);
+ /* Clear the bit to allow gatectrl */
+ v =
Re: [PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers
On Thu, 10 Feb 2011, Rajendra Nayak wrote: Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: Rajendra Nayak rna...@ti.com Thanks, queued for 2.6.39 in the 'clk_autoidle_a_2.6.39' branch. Has the OMAP4 clock data autogenerator script been updated? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/7] clock/dpll autoidle support
Hi Rajendra On Thu, 10 Feb 2011, Rajendra Nayak wrote: OMAP has various clock nodes and dpll's which support hardware level autoidle. Enabling hardware level autoidle provides better power savings without much software intervention. This series does the following to help enable hardware level autoidling using clock framework for some of these nodes on OMAP3 and OMAP4 -1- Adds support for providing function pointers for enabling/disabling autoidle in clkops -2- Populates these in clkops for all OMAP3/4 dplls -3- Enables all dpll autoidle late in boot on OMAP3 and OMAP4 -4- Adds support for mx postdivider autoidle (present only on OMAP4) and enables it late in OMAP4 boot I've reviewed and commented on all of these, asked a few questions, made a few changes, and queued the results for 2.6.39 in two branches of git://git.pwsan.com/linux-2.6: clk_a_2.6.39 (for the autoidle-independent fixes) clk_autoidle_a_2.6.39 (for the autoidle-specific code and data changes) Both branches have been added to the 'integration-2.6.39' branch of git://git.pwsan.com/linux-integration, and are available as part of the tag integration-2.6.39-20110212-004. thanks, - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
