[PATCH v4] OMAP4: hwmod data: I2C: add flag for context restore
Restore of context is not done for OMAP4. This patch
adds the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE in the OMAP4
hwmod data which activates the restore for OMAP4.
Currently the OMAP4 does not hit device off still the
driver may have support for it.
Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com
---
Applies on top of patches from Andy Green
http://www.spinics.net/lists/linux-i2c/msg05632.html
Tested on OMAP4430
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0fe9556..5e2c748 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2130,7 +2130,8 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class =
{
};
static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
};
/* i2c1 */
--
1.7.1
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Re: [PATCHv2 17/28] OMAP2420: HWMOD: Add DSS opt clocks
On Thu, 9 Jun 2011, Tomi Valkeinen wrote: Add DSS optional clocks to HWMOD data for OMAP2420. Thanks; queued for 3.1-rc fixes at git://git.pwsan.com/linux-2.6 in the branch 'omap2_3_hwmod_dss_fixes_3.1rc'. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 16/28] OMAP3: HWMOD: Add DSS opt clocks
On Thu, 9 Jun 2011, Tomi Valkeinen wrote: Add DSS optional clocks to HWMOD data for OMAP3xxx. Thanks; queued for 3.1-rc fixes at git://git.pwsan.com/linux-2.6 in the branch 'omap2_3_hwmod_dss_fixes_3.1rc'. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 18/28] OMAP2430: HWMOD: Add DSS opt clocks
On Thu, 9 Jun 2011, Tomi Valkeinen wrote: Add DSS optional clocks to HWMOD data for OMAP2430. Thanks; queued for 3.1-rc fixes at git://git.pwsan.com/linux-2.6 in the branch 'omap2_3_hwmod_dss_fixes_3.1rc'. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
* Jan Weitzel j.weit...@phytec.de [110714 01:34]: Am Donnerstag, den 14.07.2011, 00:34 -0700 schrieb Tony Lindgren: * Jan Weitzel j.weit...@phytec.de [110713 05:51]: Am Mittwoch, den 13.07.2011, 16:13 +0400 schrieb Sergei Shtylyov: Have you added that 'i' at the end intentionally? Thank you. It was a tribute to vim. :i) I'll fold the fixed patch into your original patch. Will also keep the new board files in testing-board because of the code coalescing and device tree conversion effort. So there is no way to get the board mainline yet? Well we can add it even before device tree support if it makes sense from code coalescing point of view. In this case it would mean creating board-panda-common.c or similar so the code can be shared amongst the panda variants. It seems that some GPIO pins are different and there are some difference in devices connected, but big parts of the code can be shared. Adding the pending boards without combining code would be adding code that will be going away for most part with the device tree support. And most likely the beagle and panda based boards will be the first ones to work with device tree. So anything we can do to have common board init code will also help with this effort. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] OMAP: powerdomains: Make all powerdomain target states as ON at init
On Wed, 13 Jul 2011, Santosh Shilimkar wrote: From: Rajendra Nayak rna...@ti.com Program all powerdomain target state as ON; This is to prevent domains from hitting low power states (if bootloader has target states set to something other than ON) and potentially even losing context while PM is not fully initilized. The PM late init code can then program the desired target state for all the power domains. Signed-off-by: Rajendra Nayak rna...@ti.com Thanks, dropped the second hunk of the patch and queued for 3.1-rc fixes at git://git.pwsan.com/linux-2.6 in the 'pwrdm_clkdm_fixes_3.1rc' branch. Santosh, looks like this is missing a Signed-off-by: or similar from you. Do you want me to add it? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
Hi, On Fri, Jul 15, 2011 at 12:50:24AM -0700, Tony Lindgren wrote: * Jan Weitzel j.weit...@phytec.de [110714 01:34]: Am Donnerstag, den 14.07.2011, 00:34 -0700 schrieb Tony Lindgren: * Jan Weitzel j.weit...@phytec.de [110713 05:51]: Am Mittwoch, den 13.07.2011, 16:13 +0400 schrieb Sergei Shtylyov: Have you added that 'i' at the end intentionally? Thank you. It was a tribute to vim. :i) I'll fold the fixed patch into your original patch. Will also keep the new board files in testing-board because of the code coalescing and device tree conversion effort. So there is no way to get the board mainline yet? Well we can add it even before device tree support if it makes sense from code coalescing point of view. In this case it would mean creating board-panda-common.c or similar so the code can be shared amongst the panda variants. It seems that some GPIO pins are different and there are some difference in devices connected, but big parts of the code can be shared. isn't it easier than to just add a few if (machine_is_()) checks and another MACHINE_START() to board-omap4panda.c rather than creating a new file, shuffling code around and then adding a new board file ?? -- balbi signature.asc Description: Digital signature
Re: [PATCH] OMAP: powerdomains: Make all powerdomain target states as ON at init
Hi, On Wed, Jul 13, 2011 at 08:56:27AM +0530, Santosh Shilimkar wrote: From: Rajendra Nayak rna...@ti.com Program all powerdomain target state as ON; This is to prevent domains from hitting low power states (if bootloader has target states set to something other than ON) and potentially even losing context while PM is not fully initilized. The PM late init code can then program the desired target state for all the power domains. Signed-off-by: Rajendra Nayak rna...@ti.com --- arch/arm/mach-omap2/powerdomain.c | 12 +++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index e0490bc..e61866c 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -109,6 +109,16 @@ static int _pwrdm_register(struct powerdomain *pwrdm) list_add(pwrdm-node, pwrdm_list); + /* + * Program all powerdomain target state as ON; This is to + * prevent domains from hitting low power states (if bootloader + * has target states set to something other than ON) and potentially + * even losing context while PM is not fully initilized. + * The PM late init code can then program the desired target + * state for all the power domains. + */ + pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); Just out of curiosity, I was wondering if it really makes sense to power up all power domains during boot just to avoid loosing context. Doesn't hwmod/omap_device soft-reset all IPs during initialization ? If that's really the case, shouldn't we then choose which powerdomains are strictly necessary for boot and only power those up ? Sorry if this is a non-sensical question, but I was curious about it ;-) -- balbi signature.asc Description: Digital signature
Re: [PATCH] OMAP: clockdomain: Wait for powerdomain to be ON when using clockdomain force wakeup
cc'ing Patrick
Hi Rajendra, Santosh,
some comments here:
On Wed, 13 Jul 2011, Santosh Shilimkar wrote:
While using clockdomain force wakeup method, not waiting for powerdomain
to be effectively ON may end up locking the clockdomain FSM until a
next wakeup event occurs.
One such issue was seen on OMAP4430, where L4_PER was periodically
getting stuck in in-transition state when transitioning from from OSWR to ON.
This issue was reported and investigated by Patrick Titiano p-titi...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Reported-by: Patrick Titiano p-titi...@ti.com
Cc: Kevin Hilman khil...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/clockdomain.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index b98a972..583cc3d 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -718,6 +718,8 @@ int clkdm_sleep(struct clockdomain *clkdm)
*/
int clkdm_wakeup(struct clockdomain *clkdm)
{
+ int ret;
+
if (!clkdm)
return -EINVAL;
@@ -732,7 +734,10 @@ int clkdm_wakeup(struct clockdomain *clkdm)
pr_debug(clockdomain: forcing wakeup on %s\n, clkdm-name);
- return arch_clkdm-clkdm_wakeup(clkdm);
+ ret = arch_clkdm-clkdm_wakeup(clkdm);
+ ret |= pwrdm_wait_transition(clkdm-pwrdm.ptr);
Seems like this should just call pwrdm_state_switch() or
pwrdm_clkdm_state_switch()? (This second function looks superfluous, we
should probably get rid of it.)
Shouldn't this be added to all of
clkdm_{wakeup,sleep,allow_idle,deny_idle}() if it isn't there already?
+
+ return ret;
}
/**
--
1.7.4.1
- Paul
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Re: [PATCH] OMAP: powerdomains: Make all powerdomain target states as ON at init
Hi, On Fri, 15 Jul 2011, Felipe Balbi wrote: diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index e0490bc..e61866c 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -109,6 +109,16 @@ static int _pwrdm_register(struct powerdomain *pwrdm) list_add(pwrdm-node, pwrdm_list); + /* + * Program all powerdomain target state as ON; This is to + * prevent domains from hitting low power states (if bootloader + * has target states set to something other than ON) and potentially + * even losing context while PM is not fully initilized. + * The PM late init code can then program the desired target + * state for all the power domains. + */ + pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); Just out of curiosity, I was wondering if it really makes sense to power up all power domains during boot just to avoid loosing context. Doesn't hwmod/omap_device soft-reset all IPs during initialization ? If that's really the case, shouldn't we then choose which powerdomains are strictly necessary for boot and only power those up ? Sorry if this is a non-sensical question, but I was curious about it ;-) This patch only sets the powerdomain's next power state to ON. It doesn't affect the current power state of the powerdomain. Let's say that the bootloader, previous OS (in the kexec case), or ROM code programs the next power state of some powerdomains to OFF. Let's also say that the kernel that is booted has PM disabled. The moment a powerdomain's clockdomains go inactive, the powerdomain will then switch off and all devices in that powerdomain will lose context. On a non-PM-enabled kernel, that will be unexpected and will probably cause the system to crash. This patch prevents that from happening. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] usb: musb: omap2430: handle charger OTG xceiver event
Hi, On Tue, Jul 12, 2011 at 10:44:19AM -0700, Dima Zavin wrote: On Mon, Jul 11, 2011 at 11:01 PM, Felipe Balbi ba...@ti.com wrote: Hi, On Mon, Jul 11, 2011 at 03:43:17PM -0700, Dima Zavin wrote: Set a flag on OTG charger event and check it on cable remove event (i.e. USB_EVENT_NONE). This way we will not need to power up the PHY when an external charger s/PHY/LINK Actually it's both, I should update the commit message. the PHY has to be powered up during charger detection. You could power it down after charger has been started and power it back up on the rising edge (or high level, don't remember if this is edge of level triggered) of the VBUS IRQ. is detected by the transceiver itself. ... your logic is inversed. Link shouldn't be powered up to start with. We should only power up the Link after we know it *will* be needed. The way you're doing this is: The link *isn't* being powered up by my patch. On an already detected not by your patch, true. My point is that we're powering it up too early and if you want to change anything regarding Charger Detection you need to change at the right place. charger you should do nothing at all in musb. That's the whole point of the patch: add the ability to process the USB_EVENT_CHARGER event in musb from the otg_transceiver that has already detected the charger. Today, on USB_EVENT_VBUS, you'd resume your link and then and what I said (or tried to) is that USB_EVENT_VBUS isn't an event to be handled by the link at all. The link should be pm_runtime_suspend()ed right after probe() and should be kept that way until PHY sends USB_EVENT_CHARGER_DETECTION_DONE or something similar. call otg_init, which would powerup the phy on omap4, which we do not need to do for USB_EVENT_CHARGER. That is wrong true. Still your patch only adds a flag. It's not implementing what you're describing here. connect cable - resume PHY - resume Link - if is_charger suspend Link. Not at all. Have even you looked at the patch? With the patch, 1) connect cable, detected by otg_transceiver. 2) otg_transceiver does the detection of ID pin and/or VBUS and/or dedicated charger. 3) otg_transceiver sends USB_EVENT_xxx yes, and it will send USB_EVENT_VBUS which is resuming link. 4) In musb_otg_notification(), check if the transceiver detected a charger (USB_EVENT_CHARGER). 4.1) If yes, then do nothing and leave the LINK *and* the PHY in their off states. this is not what your patch is doing. It only enables/disables a flag which your patch added. Where it should be: connect cable - resume PHY - if is_charger goto done. We only have to resume the PHY if the transceiver didn't do the charger detection. The TWL6030 doesn't do that, but depending on your PHY == transceiver. Like I said before, if you want to put any changes regarding charger detection, do it at the right location. First add some events for different USB port types (SDP, CDP, DCP), then notify those, then add handling of those events to MUSB and PHY drivers, then fix up musb to be runtime suspended right after probe, then you only need to wake musb UP in case of SDP and CDP. If you're attached to a DCP you don't even need MUSB to handle that. Also, while you are doing Charger detection, be sure to disable SoftConnect bit on MUSB and put PHY in NONDRIVING mode, this will prevent MUSB from even knowing there's a cable connected. -- balbi signature.asc Description: Digital signature
Re: [PATCH 6/6] OMAP: Add debugfs node to show the summary of all clocks
Hi, On Thu, 14 Jul 2011, Jon Hunter wrote: From: Jon Hunter jon-hun...@ti.com Add a debugfs node called summary to /sys/kernel/debug/clock/ that displays a quick summary of all clocks registered in the clocks structure. The format of the output from this node is: clock-name parent-name rate usecount This debugfs node was very helpful for taking a quick snapshot of the linux clock tree for OMAP and ensuring clock frequencies calculated by the kernel were indeed correct. This patch helped uncover some bugs in the linux clock tree for OMAP4. Signed-off-by: Jon Hunter jon-hun...@ti.com this patch was queued for 3.1 at git://git.pwsan.com/linux-2.6 in the 'prcm-devel-3.1' branch, so no need to resend this one. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/6] OMAP3+ Clock Fixes
Hi Jon On Thu, 14 Jul 2011, Jon Hunter wrote: From: Jon Hunter jon-hun...@ti.com Various clock fixes for OMAP3 and OMAP4 devices. Plus one debug patch (if anyone is interested). Jon Hunter (4): OMAP4: Add missing clock divider for OCP_ABE_ICLK OMAP3+: use DPLLs recalc function instead of omap2_get_dpll_rate OMAP3+: Update DPLL Fint range for OMAP36xx and OMAP4xxx devices OMAP: Add debugfs node to show the summary of all clocks Mike Turquette (2): OMAP4: Clock: round_rate and recalc functions for DPLL_ABE OMAP3+: use DPLL's round_rate when setting rate Could you please repost these patches, cc'ing linux-arm-ker...@lists.infradead.org ? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] OMAP: powerdomains: Make all powerdomain target states as ON at init
Hi, On Fri, Jul 15, 2011 at 02:10:46AM -0600, Paul Walmsley wrote: diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index e0490bc..e61866c 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -109,6 +109,16 @@ static int _pwrdm_register(struct powerdomain *pwrdm) list_add(pwrdm-node, pwrdm_list); + /* + * Program all powerdomain target state as ON; This is to + * prevent domains from hitting low power states (if bootloader + * has target states set to something other than ON) and potentially + * even losing context while PM is not fully initilized. + * The PM late init code can then program the desired target + * state for all the power domains. + */ + pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); Just out of curiosity, I was wondering if it really makes sense to power up all power domains during boot just to avoid loosing context. Doesn't hwmod/omap_device soft-reset all IPs during initialization ? If that's really the case, shouldn't we then choose which powerdomains are strictly necessary for boot and only power those up ? Sorry if this is a non-sensical question, but I was curious about it ;-) This patch only sets the powerdomain's next power state to ON. It doesn't affect the current power state of the powerdomain. Let's say that the bootloader, previous OS (in the kexec case), or ROM code programs the next power state of some powerdomains to OFF. Let's also say that the kernel that is booted has PM disabled. The moment a powerdomain's clockdomains go inactive, the powerdomain will then switch off and all devices in that powerdomain will lose context. On a non-PM-enabled kernel, that will be unexpected and will probably cause the system to crash. This patch prevents that from happening. I see... thanks for clarifying. The comment above the code wasn't really clear about it to me. -- balbi signature.asc Description: Digital signature
Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
* Felipe Balbi ba...@ti.com [110715 00:53]: Hi, On Fri, Jul 15, 2011 at 12:50:24AM -0700, Tony Lindgren wrote: * Jan Weitzel j.weit...@phytec.de [110714 01:34]: Am Donnerstag, den 14.07.2011, 00:34 -0700 schrieb Tony Lindgren: * Jan Weitzel j.weit...@phytec.de [110713 05:51]: Am Mittwoch, den 13.07.2011, 16:13 +0400 schrieb Sergei Shtylyov: Have you added that 'i' at the end intentionally? Thank you. It was a tribute to vim. :i) I'll fold the fixed patch into your original patch. Will also keep the new board files in testing-board because of the code coalescing and device tree conversion effort. So there is no way to get the board mainline yet? Well we can add it even before device tree support if it makes sense from code coalescing point of view. In this case it would mean creating board-panda-common.c or similar so the code can be shared amongst the panda variants. It seems that some GPIO pins are different and there are some difference in devices connected, but big parts of the code can be shared. isn't it easier than to just add a few if (machine_is_()) checks and another MACHINE_START() to board-omap4panda.c rather than creating a new file, shuffling code around and then adding a new board file ?? That works too if the init_machine does not get too complicated. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/6] OMAP4: Add missing clock divider for OCP_ABE_ICLK
cc'ing Benoît
Hi Jon
On Thu, 14 Jul 2011, Jon Hunter wrote:
From: Jon Hunter jon-hun...@ti.com
The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the
parent clock of the AESS_FCLK is the ABE_FCLK...
ABE_FCLK -- AESS_FCLK -- OCP_ABE_ICLK
The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which
determine their operational frequency. However, the dividers for
the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit,
which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to
0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2.
Similarly, when this bit is set to 1, the AESS_FCLK divider is 2
and the OCP_ABE_ICLK is 1.
Sigh. This type of hardware design makes software design difficult :-(
The above relationship between the AESS_FCLK and OCP_ABE_ICLK
dividers ensure that the OCP_ABE_ICLK clock is always half the
frequency of the ABE_CLK...
OCP_ABE_ICLK = ABE_FCLK/2
The divider for the OCP_ABE_ICLK is currently missing so add a
divider that will ensure the OCP_ABE_ICLK frequency is always half
the ABE_FCLK frequency.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/mach-omap2/clock44xx_data.c | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index 8c96567..6e158ce 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1301,11 +1301,25 @@ static struct clk mcasp3_fclk = {
.recalc = followparent_recalc,
};
+static const struct clksel_rate div2_2to1_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+ { .div = 0 },
+};
+
+static const struct clksel ocp_abe_iclk_div[] = {
+ { .parent = aess_fclk, .rates = div2_2to1_rates },
+ { .parent = NULL },
+};
+
static struct clk ocp_abe_iclk = {
.name = ocp_abe_iclk,
.parent = aess_fclk,
+ .clksel = ocp_abe_iclk_div,
+ .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+ .clksel_mask= OMAP4430_CLKSEL_AESS_FCLK_MASK,
.ops= clkops_null,
- .recalc = followparent_recalc,
+ .recalc = omap2_clksel_recalc,
};
static struct clk per_abe_24m_fclk = {
I guess the reason that this patch can get away with this is because it
doesn't allow software to change the rate of ocp_abe_iclk, and the
ocp_abe_iclk is a child of aess_fclk, so when aess_fclk is changed, it
will recalc ocp_abe_iclk.
Benoît, what do you think? Is this a reasonable approach for the script?
Or do we need to deal with some kind of 'linked clock' implementation...
- Paul
Re: [PATCH] OMAP: powerdomains: Make all powerdomain target states as ON at init
Hi Felipe, On Fri, 15 Jul 2011, Felipe Balbi wrote: I see... thanks for clarifying. The comment above the code wasn't really clear about it to me. No worries. If you propose a clarification, I'll stick that into the patch. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
Hi,
On Fri, Jul 15, 2011 at 01:20:12AM -0700, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [110715 00:53]:
Hi,
On Fri, Jul 15, 2011 at 12:50:24AM -0700, Tony Lindgren wrote:
* Jan Weitzel j.weit...@phytec.de [110714 01:34]:
Am Donnerstag, den 14.07.2011, 00:34 -0700 schrieb Tony Lindgren:
* Jan Weitzel j.weit...@phytec.de [110713 05:51]:
Am Mittwoch, den 13.07.2011, 16:13 +0400 schrieb Sergei Shtylyov:
Have you added that 'i' at the end intentionally?
Thank you. It was a tribute to vim.
:i)
I'll fold the fixed patch into your original patch. Will also
keep the new board files in testing-board because of the code
coalescing and device tree conversion effort.
So there is no way to get the board mainline yet?
Well we can add it even before device tree support if it makes
sense from code coalescing point of view. In this case it would
mean creating board-panda-common.c or similar so the code can
be shared amongst the panda variants.
It seems that some GPIO pins are different and there are some
difference in devices connected, but big parts of the code can be
shared.
isn't it easier than to just add a few if (machine_is_()) checks and
another MACHINE_START() to board-omap4panda.c rather than creating a new
file, shuffling code around and then adding a new board file ??
That works too if the init_machine does not get too complicated.
possibly something like this (still missing MACHINE_START a few more
things):
diff --git a/arch/arm/mach-omap2/board-omap4panda.c
b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe200..dff174c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -681,20 +681,44 @@ void omap4_panda_display_init(void)
omap_display_init(omap4_panda_dss_data);
}
+static struct omap_smsc911x_platform_data board_smsc911x_data __initdata = {
+ .cs = OMAP4_SMSC911X_ETH_CS,
+ .gpio_irq = OMAP4_SMSC911X_ETH_GPIO_IRQ,
+ .gpio_reset = -EINVAL,
+ .flags = SMSC911X_USE_16BIT,
+};
+
+static void __init omap4_panda_smsc91xx_init(void)
+{
+ if (!machine_is_pcm049())
+ return;
+
+ omap_mux_init_gpio(OMAP4_PCM049_ETH_GPIO_IRQ, OMAP_PIN_INPUT);
+ gpmc_smsc911x_init(board_smsc911x_data);
+}
+
static void __init omap4_panda_init(void)
{
int package = OMAP_PACKAGE_CBS;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
+
omap4_mux_init(board_mux, NULL, package);
- if (wl12xx_set_platform_data(omap_panda_wlan_data))
- pr_err(error setting wl12xx data\n);
+ if (machine_is_omap4panda()) {
+ int ret;
+
+ ret = wl12xx_set_platform_data(omap_panda_wlan_data);
+ if (ret)
+ pr_err(error setting wl12xx data\n);
+
+ platform_device_register(omap_vwlan_device);
+ }
+ omap4_panda_smsc91xx_init();
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
- platform_device_register(omap_vwlan_device);
board_serial_init();
omap4_twl6030_hsmmc_init(mmc);
--
balbi
signature.asc
Description: Digital signature
Re: [PATCH] OMAP: powerdomains: Make all powerdomain target states as ON at init
Hi, On Fri, Jul 15, 2011 at 02:23:16AM -0600, Paul Walmsley wrote: Hi Felipe, On Fri, 15 Jul 2011, Felipe Balbi wrote: I see... thanks for clarifying. The comment above the code wasn't really clear about it to me. No worries. If you propose a clarification, I'll stick that into the patch. How about something like: /* * Program target state of all power domains to ON. This is to prevent * power domains from hitting low power states during boot up and * potentially causing accesses to the address space of an IP while it * is disabled. * * PM late init code will make sure of disabling all unused IPs later. */ not sure if it's a lot better though. -- balbi signature.asc Description: Digital signature
Re: [PATCH V2 00/16] omap_hsmmc patches
On Wed, Jul 13, 2011 at 6:36 PM, Chris Ball c...@laptop.org wrote:
Hi,
On Wed, Jul 13 2011, Grazvydas Ignotas wrote:
it seems this series got lost in time, at least patches 01, 02, 03,
04, 05, 06, 07, 08, 12 look like valid standalone fixes and
improvements to me, they don't touch other trees and still apply
cleanly, so would be good to have.
Yeah. I didn't merge them because Tony still has unanswered comments on
the OMAP side of the patches, and they're submitted as a single patchset.
I've applied {2, 3, 5, 6, 7, 8, 12} to mmc-next for 3.1 now. 1 doesn't
apply because the function doesn't exist anymore. 4 doesn't apply
because iclk doesn't exist anymore.
If someone wants to look at rebasing the rest of these against mmc-next
and resubmitting, I think that'd be useful.
Thanks! 1 and 4 seem to be unneeded any more (I was trying them on
linux-next, not noticing it was not updated for a while), and others
have comments pending, so it's all done.
Thanks,
- Chris.
--
Chris Ball c...@laptop.org http://printf.net/
One Laptop Per Child
--
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Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
Am Freitag, den 15.07.2011, 00:50 -0700 schrieb Tony Lindgren: Well we can add it even before device tree support if it makes sense from code coalescing point of view. In this case it would mean creating board-panda-common.c or similar so the code can be shared amongst the panda variants. It seems that some GPIO pins are different and there are some difference in devices connected, but big parts of the code can be shared. Adding the pending boards without combining code would be adding code that will be going away for most part with the device tree support. And most likely the beagle and panda based boards will be the first ones to work with device tree. So anything we can do to have common board init code will also help with this effort. Regards, Tony pcm049 and panda board have some more different devices. I am working on patches to add NAND support and using tlv320aic3x audio codec which need regulators in platformcode. I need a hack to controll usb otg by gpio (controlling a external power circuit). The patches are not mainline ready by now. If using machine_is_() in board-omap4panda.c then also is good way, I could provide our board as patches on top of board-omap4panda.c. When will pandaboard use device tree to boot? Kind Regards, Jan -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL] minimal omap4460 support for v3.1 merge window
Tony, I boot tested this pull request on 4460 Panda and it boots up fine. Regards Vishwa -Original Message- From: linux-arm-kernel-boun...@lists.infradead.org [mailto:linux- arm-kernel-boun...@lists.infradead.org] On Behalf Of Tony Lindgren Sent: Monday, July 11, 2011 1:22 AM To: Arnd Bergmann Cc: Thomas Gleixner; linux-omap@vger.kernel.org; linux-arm- ker...@lists.infradead.org; Nicolas Pitre Subject: Re: [GIT PULL] minimal omap4460 support for v3.1 merge window Correting the email address for Arnd. * Tony Lindgren t...@atomide.com [110709 23:51]: Hi Arnd, Please pull minimal omap4460 support from: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap- 2.6.git 4460 Regards, Tony The following changes since commit 48cb1258e8b0f8c81cfb699b42326c5b2147b3f8: Tony Lindgren (1): Merge branch 'for_3.1/pm-misc' of git://git.kernel.org/.../khilman/linux-omap-pm into devel-cleanup are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap- 2.6.git 4460 Aneesh V (2): OMAP: ID: introduce chip detection for OMAP4460 OMAP4: ID: add omap_has_feature for max freq supported Rajendra Nayak (2): OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts OMAP4: clocks: Update the clock tree with 4460 clock nodes arch/arm/mach-omap2/clock44xx_data.c | 39 ++ arch/arm/mach-omap2/cm-regbits-44xx.h | 36 + arch/arm/mach-omap2/id.c | 53 arch/arm/mach-omap2/prm-regbits-44xx.h|8 arch/arm/plat-omap/include/plat/clkdev_omap.h |1 + arch/arm/plat-omap/include/plat/clock.h |2 + arch/arm/plat-omap/include/plat/cpu.h | 35 +++- 7 files changed, 162 insertions(+), 12 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux- omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] MTD: Nand: use MTD_NAND_OMAP2 for OMAP4
use MTD_NAND_OMAP2 also for OMAP4 arch. testes wit omap4430 Signed-off-by: Jan Weitzel j.weit...@phytec.de --- drivers/mtd/nand/Kconfig |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 4c34252..40e64b8 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -117,9 +117,10 @@ config MTD_NAND_AMS_DELTA config MTD_NAND_OMAP2 tristate NAND Flash device on OMAP2 and OMAP3 - depends on ARM (ARCH_OMAP2 || ARCH_OMAP3) + depends on ARM (ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4) help - Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. + Support for NAND flash on Texas Instruments OMAP2, OMAP3 and OMAP4 + platforms. config MTD_NAND_IDS tristate -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
* Jan Weitzel j.weit...@phytec.de [110715 02:42]: Am Freitag, den 15.07.2011, 00:50 -0700 schrieb Tony Lindgren: Well we can add it even before device tree support if it makes sense from code coalescing point of view. In this case it would mean creating board-panda-common.c or similar so the code can be shared amongst the panda variants. It seems that some GPIO pins are different and there are some difference in devices connected, but big parts of the code can be shared. Adding the pending boards without combining code would be adding code that will be going away for most part with the device tree support. And most likely the beagle and panda based boards will be the first ones to work with device tree. So anything we can do to have common board init code will also help with this effort. Regards, Tony pcm049 and panda board have some more different devices. I am working on patches to add NAND support and using tlv320aic3x audio codec which need regulators in platformcode. I need a hack to controll usb otg by gpio (controlling a external power circuit). The patches are not mainline ready by now. OK, let's figure out how we can add the basic support first then. If using machine_is_() in board-omap4panda.c then also is good way, I could provide our board as patches on top of board-omap4panda.c. When will pandaboard use device tree to boot? Yes, but it would better just to use separate .init_machine entries to initialize thing. Gpio entries can be initialized along the lines of the recent beagle commit 5fe8b4c19dc24e3bb873daf9e96a2439a83bbd79 that adds support for beagl xm board. Except you already have a separate machine_id, so no runtime detection is needed. That avoids adding the machine_is entries all over the place that tend to cause problems when some other panda variant is added as it requires patching in multiple places. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP4: PCM049: remove vusim regulator
* Felipe Balbi ba...@ti.com [110715 01:25]:
possibly something like this (still missing MACHINE_START a few more
things):
Yes and it would be better to initialize data in the .init_machine
to avoid adding machine_is tests in multiple places.
diff --git a/arch/arm/mach-omap2/board-omap4panda.c
b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe200..dff174c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -681,20 +681,44 @@ void omap4_panda_display_init(void)
omap_display_init(omap4_panda_dss_data);
}
+static struct omap_smsc911x_platform_data board_smsc911x_data __initdata = {
+ .cs = OMAP4_SMSC911X_ETH_CS,
+ .gpio_irq = OMAP4_SMSC911X_ETH_GPIO_IRQ,
+ .gpio_reset = -EINVAL,
+ .flags = SMSC911X_USE_16BIT,
+};
+
+static void __init omap4_panda_smsc91xx_init(void)
+{
+ if (!machine_is_pcm049())
+ return;
+
+ omap_mux_init_gpio(OMAP4_PCM049_ETH_GPIO_IRQ, OMAP_PIN_INPUT);
+ gpmc_smsc911x_init(board_smsc911x_data);
+}
+
static void __init omap4_panda_init(void)
{
int package = OMAP_PACKAGE_CBS;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
+
omap4_mux_init(board_mux, NULL, package);
- if (wl12xx_set_platform_data(omap_panda_wlan_data))
- pr_err(error setting wl12xx data\n);
+ if (machine_is_omap4panda()) {
+ int ret;
+
+ ret = wl12xx_set_platform_data(omap_panda_wlan_data);
+ if (ret)
+ pr_err(error setting wl12xx data\n);
+
+ platform_device_register(omap_vwlan_device);
+ }
+ omap4_panda_smsc91xx_init();
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
- platform_device_register(omap_vwlan_device);
board_serial_init();
omap4_twl6030_hsmmc_init(mmc);
So we sould have panda_common_init() and then omap4_panda_init()
and omap4_phycore_init() or something like that. No need for machine_is
tests then as the .machine_init already takes care of that test.
Regards,
Tony
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[PATCH v2] OMAP3: powerdomains: Match silicon revision to select the correct core_pwrdm definition
powerdomains3xxx_data.c defines core_3xxx_pre_es3_1_pwrdm and
core_3xxx_es3_1_pwrdm to take care of differences in core_pwrdm
implementations across revisions.
However,_pwrdm_lookup(core_pwrdm) always matches the first definition for
3630 ES 1.1 and 1.2 which is incorrect. This patch fixes this issue by adding
code to match silicon revision as well while looking up core_pwrdm in
_pwrdm_lookup().
core_3xxx_es3_1_pwrdm is different from core_3xxx_pre_es3_1_pwrdm in
that the former adds hardware save-restore support for USBTLL for 3430
ES3.1 and for 3630 ES1.1 and ES1.2.
Signed-off-by: Abhilash K V abhilash...@ti.com
---
v2:
* now tested on 3630 (ES1.2 and ES1.0) and 3530 (ES3.0 and ES3.1)
* fixed checkpatch errors/warnings.
arch/arm/mach-omap2/powerdomain.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 9af0847..82a2e30 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -32,6 +32,7 @@
#include powerdomain.h
#include clockdomain.h
#include plat/prcm.h
+#include plat/cpu.h
#include pm.h
@@ -58,6 +59,24 @@ static struct powerdomain *_pwrdm_lookup(const char *name)
list_for_each_entry(temp_pwrdm, pwrdm_list, node) {
if (!strcmp(name, temp_pwrdm-name)) {
+ if (!strcmp(name, core_pwrdm) cpu_is_omap3630()) {
+ if (omap_rev() OMAP3630_REV_ES1_0) {
+ /*
+* match omap_chip info for OMAP3630
+* Rev ES1.1, ES1.2 or higher
+*/
+ if (!(temp_pwrdm-omap_chip.oc
+CHIP_GE_OMAP3630ES1_1))
+ continue;
+ } else {
+ /* match omap_chip info for OMAP3630
+* Rev ES1.0
+*/
+ if (!(temp_pwrdm-omap_chip.oc
+ CHIP_IS_OMAP3630ES1))
+ continue;
+ }
+ }
pwrdm = temp_pwrdm;
break;
}
--
1.7.1
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[PATCH v14 REPOST 02/12] OMAP4: hwmod data: add dmtimer version information
OMAP4 has two groups of timers: version 1 timers are 1, 2, 10,
while the rest of the timers, 3-9, 11 are version 2 timers.
The version information is required by the driver so that they
could be handled correctly by it.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |3 +++
arch/arm/plat-omap/include/plat/dmtimer.h |4 +++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e1c69ff..be8ef2c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -27,6 +27,7 @@
#include plat/mcspi.h
#include plat/mcbsp.h
#include plat/mmc.h
+#include plat/dmtimer.h
#include omap_hwmod_common_data.h
@@ -3994,6 +3995,7 @@ static struct omap_hwmod_class_sysconfig
omap44xx_timer_1ms_sysc = {
static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
.name = timer,
.sysc = omap44xx_timer_1ms_sysc,
+ .rev= OMAP_TIMER_IP_VERSION_1,
};
static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
@@ -4009,6 +4011,7 @@ static struct omap_hwmod_class_sysconfig
omap44xx_timer_sysc = {
static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
.name = timer,
.sysc = omap44xx_timer_sysc,
+ .rev= OMAP_TIMER_IP_VERSION_2,
};
/* timer1 */
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index d0f3a2d..1892abf 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -57,7 +57,9 @@
* IP revision identifier so that Highlander IP
* in OMAP4 can be distinguished.
*/
-#define OMAP_TIMER_IP_VERSION_10x1
+#define OMAP_TIMER_IP_VERSION_10x1
+#define OMAP_TIMER_IP_VERSION_20x2
+
struct omap_dm_timer;
struct clk;
--
1.6.0.4
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[PATCH v14 REPOST 03/12] OMAP1: dmtimer: conversion to platform devices
From: Thara Gopinath th...@ti.com
Convert OMAP1 dmtimers into a platform devices and then registers with
device model framework so that it can be bound to corresponding driver.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap1/Makefile |2 +-
arch/arm/mach-omap1/timer.c | 174 +
arch/arm/plat-omap/dmtimer.c | 56 ++---
arch/arm/plat-omap/include/plat/dmtimer.h |8 ++
4 files changed, 195 insertions(+), 45 deletions(-)
create mode 100644 arch/arm/mach-omap1/timer.c
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 5b114d1..11c85cd 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,7 +4,7 @@
# Common support
obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
-obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o
+obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
new file mode 100644
index 000..980b23b
--- /dev/null
+++ b/arch/arm/mach-omap1/timer.c
@@ -0,0 +1,174 @@
+/**
+ * OMAP1 Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which internally
+ * generates timer device information and registers with linux
+ * device model. It also has low level function to chnage the timer
+ * input clock source.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma tarun.ka...@ti.com
+ * Thara Gopinath th...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/err.h
+#include linux/slab.h
+#include linux/platform_device.h
+
+#include mach/irqs.h
+
+#include plat/dmtimer.h
+
+#define OMAP1610_GPTIMER1_BASE 0xfffb1400
+#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
+#define OMAP1610_GPTIMER3_BASE 0xfffb2400
+#define OMAP1610_GPTIMER4_BASE 0xfffb2c00
+#define OMAP1610_GPTIMER5_BASE 0xfffb3400
+#define OMAP1610_GPTIMER6_BASE 0xfffb3c00
+#define OMAP1610_GPTIMER7_BASE 0xfffb7400
+#define OMAP1610_GPTIMER8_BASE 0xfffbd400
+
+#define OMAP1_DM_TIMER_COUNT 8
+
+static int omap1_dm_timer_set_src(struct platform_device *pdev,
+ int source)
+{
+ int n = (pdev-id - 1) 1;
+ u32 l;
+
+ l = omap_readl(MOD_CONF_CTRL_1) ~(0x03 n);
+ l |= source n;
+ omap_writel(l, MOD_CONF_CTRL_1);
+
+ return 0;
+}
+
+
+int __init omap1_dm_timer_init(void)
+{
+ int i;
+ int ret;
+ struct dmtimer_platform_data *pdata;
+ struct platform_device *pdev;
+
+ if (!cpu_is_omap16xx())
+ return 0;
+
+ for (i = 1; i = OMAP1_DM_TIMER_COUNT; i++) {
+ struct resource res[2];
+ u32 base, irq;
+
+ switch (i) {
+ case 1:
+ base = OMAP1610_GPTIMER1_BASE;
+ irq = INT_1610_GPTIMER1;
+ break;
+ case 2:
+ base = OMAP1610_GPTIMER2_BASE;
+ irq = INT_1610_GPTIMER2;
+ break;
+ case 3:
+ base = OMAP1610_GPTIMER3_BASE;
+ irq = INT_1610_GPTIMER3;
+ break;
+ case 4:
+ base = OMAP1610_GPTIMER4_BASE;
+ irq = INT_1610_GPTIMER4;
+ break;
+ case 5:
+ base = OMAP1610_GPTIMER5_BASE;
+ irq = INT_1610_GPTIMER5;
+ break;
+ case 6:
+ base = OMAP1610_GPTIMER6_BASE;
+ irq = INT_1610_GPTIMER6;
+ break;
+ case 7:
+ base = OMAP1610_GPTIMER7_BASE;
+ irq = INT_1610_GPTIMER7;
+ break;
+ case 8:
+ base = OMAP1610_GPTIMER8_BASE;
+ irq = INT_1610_GPTIMER8;
+ break;
+ default:
+ /*
+* not supposed to reach here.
+* this is to remove warning.
+*/
+
[PATCH v14 REPOST 04/12] OMAP2+: dmtimer: convert to platform devices
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver.
In addition, capability attribute of each of the timers is added in
hwmod database.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 22 +
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 22 +
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 27 ++
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 21 +
arch/arm/mach-omap2/timer.c| 136
arch/arm/plat-omap/include/plat/dmtimer.h | 10 ++-
6 files changed, 237 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index c4d0ae8..f9594c4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -358,6 +358,16 @@ static struct omap_hwmod_class omap2420_timer_hwmod_class
= {
.rev = OMAP_TIMER_IP_VERSION_1,
};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+ .timer_capability = OMAP_TIMER_ALWON,
+};
+
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_PWM,
+};
+
/* timer1 */
static struct omap_hwmod omap2420_timer1_hwmod;
static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
@@ -402,6 +412,7 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
.class = omap2420_timer_hwmod_class,
@@ -452,6 +463,7 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
.class = omap2420_timer_hwmod_class,
@@ -502,6 +514,7 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
.class = omap2420_timer_hwmod_class,
@@ -552,6 +565,7 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
.class = omap2420_timer_hwmod_class,
@@ -602,6 +616,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
.class = omap2420_timer_hwmod_class,
@@ -653,6 +668,7 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
.class = omap2420_timer_hwmod_class,
@@ -703,6 +719,7 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
.class = omap2420_timer_hwmod_class,
@@ -753,6 +770,7 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
},
},
+ .dev_attr = capability_alwon_dev_attr,
.slaves = omap2420_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
.class = omap2420_timer_hwmod_class,
@@ -803,6 +821,7 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
},
},
+ .dev_attr = capability_pwm_dev_attr,
[PATCH v14 REPOST 07/12] OMAP: dmtimer: pm_runtime support
Add pm_runtime feature to dmtimer whereby _get_sync() is called within
omap_dm_timer_enable(), _put_sync() is called in omap_dm_timer_disable().
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
[p-bas...@ti.com: added pm_runtime logic in probe()]
Signed-off-by: Partha Basak p-bas...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 31 +++-
arch/arm/plat-omap/include/plat/dmtimer.h |1 -
2 files changed, 8 insertions(+), 24 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 54564e9..0560248 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,6 +38,7 @@
#include linux/io.h
#include linux/slab.h
#include linux/err.h
+#include linux/pm_runtime.h
#include plat/dmtimer.h
@@ -193,33 +194,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_free);
void omap_dm_timer_enable(struct omap_dm_timer *timer)
{
- struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
-
- if (timer-enabled)
- return;
-
- if (!pdata-needs_manual_reset) {
- clk_enable(timer-fclk);
- clk_enable(timer-iclk);
- }
-
- timer-enabled = 1;
+ pm_runtime_get_sync(timer-pdev-dev);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
- struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
-
- if (!timer-enabled)
- return;
-
- if (!pdata-needs_manual_reset) {
- clk_disable(timer-iclk);
- clk_disable(timer-fclk);
- }
-
- timer-enabled = 0;
+ pm_runtime_put_sync(timer-pdev-dev);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
@@ -461,7 +442,7 @@ int omap_dm_timers_active(void)
struct omap_dm_timer *timer;
list_for_each_entry(timer, omap_timer_list, node) {
- if (!timer-enabled)
+ if (!timer-reserved)
continue;
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG)
@@ -536,6 +517,10 @@ static int __devinit omap_dm_timer_probe(struct
platform_device *pdev)
timer-irq = irq-start;
timer-pdev = pdev;
+ /* Skip pm_runtime_enable for OMAP1 */
+ if (!pdata-needs_manual_reset)
+ pm_runtime_enable(pdev-dev);
+
/* add the timer element to the list */
spin_lock_irqsave(dm_timer_lock, flags);
list_add_tail(timer-node, omap_timer_list);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index 90a504a..53d5da6 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -238,7 +238,6 @@ struct omap_dm_timer {
void __iomem *io_base;
unsigned long rate;
unsigned reserved:1;
- unsigned enabled:1;
unsigned posted:1;
u8 func_offset;
u8 intr_offset;
--
1.6.0.4
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[PATCH v14 REPOST 08/12] OMAP: dmtimer: add timeout to low-level routines
The low-level read and write access routines wait on write-pending register
in posted mode to make sure that previous write is complete on respective
registers. This waiting is done in an infinite while loop. Now it is being
modified to use timeout instead.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/include/plat/dmtimer.h | 34
1 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index 53d5da6..6e34094 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -36,6 +36,8 @@
#include linux/delay.h
#include linux/platform_device.h
+#include plat/common.h
+
#ifndef __ASM_ARCH_DMTIMER_H
#define __ASM_ARCH_DMTIMER_H
@@ -230,6 +232,8 @@ int omap_dm_timers_active(void);
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR WPSHIFT))
+#define MAX_WRITE_PEND_WAIT1 /* 10ms timeout delay */
+
struct omap_dm_timer {
unsigned long phys_base;
int id;
@@ -251,11 +255,16 @@ void omap_dm_timer_prepare(struct omap_dm_timer *timer);
static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
int posted, u8 func_offset)
{
- if (posted)
- while (__raw_readl(base +
- ((OMAP_TIMER_WRITE_PEND_REG + func_offset) 0xff))
-(reg WPSHIFT))
- cpu_relax();
+ int i = 0;
+
+ if (posted) {
+ omap_test_timeout(!(__raw_readl(base +
+ ((OMAP_TIMER_WRITE_PEND_REG + func_offset) 0xff))
+ (reg WPSHIFT)), MAX_WRITE_PEND_WAIT, i);
+
+ if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT))
+ pr_err(read timeout.\n);
+ }
return __raw_readl(base + (reg 0xff));
}
@@ -263,11 +272,16 @@ static inline u32 __omap_dm_timer_read(void __iomem
*base, u32 reg,
static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
int posted, u8 func_offset)
{
- if (posted)
- while (__raw_readl(base +
- ((OMAP_TIMER_WRITE_PEND_REG + func_offset) 0xff))
-(reg WPSHIFT))
- cpu_relax();
+ int i = 0;
+
+ if (posted) {
+ omap_test_timeout(!(__raw_readl(base +
+ ((OMAP_TIMER_WRITE_PEND_REG + func_offset) 0xff))
+ (reg WPSHIFT)), MAX_WRITE_PEND_WAIT, i);
+
+ if (WARN_ON(i == MAX_WRITE_PEND_WAIT))
+ pr_err(write timeout.\n);
+ }
__raw_writel(val, base + (reg 0xff));
}
--
1.6.0.4
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[PATCH v14 REPOST 06/12] OMAP: dmtimer: switch-over to platform device driver
Register timer devices by going through hwmod database using
hwmod API. The driver probes each of the registered devices.
Functionality which are already performed by hwmod framework
are removed from timer code. New set of timers present on
OMAP4 are now supported.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/timer.c | 48 +++-
arch/arm/plat-omap/dmtimer.c | 356 +
arch/arm/plat-omap/include/plat/dmtimer.h | 80 ---
3 files changed, 195 insertions(+), 289 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1c1e72b..9d47300 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -80,7 +80,8 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void
*dev_id)
{
struct clock_event_device *evt = clockevent_gpt;
- __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+ __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW,
+ clkev.intr_offset, clkev.func_offset);
evt-event_handler(evt);
return IRQ_HANDLED;
@@ -96,7 +97,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
__omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
- 0x - cycles, 1);
+ 0x - cycles, 1, clkev.func_offset);
return 0;
}
@@ -106,7 +107,8 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode
mode,
{
u32 period;
- __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+ __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate, true,
+ clkev.intr_offset, clkev.func_offset);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
@@ -114,10 +116,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode
mode,
period -= 1;
/* Looks like we need to first set the load value separately */
__omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
- 0x - period, 1);
+ 0x - period, 1, clkev.func_offset);
__omap_dm_timer_load_start(clkev.io_base,
- OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
- 0x - period, 1);
+ OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
+ 0x - period, 1, clkev.func_offset);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
@@ -191,7 +193,7 @@ static int __init omap_dm_timer_init_one(struct
omap_dm_timer *timer,
clk_put(src);
}
}
- __omap_dm_timer_reset(timer-io_base, 1, 1);
+ __omap_dm_timer_reset(timer-io_base, 1, 1, timer-func_offset);
timer-posted = 1;
timer-rate = clk_get_rate(timer-fclk);
@@ -212,7 +214,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
omap2_gp_timer_irq.dev_id = (void *)clkev;
setup_irq(clkev.irq, omap2_gp_timer_irq);
- __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+ __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW,
+ clkev.intr_offset, clkev.func_offset);
clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
clockevent_gpt.shift);
@@ -253,7 +256,8 @@ static struct omap_dm_timer clksrc;
static DEFINE_CLOCK_DATA(cd);
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
- return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+ return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1,
+ clksrc.func_offset);
}
static struct clocksource clocksource_gpt = {
@@ -268,7 +272,8 @@ static void notrace dmtimer_update_sched_clock(void)
{
u32 cyc;
- cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1,
+ clksrc.func_offset);
update_sched_clock(cd, cyc, (u32)~0);
}
@@ -278,7 +283,8 @@ unsigned long long notrace sched_clock(void)
u32 cyc = 0;
if (clksrc.reserved)
- cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1,
+ clksrc.func_offset);
return cyc_to_sched_clock(cd, cyc, (u32)~0);
}
@@ -476,3 +482,23 @@ static int __init omap_timer_init(struct omap_hwmod *oh,
void *unused)
[PATCH v14 REPOST 10/12] OMAP: dmtimer: mark clocksource and clockevent timers reserved
In driver probe use sys_timer_reserved to identify which all timers
have already been used for clocksource and clockevent. Mark all those
timers as reserved so that no one else can use them.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap1/timer.c |2 ++
arch/arm/plat-omap/dmtimer.c |8 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 980b23b..0b318c7 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -41,6 +41,8 @@
#define OMAP1_DM_TIMER_COUNT 8
+u32 sys_timer_reserved;
+
static int omap1_dm_timer_set_src(struct platform_device *pdev,
int source)
{
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index be55e42..8c8cb00 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -513,10 +513,14 @@ static int __devinit omap_dm_timer_probe(struct
platform_device *pdev)
timer-irq = irq-start;
timer-pdev = pdev;
- /* Skip pm_runtime_enable for OMAP1 */
- if (!pdata-needs_manual_reset)
+ if (!pdata-needs_manual_reset) {
pm_runtime_enable(pdev-dev);
+ /* Mark clocksource and clockevent timers as reserved */
+ if ((sys_timer_reserved (pdev-id - 1)) 0x1)
+ timer-reserved = 1;
+ }
+
/* add the timer element to the list */
mutex_lock(dm_timer_mutex);
list_add_tail(timer-node, omap_timer_list);
--
1.6.0.4
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[PATCH v14 REPOST 00/12] dmtimer adaptation to platform_driver
Adaptation of dmtimer code to platform driver using omap_device and
omap_hwmod abstraction. It also include pm-runtime and off-mode support.
Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Branch: Master
I have applied the patch series on top of Tony Lindgren's dmtimer patch series
taken from
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git
Branch:devel-timer
REPOST:
- Following comments from Todd Poynor toddpoy...@google.com implemented
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg52677.html
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg52676.html
- Incorrect balancing of *_runtime_get/put_sync for wakeup domain timers
in the off-mode patch corrected.
Test Info:
- OMAP4430SDP: Functional tests.
- OMAP3430SDP: Functional and Off-mode tests.
- OMAP2430SDP: Functional tests.
- OMAP2420SDP: Functional tests.
- OMAP1710SDP: Boot test.
v14:
(1) Baselined on top of Tony Lindgren's latest timer patch series.
(2) Context save/restore routines.
(3) Off-mode support
v13:
(1) Handling of early timer removed because this is being taken care by
Tony's patch series.
(2) Timers reserved for clockevent/clocksource during early boot are
registered and marked reserved.
(3) Platform specific timer code merged to mach-omap2/timer.c.
(4) Timer capabilities are added in the hwmod database to each of the
omap timers.
(5) plat-omap/dmtimer.c plat-omap/include/plat/dmtimer.h are converted
to a driver by moving them to drivers/misc/timer-omap.c and
include/linux/timer-omap.h
v12:
(1) Remove registration and initialization of all timers during early boot.
Initialize only the system timer which is set by the board file or default
value assigned to it. This timer is not considered later during rest of the
timers initialization.
(2) Use mutex instead of spinlock since there is no interrupt context.
(3) Remove hacky code to manage GPTIMER12 in mach-omap2/dmtimer.c. This is
now changed to use dev_attr instead to identify if it is a secure timer.
In the hwmod database, any secure timer entry can use this dev_attr so that
driver avoids registering tha particular timer.
(4) Removed reset function from OMAP1 and kept it back to its original place
in plat-omap/dmtimer.c, with modification of course. Instead of (is_omap16xx)
flag a new variable (needs_manual_reset) added. This flag is set for OMAP1.
So, call to reset function is made if this value is set implying that reset
is called only for OMAP1.
(5) Timer enable and disable functions cleanup with checks for early boot
condition removed. Added new interface wrapper function to configure
system timer clock source.
(6) Move OMAP4 specific register offsets from mach-omap2 to driver code
along with other register offset definitions.
(7) omap2_dm_timer_early_init() renamed to omap2_system_timer_init(),
omap2_dm_timer_normal_init() renamed to omap2_dm_timer_init().
(8) Use dev_err() instead of pr_err() in low level read/write functions.
v11:
(1) Removed early timer initialization call from omap2_init_common_devices()
in io.c. It is now called from omap2_gp_timer_init() in timer-gp.c as part
of following call sequence:
start_kernel()-time_init()-timer-init()-omap2_gp_timer_init()
(2) Basedlined on top of Paul's patch series mentioned above.
v10:
(1) Update PM runtime for active early timers so that PM runtime userspace
info is correct.
(2) Include code to configure timers to POSTED mode which got missed in
the previous version.
(3) Remove pm runtime_enable from OMAP1 specific code since this is not
applicable.
v9:
(1) In OMAP3 hwmod database, added entry for timer12 which was missing.
Beagle board uses timer12 as its millisecond timer.
(2) In OMAP3 hwmod database, rectified in-correct prcm configurations
for timer10 and timer11.
From:
.prcm = {
.module_bit = OMAP24XX_EN_GPT10_SHIFT,
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
},
To:
.prcm = {
.module_bit = OMAP3430_EN_GPT10_SHIFT,
.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
},
(3) In OMAP3 hwmod database, removed timer master port entry for all
timers because it is not supported.
static struct omap_hwmod_ocp_if *omap3xxx_timer7_masters[] = {
omap3xxx_l4_per__timer7,
};
(4) In OMAP4 hwmod database, added SIDLE_SMART_WKUP flag for
non-millisecond timers.
(5) In OMAP3 hwmod database, rectified sysconfig configuration for
non-millisecond timers.
From: omap_hwmod_sysc_type2 To: omap_hwmod_sysc_type1.
This was preventing system to go to RETENTION and OFF modes.
v8:
(1) Baselined on Tony's tree in omap-for-linus branch
(2) The last patch in v7 series has been removed because it is fixed
by following patch:
commit: 78f26e872f77b6312273216de1a8f836c6f2e143
OMAP: hwmod: Set autoidle after smartidle during _sysc_enable
v7:
(1) In omap1_dm_timer_set_src(), the computation of shift value to
[PATCH v14 REPOST 01/12] OMAP2+: dmtimer: add device names to flck nodes
Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be
retrieved by doing a clk_get with the corresponding device pointers or
device names.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/clock2420_data.c | 52 -
arch/arm/mach-omap2/clock2430_data.c | 48 +++
arch/arm/mach-omap2/clock3xxx_data.c | 36 +++
arch/arm/mach-omap2/clock44xx_data.c | 33 +
4 files changed, 167 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c
b/arch/arm/mach-omap2/clock2420_data.c
index 2926d02..15114f5 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1838,9 +1838,9 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, gpt9_ick, gpt9_ick, CK_242X),
CLK(NULL, gpt9_fck, gpt9_fck, CK_242X),
CLK(NULL, gpt10_ick,gpt10_ick, CK_242X),
- CLK(NULL, gpt10_fck,gpt10_fck, CK_242X),
+ CLK(NULL, gpt_10fck,gpt10_fck, CK_242X),
CLK(NULL, gpt11_ick,gpt11_ick, CK_242X),
- CLK(NULL, gpt11_fck,gpt11_fck, CK_242X),
+ CLK(NULL, gpt_11fck,gpt11_fck, CK_242X),
CLK(NULL, gpt12_ick,gpt12_ick, CK_242X),
CLK(NULL, gpt12_fck,gpt12_fck, CK_242X),
CLK(omap-mcbsp.1, ick, mcbsp1_ick,CK_242X),
@@ -1898,6 +1898,54 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, pka_ick, pka_ick, CK_242X),
CLK(NULL, usb_fck, usb_fck, CK_242X),
CLK(musb-hdrc,fck, osc_ck,CK_242X),
+ CLK(omap_timer.1, fck, gpt1_fck, CK_242X),
+ CLK(omap_timer.2, fck, gpt2_fck, CK_242X),
+ CLK(omap_timer.3, fck, gpt3_fck, CK_242X),
+ CLK(omap_timer.4, fck, gpt4_fck, CK_242X),
+ CLK(omap_timer.5, fck, gpt5_fck, CK_242X),
+ CLK(omap_timer.6, fck, gpt6_fck, CK_242X),
+ CLK(omap_timer.7, fck, gpt7_fck, CK_242X),
+ CLK(omap_timer.8, fck, gpt8_fck, CK_242X),
+ CLK(omap_timer.9, fck, gpt9_fck, CK_242X),
+ CLK(omap_timer.10,fck, gpt10_fck, CK_242X),
+ CLK(omap_timer.11,fck, gpt11_fck, CK_242X),
+ CLK(omap_timer.12,fck, gpt12_fck, CK_242X),
+ CLK(omap_timer.1, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.2, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.3, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.4, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.5, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.6, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.7, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.8, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.9, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.10,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.11,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.12,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.1, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.2, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.3, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.4, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.5, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.6, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.7, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.8, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.9, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.10,sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.11,sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.12,sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.1, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.2, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.3, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.4, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.5, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.6, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.7, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.8, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.9, alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.10,alt_ck, alt_ck,CK_243X),
+ CLK(omap_timer.11,alt_ck, alt_ck,
[PATCH v14 REPOST 11/12] OMAP: dmtimer: add context save/restore routines
Define context register structure and make it member of struct omap_dm_timer.
Also define two routines to save and restore dmtimer context to be used
subsequently.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 48 +
arch/arm/plat-omap/include/plat/dmtimer.h | 24 ++
2 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 8c8cb00..cdef48b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -87,6 +87,54 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer
*timer, u32 reg,
timer-func_offset);
}
+static void omap_timer_save_context(struct omap_dm_timer *timer)
+{
+ timer-context.tiocp_cfg =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
+ timer-context.tistat =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG);
+ timer-context.tisr =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
+ timer-context.tier =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_INT_EN_REG);
+ timer-context.twer =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
+ timer-context.tclr =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+ timer-context.tcrr =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
+ timer-context.tldr =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
+ timer-context.tmar =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
+ timer-context.tsicr =
+ omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
+}
+
+static void omap_timer_restore_context(struct omap_dm_timer *timer)
+{
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG,
+ timer-context.tiocp_cfg);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_SYS_STAT_REG,
+ timer-context.tistat);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+ timer-context.tisr);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG,
+ timer-context.tier);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
+ timer-context.twer);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
+ timer-context.tclr);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
+ timer-context.tcrr);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
+ timer-context.tldr);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
+ timer-context.tmar);
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+ timer-context.tsicr);
+}
+
static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
{
int c;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h
b/arch/arm/plat-omap/include/plat/dmtimer.h
index 6e34094..9a2d7e3 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -234,6 +234,29 @@ int omap_dm_timers_active(void);
#define MAX_WRITE_PEND_WAIT1 /* 10ms timeout delay */
+struct timer_regs {
+ u32 tidr;
+ u32 tiocp_cfg;
+ u32 tistat;
+ u32 tisr;
+ u32 tier;
+ u32 twer;
+ u32 tclr;
+ u32 tcrr;
+ u32 tldr;
+ u32 ttrg;
+ u32 twps;
+ u32 tmar;
+ u32 tcar1;
+ u32 tsicr;
+ u32 tcar2;
+ u32 tpir;
+ u32 tnir;
+ u32 tcvr;
+ u32 tocr;
+ u32 towr;
+};
+
struct omap_dm_timer {
unsigned long phys_base;
int id;
@@ -245,6 +268,7 @@ struct omap_dm_timer {
unsigned posted:1;
u8 func_offset;
u8 intr_offset;
+ struct timer_regs context;
struct platform_device *pdev;
struct list_head node;
};
--
1.6.0.4
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[PATCH v14 REPOST 05/12] OMAP: dmtimer: platform driver
Add dmtimer platform driver functions which include:
(1) platform driver initialization
(2) driver probe function
(3) driver remove function
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 145 +++--
arch/arm/plat-omap/include/plat/dmtimer.h | 11 ++
2 files changed, 149 insertions(+), 7 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 995bab0..8a22583 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -35,14 +35,9 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include linux/init.h
-#include linux/spinlock.h
-#include linux/errno.h
-#include linux/list.h
-#include linux/clk.h
-#include linux/delay.h
#include linux/io.h
#include linux/module.h
+#include linux/slab.h
#include mach/hardware.h
#include plat/dmtimer.h
#include mach/irqs.h
@@ -149,6 +144,7 @@ static const char **dm_source_names;
static struct clk **dm_source_clocks;
static spinlock_t dm_timer_lock;
+static LIST_HEAD(omap_timer_list);
/*
* Reads timer registers in posted and non-posted mode. The posted mode bit
@@ -544,7 +540,142 @@ int omap_dm_timers_active(void)
}
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
-static int __init omap_dm_timer_init(void)
+/**
+ * omap_dm_timer_probe - probe function called for every registered device
+ * @pdev: pointer to current timer platform device
+ *
+ * Called by driver framework at the end of device registration for all
+ * timer devices.
+ */
+static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
+{
+ int ret;
+ unsigned long flags;
+ struct omap_dm_timer *timer;
+ struct resource *mem, *irq, *ioarea;
+ struct dmtimer_platform_data *pdata = pdev-dev.platform_data;
+
+ if (!pdata) {
+ dev_err(pdev-dev, %s: no platform data.\n, __func__);
+ return -ENODEV;
+ }
+
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (unlikely(!irq)) {
+ dev_err(pdev-dev, %s: no IRQ resource.\n, __func__);
+ return -ENODEV;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!mem)) {
+ dev_err(pdev-dev, %s: no memory resource.\n, __func__);
+ return -ENODEV;
+ }
+
+ ioarea = request_mem_region(mem-start, resource_size(mem),
+ pdev-name);
+ if (!ioarea) {
+ dev_err(pdev-dev, %s: region already claimed.\n, __func__);
+ return -EBUSY;
+ }
+
+ timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+ if (!timer) {
+ dev_err(pdev-dev, %s: no memory for omap_dm_timer.\n,
+ __func__);
+ ret = -ENOMEM;
+ goto err_free_ioregion;
+ }
+
+ timer-io_base = ioremap(mem-start, resource_size(mem));
+ if (!timer-io_base) {
+ dev_err(pdev-dev, %s: ioremap failed.\n, __func__);
+ ret = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ if (pdata-timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
+ timer-func_offset = VERSION2_TIMER_WAKEUP_EN_REG_OFFSET;
+ timer-intr_offset = VERSION2_TIMER_STAT_REG_OFFSET;
+ }
+
+ timer-id = pdev-id;
+ timer-irq = irq-start;
+ timer-pdev = pdev;
+
+ /* add the timer element to the list */
+ spin_lock_irqsave(dm_timer_lock, flags);
+ list_add_tail(timer-node, omap_timer_list);
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+
+ dev_dbg(pdev-dev, Device Probed.\n);
+
+ return 0;
+
+err_free_mem:
+ kfree(timer);
+
+err_free_ioregion:
+ release_mem_region(mem-start, resource_size(mem));
+
+ return ret;
+}
+
+/**
+ * omap_dm_timer_remove - cleanup a registered timer device
+ * @pdev: pointer to current timer platform device
+ *
+ * Called by driver framework whenever a timer device is unregistered.
+ * In addition to freeing platform resources it also deletes the timer
+ * entry from the local list.
+ */
+static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
+{
+ struct omap_dm_timer *timer;
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ spin_lock_irqsave(dm_timer_lock, flags);
+ list_for_each_entry(timer, omap_timer_list, node)
+ if (timer-pdev-id == pdev-id) {
+ list_del(timer-node);
+ kfree(timer);
+ ret = 0;
+ break;
+ }
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+
+ return ret;
+}
+
+static struct platform_driver omap_dm_timer_driver = {
+ .probe = omap_dm_timer_probe,
+ .remove = omap_dm_timer_remove,
+ .driver = {
+
[PATCH v14 REPOST 09/12] OMAP: dmtimer: use mutex instead of spinlock
Since the spinlock is not used in any interrupt context we can
replace it with mutex instead.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 27 +++
1 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 0560248..be55e42 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,7 +43,7 @@
#include plat/dmtimer.h
static LIST_HEAD(omap_timer_list);
-static DEFINE_SPINLOCK(dm_timer_lock);
+static DEFINE_MUTEX(dm_timer_mutex);
/**
* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
@@ -136,9 +136,8 @@ void omap_dm_timer_prepare(struct omap_dm_timer *timer)
struct omap_dm_timer *omap_dm_timer_request(void)
{
struct omap_dm_timer *timer = NULL, *t;
- unsigned long flags;
- spin_lock_irqsave(dm_timer_lock, flags);
+ mutex_lock(dm_timer_mutex);
list_for_each_entry(t, omap_timer_list, node) {
if (t-reserved)
continue;
@@ -147,7 +146,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
timer-reserved = 1;
break;
}
- spin_unlock_irqrestore(dm_timer_lock, flags);
+ mutex_unlock(dm_timer_mutex);
if (timer)
omap_dm_timer_prepare(timer);
@@ -161,9 +160,8 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request);
struct omap_dm_timer *omap_dm_timer_request_specific(int id)
{
struct omap_dm_timer *timer = NULL, *t;
- unsigned long flags;
- spin_lock_irqsave(dm_timer_lock, flags);
+ mutex_lock(dm_timer_mutex);
list_for_each_entry(t, omap_timer_list, node) {
if (t-pdev-id == id !t-reserved) {
timer = t;
@@ -171,7 +169,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
break;
}
}
- spin_unlock_irqrestore(dm_timer_lock, flags);
+ mutex_unlock(dm_timer_mutex);
if (timer)
omap_dm_timer_prepare(timer);
@@ -220,14 +218,13 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
int i = 0;
struct omap_dm_timer *timer = NULL;
- unsigned long flags;
/* If ARMXOR cannot be idled this function call is unnecessary */
if (!(inputmask (1 1)))
return inputmask;
/* If any active timer is using ARMXOR return modified mask */
- spin_lock_irqsave(dm_timer_lock, flags);
+ mutex_lock(dm_timer_mutex);
list_for_each_entry(timer, omap_timer_list, node) {
u32 l;
@@ -240,7 +237,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
}
i++;
}
- spin_unlock_irqrestore(dm_timer_lock, flags);
+ mutex_unlock(dm_timer_mutex);
return inputmask;
}
@@ -464,7 +461,6 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
{
int ret;
- unsigned long flags;
struct omap_dm_timer *timer;
struct resource *mem, *irq, *ioarea;
struct dmtimer_platform_data *pdata = pdev-dev.platform_data;
@@ -522,9 +518,9 @@ static int __devinit omap_dm_timer_probe(struct
platform_device *pdev)
pm_runtime_enable(pdev-dev);
/* add the timer element to the list */
- spin_lock_irqsave(dm_timer_lock, flags);
+ mutex_lock(dm_timer_mutex);
list_add_tail(timer-node, omap_timer_list);
- spin_unlock_irqrestore(dm_timer_lock, flags);
+ mutex_unlock(dm_timer_mutex);
dev_dbg(pdev-dev, Device Probed.\n);
@@ -550,10 +546,9 @@ err_free_ioregion:
static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
{
struct omap_dm_timer *timer;
- unsigned long flags;
int ret = -EINVAL;
- spin_lock_irqsave(dm_timer_lock, flags);
+ mutex_lock(dm_timer_mutex);
list_for_each_entry(timer, omap_timer_list, node)
if (timer-pdev-id == pdev-id) {
list_del(timer-node);
@@ -561,7 +556,7 @@ static int __devexit omap_dm_timer_remove(struct
platform_device *pdev)
ret = 0;
break;
}
- spin_unlock_irqrestore(dm_timer_lock, flags);
+ mutex_unlock(dm_timer_mutex);
return ret;
}
--
1.6.0.4
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[PATCH v14 REPOST 12/12] OMAP: dmtimer: Off mode support
Clock is enabled only when timer is started and disabled when the the timer
is stopped. Therefore before accessing registers in functions clock is enabled
and then disabled back at the end of access.
Context save and restore functions are called as needed based upon whether the
context is lost or not.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap2/timer.c | 17 +
arch/arm/plat-omap/dmtimer.c | 97 +++--
arch/arm/plat-omap/include/plat/dmtimer.h |9 +++
3 files changed, 118 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 9d47300..d1c6219 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -44,6 +44,9 @@
#include plat/common.h
#include plat/omap_hwmod.h
#include plat/omap_device.h
+#include plat/omap-pm.h
+
+#include powerdomain.h
/* Parent clocks, eventually these will come from the clock framework */
@@ -409,6 +412,16 @@ static int omap2_dm_timer_set_src(struct platform_device
*pdev, int source)
return ret;
}
+#ifdef CONFIG_PM
+static int omap_timer_get_context_loss(struct device *dev)
+{
+ return omap_pm_get_dev_context_loss_count(dev);
+}
+
+#else
+#define omap_gpio_get_context_loss NULL
+#endif
+
struct omap_device_pm_latency omap2_dmtimer_latency[] = {
{
.deactivate_func = omap_device_idle_hwmods,
@@ -437,6 +450,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh,
void *unused)
struct dmtimer_platform_data *pdata;
struct omap_device *od;
struct omap_timer_capability_dev_attr *timer_dev_attr;
+ struct powerdomain *pwrdm;
pr_debug(%s: %s\n, __func__, oh-name);
@@ -466,6 +480,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh,
void *unused)
pdata-set_timer_src = omap2_dm_timer_set_src;
pdata-timer_ip_type = oh-class-rev;
+ pwrdm = omap_hwmod_get_pwrdm(oh);
+ pdata-loses_context = pwrdm_can_ever_lose_context(pwrdm);
+ pdata-get_context_loss_count = omap_timer_get_context_loss;
od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
omap2_dmtimer_latency,
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index cdef48b..db14d7f 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -151,12 +151,14 @@ static void omap_dm_timer_wait_for_reset(struct
omap_dm_timer *timer)
static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
+ omap_dm_timer_enable(timer);
if (timer-pdev-id != 1) {
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
omap_dm_timer_wait_for_reset(timer);
}
__omap_dm_timer_reset(timer-io_base, 0, 0, timer-func_offset);
+ omap_dm_timer_disable(timer);
timer-posted = 1;
}
@@ -171,14 +173,13 @@ void omap_dm_timer_prepare(struct omap_dm_timer *timer)
return;
}
- omap_dm_timer_enable(timer);
-
if (pdata-needs_manual_reset)
omap_dm_timer_reset(timer);
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
timer-posted = 1;
+ timer-context_changed = true;
}
struct omap_dm_timer *omap_dm_timer_request(void)
@@ -230,7 +231,6 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
void omap_dm_timer_free(struct omap_dm_timer *timer)
{
- omap_dm_timer_disable(timer);
clk_put(timer-fclk);
WARN_ON(!timer-reserved);
@@ -311,6 +311,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
void omap_dm_timer_trigger(struct omap_dm_timer *timer)
{
+ if (unlikely(!timer-reserved)) {
+ pr_err(%s: timer%d not enabled.\n, __func__, timer-id);
+ return;
+ }
+
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
@@ -319,6 +324,20 @@ void omap_dm_timer_start(struct omap_dm_timer *timer)
{
u32 l;
+ omap_dm_timer_enable(timer);
+
+ if (timer-loses_context) {
+ u32 ctx_loss_cnt_after;
+
+ ctx_loss_cnt_after =
+ timer-get_context_loss_count(timer-pdev-dev);
+ if ((ctx_loss_cnt_after != timer-ctx_loss_count)
+ timer-context_saved) {
+ omap_timer_restore_context(timer);
+ timer-context_saved = false;
+ }
+ }
+
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (!(l OMAP_TIMER_CTRL_ST)) {
l |= OMAP_TIMER_CTRL_ST;
@@ -340,6 +359,19 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
__omap_dm_timer_stop(timer-io_base, timer-posted, rate,
is_omap2, timer-intr_offset, timer-func_offset);
+
+ if (timer-loses_context) {
+
Re: [PATCHv5 01/11] OMAP: prcm: switch to a chained IRQ handler mechanism
On Tue, Jul 5, 2011 at 3:57 PM, Tero Kristo t-kri...@ti.com wrote:
Introduce a chained interrupt handler mechanism for the PRCM
interrupt, so that individual PRCM event can cleanly be handled by
handlers in separate drivers. We do this by introducing PRCM event
names, which are then matched to the particular PRCM interrupt bit
depending on the specific OMAP SoC being used.
arch/arm/mach-omap2/prcm.c implements the chained interrupt mechanism
itself, with individual PRCM events for OMAP3 and OMAP4 being
described in arch/arm/mach-omap2/prcm3xxx.c and
arch/arm/mach-omap2/prcm4xxx.c respectively. At initialization time,
the set of PRCM events is filtered against the SoC on which we are
running, keeping only the ones that are actually useful. All the logic
is written to be generic with regard to OMAP3/OMAP4, even though OMAP3
has single PRCM event registers and OMAP4 has two PRCM event
registers.
Patch tested on OMAP3 beagleboard.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Avinash.H.M avinas...@ti.com
Cc: Kevin Hilman khil...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Govindraj.R govindraj.r...@ti.com
Cc: Felipe Balbi ba...@ti.com
---
arch/arm/mach-omap2/Makefile | 4 +
arch/arm/mach-omap2/pm34xx.c | 108 --
arch/arm/mach-omap2/prcm.c | 158
arch/arm/mach-omap2/prcm3xxx.c | 112 ++
arch/arm/mach-omap2/prcm4xxx.c | 137 +++
arch/arm/plat-omap/include/plat/prcm.h | 46 +
6 files changed, 495 insertions(+), 70 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm3xxx.c
create mode 100644 arch/arm/mach-omap2/prcm4xxx.c
[..]
+ if (irq_setup-base_irq 0) {
+ pr_err(PRCM: failed to allocate irq descs\n);
+ irq_set_chained_handler(irq_setup-irq, NULL);
+ return irq_setup-base_irq;
+ }
+
+ for (i = 0; i = max_irq / 32; i++) {
+ gc = irq_alloc_generic_chip(PRCM, 1,
+ irq_setup-base_irq + i * 32, NULL, handle_level_irq);
+
+ ct = gc-chip_types;
+ ct-chip.irq_ack = irq_gc_ack;
With patch [1] already part of 3.0-rc7 Mainline.
irq_gc_ack needs to be changed as below.
ct-chip.irq_ack = irq_gc_ack_set_bit;
I dropped tmp patches from v5 and picked rest of v5 applied
on wip-runtime patches and tested same.
Most of the things worked fine on 3430SDP
System wide suspend (with console_suspend)
retention and off-mode.
I have hosted a branch with the same if some else
is interested in testing.
[rc7 + wip_uart runtime patches + irq_chaining patches]
git://gitorious.org/runtime_3-0/runtime_3-0.git
Branch: wip_irqchn
feel free to add,
Acked-by: Govindraj.R govindraj.r...@ti.com
Tested-by: Govindraj.R govindraj.r...@ti.com
--
Thanks,
Govindraj.R
[1]:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5;hp=d30e1521b2afb5e6f21ca8bc1a4b6ec2afc93597
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How to get the handler of a device that has been open
Hi all: I have got a problem while I want to open a mutex device, which has been opened by another process. such as /dev/apls9802als, which is opened while the system boot up. But I have to do some test to its read function in its driver provided to the user space. Is there a way that I can close the handler that has been opened and reopen it by the test program I write? Any hacking way for this? Thanks. Best Regards Shijie -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/6] OMAP4: Add missing clock divider for OCP_ABE_ICLK
Hi Paul,
On 7/15/2011 3:21, Paul Walmsley wrote:
cc'ing Benoît
Hi Jon
On Thu, 14 Jul 2011, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the
parent clock of the AESS_FCLK is the ABE_FCLK...
ABE_FCLK -- AESS_FCLK -- OCP_ABE_ICLK
The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which
determine their operational frequency. However, the dividers for
the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit,
which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to
0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2.
Similarly, when this bit is set to 1, the AESS_FCLK divider is 2
and the OCP_ABE_ICLK is 1.
Sigh. This type of hardware design makes software design difficult :-(
Hopefully, because this is a interface clock the impact is really
minimal...more below...
The above relationship between the AESS_FCLK and OCP_ABE_ICLK
dividers ensure that the OCP_ABE_ICLK clock is always half the
frequency of the ABE_CLK...
OCP_ABE_ICLK = ABE_FCLK/2
The divider for the OCP_ABE_ICLK is currently missing so add a
divider that will ensure the OCP_ABE_ICLK frequency is always half
the ABE_FCLK frequency.
Signed-off-by: Jon Hunterjon-hun...@ti.com
---
arch/arm/mach-omap2/clock44xx_data.c | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index 8c96567..6e158ce 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1301,11 +1301,25 @@ static struct clk mcasp3_fclk = {
.recalc =followparent_recalc,
};
+static const struct clksel_rate div2_2to1_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+ { .div = 0 },
+};
+
+static const struct clksel ocp_abe_iclk_div[] = {
+ { .parent =aess_fclk, .rates = div2_2to1_rates },
+ { .parent = NULL },
+};
+
static struct clk ocp_abe_iclk = {
.name = ocp_abe_iclk,
.parent =aess_fclk,
+ .clksel = ocp_abe_iclk_div,
+ .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+ .clksel_mask= OMAP4430_CLKSEL_AESS_FCLK_MASK,
.ops=clkops_null,
- .recalc =followparent_recalc,
+ .recalc =omap2_clksel_recalc,
};
static struct clk per_abe_24m_fclk = {
I guess the reason that this patch can get away with this is because it
doesn't allow software to change the rate of ocp_abe_iclk, and the
ocp_abe_iclk is a child of aess_fclk, so when aess_fclk is changed, it
will recalc ocp_abe_iclk.
Benoît, what do you think? Is this a reasonable approach for the script?
Or do we need to deal with some kind of 'linked clock' implementation...
If you want my two cents on this matter, I would say that...
1). People should not need to configure the ocp_abe_iclk clock
directly, because regardless of the divider setting it is always 1/2 the
abe_fclk. In other words, only the aess_fclk frequency is really
changing because of the divider and the above relationship ensures that
the ocp_abe_iclk is always the same frequency. So a user only cares
about the aess_fclk frequency and the ocp_abe_iclk frequency is
handled for them.
2). The ocp_abe_iclk is an interface clock and is not a parent to any
other functional clock and therefore, is not driving any internal logic
in a peripheral which would have a direct impact of the speed of that
peripheral. However, there does appear to be another bug here in the
clock44xx_data.c as it shows that the ocp_abe_iclk is parent to the
slimbus1_fck which I believe is incorrect. According to the TRM, the
the ocp_abe_iclk is parent to the slimbus1_iclk. I can send another
patch for this. However, I will let Benoit chime in first.
Cheers
Jon
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Re: [PATCH 0/6] OMAP3+ Clock Fixes
Hi Paul, On 7/15/2011 3:16, Paul Walmsley wrote: Hi Jon On Thu, 14 Jul 2011, Jon Hunter wrote: From: Jon Hunterjon-hun...@ti.com Various clock fixes for OMAP3 and OMAP4 devices. Plus one debug patch (if anyone is interested). Jon Hunter (4): OMAP4: Add missing clock divider for OCP_ABE_ICLK OMAP3+: use DPLLs recalc function instead of omap2_get_dpll_rate OMAP3+: Update DPLL Fint range for OMAP36xx and OMAP4xxx devices OMAP: Add debugfs node to show the summary of all clocks Mike Turquette (2): OMAP4: Clock: round_rate and recalc functions for DPLL_ABE OMAP3+: use DPLL's round_rate when setting rate Could you please repost these patches, cc'ing linux-arm-ker...@lists.infradead.org ? No problem. Will re-send. I will drop patch #6 (I see this in your queue) and I may add one for the slimbus fck bug too. However, I will wait for Benoit's feedback on #1. Cheers Jon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 0/2] join omap4panda and pcm049
First try to join both boards. Only compile testet. basis for discusson Jan Weitzel (2): omap4: board-omap4panda: prepare for join omap4: board-omap4panda: join Phytec phyCORE-OMAP4 arch/arm/mach-omap2/Kconfig |6 + arch/arm/mach-omap2/board-omap4panda.c | 817 +++--- arch/arm/plat-omap/include/plat/uncompress.h |1 + 3 files changed, 616 insertions(+), 208 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] omap4: board-omap4panda: join Phytec phyCORE-OMAP4
This adds support for the Phytec OMAP4430 board called phyCORE-OMAP4 PCM049.
It reuse board-omap4panda platform code.
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
arch/arm/mach-omap2/Kconfig |6 +
arch/arm/mach-omap2/board-omap4panda.c | 321 ++
arch/arm/plat-omap/include/plat/uncompress.h |1 +
3 files changed, 328 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6b88799..d5e4b60 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -333,6 +333,12 @@ config MACH_OMAP4_PANDA
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE
+config MACH_PCM049
+ bool OMAP4 based phyCORE OMAP4
+ depends on ARCH_OMAP4
+ default y
+ select OMAP_PACKAGE_CBS
+
config OMAP3_EMU
bool OMAP3 debugging peripherals
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/board-omap4panda.c
b/arch/arm/mach-omap2/board-omap4panda.c
index b9bea86..2395089 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -25,9 +25,13 @@
#include linux/gpio.h
#include linux/usb/otg.h
#include linux/i2c/twl.h
+#include linux/i2c/at24.h
+#include linux/mfd/stmpe.h
+#include linux/leds-pca9532.h
#include linux/regulator/machine.h
#include linux/regulator/fixed.h
#include linux/wl12xx.h
+#include linux/smsc911x.h
#include mach/hardware.h
#include mach/omap4-common.h
@@ -39,6 +43,8 @@
#include plat/board.h
#include plat/common.h
#include plat/usb.h
+#include plat/gpmc.h
+#include plat/gpmc-smsc911x.h
#include plat/mmc.h
#include video/omap-panel-generic-dpi.h
@@ -52,6 +58,11 @@
#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
+#define OMAP4_PCM049_ETH_GPIO_IRQ 121
+#define OMAP4_PCM049_ETH_CS5
+#define OMAP4_PCM049_STMPE811_GPIO_IRQ 117
+#define OMAP4_PCM049_LCD_ENABLE118
+
static struct gpio_led gpio_leds[] = {
{
.name = pandaboard::status1,
@@ -671,3 +682,313 @@ MACHINE_START(OMAP4_PANDA, OMAP4 Panda board)
.init_machine = omap4_panda_init,
.timer = omap4_timer,
MACHINE_END
+
+/* phyCORE OMAP4 */
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
+ .cs = OMAP4_PCM049_ETH_CS,
+ .gpio_irq = OMAP4_PCM049_ETH_GPIO_IRQ,
+ .gpio_reset = -EINVAL,
+ .flags = SMSC911X_USE_16BIT,
+};
+
+static inline void __init pcm049_init_smsc911x(void)
+{
+ omap_mux_init_gpio(OMAP4_PCM049_ETH_GPIO_IRQ, OMAP_PIN_INPUT);
+ gpmc_smsc911x_init(board_smsc911x_data);
+}
+#else
+static inline void __init pcm049_init_smsc911x(void) { return; }
+#endif
+/* Fixed regulator for max1027 */
+static struct regulator_consumer_supply pcm049_vcc_3v3_consumer_supply[] = {
+ REGULATOR_SUPPLY(vcc, 4-0064),
+};
+
+struct regulator_init_data pcm049_vcc_3v3_initdata = {
+ .consumer_supplies = pcm049_vcc_3v3_consumer_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pcm049_vcc_3v3_consumer_supply),
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct fixed_voltage_config pcm049_vcc_3v3_config = {
+ .supply_name= pcm049_vcc_3v3,
+ .microvolts = 330,
+ .gpio = -EINVAL,
+ .enabled_at_boot= 1,
+ .init_data = pcm049_vcc_3v3_initdata,
+};
+
+static struct platform_device pcm049_vcc_3v3_device = {
+ .name = reg-fixed-voltage,
+ .id = 0,
+ .dev= {
+ .platform_data = pcm049_vcc_3v3_config,
+ },
+};
+/* Display */
+static int pcm049_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+ return gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 1);
+}
+
+static void pcm049_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+ gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 0);
+ return;
+}
+
+/* Using generic display panel */
+static struct panel_generic_dpi_data omap4_dpi_panel = {
+ .name = pd050vl1,
+ .platform_enable= pcm049_panel_enable_lcd,
+ .platform_disable = pcm049_panel_disable_lcd,
+};
+
+struct omap_dss_device pcm049_dpi_device = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = dpi,
+ .driver_name= generic_dpi_panel,
+ .data = omap4_dpi_panel,
+ .phy.dpi.data_lines = 24,
+ .channel= OMAP_DSS_CHANNEL_LCD2,
+};
+
+static void pcm049_dvi_mux_init(void)
+{
+ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+ omap_mux_init_signal(hdmi_hpd,
+ OMAP_PIN_INPUT_PULLUP);
+
[PATCH 1/2] omap4: board-omap4panda: prepare for join
Prepare board-omap4panda for joing other similar boards.
MUX: board_mux and omap4_panda_mux
omap4_common_preinit: for muxing
omap4_common_init: all common devices
omap4_panda_config: gpios, omap_board_data, i2c_board_info ...
runtime overwriteable
some inititialisation check if omap4_panda_config entry is valid
i2c_2_board_speed == 0 - i2c_2 not used
hup_power_gpio == EINVAL - gpio not used
Signed-off-by: Jan Weitzel j.weit...@phytec.de
---
arch/arm/mach-omap2/board-omap4panda.c | 498 ++-
1 files changed, 289 insertions(+), 209 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c
b/arch/arm/mach-omap2/board-omap4panda.c
index 9aaa960..b9bea86 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -47,23 +47,11 @@
#include mux.h
#include common-board-devices.h
-#define GPIO_HUB_POWER 1
-#define GPIO_HUB_NRESET62
#define GPIO_WIFI_PMENA43
#define GPIO_WIFI_IRQ 53
#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
-/* wl127x BT, FM, GPS connectivity chip */
-static int wl1271_gpios[] = {46, -1, -1};
-static struct platform_device wl1271_device = {
- .name = kim,
- .id = -1,
- .dev= {
- .platform_data = wl1271_gpios,
- },
-};
-
static struct gpio_led gpio_leds[] = {
{
.name = pandaboard::status1,
@@ -77,21 +65,219 @@ static struct gpio_led gpio_leds[] = {
},
};
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
+/*
+ * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
+ * is connected as I2C slave device, and can be accessed at address 0x50
+ */
+static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
+ {
+ I2C_BOARD_INFO(eeprom, 0x50),
+ },
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ /* dispc2_data23 */
+ OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data22 */
+ OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data21 */
+ OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data20 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data19 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data18 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data15 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data14 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data13 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data12 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data11 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data10 */
+ OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data9 */
+ OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data16 */
+ OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data17 */
+ OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_hsync */
+ OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_pclk */
+ OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_vsync */
+ OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_de */
+ OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data8 */
+ OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data7 */
+ OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data6 */
+ OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data5 */
+ OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data4 */
+ OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data3 */
+ OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data2 */
+ OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data1 */
+ OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data0 */
+ OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+ OMAP_MUX_STATIC(uart2_cts.uart2_cts,
+OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+
Re: [PATCHv5 01/11] OMAP: prcm: switch to a chained IRQ handler mechanism
On Tue, Jul 05, 2011 at 01:27:47PM +0300, Tero Kristo wrote:
Introduce a chained interrupt handler mechanism for the PRCM
interrupt, so that individual PRCM event can cleanly be handled by
handlers in separate drivers. We do this by introducing PRCM event
names, which are then matched to the particular PRCM interrupt bit
depending on the specific OMAP SoC being used.
arch/arm/mach-omap2/prcm.c implements the chained interrupt mechanism
itself, with individual PRCM events for OMAP3 and OMAP4 being
described in arch/arm/mach-omap2/prcm3xxx.c and
arch/arm/mach-omap2/prcm4xxx.c respectively. At initialization time,
the set of PRCM events is filtered against the SoC on which we are
running, keeping only the ones that are actually useful. All the logic
is written to be generic with regard to OMAP3/OMAP4, even though OMAP3
has single PRCM event registers and OMAP4 has two PRCM event
registers.
...
+
+ prcm_wkup_irq = omap_prcm_event_to_irq(wkup);
+ prcm_io_irq = omap_prcm_event_to_irq(io);
Should check error return for both.
+
+ ret = request_irq(prcm_wkup_irq, _prcm_int_handle_wakeup,
+ IRQF_NO_SUSPEND | IRQF_DISABLED, prcm_wkup, NULL);
...
+ for (i = 0; i = max_irq / 32; i++) {
+ gc = irq_alloc_generic_chip(PRCM, 1,
+ irq_setup-base_irq + i * 32, NULL, handle_level_irq);
+
Should check NULL return for out of memory.
+ ct = gc-chip_types;
...
+ /* Copy setup from __initdata section */
+ irq_setup = kmalloc(sizeof(struct omap_prcm_irq_setup), GFP_KERNEL);
Check NULL return.
+ memcpy(irq_setup, setup, sizeof(struct omap_prcm_irq_setup));
+
+ irqs = kmalloc(sizeof(struct omap_prcm_irq) *
+ setup-num_irqs, GFP_KERNEL);
Check NULL return.
+ memcpy(irqs, setup-irqs, sizeof(struct omap_prcm_irq) *
+ setup-num_irqs);
Todd
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[PATCH 0/3] OMAP3 ISP patches for v3.1
Hi everybody, Here are the OMAP3 ISP patches in my queue for v3.1. I'll send a pull request in a couple of days if there's no objection. Kalle Jokiniemi (2): OMAP3: ISP: Add regulator control for omap34xx OMAP3: RX-51: define vdds_csib regulator supply Laurent Pinchart (1): omap3isp: Support configurable HS/VS polarities arch/arm/mach-omap2/board-rx51-peripherals.c |5 drivers/media/video/omap3isp/isp.h |6 + drivers/media/video/omap3isp/ispccdc.c |4 +- drivers/media/video/omap3isp/ispccp2.c | 27 - drivers/media/video/omap3isp/ispccp2.h |1 + 5 files changed, 39 insertions(+), 4 deletions(-) -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] OMAP3: RX-51: define vdds_csib regulator supply
From: Kalle Jokiniemi kalle.jokini...@nokia.com
The RX-51 uses the CSIb IO complex for camera operation. The
board file is missing definition for the regulator supplying
the CSIb complex, so this is added for better power
management.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Acked-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
Cc: t...@atomide.com
---
arch/arm/mach-omap2/board-rx51-peripherals.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
Tony, can I push this patch through the V4L/DVB tree, or would you like to
pick it yourself ?
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c
b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 88bd6f7..17e5685 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -361,6 +361,9 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
static struct regulator_consumer_supply rx51_vmmc1_supply =
REGULATOR_SUPPLY(vmmc, omap_hsmmc.0);
+static struct regulator_consumer_supply rx51_vaux2_supply =
+ REGULATOR_SUPPLY(vdds_csib, omap3isp);
+
static struct regulator_consumer_supply rx51_vaux3_supply =
REGULATOR_SUPPLY(vmmc, omap_hsmmc.1);
@@ -424,6 +427,8 @@ static struct regulator_init_data rx51_vaux2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = rx51_vaux2_supply,
};
/* VAUX3 - adds more power to VIO_18 rail */
--
1.7.3.4
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[PATCH 3/3] omap3isp: Support configurable HS/VS polarities
Add two fields to the ISP parallel platform data to set the HS and VS
signals polarities.
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
drivers/media/video/omap3isp/isp.h |6 ++
drivers/media/video/omap3isp/ispccdc.c |4 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/media/video/omap3isp/isp.h
b/drivers/media/video/omap3isp/isp.h
index 2620c40..529e582 100644
--- a/drivers/media/video/omap3isp/isp.h
+++ b/drivers/media/video/omap3isp/isp.h
@@ -139,6 +139,10 @@ struct isp_reg {
* 3 - CAMEXT[13:6] - CAM[7:0]
* @clk_pol: Pixel clock polarity
* 0 - Non Inverted, 1 - Inverted
+ * @hs_pol: Horizontal synchronization polarity
+ * 0 - Active high, 1 - Active low
+ * @vs_pol: Vertical synchronization polarity
+ * 0 - Active high, 1 - Active low
* @bridge: CCDC Bridge input control
* ISPCTRL_PAR_BRIDGE_DISABLE - Disable
* ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian
@@ -147,6 +151,8 @@ struct isp_reg {
struct isp_parallel_platform_data {
unsigned int data_lane_shift:2;
unsigned int clk_pol:1;
+ unsigned int hs_pol:1;
+ unsigned int vs_pol:1;
unsigned int bridge:4;
};
diff --git a/drivers/media/video/omap3isp/ispccdc.c
b/drivers/media/video/omap3isp/ispccdc.c
index 6766247..b8cb7dd 100644
--- a/drivers/media/video/omap3isp/ispccdc.c
+++ b/drivers/media/video/omap3isp/ispccdc.c
@@ -1148,6 +1148,8 @@ static void ccdc_configure(struct isp_ccdc_device *ccdc)
omap3isp_configure_bridge(isp, ccdc-input, pdata, shift);
ccdc-syncif.datsz = depth_out;
+ ccdc-syncif.hdpol = pdata ? pdata-hs_pol : 0;
+ ccdc-syncif.vdpol = pdata ? pdata-vs_pol : 0;
ccdc_config_sync_if(ccdc, ccdc-syncif);
/* CCDC_PAD_SINK */
@@ -2256,8 +2258,6 @@ int omap3isp_ccdc_init(struct isp_device *isp)
ccdc-syncif.fldout = 0;
ccdc-syncif.fldpol = 0;
ccdc-syncif.fldstat = 0;
- ccdc-syncif.hdpol = 0;
- ccdc-syncif.vdpol = 0;
ccdc-clamp.oblen = 0;
ccdc-clamp.dcsubval = 0;
--
1.7.3.4
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[PATCH 1/3] OMAP3: ISP: Add regulator control for omap34xx
From: Kalle Jokiniemi kalle.jokini...@nokia.com
The current omap3isp driver is missing regulator handling
for CSIb complex in omap34xx based devices. This patch
adds a mechanism for this to the omap3isp driver.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Acked-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
drivers/media/video/omap3isp/ispccp2.c | 27 +--
drivers/media/video/omap3isp/ispccp2.h |1 +
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/media/video/omap3isp/ispccp2.c
b/drivers/media/video/omap3isp/ispccp2.c
index 0e16cab..ec9e395f 100644
--- a/drivers/media/video/omap3isp/ispccp2.c
+++ b/drivers/media/video/omap3isp/ispccp2.c
@@ -30,6 +30,7 @@
#include linux/module.h
#include linux/mutex.h
#include linux/uaccess.h
+#include linux/regulator/consumer.h
#include isp.h
#include ispreg.h
@@ -163,6 +164,9 @@ static void ccp2_if_enable(struct isp_ccp2_device *ccp2, u8
enable)
struct isp_pipeline *pipe = to_isp_pipeline(ccp2-subdev.entity);
int i;
+ if (enable ccp2-vdds_csib)
+ regulator_enable(ccp2-vdds_csib);
+
/* Enable/Disable all the LCx channels */
for (i = 0; i CCP2_LCx_CHANS_NUM; i++)
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
@@ -186,6 +190,9 @@ static void ccp2_if_enable(struct isp_ccp2_device *ccp2, u8
enable)
ISPCCP2_LC01_IRQENABLE,
ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ);
}
+
+ if (!enable ccp2-vdds_csib)
+ regulator_disable(ccp2-vdds_csib);
}
/*
@@ -1137,6 +1144,9 @@ error:
*/
void omap3isp_ccp2_cleanup(struct isp_device *isp)
{
+ struct isp_ccp2_device *ccp2 = isp-isp_ccp2;
+
+ regulator_put(ccp2-vdds_csib);
}
/*
@@ -1151,14 +1161,27 @@ int omap3isp_ccp2_init(struct isp_device *isp)
init_waitqueue_head(ccp2-wait);
- /* On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
+ /*
+* On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
+* complex, which is powered by vdds_csib power rail. Hence the
+* request for the regulator.
+*
+* On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
* the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
* configured.
*
* TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
*/
- if (isp-revision == ISP_REVISION_15_0)
+ if (isp-revision == ISP_REVISION_2_0) {
+ ccp2-vdds_csib = regulator_get(isp-dev, vdds_csib);
+ if (IS_ERR(ccp2-vdds_csib)) {
+ dev_dbg(isp-dev,
+ Could not get regulator vdds_csib\n);
+ ccp2-vdds_csib = NULL;
+ }
+ } else if (isp-revision == ISP_REVISION_15_0) {
ccp2-phy = isp-isp_csiphy1;
+ }
ret = ccp2_init_entities(ccp2);
if (ret 0)
diff --git a/drivers/media/video/omap3isp/ispccp2.h
b/drivers/media/video/omap3isp/ispccp2.h
index 5505a86..6674e9d 100644
--- a/drivers/media/video/omap3isp/ispccp2.h
+++ b/drivers/media/video/omap3isp/ispccp2.h
@@ -81,6 +81,7 @@ struct isp_ccp2_device {
struct isp_interface_mem_config mem_cfg;
struct isp_video video_in;
struct isp_csiphy *phy;
+ struct regulator *vdds_csib;
unsigned int error;
enum isp_pipeline_stream_state state;
wait_queue_head_t wait;
--
1.7.3.4
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[PATCH] GPMC: Limited addressing support
This patch provides a way to enable the GPMC limited addressing mode which is needed to access nonmultiplexed devices. Signed-off-by: Raphael Assenat r...@8d.com diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 130034b..521944a 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -540,6 +540,15 @@ int gpmc_cs_configure(int cs, int cmd, int wval) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); break; + case GPMC_EN_LIMITEDADDRESS: + regval = gpmc_read_reg(GPMC_CONFIG); + if (wval) + regval |= GPMC_CONFIG_LIMITEDADDRESS; + else + regval = ~GPMC_CONFIG_LIMITEDADDRESS; + gpmc_write_reg(GPMC_CONFIG, regval); + break; + default: printk(KERN_ERR gpmc_configure_cs: Not supported\n); err = -EINVAL; diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 1527929..7fdbbb8 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -42,6 +42,7 @@ #define GPMC_NAND_DATA 0x000c #define GPMC_ENABLE_IRQ0x000d +#define GPMC_EN_LIMITEDADDRESS 0x000e /* ECC commands */ #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ @@ -75,6 +76,7 @@ #define GPMC_DEVICETYPE_NOR0 #define GPMC_DEVICETYPE_NAND 2 +#define GPMC_CONFIG_LIMITEDADDRESS 0x0002 #define GPMC_CONFIG_WRITEPROTECT 0x0010 #define GPMC_STATUS_BUFF_EMPTY 0x0001 #define WR_RD_PIN_MONITORING 0x0060 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4] OMAP4: hwmod data: I2C: add flag for context restore
Shubhrajyoti D shubhrajy...@ti.com writes:
Restore of context is not done for OMAP4. This patch
adds the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE in the OMAP4
hwmod data which activates the restore for OMAP4.
Currently the OMAP4 does not hit device off still the
driver may have support for it.
Signed-off-by: Shubhrajyoti D shubhrajy...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Please repost one more time with the linux-arm-kernel list Cc'd (and you
can add my reviewed-by tag.)
Paul can then probably queue this for v3.1-rc
Kevin
---
Applies on top of patches from Andy Green
http://www.spinics.net/lists/linux-i2c/msg05632.html
Tested on OMAP4430
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0fe9556..5e2c748 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2130,7 +2130,8 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
};
static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
};
/* i2c1 */
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[PATCH] usb: musb: Enable DMA mode1 RX for USB-Mass-Storage
From: Vikram Pandita vikram.pand...@ti.com
This patch enables the DMA mode1 RX support.
This feature is enabled based on the short_not_ok flag passed from
gadget drivers.
This will result in a thruput performance gain of around
40% for USB mass-storage/mtp use cases.
Based on Original work by
Anand Gadiyar gadi...@ti.com on 2.6.35 kernel
Tested on OMAP4460 Blaze board.
Signed-off-by: Moiz Sonasath m-sonas...@ti.com
Signed-off-by: Vikram Pandita vikram.pand...@ti.com
---
drivers/usb/musb/musb_gadget.c | 42 ---
1 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 9412410..e643ec2 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -624,6 +624,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
/*
* Context: controller locked, IRQs blocked, endpoint selected
*/
+
static void rxstate(struct musb *musb, struct musb_request *req)
{
const u8epnum = req-epnum;
@@ -634,6 +635,7 @@ static void rxstate(struct musb *musb, struct musb_request
*req)
u16 len;
u16 csr = musb_readw(epio, MUSB_RXCSR);
struct musb_hw_ep *hw_ep = musb-endpoints[epnum];
+ u8 use_mode_1;
if (hw_ep-is_shared_fifo)
musb_ep = hw_ep-ep_in;
@@ -683,6 +685,18 @@ static void rxstate(struct musb *musb, struct musb_request
*req)
if (csr MUSB_RXCSR_RXPKTRDY) {
len = musb_readw(epio, MUSB_RXCOUNT);
+
+ /*
+* Enable Mode 1 for RX transfers only for mass-storage
+* use-case, based on short_not_ok flag which is set only
+* from file_storage and f_mass_storage drivers
+*/
+
+ if (request-short_not_ok len == musb_ep-packet_sz)
+ use_mode_1 = 1;
+ else
+ use_mode_1 = 0;
+
if (request-actual request-length) {
#ifdef CONFIG_USB_INVENTRA_DMA
if (is_buffer_mapped(req)) {
@@ -714,10 +728,13 @@ static void rxstate(struct musb *musb, struct
musb_request *req)
* then becomes usable as a runtime use mode 1 hint...
*/
- csr |= MUSB_RXCSR_DMAENAB;
-#ifdef USE_MODE1
+ /* Experimental: Mode1 works with mass storage use cases
+*/
+ if (use_mode_1) {
csr |= MUSB_RXCSR_AUTOCLEAR;
- /* csr |= MUSB_RXCSR_DMAMODE; */
+ musb_writew(epio, MUSB_RXCSR, csr);
+ csr |= MUSB_RXCSR_DMAENAB;
+ musb_writew(epio, MUSB_RXCSR, csr);
/* this special sequence (enabling and then
* disabling MUSB_RXCSR_DMAMODE) is required
@@ -725,26 +742,27 @@ static void rxstate(struct musb *musb, struct
musb_request *req)
*/
musb_writew(epio, MUSB_RXCSR,
csr | MUSB_RXCSR_DMAMODE);
-#else
+ musb_writew(epio, MUSB_RXCSR, csr);
+
+ } else {
if (!musb_ep-hb_mult
musb_ep-hw_ep-rx_double_buffered)
csr |= MUSB_RXCSR_AUTOCLEAR;
-#endif
+ csr |= MUSB_RXCSR_DMAENAB;
musb_writew(epio, MUSB_RXCSR, csr);
+ }
if (request-actual request-length) {
int transfer_size = 0;
-#ifdef USE_MODE1
+ if (use_mode_1) {
transfer_size = min(request-length -
request-actual,
channel-max_len);
-#else
+ musb_ep-dma-desired_mode = 1;
+ } else {
transfer_size = min(request-length -
request-actual,
(unsigned)len);
-#endif
- if (transfer_size = musb_ep-packet_sz)
- musb_ep-dma-desired_mode = 0;
- else
- musb_ep-dma-desired_mode = 1;
+ musb_ep-dma-desired_mode = 0;
+ }
use_dma = c-channel_program(
channel,
--
1.7.4.1
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