Re: [PATCH 06/18] ARM: dts: omap3-overo: Enable MMC2

[Florian Vaussard]

Hello Javier,

On 01/09/2014 09:43 PM, Javier Martinez Canillas wrote:
> [adding Enric Balletbo to cc]
> 
> Hello Florian,
> 
> On Thu, Jan 9, 2014 at 1:48 PM, Florian Vaussard
>  wrote:
>> MMC2 is used by the on-board WiFi module populated on some boards
>> (based on Marvell Libertas 8688 SDIO).
>>
>> Note: currently WiFi only works on cold boot, as the module is not
>> properly reset (missing binding for the GPIO reset).
>>
> 
> Have you looked at commit 0e9fd777 ("ARM: dts: omap3-igep: Add support
> for LBEE1USJYC WiFi connected to SDIO") ?
> 
> If I remember correctly the LBEE1USJYC Wifi/BT combo module is
> basically a Marvell Libertas 8688 Wlan and Enric got soft reset
> working too by adding a GPIO property to the regulator for the reset
> GPIO.
> 

Many thanks for the pointer. In the initial version, I had a regulator
like you. But now I doubt if it was correctly added to the MMC node,
which could be why it was not working... I will try again.

Thanks for your help!

Florian
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Re: 3.13-rc2 phy-twl4030-usb.c - Timeout setting T2 HSUSB PHY DPLL

[Belisko Marek]

Hi,

On Fri, Jan 10, 2014 at 6:25 AM, Kishon Vijay Abraham I  wrote:
> Hi,
>
> On Thursday 09 January 2014 10:54 AM, Roger Quadros wrote:
>> Hi Marek,
>>
>> I have no idea what is happening there. Have you tried using device tree 
>> boot?
>> Board file boot support would be dropped eventually.
>>
>> Did you try if I2C read write to the twl4030 device works and all necessary 
>> clocks/supplies are
>> present?
>>
>> Kishon, do you know what is causing the USB DPLL failure there?
Issue was fixed. There was in 3.13-rc7 issue with unable to find phy
(phy was twl4030_usb). After that
issue is gone.
>
> Not sure what's causing those failures :-s
>
> -Kishon
>
>>
>> cheers,
>> -roger
>>
>> On 01/09/2014 02:31 AM, Belisko Marek wrote:
>>> Any pointers? Still present in 3.13-rc7.
>>>
>>> On Wed, Dec 4, 2013 at 1:22 PM, Roger Quadros  wrote:
 +Kishon

 On 12/03/2013 11:33 PM, Belisko Marek wrote:
> Hi,
>
> current 3.13-rcX break usb support on gta04 board (similar to
> beagleboard) when booting via board file.
>
> In console we can see messages:
>  [ 5227.287841] twl4030_usb twl4030_usb: Timeout setting T2 HSUSB PHY 
> DPLL clock
> [ 5232.936096] omap_musb_mailbox: musb core is not yet ready
> [ 5233.958160] twl4030_usb twl4030_usb: Timeout setting T2 HSUSB PHY DPLL 
> clock
> [ 5235.058227] twl4030_usb twl4030_usb: Timeout setting T2 HSUSB PHY DPLL 
> clock
>
> Any pointer what could cause that? (in 3.12 usb works fine)
>
> BR,
>
> marek
>

>>>
>>> BR,
>>>
>>> marek
>>>
>>
>

BR,

marek

-- 
as simple and primitive as possible
-
Marek Belisko - OPEN-NANDRA
Freelance Developer

Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052 184
skype: marekwhite
twitter: #opennandra
web: http://open-nandra.com
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Re: 3.13-rc2 phy-twl4030-usb.c - Timeout setting T2 HSUSB PHY DPLL

[Kishon Vijay Abraham I]

Hi,

On Thursday 09 January 2014 10:54 AM, Roger Quadros wrote:
> Hi Marek,
> 
> I have no idea what is happening there. Have you tried using device tree boot?
> Board file boot support would be dropped eventually.
> 
> Did you try if I2C read write to the twl4030 device works and all necessary 
> clocks/supplies are
> present?
> 
> Kishon, do you know what is causing the USB DPLL failure there?

Not sure what's causing those failures :-s

-Kishon

> 
> cheers,
> -roger
> 
> On 01/09/2014 02:31 AM, Belisko Marek wrote:
>> Any pointers? Still present in 3.13-rc7.
>>
>> On Wed, Dec 4, 2013 at 1:22 PM, Roger Quadros  wrote:
>>> +Kishon
>>>
>>> On 12/03/2013 11:33 PM, Belisko Marek wrote:
 Hi,

 current 3.13-rcX break usb support on gta04 board (similar to
 beagleboard) when booting via board file.

 In console we can see messages:
  [ 5227.287841] twl4030_usb twl4030_usb: Timeout setting T2 HSUSB PHY DPLL 
 clock
 [ 5232.936096] omap_musb_mailbox: musb core is not yet ready
 [ 5233.958160] twl4030_usb twl4030_usb: Timeout setting T2 HSUSB PHY DPLL 
 clock
 [ 5235.058227] twl4030_usb twl4030_usb: Timeout setting T2 HSUSB PHY DPLL 
 clock

 Any pointer what could cause that? (in 3.12 usb works fine)

 BR,

 marek

>>>
>>
>> BR,
>>
>> marek
>>
> 

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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

Hi,

On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
> > So, bad luck number release for this, as v12 wasn't sufficient still.
> > 
> > Changes compared to previous version:
> > - Dropped any changes to generic clock drivers, as it seems impossible
> >   to agree anything in short term, this means the patch set shrank in
> >   size from 49 patches to 40 (first 9 patches were dropped).
> > - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> >   to drivers/clk/ti, and made the modifications needed to the TI version
> >   of the clock drivers only (based on discussions with Mike, this is fine)
> > - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
> >   with any generic implementation we might have at some point, migrating
> >   this to the generic version should be easy enough also.
> > - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> >   versions and resulted into an orphan clock node
> > - Fixed compile problem for omap5 only build reported by Felipe
> > - Fixed a couple of sparse warnings
> > - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> >   instead of __raw_readl / __raw_writel
> > 
> > Testing done:
> > - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> > - omap4-panda-es: boot / suspend-resume (RET)
> > - omap5-uevm: boot
> > - am335x-bone: boot
> > - dra7-evm: boot
> > 
> > Maintainer friendly branches also available:
> > 
> > tree: https://github.com/t-kristo/linux-pm.git
> > 
> > clk driver only (Mike): clk-next-dt-clks-v13
> > DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> > full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> > 
> > -Tero
> > 
> 
> Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
> =
> Conflict resolution during rebase to maintainer's -14 branches:
> 
> 1. (trivial) Against mike's clk-next dbdf6ff Merge branch
> 'clk-next-unregister' into clk-next
> 
> Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
> mechanism
> conflict drivers/clk/Makefile (trivial fix)
> 
> 2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
> fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix
> 
> ARM: OMAP2+: clock: use driver API instead of direct memory read/write
> 
> conflicts with be changes on Tony's be branch.
> commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
> ARM: OMAP2+: raw read and write endian fix
> 
> Conflict:
> arch/arm/mach-omap2/clkt_clksel.c
> arch/arm/mach-omap2/clkt_dpll.c
> arch/arm/mach-omap2/clkt_iclk.c
> arch/arm/mach-omap2/clock.c
> arch/arm/mach-omap2/clock36xx.c
> arch/arm/mach-omap2/dpll3xxx.c
> arch/arm/mach-omap2/dpll44xx.c
> 
> Both change raw_readls -> should now be just clk api instead which
> already does readl_relaxed etc.. If Tony feels like, then we should
> probably post a branch based on 'be' branch for easy merge.
> 
> 3. I could not detect any merge conflict against Benoit's queued up
> series (but maybe he has'nt pushed everything to remote tree)..
> 
> 
> Patch verification report:
> ==
> Report: http://pastebin.mozilla.org/3976492
> 
> 
> * sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
> divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
> +drivers/clk/ti/divider.c: warning: context imbalance in
> 'ti_clk_divider_set_rate' - different lock contexts for basic block
> +drivers/clk/ti/mux.c: warning: context imbalance in
> 'ti_clk_mux_set_parent' - different lock contexts for basic block
> 
> * checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
> file, [PATCH 18/40] CLK: TI: add omap3 clock init file
> WARNING: static const char * array should probably be static const
> char * const
> 
> 
> Boot reports:
> =
> - previous orphan clocks seem solved.
> - All available platforms seem to boot fine and no regression could be
> seen on initial view
> 
> OMAP2430:
>   1. SDP2430
> before: http://pastebin.mozilla.org/3976359
> after: http://pastebin.mozilla.org/3976467
> 
> AM335x:
>   2. am335x-evm
> before: http://pastebin.mozilla.org/3976284
> after: http://pastebin.mozilla.org/3976374
>   3. am335x-sk
> before: http://pastebin.mozilla.org/3976295
> after: http://pastebin.mozilla.org/3976375
>   4. BeagleBone Black:
> before: http://pastebin.mozilla.org/3976321
> after: http://pastebin.mozilla.org/3976441
> 
> AM3517:
>   5. am3517-evm
> before: http://pastebin.mozilla.org/3976297
> after: http://pastebin.mozilla.org/3976397
>   6. craneboard
> before: http://pastebin.mozilla.org/3976322
> after: http://pastebin.mozilla.org/3976452
> 
> OMAP3430:
>   7. ldp
> before: http://pastebin.mozilla.org/3976356
> after: http://pastebin.mozilla.org/3976455
>   8. sdp3430
> before: http://pastebin.mozilla.org/3976360
> after: http://pastebin.mozilla.org/3976468
> 
> OMAP3630/DM3730:
>   9. am37x-evm
> before: ht

Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Mike Turquette]

Quoting Tero Kristo (2014-01-09 06:00:11)
> Hi,
> 
> So, bad luck number release for this, as v12 wasn't sufficient still.
> 
> Changes compared to previous version:
> - Dropped any changes to generic clock drivers, as it seems impossible
>   to agree anything in short term, this means the patch set shrank in
>   size from 49 patches to 40 (first 9 patches were dropped).
> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>   to drivers/clk/ti, and made the modifications needed to the TI version
>   of the clock drivers only (based on discussions with Mike, this is fine)
> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>   with any generic implementation we might have at some point, migrating
>   this to the generic version should be easy enough also.
> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>   versions and resulted into an orphan clock node
> - Fixed compile problem for omap5 only build reported by Felipe
> - Fixed a couple of sparse warnings
> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>   instead of __raw_readl / __raw_writel

Hi Tero,

This approach takes care of all of my concerns with this series. Thanks
for your long suffering patience on it.

It seems some build errors are cropping up, so once those are fixed then
I'll be happy to merge clk-next-dt-clks-v13 into clk-next for 3.14.

Regards,
Mike

> 
> Testing done:
> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> - omap4-panda-es: boot / suspend-resume (RET)
> - omap5-uevm: boot
> - am335x-bone: boot
> - dra7-evm: boot
> 
> Maintainer friendly branches also available:
> 
> tree: https://github.com/t-kristo/linux-pm.git
> 
> clk driver only (Mike): clk-next-dt-clks-v13
> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> 
> -Tero
> 
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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Nishanth Menon]

On 01/09/2014 08:00 AM, Tero Kristo wrote:
> Hi,
> 
> So, bad luck number release for this, as v12 wasn't sufficient still.
> 
> Changes compared to previous version:
> - Dropped any changes to generic clock drivers, as it seems impossible
>   to agree anything in short term, this means the patch set shrank in
>   size from 49 patches to 40 (first 9 patches were dropped).
> - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
>   to drivers/clk/ti, and made the modifications needed to the TI version
>   of the clock drivers only (based on discussions with Mike, this is fine)
> - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
>   with any generic implementation we might have at some point, migrating
>   this to the generic version should be easy enough also.
> - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
>   versions and resulted into an orphan clock node
> - Fixed compile problem for omap5 only build reported by Felipe
> - Fixed a couple of sparse warnings
> - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
>   instead of __raw_readl / __raw_writel
> 
> Testing done:
> - omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
> - omap4-panda-es: boot / suspend-resume (RET)
> - omap5-uevm: boot
> - am335x-bone: boot
> - dra7-evm: boot
> 
> Maintainer friendly branches also available:
> 
> tree: https://github.com/t-kristo/linux-pm.git
> 
> clk driver only (Mike): clk-next-dt-clks-v13
> DTS data only (Benoit): dts_for_3.14-dt-clks-v13
> full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13
> 
> -Tero
> 

Maintainer branches conflicts (using 3.13-rc7-dt-clks-v13):
=
Conflict resolution during rebase to maintainer's -14 branches:

1. (trivial) Against mike's clk-next dbdf6ff Merge branch
'clk-next-unregister' into clk-next

Could not apply 2edf7ad... CLK: TI: add DT alias clock registration
mechanism
conflict drivers/clk/Makefile (trivial fix)

2. (manual, but changes are easy) Against Tony's omap-for-v3.14/be
fc6ca98 ARM: OMAP: debug-leds: raw read and write endian fix

ARM: OMAP2+: clock: use driver API instead of direct memory read/write

conflicts with be changes on Tony's be branch.
commit 80f304dd2360cf5d50953c4eb4e902536f6a1263
ARM: OMAP2+: raw read and write endian fix

Conflict:
arch/arm/mach-omap2/clkt_clksel.c
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/clkt_iclk.c
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock36xx.c
arch/arm/mach-omap2/dpll3xxx.c
arch/arm/mach-omap2/dpll44xx.c

Both change raw_readls -> should now be just clk api instead which
already does readl_relaxed etc.. If Tony feels like, then we should
probably post a branch based on 'be' branch for easy merge.

3. I could not detect any merge conflict against Benoit's queued up
series (but maybe he has'nt pushed everything to remote tree)..


Patch verification report:
==
Report: http://pastebin.mozilla.org/3976492


* sparse warning added in [PATCH 06/40] CLK: ti: add support for ti
divider-clock, [PATCH 10/40] clk: ti: add support for basic mux clock
+drivers/clk/ti/divider.c: warning: context imbalance in
'ti_clk_divider_set_rate' - different lock contexts for basic block
+drivers/clk/ti/mux.c: warning: context imbalance in
'ti_clk_mux_set_parent' - different lock contexts for basic block

* checkpatch warning [PATCH 16/40] CLK: TI: add am33xx clock init
file, [PATCH 18/40] CLK: TI: add omap3 clock init file
WARNING: static const char * array should probably be static const
char * const


Boot reports:
=
- previous orphan clocks seem solved.
- All available platforms seem to boot fine and no regression could be
seen on initial view

OMAP2430:
  1. SDP2430
before: http://pastebin.mozilla.org/3976359
after: http://pastebin.mozilla.org/3976467

AM335x:
  2. am335x-evm
before: http://pastebin.mozilla.org/3976284
after: http://pastebin.mozilla.org/3976374
  3. am335x-sk
before: http://pastebin.mozilla.org/3976295
after: http://pastebin.mozilla.org/3976375
  4. BeagleBone Black:
before: http://pastebin.mozilla.org/3976321
after: http://pastebin.mozilla.org/3976441

AM3517:
  5. am3517-evm
before: http://pastebin.mozilla.org/3976297
after: http://pastebin.mozilla.org/3976397
  6. craneboard
before: http://pastebin.mozilla.org/3976322
after: http://pastebin.mozilla.org/3976452

OMAP3430:
  7. ldp
before: http://pastebin.mozilla.org/3976356
after: http://pastebin.mozilla.org/3976455
  8. sdp3430
before: http://pastebin.mozilla.org/3976360
after: http://pastebin.mozilla.org/3976468

OMAP3630/DM3730:
  9. am37x-evm
before: http://pastebin.mozilla.org/3976300
after: http://pastebin.mozilla.org/3976398
  10. beagle-XM
before: http://pastebin.mozilla.org/3976319
after: http://pastebin.mozilla.org/3976440

OMAP4430:
  11. SDP4430
before: http://pastebin.mozilla.org/3976361
after: http://

Re: [PATCH 06/18] ARM: dts: omap3-overo: Enable MMC2

[Javier Martinez Canillas]

[adding Enric Balletbo to cc]

Hello Florian,

On Thu, Jan 9, 2014 at 1:48 PM, Florian Vaussard
 wrote:
> MMC2 is used by the on-board WiFi module populated on some boards
> (based on Marvell Libertas 8688 SDIO).
>
> Note: currently WiFi only works on cold boot, as the module is not
> properly reset (missing binding for the GPIO reset).
>

Have you looked at commit 0e9fd777 ("ARM: dts: omap3-igep: Add support
for LBEE1USJYC WiFi connected to SDIO") ?

If I remember correctly the LBEE1USJYC Wifi/BT combo module is
basically a Marvell Libertas 8688 Wlan and Enric got soft reset
working too by adding a GPIO property to the regulator for the reset
GPIO.

Hope it helps,
Javier
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Re: [PATCH 00/18] ARM: dts: Better support for Gumstix Overo

[Florian Vaussard]

Hi Ash,

On 01/09/2014 07:13 PM, Ash Charles wrote:
> Hi Florian,
> On Thu, Jan 9, 2014 at 9:06 AM, Benoit Cousson  wrote:
>>> The patches 13 to 17 are based on the hardware schematics and
>>> compile-tested, as I
>>> do not have the necessary hardware (anyone willing to send me some boards
>>> ? :-)
> Firstly: thanks!

You are welcome.

> Secondly: Could you email (a...@gumstix.com) me a wish list of
> boards/hardware?  I'll see what I can wrangle.
> 

Ok, I will see what I would need to advance further the DT support.

Best,

Florian
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Re: [PATCH 00/18] ARM: dts: Better support for Gumstix Overo

[Florian Vaussard]

Hi Benoit,

On 01/09/2014 06:06 PM, Benoit Cousson wrote:
> Hi Florian,
> 
> On 09/01/2014 17:47, Florian Vaussard wrote:
>> Hello,
>>
>> This series adds a number of improvements to Gumstix Overo.
> 
> Thanks for that nice series.
> 
>> Patch 1+2: fix an issue with the vendor prefix (reported long ago by
>> Javier Martinez Canillas)
>> Patch 3+4: add some missing pinctrl entries
>> Patch 5: completely turn off the PMIC on power off
>> Patch 6: enable the on-board Wifi
>> Patch 7: add the high-speed USB PHY
>> Patch 8: add specific timings for LAN9221 into a generic file
>> -> This might interest other people using the same chip, result in
>> doubled bandwith
>>
>> Patch 9: simplify omap3-tobi by using patch 8
>> Patch 10: add support for AT24C01 EEPROM used on expansion boards
>> Patch 11: factorize parts common to all expansion boards
>> Patch 12: rename omap3-tobi to omap3-overo-tobi
>> -> I do not know to which extent this might qualify as an API breakage,
>> but the new name is far better IMHO
>>

Do you have any thoughts on this? I guess that the Tobi DT is not very
widely used, apart for testing purposes, but I do not want to be flamed
due to an API breakage :D But I deem the new name to be worth the risk.

>> Patch 13 to 17: add new extension boards (Palo43, Gallop43, Alto35,
>> Chestnut43, Summit)
>> Patch 18: add the HDMI output
>> -> this patch depends on Tomi Valkeinen's DT binding for OMAPDSS,
>> which is
>> not yet merged, so this patch will have to wait
>>
>>
>> The patches 13 to 17 are based on the hardware schematics and
>> compile-tested, as I
>> do not have the necessary hardware (anyone willing to send me some
>> boards ? :-)
>> We are mainly missing the support for the various LCDs, the
>> accelerometer + probably
>> other small things.
>>
>> This series is based on Tony's omap-for-v3.14/dt branch + work from
>> Tomi [1] for the patch 18.
>>
>> Benoit: I guess that I am too late for the 3.14... ?
> 
> Yeah, I think so, even my 3.14 branch is too late for 3.14 :-)
> 

Damn!

Ok, will go for 3.15. Anyway, I have other DT patches under the hood
(OMAP4 DuoVero + my own board), so everything can go into the same release.

Best,

Florian
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Re: [PATCH v2 1/2] ARM: dts: Add omap specific pinctrl defines to use padconf addresses

[Florian Vaussard]

Hi Tony,

On 01/08/2014 12:20 AM, Tony Lindgren wrote:
> * Laurent Pinchart  [140107 15:10]:
>> Hi Tony,
>>
>> On Tuesday 07 January 2014 14:30:21 Tony Lindgren wrote:
>>> * Laurent Pinchart  [131220 07:52]:
 From: Tony Lindgren 
 +/*
 + * Macros to allow using the absolute physical address instead of the
 + * padconf registers instead of the offset from padconf base.
 + */
 +#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0x) - (offset))
 +
 +#define OMAP2420_CORE_IOPAD(pa, val)  OMAP_IOPAD_OFFSET((pa), 0x0030)
 (val)
 +#define OMAP2430_CORE_IOPAD(pa, val)  OMAP_IOPAD_OFFSET((pa), 0x2030)
 (val)
 +#define OMAP3_CORE1_IOPAD(pa, val)OMAP_IOPAD_OFFSET((pa), 0x2030) 
 (val)
 +#define OMAP3_CORE2_IOPAD(pa, val)OMAP_IOPAD_OFFSET((pa), 0x25a0) 
 (val)
>>>
>>> Sorry for the delay on these, I'm only now getting back to looking
>>> at all the emails since the holidays :)
>>>
>>> After looking at Nishant's omap3 pinctrl core2 patch, looks like we need
>>> to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.
>>
>> That was my first impression as well, but I think we actually don't need to. 
>> The OMAP3430 just has no useful registers in the 0x25a0 - 0x25d7 area, so we 
>> can make the CORE2 macro span that for both 3430 and 3630.
> 
> Hmm well I already did it :) In general my gut feeling is along the lines
> what you're saying, I think the padconf registers are all there on all
> omap3 SoCs, but only some of the padconf registers are used depending on
> the SoC revision and package.
> 
> Anyways, it should not hurt to have the padconf registers defined the
> same way as the documentation has them, at least we may get some extra
> warnings if people try to configure unused registers for 3430.
>  

I can see one downside to this approach; if you update the revision of
your processor from omap34xx to omap36xx, and if you are using pins from
the overlapping range [0x25d8; 0x25fc], you will have to update all the
macros, instead of simply updating the #include statement.

Let me introduce a real-life example. I am using Overo products. The
processor board must be stacked onto an expansion board. I currently
have only one include file for the processor board (omap3-overo.dtsi).
But in reality, Gumstix is currently selling 14 models, with
pin-compatible processors (omap35x3, dm3730, am3703) [1].

So I #include omap34xx.dtsi (to be compatible with the omap35x3 models).
The range [0x25d8; 0x25fc] defines a number of used features (hsusb2,
gpios). To update to newer versions, I have to change the #include, but
also all the OMAP3430_CORE2_IOPAD() macros spread across the expansion
boards (omap3-tobi + future expansion boards, see my series from today).
Even if the newer models do not use the omap36xx-specific features.

Obviously, I currently do not have a straightforward way to support all
the models/revisions with one single file. But if a solution is found in
the future, it will be far easier if the expansions boards do not depend
on the exact processor with such macros.

Regards,

Florian

[1] https://store.gumstix.com/index.php/category/33/
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Re: [PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Felipe Balbi]

On Thu, Jan 09, 2014 at 12:40:59PM -0600, Felipe Balbi wrote:
> Hi,
> 
> On Thu, Jan 09, 2014 at 11:22:17AM -0600, Felipe Balbi wrote:
> > > Changes compared to previous version:
> > > - Dropped any changes to generic clock drivers, as it seems impossible
> > >   to agree anything in short term, this means the patch set shrank in
> > >   size from 49 patches to 40 (first 9 patches were dropped).
> > > - Copy pasted implementation for clk-divider and clk-mux from drivers/clk
> > >   to drivers/clk/ti, and made the modifications needed to the TI version
> > >   of the clock drivers only (based on discussions with Mike, this is fine)
> > > - Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't 
> > > conflict
> > >   with any generic implementation we might have at some point, migrating
> > >   this to the generic version should be easy enough also.
> > > - Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
> > >   versions and resulted into an orphan clock node
> > > - Fixed compile problem for omap5 only build reported by Felipe
> > > - Fixed a couple of sparse warnings
> > > - changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
> > >   instead of __raw_readl / __raw_writel
> > 
> > just caught a build breakage. .config attached
> 
> forgot to give you build errors found, they're here:
> http://hastebin.com/jibuyuyoto.vbs
> 
> Also, just caught another build breakage:
> 
> http://hastebin.com/reravalupe.vbs
> 
> .config attached

hmm, quite a few configs are failing, seems like have DRA7xx without
OMAP4 or OMAP5 breaks builds.

-- 
balbi


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Re: [PATCH 00/18] ARM: dts: Better support for Gumstix Overo

[Ash Charles]

Hi Florian,
On Thu, Jan 9, 2014 at 9:06 AM, Benoit Cousson  wrote:
>> The patches 13 to 17 are based on the hardware schematics and
>> compile-tested, as I
>> do not have the necessary hardware (anyone willing to send me some boards
>> ? :-)
Firstly: thanks!
Secondly: Could you email (a...@gumstix.com) me a wish list of
boards/hardware?  I'll see what I can wrangle.

--Ash
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Re: [PATCH v8 3/7] regulator: add pbias regulator support

[Mark Brown]

On Thu, Jan 09, 2014 at 08:20:58PM +0530, Balaji T K wrote:
> pbias register controls internal power supply to sd card i/o pads
> in most OMAPs (OMAP2-5, DRA7).
> Control bits for selecting voltage level and
> enabling/disabling are in the same PBIAS register.

Acked-by: Mark Brown 


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Re: [PATCH 00/18] ARM: dts: Better support for Gumstix Overo

[Benoit Cousson]

Hi Florian,

On 09/01/2014 17:47, Florian Vaussard wrote:

Hello,

This series adds a number of improvements to Gumstix Overo.


Thanks for that nice series.


Patch 1+2: fix an issue with the vendor prefix (reported long ago by Javier 
Martinez Canillas)
Patch 3+4: add some missing pinctrl entries
Patch 5: completely turn off the PMIC on power off
Patch 6: enable the on-board Wifi
Patch 7: add the high-speed USB PHY
Patch 8: add specific timings for LAN9221 into a generic file
-> This might interest other people using the same chip, result in doubled 
bandwith

Patch 9: simplify omap3-tobi by using patch 8
Patch 10: add support for AT24C01 EEPROM used on expansion boards
Patch 11: factorize parts common to all expansion boards
Patch 12: rename omap3-tobi to omap3-overo-tobi
-> I do not know to which extent this might qualify as an API breakage,
but the new name is far better IMHO

Patch 13 to 17: add new extension boards (Palo43, Gallop43, Alto35, Chestnut43, 
Summit)
Patch 18: add the HDMI output
-> this patch depends on Tomi Valkeinen's DT binding for OMAPDSS, which is
not yet merged, so this patch will have to wait


The patches 13 to 17 are based on the hardware schematics and compile-tested, 
as I
do not have the necessary hardware (anyone willing to send me some boards ? :-)
We are mainly missing the support for the various LCDs, the accelerometer + 
probably
other small things.

This series is based on Tony's omap-for-v3.14/dt branch + work from Tomi [1] 
for the patch 18.

Benoit: I guess that I am too late for the 3.14... ?


Yeah, I think so, even my 3.14 branch is too late for 3.14 :-)

Thanks,
Benoit



Regards,

Florian


Florian Vaussard (18):
   of: add vendor prefix for Gumstix
   ARM: dts: omap3-tobi: Use the correct vendor prefix
   ARM: dts: omap3-tobi: Add missing pinctrl
   ARM: dts: omap3-overo: Add missing pinctrl
   ARM: dts: omap3-overo: Use complete poweroff
   ARM: dts: omap3-overo: Enable MMC2
   ARM: dts: omap3-overo: Add HSUSB PHY
   ARM: dts: omap: Add common file for SMSC9221
   ARM: dts: omap3-tobi: Use include file omap-gpmc-smsc9221
   ARM: dts: omap3-tobi: Add AT24C01 EEPROM
   ARM: dts: omap3-tobi: Create a file for common Gumstix peripherals
   ARM: dts: omap3-tobi: Rename to omap3-overo-tobi
   ARM: dts: Add support for the Overo Palo43
   ARM: dts: Add support for the Overo Gallop43
   ARM: dts: Add support for the Overo Alto35
   ARM: dts: Add support for the Overo Chestnut43
   ARM: dts: Add support for the Overo Summit
   ARM: dts: overo: Add support for DVI output

  .../devicetree/bindings/vendor-prefixes.txt|   1 +
  arch/arm/boot/dts/Makefile |   7 +-
  arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi  |  58 ++
  arch/arm/boot/dts/omap3-overo-alto35.dts   |  52 +
  arch/arm/boot/dts/omap3-overo-chestnut43.dts   |  76 +
  arch/arm/boot/dts/omap3-overo-common-dvi.dtsi  | 108 ++
  arch/arm/boot/dts/omap3-overo-common.dtsi  |  39 +++
  arch/arm/boot/dts/omap3-overo-gallop43.dts |  51 +
  arch/arm/boot/dts/omap3-overo-palo43.dts   |  52 +
  arch/arm/boot/dts/omap3-overo-summit.dts   |  30 +
  .../dts/{omap3-tobi.dts => omap3-overo-tobi.dts}   |  41 +--
  arch/arm/boot/dts/omap3-overo.dtsi | 122 +++--
  12 files changed, 594 insertions(+), 43 deletions(-)
  create mode 100644 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
  create mode 100644 arch/arm/boot/dts/omap3-overo-alto35.dts
  create mode 100644 arch/arm/boot/dts/omap3-overo-chestnut43.dts
  create mode 100644 arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
  create mode 100644 arch/arm/boot/dts/omap3-overo-common.dtsi
  create mode 100644 arch/arm/boot/dts/omap3-overo-gallop43.dts
  create mode 100644 arch/arm/boot/dts/omap3-overo-palo43.dts
  create mode 100644 arch/arm/boot/dts/omap3-overo-summit.dts
  rename arch/arm/boot/dts/{omap3-tobi.dts => omap3-overo-tobi.dts} (54%)




--
Benoît Cousson
BayLibre
Embedded Linux Technology Lab
www.baylibre.com
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[PATCH 16/18] ARM: dts: Add support for the Overo Chestnut43

[Florian Vaussard]

Chestnut43 is an expansion board for Gumstix Overo products.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/omap3-overo-chestnut43.dts | 76 
 2 files changed, 77 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-overo-chestnut43.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 29432b0..3f6ef70 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -190,6 +190,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
omap3-overo-alto35.dtb \
+   omap3-overo-chestnut43.dtb \
omap3-overo-gallop43.dtb \
omap3-overo-palo43.dtb \
omap3-overo-tobi.dtb \
diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts 
b/arch/arm/boot/dts/omap3-overo-chestnut43.dts
new file mode 100644
index 000..3361c2d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-chestnut43.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Chestnut43 expansion board is manufactured by Gumstix Inc.
+ */
+
+#include "omap3-overo-common.dtsi"
+
+#include 
+
+/ {
+   model = "TI OMAP3 Gumstix Overo on Chestnut43";
+   compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", 
"ti,omap3";
+
+   leds {
+   compatible = "gpio-leds";
+   heartbeat {
+   label = "overo:red:gpio21";
+   gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "heartbeat";
+   };
+   gpio22 {
+   label = "overo:blue:gpio22";
+   gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   button0@23 {
+   label = "button0";
+   linux,code = ;
+   gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   button1@14 {
+   label = "button1";
+   linux,code = ;
+   gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   };
+
+   vddvario: regulator-vddvario {
+ compatible = "regulator-fixed";
+ regulator-name = "vddvario";
+ regulator-always-on;
+   };
+
+   vdd33a: regulator-vdd33a {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd33a";
+   regulator-always-on;
+   };
+};
+
+#include "omap-gpmc-smsc9221.dtsi"
+
+&gpmc {
+   ranges = <5 0 0x2c00 0x100>;/* CS5 */
+
+   ethernet@gpmc {
+   reg = <5 0 0xff>;
+   interrupt-parent = <&gpio6>;
+   interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
+   };
+};
+
-- 
1.8.1.2

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[PATCH 18/18] ARM: dts: overo: Add support for DVI output

[Florian Vaussard]

Summit and Tobi expansion boards have a HDMI connector with a TFP410
encoder. Add a common include file for this configuration, and then
use it for Summit and Tobi.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-overo-common-dvi.dtsi | 108 ++
 arch/arm/boot/dts/omap3-overo-summit.dts  |   3 +
 arch/arm/boot/dts/omap3-overo-tobi.dts|   2 +
 3 files changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-overo-common-dvi.dtsi

diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi 
b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
new file mode 100644
index 000..e4a0fa0
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * DVI output for some Gumstix Overo boards (Tobi and Summit)
+ */
+
+&omap3_pmx_core {
+   i2c3_pins: pinmux_i2c3_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)
/* i2c3_scl.i2c3_scl */
+   OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)
/* i2c3_sda.i2c3_sda */
+   >;
+   };
+
+   dss_dpi_pins: pinmux_dss_dpi_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   
/* dss_pclk.dss_pclk */
+   OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   
/* dss_hsync.dss_hsync */
+   OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   
/* dss_vsync.dss_vsync */
+   OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   
/* dss_acbias.dss_acbias */
+   OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)   
/* dss_data0.dss_data0 */
+   OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)   
/* dss_data1.dss_data1 */
+   OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)   
/* dss_data2.dss_data2 */
+   OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)   
/* dss_data3.dss_data3 */
+   OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)   
/* dss_data4.dss_data4 */
+   OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)   
/* dss_data5.dss_data5 */
+   OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   
/* dss_data6.dss_data6 */
+   OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   
/* dss_data7.dss_data7 */
+   OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   
/* dss_data8.dss_data8 */
+   OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   
/* dss_data9.dss_data9 */
+   OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   
/* dss_data10.dss_data10 */
+   OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   
/* dss_data11.dss_data11 */
+   OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   
/* dss_data12.dss_data12 */
+   OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   
/* dss_data13.dss_data13 */
+   OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   
/* dss_data14.dss_data14 */
+   OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   
/* dss_data15.dss_data15 */
+   OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   
/* dss_data16.dss_data16 */
+   OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   
/* dss_data17.dss_data17 */
+   OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)   
/* dss_data18.dss_data18 */
+   OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)   
/* dss_data19.dss_data19 */
+   OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)   
/* dss_data20.dss_data20 */
+   OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)   
/* dss_data21.dss_data21 */
+   OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)   
/* dss_data22.dss_data22 */
+   OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)   
/* dss_data23.dss_data23 */
+   >;
+   };
+};
+
+&dss {
+   pinctrl-names = "default";
+   pinctrl-0 = <&dss_dpi_pins>;
+
+   vdds_dsi-supply = <&vpll2>;
+
+   dpi_out: endpoint {
+   remote-endpoint = <&tfp410_in>;
+   data-lines = <24>;
+   };
+};
+
+/ {
+   aliases {
+   display0 = &dvi0;
+   };
+
+   tfp410: encoder@0 {
+   compatible = "ti,tfp410";
+
+   ports {
+   #address

[PATCH 17/18] ARM: dts: Add support for the Overo Summit

[Florian Vaussard]

Summit is an expansion board for Gumstix Overo products.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/omap3-overo-summit.dts | 27 +++
 2 files changed, 28 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-overo-summit.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3f6ef70..d00f023 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-overo-chestnut43.dtb \
omap3-overo-gallop43.dtb \
omap3-overo-palo43.dtb \
+   omap3-overo-summit.dtb \
omap3-overo-tobi.dtb \
omap3-gta04.dtb \
omap3-igep0020.dtb \
diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts 
b/arch/arm/boot/dts/omap3-overo-summit.dts
new file mode 100644
index 000..fd8b47c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-summit.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Summit expansion board is manufactured by Gumstix Inc.
+ */
+
+#include "omap3-overo-common.dtsi"
+
+/ {
+   model = "TI OMAP3 Gumstix Overo on Summit";
+   compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", 
"ti,omap3";
+
+   leds {
+   compatible = "gpio-leds";
+   heartbeat {
+   label = "overo:red:gpio21";
+   gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+};
-- 
1.8.1.2

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[PATCH 14/18] ARM: dts: Add support for the Overo Gallop43

[Florian Vaussard]

Gallop43 is an expansion board for Gumstix Overo products.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/Makefile |  1 +
 arch/arm/boot/dts/omap3-overo-gallop43.dts | 51 ++
 2 files changed, 52 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-overo-gallop43.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 98f9bc5..799b306 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -189,6 +189,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-n900.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
+   omap3-overo-gallop43.dtb \
omap3-overo-palo43.dtb \
omap3-overo-tobi.dtb \
omap3-gta04.dtb \
diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts 
b/arch/arm/boot/dts/omap3-overo-gallop43.dts
new file mode 100644
index 000..32f719e
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-gallop43.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Gallop43 expansion board is manufactured by Gumstix Inc.
+ */
+
+#include "omap3-overo-common.dtsi"
+
+#include 
+
+/ {
+   model = "TI OMAP3 Gumstix Overo on Gallop43";
+   compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", 
"ti,omap3";
+
+   leds {
+   compatible = "gpio-leds";
+   heartbeat {
+   label = "overo:red:gpio21";
+   gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "heartbeat";
+   };
+   gpio22 {
+   label = "overo:blue:gpio22";
+   gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   button0@23 {
+   label = "button0";
+   linux,code = ;
+   gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   button1@14 {
+   label = "button1";
+   linux,code = ;
+   gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   };
+};
-- 
1.8.1.2

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[PATCH 02/18] ARM: dts: omap3-tobi: Use the correct vendor prefix

[Florian Vaussard]

Gumstix is the correct vendor for all Overo related products.

Reported-by: Javier Martinez Canillas 
Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-tobi.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 7e4ad2a..9fe10ca 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -14,7 +14,7 @@
 
 / {
model = "TI OMAP3 Gumstix Overo on Tobi";
-   compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
+   compatible = "gumstix,omap3-tobi", "gumstix,omap3-overo", "ti,omap3";
 
leds {
compatible = "gpio-leds";
-- 
1.8.1.2

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[PATCH 15/18] ARM: dts: Add support for the Overo Alto35

[Florian Vaussard]

Alto35 is an expansion board for Gumstix Overo products.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/omap3-overo-alto35.dts | 52 
 2 files changed, 53 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-overo-alto35.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 799b306..29432b0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -189,6 +189,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-n900.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
+   omap3-overo-alto35.dtb \
omap3-overo-gallop43.dtb \
omap3-overo-palo43.dtb \
omap3-overo-tobi.dtb \
diff --git a/arch/arm/boot/dts/omap3-overo-alto35.dts 
b/arch/arm/boot/dts/omap3-overo-alto35.dts
new file mode 100644
index 000..40c7e6c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-alto35.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Alto35 expansion board is manufactured by Gumstix Inc.
+ */
+
+#include "omap3-overo-common.dtsi"
+
+#include 
+
+/ {
+   model = "TI OMAP3 Gumstix Overo on Alto35";
+   compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", 
"ti,omap3";
+
+   leds {
+   compatible = "gpio-leds";
+   gpio148 {
+   label = "overo:red:gpio148";
+   gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;   /* gpio 148 */
+   };
+   gpio150 {
+   label = "overo:yellow:gpio150";
+   gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;   /* gpio 150 */
+   };
+   gpio151 {
+   label = "overo:blue:gpio151";
+   gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;   /* gpio 151 */
+   };
+   gpio170 {
+   label = "overo:green:gpio170";
+   gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;   /* gpio 170 */
+   };
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   button0@10 {
+   label = "button0";
+   linux,code = ;
+   gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   };
+};
-- 
1.8.1.2

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[PATCH 11/18] ARM: dts: omap3-tobi: Create a file for common Gumstix peripherals

[Florian Vaussard]

Gumstix expansion boards share a couple of peripherals:
- i2c3 is used for the console
- AT24C01 EEPROM on i2c3

Use this file for omap3-tobi.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-overo-common.dtsi | 39 +++
 arch/arm/boot/dts/omap3-tobi.dts  | 27 +
 2 files changed, 40 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-overo-common.dtsi

diff --git a/arch/arm/boot/dts/omap3-overo-common.dtsi 
b/arch/arm/boot/dts/omap3-overo-common.dtsi
new file mode 100644
index 000..5f38ce8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-common.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...)
+ */
+
+#include "omap3-overo.dtsi"
+
+&omap3_pmx_core {
+   i2c3_pins: pinmux_i2c3_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)
/* i2c3_scl.i2c3_scl */
+   OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)
/* i2c3_sda.i2c3_sda */
+   >;
+   };
+};
+
+&i2c3 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&i2c3_pins>;
+   clock-frequency = <10>;
+
+   /* optional 1K EEPROM with revision information */
+   eeprom@51 {
+   compatible = "atmel,24c01";
+   reg = <0x51>;
+   pagesize = <8>;
+   };
+};
+
+&mmc3 {
+   status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 67c056d..928d12f 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-#include "omap3-overo.dtsi"
+#include "omap3-overo-common.dtsi"
 
 / {
model = "TI OMAP3 Gumstix Overo on Tobi";
@@ -38,15 +38,6 @@
};
 };
 
-&omap3_pmx_core {
-   i2c3_pins: pinmux_i2c3_pins {
-   pinctrl-single,pins = <
-   OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)
/* i2c3_scl.i2c3_scl */
-   OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)
/* i2c3_sda.i2c3_sda */
-   >;
-   };
-};
-
 #include "omap-gpmc-smsc9221.dtsi"
 
 &gpmc {
@@ -59,19 +50,3 @@
};
 };
 
-&i2c3 {
-   pinctrl-names = "default";
-   pinctrl-0 = <&i2c3_pins>;
-   clock-frequency = <10>;
-
-   /* optional 1K EEPROM with revision information */
-   eeprom@51 {
-   compatible = "atmel,24c01";
-   reg = <0x51>;
-   pagesize = <8>;
-   };
-};
-
-&mmc3 {
-   status = "disabled";
-};
-- 
1.8.1.2

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[PATCH 00/18] ARM: dts: Better support for Gumstix Overo

[Florian Vaussard]

Hello,

This series adds a number of improvements to Gumstix Overo.

Patch 1+2: fix an issue with the vendor prefix (reported long ago by Javier 
Martinez Canillas)
Patch 3+4: add some missing pinctrl entries
Patch 5: completely turn off the PMIC on power off
Patch 6: enable the on-board Wifi
Patch 7: add the high-speed USB PHY
Patch 8: add specific timings for LAN9221 into a generic file
-> This might interest other people using the same chip, result in doubled 
bandwith

Patch 9: simplify omap3-tobi by using patch 8
Patch 10: add support for AT24C01 EEPROM used on expansion boards
Patch 11: factorize parts common to all expansion boards
Patch 12: rename omap3-tobi to omap3-overo-tobi
-> I do not know to which extent this might qualify as an API breakage,
   but the new name is far better IMHO

Patch 13 to 17: add new extension boards (Palo43, Gallop43, Alto35, Chestnut43, 
Summit)
Patch 18: add the HDMI output
-> this patch depends on Tomi Valkeinen's DT binding for OMAPDSS, which is
   not yet merged, so this patch will have to wait


The patches 13 to 17 are based on the hardware schematics and compile-tested, 
as I
do not have the necessary hardware (anyone willing to send me some boards ? :-)
We are mainly missing the support for the various LCDs, the accelerometer + 
probably
other small things.

This series is based on Tony's omap-for-v3.14/dt branch + work from Tomi [1] 
for the patch 18.

Benoit: I guess that I am too late for the 3.14... ?

Regards,

Florian


Florian Vaussard (18):
  of: add vendor prefix for Gumstix
  ARM: dts: omap3-tobi: Use the correct vendor prefix
  ARM: dts: omap3-tobi: Add missing pinctrl
  ARM: dts: omap3-overo: Add missing pinctrl
  ARM: dts: omap3-overo: Use complete poweroff
  ARM: dts: omap3-overo: Enable MMC2
  ARM: dts: omap3-overo: Add HSUSB PHY
  ARM: dts: omap: Add common file for SMSC9221
  ARM: dts: omap3-tobi: Use include file omap-gpmc-smsc9221
  ARM: dts: omap3-tobi: Add AT24C01 EEPROM
  ARM: dts: omap3-tobi: Create a file for common Gumstix peripherals
  ARM: dts: omap3-tobi: Rename to omap3-overo-tobi
  ARM: dts: Add support for the Overo Palo43
  ARM: dts: Add support for the Overo Gallop43
  ARM: dts: Add support for the Overo Alto35
  ARM: dts: Add support for the Overo Chestnut43
  ARM: dts: Add support for the Overo Summit
  ARM: dts: overo: Add support for DVI output

 .../devicetree/bindings/vendor-prefixes.txt|   1 +
 arch/arm/boot/dts/Makefile |   7 +-
 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi  |  58 ++
 arch/arm/boot/dts/omap3-overo-alto35.dts   |  52 +
 arch/arm/boot/dts/omap3-overo-chestnut43.dts   |  76 +
 arch/arm/boot/dts/omap3-overo-common-dvi.dtsi  | 108 ++
 arch/arm/boot/dts/omap3-overo-common.dtsi  |  39 +++
 arch/arm/boot/dts/omap3-overo-gallop43.dts |  51 +
 arch/arm/boot/dts/omap3-overo-palo43.dts   |  52 +
 arch/arm/boot/dts/omap3-overo-summit.dts   |  30 +
 .../dts/{omap3-tobi.dts => omap3-overo-tobi.dts}   |  41 +--
 arch/arm/boot/dts/omap3-overo.dtsi | 122 +++--
 12 files changed, 594 insertions(+), 43 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-overo-alto35.dts
 create mode 100644 arch/arm/boot/dts/omap3-overo-chestnut43.dts
 create mode 100644 arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-overo-common.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-overo-gallop43.dts
 create mode 100644 arch/arm/boot/dts/omap3-overo-palo43.dts
 create mode 100644 arch/arm/boot/dts/omap3-overo-summit.dts
 rename arch/arm/boot/dts/{omap3-tobi.dts => omap3-overo-tobi.dts} (54%)

-- 
1.8.1.2

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[PATCH 12/18] ARM: dts: omap3-tobi: Rename to omap3-overo-tobi

[Florian Vaussard]

To enhance the clarity and coherence, rename omap3-tobi to omap3-overo-tobi.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/Makefile | 2 +-
 arch/arm/boot/dts/{omap3-tobi.dts => omap3-overo-tobi.dts} | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/arm/boot/dts/{omap3-tobi.dts => omap3-overo-tobi.dts} (93%)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b7af502..7b028e4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -189,7 +189,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-n900.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
-   omap3-tobi.dtb \
+   omap3-overo-tobi.dtb \
omap3-gta04.dtb \
omap3-igep0020.dtb \
omap3-igep0030.dtb \
diff --git a/arch/arm/boot/dts/omap3-tobi.dts 
b/arch/arm/boot/dts/omap3-overo-tobi.dts
similarity index 93%
rename from arch/arm/boot/dts/omap3-tobi.dts
rename to arch/arm/boot/dts/omap3-overo-tobi.dts
index 928d12f..5072da2 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-tobi.dts
@@ -14,7 +14,7 @@
 
 / {
model = "TI OMAP3 Gumstix Overo on Tobi";
-   compatible = "gumstix,omap3-tobi", "gumstix,omap3-overo", "ti,omap3";
+   compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", 
"ti,omap3";
 
leds {
compatible = "gpio-leds";
-- 
1.8.1.2

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[PATCH 04/18] ARM: dts: omap3-overo: Add missing pinctrl

[Florian Vaussard]

Add missing pinctrl entries for:
- i2c1
- mmc1

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-overo.dtsi | 40 +-
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-overo.dtsi 
b/arch/arm/boot/dts/omap3-overo.dtsi
index a461d2f..2d8b80c 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -34,7 +34,36 @@
};
 };
 
+&omap3_pmx_core {
+   uart3_pins: pinmux_uart3_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | 
PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+   OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)   
/* uart3_tx_irtx.uart3_tx_irtx */
+   >;
+   };
+
+   i2c1_pins: pinmux_i2c1_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)
/* i2c1_scl.i2c1_scl */
+   OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)
/* i2c1_sda.i2c1_sda */
+   >;
+   };
+
+   mmc1_pins: pinmux_mmc1_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_clk.sdmmc1_clk */
+   OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_cmd.sdmmc1_cmd */
+   OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_dat0.sdmmc1_dat0 */
+   OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_dat1.sdmmc1_dat1 */
+   OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_dat2.sdmmc1_dat2 */
+   OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_dat3.sdmmc1_dat3 */
+   >;
+   };
+};
+
 &i2c1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&i2c1_pins>;
clock-frequency = <260>;
 
twl: twl@48 {
@@ -60,6 +89,8 @@
 
 /* on board microSD slot */
 &mmc1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
bus-width = <4>;
 };
@@ -82,15 +113,6 @@
power = <50>;
 };
 
-&omap3_pmx_core {
-   uart3_pins: pinmux_uart3_pins {
-   pinctrl-single,pins = <
-   0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* 
uart3_rx_irrx.uart3_rx_irrx */
-   0x170 (PIN_OUTPUT | MUX_MODE0) /* 
uart3_tx_irtx.uart3_tx_irtx */
-   >;
-   };
-};
-
 &uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
-- 
1.8.1.2

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[PATCH 13/18] ARM: dts: Add support for the Overo Palo43

[Florian Vaussard]

Palo43 is an expansion board for Gumstix Overo products.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/omap3-overo-palo43.dts | 52 
 2 files changed, 53 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3-overo-palo43.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7b028e4..98f9bc5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -189,6 +189,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-n900.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
+   omap3-overo-palo43.dtb \
omap3-overo-tobi.dtb \
omap3-gta04.dtb \
omap3-igep0020.dtb \
diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts 
b/arch/arm/boot/dts/omap3-overo-palo43.dts
new file mode 100644
index 000..2d5791b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-palo43.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Palo43 expansion board is manufactured by Gumstix Inc.
+ */
+
+#include "omap3-overo-common.dtsi"
+
+#include 
+
+/ {
+   model = "TI OMAP3 Gumstix Overo on Palo43";
+   compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", 
"ti,omap3";
+
+   leds {
+   compatible = "gpio-leds";
+   heartbeat {
+   label = "overo:red:gpio21";
+   gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "heartbeat";
+   };
+   gpio22 {
+   label = "overo:blue:gpio22";
+   gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   button0@23 {
+   label = "button0";
+   linux,code = ;
+   gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   button1@14 {
+   label = "button1";
+   linux,code = ;
+   gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+   gpio-key,wakeup;
+   };
+   };
+};
+
-- 
1.8.1.2

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[PATCH 08/18] ARM: dts: omap: Add common file for SMSC9221

[Florian Vaussard]

Some devices (SMSC9217, SMSC9218 and SMSC9221 at least) have better
timings, allowing a higher transfer speed. Create a common file
with these timings.

Performance results with iperf:

- omap-gpmc-smsc911x.dtsi => 54.9 Mbps
- omap-gpmc-smsc9221.dtsi => 92.7 Mbps

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi | 58 +++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi

diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi 
b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
new file mode 100644
index 000..73e272f
--- /dev/null
+++ b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Common file for GPMC connected smsc9221 on omaps
+ *
+ * Compared to smsc911x, smsc9221 (and others like smsc9217
+ * or smsc 9218) has faster timings, leading to higher
+ * bandwidth.
+ *
+ * Note that the board specifc DTS file needs to specify
+ * ranges, pinctrl, reg, interrupt parent and interrupts.
+ */
+
+/ {
+   vddvario: regulator-vddvario {
+ compatible = "regulator-fixed";
+ regulator-name = "vddvario";
+ regulator-always-on;
+   };
+
+   vdd33a: regulator-vdd33a {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd33a";
+   regulator-always-on;
+   };
+};
+
+&gpmc {
+   ethernet@gpmc {
+   compatible = "smsc,lan9221","smsc,lan9115";
+   bank-width = <2>;
+
+   gpmc,mux-add-data;
+   gpmc,cs-on-ns = <0>;
+   gpmc,cs-rd-off-ns = <42>;
+   gpmc,cs-wr-off-ns = <36>;
+   gpmc,adv-on-ns = <6>;
+   gpmc,adv-rd-off-ns = <12>;
+   gpmc,adv-wr-off-ns = <12>;
+   gpmc,oe-on-ns = <0>;
+   gpmc,oe-off-ns = <42>;
+   gpmc,we-on-ns = <0>;
+   gpmc,we-off-ns = <36>;
+   gpmc,rd-cycle-ns = <60>;
+   gpmc,wr-cycle-ns = <54>;
+   gpmc,access-ns = <36>;
+   gpmc,page-burst-access-ns = <0>;
+   gpmc,bus-turnaround-ns = <0>;
+   gpmc,cycle2cycle-delay-ns = <0>;
+   gpmc,wr-data-mux-bus-ns = <18>;
+   gpmc,wr-access-ns = <42>;
+   gpmc,cycle2cycle-samecsen;
+   gpmc,cycle2cycle-diffcsen;
+
+   vddvario-supply = <&vddvario>;
+   vdd33a-supply = <&vdd33a>;
+   reg-io-width = <4>;
+   smsc,save-mac-address;
+   };
+};
-- 
1.8.1.2

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[PATCH 09/18] ARM: dts: omap3-tobi: Use include file omap-gpmc-smsc9221

[Florian Vaussard]

Use the timings provided by omap-gpmc-smsc9221. This does not change
the timings, but it avoids code duplication.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-tobi.dts | 30 +++---
 1 file changed, 3 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index d39fe57..e9a841a 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -47,39 +47,15 @@
};
 };
 
+#include "omap-gpmc-smsc9221.dtsi"
+
 &gpmc {
ranges = <5 0 0x2c00 0x100>;/* CS5 */
 
-   ethernet@5,0 {
-   compatible = "smsc,lan9221", "smsc,lan9115";
+   ethernet@gpmc {
reg = <5 0 0xff>;
-   bank-width = <2>;
-
-   gpmc,mux-add-data;
-   gpmc,cs-on-ns = <0>;
-   gpmc,cs-rd-off-ns = <42>;
-   gpmc,cs-wr-off-ns = <36>;
-   gpmc,adv-on-ns = <6>;
-   gpmc,adv-rd-off-ns = <12>;
-   gpmc,adv-wr-off-ns = <12>;
-   gpmc,oe-on-ns = <0>;
-   gpmc,oe-off-ns = <42>;
-   gpmc,we-on-ns = <0>;
-   gpmc,we-off-ns = <36>;
-   gpmc,rd-cycle-ns = <60>;
-   gpmc,wr-cycle-ns = <54>;
-   gpmc,access-ns = <36>;
-   gpmc,page-burst-access-ns = <0>;
-   gpmc,bus-turnaround-ns = <0>;
-   gpmc,cycle2cycle-delay-ns = <0>;
-   gpmc,wr-data-mux-bus-ns = <18>;
-   gpmc,wr-access-ns = <42>;
-   gpmc,cycle2cycle-samecsen;
-   gpmc,cycle2cycle-diffcsen;
-
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
-   reg-io-width = <4>;
};
 };
 
-- 
1.8.1.2

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[PATCH 10/18] ARM: dts: omap3-tobi: Add AT24C01 EEPROM

[Florian Vaussard]

Add the AT24C01 EEPROM node populated on most Gumstix expansion board.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-tobi.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index e9a841a..67c056d 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -63,6 +63,13 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <10>;
+
+   /* optional 1K EEPROM with revision information */
+   eeprom@51 {
+   compatible = "atmel,24c01";
+   reg = <0x51>;
+   pagesize = <8>;
+   };
 };
 
 &mmc3 {
-- 
1.8.1.2

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[PATCH 06/18] ARM: dts: omap3-overo: Enable MMC2

[Florian Vaussard]

MMC2 is used by the on-board WiFi module populated on some boards
(based on Marvell Libertas 8688 SDIO).

Note: currently WiFi only works on cold boot, as the module is not
properly reset (missing binding for the GPIO reset).

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-overo.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-overo.dtsi 
b/arch/arm/boot/dts/omap3-overo.dtsi
index d48f25c..9ce9591 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -32,6 +32,12 @@
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
+
+   vlibertas: regulator-vlibertas {
+   compatible = "regulator-fixed";
+   regulator-name = "vlibertas";
+   regulator-always-on;
+   };
 };
 
 &omap3_pmx_core {
@@ -59,6 +65,17 @@
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc1_dat3.sdmmc1_dat3 */
>;
};
+
+   mmc2_pins: pinmux_mmc2_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_clk.sdmmc2_clk */
+   OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_cmd.sdmmc2_cmd */
+   OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_dat0.sdmmc2_dat0 */
+   OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_dat1.sdmmc2_dat1 */
+   OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_dat2.sdmmc2_dat2 */
+   OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_dat3.sdmmc2_dat3 */
+   >;
+   };
 };
 
 &i2c1 {
@@ -102,7 +119,11 @@
 
 /* optional on board WiFi */
 &mmc2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc2_pins>;
+   vmmc-supply = <&vlibertas>;
bus-width = <4>;
+   non-removable;
 };
 
 &twl_gpio {
-- 
1.8.1.2

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[PATCH 03/18] ARM: dts: omap3-tobi: Add missing pinctrl

[Florian Vaussard]

Add missing pinctrl entries:
- i2c3

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-tobi.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index 9fe10ca..d39fe57 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -38,6 +38,15 @@
};
 };
 
+&omap3_pmx_core {
+   i2c3_pins: pinmux_i2c3_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)
/* i2c3_scl.i2c3_scl */
+   OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)
/* i2c3_sda.i2c3_sda */
+   >;
+   };
+};
+
 &gpmc {
ranges = <5 0 0x2c00 0x100>;/* CS5 */
 
@@ -75,6 +84,8 @@
 };
 
 &i2c3 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&i2c3_pins>;
clock-frequency = <10>;
 };
 
-- 
1.8.1.2

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[PATCH 05/18] ARM: dts: omap3-overo: Use complete poweroff

[Florian Vaussard]

Currently, the TWL4030 PMIC does not completely poweroff the processor.
Commit b0fc1da4d0359d3cce8f12e0f014aed0704ae202 introduced the necessary
binding to do this, so use it.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-overo.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-overo.dtsi 
b/arch/arm/boot/dts/omap3-overo.dtsi
index 2d8b80c..d48f25c 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -76,6 +76,11 @@
codec {
};
};
+
+   twl_power: power {
+   compatible = "ti,twl4030-power";
+   ti,use_poweroff;
+   };
};
 };
 
-- 
1.8.1.2

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[PATCH 01/18] of: add vendor prefix for Gumstix

[Florian Vaussard]

Using "gumstix" for Gumstix Inc.

Signed-off-by: Florian Vaussard 
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index edbb8d8..968a955 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -33,6 +33,7 @@ fsl   Freescale Semiconductor
 GEFanucGE Fanuc Intelligent Platforms Embedded Systems, Inc.
 gefGE Fanuc Intelligent Platforms Embedded Systems, Inc.
 gmtGlobal Mixed-mode Technology, Inc.
+gumstixGumstix, Inc.
 hisilicon  Hisilicon Limited.
 hp Hewlett Packard
 ibmInternational Business Machines (IBM)
-- 
1.8.1.2

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[PATCH 07/18] ARM: dts: omap3-overo: Add HSUSB PHY

[Florian Vaussard]

Add the High-Speed USB PHY.

Signed-off-by: Florian Vaussard 
---
 arch/arm/boot/dts/omap3-overo.dtsi | 60 ++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-overo.dtsi 
b/arch/arm/boot/dts/omap3-overo.dtsi
index 9ce9591..ecf5818 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -33,6 +33,24 @@
ti,codec = <&twl_audio>;
};
 
+   /* HS USB Port 2 Power */
+   hsusb2_power: hsusb2_power_reg {
+   compatible = "regulator-fixed";
+   regulator-name = "hsusb2_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = <&gpio6 8 0>;/* gpio_168 */
+   startup-delay-us = <7>;
+   enable-active-high;
+   };
+
+   /* HS USB Host PHY on PORT 2 */
+   hsusb2_phy: hsusb2_phy {
+   compatible = "usb-nop-xceiv";
+   reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;  /* gpio_183 */
+   vcc-supply = <&hsusb2_power>;
+   };
+
vlibertas: regulator-vlibertas {
compatible = "regulator-fixed";
regulator-name = "vlibertas";
@@ -41,6 +59,11 @@
 };
 
 &omap3_pmx_core {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   &hsusb2_pins
+   >;
+
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | 
PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
@@ -76,6 +99,35 @@
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) 
/* sdmmc2_dat3.sdmmc2_dat3 */
>;
};
+
+   hsusb2_pins: pinmux_hsusb2_pins {
+   pinctrl-single,pins = <
+   OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | 
MUX_MODE3)   /* mcspi1_cs3.hsusb2_data2 */
+   OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | 
MUX_MODE3)   /* mcspi2_clk.hsusb2_data7 */
+   OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | 
MUX_MODE3)   /* mcspi2_simo.hsusb2_data4 */
+   OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | 
MUX_MODE3)   /* mcspi2_somi.hsusb2_data5 */
+   OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | 
MUX_MODE3)   /* mcspi2_cs0.hsusb2_data6 */
+   OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | 
MUX_MODE3)   /* mcspi2_cs1.hsusb2_data3 */
+   >;
+   };
+};
+
+&omap3_pmx_core2 {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   &hsusb2_2_pins
+   >;
+
+   hsusb2_2_pins: pinmux_hsusb2_2_pins {
+   pinctrl-single,pins = <
+   OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
/* etk_d10.hsusb2_clk */
+   OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
/* etk_d11.hsusb2_stp */
+   OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | 
MUX_MODE3)/* etk_d12.hsusb2_dir */
+   OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | 
MUX_MODE3)/* etk_d13.hsusb2_nxt */
+   OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | 
MUX_MODE3)/* etk_d14.hsusb2_data0 */
+   OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | 
MUX_MODE3)/* etk_d15.hsusb2_data1 */
+   >;
+   };
 };
 
 &i2c1 {
@@ -139,6 +191,14 @@
power = <50>;
 };
 
+&usbhshost {
+   port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+   phys = <0 &hsusb2_phy>;
+};
+
 &uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
-- 
1.8.1.2

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Re: DSS DT support for 3.14 probably not possible

[Tony Lindgren]

* Tomi Valkeinen  [140109 02:00]:
> Hi Tony,
> 
> Unfortunately I think the DSS DT series will miss 3.14 merge window.
> 
> The code feels quite fine, but I'm still in the process of writing the
> binding documentation and getting those reviewed. And that review could
> of course lead to some new changes.

OK
 
> So if we're going for DT-only boot for 3.14, I guess the only option is
> to create the quirk display platform data for all the boards...

We can't quite yet make things DT-only. So let's just add the display
quirk support as needed.

Regards,

Tony
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Re: [PATCH v2 2/3] ARM: OMAP2+: Add support to parse optional clk info from DT

[Nishanth Menon]

On 12/12/2013 05:38 AM, Rajendra Nayak wrote:
> With clocks for OMAP moving to DT, its now possible to pass all optional clock
> data for each device from DT instead of having it in hwmod.
> 
> Signed-off-by: Rajendra Nayak 
> ---
>  arch/arm/mach-omap2/omap_hwmod.c |   65 
> --
>  1 file changed, 63 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c 
> b/arch/arm/mach-omap2/omap_hwmod.c
> index f22..271634f 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -807,6 +807,64 @@ static int _init_interface_clks(struct omap_hwmod *oh)
>   return ret;
>  }
>  
> +static const char **_parse_opt_clks_dt(struct omap_hwmod *oh,
> +struct device_node *np,
> +int *opt_clks_cnt)
> +{
> + int i, clks_cnt;
> + const char *clk_name;
> + const char **opt_clk_names;
> +
> + clks_cnt = of_property_count_strings(np, "clock-names");
> + if (!clks_cnt)
> + return NULL;
> +
> + opt_clk_names = kzalloc(sizeof(char *)*clks_cnt, GFP_KERNEL);
> + if (!opt_clk_names)
> + return NULL;
> +
> + for (i = 0; i < clks_cnt; i++) {
> + of_property_read_string_index(np, "clock-names", i, &clk_name);
> + if (!strcmp(clk_name, "fck"))
> + continue;
> + opt_clks_cnt++;
> + opt_clk_names[i] = clk_name;

This assumes that any clock-names entry which does not match "fck" is
an optional clock that should be controlled by hwmod -> this is not
always the case and in cases such as gpio or mmc, the optional
debounce clock is actually prefered to be controlled by the driver.

we wont have a way around that.

> + }
> + return opt_clk_names;
> +}
> +
> +static int _init_opt_clks_dt(struct omap_hwmod *oh, struct device_node *np)
> +{
> + struct clk *c;
> + int i, opt_clks_cnt = 0;
> + int ret = 0;
> + const char **opt_clk_names;
> +
> + opt_clk_names = _parse_opt_clks_dt(oh, np, &opt_clks_cnt);
> + if (!opt_clk_names)
> + return -EINVAL;
> +
> + oh->opt_clks = kzalloc(sizeof(struct omap_hwmod_opt_clk *)
> +* opt_clks_cnt, GFP_KERNEL);
> + if (!oh->opt_clks)
> + return -ENOMEM;
> +
> + oh->opt_clks_cnt = opt_clks_cnt;
> +
> + for (i = 0; i < oh->opt_clks_cnt; i++) {
> + c = of_clk_get_by_name(np, opt_clk_names[i]);
> + if (IS_ERR(c)) {
> + pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
> + oh->name, opt_clk_names[i]);
> + ret = -EINVAL;
> + }
> + oh->opt_clks[i]._clk = c;
> + oh->opt_clks[i].role = opt_clk_names[i];
> + clk_prepare(oh->opt_clks[i]._clk);
> + }
> + return ret;
> +}
> +
>  /**
>   * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
>   * @oh: struct omap_hwmod *
> @@ -814,13 +872,16 @@ static int _init_interface_clks(struct omap_hwmod *oh)
>   * Called from _init_clocks().  Populates the @oh omap_hwmod_opt_clk
>   * clock pointers.  Returns 0 on success or -EINVAL on error.
>   */
> -static int _init_opt_clks(struct omap_hwmod *oh)
> +static int _init_opt_clks(struct omap_hwmod *oh, struct device_node *np)
>  {
>   struct omap_hwmod_opt_clk *oc;
>   struct clk *c;
>   int i;
>   int ret = 0;
>  
> + if (of_get_property(np, "clocks", NULL))
> + return _init_opt_clks_dt(oh, np);
> +
>   for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
>   c = clk_get(NULL, oc->clk);
>   if (IS_ERR(c)) {
> @@ -1590,7 +1651,7 @@ static int _init_clocks(struct omap_hwmod *oh, void 
> *data,
>  
>   ret |= _init_main_clk(oh, np);
>   ret |= _init_interface_clks(oh);
> - ret |= _init_opt_clks(oh);
> + ret |= _init_opt_clks(oh, np);
>  
>   if (!ret)
>   oh->_state = _HWMOD_STATE_CLKS_INITED;
> 


-- 
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Nishanth Menon
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Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Russell King - ARM Linux]

On Tue, Jan 07, 2014 at 05:21:11PM -0800, Tony Lindgren wrote:
> * Russell King - ARM Linux  [140102 07:11]:
> > The following patch series moves code to setup the DMA hardware and
> > service interrupts from the hardware to the DMA engine driver.  This
> > reduces the dependency on the legacy DMA implementation.
> > 
> > This series does not remove the channel allocation/freeing hooks which
> > are used to manage the allocation of physical channels - this is the
> > next step in the evolution.
> > 
> > The patches which move the interrupt handling are currently less than
> > perfect since they're writing to ENABLE_L0 under a different spinlock,
> > and hence RFC only at the moment.
> 
> Nice to see this happening. These seem to work for me based on a quick
> try on omap2+, but on omap1 the build fails:
> 
> arch/arm/mach-omap1/dma.c: In function ‘dma_write’:
> arch/arm/mach-omap1/dma.c:186: error: ‘const struct omap_dma_reg’ has no 
> member named ‘size’

Right, needs this incremental patch:

diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3afde9628839..404f89e3eeb8 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -183,7 +183,7 @@ static inline void dma_write(u32 val, int reg, int lch)
addr += reg_map[reg].stride * lch;
 
__raw_writew(val, addr);
-   if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+   if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
__raw_writew(val >> 16, addr + 2);
 }
 
@@ -196,7 +196,7 @@ static inline u32 dma_read(int reg, int lch)
addr += reg_map[reg].stride * lch;
 
val = __raw_readw(addr);
-   if (reg_map[reg].size == OMAP_DMA_REG_2X16BIT)
+   if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
val |= __raw_readw(addr + 2) << 16;
 
return val;


-- 
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in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
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Re: [PATCH v8 1/7] mmc: omap_hsmmc: use devm_regulator API

[Felipe Balbi]

Hi,

On Thu, Jan 09, 2014 at 08:20:56PM +0530, Balaji T K wrote:
> Use devm_regulator API, while at it use
> devm_regulator_get_optional for optional vmmc_aux supply
> 
> Signed-off-by: Balaji T K 
> Acked-by: Tony Lindgren 
> ---
>  drivers/mmc/host/omap_hsmmc.c |6 ++
>  1 files changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index dbd32ad..1eb4350 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -316,7 +316,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
> *host)
>   struct regulator *reg;
>   int ocr_value = 0;
>  
> - reg = regulator_get(host->dev, "vmmc");
> + reg = devm_regulator_get(host->dev, "vmmc");
>   if (IS_ERR(reg)) {
>   dev_err(host->dev, "vmmc regulator missing\n");
>   return PTR_ERR(reg);
> @@ -336,7 +336,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
> *host)
>   }
>  
>   /* Allow an aux regulator */
> - reg = regulator_get(host->dev, "vmmc_aux");
> + reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
>   host->vcc_aux = IS_ERR(reg) ? NULL : reg;
>  
>   /* For eMMC do not power off when not in sleep state */
> @@ -366,8 +366,6 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
> *host)
>  
>  static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)

since this function does nothing now, you could pretty much remove it
and move set_power assignment to ->remove() directly. No strong feelings
though.

-- 
balbi


signature.asc
Description: Digital signature

[PATCH v8 6/7] ARM: OMAP: enable SYSCON and REGULATOR_PBIAS in omap2plus_defconfig

[Balaji T K]

Enable REGULATOR_PBIAS needed for SD card on most OMAPs.

Signed-off-by: Balaji T K 
---
 arch/arm/configs/omap2plus_defconfig |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/omap2plus_defconfig 
b/arch/arm/configs/omap2plus_defconfig
index bfa80a1..f67baa9 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -169,6 +169,7 @@ CONFIG_DRA752_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_OMAP_WATCHDOG=y
 CONFIG_TWL4030_WATCHDOG=y
+CONFIG_MFD_SYSCON=y
 CONFIG_MFD_PALMAS=y
 CONFIG_MFD_TPS65217=y
 CONFIG_MFD_TPS65910=y
@@ -180,6 +181,7 @@ CONFIG_REGULATOR_TPS6507X=y
 CONFIG_REGULATOR_TPS65217=y
 CONFIG_REGULATOR_TPS65910=y
 CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_PBIAS=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MODE_HELPERS=y
-- 
1.7.5.4

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[PATCH v8 2/7] mmc: omap_hsmmc: handle vcc and vcc_aux independently

[Balaji T K]

handle vcc and vcc_aux independently to reduce indent.

Signed-off-by: Balaji T K 
Acked-by: Tony Lindgren 
---
 drivers/mmc/host/omap_hsmmc.c |   54 +++--
 1 files changed, 25 insertions(+), 29 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 1eb4350..342be25 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -286,11 +286,12 @@ static int omap_hsmmc_set_power(struct device *dev, int 
slot, int power_on,
 * chips/cards need an interface voltage rail too.
 */
if (power_on) {
-   ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
+   if (host->vcc)
+   ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
/* Enable interface voltage rail, if needed */
if (ret == 0 && host->vcc_aux) {
ret = regulator_enable(host->vcc_aux);
-   if (ret < 0)
+   if (ret < 0 && host->vcc)
ret = mmc_regulator_set_ocr(host->mmc,
host->vcc, 0);
}
@@ -298,7 +299,7 @@ static int omap_hsmmc_set_power(struct device *dev, int 
slot, int power_on,
/* Shut down the rail */
if (host->vcc_aux)
ret = regulator_disable(host->vcc_aux);
-   if (!ret) {
+   if (host->vcc) {
/* Then proceed to shut down the local regulator */
ret = mmc_regulator_set_ocr(host->mmc,
host->vcc, 0);
@@ -318,10 +319,10 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
*host)
 
reg = devm_regulator_get(host->dev, "vmmc");
if (IS_ERR(reg)) {
-   dev_err(host->dev, "vmmc regulator missing\n");
+   dev_err(host->dev, "unable to get vmmc regulator %ld\n",
+   PTR_ERR(reg));
return PTR_ERR(reg);
} else {
-   mmc_slot(host).set_power = omap_hsmmc_set_power;
host->vcc = reg;
ocr_value = mmc_regulator_get_ocrmask(reg);
if (!mmc_slot(host).ocr_mask) {
@@ -334,31 +335,26 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host 
*host)
return -EINVAL;
}
}
+   }
+   mmc_slot(host).set_power = omap_hsmmc_set_power;
 
-   /* Allow an aux regulator */
-   reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
-   host->vcc_aux = IS_ERR(reg) ? NULL : reg;
+   /* Allow an aux regulator */
+   reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
+   host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 
-   /* For eMMC do not power off when not in sleep state */
-   if (mmc_slot(host).no_regulator_off_init)
-   return 0;
-   /*
-   * UGLY HACK:  workaround regulator framework bugs.
-   * When the bootloader leaves a supply active, it's
-   * initialized with zero usecount ... and we can't
-   * disable it without first enabling it.  Until the
-   * framework is fixed, we need a workaround like this
-   * (which is safe for MMC, but not in general).
-   */
-   if (regulator_is_enabled(host->vcc) > 0 ||
-   (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
-   int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
+   /* For eMMC do not power off when not in sleep state */
+   if (mmc_slot(host).no_regulator_off_init)
+   return 0;
+   /*
+* To disable boot_on regulator, enable regulator
+* to increase usecount and then disable it.
+*/
+   if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
+   (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
+   int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 
-   mmc_slot(host).set_power(host->dev, host->slot_id,
-1, vdd);
-   mmc_slot(host).set_power(host->dev, host->slot_id,
-0, 0);
-   }
+   mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
+   mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
}
 
return 0;
-- 
1.7.5.4

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[PATCH v8 7/7] mmc: omap_hsmmc: remove pbias workaround

[Balaji T K]

remove pbias workaround

Signed-off-by: Balaji T K 
Acked-by: Tony Lindgren 
---
 drivers/mmc/host/omap_hsmmc.c |   20 +---
 1 files changed, 1 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 0a390f8..0f0aa5d 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -170,7 +170,6 @@ struct omap_hsmmc_host {
struct  regulator   *vcc_aux;
struct  regulator   *pbias;
boolpbias_enabled;
-   int pbias_disable;
void__iomem *base;
resource_size_t mapbase;
spinlock_t  irq_lock; /* Prevent races with irq handler */
@@ -267,13 +266,6 @@ static int omap_hsmmc_set_power(struct device *dev, int 
slot, int power_on,
 */
if (!host->vcc)
return 0;
-   /*
-* With DT, never turn OFF the regulator for MMC1. This is because
-* the pbias cell programming support is still missing when
-* booting with Device tree
-*/
-   if (host->pbias_disable && !vdd)
-   return 0;
 
if (mmc_slot(host).before_set_reg)
mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
@@ -1541,13 +1533,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, 
struct mmc_ios *ios)
 * of external transceiver; but they all handle 1.8V.
 */
if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
-   (ios->vdd == DUAL_VOLT_OCR_BIT) &&
-   /*
-* With pbias cell programming missing, this
-* can't be allowed on MMC1 when booting with device
-* tree.
-*/
-   !host->pbias_disable) {
+   (ios->vdd == DUAL_VOLT_OCR_BIT)) {
/*
 * The mmc_select_voltage fn of the core does
 * not seem to set the power_mode to
@@ -1880,10 +1866,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
omap_hsmmc_context_save(host);
 
-   /* This can be removed once we support PBIAS with DT */
-   if (host->dev->of_node && res->start == 0x4809c000)
-   host->pbias_disable = 1;
-
host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
/*
 * MMC can still work without debounce clock.
-- 
1.7.5.4

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[PATCH v8 3/7] regulator: add pbias regulator support

[Balaji T K]

pbias register controls internal power supply to sd card i/o pads
in most OMAPs (OMAP2-5, DRA7).
Control bits for selecting voltage level and
enabling/disabling are in the same PBIAS register.

Signed-off-by: Balaji T K 
Acked-by: Tony Lindgren 
---
 .../bindings/regulator/pbias-regulator.txt |   27 ++
 drivers/regulator/Kconfig  |9 +
 drivers/regulator/Makefile |1 +
 drivers/regulator/pbias-regulator.c|  261 
 4 files changed, 298 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/pbias-regulator.txt
 create mode 100644 drivers/regulator/pbias-regulator.c

diff --git a/Documentation/devicetree/bindings/regulator/pbias-regulator.txt 
b/Documentation/devicetree/bindings/regulator/pbias-regulator.txt
new file mode 100644
index 000..d9342f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/pbias-regulator.txt
@@ -0,0 +1,27 @@
+PBIAS internal regulator for SD card dual voltage i/o pads on OMAP SoCs.
+
+Required properties:
+- compatible:
+  - "ti,pbias-omap" for OMAP2, OMAP3, OMAP4, OMAP5, DRA7.
+- reg: pbias register offset from syscon base and size of pbias register.
+- regulator-name : should be
+   pbias_mmc_omap2430 for OMAP2430, OMAP3 SoCs
+   pbias_sim_omap3 for OMAP3 SoCs
+   pbias_mmc_omap4 for OMAP4 SoCs
+   pbias_mmc_omap5 for OMAP5 and DRA7 SoC
+
+pbias_regulator node should be a child of syscon node (system control module)
+
+Optional properties:
+- Any optional property defined in bindings/regulator/regulator.txt
+
+Example:
+
+   pbias_regulator: pbias_regulator {
+   compatible = "ti,pbias-omap";
+   reg = <0 0x4>;
+   pbias_mmc_reg: pbias_mmc_omap5 {
+   regulator-name = "pbias_mmc_omap5";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <300>;
+   };
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index ce785f4..741e8fb 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -369,6 +369,15 @@ config REGULATOR_PALMAS
  on the muxing. This is handled automatically in the driver by
  reading the mux info from OTP.
 
+config REGULATOR_PBIAS
+   tristate "PBIAS OMAP regulator driver"
+   depends on (ARCH_OMAP || COMPILE_TEST) && MFD_SYSCON
+   help
+Say y here to support pbias regulator for mmc1:SD card i/o
+on OMAP SoCs.
+This driver provides support for OMAP pbias modelled
+regulators.
+
 config REGULATOR_PCAP
tristate "Motorola PCAP2 regulator driver"
depends on EZX_PCAP
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 01c597e..16000fa 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_REGULATOR_MC13XXX_CORE) +=  
mc13xxx-regulator-core.o
 obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
 obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
 obj-$(CONFIG_REGULATOR_TPS51632) += tps51632-regulator.o
+obj-$(CONFIG_REGULATOR_PBIAS) += pbias-regulator.o
 obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
 obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
 obj-$(CONFIG_REGULATOR_RC5T583)  += rc5t583-regulator.o
diff --git a/drivers/regulator/pbias-regulator.c 
b/drivers/regulator/pbias-regulator.c
new file mode 100644
index 000..811983d
--- /dev/null
+++ b/drivers/regulator/pbias-regulator.c
@@ -0,0 +1,261 @@
+/*
+ * pbias-regulator.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Balaji T K 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct pbias_reg_info {
+   u32 enable;
+   u32 enable_mask;
+   u32 vmode;
+   unsigned int enable_time;
+   char *name;
+};
+
+struct pbias_regulator_data {
+   struct regulator_desc desc;
+   void __iomem *pbias_addr;
+   unsigned int pbias_reg;
+   struct regulator_dev *dev;
+   struct regmap *syscon;
+   const struct pbias_reg_info *info;
+   int voltage;
+};
+
+static int pbias_regulator_set_voltage(struct regulator_dev *dev,

[PATCH v8 4/7] mmc: omap_hsmmc: adapt hsmmc to use pbias regulator

[Balaji T K]

In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.

Signed-off-by: Balaji T K 
---
 drivers/mmc/host/omap_hsmmc.c |   39 +++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 342be25..0a390f8 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -126,6 +126,10 @@
 #define OMAP_MMC_MAX_CLOCK 5200
 #define DRIVER_NAME"omap_hsmmc"
 
+#define VDD_1V8180 /* 18 uV */
+#define VDD_3V0300 /* 30 uV */
+#define VDD_165_195(ffs(MMC_VDD_165_195) - 1)
+
 /*
  * One controller can have multiple slots, like on some omap boards using
  * omap.c controller driver. Luckily this is not currently done on any known
@@ -164,6 +168,8 @@ struct omap_hsmmc_host {
 */
struct  regulator   *vcc;
struct  regulator   *vcc_aux;
+   struct  regulator   *pbias;
+   boolpbias_enabled;
int pbias_disable;
void__iomem *base;
resource_size_t mapbase;
@@ -272,6 +278,15 @@ static int omap_hsmmc_set_power(struct device *dev, int 
slot, int power_on,
if (mmc_slot(host).before_set_reg)
mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 
+   if (host->pbias) {
+   if (host->pbias_enabled == 1) {
+   ret = regulator_disable(host->pbias);
+   if (!ret)
+   host->pbias_enabled = 0;
+   }
+   regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
+   }
+
/*
 * Assume Vcc regulator is used only to power the card ... OMAP
 * VDDS is used to power the pins, optionally with a transceiver to
@@ -306,9 +321,29 @@ static int omap_hsmmc_set_power(struct device *dev, int 
slot, int power_on,
}
}
 
+   if (host->pbias) {
+   if (vdd <= VDD_165_195)
+   ret = regulator_set_voltage(host->pbias, VDD_1V8,
+   VDD_1V8);
+   else
+   ret = regulator_set_voltage(host->pbias, VDD_3V0,
+   VDD_3V0);
+   if (ret < 0)
+   goto error_set_power;
+
+   if (host->pbias_enabled == 0) {
+   ret = regulator_enable(host->pbias);
+   if (!ret) {
+   host->pbias_enabled = 1;
+   goto error_set_power;
+   }
+   }
+   }
+
if (mmc_slot(host).after_set_reg)
mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 
+error_set_power:
return ret;
 }
 
@@ -342,6 +377,9 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 
+   reg = devm_regulator_get_optional(host->dev, "pbias");
+   host->pbias = IS_ERR(reg) ? NULL : reg;
+
/* For eMMC do not power off when not in sleep state */
if (mmc_slot(host).no_regulator_off_init)
return 0;
@@ -1808,6 +1846,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
host->base  = ioremap(host->mapbase, SZ_4K);
host->power_mode = MMC_POWER_OFF;
host->next_data.cookie = 1;
+   host->pbias_enabled = 0;
 
platform_set_drvdata(pdev, host);
 
-- 
1.7.5.4

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[PATCH v8 0/7] mmc: omap_hsmmc: pbias dt and cleanup

[Balaji T K]

Few cleanups to reduce code indent,
Add pbias_regulator support and adapt omap_hsmmc to use pbias regulator
to configure required voltage on mmc1 pad(SD card) i/o rails on OMAP SoCs.

Balaji T K (7):
  mmc: omap_hsmmc: use devm_regulator API
  mmc: omap_hsmmc: handle vcc and vcc_aux independently
  regulator: add pbias regulator support
  mmc: omap_hsmmc: adapt hsmmc to use pbias regulator
  ARM: dts: add pbias dt node
  ARM: OMAP: enable SYSCON and REGULATOR_PBIAS in omap2plus_defconfig
  mmc: omap_hsmmc: remove pbias workaround

 .../bindings/regulator/pbias-regulator.txt |   27 ++
 arch/arm/boot/dts/dra7.dtsi|   18 ++
 arch/arm/boot/dts/omap2430.dtsi|   18 ++
 arch/arm/boot/dts/omap3.dtsi   |   18 ++
 arch/arm/boot/dts/omap4.dtsi   |   18 ++
 arch/arm/boot/dts/omap5.dtsi   |   18 ++
 arch/arm/configs/omap2plus_defconfig   |2 +
 drivers/mmc/host/omap_hsmmc.c  |  113 +
 drivers/regulator/Kconfig  |9 +
 drivers/regulator/Makefile |1 +
 drivers/regulator/pbias-regulator.c|  261 
 11 files changed, 454 insertions(+), 49 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/regulator/pbias-regulator.txt
 create mode 100644 drivers/regulator/pbias-regulator.c

-- 
1.7.5.4

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[PATCH v8 5/7] ARM: dts: add pbias dt node

[Balaji T K]

Add pbias regulator node as a child of system control
module - syscon.

Signed-off-by: Balaji T K 
Acked-by: Tony Lindgren 
---
 arch/arm/boot/dts/dra7.dtsi |   18 ++
 arch/arm/boot/dts/omap2430.dtsi |   18 ++
 arch/arm/boot/dts/omap3.dtsi|   18 ++
 arch/arm/boot/dts/omap4.dtsi|   18 ++
 arch/arm/boot/dts/omap5.dtsi|   18 ++
 5 files changed, 90 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..9974bde 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -110,6 +110,23 @@
ti,hwmods = "counter_32k";
};
 
+   dra7_ctrl_general: tisyscon@4a002e00 {
+   compatible = "syscon", "simple-bus";
+   reg = <0x4a002e00 0x7c>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   pbias_regulator: pbias_regulator {
+   compatible = "ti,pbias-omap";
+   reg = <0 0x4>;
+   pbias_mmc_reg: pbias_mmc_omap5 {
+   regulator-name = "pbias_mmc_omap5";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <300>;
+   };
+   };
+   };
+
dra7_pmx_core: pinmux@4a003400 {
compatible = "pinctrl-single";
reg = <0x4a003400 0x0464>;
@@ -485,6 +502,7 @@
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
status = "disabled";
+   pbias-supply = <&pbias_mmc_reg>;
};
 
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345..5ec3638 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,23 @@
pinctrl-single,function-mask = <0x3f>;
};
 
+   omap2_scm_general: tisyscon@49002270 {
+   compatible = "syscon", "simple-bus";
+   reg = <0x49002270 0x240>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   pbias_regulator: pbias_regulator {
+   compatible = "ti,pbias-omap";
+   reg = <0x230 0x4>;
+   pbias_mmc_reg: pbias_mmc_omap2430 {
+   regulator-name = "pbias_mmc_omap2430";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <300>;
+   };
+   };
+   };
+
gpio1: gpio@4900c000 {
compatible = "ti,omap2-gpio";
reg = <0x4900c000 0x200>;
@@ -183,6 +200,7 @@
ti,dual-volt;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
+   pbias-supply = <&pbias_mmc_reg>;
};
 
mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index daabf99..0f50990 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -137,6 +137,23 @@
pinctrl-single,function-mask = <0xff1f>;
};
 
+   omap3_scm_general: tisyscon@48002270 {
+   compatible = "syscon", "simple-bus";
+   reg = <0x48002270 0x2f0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   pbias_regulator: pbias_regulator {
+   compatible = "ti,pbias-omap";
+   reg = <0x2b0 0x4>;
+   pbias_mmc_reg: pbias_mmc_omap2430 {
+   regulator-name = "pbias_mmc_omap2430";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <300>;
+   };
+   };
+   };
+
gpio1: gpio@4831 {
compatible = "ti,omap3-gpio";
reg = <0x4831 0x200>;
@@ -351,6 +368,7 @@
ti,dual-volt;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
+  

[PATCH v8 1/7] mmc: omap_hsmmc: use devm_regulator API

[Balaji T K]

Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply

Signed-off-by: Balaji T K 
Acked-by: Tony Lindgren 
---
 drivers/mmc/host/omap_hsmmc.c |6 ++
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index dbd32ad..1eb4350 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -316,7 +316,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
struct regulator *reg;
int ocr_value = 0;
 
-   reg = regulator_get(host->dev, "vmmc");
+   reg = devm_regulator_get(host->dev, "vmmc");
if (IS_ERR(reg)) {
dev_err(host->dev, "vmmc regulator missing\n");
return PTR_ERR(reg);
@@ -336,7 +336,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
}
 
/* Allow an aux regulator */
-   reg = regulator_get(host->dev, "vmmc_aux");
+   reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 
/* For eMMC do not power off when not in sleep state */
@@ -366,8 +366,6 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 
 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 {
-   regulator_put(host->vcc);
-   regulator_put(host->vcc_aux);
mmc_slot(host).set_power = NULL;
 }
 
-- 
1.7.5.4

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[PATCHv13 38/40] ARM: AM43xx: Enable clock init

[Tero Kristo]

Initializes clock data from device tree.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-omap2/io.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 44fc8cd..bbd2959 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -606,6 +606,7 @@ void __init am43xx_init_early(void)
am43xx_clockdomains_init();
am43xx_hwmod_init();
omap_hwmod_init_postsetup();
+   omap_clk_soc_init = am43xx_dt_clk_init;
 }
 
 void __init am43xx_init_late(void)
-- 
1.7.9.5

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[PATCHv13 39/40] ARM: AM33xx: remove old clock data and link in new clock init code

[Tero Kristo]

AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/Makefile  |1 -
 arch/arm/mach-omap2/cclock33xx_data.c | 1064 -
 arch/arm/mach-omap2/io.c  |2 +-
 3 files changed, 1 insertion(+), 1066 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e9d63ec..088305f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -189,7 +189,6 @@ obj-$(CONFIG_ARCH_OMAP3)+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)   += $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)   += dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)   += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)   += cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)+= $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)+= dpll3xxx.o dpll44xx.o
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c 
b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30e..000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath 
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_1920_ck, CLK_IS_ROOT, 1920, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_2400_ck, CLK_IS_ROOT, 2400, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_2500_ck, CLK_IS_ROOT, 2500, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_2600_ck, CLK_IS_ROOT, 2600, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-   "virt_1920_ck", "virt_2400_ck", "virt_2500_ck",
-   "virt_2600_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-  AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-  AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-  AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-  0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 1200, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-   .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
-   .clk_bypass = &sys_clkin_ck,
-   .clk_ref= &sys_clkin_ck,
-   .control_reg= AM33XX_CM_CLKMODE_DPLL_CORE,
-   .modes  = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-   .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
-   .mult_mask  = AM33XX_DPLL_MULT_MASK,
-   .div1_mask  = AM33XX_DPLL_DIV_MASK,
-   .enable_mask= AM33XX_DPLL_EN_MASK,
-   .idlest_mask= AM33XX_ST_DPLL_CLK_MASK,
-   .max_multiplier = 2047,
-   .max_divider= 128,
-   .min_divider= 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-   "sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-   .recalc_rate= &omap3_dpll_recalc,
-   .get_parent = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-   .hw = {
-   .clk= &dpll_core_ck,
-   },
-   .dpll_data  = &dpll_core_dd,
-   .ops= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-   "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpl

[PATCHv13 40/40] ARM: OMAP3: use DT clock init if DT data is available

[Tero Kristo]

OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/io.c |   13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f28399f..b8097fe 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
 void __init omap3430_init_early(void)
 {
omap3_init_early();
+   if (of_have_populated_dt())
+   omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap35xx_init_early(void)
 {
omap3_init_early();
+   if (of_have_populated_dt())
+   omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap3630_init_early(void)
 {
omap3_init_early();
+   if (of_have_populated_dt())
+   omap_clk_soc_init = omap3630_dt_clk_init;
 }
 
 void __init am35xx_init_early(void)
 {
omap3_init_early();
+   if (of_have_populated_dt())
+   omap_clk_soc_init = am35xx_dt_clk_init;
 }
 
 void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_soc_init = omap3xxx_clk_init;
+   if (of_have_populated_dt())
+   omap_clk_soc_init = ti81xx_dt_clk_init;
+   else
+   omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
-- 
1.7.9.5

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[PATCHv13 34/40] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT

[Tero Kristo]

This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-omap2/prm.h|1 +
 arch/arm/mach-omap2/prm_common.c |   66 ++
 2 files changed, 67 insertions(+)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6..623db40 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
 # endif
 
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174..b4c4ab9 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
 
 #include "soc.h"
 #include "prm2xxx_3xxx.h"
@@ -30,6 +34,7 @@
 #include "prm3xxx.h"
 #include "prm44xx.h"
 #include "common.h"
+#include "clock.h"
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
 
return 0;
 }
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+   { .compatible = "ti,am3-prcm" },
+   { .compatible = "ti,am3-scrm" },
+   { .compatible = "ti,am4-prcm" },
+   { .compatible = "ti,am4-scrm" },
+   { .compatible = "ti,omap3-prm" },
+   { .compatible = "ti,omap3-cm" },
+   { .compatible = "ti,omap3-scrm" },
+   { .compatible = "ti,omap4-cm1" },
+   { .compatible = "ti,omap4-prm" },
+   { .compatible = "ti,omap4-cm2" },
+   { .compatible = "ti,omap4-scrm" },
+   { .compatible = "ti,omap5-prm" },
+   { .compatible = "ti,omap5-cm-core-aon" },
+   { .compatible = "ti,omap5-scrm" },
+   { .compatible = "ti,omap5-cm-core" },
+   { .compatible = "ti,dra7-prm" },
+   { .compatible = "ti,dra7-cm-core-aon" },
+   { .compatible = "ti,dra7-cm-core" },
+   { }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+   .flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(void __iomem *reg)
+{
+   return omap2_clk_readl(&memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, void __iomem *reg)
+{
+   omap2_clk_writel(val, &memmap_dummy_ck, reg);
+}
+
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
+   .clk_readl = prm_clk_readl,
+   .clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+   struct device_node *np;
+   void __iomem *mem;
+   int memmap_index = 0;
+
+   ti_clk_ll_ops = &omap_clk_ll_ops;
+
+   for_each_matching_node(np, omap_prcm_dt_match_table) {
+   mem = of_iomap(np, 0);
+   clk_memmaps[memmap_index] = mem;
+   ti_dt_clk_init_provider(np, memmap_index);
+   memmap_index++;
+   }
+
+   ti_dt_clockdomains_setup();
+
+   return 0;
+}
-- 
1.7.9.5

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[PATCHv13 31/40] ARM: OMAP2+: clock: use driver API instead of direct memory read/write

[Tero Kristo]

Clock nodes shall use the services provided by underlying drivers to access
the hardware registers instead of direct memory read/write. Thus, change
all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-omap2/clkt_clksel.c |   10 +-
 arch/arm/mach-omap2/clkt_dpll.c   |6 +++---
 arch/arm/mach-omap2/clkt_iclk.c   |   20 
 arch/arm/mach-omap2/clock.c   |   25 +
 arch/arm/mach-omap2/clock36xx.c   |7 ---
 arch/arm/mach-omap2/dpll3xxx.c|   37 -
 arch/arm/mach-omap2/dpll44xx.c|   12 ++--
 7 files changed, 63 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt_clksel.c 
b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6f..7ee2610 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 
field_val)
 {
u32 v;
 
-   v = __raw_readl(clk->clksel_reg);
+   v = omap2_clk_readl(clk, clk->clksel_reg);
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
-   __raw_writel(v, clk->clksel_reg);
+   omap2_clk_writel(v, clk, clk->clksel_reg);
 
-   v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+   v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
 }
 
 /**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
if (!clk->clksel || !clk->clksel_mask)
return 0;
 
-   v = __raw_readl(clk->clksel_reg);
+   v = omap2_clk_readl(clk, clk->clksel_reg);
v &= clk->clksel_mask;
v >>= __ffs(clk->clksel_mask);
 
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
WARN((!clk->clksel || !clk->clksel_mask),
 "clock: %s: attempt to call on a non-clksel clock", clk_name);
 
-   r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+   r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
 
for (clks = clk->clksel; clks->parent && !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230..47f9562 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
if (!dd)
return -EINVAL;
 
-   v = __raw_readl(dd->control_reg);
+   v = omap2_clk_readl(clk, dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
 
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
return 0;
 
/* Return bypass rate if DPLL is bypassed */
-   v = __raw_readl(dd->control_reg);
+   v = omap2_clk_readl(clk, dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
 
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
return __clk_get_rate(dd->clk_bypass);
}
 
-   v = __raw_readl(dd->mult_div1_reg);
+   v = omap2_clk_readl(clk, dd->mult_div1_reg);
dpll_mult = v & dd->mult_mask;
dpll_mult >>= __ffs(dd->mult_mask);
dpll_div = v & dd->div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03..333f0a6 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -25,25 +25,29 @@
 /* XXX */
 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
 {
-   u32 v, r;
+   u32 v;
+   void __iomem *r;
 
-   r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+   r = (__force void __iomem *)
+   ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-   v = __raw_readl((__force void __iomem *)r);
+   v = omap2_clk_readl(clk, r);
v |= (1 << clk->enable_bit);
-   __raw_writel(v, (__force void __iomem *)r);
+   omap2_clk_writel(v, clk, r);
 }
 
 /* XXX */
 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
 {
-   u32 v, r;
+   u32 v;
+   void __iomem *r;
 
-   r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+   r = (__force void __iomem *)
+   ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-   v = __raw_readl((__force void __iomem *)r);
+   v = omap2_clk_readl(clk, r);
v &= ~(1 << clk->enable_bit);
-   __raw_writel(v, (__force void __iomem *)r);
+   omap2_clk_writel(v, clk, r);
 }
 
 /* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index be53bb2..591581a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -111,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 
 /**
  * _wait_idlest_generic - wait for a module to leave the idle state
+ * @clk: module c

[PATCHv13 35/40] ARM: OMAP2+: io: use new clock init API

[Tero Kristo]

clk_init is now separated to a common function which gets called for all
SoC:s, which initializes the DT clocks and calls the SoC specific clock init.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-omap2/common.h |2 +-
 arch/arm/mach-omap2/io.c |   32 +++-
 arch/arm/mach-omap2/timer.c  |6 ++
 3 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index e30ef67..5ccf36d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -305,7 +305,7 @@ struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
 /* SoC specific clock initializer */
-extern int (*omap_clk_init)(void);
+int omap_clk_init(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3d9b3fc..8517a62 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,10 +55,10 @@
 #include "prm44xx.h"
 
 /*
- * omap_clk_init: points to a function that does the SoC-specific
+ * omap_clk_soc_init: points to a function that does the SoC-specific
  * clock initializations
  */
-int (*omap_clk_init)(void);
+static int (*omap_clk_soc_init)(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -419,7 +419,7 @@ void __init omap2420_init_early(void)
omap242x_clockdomains_init();
omap2420_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = omap2420_clk_init;
+   omap_clk_soc_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
@@ -448,7 +448,7 @@ void __init omap2430_init_early(void)
omap243x_clockdomains_init();
omap2430_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = omap2430_clk_init;
+   omap_clk_soc_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
@@ -482,7 +482,7 @@ void __init omap3_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = omap3xxx_clk_init;
+   omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
@@ -520,7 +520,7 @@ void __init ti81xx_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = omap3xxx_clk_init;
+   omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
@@ -581,7 +581,7 @@ void __init am33xx_init_early(void)
am33xx_clockdomains_init();
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = am33xx_clk_init;
+   omap_clk_soc_init = am33xx_clk_init;
 }
 
 void __init am33xx_init_late(void)
@@ -635,7 +635,7 @@ void __init omap4430_init_early(void)
omap44xx_clockdomains_init();
omap44xx_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = omap4xxx_clk_init;
+   omap_clk_soc_init = omap4xxx_clk_init;
 }
 
 void __init omap4430_init_late(void)
@@ -666,7 +666,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
-   omap_clk_init = omap5xxx_dt_clk_init;
+   omap_clk_soc_init = omap5xxx_dt_clk_init;
 }
 
 void __init omap5_init_late(void)
@@ -711,3 +711,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params 
*sdrc_cs0,
_omap2_init_reprogram_sdrc();
}
 }
+
+int __init omap_clk_init(void)
+{
+   int ret = 0;
+
+   if (!omap_clk_soc_init)
+   return 0;
+
+   ret = of_prcm_init();
+   if (!ret)
+   ret = omap_clk_soc_init();
+
+   return ret;
+}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3ca81e0..60e5fc9 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void)
   clksrc_nr, clksrc_src, clksrc_prop)  \
 void __init omap##name##_gptimer_timer_init(void)  \
 {  \
-   if (omap_clk_init)  \
-   omap_clk_init();\
+   omap_clk_init();\
omap_dmtimer_init();\
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);\
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
@@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void)   
\
clksrc_nr, clksrc_src, clksrc_prop) \
 void __init omap##name##_sync32k_timer_init(void)  \
 {  \

[PATCHv13 33/40] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name

[Tero Kristo]

DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.

Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.

This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/omap_hwmod.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cc24c95..433fe2f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1578,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
if (!oh->clkdm) {
pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
oh->name, oh->clkdm_name);
-   return -EINVAL;
+   return 0;
}
 
pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4237,6 +4237,7 @@ void __init omap_hwmod_init(void)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+   soc_ops.init_clkdm = _init_clkdm;
} else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
-- 
1.7.9.5

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[PATCHv13 29/40] ARM: dts: am43xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo 
---
 arch/arm/boot/dts/am4372.dtsi|   28 ++
 arch/arm/boot/dts/am43xx-clocks.dtsi |  656 ++
 2 files changed, 684 insertions(+)
 create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103..c6bd4d9 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,6 +67,32 @@
ranges;
ti,hwmods = "l3_main";
 
+   prcm: prcm@44df {
+   compatible = "ti,am4-prcm";
+   reg = <0x44df 0x11000>;
+
+   prcm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   prcm_clockdomains: clockdomains {
+   };
+   };
+
+   scrm: scrm@44e1 {
+   compatible = "ti,am4-scrm";
+   reg = <0x44e1 0x2000>;
+
+   scrm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   scrm_clockdomains: clockdomains {
+   };
+   };
+
edma: edma@4900 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
@@ -665,3 +691,5 @@
};
};
 };
+
+/include/ "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi 
b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 000..142009c
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+   sys_clkin_ck: sys_clkin_ck {
+   #clock-cells = <0>;
+   compatible = "ti,mux-clock";
+   clocks = <&virt_1920_ck>, <&virt_2400_ck>, 
<&virt_2500_ck>, <&virt_2600_ck>;
+   ti,bit-shift = <22>;
+   reg = <0x0040>;
+   };
+
+   adc_tsc_fck: adc_tsc_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   dcan0_fck: dcan0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   dcan1_fck: dcan1_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   mcasp0_fck: mcasp0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   mcasp1_fck: mcasp1_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   smartreflex0_fck: smartreflex0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   smartreflex1_fck: smartreflex1_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   sha0_fck: sha0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   aes0_fck: aes0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+};
+&prcm_clocks {
+   clk_32768_ck: clk_32768_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   };
+
+   clk_rc32k_ck: clk_rc32k_ck {
+   #clock-

[PATCHv13 32/40] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm

[Tero Kristo]

If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/omap_hwmod.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8a1b5e0..cc24c95 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
if (oh->clkdm) {
return oh->clkdm;
} else if (oh->_clk) {
+   if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+   return NULL;
clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
return  clk->clkdm;
}
-- 
1.7.9.5

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[PATCHv13 22/40] ARM: dts: dra7 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo 
---
 arch/arm/boot/dts/dra7.dtsi  |   41 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 1985 ++
 2 files changed, 2026 insertions(+)
 create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..1fd75aa 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -104,6 +104,45 @@
interrupts = ,
 ;
 
+   prm: prm@4ae06000 {
+   compatible = "ti,dra7-prm";
+   reg = <0x4ae06000 0x3000>;
+
+   prm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   prm_clockdomains: clockdomains {
+   };
+   };
+
+   cm_core_aon: cm_core_aon@4a005000 {
+   compatible = "ti,dra7-cm-core-aon";
+   reg = <0x4a005000 0x2000>;
+
+   cm_core_aon_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   cm_core_aon_clockdomains: clockdomains {
+   };
+   };
+
+   cm_core: cm_core@4a008000 {
+   compatible = "ti,dra7-cm-core";
+   reg = <0x4a008000 0x3000>;
+
+   cm_core_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   cm_core_clockdomains: clockdomains {
+   };
+   };
+
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
@@ -584,3 +623,5 @@
};
};
 };
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 000..32df847
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,1985 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+   atl_clkin0_ck: atl_clkin0_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   atl_clkin1_ck: atl_clkin1_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   atl_clkin2_ck: atl_clkin2_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   atlclkin3_ck: atlclkin3_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   hdmi_clkin_ck: hdmi_clkin_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   mlb_clkin_ck: mlb_clkin_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   mlbp_clkin_ck: mlbp_clkin_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <1>;
+   };
+
+   ref_clkin0_ck: ref_clkin0_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   ref_clkin1_ck: ref_clkin1_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   ref_clkin2_ck: ref_clkin2_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   ref_clkin3_ck: ref_clkin3_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   };
+
+   rmii_clk_ck: rmii_clk_ck {
+   #clock-cells = <0>;
+   compatible = "f

[PATCHv13 20/40] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.

Signed-off-by: Tero Kristo 
---
 arch/arm/boot/dts/omap4.dtsi   |   54 ++
 arch/arm/boot/dts/omap443x-clocks.dtsi |   18 +
 arch/arm/boot/dts/omap443x.dtsi|2 +
 arch/arm/boot/dts/omap4460.dtsi|2 +
 arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 1651 
 6 files changed, 1754 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index a1e0585..d3f8a6e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,58 @@
interrupts = ,
 ;
 
+   cm1: cm1@4a004000 {
+   compatible = "ti,omap4-cm1";
+   reg = <0x4a004000 0x2000>;
+
+   cm1_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   cm1_clockdomains: clockdomains {
+   };
+   };
+
+   prm: prm@4a306000 {
+   compatible = "ti,omap4-prm";
+   reg = <0x4a306000 0x3000>;
+
+   prm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   prm_clockdomains: clockdomains {
+   };
+   };
+
+   cm2: cm2@4a008000 {
+   compatible = "ti,omap4-cm2";
+   reg = <0x4a008000 0x3000>;
+
+   cm2_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   cm2_clockdomains: clockdomains {
+   };
+   };
+
+   scrm: scrm@4a30a000 {
+   compatible = "ti,omap4-scrm";
+   reg = <0x4a30a000 0x2000>;
+
+   scrm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   scrm_clockdomains: clockdomains {
+   };
+   };
+
counter32k: counter@4a304000 {
compatible = "ti,omap-counter32k";
reg = <0x4a304000 0x20>;
@@ -707,3 +759,5 @@
};
};
 };
+
+/include/ "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi 
b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 000..2bd2166
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+   bandgap_fclk: bandgap_fclk {
+   #clock-cells = <0>;
+   compatible = "ti,gate-clock";
+   clocks = <&sys_32k_ck>;
+   ti,bit-shift = <8>;
+   reg = <0x1888>;
+   };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..f67e191 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -31,3 +31,5 @@
compatible = "ti,omap4430-bandgap";
};
 };
+
+/include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..1758601 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -39,3 +39,5 @@
gpios = <&gpio3 22 0>; /* tshut */
};
 };
+
+/include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi 
b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 000..be033e9
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+   div_ts_ck: div_ts_ck {
+   #clock-cells = <0>;
+   compatible = "ti,divider-

[PATCHv13 28/40] ARM: dts: AM35xx: use DT clock data

[Tero Kristo]

AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.

Signed-off-by: Tero Kristo 
---
 arch/arm/boot/dts/am3517.dtsi |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 2fbe02f..788391f 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -61,3 +61,6 @@
};
};
 };
+
+/include/ "am35xx-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
-- 
1.7.9.5

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[PATCHv13 24/40] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock

[Tero Kristo]

From: J Keerthy 

This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.

Signed-off-by: J Keerthy 
Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d4e7410..d616359 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1183,13 +1183,10 @@
 
apll_pcie_m2_ck: apll_pcie_m2_ck {
#clock-cells = <0>;
-   compatible = "ti,divider-clock";
+   compatible = "fixed-factor-clock";
clocks = <&apll_pcie_ck>;
-   ti,max-div = <127>;
-   ti,autoidle-shift = <8>;
-   reg = <0x0224>;
-   ti,index-starts-at-one;
-   ti,invert-autoidle-bit;
+   clock-mult = <1>;
+   clock-div = <1>;
};
 
dpll_per_ck: dpll_per_ck {
-- 
1.7.9.5

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[PATCHv13 21/40] ARM: dts: omap5 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo 
---
 arch/arm/boot/dts/omap5.dtsi   |   54 ++
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 1399 
 2 files changed, 1453 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc3fad5..2f12a47 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -107,6 +107,58 @@
interrupts = ,
 ;
 
+   prm: prm@4ae06000 {
+   compatible = "ti,omap5-prm";
+   reg = <0x4ae06000 0x3000>;
+
+   prm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   prm_clockdomains: clockdomains {
+   };
+   };
+
+   cm_core_aon: cm_core_aon@4a004000 {
+   compatible = "ti,omap5-cm-core-aon";
+   reg = <0x4a004000 0x2000>;
+
+   cm_core_aon_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   cm_core_aon_clockdomains: clockdomains {
+   };
+   };
+
+   scrm: scrm@4ae0a000 {
+   compatible = "ti,omap5-scrm";
+   reg = <0x4ae0a000 0x2000>;
+
+   scrm_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   scrm_clockdomains: clockdomains {
+   };
+   };
+
+   cm_core: cm_core@4a008000 {
+   compatible = "ti,omap5-cm-core";
+   reg = <0x4a008000 0x3000>;
+
+   cm_core_clocks: clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   cm_core_clockdomains: clockdomains {
+   };
+   };
+
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
@@ -739,3 +791,5 @@
};
};
 };
+
+/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi 
b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 000..d487fda
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1399 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+   pad_clks_src_ck: pad_clks_src_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <1200>;
+   };
+
+   pad_clks_ck: pad_clks_ck {
+   #clock-cells = <0>;
+   compatible = "ti,gate-clock";
+   clocks = <&pad_clks_src_ck>;
+   ti,bit-shift = <8>;
+   reg = <0x0108>;
+   };
+
+   secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   };
+
+   slimbus_src_clk: slimbus_src_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <1200>;
+   };
+
+   slimbus_clk: slimbus_clk {
+   #clock-cells = <0>;
+   compatible = "ti,gate-clock";
+   clocks = <&slimbus_src_clk>;
+   ti,bit-shift = <10>;
+   reg = <0x0108>;
+   };
+
+   sys_32k_ck: sys_32k_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   };
+
+   virt_1200_ck: virt_1200_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <1200>;
+   };
+
+   virt_1300_ck: virt_1300_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <1300>;
+   };
+
+   virt_1680_ck: virt_1680_ck {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <1680>;
+   };
+
+   virt_1920_ck: virt_1920_ck {
+   #clock

[PATCHv13 30/40] ARM: OMAP2+: clock: add support for indexed memmaps

[Tero Kristo]

Using indexed memmaps is required for isolating the actual memory access
from the clock code. Now, the driver providing the support for the clock IP
block provides the low level routines for reading/writing clock registers
also.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-omap2/clock.c |   26 +-
 arch/arm/mach-omap2/clock.h |5 +
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 238be3f..be53bb2 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
 #include 
 #include 
 
-
 #include 
 
 #include "soc.h"
@@ -56,6 +55,31 @@ u16 cpu_mask;
 static bool clkdm_control = true;
 
 static LIST_HEAD(clk_hw_omap_clocks);
+void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
+{
+   if (clk->flags & MEMMAP_ADDRESSING) {
+   struct clk_omap_reg *r = (struct clk_omap_reg *)®
+   writel_relaxed(val, clk_memmaps[r->index] + r->offset);
+   } else {
+   writel_relaxed(val, reg);
+   }
+}
+
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
+{
+   u32 val;
+
+   if (clk->flags & MEMMAP_ADDRESSING) {
+   struct clk_omap_reg *r = (struct clk_omap_reg *)®
+   val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+   } else {
+   val = readl_relaxed(reg);
+   }
+
+   return val;
+}
 
 /*
  * Used for clocks that have the same value as the parent clock,
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index cbe5ff7..bda767a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -254,6 +254,9 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
   const char *core_ck_name,
   const char *mpu_ck_name);
 
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
+
 extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
@@ -288,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
 
+extern void __iomem *clk_memmaps[];
+
 extern int am33xx_clk_init(void);
 
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-- 
1.7.9.5

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[PATCHv13 37/40] ARM: OMAP: DRA7: Enable clock init

[Tero Kristo]

Initializes clock data from device tree.

Signed-off-by: Tero Kristo 
---
 arch/arm/mach-omap2/io.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c95b836..44fc8cd 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -692,6 +692,7 @@ void __init dra7xx_init_early(void)
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
+   omap_clk_soc_init = dra7xx_dt_clk_init;
 }
 
 void __init dra7xx_init_late(void)
-- 
1.7.9.5

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[PATCHv13 26/40] ARM: dts: am33xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo 
---
 arch/arm/boot/dts/am33xx-clocks.dtsi |  664 ++
 arch/arm/boot/dts/am33xx.dtsi|   28 ++
 2 files changed, 692 insertions(+)
 create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi 
b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 000..9ccfe50
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,664 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+   sys_clkin_ck: sys_clkin_ck {
+   #clock-cells = <0>;
+   compatible = "ti,mux-clock";
+   clocks = <&virt_1920_ck>, <&virt_2400_ck>, 
<&virt_2500_ck>, <&virt_2600_ck>;
+   ti,bit-shift = <22>;
+   reg = <0x0040>;
+   };
+
+   adc_tsc_fck: adc_tsc_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   dcan0_fck: dcan0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   dcan1_fck: dcan1_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   mcasp0_fck: mcasp0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   mcasp1_fck: mcasp1_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   smartreflex0_fck: smartreflex0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   smartreflex1_fck: smartreflex1_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   sha0_fck: sha0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   aes0_fck: aes0_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   rng_fck: rng_fck {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clocks = <&sys_clkin_ck>;
+   clock-mult = <1>;
+   clock-div = <1>;
+   };
+
+   ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+   #clock-cells = <0>;
+   compatible = "ti,composite-no-wait-gate-clock";
+   clocks = <&dpll_per_m2_ck>;
+   ti,bit-shift = <0>;
+   reg = <0x0664>;
+   };
+
+   ehrpwm0_tbclk: ehrpwm0_tbclk {
+   #clock-cells = <0>;
+   compatible = "ti,composite-clock";
+   clocks = <&ehrpwm0_gate_tbclk>;
+   };
+
+   ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+   #clock-cells = <0>;
+   compatible = "ti,composite-no-wait-gate-clock";
+   clocks = <&dpll_per_m2_ck>;
+   ti,bit-shift = <1>;
+   reg = <0x0664>;
+   };
+
+   ehrpwm1_tbclk: ehrpwm1_tbclk {
+   #clock-cells = <0>;
+   compatible = "ti,composite-clock";
+   clocks = <&ehrpwm1_gate_tbclk>;
+   };
+
+   ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+   #clock-cells = <0>;
+   compatible = "ti,composite-no-wait-gate-clock";
+   clocks = <&dpll_per_m2_ck>;
+   ti,bit-shift = <2>;
+   reg = <0x0664>;
+   };
+
+   ehrpwm2_tbclk: ehrpwm2_tbclk {
+   #clock-cells = <0>;
+   compatible = "ti,composite-clock";
+   clocks = <&ehrpwm2_gate_tbclk>;
+   };

[PATCHv13 18/40] CLK: TI: add omap3 clock init file

[Tero Kristo]

clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/clock3xxx.h |1 -
 drivers/clk/ti/Makefile |2 +-
 drivers/clk/ti/clk-3xxx.c   |  401 +++
 include/linux/clk/ti.h  |5 +
 4 files changed, 407 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/ti/clk-3xxx.c

diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
 int omap3xxx_clk_init(void);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
 
 extern struct clk *sdrc_ick_p;
 extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index e42a703..ab386c8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@ obj-y   += clk.o dpll.o 
autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
   composite.o mux.o apll.o
 obj-$(CONFIG_SOC_AM33XX)   += clk-33xx.o
-obj-$(CONFIG_ARCH_OMAP3)   += interface.o
+obj-$(CONFIG_ARCH_OMAP3)   += interface.o clk-3xxx.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
 obj-$(CONFIG_SOC_DRA7XX)   += clk-7xx.o
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 000..d323023
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,401 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+
+static struct ti_dt_clk omap3xxx_clks[] = {
+   DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
+   DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
+   DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
+   DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
+   DT_CLK(NULL, "virt_1920_ck", "virt_1920_ck"),
+   DT_CLK(NULL, "virt_2600_ck", "virt_2600_ck"),
+   DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
+   DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
+   DT_CLK("twl", "fck", "osc_sys_ck"),
+   DT_CLK(NULL, "sys_ck", "sys_ck"),
+   DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
+   DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
+   DT_CLK(NULL, "sys_altclk", "sys_altclk"),
+   DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
+   DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
+   DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
+   DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
+   DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
+   DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
+   DT_CLK(NULL, "core_ck", "core_ck"),
+   DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
+   DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
+   DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
+   DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
+   DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
+   DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
+   DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
+   DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
+   DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
+   DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
+   DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
+   DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
+   DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
+   DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
+   DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
+   DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
+   DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
+   DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
+   DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
+   DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
+   DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
+   DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
+   DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
+   DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
+   DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
+   DT_CLK(NULL

[PATCHv13 25/40] ARM: dts: DRA7: Add PCIe related clock nodes

[Tero Kristo]

From: J Keerthy 

This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: J Keerthy 
Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d616359..e96da9a 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,31 @@
reg = <0x021c>, <0x0220>;
};
 
+   optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+   compatible = "ti,divider-clock";
+   clocks = <&apll_pcie_ck>;
+   #clock-cells = <0>;
+   reg = <0x021c>;
+   ti,bit-shift = <8>;
+   ti,max-div = <2>;
+   };
+
+   optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+   compatible = "ti,gate-clock";
+   clocks = <&apll_pcie_ck>;
+   #clock-cells = <0>;
+   reg = <0x13b0>;
+   ti,bit-shift = <9>;
+   };
+
+   optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+   compatible = "ti,gate-clock";
+   clocks = <&optfclk_pciephy_div>;
+   #clock-cells = <0>;
+   reg = <0x13b0>;
+   ti,bit-shift = <10>;
+   };
+
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
-- 
1.7.9.5

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[PATCHv13 12/40] CLK: TI: add omap5 clock init file

[Tero Kristo]

clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/io.c  |1 +
 drivers/clk/ti/Makefile   |1 +
 drivers/clk/ti/clk-54xx.c |  239 +
 include/linux/clk/ti.h|1 +
 4 files changed, 242 insertions(+)
 create mode 100644 drivers/clk/ti/clk-54xx.c

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cd22262..3d9b3fc 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -666,6 +666,7 @@ void __init omap5_init_early(void)
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
+   omap_clk_init = omap5xxx_dt_clk_init;
 }
 
 void __init omap5_init_late(void)
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 381f1f8..935e5d2 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@ obj-y   += clk.o dpll.o 
autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
   composite.o mux.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
+obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
 endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 000..c876e6e
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,239 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OMAP5_DPLL_ABE_DEFFREQ 98304000
+
+static struct ti_dt_clk omap54xx_clks[] = {
+   DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+   DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+   DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+   DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+   DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+   DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+   DT_CLK(NULL, "virt_1200_ck", "virt_1200_ck"),
+   DT_CLK(NULL, "virt_1300_ck", "virt_1300_ck"),
+   DT_CLK(NULL, "virt_1680_ck", "virt_1680_ck"),
+   DT_CLK(NULL, "virt_1920_ck", "virt_1920_ck"),
+   DT_CLK(NULL, "virt_2600_ck", "virt_2600_ck"),
+   DT_CLK(NULL, "virt_2700_ck", "virt_2700_ck"),
+   DT_CLK(NULL, "virt_3840_ck", "virt_3840_ck"),
+   DT_CLK(NULL, "sys_clkin", "sys_clkin"),
+   DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+   DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+   DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+   DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+   DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+   DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+   DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+   DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+   DT_CLK(NULL, "abe_clk", "abe_clk"),
+   DT_CLK(NULL, "abe_iclk", "abe_iclk"),
+   DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+   DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+   DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+   DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+   DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
+   DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
+   DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
+   DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
+   DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
+   DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
+   DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
+   DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
+   DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
+   DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
+   DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
+   DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+   DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
+   DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
+   DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
+   DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
+   DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
+   DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
+   DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
+   DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+   DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll

[PATCHv13 17/40] CLK: TI: add interface clock support for OMAP3

[Tero Kristo]

OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/interface.txt |   54 +
 arch/arm/mach-omap2/clock.h|5 -
 drivers/clk/ti/Makefile|1 +
 drivers/clk/ti/interface.c |  125 
 include/linux/clk/ti.h |5 +
 5 files changed, 185 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
 create mode 100644 drivers/clk/ti/interface.c

diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt 
b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 000..064e8ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,54 @@
+Binding for Texas Instruments interface clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+  "ti,omap3-interface-clock" - basic OMAP3 interface clock
+  "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
+  capability for waiting clock to be ready
+  "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
+   handling
+  "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW 
handling
+  "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW 
handling
+  "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW 
handling
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
+
+Examples:
+   aes1_ick: aes1_ick@48004a14 {
+   #clock-cells = <0>;
+   compatible = "ti,omap3-interface-clock";
+   clocks = <&security_l4_ick2>;
+   reg = <0x48004a14 0x4>;
+   ti,bit-shift = <3>;
+   };
+
+   cam_ick: cam_ick@48004f10 {
+   #clock-cells = <0>;
+   compatible = "ti,omap3-no-wait-interface-clock";
+   clocks = <&l4_ick>;
+   reg = <0x48004f10 0x4>;
+   ti,bit-shift = <0>;
+   };
+
+   ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+   #clock-cells = <0>;
+   compatible = "ti,omap3-ssi-interface-clock";
+   clocks = <&ssi_l4_ick>;
+   reg = <0x48004a10 0x4>;
+   ti,bit-shift = <0>;
+   };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1da9dc3..cbe5ff7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -270,15 +270,10 @@ extern struct clk dummy_ck;
 
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7eb6f2b..e42a703 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,6 +3,7 @@ obj-y   += clk.o dpll.o 
autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
   composite.o mux.o apll.o
 obj-$(CONFIG_SOC_AM33XX)   += clk-33xx.o
+obj-$(CONFIG_ARCH_OMAP3)   += interface.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
 obj-$(CONFIG_SO

[PATCHv13 14/40] CLK: TI: DRA7: Add APLL support

[Tero Kristo]

From: J Keerthy 

The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.

APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.

Signed-off-by: J Keerthy 
Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/apll.txt  |   31 +++
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/apll.c  |  223 
 3 files changed, 255 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
 create mode 100644 drivers/clk/ti/apll.c

diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt 
b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 000..7faf5a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,31 @@
+Binding for Texas Instruments APLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be "ti,dra7-apll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the APLL.
+  It contains the information of registers in the following order:
+   "control" - contains the control register base address
+   "idlest" - contains the idlest register base address
+
+Examples:
+   apll_pcie_ck: apll_pcie_ck@4a008200 {
+   #clock-cells = <0>;
+   clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+   reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+   compatible = "ti,dra7-apll-clock";
+   };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 935e5d2..3d71e1e 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
 ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
-  composite.o mux.o
+  composite.o mux.o apll.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
 endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 000..b986f61
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,223 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE 0x2
+#define MAX_APLL_WAIT_TRIES100
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+   struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+   int r = 0, i = 0;
+   struct dpll_data *ad;
+   const char *clk_name;
+   u8 state = 1;
+   u32 v;
+
+   ad = clk->dpll_data;
+   if (!ad)
+   return -EINVAL;
+
+   clk_name = __clk_get_name(clk->hw.clk);
+
+   state <<= __ffs(ad->idlest_mask);
+
+   /* Check is already locked */
+   v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
+
+   if ((v & ad->idlest_mask) == state)
+   return r;
+
+   v = ti_clk_ll_ops->clk_readl(ad->control_reg);
+   v &= ~ad->enable_mask;
+   v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+   ti_clk_ll_ops->clk_writel(v, ad->control_reg);
+
+   state <<= __ffs(ad->idlest_mask);
+
+   while (1) {
+   v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
+   if ((v & ad->idlest_mask) == state)
+   break;
+  

[PATCHv13 13/40] CLK: TI: omap5: Initialize USB_DPLL at boot

[Tero Kristo]

From: Roger Quadros 

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Signed-off-by: Roger Quadros 
Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 drivers/clk/ti/clk-54xx.c |   18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index c876e6e..0ef9f58 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
 
 #define OMAP5_DPLL_ABE_DEFFREQ 98304000
 
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ 96000
+
 static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
@@ -220,7 +226,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
 int __init omap5xxx_dt_clk_init(void)
 {
int rc;
-   struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+   struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 
ti_dt_clocks_register(omap54xx_clks);
 
@@ -235,5 +241,15 @@ int __init omap5xxx_dt_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+   usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+   rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+   if (rc)
+   pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+   usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
+   rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+   if (rc)
+   pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
return 0;
 }
-- 
1.7.9.5

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[PATCHv13 11/40] CLK: TI: add omap4 clock init file

[Tero Kristo]

clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/clock.h |1 -
 drivers/clk/ti/Makefile |1 +
 drivers/clk/ti/clk-44xx.c   |  316 +++
 include/linux/clk/ti.h  |3 +
 4 files changed, 320 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-44xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6bd72b5..b83fca6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
 int omap2_clk_deny_idle(struct clk *clk);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ef61d39..381f1f8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,4 +2,5 @@ ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
   composite.o mux.o
+obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
 endif
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 000..ae00218
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,316 @@
+/*
+ * OMAP4 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ 98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ 96000
+
+static struct ti_dt_clk omap44xx_clks[] = {
+   DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
+   DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
+   DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
+   DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
+   DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+   DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
+   DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
+   DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+   DT_CLK(NULL, "virt_1200_ck", "virt_1200_ck"),
+   DT_CLK(NULL, "virt_1300_ck", "virt_1300_ck"),
+   DT_CLK(NULL, "virt_1680_ck", "virt_1680_ck"),
+   DT_CLK(NULL, "virt_1920_ck", "virt_1920_ck"),
+   DT_CLK(NULL, "virt_2600_ck", "virt_2600_ck"),
+   DT_CLK(NULL, "virt_2700_ck", "virt_2700_ck"),
+   DT_CLK(NULL, "virt_3840_ck", "virt_3840_ck"),
+   DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+   DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
+   DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
+   DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
+   DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
+   DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
+   DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", 
"abe_dpll_bypass_clk_mux_ck"),
+   DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
+   DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+   DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+   DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+   DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+   DT_CLK(NULL, "abe_clk", "abe_clk"),
+   DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+   DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+   DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
+   DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+   DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+   DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
+   DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
+   DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
+   DT_CLK(NULL, "ddrphy_ck", "ddrphy_

[PATCHv13 23/40] ARM: dts: clk: Add apll related clocks

[Tero Kristo]

From: J Keerthy 

The patch adds a mux node to choose the parent of apll_pcie_ck node.

Signed-off-by: J Keerthy 
Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 32df847..d4e7410 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1150,11 +1150,19 @@
ti,invert-autoidle-bit;
};
 
+   apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+   compatible = "ti,mux-clock";
+   clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+   #clock-cells = <0>;
+   reg = <0x021c 0x4>;
+   ti,bit-shift = <7>;
+   };
+
apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
-   compatible = "ti,omap4-dpll-clock";
-   clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
-   reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+   compatible = "ti,dra7-apll-clock";
+   clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+   reg = <0x021c>, <0x0220>;
};
 
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
-- 
1.7.9.5

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[PATCHv13 19/40] CLK: TI: add am43xx clock init file

[Tero Kristo]

clk-43xx.c now contains the clock init functionality for am43xx, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 drivers/clk/ti/Makefile   |2 +-
 drivers/clk/ti/clk-43xx.c |  118 +
 include/linux/clk/ti.h|1 +
 3 files changed, 120 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-43xx.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ab386c8..007c3c2 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,7 @@
 ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
-  composite.o mux.o apll.o
+  composite.o mux.o apll.o clk-43xx.o
 obj-$(CONFIG_SOC_AM33XX)   += clk-33xx.o
 obj-$(CONFIG_ARCH_OMAP3)   += interface.o clk-3xxx.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
new file mode 100644
index 000..67c8de5
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx.c
@@ -0,0 +1,118 @@
+/*
+ * AM43XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static struct ti_dt_clk am43xx_clks[] = {
+   DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+   DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+   DT_CLK(NULL, "virt_1920_ck", "virt_1920_ck"),
+   DT_CLK(NULL, "virt_2400_ck", "virt_2400_ck"),
+   DT_CLK(NULL, "virt_2500_ck", "virt_2500_ck"),
+   DT_CLK(NULL, "virt_2600_ck", "virt_2600_ck"),
+   DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+   DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+   DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+   DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+   DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+   DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+   DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+   DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+   DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+   DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+   DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+   DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+   DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+   DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+   DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+   DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", 
"dpll_per_m2_div4_wkupdm_ck"),
+   DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+   DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+   DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+   DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+   DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+   DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+   DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+   DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+   DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+   DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+   DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+   DT_CLK(NULL, "sha0_fck", "sha0_fck"),
+   DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+   DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+   DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+   DT_CLK(NULL, "timer3_fck", "timer3_fck"),
+   DT_CLK(NULL, "timer4_fck", "timer4_fck"),
+   DT_CLK(NULL, "timer5_fck", "timer5_fck"),
+   DT_CLK(NULL, "timer6_fck", "timer6_fck"),
+   DT_CLK(NULL, "timer7_fck", "timer7_fck"),
+   DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
+   DT_CLK(NULL, "l3_gclk", "l3_gclk"),
+   DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
+   DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
+   DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
+   DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
+   DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
+   DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
+   DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
+   DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
+   DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
+   DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
+   DT_CLK(NULL, "gpio2_dbclk", "gpio

[PATCHv13 15/40] CLK: TI: add dra7 clock init file

[Tero Kristo]

clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 drivers/clk/ti/Makefile  |1 +
 drivers/clk/ti/clk-7xx.c |  332 ++
 include/linux/clk/ti.h   |1 +
 3 files changed, 334 insertions(+)
 create mode 100644 drivers/clk/ti/clk-7xx.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 3d71e1e..f8ae4b5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -4,4 +4,5 @@ obj-y   += clk.o dpll.o 
autoidle.o divider.o \
   composite.o mux.o apll.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
+obj-$(CONFIG_SOC_DRA7XX)   += clk-7xx.o
 endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 000..9977653
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,332 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRA7_DPLL_ABE_DEFFREQ  361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 10
+
+
+static struct ti_dt_clk dra7xx_clks[] = {
+   DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
+   DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
+   DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
+   DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"),
+   DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
+   DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
+   DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
+   DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
+   DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
+   DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
+   DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
+   DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
+   DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
+   DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
+   DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
+   DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
+   DT_CLK(NULL, "virt_1200_ck", "virt_1200_ck"),
+   DT_CLK(NULL, "virt_1300_ck", "virt_1300_ck"),
+   DT_CLK(NULL, "virt_1680_ck", "virt_1680_ck"),
+   DT_CLK(NULL, "virt_1920_ck", "virt_1920_ck"),
+   DT_CLK(NULL, "virt_2000_ck", "virt_2000_ck"),
+   DT_CLK(NULL, "virt_2600_ck", "virt_2600_ck"),
+   DT_CLK(NULL, "virt_2700_ck", "virt_2700_ck"),
+   DT_CLK(NULL, "virt_3840_ck", "virt_3840_ck"),
+   DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
+   DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
+   DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
+   DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
+   DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
+   DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
+   DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
+   DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
+   DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
+   DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
+   DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
+   DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
+   DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
+   DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
+   DT_CLK(NULL, "abe_clk", "abe_clk"),
+   DT_CLK(NULL, "aess_fclk", "aess_fclk"),
+   DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
+   DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
+   DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
+   DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
+   DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
+   DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
+   DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
+   DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
+   DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
+   DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
+   DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
+   DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
+   DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
+   DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
+   DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
+   DT_CLK(NULL, "dpll_core_ck", "dpll_co

[PATCHv13 16/40] CLK: TI: add am33xx clock init file

[Tero Kristo]

clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.

This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.

Signed-off-by: Tero Kristo 
Tested-by: Nishanth Menon 
Acked-by: Tony Lindgren 
---
 arch/arm/mach-omap2/clock.h |1 -
 drivers/clk/ti/Makefile |1 +
 drivers/clk/ti/clk-33xx.c   |  161 +++
 include/linux/clk/ti.h  |2 +
 4 files changed, 164 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-33xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b83fca6..1da9dc3 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -249,7 +249,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
 int omap2_clk_deny_idle(struct clk *clk);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
   const char *core_ck_name,
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f8ae4b5..7eb6f2b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
   composite.o mux.o apll.o
+obj-$(CONFIG_SOC_AM33XX)   += clk-33xx.o
 obj-$(CONFIG_ARCH_OMAP4)   += clk-44xx.o
 obj-$(CONFIG_SOC_OMAP5)+= clk-54xx.o
 obj-$(CONFIG_SOC_DRA7XX)   += clk-7xx.o
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 000..776ee45
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,161 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static struct ti_dt_clk am33xx_clks[] = {
+   DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
+   DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
+   DT_CLK(NULL, "virt_1920_ck", "virt_1920_ck"),
+   DT_CLK(NULL, "virt_2400_ck", "virt_2400_ck"),
+   DT_CLK(NULL, "virt_2500_ck", "virt_2500_ck"),
+   DT_CLK(NULL, "virt_2600_ck", "virt_2600_ck"),
+   DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
+   DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
+   DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
+   DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
+   DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
+   DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
+   DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
+   DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
+   DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+   DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
+   DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
+   DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
+   DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
+   DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
+   DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
+   DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
+   DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
+   DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", 
"dpll_per_m2_div4_wkupdm_ck"),
+   DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
+   DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
+   DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
+   DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
+   DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
+   DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
+   DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+   DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
+   DT_CLK("481d.d_can", NULL, "dcan1_fck"),
+   DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
+   DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
+   DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
+   DT_CLK(NULL, "mmu_fck", "mmu_fck"),
+   DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
+   DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
+   DT_CLK(NULL, "sha0_fck

[PATCHv13 10/40] clk: ti: add support for basic mux clock

[Tero Kristo]

ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.

Signed-off-by: Tero Kristo 
---
 Documentation/devicetree/bindings/clock/ti/mux.txt |   76 ++
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/composite.c |2 +-
 drivers/clk/ti/mux.c   |  246 
 include/linux/clk/ti.h |1 +
 5 files changed, 325 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt
 create mode 100644 drivers/clk/ti/mux.c

diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt 
b/Documentation/devicetree/bindings/clock/ti/mux.txt
new file mode 100644
index 000..2d0d170
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/mux.txt
@@ -0,0 +1,76 @@
+Binding for TI mux clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped multiplexer with multiple input clock signals or
+parents, one of which can be selected as output.  This clock does not
+gate or adjust the parent rate via a divider or multiplier.
+
+By default the "clocks" property lists the parents in the same order
+as they are programmed into the regster.  E.g:
+
+   clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
+
+results in programming the register as follows:
+
+register value selected parent clock
+0  foo_clock
+1  bar_clock
+2  baz_clock
+
+Some clock controller IPs do not allow a value of zero to be programmed
+into the register, instead indexing begins at 1.  The optional property
+"index-starts-at-one" modified the scheme as follows:
+
+register value selected clock parent
+1  foo_clock
+2  bar_clock
+3  baz_clock
+
+The binding must provide the register to control the mux. Optionally
+the number of bits to shift the control field in the register can be
+supplied. If the shift value is missing it is the same as supplying
+a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : register offset for register controlling adjustable mux
+
+Optional properties:
+- ti,bit-shift : number of bits to shift the bit-mask, defaults to
+  0 if not present
+- ti,index-starts-at-one : valid input select programming starts at 1, not
+  zero
+- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
+  not supported by the composite-mux-clock subtype
+
+Examples:
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+   #clock-cells = <0>;
+   compatible = "ti,mux-clock";
+   clocks = <&virt_1200_ck>, <&virt_1300_ck>, <&virt_1680_ck>, 
<&virt_1920_ck>, <&virt_2600_ck>, <&virt_2700_ck>, 
<&virt_3840_ck>;
+   reg = <0x0110>;
+   ti,index-starts-at-one;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+   #clock-cells = <0>;
+   compatible = "ti,mux-clock";
+   clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+   ti,bit-shift = <24>;
+   reg = <0x0108>;
+};
+
+mcbsp5_mux_fck: mcbsp5_mux_fck {
+   #clock-cells = <0>;
+   compatible = "ti,composite-mux-clock";
+   clocks = <&core_96m_fck>, <&mcbsp_clks>;
+   ti,bit-shift = <4>;
+   reg = <0x02d8>;
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 67056fb..ef61d39 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
   fixed-factor.o gate.o clockdomain.o \
-  composite.o
+  composite.o mux.o
 endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index ffb8db4..19d8980 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -173,7 +173,7 @@ static void __init ti_clk_register_composite(struct clk_hw 
*hw,
clk = clk_register_composite(NULL, node->name,
 parent_names, num_parents,
 _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
-&clk_mux_ops,
+&ti_clk_mux_ops,
 _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
 &ti_composite_divider_ops,
 _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
new file mode 100644
index 000..0197a47

[PATCHv13 07/40] clk: ti: add support for TI fixed factor clock

[Tero Kristo]

This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.

Signed-off-by: Tero Kristo 
---
 .../bindings/clock/ti/fixed-factor-clock.txt   |   43 +
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/fixed-factor.c  |   66 
 3 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
 create mode 100644 drivers/clk/ti/fixed-factor.c

diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt 
b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
new file mode 100644
index 000..662b36d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
@@ -0,0 +1,43 @@
+Binding for TI fixed factor rate clock sources.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1], and also uses the autoidle
+support from TI autoidle clock [2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
+
+Required properties:
+- compatible : shall be "ti,fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- ti,clock-div: fixed divider.
+- ti,clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
+  see [2]
+- reg: offset for the autoidle register of this clock, see [2]
+- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
+- ti,set-rate-parent: clk_set_rate is propagated to parent
+
+Example:
+   clock {
+   compatible = "ti,fixed-factor-clock";
+   clocks = <&parentclk>;
+   #clock-cells = <0>;
+   ti,clock-div = <2>;
+   ti,clock-mult = <1>;
+   };
+
+   dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+   #clock-cells = <0>;
+   compatible = "ti,fixed-factor-clock";
+   clocks = <&dpll_usb_ck>;
+   ti,clock-div = <1>;
+   ti,autoidle-shift = <8>;
+   reg = <0x01b4>;
+   ti,clock-mult = <1>;
+   ti,invert-autoidle-bit;
+   };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 640ebf9..f57fc4b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
 ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
-  composite.o
+  fixed-factor.o composite.o
 endif
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
new file mode 100644
index 000..c2c8a28
--- /dev/null
+++ b/drivers/clk/ti/fixed-factor.c
@@ -0,0 +1,66 @@
+/*
+ * TI Fixed Factor Clock
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+/**
+ * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
+ * @node: device node for this clock
+ *
+ * Sets up a simple fixed factor clock based on device tree info.
+ */
+static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
+{
+   struct clk *clk;
+   const char *clk_name = node->name;
+   const char *parent_name;
+   u32 div, mult;
+   u32 flags = 0;
+
+   if (of_property_read_u32(node, "ti,clock-div", &div)) {
+   pr_err("%s must have a clock-div property\n", node->name);
+   return;
+   }
+
+   if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
+   pr_err("%s must have a clock-mult property\n", node->name);
+   return;
+   }
+
+   if (of_property_read_bool(node, "ti,set-rate-parent"))
+   flags |= CLK_SET_RATE_PARENT;
+
+   parent_name = of_clk_get_parent_name(node, 0);
+
+   clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
+   mult, div);
+
+   if (!IS_ERR(clk)) {
+   of_clk_add_provider(node, of_clk_src_simple_get, clk);
+   of_ti_clk_autoidle_setup(node);
+   }
+}
+CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
+ 

[PATCHv13 08/40] CLK: TI: add support for gate clock

[Tero Kristo]

This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/gate.txt  |   85 +++
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/gate.c  |  249 
 include/linux/clk/ti.h |6 +
 4 files changed, 341 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
 create mode 100644 drivers/clk/ti/gate.c

diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt 
b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 000..125281a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,85 @@
+Binding for Texas Instruments gate clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+  "ti,gate-clock" - basic gate clock
+  "ti,wait-gate-clock" - gate clock which waits until clock is active before
+returning from clk_enable()
+  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
+  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
+  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
+ clock directly from a clockdomain, see [3] how
+ to map clockdomains properly
+  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
+ required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable gate, not needed for
+   ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,bit-shift : bit shift for programming the clock gate, invalid for
+ti,clkdm-gate-clock type
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+  gates the clock and clearing the bit ungates the clock.
+
+Examples:
+   mmchs2_fck: mmchs2_fck@48004a00 {
+   #clock-cells = <0>;
+   compatible = "ti,gate-clock";
+   clocks = <&core_96m_fck>;
+   reg = <0x48004a00 0x4>;
+   ti,bit-shift = <25>;
+   };
+
+   uart4_fck_am35xx: uart4_fck_am35xx {
+   #clock-cells = <0>;
+   compatible = "ti,wait-gate-clock";
+   clocks = <&core_48m_fck>;
+   reg = <0x0a00>;
+   ti,bit-shift = <23>;
+   };
+
+   dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+   #clock-cells = <0>;
+   compatible = "ti,dss-gate-clock";
+   clocks = <&dpll4_m4x2_ck>;
+   reg = <0x48004e00 0x4>;
+   ti,bit-shift = <0>;
+   };
+
+   emac_ick: emac_ick@4800259c {
+   #clock-cells = <0>;
+   compatible = "ti,am35xx-gate-clock";
+   clocks = <&ipss_ick>;
+   reg = <0x4800259c 0x4>;
+   ti,bit-shift = <1>;
+   };
+
+   emu_src_ck: emu_src_ck {
+   #clock-cells = <0>;
+   compatible = "ti,clkdm-gate-clock";
+   clocks = <&emu_src_mux_ck>;
+   };
+
+   dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+   #clock-cells = <0>;
+   compatible = "ti,hsdiv-gate-clock";
+   clocks = <&dpll4_m2x2_mul_ck>;
+   ti,bit-shift = <0x1b>;
+   reg = <0x48004d00 0x4>;
+   ti,set-bit-to-disable;
+   };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f57fc4b..7cba389 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
 ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
-  fixed-factor

[PATCHv13 06/40] CLK: ti: add support for ti divider-clock

[Tero Kristo]

This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/divider.txt   |  114 +
 drivers/clk/ti/Makefile|3 +-
 drivers/clk/ti/composite.c |2 +-
 drivers/clk/ti/divider.c   |  487 
 include/linux/clk/ti.h |2 +
 5 files changed, 606 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt
 create mode 100644 drivers/clk/ti/divider.c

diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt 
b/Documentation/devicetree/bindings/clock/ti/divider.txt
new file mode 100644
index 000..35a6f5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/divider.txt
@@ -0,0 +1,114 @@
+Binding for TI divider clock
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent.  By default the value programmed into
+the register is one less than the actual divisor value.  E.g:
+
+register value actual divisor value
+0  1
+1  2
+2  3
+
+This assumption may be modified by the following optional properties:
+
+ti,index-starts-at-one - valid divisor values start at 1, not the default
+of 0.  E.g:
+register value actual divisor value
+1  1
+2  2
+3  3
+
+ti,index-power-of-two - valid divisor values are powers of two.  E.g:
+register value actual divisor value
+0  1
+1  2
+2  4
+
+Additionally an array of valid dividers may be supplied like so:
+
+   ti,dividers = <4>, <8>, <0>, <16>;
+
+Which will map the resulting values to a divisor table by their index:
+register value actual divisor value
+0  4
+1  8
+2  
+3  16
+
+Any zero value in this array means the corresponding bit-value is invalid
+and must not be used.
+
+The binding must also provide the register to control the divider and
+unless the divider array is provided, min and max dividers. Optionally
+the number of bits to shift that mask, if necessary. If the shift value
+is missing it is the same as supplying a zero shift.
+
+This binding can also optionally provide support to the hardware autoidle
+feature, see [2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
+
+Required properties:
+- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- ti,dividers : array of integers defining divisors
+- ti,bit-shift : number of bits to shift the divider value, defaults to 0
+- ti,min-div : min divisor for dividing the input clock rate, only
+  needed if the first divisor is offset from the default value (1)
+- ti,max-div : max divisor for dividing the input clock rate, only needed
+  if ti,dividers is not defined.
+- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
+  only valid if ti,dividers is not defined.
+- ti,index-power-of-two : valid divisor programming must be a power of two,
+  only valid if ti,dividers is not defined.
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
+  see [2]
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
+  see [2]
+- ti,set-rate-parent : clk_set_rate is propagated to parent
+
+Examples:
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+   #clock-cells = <0>;
+   compatible = "ti,divider-clock";
+   clocks = <&dpll_usb_ck>;
+   ti,max-div = <127>;
+   reg = <0x190>;
+   ti,index-starts-at-one;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+   #clock-cells = <0>;
+   compatible = "ti,divider-clock";
+   clocks = <&abe_clk>;
+   ti,bit-shift = <24>;
+   reg = <0x528>;
+   ti,max-div = <2>;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+   #clock-cells = <0>;
+   compatible = "ti,composite-divider-clock";
+   clocks = <&dpll_core_x2_ck>;
+   ti,max-div = <31>;
+   reg = <0x0134>;
+   ti,index-starts-at-one;
+};
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+   #clock-cells = <0>;
+   compatible = "ti,composite-divider-clock";
+   clocks = <&corex2_fck>;
+   ti,bit-shift = <8>;
+   reg = <0x0a40>;
+   ti,dividers = <0>, <1>, <2

[PATCHv13 03/40] CLK: TI: Add DPLL clock support

[Tero Kristo]

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/dpll.txt  |   75 +++
 arch/arm/mach-omap2/clock.h|  164 +-
 arch/arm/mach-omap2/clock3xxx.h|2 -
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/dpll.c  |  558 
 include/linux/clk/ti.h |  172 ++
 6 files changed, 807 insertions(+), 166 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
 create mode 100644 drivers/clk/ti/dpll.c

diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt 
b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 000..30bfdb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,75 @@
+Binding for Texas Instruments DPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+   "ti,omap3-dpll-clock",
+   "ti,omap3-dpll-core-clock",
+   "ti,omap3-dpll-per-clock",
+   "ti,omap3-dpll-per-j-type-clock",
+   "ti,omap4-dpll-clock",
+   "ti,omap4-dpll-x2-clock",
+   "ti,omap4-dpll-core-clock",
+   "ti,omap4-dpll-m4xen-clock",
+   "ti,omap4-dpll-j-type-clock",
+   "ti,am3-dpll-no-gate-clock",
+   "ti,am3-dpll-j-type-clock",
+   "ti,am3-dpll-no-gate-j-type-clock",
+   "ti,am3-dpll-clock",
+   "ti,am3-dpll-core-clock",
+   "ti,am3-dpll-x2-clock",
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks, first entry lists reference clock
+  and second entry bypass clock
+- reg : offsets for the register set for controlling the DPLL.
+  Registers are listed in following order:
+   "control" - contains the control register base address
+   "idlest" - contains the idle status register base address
+   "mult-div1" - contains the multiplier / divider register base address
+   "autoidle" - contains the autoidle register base address (optional)
+  ti,am3-* dpll types do not have autoidle register
+
+Optional properties:
+- DPLL mode setting - defining any one or more of the following overrides
+  default setting.
+   - ti,low-power-stop : DPLL supports low power stop mode, gating output
+   - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
+   - ti,lock : DPLL locks in programmed rate
+
+Examples:
+   dpll_core_ck: dpll_core_ck@44e00490 {
+   #clock-cells = <0>;
+   compatible = "ti,omap4-dpll-core-clock";
+   clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+   reg = <0x490>, <0x45c>, <0x488>, <0x468>;
+   };
+
+   dpll2_ck: dpll2_ck@48004004 {
+   #clock-cells = <0>;
+   compatible = "ti,omap3-dpll-clock";
+   clocks = <&sys_ck>, <&dpll2_fck>;
+   ti,low-power-stop;
+   ti,low-power-bypass;
+   ti,lock;
+   reg = <0x4>, <0x24>, <0x34>, <0x40>;
+   };
+
+   dpll_core_ck: dpll_core_ck@44e00490 {
+   #clock-cells = <0>;
+   compatible = "ti,am3-dpll-core-clock";
+   clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+   reg = <0x90>, <0x5c>, <0x68>;
+   };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 82916cc..b345f3e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include 
 #include 
+#include 
 
 struct omap_clk {
u16 cpu;
@@ -37,7 +38,6 @@ struct omap_clk {
}
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
@@ -178,141 +178,6 @@ struct clksel {
const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1

[PATCHv13 04/40] CLK: TI: add autoidle support

[Tero Kristo]

TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/autoidle.txt  |   39 ++
 arch/arm/mach-omap2/clock.c|6 +
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/autoidle.c  |  133 
 include/linux/clk/ti.h |9 ++
 5 files changed, 188 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/autoidle.txt
 create mode 100644 drivers/clk/ti/autoidle.c

diff --git a/Documentation/devicetree/bindings/clock/ti/autoidle.txt 
b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
new file mode 100644
index 000..7c735dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
@@ -0,0 +1,39 @@
+Binding for Texas Instruments autoidle clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a register mapped
+clock which can be put to idle automatically by hardware based on the usage
+and a configuration bit setting. Autoidle clock is never an individual
+clock, it is always a derivative of some basic clock like a gate, divider,
+or fixed-factor.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- reg : offset for the register controlling the autoidle
+- ti,autoidle-shift : bit shift of the autoidle enable bit
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
+
+Examples:
+   dpll_core_m4_ck: dpll_core_m4_ck {
+   #clock-cells = <0>;
+   compatible = "ti,divider-clock";
+   clocks = <&dpll_core_x2_ck>;
+   ti,max-div = <31>;
+   ti,autoidle-shift = <8>;
+   reg = <0x2d38>;
+   ti,index-starts-at-one;
+   ti,invert-autoidle-bit;
+   };
+
+   dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+   #clock-cells = <0>;
+   compatible = "ti,fixed-factor-clock";
+   clocks = <&dpll_usb_ck>;
+   ti,clock-div = <1>;
+   ti,autoidle-shift = <8>;
+   reg = <0x01b4>;
+   ti,clock-mult = <1>;
+   ti,invert-autoidle-bit;
+   };
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c7c5d31..238be3f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->allow_idle)
c->ops->allow_idle(c);
+
+   of_ti_clk_allow_autoidle_all();
+
return 0;
 }
 
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
list_for_each_entry(c, &clk_hw_omap_clocks, node)
if (c->ops && c->ops->deny_idle)
c->ops->deny_idle(c);
+
+   of_ti_clk_deny_autoidle_all();
+
return 0;
 }
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y  += clk.o dpll.o
+obj-y  += clk.o dpll.o autoidle.o
 endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 000..8912ff8
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,133 @@
+/*
+ * TI clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct clk_ti_autoidle {
+   void __iomem*reg;
+   u8  shift;
+   u8  flags;
+   const char  *name;
+   struct list_headnode;
+};
+
+#define AUTOIDLE_LOW   0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void ti_allow_autoidle(struct clk_ti_autoidle *clk)
+{
+   u32 val;
+
+   val = ti_clk_ll_ops->clk_readl(clk->reg);
+
+   if (clk->flags & AUTOIDLE_LOW)
+   val &= ~(1 << clk->shift);
+   else
+   val |= (1 << clk->shift);

[PATCHv13 09/40] CLK: TI: add support for clockdomain binding

[Tero Kristo]

Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks. Clockdomain
itself is rather misleading name for the hardware functionality, as at
least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either
clocks and/or IP blocks, thus idle-domain or such might be more appropriate.
For most cases on these SoCs, the kernel doesn't even need the information
and the mappings can be ignored.

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/clockdomain.txt   |   24 +++
 drivers/clk/ti/Makefile|3 +-
 drivers/clk/ti/clockdomain.c   |   70 
 include/linux/clk/ti.h |1 +
 4 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt
 create mode 100644 drivers/clk/ti/clockdomain.c

diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt 
b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
new file mode 100644
index 000..cb76b3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
@@ -0,0 +1,24 @@
+Binding for Texas Instruments clockdomain.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1] in consumer role.
+Every clock on TI SoC belongs to one clockdomain, but software
+only needs this information for specific clocks which require
+their parent clockdomain to be controlled when the clock is
+enabled/disabled. This binding doesn't define a new clock
+binding type, it is used to group existing clock nodes under
+hardware hierarchy.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,clockdomain"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of clocks within this domain
+
+Examples:
+   dss_clkdm: dss_clkdm {
+   compatible = "ti,clockdomain";
+   clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+   };
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 7cba389..67056fb 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y  += clk.o dpll.o autoidle.o divider.o \
-  fixed-factor.o gate.o composite.o
+  fixed-factor.o gate.o clockdomain.o \
+  composite.o
 endif
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
new file mode 100644
index 000..f1e0038
--- /dev/null
+++ b/drivers/clk/ti/clockdomain.c
@@ -0,0 +1,70 @@
+/*
+ * OMAP clockdomain support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
+   struct clk *clk;
+   struct clk_hw *clk_hw;
+   const char *clkdm_name = node->name;
+   int i;
+   int num_clks;
+
+   num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+
+   for (i = 0; i < num_clks; i++) {
+   clk = of_clk_get(node, i);
+   if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+   pr_warn("can't setup clkdm for basic clk %s\n",
+   __clk_get_name(clk));
+   continue;
+   }
+   clk_hw = __clk_get_hw(clk);
+   to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
+   omap2_init_clk_clkdm(clk_hw);
+   }
+}
+
+static struct of_device_id ti_clkdm_match_table[] __initdata = {
+   { .compatible = "ti,clockdomain" },
+   { }
+};
+
+/**
+ * ti_dt_clockdomains_setup - setup device tree clockdomains
+ *
+ * Initializes clockdomain nodes for a SoC. This parses through all the
+ * nodes with compatible = "ti,clockdomain", and add the clockdomain
+ * info for all the clocks listed under these. This function shall be
+ * called after rest of the DT clock init has completed and all
+ * clock nodes have been registered.
+ */
+void __init ti_dt_clockdomains_setup(void)
+{
+   struct device_node *np;
+   for_each_mat

[PATCHv13 00/40] ARM: TI SoC clock DT conversion

[Tero Kristo]

Hi,

So, bad luck number release for this, as v12 wasn't sufficient still.

Changes compared to previous version:
- Dropped any changes to generic clock drivers, as it seems impossible
  to agree anything in short term, this means the patch set shrank in
  size from 49 patches to 40 (first 9 patches were dropped).
- Copy pasted implementation for clk-divider and clk-mux from drivers/clk
  to drivers/clk/ti, and made the modifications needed to the TI version
  of the clock drivers only (based on discussions with Mike, this is fine)
- Changed name of clk_ll_ops to ti_clk_ll_ops so that this doesn't conflict
  with any generic implementation we might have at some point, migrating
  this to the generic version should be easy enough also.
- Fixed trace_clk_div_div_ck for omap4, this node was broken in previous
  versions and resulted into an orphan clock node
- Fixed compile problem for omap5 only build reported by Felipe
- Fixed a couple of sparse warnings
- changed the mach-omap2/clock.c to use readl_relaxed / writel_relaxed
  instead of __raw_readl / __raw_writel

Testing done:
- omap3-beagle: boot / suspend-resume (RET) / suspend-resume (OFF)
- omap4-panda-es: boot / suspend-resume (RET)
- omap5-uevm: boot
- am335x-bone: boot
- dra7-evm: boot

Maintainer friendly branches also available:

tree: https://github.com/t-kristo/linux-pm.git

clk driver only (Mike): clk-next-dt-clks-v13
DTS data only (Benoit): dts_for_3.14-dt-clks-v13
full-branch (Tony/Paul): 3.13-rc7-dt-clks-v13

-Tero

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[PATCHv13 05/40] clk: ti: add composite clock support

[Tero Kristo]

This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.

Signed-off-by: Tero Kristo 
---
 .../devicetree/bindings/clock/ti/composite.txt |   54 
 arch/arm/mach-omap2/clock.h|3 -
 drivers/clk/ti/Makefile|2 +-
 drivers/clk/ti/composite.c |  269 
 include/linux/clk/ti.h |   12 +
 5 files changed, 336 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/composite.txt
 create mode 100644 drivers/clk/ti/composite.c

diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt 
b/Documentation/devicetree/bindings/clock/ti/composite.txt
new file mode 100644
index 000..5f43c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/composite.txt
@@ -0,0 +1,54 @@
+Binding for TI composite clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped composite clock with multiple different sub-types;
+
+a multiplexer clock with multiple input clock signals or parents, one
+of which can be selected as output, this behaves exactly as [2]
+
+an adjustable clock rate divider, this behaves exactly as [3]
+
+a gating function which can be used to enable and disable the output
+clock, this behaves exactly as [4]
+
+The binding must provide a list of the component clocks that shall be
+merged to this clock. The component clocks shall be of one of the
+"ti,*composite*-clock" types.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/mux.txt
+[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[4] Documentation/devicetree/bindings/clock/ti/gate.txt
+
+Required properties:
+- compatible : shall be: "ti,composite-clock"
+- clocks : link phandles of component clocks
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Examples:
+
+usb_l4_gate_ick: usb_l4_gate_ick {
+   #clock-cells = <0>;
+   compatible = "ti,composite-interface-clock";
+   clocks = <&l4_ick>;
+   ti,bit-shift = <5>;
+   reg = <0x0a10>;
+};
+
+usb_l4_div_ick: usb_l4_div_ick {
+   #clock-cells = <0>;
+   compatible = "ti,composite-divider-clock";
+   clocks = <&l4_ick>;
+   ti,bit-shift = <4>;
+   ti,max-div = <1>;
+   reg = <0x0a40>;
+   ti,index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick {
+   #clock-cells = <0>;
+   compatible = "ti,composite-clock";
+   clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b345f3e..6bd72b5 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -240,9 +240,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap 
*clk);
 
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
   void __iomem **other_reg,
   u8 *other_bit);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..a4a7595 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y  += clk.o dpll.o autoidle.o
+obj-y  += clk.o dpll.o autoidle.o composite.o
 endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
new file mode 100644
index 000..6539b65
--- /dev/null
+++ b/drivers/clk/ti/composite.c
@@ -0,0 +1,269 @@
+/*
+ * TI composite clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+   return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long ti_composite_round_rate(struct clk_hw *hw, unsigned lon

[PATCHv13 02/40] CLK: ti: add init support for clock IP blocks

[Tero Kristo]

ti_dt_clk_init_provider() can now be used to initialize the contents of
a single clock IP block. This parses all the clocks under the IP block
and calls the corresponding init function for them.

This patch also introduces a helper function for the TI clock drivers
to get register info from DT and append the master IP info to this.

Signed-off-by: Tero Kristo 
---
 drivers/clk/clk.c|4 +-
 drivers/clk/ti/clk.c |  112 ++
 include/linux/clk-provider.h |2 +
 include/linux/clk/ti.h   |   35 +
 4 files changed, 150 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6..bbbe799 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2104,8 +2104,6 @@ struct of_clk_provider {
void *data;
 };
 
-extern struct of_device_id __clk_of_table[];
-
 static const struct of_device_id __clk_of_table_sentinel
__used __section(__clk_of_table_end);
 
@@ -2245,7 +2243,7 @@ void __init of_clk_init(const struct of_device_id 
*matches)
struct device_node *np;
 
if (!matches)
-   matches = __clk_of_table;
+   matches = &__clk_of_table;
 
for_each_matching_node_and_match(np, matches, &match) {
of_clk_init_cb_t clk_init_cb = match->data;
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index ef1a7cd..b1a6f71 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -19,10 +19,15 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #undef pr_fmt
 #define pr_fmt(fmt) "%s: " fmt, __func__
 
+static int ti_dt_clk_memmap_index;
+struct ti_clk_ll_ops *ti_clk_ll_ops;
+
 /**
  * ti_dt_clocks_register - register DT alias clocks during boot
  * @oclks: list of clocks to register
@@ -53,3 +58,110 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
}
}
 }
+
+struct clk_init_item {
+   struct device_node *node;
+   struct clk_hw *hw;
+   ti_of_clk_init_cb_t func;
+   struct list_head link;
+};
+
+static LIST_HEAD(retry_list);
+
+/**
+ * ti_clk_retry_init - retries a failed clock init at later phase
+ * @node: device not for the clock
+ * @hw: partially initialized clk_hw struct for the clock
+ * @func: init function to be called for the clock
+ *
+ * Adds a failed clock init to the retry list. The retry list is parsed
+ * once all the other clocks have been initialized.
+ */
+int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+ ti_of_clk_init_cb_t func)
+{
+   struct clk_init_item *retry;
+
+   pr_debug("%s: adding to retry list...\n", node->name);
+   retry = kzalloc(sizeof(*retry), GFP_KERNEL);
+   if (!retry)
+   return -ENOMEM;
+
+   retry->node = node;
+   retry->func = func;
+   retry->hw = hw;
+   list_add(&retry->link, &retry_list);
+
+   return 0;
+}
+
+/**
+ * ti_clk_get_reg_addr - get register address for a clock register
+ * @node: device node for the clock
+ * @index: register index from the clock node
+ *
+ * Builds clock register address from device tree information. This
+ * is a struct of type clk_omap_reg.
+ */
+void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
+{
+   struct clk_omap_reg *reg;
+   u32 val;
+   u32 tmp;
+
+   reg = (struct clk_omap_reg *)&tmp;
+   reg->index = ti_dt_clk_memmap_index;
+
+   if (of_property_read_u32_index(node, "reg", index, &val)) {
+   pr_err("%s must have reg[%d]!\n", node->name, index);
+   return NULL;
+   }
+
+   reg->offset = val;
+
+   return (void __iomem *)tmp;
+}
+
+/**
+ * ti_dt_clk_init_provider - init master clock provider
+ * @parent: master node
+ * @index: internal index for clk_reg_ops
+ *
+ * Initializes a master clock IP block and its child clock nodes.
+ * Regmap is provided for accessing the register space for the
+ * IP block and all the clocks under it.
+ */
+void ti_dt_clk_init_provider(struct device_node *parent, int index)
+{
+   const struct of_device_id *match;
+   struct device_node *np;
+   struct device_node *clocks;
+   of_clk_init_cb_t clk_init_cb;
+   struct clk_init_item *retry;
+   struct clk_init_item *tmp;
+
+   ti_dt_clk_memmap_index = index;
+
+   /* get clocks for this parent */
+   clocks = of_get_child_by_name(parent, "clocks");
+   if (!clocks) {
+   pr_err("%s missing 'clocks' child node.\n", parent->name);
+   return;
+   }
+
+   for_each_child_of_node(clocks, np) {
+   match = of_match_node(&__clk_of_table, np);
+   if (!match)
+   continue;
+   clk_init_cb = (of_clk_init_cb_t)match->data;
+   pr_debug("%s: initializing: %s\n", __func__, np->name);
+   clk_init_cb(np);
+   }
+
+   list_for_each_entry_safe(retry, tmp, &retry_list, link) {
+   

[PATCHv13 01/40] CLK: TI: add DT alias clock registration mechanism

[Tero Kristo]

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo 
---
 drivers/clk/Makefile|1 +
 drivers/clk/ti/Makefile |3 +++
 drivers/clk/ti/clk.c|   55 +++
 include/linux/clk/ti.h  |   42 
 4 files changed, 101 insertions(+)
 create mode 100644 drivers/clk/ti/Makefile
 create mode 100644 drivers/clk/ti/clk.c
 create mode 100644 include/linux/clk/ti.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9..c61f768 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA)  += tegra/
 obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
 obj-$(CONFIG_COMMON_CLK_XGENE)  += clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
+obj-$(CONFIG_ARCH_OMAP)+= ti/
 
 obj-$(CONFIG_X86)  += x86/
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 000..1825f7f
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(CONFIG_OF),)
+obj-y  += clk.o
+endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 000..ef1a7cd
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,55 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+/**
+ * ti_dt_clocks_register - register DT alias clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register alias or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
+{
+   struct ti_dt_clk *c;
+   struct device_node *node;
+   struct clk *clk;
+   struct of_phandle_args clkspec;
+
+   for (c = oclks; c->node_name != NULL; c++) {
+   node = of_find_node_by_name(NULL, c->node_name);
+   clkspec.np = node;
+   clk = of_clk_get_from_provider(&clkspec);
+
+   if (!IS_ERR(clk)) {
+   c->lk.clk = clk;
+   clkdev_add(&c->lk);
+   } else {
+   pr_warn("failed to lookup clock node %s\n",
+   c->node_name);
+   }
+   }
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
new file mode 100644
index 000..df94c24
--- /dev/null
+++ b/include/linux/clk/ti.h
@@ -0,0 +1,42 @@
+/*
+ * TI clock drivers support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_CLK_TI_H__
+#define __LINUX_CLK_TI_H__
+
+#include 
+
+/**
+ * struct ti_dt_clk - OMAP DT clock alias declarations
+ * @lk: clock lookup definition
+ * @node_name: clock DT node to map to
+ */
+struct ti_dt_clk {
+   struct clk_lookup   lk;
+   char*node_name;
+};
+
+#define DT_CLK(dev, con, name) \
+   {   \
+   .lk = { \
+   .dev_id = dev,  \
+   .con_id = con,  \
+   },  \
+   .node_name = name,  \
+   }
+
+
+void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+
+#endif
-- 
1.7.9.5

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Re: [PATCH RFC 00/26] Migrate more OMAP DMA code to DMA engine

[Vinod Koul]

On Thu, Jan 02, 2014 at 03:08:36PM +, Russell King - ARM Linux wrote:
> The following patch series moves code to setup the DMA hardware and
> service interrupts from the hardware to the DMA engine driver.  This
> reduces the dependency on the legacy DMA implementation.
Didnt the code getting removed from legacy, are there any users still of
the legacy driver in mainline?

--
~Vinod
> 
> This series does not remove the channel allocation/freeing hooks which
> are used to manage the allocation of physical channels - this is the
> next step in the evolution.
> 
> The patches which move the interrupt handling are currently less than
> perfect since they're writing to ENABLE_L0 under a different spinlock,
> and hence RFC only at the moment.
> 
>  arch/arm/mach-omap1/dma.c |  183 +
>  arch/arm/mach-omap2/dma.c |  183 ++
>  arch/arm/plat-omap/dma.c  |   17 +-
>  drivers/dma/omap-dma.c|  653 
> -
>  include/linux/omap-dma.h  |   25 ++-
>  5 files changed, 774 insertions(+), 287 deletions(-)
> 
> -- 
> FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
> in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
> Estimate before purchase was "up to 13.2Mbit".

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RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support

[Hiremath, Vaibhav]

> -Original Message-
> From: Hiremath, Vaibhav
> Sent: Thursday, January 09, 2014 2:01 PM
> To: Valkeinen, Tomi; Ivaylo Dimitrov
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-fb...@vger.kernel.org
> Subject: RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> 
> 
> > -Original Message-
> > From: Valkeinen, Tomi
> > Sent: Thursday, January 09, 2014 1:52 PM
> > To: Hiremath, Vaibhav; Ivaylo Dimitrov
> > Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> > ker...@lists.infradead.org; linux-fb...@vger.kernel.org
> > Subject: Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> >
> > On 2014-01-09 07:06, Hiremath, Vaibhav wrote:
> >
> > > I am seeing underflow issue on AM43x device if I use omapfb_vram
> argument.
> > > Did you see this on OMAP?
> > >
> > > I am using "omapfb_vram=10M@0xA000", and I believe it is correct
> > > way
> > of usage.
> >
> > Hmm ok... The AM4x seems to have issues anyway, as we're seeing
> > underflows easily in other situations also.
> >
> > Well, there's a small difference in the allocation. The normal dma
> > alloc uses
> > dma_alloc_attrs() and passes DMA_ATTR_WRITE_COMBINE as a flag, whereas
> > allocating from the absolute address just uses the piece of memory. I
> > couldn't find how to set write-combine for the abs memory area.
> >
> > Then again, that's for CPU caching, so I don't see why it would affect
> > DSS as such (but that's still something we should measure, cpu
> > read/write perf for normal and abs allocation).
> >
> > The only thought I have is that somehow the reserved memory area is
> > missing some configuration that is done for the rest of the memory.
> > But that's purely a guess, this is totally out of my area of expertise...
> >
> > Vaibhav, just to be sure, can you run both with normal dma_alloc and
> > with the reserve, and verify that the dispc register dumps are the same?
> > I don't see how they could be different, but just to be sure.
> >
> 
> Will check and update you shortly.
> 

I checked both the DSS configuration in both scenarios and they look same to me.


With normal dma_alloc:
===
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /proc/cmdline
console=ttyO0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait mem=128M 
consoleblank=0 clocksource=gp_timer consoleblank=0 earlyprintk
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dss
DSS_REVISION0020
DSS_SYSCONFIG   0001
DSS_SYSSTATUS   0001
DSS_CONTROL 0018
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/clk
- DSS -
DSS_FCK (DSS_FCLK1) = 19800
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK1)
fck 19800
- LCD -
LCD clk source = DSS_FCK (DSS_FCLK1)
lck 19800   lck div 1
pck 3300pck div 6
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dispc_irq
period 44780 ms
irqs 1
FRAMEDONE 0
VSYNC 1
EVSYNC_EVEN   1
EVSYNC_ODD1
ACBIAS_COUNT_STAT 0
PROG_LINE_NUM 1
GFX_FIFO_UNDERFLOW0
GFX_END_WIN   1
PAL_GAMMA_MASK0
OCP_ERR   0
VID1_FIFO_UNDERFLOW   0
VID1_END_WIN  0
VID2_FIFO_UNDERFLOW   0
VID2_END_WIN  0
SYNC_LOST 0
SYNC_LOST_DIGIT   0
WAKEUP0
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dispc
DISPC_REVISION 0030
DISPC_SYSCONFIG2011
DISPC_SYSSTATUS0001
DISPC_IRQSTATUS00ae
DISPC_IRQENABLEd640
DISPC_CONTROL  00018309
DISPC_CONFIG   0204
DISPC_CAPABLE  03ff
DISPC_LINE_STATUS  00b1
DISPC_LINE_NUMBER  
DISPC_GLOBAL_ALPHA 00ff
DISPC_DEFAULT_COLOR(LCD)   
DISPC_TRANS_COLOR(LCD) 
DISPC_SIZE_MGR(LCD)01df031f
DISPC_DEFAULT_COLOR(LCD)   
DISPC_TRANS_COLOR(LCD) 
DISPC_TIMING_H(LCD)00f0d11d
DISPC_TIMING_V(LCD)00a0160c
DISPC_POL_FREQ(LCD)3000
DISPC_DIVISORo(LCD)   

[PATCH v5 0/9] USB Host support for OMAP5 uEVM (for 3.14)

[Roger Quadros]

Hi Benoit & Tony,

This patchset brings up USB Host ports and Ethernet port on
the OMAP5 uEVM board.

It depends on the TI Clock DT conversion patches [1] and is based
on 3.13-rc7

[1] - http://article.gmane.org/gmane.linux.ports.arm.kernel/289895

NOTE: I've tested this only on the OMAP5 uEVM board. Since the patchset
changes could affect OMAP3/4, it must be verified at least on
a Beagleboard and a Panda board before being pulled in.
I request someone to verify this on OMAP3/4 since I don't have access
to those boards at the moment. Thanks.

Changelog:

v5:
- Expose all clocks in the DT binding document for mfd:omap-usb-host
and mfd:omap-usb-tll

v4:
- Updated DT binding document for clock binding

v3:
- Rebased on top of 3.13-rc7

cheers,
-roger

Roger Quadros (9):
  mfd: omap-usb-host: Use resource managed clk_get()
  mfd: omap-usb-host: Get clocks based on hardware revision
  mfd: omap-usb-host: Update DT clock binding information
  mfd: omap-usb-tll: Update DT clock binding information
  ARM: dts: omap4: Update omap-usb-host node
  ARM: dts: omap5: Update omap-usb-host node
  ARM: dts: omap4-panda: Provide USB PHY clock
  ARM: dts: omap5-uevm: Provide USB PHY clock
  ARM: OMAP2+: Remove legacy_init_ehci_clk()

 .../devicetree/bindings/mfd/omap-usb-host.txt  |  23 +++
 .../devicetree/bindings/mfd/omap-usb-tll.txt   |  10 ++
 arch/arm/boot/dts/omap4-panda-common.dtsi  |   8 +-
 arch/arm/boot/dts/omap4.dtsi   |   6 +
 arch/arm/boot/dts/omap5-uevm.dts   |   8 +-
 arch/arm/boot/dts/omap5.dtsi   |   6 +
 arch/arm/mach-omap2/pdata-quirks.c |  16 --
 drivers/mfd/omap-usb-host.c| 172 ++---
 8 files changed, 128 insertions(+), 121 deletions(-)

-- 
1.8.3.2

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[PATCH v5 4/9] mfd: omap-usb-tll: Update DT clock binding information

[Roger Quadros]

The omap-usb-tll driver needs one clock for each TLL channel.
Add this information to the DT binding document.

CC: Lee Jones 
CC: Samuel Ortiz 
Signed-off-by: Roger Quadros 
---
 Documentation/devicetree/bindings/mfd/omap-usb-tll.txt | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt 
b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
index 62fe697..c58d704 100644
--- a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
+++ b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
@@ -7,6 +7,16 @@ Required properties:
 - interrupts : should contain the TLL module's interrupt
 - ti,hwmod : must contain "usb_tll_hs"
 
+Optional properties:
+
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+
+- clock-names: should include:
+  * "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock
+  * "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock
+  * "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock
+
 Example:
 
usbhstll: usbhstll@4a062000 {
-- 
1.8.3.2

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[PATCH v5 7/9] ARM: dts: omap4-panda: Provide USB PHY clock

[Roger Quadros]

The USB PHY gets its clock from AUXCLK3. Provide this
information.

Signed-off-by: Roger Quadros 
---
 arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi 
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 88c6a05..50b72966 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -83,12 +83,8 @@
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;   /* gpio_62 */
vcc-supply = <&hsusb1_power>;
-   /**
-* FIXME:
-* put the right clock phandle here when available
-*  clocks = <&auxclk3>;
-*  clock-names = "main_clk";
-*/
+   clocks = <&auxclk3_ck>;
+   clock-names = "main_clk";
clock-frequency = <1920>;
};
 
-- 
1.8.3.2

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[PATCH v5 8/9] ARM: dts: omap5-uevm: Provide USB PHY clock

[Roger Quadros]

The HS USB 2 PHY gets its clock from AUXCLK1. Provide this
information.

Signed-off-by: Roger Quadros 
---
 arch/arm/boot/dts/omap5-uevm.dts | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 002fa70..3b99ec2 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -31,12 +31,8 @@
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 
HUB_NRESET */
-   /**
- * FIXME
- * Put the right clock phandle here when available
- * clocks = <&auxclk1>;
- * clock-names = "main_clk";
- */
+   clocks = <&auxclk1_ck>;
+   clock-names = "main_clk";
clock-frequency = <1920>;
};
 
-- 
1.8.3.2

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[PATCH v5 6/9] ARM: dts: omap5: Update omap-usb-host node

[Roger Quadros]

The omap-usb-host driver expects a certain name for internal
and external reference clocks. Provide these clocks.

Signed-off-by: Roger Quadros 
---
 arch/arm/boot/dts/omap5.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 2f12a47..0f82ecf 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -765,6 +765,12 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+   clocks = <&l3init_60m_fclk>,
+<&xclk60mhsp1_ck>,
+<&xclk60mhsp2_ck>;
+   clock-names = "refclk_60m_int",
+ "refclk_60m_ext_p1",
+ "refclk_60m_ext_p2";
 
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3", "usb-ohci";
-- 
1.8.3.2

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[PATCH v5 2/9] mfd: omap-usb-host: Get clocks based on hardware revision

[Roger Quadros]

Not all revisions have all the clocks so get the necessary clocks
based on hardware revision.

This should avoid un-necessary clk_get failure messages that were
observed earlier.

Be more strict and always fail on clk_get() error.

CC: Lee Jones 
CC: Samuel Ortiz 
Signed-off-by: Roger Quadros 
---
 drivers/mfd/omap-usb-host.c | 93 +++--
 1 file changed, 64 insertions(+), 29 deletions(-)

diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 1c9bca2..7202cc6 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -92,7 +92,6 @@
 #define is_ehci_tll_mode(x)(x == OMAP_EHCI_PORT_MODE_TLL)
 #define is_ehci_hsic_mode(x)   (x == OMAP_EHCI_PORT_MODE_HSIC)
 
-
 struct usbhs_hcd_omap {
int nports;
struct clk  **utmi_clk;
@@ -665,22 +664,41 @@ static int usbhs_omap_probe(struct platform_device *pdev)
goto err_mem;
}
 
-   need_logic_fck = false;
+   /* Set all clocks as invalid to begin with */
+   omap->ehci_logic_fck = omap->init_60m_fclk = ERR_PTR(-EINVAL);
+   omap->utmi_p1_gfclk = omap->utmi_p2_gfclk = ERR_PTR(-EINVAL);
+   omap->xclk60mhsp1_ck = omap->xclk60mhsp2_ck = ERR_PTR(-EINVAL);
+
for (i = 0; i < omap->nports; i++) {
-   if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
-   is_ehci_hsic_mode(i))
-   need_logic_fck |= true;
+   omap->utmi_clk[i] = ERR_PTR(-EINVAL);
+   omap->hsic480m_clk[i] = ERR_PTR(-EINVAL);
+   omap->hsic60m_clk[i] = ERR_PTR(-EINVAL);
}
 
-   omap->ehci_logic_fck = ERR_PTR(-EINVAL);
-   if (need_logic_fck) {
-   omap->ehci_logic_fck = devm_clk_get(dev, "ehci_logic_fck");
-   if (IS_ERR(omap->ehci_logic_fck)) {
-   ret = PTR_ERR(omap->ehci_logic_fck);
-   dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
+   /* for OMAP3 i.e. USBHS REV1 */
+   if (omap->usbhs_rev == OMAP_USBHS_REV1) {
+   need_logic_fck = false;
+   for (i = 0; i < omap->nports; i++) {
+   if (is_ehci_phy_mode(pdata->port_mode[i]) ||
+   is_ehci_tll_mode(pdata->port_mode[i]) ||
+   is_ehci_hsic_mode(pdata->port_mode[i]))
+
+   need_logic_fck |= true;
+   }
+
+   if (need_logic_fck) {
+   omap->ehci_logic_fck = clk_get(dev, "usbhost_120m_fck");
+   if (IS_ERR(omap->ehci_logic_fck)) {
+   ret = PTR_ERR(omap->ehci_logic_fck);
+   dev_err(dev, "usbhost_120m_fck failed:%d\n",
+   ret);
+   goto err_mem;
+   }
}
+   goto initialize;
}
 
+   /* for OMAP4+ i.e. USBHS REV2+ */
omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk");
if (IS_ERR(omap->utmi_p1_gfclk)) {
ret = PTR_ERR(omap->utmi_p1_gfclk);
@@ -728,54 +746,71 @@ static int usbhs_omap_probe(struct platform_device *pdev)
 * them
 */
omap->utmi_clk[i] = devm_clk_get(dev, clkname);
-   if (IS_ERR(omap->utmi_clk[i]))
-   dev_dbg(dev, "Failed to get clock : %s : %ld\n",
-   clkname, PTR_ERR(omap->utmi_clk[i]));
+   if (IS_ERR(omap->utmi_clk[i])) {
+   ret = PTR_ERR(omap->utmi_clk[i]);
+   dev_err(dev, "Failed to get clock : %s : %d\n",
+   clkname, ret);
+   goto err_mem;
+   }
 
snprintf(clkname, sizeof(clkname),
"usb_host_hs_hsic480m_p%d_clk", i + 1);
omap->hsic480m_clk[i] = devm_clk_get(dev, clkname);
-   if (IS_ERR(omap->hsic480m_clk[i]))
-   dev_dbg(dev, "Failed to get clock : %s : %ld\n",
-   clkname, PTR_ERR(omap->hsic480m_clk[i]));
+   if (IS_ERR(omap->hsic480m_clk[i])) {
+   ret = PTR_ERR(omap->hsic480m_clk[i]);
+   dev_err(dev, "Failed to get clock : %s : %d\n",
+   clkname, ret);
+   goto err_mem;
+   }
 
snprintf(clkname, sizeof(clkname),
"usb_host_hs_hsic60m_p%d_clk", i + 1);
omap->hsic60m_clk[i] = devm_clk_get(dev, clkname);
-   if (IS_ERR(omap->hsic60m_clk[i]))
-   dev_dbg(dev, "Failed to get clock : %s : %ld\n",
-   clkname, PTR_ERR(omap->hsic60m_clk[i]));
+   if (IS_ERR(omap->hsic60m_clk[i])) {
+  

[PATCH v5 9/9] ARM: OMAP2+: Remove legacy_init_ehci_clk()

[Roger Quadros]

The necessary clock phandle for the EHCI clock is now provided
via device tree so we no longer need this legacy method.

Signed-off-by: Roger Quadros 
---
 arch/arm/mach-omap2/pdata-quirks.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/arch/arm/mach-omap2/pdata-quirks.c 
b/arch/arm/mach-omap2/pdata-quirks.c
index 39f020c..6a4e2d1 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -26,20 +26,6 @@ struct pdata_init {
void (*fn)(void);
 };
 
-/*
- * Create alias for USB host PHY clock.
- * Remove this when clock phandle can be provided via DT
- */
-static void __init __used legacy_init_ehci_clk(char *clkname)
-{
-   int ret;
-
-   ret = clk_add_alias("main_clk", NULL, clkname, NULL);
-   if (ret)
-   pr_err("%s:Failed to add main_clk alias to %s :%d\n",
-  __func__, clkname, ret);
-}
-
 #if IS_ENABLED(CONFIG_WL12XX)
 
 static struct wl12xx_platform_data wl12xx __initdata;
@@ -105,7 +91,6 @@ static void __init omap4_sdp_legacy_init(void)
 static void __init omap4_panda_legacy_init(void)
 {
omap4_panda_display_init_of();
-   legacy_init_ehci_clk("auxclk3_ck");
legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
 }
 #endif
@@ -113,7 +98,6 @@ static void __init omap4_panda_legacy_init(void)
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_uevm_legacy_init(void)
 {
-   legacy_init_ehci_clk("auxclk1_ck");
 }
 #endif
 
-- 
1.8.3.2

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[PATCH v5 3/9] mfd: omap-usb-host: Update DT clock binding information

[Roger Quadros]

The omap-usb-host driver expects certained named clocks.
Add this information to the DT binding document.

Use clock names as per function for reference clocks.

CC: Lee Jones 
CC: Samuel Ortiz 
Signed-off-by: Roger Quadros 
---
 .../devicetree/bindings/mfd/omap-usb-host.txt  | 23 ++
 drivers/mfd/omap-usb-host.c|  6 +++---
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt 
b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
index b381fa6..4721b2d 100644
--- a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
+++ b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
@@ -32,6 +32,29 @@ Optional properties:
 - single-ulpi-bypass: Must be present if the controller contains a single
   ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
 
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+
+- clock-names: should include:
+  For OMAP3
+  * "usbhost_120m_fck" - 120MHz Functional clock.
+
+  For OMAP4+
+  * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
+  * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock 
mux.
+  * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
+  * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
+  * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
+  * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
+  * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
+  * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
+  * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
+  * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
+  * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
+  * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
+  * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
+  * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
+
 Required properties if child node exists:
 
 - #address-cells: Must be 1
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 7202cc6..eeea6e6 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -713,21 +713,21 @@ static int usbhs_omap_probe(struct platform_device *pdev)
goto err_mem;
}
 
-   omap->xclk60mhsp1_ck = devm_clk_get(dev, "xclk60mhsp1_ck");
+   omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1");
if (IS_ERR(omap->xclk60mhsp1_ck)) {
ret = PTR_ERR(omap->xclk60mhsp1_ck);
dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
goto err_mem;
}
 
-   omap->xclk60mhsp2_ck = devm_clk_get(dev, "xclk60mhsp2_ck");
+   omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2");
if (IS_ERR(omap->xclk60mhsp2_ck)) {
ret = PTR_ERR(omap->xclk60mhsp2_ck);
dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
goto err_mem;
}
 
-   omap->init_60m_fclk = devm_clk_get(dev, "init_60m_fclk");
+   omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int");
if (IS_ERR(omap->init_60m_fclk)) {
ret = PTR_ERR(omap->init_60m_fclk);
dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
-- 
1.8.3.2

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[PATCH v5 5/9] ARM: dts: omap4: Update omap-usb-host node

[Roger Quadros]

The omap-usb-host driver expects a certain name for internal
and external reference clocks. Provide these clocks.

Signed-off-by: Roger Quadros 
---
 arch/arm/boot/dts/omap4.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d3f8a6e..39a05ce 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -697,6 +697,12 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+   clocks = <&init_60m_fclk>,
+<&xclk60mhsp1_ck>,
+<&xclk60mhsp2_ck>;
+   clock-names = "refclk_60m_int",
+ "refclk_60m_ext_p1",
+ "refclk_60m_ext_p2";
 
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3", "usb-ohci";
-- 
1.8.3.2

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[PATCH v5 1/9] mfd: omap-usb-host: Use resource managed clk_get()

[Roger Quadros]

Use devm_clk_get() instead of clk_get().

CC: Lee Jones 
CC: Samuel Ortiz 
Signed-off-by: Roger Quadros 
---
 drivers/mfd/omap-usb-host.c | 81 +
 1 file changed, 16 insertions(+), 65 deletions(-)

diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 142650f..1c9bca2 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -674,46 +674,46 @@ static int usbhs_omap_probe(struct platform_device *pdev)
 
omap->ehci_logic_fck = ERR_PTR(-EINVAL);
if (need_logic_fck) {
-   omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
+   omap->ehci_logic_fck = devm_clk_get(dev, "ehci_logic_fck");
if (IS_ERR(omap->ehci_logic_fck)) {
ret = PTR_ERR(omap->ehci_logic_fck);
dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
}
}
 
-   omap->utmi_p1_gfclk = clk_get(dev, "utmi_p1_gfclk");
+   omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk");
if (IS_ERR(omap->utmi_p1_gfclk)) {
ret = PTR_ERR(omap->utmi_p1_gfclk);
dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
-   goto err_p1_gfclk;
+   goto err_mem;
}
 
-   omap->utmi_p2_gfclk = clk_get(dev, "utmi_p2_gfclk");
+   omap->utmi_p2_gfclk = devm_clk_get(dev, "utmi_p2_gfclk");
if (IS_ERR(omap->utmi_p2_gfclk)) {
ret = PTR_ERR(omap->utmi_p2_gfclk);
dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
-   goto err_p2_gfclk;
+   goto err_mem;
}
 
-   omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
+   omap->xclk60mhsp1_ck = devm_clk_get(dev, "xclk60mhsp1_ck");
if (IS_ERR(omap->xclk60mhsp1_ck)) {
ret = PTR_ERR(omap->xclk60mhsp1_ck);
dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
-   goto err_xclk60mhsp1;
+   goto err_mem;
}
 
-   omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
+   omap->xclk60mhsp2_ck = devm_clk_get(dev, "xclk60mhsp2_ck");
if (IS_ERR(omap->xclk60mhsp2_ck)) {
ret = PTR_ERR(omap->xclk60mhsp2_ck);
dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
-   goto err_xclk60mhsp2;
+   goto err_mem;
}
 
-   omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
+   omap->init_60m_fclk = devm_clk_get(dev, "init_60m_fclk");
if (IS_ERR(omap->init_60m_fclk)) {
ret = PTR_ERR(omap->init_60m_fclk);
dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
-   goto err_init60m;
+   goto err_mem;
}
 
for (i = 0; i < omap->nports; i++) {
@@ -727,21 +727,21 @@ static int usbhs_omap_probe(struct platform_device *pdev)
 * platforms have all clocks and we can function without
 * them
 */
-   omap->utmi_clk[i] = clk_get(dev, clkname);
+   omap->utmi_clk[i] = devm_clk_get(dev, clkname);
if (IS_ERR(omap->utmi_clk[i]))
dev_dbg(dev, "Failed to get clock : %s : %ld\n",
clkname, PTR_ERR(omap->utmi_clk[i]));
 
snprintf(clkname, sizeof(clkname),
"usb_host_hs_hsic480m_p%d_clk", i + 1);
-   omap->hsic480m_clk[i] = clk_get(dev, clkname);
+   omap->hsic480m_clk[i] = devm_clk_get(dev, clkname);
if (IS_ERR(omap->hsic480m_clk[i]))
dev_dbg(dev, "Failed to get clock : %s : %ld\n",
clkname, PTR_ERR(omap->hsic480m_clk[i]));
 
snprintf(clkname, sizeof(clkname),
"usb_host_hs_hsic60m_p%d_clk", i + 1);
-   omap->hsic60m_clk[i] = clk_get(dev, clkname);
+   omap->hsic60m_clk[i] = devm_clk_get(dev, clkname);
if (IS_ERR(omap->hsic60m_clk[i]))
dev_dbg(dev, "Failed to get clock : %s : %ld\n",
clkname, PTR_ERR(omap->hsic60m_clk[i]));
@@ -784,7 +784,7 @@ static int usbhs_omap_probe(struct platform_device *pdev)
 
if (ret) {
dev_err(dev, "Failed to create DT children: %d\n", ret);
-   goto err_alloc;
+   goto err_mem;
}
 
} else {
@@ -792,40 +792,12 @@ static int usbhs_omap_probe(struct platform_device *pdev)
if (ret) {
dev_err(dev, "omap_usbhs_alloc_children failed: %d\n",
ret);
-   goto err_alloc;
+   goto err_mem;
}
}
 
return 0;
 
-err_alloc:
-   for (i = 0; i < omap->nports; i++) {
-  

Re: [PATCH v4 0/5] USB Host support for OMAP5 uEVM (for 3.14)

[Michele Paolino]

On 09/01/2014 12:08, Roger Quadros wrote:

Hi Michele,

Did you enable CONFIG_USB_EHCI_HCD_OMAP in the kernel config?
It is not enabled by default in omap2plus_defconfig.

Indeed it works.  Thank you!



cheers,
-roger

On 01/09/2014 04:34 PM, Michele Paolino wrote:

Hello Roger,

I'm testing your patch on an OMAP5430 EVM board. The ethernet is not working in 
my case. The kernel I'm using is (Tero Kristo's repo - branch 
3.13-rc7-dt-clks-v13). Is there something that I'm missing?

Here below you can find more info about my configuration:

boot error messages:
eth0: ERROR while getting interface flags: No such device
SIOCSIFADDR: No such device
eth0: ERROR while getting interface flags: No such device
SIOCADDRT: Network is unreachable

root@OMAP5:~# /usr/lib/klibc/bin/ipconfig eth0
ipconfig: eth0: SIOCGIFINDEX: No such device
/usr/lib/klibc/bin/ipconfig: no devices to configure

root@OMAP5:~# uname -a
Linux OMAP5 3.13.0-rc7-g2a4526d-dirty #0 SMP Wed Jan 8 10:41:48 CET 2014x

root@OMAP5:~# dmesg | grep eth
[1.661434] usbcore: registered new interface driver cdc_ether

Regards,


On 08/01/2014 07:15, Roger Quadros wrote:

Hi Benoit & Tony,

This patchset brings up USB Host ports and Ethernet port on
the OMAP5 uEVM board.

It depends on the TI Clock DT conversion patches [1] and is based
on 3.13-rc7

[1] - http://article.gmane.org/gmane.linux.ports.arm.kernel/289895

Changelog:

v4:
- Updated DT binding document for clock binding

v3:
- Rebased on top of 3.13-rc7

cheers,
-roger

Roger Quadros (5):
   mfd: omap-usb-host: Update DT clock binding information
   ARM: dts: OMAP5: Add 60MHz clock reference to USB Host module
   ARM: dts: omap4-panda: Provide USB PHY clock
   ARM: dts: omap5-uevm: Provide USB PHY clock
   ARM: OMAP2+: Remove legacy_init_ehci_clk()

  Documentation/devicetree/bindings/mfd/omap-usb-host.txt |  4 
  arch/arm/boot/dts/omap4-panda-common.dtsi   |  8 ++--
  arch/arm/boot/dts/omap5-uevm.dts|  8 ++--
  arch/arm/boot/dts/omap5.dtsi|  2 ++
  arch/arm/mach-omap2/pdata-quirks.c  | 16 
  5 files changed, 10 insertions(+), 28 deletions(-)



--
*Michele Paolino*, Virtualization R&D Engineer
Virtual Open Systems
/Open Source  KVM  Virtualization  Developments/
/Multicore Systems Virtualization Porting Services/
Web/:/ www.virtualopensystems. com 




--
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Re: [PATCH v4 0/5] USB Host support for OMAP5 uEVM (for 3.14)

[Roger Quadros]

Hi Michele,

Did you enable CONFIG_USB_EHCI_HCD_OMAP in the kernel config?
It is not enabled by default in omap2plus_defconfig.

cheers,
-roger

On 01/09/2014 04:34 PM, Michele Paolino wrote:
> Hello Roger,
> 
> I'm testing your patch on an OMAP5430 EVM board. The ethernet is not working 
> in my case. The kernel I'm using is (Tero Kristo's repo - branch 
> 3.13-rc7-dt-clks-v13). Is there something that I'm missing?
> 
> Here below you can find more info about my configuration:
> 
> boot error messages:
> eth0: ERROR while getting interface flags: No such device
> SIOCSIFADDR: No such device
> eth0: ERROR while getting interface flags: No such device
> SIOCADDRT: Network is unreachable
> 
> root@OMAP5:~# /usr/lib/klibc/bin/ipconfig eth0  
> ipconfig: eth0: SIOCGIFINDEX: No such device
> /usr/lib/klibc/bin/ipconfig: no devices to configure
> 
> root@OMAP5:~# uname -a
> Linux OMAP5 3.13.0-rc7-g2a4526d-dirty #0 SMP Wed Jan 8 10:41:48 CET 2014x
> 
> root@OMAP5:~# dmesg | grep eth
> [1.661434] usbcore: registered new interface driver cdc_ether
> 
> Regards,
> 
> 
> On 08/01/2014 07:15, Roger Quadros wrote:
>> Hi Benoit & Tony,
>>
>> This patchset brings up USB Host ports and Ethernet port on
>> the OMAP5 uEVM board.
>>
>> It depends on the TI Clock DT conversion patches [1] and is based
>> on 3.13-rc7
>>
>> [1] - http://article.gmane.org/gmane.linux.ports.arm.kernel/289895
>>
>> Changelog:
>>
>> v4:
>> - Updated DT binding document for clock binding
>>
>> v3:
>> - Rebased on top of 3.13-rc7
>>
>> cheers,
>> -roger
>>
>> Roger Quadros (5):
>>   mfd: omap-usb-host: Update DT clock binding information
>>   ARM: dts: OMAP5: Add 60MHz clock reference to USB Host module
>>   ARM: dts: omap4-panda: Provide USB PHY clock
>>   ARM: dts: omap5-uevm: Provide USB PHY clock
>>   ARM: OMAP2+: Remove legacy_init_ehci_clk()
>>
>>  Documentation/devicetree/bindings/mfd/omap-usb-host.txt |  4 
>>  arch/arm/boot/dts/omap4-panda-common.dtsi   |  8 ++--
>>  arch/arm/boot/dts/omap5-uevm.dts|  8 ++--
>>  arch/arm/boot/dts/omap5.dtsi|  2 ++
>>  arch/arm/mach-omap2/pdata-quirks.c  | 16 
>> 
>>  5 files changed, 10 insertions(+), 28 deletions(-)
>>
> 
> 
> -- 
> *Michele Paolino*, Virtualization R&D Engineer
> Virtual Open Systems
> /Open Source  KVM  Virtualization  Developments/
> /Multicore Systems Virtualization Porting Services/
> Web/:/ www.virtualopensystems. com 
> 
> 
> 

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DSS DT support for 3.14 probably not possible

[Tomi Valkeinen]

Hi Tony,

Unfortunately I think the DSS DT series will miss 3.14 merge window.

The code feels quite fine, but I'm still in the process of writing the
binding documentation and getting those reviewed. And that review could
of course lead to some new changes.

So if we're going for DT-only boot for 3.14, I guess the only option is
to create the quirk display platform data for all the boards...

 Tomi



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Description: OpenPGP digital signature

RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support

[Hiremath, Vaibhav]

> -Original Message-
> From: Valkeinen, Tomi
> Sent: Thursday, January 09, 2014 1:52 PM
> To: Hiremath, Vaibhav; Ivaylo Dimitrov
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-fb...@vger.kernel.org
> Subject: Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> 
> On 2014-01-09 07:06, Hiremath, Vaibhav wrote:
> 
> > I am seeing underflow issue on AM43x device if I use omapfb_vram argument.
> > Did you see this on OMAP?
> >
> > I am using "omapfb_vram=10M@0xA000", and I believe it is correct way
> of usage.
> 
> Hmm ok... The AM4x seems to have issues anyway, as we're seeing underflows
> easily in other situations also.
> 
> Well, there's a small difference in the allocation. The normal dma alloc uses
> dma_alloc_attrs() and passes DMA_ATTR_WRITE_COMBINE as a flag, whereas
> allocating from the absolute address just uses the piece of memory. I couldn't
> find how to set write-combine for the abs memory area.
> 
> Then again, that's for CPU caching, so I don't see why it would affect DSS as
> such (but that's still something we should measure, cpu read/write perf for
> normal and abs allocation).
> 
> The only thought I have is that somehow the reserved memory area is missing
> some configuration that is done for the rest of the memory. But that's purely 
> a
> guess, this is totally out of my area of expertise...
> 
> Vaibhav, just to be sure, can you run both with normal dma_alloc and with the
> reserve, and verify that the dispc register dumps are the same?
> I don't see how they could be different, but just to be sure.
> 

Will check and update you shortly.

Thanks,
Vaibhav
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