Re: [PATCH v8 4/8] can: c_can: Add syscon/regmap RAMINIT mechanism
Tomi, On 05/01/15 11:18, Tomi Valkeinen wrote: Hi Roger, On 14/11/14 20:09, Marc Kleine-Budde wrote: From: Roger Quadros rog...@ti.com Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver. To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM. Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register. This patch updates the syscon regmap using regmap_read + regmap_write. That's not a safe way to update the bits, as some other driver may touch the register between the read and write. The change has to be made using regmap_update_bits. We don't have other drivers using the register at the moment, but I presume we will sooner or later. I remember updating this after you pointed it out to me earlier, but it seems I picked up the older version while sending. :(. Thanks for pointing it again. I'll prepare a fix on top. cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Revert disabling of smc91x for n900
On Tue 2015-01-06 08:59:03, Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [150106 00:03]:
On Mon 2015-01-05 15:02:29, Tony Lindgren wrote:
Revert ARM: dts: Disable smc91x on n900 until bootloader
dependency is removed. We've now fixed the issues that
caused problems with uninitialized hardware depending on
the bootloader version. Mostly things got fixed with
the following commits:
9a894953a97b (ARM: dts: Fix bootloader version dependencies by muxing
n900 smc91x pins)
7d2911c43815 (net: smc91x: Fix gpios for device tree based booting)
Note that this only affects the early development boards
with Ethernet that we still have in a few automated boot
test systems.
Signed-off-by: Tony Lindgren t...@atomide.com
Normally, the early development boards should have separate dts file
(then include common parts), no?
In this case it won't matter. The GPMC hardware is there, the probe
just fails if no smsc91x is found.
Could you at least add a note to the dts file what is it? Because I
always thought it is a bug.
Sure, updated patch below. Can somebody please test boot it on
a production n900 too to make sure it no longer causes issues?
Actually... how do you manage your n900 to boot? Does it also boot
from 0x?
I believe I'm hitting dtb size limit (again), and 3.19-rc3 does not boot
unless I somehow make dtb smaller... like the patch below.
---
make dtb smaller so that it boots.
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 53f3ca0..82f4597 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -140,14 +140,6 @@
;
};
- ethernet_pins: pinmux_ethernet_pins {
- pinctrl-single,pins =
- OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN |
MUX_MODE4) /* gpmc_ncs3.gpio_54 */
- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4)
/* dss_data16.gpio_86 */
- OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)
/* uart3_rts_sd.gpio_164 */
- ;
- };
-
gpmc_pins: pinmux_gpmc_pins {
pinctrl-single,pins =
@@ -700,42 +692,6 @@
};
};
- ethernet@gpmc {
- compatible = smsc,lan91c94;
-
- status = disabled;
-
- interrupt-parent = gpio2;
- interrupts = 22 IRQ_TYPE_LEVEL_HIGH; /* gpio54 */
- reg = 1 0x300 0xf;/* 16 byte IO range at offset
0x300 */
- bank-width = 2;
- pinctrl-names = default;
- pinctrl-0 = ethernet_pins;
- power-gpios = gpio3 22 GPIO_ACTIVE_HIGH; /* gpio86 */
- reset-gpios = gpio6 4 GPIO_ACTIVE_HIGH; /* gpio164 */
- gpmc,device-width = 2;
- gpmc,sync-clk-ps = 0;
- gpmc,cs-on-ns = 0;
- gpmc,cs-rd-off-ns = 48;
- gpmc,cs-wr-off-ns = 24;
- gpmc,adv-on-ns = 0;
- gpmc,adv-rd-off-ns = 0;
- gpmc,adv-wr-off-ns = 0;
- gpmc,we-on-ns = 12;
- gpmc,we-off-ns = 18;
- gpmc,oe-on-ns = 12;
- gpmc,oe-off-ns = 48;
- gpmc,page-burst-access-ns = 0;
- gpmc,access-ns = 42;
- gpmc,rd-cycle-ns = 180;
- gpmc,wr-cycle-ns = 180;
- gpmc,bus-turnaround-ns = 0;
- gpmc,cycle2cycle-delay-ns = 0;
- gpmc,wait-monitoring-ns = 0;
- gpmc,clk-activation-ns = 0;
- gpmc,wr-access-ns = 0;
- gpmc,wr-data-mux-bus-ns = 12;
- };
};
mcspi1 {
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Re: [PATCH] serial: 8250: Make ISA ports optional
On Tuesday 06 January 2015 16:47:55 Peter Hurley wrote: On 01/06/2015 02:43 PM, Arnd Bergmann wrote: On Tuesday 06 January 2015 09:32:02 Peter Hurley wrote: On 01/06/2015 08:13 AM, Arnd Bergmann wrote: On Monday 05 January 2015 22:09:45 Peter Hurley wrote: Some arches have no need to create unprobed 8250 ports; these phantom ports are primarily required for ISA ports which have no probe mechanism or to provide non-operational ports for userspace to configure (via TIOCSSERIAL and TIOCSERCONFIG ioctls). Provide CONFIG_SERIAL_8250_PHANTOM_UARTS knob to disable phantom port registration; ie., CONFIG_SERIAL_8250_PHANTOM_UARTS=N only registers probed ports (ACPI/PNP, serial8250 platform devices, PCI, etc). Cc: Sebastian Andrzej Siewior bige...@linutronix.de Cc: Tony Lindgren t...@atomide.com Cc: Grant Likely grant.lik...@linaro.org Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Peter Hurley pe...@hurleysoftware.com The intent is definitely right, but I think a better approach is possible. I haven't tried it here, but how about moving the serial8250_init function into a separate module, along with all the other parts that are only used for ISA devices, but leaving the actual core (all exported symbols) in this file? Unfortunately, I don't see a way to remove the stacked initialization without risking tons of breakage. Since later probes can find an already-existing port and re-initialize it, the probe order is crucial. For example, a PCI probe can find an existing serial8250 platform device port, resulting in only one device node. I'm probably missing something important, by why would that be any different if the PCI driver gets loaded first and the ISA driver second? Well, the PCI driver would have the proper irq, for one. So, if the the platform driver re-initialized the port to the wrong irq... I see. So we must still ensure that the ISA driver either gets loaded before the PCI driver, or never. It is already closely coupled with the PNP driver, but I think we can still get to the point where you don't load the ISA driver at all if you only have platform 8250 ports that are not supposed to be reconfigurable. On most non-x86 machines, I would think we also want a way to build the PCI driver without that dependency. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
Hello,
On 2015-01-05 18:20, Nishanth Menon wrote:
On 13:19-20150105, Marek Szyprowski wrote:
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for r3p3, but it should be uniform for all revisions.
Reported-by: Nishanth Menon n...@ti.com
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5e65ca8dea62..0aeeaa95c42d 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -623,14 +623,14 @@ static void l2c310_resume(void)
unsigned revision;
/* restore pl310 setup */
- writel_relaxed(l2x0_saved_regs.tag_latency,
- base + L310_TAG_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.data_latency,
- base + L310_DATA_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.filter_end,
- base + L310_ADDR_FILTER_END);
- writel_relaxed(l2x0_saved_regs.filter_start,
- base + L310_ADDR_FILTER_START);
+ l2c_write_sec(l2x0_saved_regs.tag_latency, base,
+ L310_TAG_LATENCY_CTRL);
+ l2c_write_sec(l2x0_saved_regs.data_latency, base,
+ L310_DATA_LATENCY_CTRL);
+ l2c_write_sec(l2x0_saved_regs.filter_end, base,
+ L310_ADDR_FILTER_END);
+ l2c_write_sec(l2x0_saved_regs.filter_start, base,
+ L310_ADDR_FILTER_START);
revision = readl_relaxed(base + L2X0_CACHE_ID)
L2X0_CACHE_ID_RTL_MASK;
Do you need the following as well at this point in the patch series?
Agreed that the writes will disappear later in the series.
Right. Thanks for pointing this. I will send an updated version, which
will also fix the checkpatch --strict issues.
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 0aeeaa9..7afab37 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1135,28 +1135,28 @@ static void __init l2c310_of_parse(const struct
device_node *np,
of_property_read_u32_array(np, arm,tag-latency, tag, ARRAY_SIZE(tag));
if (tag[0] tag[1] tag[2])
- writel_relaxed(
+ l2c_write_sec(
L310_LATENCY_CTRL_RD(tag[0] - 1) |
L310_LATENCY_CTRL_WR(tag[1] - 1) |
L310_LATENCY_CTRL_SETUP(tag[2] - 1),
- l2x0_base + L310_TAG_LATENCY_CTRL);
+ l2x0_base, L310_TAG_LATENCY_CTRL);
of_property_read_u32_array(np, arm,data-latency,
data, ARRAY_SIZE(data));
if (data[0] data[1] data[2])
- writel_relaxed(
+ l2c_write_sec(
L310_LATENCY_CTRL_RD(data[0] - 1) |
L310_LATENCY_CTRL_WR(data[1] - 1) |
L310_LATENCY_CTRL_SETUP(data[2] - 1),
- l2x0_base + L310_DATA_LATENCY_CTRL);
+ l2x0_base, L310_DATA_LATENCY_CTRL);
of_property_read_u32_array(np, arm,filter-ranges,
filter, ARRAY_SIZE(filter));
if (filter[1]) {
- writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
- l2x0_base + L310_ADDR_FILTER_END);
- writel_relaxed((filter[0] ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
- l2x0_base + L310_ADDR_FILTER_START);
+ l2c_write_sec(ALIGN(filter[0] + filter[1], SZ_1M),
+ l2x0_base, L310_ADDR_FILTER_END);
+ l2c_write_sec((filter[0] ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
+ l2x0_base, L310_ADDR_FILTER_START);
}
ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, assoc, SZ_512K);
Best regards
--
Marek Szyprowski, PhD
Samsung RD Institute Poland
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Re: [PATCH] irqchip: omap-intc: fix legacy DMA regression
Am 06.01.2015 um 17:51 schrieb Felipe Balbi:
commit 55601c9f2467 (arm: omap: intc: switch over
to linear irq domain) introduced a regression with
SDMA legacy driver because that driver strictly depends
on INTC's IRQs starting at NR_IRQs. Aparently
irq_domain_add_linear() won't guarantee that, since we see
a 7 IRQs difference when booting with and without the
commit cited above.
Until arch/arm/plat-omap/dma.c is properly fixed, we
must maintain OMAP2/3 using irq_domain_add_legacy().
A FIXME note was added so people know to delete that
code once that legacy DMA driver is fixed up.
Fixes: 55601c9f2467 (arm: omap: intc: switch over to linear irq domain)
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/irqchip/irq-omap-intc.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c
index 3c970259c0eb..6ef88f56cf8d 100644
--- a/drivers/irqchip/irq-omap-intc.c
+++ b/drivers/irqchip/irq-omap-intc.c
@@ -263,7 +263,7 @@ static int __init omap_init_irq_of(struct device_node *node)
return ret;
}
-static int __init omap_init_irq_legacy(u32 base)
+static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
{
int j, irq_base;
@@ -277,7 +277,7 @@ static int __init omap_init_irq_legacy(u32 base)
irq_base = 0;
}
- domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
+ domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
irq_domain_simple_ops, NULL);
omap_irq_soft_reset();
@@ -301,10 +301,26 @@ static int __init omap_init_irq(u32 base, struct
device_node *node)
{
int ret;
- if (node)
+ /*
+* FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
+* depends is still not ready for linear IRQ domains; because of that
+* we need to temporarily blacklist OMAP2 and OMAP3 devices from using
+* linear IRQ Domain until that driver is finally fixed.
+*/
+ if (of_device_is_compatible(node, ti,omap2-intc) ||
+ of_device_is_compatible(node, ti,omap3-intc)) {
+ struct resource res;
+
+ if (of_address_to_resource(node, 0, res))
+ return -ENOMEM;
+
+ base = res.start;
+ ret = omap_init_irq_legacy(base, node);
+ } else if (node) {
ret = omap_init_irq_of(node);
- else
- ret = omap_init_irq_legacy(base);
+ } else {
+ ret = omap_init_irq_legacy(base, NULL);
+ }
if (ret == 0)
omap_irq_enable_protection();
Thanks, works on DM3730.
Peter
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Re: [PATCH] ARM: OMAP2+: hwmod: Fix _wait_target_ready() for hwmods without sysc
On 06/01/15 04:04, Paul Walmsley wrote:
Roger, Lokesh, could you try this one instead?
It passes all the basic tests here except it does not boot on the 4460
VAR-SOM-OM - unclear why at this point - but it would be good to see if it
works on your AM4372 boards, since I don't have that one.
Test logs are here:
http://www.pwsan.com/omap/testlogs/hwmod_skip_only_remap_v3.19-rc/20150105171744/
- Paul
From 4f2e13bd2181e0ebede3aabc484aa2339830748a Mon Sep 17 00:00:00 2001
From: Paul Walmsley p...@pwsan.com
Date: Mon, 5 Jan 2015 15:49:57 -0700
Subject: [PATCH] Only skip ioremap() if IP block does not have OCP header
registers. Experimental.
---
arch/arm/mach-omap2/omap_hwmod.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c
b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908dc5cf0..03df8833d399 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1938,6 +1938,8 @@ static int _reset(struct omap_hwmod *oh)
pr_debug(omap_hwmod: %s: resetting\n, oh-name);
if (oh-class-reset) {
+ WARN(!oh-_mpu_rt_va, Attempt to call custom reset with no MPU
register target ioremapped: %s,
+ oh-name);
Not part of $subject.
r = oh-class-reset(oh);
} else {
if (oh-rst_lines_cnt 0) {
@@ -2358,15 +2360,19 @@ static int of_dev_hwmod_lookup(struct device_node *np,
}
/**
- * _init_mpu_rt_base - populate the virtual address for a hwmod
+ * _init_mpu_rt_base - populate the MPU port and virtual address
* @oh: struct omap_hwmod * to locate the virtual address
* @data: (unused, caller should pass NULL)
* @index: index of the reg entry iospace in device tree
* @np: struct device_node * of the IP block's device node in the DT data
*
- * Cache the virtual address used by the MPU to access this IP block's
- * registers. This address is needed early so the OCP registers that
- * are part of the device's address space can be ioremapped properly.
+ * Cache the interconnect target port and the virtual address used by
+ * the MPU to access this IP block's registers. The address is needed
+ * early so the OCP registers that are part of the device's address
+ * space can be ioremapped properly. The presence or absence of the
+ * interconnect target port also indicates whether the hwmod code
+ * should wait for the IP block to indicate readiness after it is
+ * enabled.
*
* Returns 0 on success, -EINVAL if an invalid hwmod is passed, and
* -ENXIO on absent or invalid register target address space.
@@ -2385,6 +2391,13 @@ static int __init _init_mpu_rt_base(struct omap_hwmod
*oh, void *data,
if (oh-_int_flags _HWMOD_NO_MPU_PORT)
return -ENXIO;
+ /*
+ * If there's no need for the hwmod code to read or write to
+ * the IP block registers, bail out early before the ioremap()
+ */
+ if (!oh-class-sysc)
+ return 0;
+
mem = _find_mpu_rt_addr_space(oh);
if (!mem) {
pr_debug(omap_hwmod: %s: no MPU register target found\n,
@@ -2451,14 +2464,10 @@ static int __init _init(struct omap_hwmod *oh, void
*data)
oh-name, np-name);
}
- if (oh-class-sysc) {
- r = _init_mpu_rt_base(oh, NULL, index, np);
- if (r 0) {
- WARN(1, omap_hwmod: %s: doesn't have mpu register
target base\n,
- oh-name);
- return 0;
- }
- }
+ r = _init_mpu_rt_base(oh, NULL, index, np);
+ if (r 0)
+ pr_debug(omap_hwmod: %s: doesn't have mpu register target
base\n,
+ oh-name);
This is the real piece that fixes the issue.
r = _init_clocks(oh, NULL);
if (r 0) {
I've tested this patch on am43x-gp-evm, and it seems to fix the issue although
with some unpleasant warning messages.
So if we can get rid of the WARN() you can put my
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
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Re: [PATCH v11 3/9] ARM: l2c: Refactor the driver to use commit-like interface
Hello,
On 2015-01-05 18:22, Nishanth Menon wrote:
On 13:19-20150105, Marek Szyprowski wrote:
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring
latency and filter regs' patch]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 210 ++-
1 file changed, 115 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 0aeeaa95c42d..f9013320c8ce 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -41,12 +41,14 @@ struct l2c_init_data {
void (*enable)(void __iomem *, u32, unsigned);
void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
void (*save)(void __iomem *);
+ void (*configure)(void __iomem *);
struct outer_cache_fns outer_cache;
};
#define CACHE_LINE_SIZE 32
static void __iomem *l2x0_base;
+static const struct l2c_init_data *l2x0_data;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
@@ -106,6 +108,14 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
}
}
+static void l2c_configure(void __iomem *base)
+{
+ if (l2x0_data-configure)
+ l2x0_data-configure(base);
+
+ l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+}
+
/*
* Enable the L2 cache controller. This function must only be
* called when the cache controller is known to be disabled.
@@ -114,7 +124,12 @@ static void l2c_enable(void __iomem *base, u32 aux,
unsigned num_lock)
{
unsigned long flags;
- l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+ /* Do not touch the controller if already enabled. */
+ if (readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)
+ return;
+
+ l2x0_saved_regs.aux_ctrl = aux;
+ l2c_configure(base);
l2c_unlock(base, num_lock);
@@ -208,6 +223,11 @@ static void l2c_save(void __iomem *base)
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
}
+static void l2c_resume(void)
+{
+ l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data-num_lock);
+}
+
/*
* L2C-210 specific code.
*
@@ -288,14 +308,6 @@ static void l2c210_sync(void)
__l2c210_cache_sync(l2x0_base);
}
-static void l2c210_resume(void)
-{
- void __iomem *base = l2x0_base;
-
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN))
- l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
-}
-
static const struct l2c_init_data l2c210_data __initconst = {
.type = L2C-210,
.way_size_0 = SZ_8K,
@@ -309,7 +321,7 @@ static const struct l2c_init_data l2c210_data __initconst =
{
.flush_all = l2c210_flush_all,
.disable = l2c_disable,
.sync = l2c210_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -466,7 +478,7 @@ static const struct l2c_init_data l2c220_data = {
.flush_all = l2c220_flush_all,
.disable = l2c_disable,
.sync = l2c220_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -615,39 +627,29 @@ static void __init l2c310_save(void __iomem *base)
L310_POWER_CTRL);
}
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)) {
- unsigned revision;
-
- /* restore pl310 setup */
- l2c_write_sec(l2x0_saved_regs.tag_latency, base,
- L310_TAG_LATENCY_CTRL);
- l2c_write_sec(l2x0_saved_regs.data_latency, base,
- L310_DATA_LATENCY_CTRL);
- l2c_write_sec(l2x0_saved_regs.filter_end, base,
- L310_ADDR_FILTER_END);
- l2c_write_sec(l2x0_saved_regs.filter_start, base,
- L310_ADDR_FILTER_START);
-
- revision = readl_relaxed(base + L2X0_CACHE_ID)
-
[PATCH v12 8/9] ARM: EXYNOS: Add support for non-secure L2X0 resume
From: Tomasz Figa t.f...@samsung.com On Exynos SoCs it is necessary to resume operation of L2C early in assembly code, because otherwise certain systems will crash. This patch adds necessary code to non-secure resume handler. Signed-off-by: Tomasz Figa t.f...@samsung.com [rewrote the code accessing l2x0_saved_regs] Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com Acked-by: Arnd Bergmann a...@arndb.de Acked-by: Kukjin Kim kgene@samsung.com --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe..31d25834b9c4 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -16,6 +16,8 @@ */ #include linux/linkage.h +#include asm/asm-offsets.h +#include asm/hardware/cache-l2x0.h #include smc.h #define CPU_MASK 0xff00 @@ -74,6 +76,45 @@ ENTRY(exynos_cpu_resume_ns) mov r0, #SMC_CMD_C15RESUME dsb smc #0 +#ifdef CONFIG_CACHE_L2X0 + adr r0, 1f + ldr r2, [r0] + add r0, r2, r0 + + /* Check that the address has been initialised. */ + ldr r1, [r0, #L2X0_R_PHY_BASE] + teq r1, #0 + beq skip_l2x0 + + /* Check if controller has been enabled. */ + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne skip_l2x0 + + ldr r1, [r0, #L2X0_R_TAG_LATENCY] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + ldr r3, [r0, #L2X0_R_PREFETCH_CTRL] + mov r0, #SMC_CMD_L2X0SETUP1 + smc #0 + + /* Reload saved regs pointer because smc corrupts registers. */ + adr r0, 1f + ldr r2, [r0] + add r0, r2, r0 + + ldr r1, [r0, #L2X0_R_PWR_CTRL] + ldr r2, [r0, #L2X0_R_AUX_CTRL] + mov r0, #SMC_CMD_L2X0SETUP2 + smc #0 + + mov r0, #SMC_CMD_L2X0INVALL + smc #0 + + mov r1, #1 + mov r0, #SMC_CMD_L2X0CTRL + smc #0 +skip_l2x0: +#endif /* CONFIG_CACHE_L2X0 */ skip_cp15: b cpu_resume ENDPROC(exynos_cpu_resume_ns) @@ -83,3 +124,8 @@ cp15_save_diag: .globl cp15_save_power cp15_save_power: .long 0 @ cp15 power control + +#ifdef CONFIG_CACHE_L2X0 + .align +1: .long l2x0_saved_regs - . +#endif /* CONFIG_CACHE_L2X0 */ -- 1.9.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v12 7/9] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
From: Tomasz Figa t.f...@samsung.com
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec and .configure callbacks is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[added comment and reworked unconditional call to SMC_CMD_L2X0INVALL]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Kukjin Kim kgene@samsung.com
---
arch/arm/mach-exynos/firmware.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 766f57d2f029..4791a3cc00f9 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
#include asm/cacheflush.h
#include asm/cputype.h
#include asm/firmware.h
+#include asm/hardware/cache-l2x0.h
#include asm/suspend.h
#include mach/map.h
@@ -136,6 +137,43 @@ static const struct firmware_ops exynos_firmware_ops = {
.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_resume : NULL,
};
+static void exynos_l2_write_sec(unsigned long val, unsigned reg)
+{
+ static int l2cache_enabled;
+
+ switch (reg) {
+ case L2X0_CTRL:
+ if (val L2X0_CTRL_EN) {
+ /*
+* Before the cache can be enabled, due to firmware
+* design, SMC_CMD_L2X0INVALL must be called.
+*/
+ if (!l2cache_enabled) {
+ exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+ l2cache_enabled = 1;
+ }
+ } else {
+ l2cache_enabled = 0;
+ }
+ exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
+ break;
+
+ case L2X0_DEBUG_CTRL:
+ exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
+ break;
+
+ default:
+ WARN_ONCE(1, %s: ignoring write to reg 0x%x\n, __func__, reg);
+ }
+}
+
+static void exynos_l2_configure(const struct l2x0_regs *regs)
+{
+ exynos_smc(SMC_CMD_L2X0SETUP1, regs-tag_latency, regs-data_latency,
+ regs-prefetch_ctrl);
+ exynos_smc(SMC_CMD_L2X0SETUP2, regs-pwr_ctrl, regs-aux_ctrl, 0);
+}
+
void __init exynos_firmware_init(void)
{
struct device_node *nd;
@@ -155,4 +193,16 @@ void __init exynos_firmware_init(void)
pr_info(Running under secure firmware.\n);
register_firmware_ops(exynos_firmware_ops);
+
+ /*
+* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
+* running under secure firmware, require certain registers of L2
+* cache controller to be written in secure mode. Here .write_sec
+* callback is provided to perform necessary SMC calls.
+*/
+ if (IS_ENABLED(CONFIG_CACHE_L2X0)
+ read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+ outer_cache.write_sec = exynos_l2_write_sec;
+ outer_cache.configure = exynos_l2_configure;
+ }
}
--
1.9.2
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[PATCH v12 6/9] ARM: l2c: Add support for overriding prefetch settings
From: Tomasz Figa t.f...@samsung.com
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in the
driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[mszyprow: rebased onto v3.18-rc1, added error message when prefetch related
dt property has been provided without any value]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/mm/cache-l2x0.c | 54 ++
2 files changed, 64 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b/Documentation/devicetree/bindings/arm/l2cc.txt
index 292ef7ca3058..0dbabe9a6b0a 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -57,6 +57,16 @@ Optional properties:
- cache-id-part: cache id part number to be used if it is not present
on hardware
- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if
non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
Example:
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5288153f28b8..01de13809454 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1169,6 +1169,8 @@ static void __init l2c310_of_parse(const struct
device_node *np,
u32 tag[3] = { 0, 0, 0 };
u32 filter[2] = { 0, 0 };
u32 assoc;
+ u32 prefetch;
+ u32 val;
int ret;
of_property_read_u32_array(np, arm,tag-latency, tag, ARRAY_SIZE(tag));
@@ -1214,6 +1216,58 @@ static void __init l2c310_of_parse(const struct
device_node *np,
assoc);
break;
}
+
+ prefetch = l2x0_saved_regs.prefetch_ctrl;
+
+ ret = of_property_read_u32(np, arm,double-linefill, val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,double-linefill property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,double-linefill-incr, val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,double-linefill-incr property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,double-linefill-wrap, val);
+ if (ret == 0) {
+ if (!val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,double-linefill-wrap property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,prefetch-drop, val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_PREFETCH_DROP;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,prefetch-drop property value is
missing\n);
+ }
+
+ ret = of_property_read_u32(np, arm,prefetch-offset, val);
+ if (ret == 0) {
+ prefetch = ~L310_PREFETCH_CTRL_OFFSET_MASK;
+ prefetch |= val L310_PREFETCH_CTRL_OFFSET_MASK;
+ } else if (ret != -EINVAL) {
+ pr_err(L2C-310 OF arm,prefetch-offset property value is
missing\n);
+ }
+
+ l2x0_saved_regs.prefetch_ctrl = prefetch;
}
static const struct l2c_init_data of_l2c310_data __initconst = {
--
1.9.2
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[PATCH v12 9/9] ARM: dts: exynos4: Add nodes for L2 cache controller
From: Tomasz Figa t.f...@samsung.com
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Kukjin Kim kgene@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63c8070..8e45ea44317e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -81,6 +81,15 @@
reg = 0x10023CA0 0x20;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = arm,pl310-cache;
+ reg = 0x10502000 0x1000;
+ cache-unified;
+ cache-level = 2;
+ arm,tag-latency = 2 2 1;
+ arm,data-latency = 2 2 1;
+ };
+
gic: interrupt-controller@1049 {
cpu-offset = 0x8000;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b70402e943..8bc97c415c9a 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -54,6 +54,20 @@
reg = 0x10023CA0 0x20;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = arm,pl310-cache;
+ reg = 0x10502000 0x1000;
+ cache-unified;
+ cache-level = 2;
+ arm,tag-latency = 2 2 1;
+ arm,data-latency = 3 2 1;
+ arm,double-linefill = 1;
+ arm,double-linefill-incr = 0;
+ arm,double-linefill-wrap = 1;
+ arm,prefetch-drop = 1;
+ arm,prefetch-offset = 7;
+ };
+
clock: clock-controller@1003 {
compatible = samsung,exynos4412-clock;
reg = 0x1003 0x2;
--
1.9.2
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[PATCH v12 3/9] ARM: l2c: Refactor the driver to use commit-like interface
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring
latency and filter regs' patch]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mm/cache-l2x0.c | 212 ++-
1 file changed, 116 insertions(+), 96 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b83c401ca50c..dde0d54ac41e 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -41,12 +41,14 @@ struct l2c_init_data {
void (*enable)(void __iomem *, u32, unsigned);
void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
void (*save)(void __iomem *);
+ void (*configure)(void __iomem *);
struct outer_cache_fns outer_cache;
};
#define CACHE_LINE_SIZE32
static void __iomem *l2x0_base;
+static const struct l2c_init_data *l2x0_data;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
@@ -106,6 +108,14 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
}
}
+static void l2c_configure(void __iomem *base)
+{
+ if (l2x0_data-configure)
+ l2x0_data-configure(base);
+
+ l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+}
+
/*
* Enable the L2 cache controller. This function must only be
* called when the cache controller is known to be disabled.
@@ -114,7 +124,12 @@ static void l2c_enable(void __iomem *base, u32 aux,
unsigned num_lock)
{
unsigned long flags;
- l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+ /* Do not touch the controller if already enabled. */
+ if (readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)
+ return;
+
+ l2x0_saved_regs.aux_ctrl = aux;
+ l2c_configure(base);
l2c_unlock(base, num_lock);
@@ -208,6 +223,11 @@ static void l2c_save(void __iomem *base)
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
}
+static void l2c_resume(void)
+{
+ l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data-num_lock);
+}
+
/*
* L2C-210 specific code.
*
@@ -288,14 +308,6 @@ static void l2c210_sync(void)
__l2c210_cache_sync(l2x0_base);
}
-static void l2c210_resume(void)
-{
- void __iomem *base = l2x0_base;
-
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN))
- l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
-}
-
static const struct l2c_init_data l2c210_data __initconst = {
.type = L2C-210,
.way_size_0 = SZ_8K,
@@ -309,7 +321,7 @@ static const struct l2c_init_data l2c210_data __initconst =
{
.flush_all = l2c210_flush_all,
.disable = l2c_disable,
.sync = l2c210_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -466,7 +478,7 @@ static const struct l2c_init_data l2c220_data = {
.flush_all = l2c220_flush_all,
.disable = l2c_disable,
.sync = l2c220_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -615,39 +627,29 @@ static void __init l2c310_save(void __iomem *base)
L310_POWER_CTRL);
}
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)) {
- unsigned revision;
-
- /* restore pl310 setup */
- l2c_write_sec(l2x0_saved_regs.tag_latency, base,
- L310_TAG_LATENCY_CTRL);
- l2c_write_sec(l2x0_saved_regs.data_latency, base,
- L310_DATA_LATENCY_CTRL);
- l2c_write_sec(l2x0_saved_regs.filter_end, base,
- L310_ADDR_FILTER_END);
- l2c_write_sec(l2x0_saved_regs.filter_start, base,
- L310_ADDR_FILTER_START);
-
- revision = readl_relaxed(base + L2X0_CACHE_ID)
- L2X0_CACHE_ID_RTL_MASK;
-
-
[PATCH v12 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for r3p3, but it should be uniform for all revisions.
Reported-by: Nishanth Menon n...@ti.com
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mm/cache-l2x0.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5e65ca8dea62..b83c401ca50c 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -623,14 +623,14 @@ static void l2c310_resume(void)
unsigned revision;
/* restore pl310 setup */
- writel_relaxed(l2x0_saved_regs.tag_latency,
- base + L310_TAG_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.data_latency,
- base + L310_DATA_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.filter_end,
- base + L310_ADDR_FILTER_END);
- writel_relaxed(l2x0_saved_regs.filter_start,
- base + L310_ADDR_FILTER_START);
+ l2c_write_sec(l2x0_saved_regs.tag_latency, base,
+ L310_TAG_LATENCY_CTRL);
+ l2c_write_sec(l2x0_saved_regs.data_latency, base,
+ L310_DATA_LATENCY_CTRL);
+ l2c_write_sec(l2x0_saved_regs.filter_end, base,
+ L310_ADDR_FILTER_END);
+ l2c_write_sec(l2x0_saved_regs.filter_start, base,
+ L310_ADDR_FILTER_START);
revision = readl_relaxed(base + L2X0_CACHE_ID)
L2X0_CACHE_ID_RTL_MASK;
@@ -1135,28 +1135,28 @@ static void __init l2c310_of_parse(const struct
device_node *np,
of_property_read_u32_array(np, arm,tag-latency, tag, ARRAY_SIZE(tag));
if (tag[0] tag[1] tag[2])
- writel_relaxed(
+ l2c_write_sec(
L310_LATENCY_CTRL_RD(tag[0] - 1) |
L310_LATENCY_CTRL_WR(tag[1] - 1) |
L310_LATENCY_CTRL_SETUP(tag[2] - 1),
- l2x0_base + L310_TAG_LATENCY_CTRL);
+ l2x0_base, L310_TAG_LATENCY_CTRL);
of_property_read_u32_array(np, arm,data-latency,
data, ARRAY_SIZE(data));
if (data[0] data[1] data[2])
- writel_relaxed(
+ l2c_write_sec(
L310_LATENCY_CTRL_RD(data[0] - 1) |
L310_LATENCY_CTRL_WR(data[1] - 1) |
L310_LATENCY_CTRL_SETUP(data[2] - 1),
- l2x0_base + L310_DATA_LATENCY_CTRL);
+ l2x0_base, L310_DATA_LATENCY_CTRL);
of_property_read_u32_array(np, arm,filter-ranges,
filter, ARRAY_SIZE(filter));
if (filter[1]) {
- writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
- l2x0_base + L310_ADDR_FILTER_END);
- writel_relaxed((filter[0] ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
- l2x0_base + L310_ADDR_FILTER_START);
+ l2c_write_sec(ALIGN(filter[0] + filter[1], SZ_1M),
+ l2x0_base, L310_ADDR_FILTER_END);
+ l2c_write_sec((filter[0] ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
+ l2x0_base, L310_ADDR_FILTER_START);
}
ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, assoc, SZ_512K);
--
1.9.2
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[PATCH v12 4/9] ARM: l2c: Add interface to ask hypervisor to configure L2C
From: Tomasz Figa t.f...@samsung.com
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware according to
specified parameters. This patch adds such.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/include/asm/outercache.h | 3 +++
arch/arm/mm/cache-l2x0.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 891a56b35bcf..563b92fc2f41 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -23,6 +23,8 @@
#include linux/types.h
+struct l2x0_regs;
+
struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
@@ -36,6 +38,7 @@ struct outer_cache_fns {
/* This is an ARM L2C thing */
void (*write_sec)(unsigned long, unsigned);
+ void (*configure)(const struct l2x0_regs *);
};
extern struct outer_cache_fns outer_cache;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index dde0d54ac41e..5288153f28b8 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -110,6 +110,11 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
static void l2c_configure(void __iomem *base)
{
+ if (outer_cache.configure) {
+ outer_cache.configure(l2x0_saved_regs);
+ return;
+ }
+
if (l2x0_data-configure)
l2x0_data-configure(base);
@@ -910,6 +915,7 @@ static int __init __l2c_init(const struct l2c_init_data
*data,
fns = data-outer_cache;
fns.write_sec = outer_cache.write_sec;
+ fns.configure = outer_cache.configure;
if (data-fixup)
data-fixup(l2x0_base, cache_id, fns);
--
1.9.2
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[PATCH v12 0/9] Enable L2 cache support on Exynos4210/4x12 SoCs
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+ platforms by moving l2cache initialization to
common code. This will resolve too early call to l2cache init, what might
cause kmalloc failure in code added in next patches.
Next patch fixes access method to latency and filter settings in l2cache
driver.
Next four patches extend existing support for secure write in L2C driver
to account for design of secure firmware running on Exynos. Namely:
1) direct read access to certain registers is needed on Exynos, because
secure firmware calls set several registers at once,
2) not all boards are running secure firmware, so .write_sec callback
needs to be installed in Exynos firmware ops initialization code,
3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
is not allowed and so must use l2c_write_sec as well,
4) on certain boards, default value of prefetch register is incorrect
and must be overridden at L2C initialization.
For boards running with firmware that provides access to individual
L2C registers this series should introduce no functional changes. However
since the driver is widely used on other platforms I'd like to kindly ask
any interested people for testing.
Further three patches add implementation of .write_sec and .configure
callbacks for Exynos secure firmware and necessary DT nodes to enable
L2 cache.
Changes in this version tested on Exynos4412-based TRATS2 and OdroidU3+
boards (both with secure firmware). There should be no functional change
for Exynos boards running without secure firmware. OMAP based platforms
were tested by Nishanth Menon and Tony Lindgren.
Depends on:
- v3.19-rc2
Changelog:
Changes since v11:
(https://lkml.org/lkml/2015/1/5/254)
- Added changes suggested by Nishanth to 'ARM: l2c: use l2c_write_sec()
for restoring latency and filter regs' patch
- Fixed 'checkpatch --strict' issues
- Added Nishanth's and Tony's acked/tested tags
Changes since v10:
(https://lkml.org/lkml/2014/12/23/151)
- Added patch, which fixes access method to latency and filter settings
in l2cache
Changes since v9:
(https://lkml.org/lkml/2014/11/17/217)
- Rebased onto vanilla v3.19-rc1
- Added patch for Omap2+ (move l2cache initialization to common code), what
fixes too early initialization (kmalloc failure)
Changes since v8:
(http://lkml.org/lkml/2014/11/13/263)
- Rebased onto vanilla v3.18-rc3 and added required includes, which were
previously added by other patches
- Added Acked-by tags for Exynos part
Changes since v7:
(https://lkml.org/lkml/2014/10/29/158)
- rebased onto arm-soc/for-next kernel tree (depends on patches merged to
v3.18-rc3 and arm-soc/samsung/pm2 branch)
- removed 'ARM: l2c: unify L2C-310 OF initialization error messages' patch
(no longer needed)
Changes since v6:
(https://lkml.org/lkml/2014/10/27/233)
- changed PL310 to L2C-310 prefix in error messages
- added patch shortening the error message about incorrect associativity
Changes since v5:
(https://lkml.org/lkml/2014/9/24/364)
- rebased onto v3.18-rc2
- added error message about missing properties values
Changes since v4:
(https://lkml.org/lkml/2014/8/26/461)
- rewrote the code accessing l2x0_saved_regs from assembly code
- added comment and reworked unconditional call to SMC_CMD_L2X0INVALL
Patch summary:
Marek Szyprowski (2):
ARM: OMAP2+: use common l2cache initialization code
ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
Tomasz Figa (7):
ARM: l2c: Refactor the driver to use commit-like interface
ARM: l2c: Add interface to ask hypervisor to configure L2C
ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
not NULL
ARM: l2c: Add support for overriding prefetch settings
ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
ARM: EXYNOS: Add support for non-secure L2X0 resume
ARM: dts: exynos4: Add nodes for L2 cache controller
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
arch/arm/include/asm/outercache.h | 3 +
arch/arm/kernel/irq.c | 3 +-
arch/arm/mach-exynos/firmware.c| 50 +
arch/arm/mach-exynos/sleep.S | 46 +
arch/arm/mach-omap2/board-generic.c| 6 +
arch/arm/mach-omap2/common.h | 8 +
arch/arm/mach-omap2/omap4-common.c | 16 +-
arch/arm/mm/cache-l2x0.c | 272 -
11 files changed, 325 insertions(+), 112 deletions(-)
--
1.9.2
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More
[PATCH v12 5/9] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL
From: Tomasz Figa t.f...@samsung.com
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index ad857bada96c..350f188c92d2 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -109,7 +109,8 @@ void __init init_IRQ(void)
if (IS_ENABLED(CONFIG_OF) IS_ENABLED(CONFIG_CACHE_L2X0)
(machine_desc-l2c_aux_mask || machine_desc-l2c_aux_val)) {
- outer_cache.write_sec = machine_desc-l2c_write_sec;
+ if (!outer_cache.write_sec)
+ outer_cache.write_sec = machine_desc-l2c_write_sec;
ret = l2x0_of_init(machine_desc-l2c_aux_val,
machine_desc-l2c_aux_mask);
if (ret)
--
1.9.2
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Re: [PATCH v11 1/9] ARM: OMAP2+: use common l2cache initialization code
2015-01-06 5:25 GMT+09:00 Arnd Bergmann a...@arndb.de: On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote: DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened Device Tree)) + .l2c_aux_val= OMAP_L2C_AUX_CTRL, + .l2c_aux_mask = 0xcf9f, + .l2c_write_sec = omap4_l2c310_write_sec, .reserve= omap_reserve, .smp= smp_ops(omap4_smp_ops), .map_io = omap4_map_io, Could we also get those values into the dts files? Clearly we can't remove them here without breaking compatibility with old dtbs, but it would be nice to have all new dtbs do the right thing. Sounds like a good next step after merging this series. :) Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v12 1/9] ARM: OMAP2+: use common l2cache initialization code
This patch implements generic DT L2C initialisation (the one from
init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/board-generic.c | 6 ++
arch/arm/mach-omap2/common.h| 8
arch/arm/mach-omap2/omap4-common.c | 16 +---
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..c5c480b76da5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -171,6 +171,9 @@ static const char *const omap4_boards_compat[] __initconst
= {
};
DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec = omap4_l2c310_write_sec,
.reserve= omap_reserve,
.smp= smp_ops(omap4_smp_ops),
.map_io = omap4_map_io,
@@ -214,6 +217,9 @@ static const char *const am43_boards_compat[] __initconst =
{
};
DT_MACHINE_START(AM43_DT, Generic AM43 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec = omap4_l2c310_write_sec,
.map_io = am33xx_map_io,
.init_early = am43xx_init_early,
.init_late = am43xx_init_late,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..2610c9f8d29f 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -35,6 +35,7 @@
#include linux/irqchip/irq-omap-intc.h
#include asm/proc-fns.h
+#include asm/hardware/cache-l2x0.h
#include i2c.h
#include serial.h
@@ -94,11 +95,18 @@ extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);
#ifdef CONFIG_CACHE_L2X0
int omap_l2_cache_init(void);
+#define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \
+L310_AUX_CTRL_DATA_PREFETCH | \
+L310_AUX_CTRL_INSTR_PREFETCH)
+void omap4_l2c310_write_sec(unsigned long val, unsigned reg);
#else
static inline int omap_l2_cache_init(void)
{
return 0;
}
+
+#define OMAP_L2C_AUX_CTRL 0
+#define omap4_l2c310_write_sec NULL
#endif
extern void omap5_realtime_timer_init(void);
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44abe49b..fe99ceff2e2d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -166,7 +166,7 @@ void __iomem *omap4_get_l2cache_base(void)
return l2cache_base;
}
-static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
+void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
{
unsigned smc_op;
@@ -201,24 +201,10 @@ static void omap4_l2c310_write_sec(unsigned long val,
unsigned reg)
int __init omap_l2_cache_init(void)
{
- u32 aux_ctrl;
-
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
if (WARN_ON(!l2cache_base))
return -ENOMEM;
-
- /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
- aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
- L310_AUX_CTRL_DATA_PREFETCH |
- L310_AUX_CTRL_INSTR_PREFETCH;
-
- outer_cache.write_sec = omap4_l2c310_write_sec;
- if (of_have_populated_dt())
- l2x0_of_init(aux_ctrl, 0xcf9f);
- else
- l2x0_init(l2cache_base, aux_ctrl, 0xcf9f);
-
return 0;
}
#endif
--
1.9.2
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Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
On 17:42-20150107, Marc Zyngier wrote: As for the patches, they are on top of 3.19-rc3. Applied the 21 patches and gave a quick dry run on various boards BASE = v3.19-rc3 + 1 uImage+dtb patch for IRQ = v3.19-rc3 + irq series NOTE: I am yet to dig in deeper to figure out which platform may have valid regressions etc. will do that tomorrow. meanwhile, some raw test results below: +++v3.19-rc3 - BOOT TEST+++ boot 1: am335x-evm: BOOT: PASS: http://slexy.org/raw/s2IOPX99Ty 2: am335x-sk: BOOT: FAIL: http://slexy.org/raw/s2dzt0lTF7 3: am3517-evm: BOOT: PASS: http://slexy.org/raw/s23yAMKuRx 4: am37x-evm: BOOT: PASS: http://slexy.org/raw/s20vsYwsYQ 5: am437x-sk: BOOT: PASS: http://slexy.org/raw/s2QgujFs6l 6:am43xx-epos: BOOT: PASS: http://slexy.org/raw/s2QHVg9XcB 7: am43xx-gpevm: BOOT: PASS: http://slexy.org/raw/s2Ep5DEQuk 8:BeagleBoard-X15(am57xx-evm): BOOT: PASS: http://slexy.org/raw/s20STBNTs9 9: BeagleBoard-XM: BOOT: PASS: http://slexy.org/raw/s2UhG6u7yM 10:beagleboard-vanilla: BOOT: PASS: http://slexy.org/raw/s2QB7ECFKw 11: beaglebone-black: BOOT: PASS: http://slexy.org/raw/s20iAe7yTa 12: beaglebone: BOOT: PASS: http://slexy.org/raw/s20Uui1gkn 13: craneboard: BOOT: PASS: http://slexy.org/raw/s21DcY6gn4 14: dra72x-evm: BOOT: PASS: http://slexy.org/raw/s2qj7IvmaV 15: dra7xx-evm: BOOT: PASS: http://slexy.org/raw/s20lLxN8bR 16: OMAP3430-Labrador(LDP): BOOT: PASS: http://slexy.org/raw/s20GmT9ASX 17: n900: BOOT: FAIL: http://slexy.org/raw/s2riSEzfea 18: omap5-evm: BOOT: PASS: http://slexy.org/raw/s21adCD3Js 19: pandaboard-es: BOOT: PASS: http://slexy.org/raw/s21Am3vEzM 20: pandaboard-vanilla: BOOT: PASS: http://slexy.org/raw/s2XLmW2ONB 21:sdp2430: BOOT: PASS: http://slexy.org/raw/s21ehzlzyv 22:sdp3430: BOOT: PASS: http://slexy.org/raw/s24gh1VUnl 23:sdp4430: BOOT: PASS: http://slexy.org/raw/s2HfgkFfOx TOTAL = 23 boards, Booted Boards = 21, No Boot boards = 2 +++ IRQ - BOOT TEST+++ boot 1: am335x-evm: BOOT: PASS: http://slexy.org/raw/s21411sejg 2: am335x-sk: BOOT: PASS: http://slexy.org/raw/s209N4Tu4E 3: am3517-evm: BOOT: PASS: http://slexy.org/raw/s2Shbhciy8 4: am37x-evm: BOOT: PASS: http://slexy.org/raw/s20wfqH0Wo 5: am437x-sk: BOOT: PASS: http://slexy.org/raw/s21uAXcB12 6:am43xx-epos: BOOT: PASS: http://slexy.org/raw/s26MGCZz0i 7: am43xx-gpevm: BOOT: PASS: http://slexy.org/raw/s2c8IGmWfB 8:BeagleBoard-X15(am57xx-evm): BOOT: FAIL: http://slexy.org/raw/s2u1yV4hHK 9: BeagleBoard-XM: BOOT: PASS: http://slexy.org/raw/s20zzOBKWJ 10:beagleboard-vanilla: BOOT: PASS: http://slexy.org/raw/s2wffxWVGa 11: beaglebone-black: BOOT: PASS: http://slexy.org/raw/s2Yshc0Vkw 12: beaglebone: BOOT: PASS: http://slexy.org/raw/s2Ki0ohBVf 13: craneboard: BOOT: PASS: http://slexy.org/raw/s2GVlDWkzP 14: dra72x-evm: BOOT: PASS: http://slexy.org/raw/s2dfZIVZ42 15: dra7xx-evm: BOOT: PASS: http://slexy.org/raw/s25UqvqVna 16: OMAP3430-Labrador(LDP): BOOT: PASS: http://slexy.org/raw/s20plEBPRB 17: n900: BOOT: FAIL: http://slexy.org/raw/s20zeM6YUP 18: omap5-evm: BOOT: PASS: http://slexy.org/raw/s2JOb4VEGJ 19: pandaboard-es: BOOT: PASS: http://slexy.org/raw/s20jCqY4OV 20: pandaboard-vanilla: BOOT: PASS: http://slexy.org/raw/s21TuquMeN 21:sdp2430: BOOT: PASS: http://slexy.org/raw/s20z1S6w1a 22:sdp3430: BOOT: PASS: http://slexy.org/raw/s20SJo6BqV 23:sdp4430: BOOT: PASS: http://slexy.org/raw/s204Bn9azX TOTAL = 23 boards, Booted Boards = 21, No Boot boards = 2 +++v3.19-rc3 - POWER TEST+++ power 1: am335x-evm: BOOT: PASS: err=10 warn=24, CPUFreq: PASS, CPUIdle: N/A: http://slexy.org/raw/s20t02tklu 2: am335x-sk: BOOT: FAIL: http://slexy.org/raw/s2HX7WisAk 3: am3517-evm: BOOT: FAIL: http://slexy.org/raw/s2mdCPTUBw 4: am37x-evm: BOOT: FAIL: http://slexy.org/raw/s2beWlmPMy 5: am437x-sk: BOOT: PASS: crit=2 err=12 warn=25, CPUFreq: N/A, CPUIdle: N/A: http://slexy.org/raw/s2Z0QTrATC 6:am43xx-epos: BOOT: PASS: crit=2 err=15 warn=26, CPUFreq: N/A, CPUIdle: N/A: http://slexy.org/raw/s21VqMaKE5 7: am43xx-gpevm: BOOT: PASS: crit=2 err=12 warn=25, CPUFreq: N
Re: [PATCH 00/11] ARM: OMAP3: legacy clock data move under clk driver
* Tero Kristo t-kri...@ti.com [141216 08:22]: Hi, These patches move the legacy clock data for omap3 under drivers/clk/ti. After these patches are applied, it should be possible to get rid of clk-private.h (long pending project for Mike.) Testing done (on top of 3.18-rc1): omap3-beagle: boot / suspend-resume (ret/off) / cpuidle (ret/off) omap3-beagle-xm: boot upto fs mount (see note below) sdp3430: boot n900: boot Note: beagle-xm failed with FS mount on the board I have access to, but this happens with clean 3.18-rc1 and linux-next also at the moment. The board has probably corrupted filesystem image but I am unable to fix this atm (remote board.) Test branch: tree: https://github.com/t-kristo/linux-pm.git branch: 3.18-rc1-omap3-clk-rework Great, hopefully this will finally allow Mike to make the generic struct clk private to drivers/clk :) Seems to boot just fine based on a quick legacy booting test on n900. Mike, assuming no other issues, can you please apply these into a immutable branch against v3.19-rc1 that Paul and I can also merge in as needed? Please also feel free to add: Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: am437x-sk-evm: Hook dcdc2 as the cpu0-supply
* Felipe Balbi ba...@ti.com [141222 12:41]: On Thu, Dec 04, 2014 at 09:24:39AM -0600, Felipe Balbi wrote: From: Dave Gerlach d-gerl...@ti.com Hook dcdc2 as the cpu0-supply. Signed-off-by: Dave Gerlach d-gerl...@ti.com Signed-off-by: Felipe Balbi ba...@ti.com btw, before sending this, I tested on my AM437x Starter Kit, so Tested-by: Felipe Balbi ba...@ti.com Applying into omap-for-v3.20/dt thanks. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: am57xx-beagle-x15: Add dual ethernet
* Felipe Balbi ba...@ti.com [141204 13:05]: Add CPSW DT binding to beagle X15 DTS in order to get ethernet working with this board. Note that we're also adding sleep state which will place all pins in mux mode 15 - which means driver off - thus conserving power. Signed-off-by: Nishanth Menon n...@ti.com Signed-off-by: Sekhar Nori nsek...@ti.com Signed-off-by: Felipe Balbi ba...@ti.com --- Changes since v1: - removed duplicated SoB from myself - Fixed s/Slave 1/Slave2/ in one comment - slightly improved commit log Applying into omap-for-v3.20/dt thanks. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/6] arm: boot: dts: am437x-sk: DTS pinmux fixes
* Felipe Balbi ba...@ti.com [141204 09:09]: Hi, On Thu, Dec 04, 2014 at 11:04:15AM -0600, Felipe Balbi wrote: Here's a small series of non-critical fixes and improvements for AM437x Starter Kit DTS. Basically I'm removing unnecessary pulls and adding explicit pinmux for a couple interfaces which were missing. All patches tested on top of commit 1ca7c60 (Add linux-next specific files for 20141204). Boot logs will be attached as a reply here. boot log attached. no idea why the thing says -dirty. Just reboot and I get: # uname -a Linux saruman 3.18.0-rc7-next-20141204-9-g8ade679 #2348 SMP Thu Dec 4 11:04:44 CST 2014 armv7l GNU/Linux Applying all these into omap-for-v3.20/dt thanks. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dts: omap3-n900: cleanup english
* Pavel Machek pa...@ucw.cz [141207 08:14]:
This fixes english in comments and removes extra empty newline.
Signed-off-by: Pavel Machek pa...@ucw.cz
Applying into omap-for-v3.20/dt thanks.
Tony
diff --git a/arch/arm/boot/dts/omap3-n900.dts
b/arch/arm/boot/dts/omap3-n900.dts
index 11d8afd..9e0e5a2 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -287,7 +287,7 @@
regulator-name = V28;
regulator-min-microvolt = 280;
regulator-max-microvolt = 280;
- regulator-always-on; /* due battery cover sensor */
+ regulator-always-on; /* due to battery cover sensor */
};
vaux2 {
@@ -345,7 +345,6 @@
regulator-name = VIO;
regulator-min-microvolt = 180;
regulator-max-microvolt = 180;
-
};
vintana1 {
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
--
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Re: [PATCH V2] ARM: dts: am57xx-beagle-x15: Add GPIO controlled fan node
* Nishanth Menon n...@ti.com [141205 09:51]:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
Signed-off-by: Nishanth Menon n...@ti.com
Applying into omap-for-v3.20/dt thanks.
Tony
---
V2: review comment updates
review comments update
- Sanitized outlook-ified name back to normal ;)
- removed unnecessary pinctrl-names property.
V1: https://patchwork.kernel.org/patch/5444911/
Depends on the following:
https://patchwork.kernel.org/patch/5439201/
https://patchwork.kernel.org/patch/5439191/
enable and disable can be controlled by (post the RPM, it finds
closest match - even a 1 will do)
echo '13000' /sys/class/hwmon/hwmon0/fan1_target
and
echo '0' /sys/class/hwmon/hwmon0/fan1_target
Test log: http://slexy.org/view/s2T0ajh46z
requires CONFIG_GPIO_PALMAS and CONFIG_SENSORS_GPIO_FAN to be operational
Applies on
https://git.kernel.org/cgit/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v3.19/dt-v2
arch/arm/boot/dts/am57xx-beagle-x15.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..4e55e94 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -80,6 +80,14 @@
default-state = off;
};
};
+
+ gpio_fan {
+ /* Based on 5v 500mA AFB02505HHB */
+ compatible = gpio-fan;
+ gpios = tps659038_gpio 1 GPIO_ACTIVE_HIGH;
+ gpio-fan,speed-map = 00
+ 13000 1;
+ };
};
dra7_pmx_core {
@@ -314,6 +322,12 @@
wakeup-source;
ti,palmas-long-press-seconds = 12;
};
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = ti,palmas-gpio;
+ gpio-controller;
+ #gpio-cells = 2;
+ };
};
tmp102: tmp102@48 {
--
1.7.9.5
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Re: [PATCH 2/2] ARM: dts: DRA7X: drop id property in pcie_phy
* Kishon Vijay Abraham I kis...@ti.com [141223 02:14]: On Tuesday 16 December 2014 02:52 PM, Vignesh R wrote: Since phyid is no longer used by pcie driver, this field can be dropped from the DT. Signed-off-by: Vignesh R vigne...@ti.com Acked-by: Kishon Vijay Abraham I kis...@ti.com Applying into omap-for-v3.20/dt thanks. Tony --- arch/arm/boot/dts/dra7.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 63bf99be1762..889e3023e68f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -,7 +,6 @@ wkupclk, refclk, div-clk, phy-div; #phy-cells = 0; - id = 1; ti,hwmods = pcie1-phy; }; @@ -1132,7 +1131,6 @@ div-clk, phy-div; #phy-cells = 0; ti,hwmods = pcie2-phy; - id = 2; status = disabled; }; }; -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] ARM: dts: am57xx-beagle-x15: Add GPIO controlled fan node
On 15:44-20150107, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [141205 09:51]:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
Signed-off-by: Nishanth Menon n...@ti.com
Applying into omap-for-v3.20/dt thanks.
Tony
Could you pick up the very latest rev:
https://patchwork.kernel.org/patch/5569521/ ?
---
V2: review comment updates
review comments update
- Sanitized outlook-ified name back to normal ;)
- removed unnecessary pinctrl-names property.
V1: https://patchwork.kernel.org/patch/5444911/
Depends on the following:
https://patchwork.kernel.org/patch/5439201/
https://patchwork.kernel.org/patch/5439191/
enable and disable can be controlled by (post the RPM, it finds
closest match - even a 1 will do)
echo '13000' /sys/class/hwmon/hwmon0/fan1_target
and
echo '0' /sys/class/hwmon/hwmon0/fan1_target
Test log: http://slexy.org/view/s2T0ajh46z
requires CONFIG_GPIO_PALMAS and CONFIG_SENSORS_GPIO_FAN to be operational
Applies on
https://git.kernel.org/cgit/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v3.19/dt-v2
arch/arm/boot/dts/am57xx-beagle-x15.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..4e55e94 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -80,6 +80,14 @@
default-state = off;
};
};
+
+ gpio_fan {
+ /* Based on 5v 500mA AFB02505HHB */
+ compatible = gpio-fan;
+ gpios = tps659038_gpio 1 GPIO_ACTIVE_HIGH;
+ gpio-fan,speed-map = 00
+ 13000 1;
+ };
};
dra7_pmx_core {
@@ -314,6 +322,12 @@
wakeup-source;
ti,palmas-long-press-seconds = 12;
};
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = ti,palmas-gpio;
+ gpio-controller;
+ #gpio-cells = 2;
+ };
};
tmp102: tmp102@48 {
--
1.7.9.5
--
Regards,
Nishanth Menon
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Re: [PATCH 1/5] ARM: AM43xx: hwmod: add VPFE hwmod entries
* Lad, Prabhakar prabhakar.cse...@gmail.com [141218 08:27]:
From: Benoit Parrot bpar...@ti.com
this patch adds VPFE HWMOD data for AM43xx.
Signed-off-by: Benoit Parrot bpar...@ti.com
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: Lad, Prabhakar prabhakar.cse...@gmail.com
Paul probably wants to queue this, I'll pick the dts
changes.
Regards,
Tony
---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 56
++
arch/arm/mach-omap2/prcm43xx.h | 3 +-
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index fea01aa..bd9067e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -483,6 +483,44 @@ static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
},
};
+static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x104,
+ .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
+ .name = vpfe,
+ .sysc = am43xx_vpfe_sysc,
+};
+
+static struct omap_hwmod am43xx_vpfe0_hwmod = {
+ .name = vpfe0,
+ .class = am43xx_vpfe_hwmod_class,
+ .clkdm_name = l3s_clkdm,
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
+ },
+ },
+};
+
+static struct omap_hwmod am43xx_vpfe1_hwmod = {
+ .name = vpfe1,
+ .class = am43xx_vpfe_hwmod_class,
+ .clkdm_name = l3s_clkdm,
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
+ },
+ },
+};
+
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
.master = am33xx_l3_main_hwmod,
@@ -750,6 +788,22 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi =
{
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
+ .master = am33xx_l3_main_hwmod,
+ .slave = am43xx_vpfe0_hwmod,
+ .clk= l3_gclk,
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
+ .master = am33xx_l3_main_hwmod,
+ .slave = am43xx_vpfe1_hwmod,
+ .clk= l3_gclk,
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
am33xx_l4_wkup__synctimer,
am43xx_l4_ls__timer8,
@@ -848,6 +902,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[]
__initdata = {
am43xx_l4_ls__dss,
am43xx_l4_ls__dss_dispc,
am43xx_l4_ls__dss_rfbi,
+ am43xx_l3__vpfe0,
+ am43xx_l3__vpfe1,
NULL,
};
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index ad7b3e9..8aa4c2c 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -143,5 +143,6 @@
#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET0x0268
#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
-
+#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068
+#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070
#endif
--
1.9.1
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Re: [PATCH] arm: boot: dts: add support for AM437x IDK
* Felipe Balbi ba...@ti.com [141222 14:33]: The AM437x Industrial Development Kit (IDK) is an application development platform targeted at industrial communication and control applications. It comes with a 3-phase motor driver, PROFINET, PROFIBUS and a few other industrial communication interfaces. The board has 1GiB of DDR3 RAM, QSPI NOR flash, a 100% discrete power design (no PMIC) and an on-board 2MP camera (not supported with Linux as of this writing). Signed-off-by: Felipe Balbi ba...@ti.com Applying into omap-for-v3.20/dt thanks. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/5] arm: boot: dts: am437x-sk: add power button binding
* Felipe Balbi ba...@ti.com [141226 11:31]:
Let this board report KEY_POWER so upper layers
can decide what to do when power button is pressed.
Signed-off-by: Felipe Balbi ba...@ti.com
Applying this one into omap-for-v3.20/dt thanks.
Tony
---
arch/arm/boot/dts/am437x-sk-evm.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc9..c53840c 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -386,6 +386,11 @@
regulator-always-on;
};
+ power-button {
+ compatible = ti,tps65218-pwrbutton;
+ status = okay;
+ interrupts = 3 IRQ_TYPE_EDGE_BOTH;
+ };
};
at24@50 {
--
2.2.0
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Re: [PATCH] ARM: OMAP: DTS: N950/N9: add twl_power
* Aaro Koskinen aaro.koski...@iki.fi [141226 12:12]:
Add twl_power for N950/N9. Start with the simplest configuration to just
enable power off.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
Applying into omap-for-v3.20/dt thanks.
Tony
---
arch/arm/boot/dts/omap3-n950-n9.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi
b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 1e49dfe..c41db94 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -60,6 +60,11 @@
twl {
compatible = ti,twl5031;
+
+ twl_power: power {
+ compatible = ti,twl4030-power;
+ ti,use_poweroff;
+ };
};
twl_gpio {
--
2.2.0
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Re: [PATCH v2] arm: boot: dts: am437x-idk: add gpio-based power key
* Felipe Balbi ba...@ti.com [141226 12:56]:
AM437x IDK board has a User Switch which we can
program to whatever we want. Because this board
doesn't have a PMIC which can give us power button
presses, let's use this user switch as a gpio-keys
power button.
Signed-off-by: Felipe Balbi ba...@ti.com
Applying into omap-for-v3.20/dt thanks.
Tony
---
Changes since v1:
- Add explicit pinctrl data.
(note that ball reset state is already MUX_MODE7, and even
though it was already working before, as can be seen from
v1's boot logs, it's best that we cope with possibly broken
bootloaders)
depends on [1]. Boot logs at [2]. Note that this can rather easily
be folded into the original patch if so desired.
[1] http://marc.info/?l=linux-omapm=141928747902983w=2
[2] http://hastebin.com/qezicehunu
arch/arm/boot/dts/am437x-idk-evm.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts
b/arch/arm/boot/dts/am437x-idk-evm.dts
index b52dd0a..f9a17e2 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -96,9 +96,29 @@
regulator-boot-on;
vin-supply = v1_5dreg;
};
+
+ gpio_keys: gpio_keys {
+ compatible = gpio-keys;
+ pinctrl-names = default;
+ pinctrl-0 = gpio_keys_pins_default;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ switch@0 {
+ label = power-button;
+ linux,code = KEY_POWER;
+ gpios = gpio4 2 GPIO_ACTIVE_LOW;
+ };
+ };
};
am43xx_pinmux {
+ gpio_keys_pins_default: gpio_keys_pins_default {
+ pinctrl-single,pins =
+ 0x1b8 (PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
+ ;
+ };
+
i2c0_pins_default: i2c0_pins_default {
pinctrl-single,pins =
0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /*
i2c0_sda.i2c0_sda */
@@ -282,6 +302,10 @@
status = okay;
};
+gpio4 {
+ status = okay;
+};
+
gpio5 {
status = okay;
};
--
2.2.0
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Re: [PATCH v2] ARM: dts: cm-t3x: add NAND support
* Dmitry Lifshitz lifsh...@compulab.co.il [141229 23:42]:
On 12/29/2014 03:06 PM, Roger Quadros wrote:
On 28/12/14 16:30, Dmitry Lifshitz wrote:
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -50,7 +50,8 @@
#include omap-gpmc-smsc911x.dtsi
gpmc {
- ranges = 5 0 0x2c00 0x0100;
+ ranges = 5 0 0x2c00 0x0100, /* CM-T3x30 SMSC9x Eth */
+0 0 0x 0x0100; /* CM-T3x NAND */
Isn't this ranges property redundant as it will anyways be overridden by the
board specific dts?
The ranges are specified here (and other files below) by design.
We built a tree like structure to organize DT files -
d234e4239 ARM: dts: sbc-t3x: refactor DT support
It allows to inherit/override properties common for different boards.
Our customers do not have to deal with a correct GPMC ranges settings, once
they base on omap3-cm-t3x.dts core module DT file (in case they do not
connect additional device to the bus).
This is the point of Igor's comment to the previous patch version.
Roger, do you still have pending issues with this patch?
Regards,
Tony
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Re: [PATCH V2] ARM: dts: am57xx-beagle-x15: Add GPIO controlled fan node
* Nishanth Menon n...@ti.com [150107 16:01]: On 15:44-20150107, Tony Lindgren wrote: * Nishanth Menon n...@ti.com [141205 09:51]: TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply a fan (such as AFB02505HHB) over J1 connector for various purposes. Provide device tree node to enable the same. Signed-off-by: Nishanth Menon n...@ti.com Applying into omap-for-v3.20/dt thanks. Tony Could you pick up the very latest rev: https://patchwork.kernel.org/patch/5569521/ ? Yeah sorry just noticed I had tagged two versions, will use the v4 instead. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4] ARM: dts: am57xx-beagle-x15: Add GPIO controlled fan node
* Felipe Balbi ba...@ti.com [150105 09:30]:
On Mon, Jan 05, 2015 at 10:32:29AM -0600, Nishanth Menon wrote:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
Signed-off-by: Nishanth Menon n...@ti.com
have already reviewed this one previously:
Reviewed-by: Felipe Balbi ba...@ti.com
Applying this into omap-for-v3.20/dt instead of the
earlier version thanks.
Tony
---
V4: Change format of the speed-map used.
V3: https://patchwork.kernel.org/patch/5562121/
V2: https://patchwork.kernel.org/patch/5445111/
V1: https://patchwork.kernel.org/patch/5444911/
Enable and disable can be controlled by (post the RPM, it finds
closest match - even a 1 will do)
echo '13000' /sys/class/hwmon/hwmon0/fan1_target
and
echo '0' /sys/class/hwmon/hwmon0/fan1_target
Test log: http://slexy.org/view/s2T0ajh46z
requires CONFIG_GPIO_PALMAS and CONFIG_SENSORS_GPIO_FAN to be operational
Applies on v3.19-rc1
arch/arm/boot/dts/am57xx-beagle-x15.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 6c2e8e4..c5d4cea 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -80,6 +80,14 @@
default-state = off;
};
};
+
+ gpio_fan: gpio_fan {
+ /* Based on 5v 500mA AFB02505HHB */
+ compatible = gpio-fan;
+ gpios = tps659038_gpio 1 GPIO_ACTIVE_HIGH;
+ gpio-fan,speed-map = 0 0,
+13000 1;
+ };
};
dra7_pmx_core {
@@ -394,6 +402,12 @@
wakeup-source;
ti,palmas-long-press-seconds = 12;
};
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = ti,palmas-gpio;
+ gpio-controller;
+ #gpio-cells = 2;
+ };
};
tmp102: tmp102@48 {
--
1.7.9.5
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balbi
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Re: [PATCH] arm: omap: reduce zImage size on omap2plus_defconfig
* Felipe Balbi ba...@ti.com [141226 08:29]: On Fri, Dec 26, 2014 at 08:13:49AM -0800, Tony Lindgren wrote: * Felipe Balbi ba...@ti.com [141226 07:29]: On Fri, Dec 26, 2014 at 03:04:00PM +0200, grygorii.stras...@linaro.org wrote: Tony, your call May be it will be good thing to split this patch. That way more information will be stored in commit log about which set of options gives us what benefits. And also, It will allow to continue with agreed changes. ? can be done, but then again, it's just a defconfig change. Tony, your call. I think we should move omap2plus_defconfig to be mostly modular and usable for distros as a base. Most distros prefer to build almost everything as loadable modules. And my preference is that we should only keep the minimum rootfs for devices and serial support as built-in and rely on initramfs for most drivers. And slowly move also the remaining built-in drivers to be loadable modules. The reasons for having drivers as loadable modules are many. It allows distros to use the same kernel for all the devices without bloating the kernel. It makes developing drivers easier as just the module needs to be reloaded. And loadable modules protect us from cross-framework spaghetti calls in the kernel as the interfaces are clearly defined. Are there people really using SATA as rootfs right now on omaps? Yes. That is exactly my point. From my side I'd like to note that I know about few ongoing projects on DRA7x EVM where SATA is used as rootfs - now It is the fast possible way to start Android. now this is something different. This is evidence that there are people relying on SATA on rootfs. I'll leave to Tony again. OK sounds like people are really using SATA as rootfs, so we might as well keep it built in then. And it does not affect the PM on the devices that do have PM working, that has been a problem with having some drivers built-in. We can still work towards making the current rootfs device drivers into loadable modules in the long term :) Here's v3: Thanks, applying this into omap-for-v3.20/defconfig. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] arm: omap2plus_defconfig: enable TPS65218 power button
* Felipe Balbi ba...@ti.com [141226 11:31]: Enable tps65218 power button driver by default as a dynamically linked module so AM437x SK can report power button presses. Signed-off-by: Felipe Balbi ba...@ti.com Applying this into omap-for-v3.20/defconfig thanks. Tony --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a85..f4a4b2f 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -183,6 +183,7 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_TSC2005=m CONFIG_TOUCHSCREEN_TSC2007=m CONFIG_INPUT_MISC=y +CONFIG_INPUT_TPS65218_PWRBUTTON=m CONFIG_INPUT_TWL4030_PWRBUTTON=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Revert disabling of smc91x for n900
On Wed 2015-01-07 08:40:06, Tony Lindgren wrote: * Nishanth Menon n...@ti.com [150107 07:47]: On 01/07/2015 03:57 AM, Pavel Machek wrote: On Tue 2015-01-06 08:59:03, Tony Lindgren wrote: * Pavel Machek pa...@ucw.cz [150106 00:03]: On Mon 2015-01-05 15:02:29, Tony Lindgren wrote: Revert ARM: dts: Disable smc91x on n900 until bootloader dependency is removed. We've now fixed the issues that caused problems with uninitialized hardware depending on the bootloader version. Mostly things got fixed with the following commits: 9a894953a97b (ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins) 7d2911c43815 (net: smc91x: Fix gpios for device tree based booting) Note that this only affects the early development boards with Ethernet that we still have in a few automated boot test systems. Signed-off-by: Tony Lindgren t...@atomide.com Normally, the early development boards should have separate dts file (then include common parts), no? In this case it won't matter. The GPMC hardware is there, the probe just fails if no smsc91x is found. Could you at least add a note to the dts file what is it? Because I always thought it is a bug. Sure, updated patch below. Can somebody please test boot it on a production n900 too to make sure it no longer causes issues? Actually... how do you manage your n900 to boot? Does it also boot from 0x? I believe I'm hitting dtb size limit (again), and 3.19-rc3 does not boot unless I somehow make dtb smaller... like the patch below. --- make dtb smaller so that it boots. I am using chained boot (NOLO-u-boot-kernel (zImage +dtb concatenated) on a real n900 I have the same issue as well. using omap2plus_defconfig. I was able to bisect next tags as follows: next-20141128 worked, next-20141201 stopped booting and the change was new dts addition, removing the dts addition helped next-20141201 boot as well. Current state: https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447 https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448 I had complained originally here: http://marc.info/?t=14194620311r=1w=2 Apologies on not following up on the thread, got distracted. Hmm strange a plain omap2plus_defconfig kernel boots just fine here. Also boots fine with appended DTB and 0x using something like: Interesting. $ cat arch/arm/boot/zImage arch/arm/boot/dts/omap3-n900.dtb /tmp/zImage $ 0x -m /tmp/zImage -l -b I'm doing something similar, with difference that I also pass commandline using -b. My boot log is appended in case that provides any clues. Note that I'm only loading it with -l and not flashing it though. Ok, I'll try with defconfig, and am sending you my .config in case it depends on it. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html config.gz Description: application/gzip
Re: [PATCH] ARM: dts: Revert disabling of smc91x for n900
Hi! Sure, updated patch below. Can somebody please test boot it on a production n900 too to make sure it no longer causes issues? Actually... how do you manage your n900 to boot? Does it also boot from 0x? I believe I'm hitting dtb size limit (again), and 3.19-rc3 does not boot unless I somehow make dtb smaller... like the patch below. --- make dtb smaller so that it boots. I am using chained boot (NOLO-u-boot-kernel (zImage +dtb concatenated) on a real n900 I have the same issue as well. using omap2plus_defconfig. I was able to bisect next tags as follows: next-20141128 worked, next-20141201 stopped booting and the change was new dts addition, removing the dts addition helped next-20141201 boot as well. Current state: https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447 https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448 I had complained originally here: http://marc.info/?t=14194620311r=1w=2 Apologies on not following up on the thread, got distracted. Actually, I noticed this some time ago, and there's some additional discussion at Subject: Re: dtb size limit? was Re: Tiny dts change breaks boot on n900 Message-ID: 20141110150915.gh31...@atomide.com Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Revert disabling of smc91x for n900
On 01/07/2015 03:57 AM, Pavel Machek wrote: On Tue 2015-01-06 08:59:03, Tony Lindgren wrote: * Pavel Machek pa...@ucw.cz [150106 00:03]: On Mon 2015-01-05 15:02:29, Tony Lindgren wrote: Revert ARM: dts: Disable smc91x on n900 until bootloader dependency is removed. We've now fixed the issues that caused problems with uninitialized hardware depending on the bootloader version. Mostly things got fixed with the following commits: 9a894953a97b (ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins) 7d2911c43815 (net: smc91x: Fix gpios for device tree based booting) Note that this only affects the early development boards with Ethernet that we still have in a few automated boot test systems. Signed-off-by: Tony Lindgren t...@atomide.com Normally, the early development boards should have separate dts file (then include common parts), no? In this case it won't matter. The GPMC hardware is there, the probe just fails if no smsc91x is found. Could you at least add a note to the dts file what is it? Because I always thought it is a bug. Sure, updated patch below. Can somebody please test boot it on a production n900 too to make sure it no longer causes issues? Actually... how do you manage your n900 to boot? Does it also boot from 0x? I believe I'm hitting dtb size limit (again), and 3.19-rc3 does not boot unless I somehow make dtb smaller... like the patch below. --- make dtb smaller so that it boots. I am using chained boot (NOLO-u-boot-kernel (zImage +dtb concatenated) on a real n900 I have the same issue as well. using omap2plus_defconfig. I was able to bisect next tags as follows: next-20141128 worked, next-20141201 stopped booting and the change was new dts addition, removing the dts addition helped next-20141201 boot as well. Current state: https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447 https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448 I had complained originally here: http://marc.info/?t=14194620311r=1w=2 Apologies on not following up on the thread, got distracted. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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Re: [PATCH] ARM: dts: Revert disabling of smc91x for n900
On Wed 2015-01-07 08:40:06, Tony Lindgren wrote: * Nishanth Menon n...@ti.com [150107 07:47]: On 01/07/2015 03:57 AM, Pavel Machek wrote: On Tue 2015-01-06 08:59:03, Tony Lindgren wrote: * Pavel Machek pa...@ucw.cz [150106 00:03]: On Mon 2015-01-05 15:02:29, Tony Lindgren wrote: Revert ARM: dts: Disable smc91x on n900 until bootloader dependency is removed. We've now fixed the issues that caused problems with uninitialized hardware depending on the bootloader version. Mostly things got fixed with the following commits: 9a894953a97b (ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins) 7d2911c43815 (net: smc91x: Fix gpios for device tree based booting) Note that this only affects the early development boards with Ethernet that we still have in a few automated boot test systems. Signed-off-by: Tony Lindgren t...@atomide.com Normally, the early development boards should have separate dts file (then include common parts), no? In this case it won't matter. The GPMC hardware is there, the probe just fails if no smsc91x is found. Could you at least add a note to the dts file what is it? Because I always thought it is a bug. Sure, updated patch below. Can somebody please test boot it on a production n900 too to make sure it no longer causes issues? Actually... how do you manage your n900 to boot? Does it also boot from 0x? I believe I'm hitting dtb size limit (again), and 3.19-rc3 does not boot unless I somehow make dtb smaller... like the patch below. --- make dtb smaller so that it boots. I am using chained boot (NOLO-u-boot-kernel (zImage +dtb concatenated) on a real n900 I have the same issue as well. using omap2plus_defconfig. I was able to bisect next tags as follows: next-20141128 worked, next-20141201 stopped booting and the change was new dts addition, removing the dts addition helped next-20141201 boot as well. Current state: https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447 https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448 I had complained originally here: http://marc.info/?t=14194620311r=1w=2 Apologies on not following up on the thread, got distracted. Hmm strange a plain omap2plus_defconfig kernel boots just fine here. Also boots fine with appended DTB and 0x using something like: I tried omap2plus_defconfig + my smaller DTB, and I stare at blank screen where kernel messages should be (no serial cable here, sorry). I reverted my smaller DTB changes, and now I'm staring at nokia logo, followed by backlight off. Strange. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] irqchip: kill the GIC routable domain
On Tue, Dec 09, 2014 at 06:40:35PM +, Marc Zyngier wrote:
On 09/12/14 18:17, Nishanth Menon wrote:
On 09:53-20141209, Marc Zyngier wrote:
On 08/12/14 22:41, Nishanth Menon wrote:
Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
assume you will squash as needed and repost with linux-omap mailing list
in CC.
Brilliant. I'll squash that into my tree and repost at some point.
K, it will be nice to have a reflow of the series based on v3.19-rc1
since there are dts dependencies and we dont want folks to have
regressions on their platforms of choice..
Obviously, my tests are basic boot tests and should get a few weeks(as
you already mentioned) on linux-next to get properly soaked
I increased the scope of testing knowing that WUGEN is present in many
A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
my testing.. Also a few notes:
Stuff like: am437x is a bit questionable (interrupt-parent probably
should be wugen?)
175: 0 GIC 39 tps65218
OMAP5: (should be wugen?)
308: 4323 0 GIC 106 OMAP UART2
411: 0 0 GIC 151 twl6040
405: 1 0 GIC 39 palmas
Well, I can't really tell. Someone with access to the documentation
should be able to find out.
AM437x: http://www.ti.com/lit/pdf/spruhl7
OMAP5: http://www.ti.com/lit/pdf/swpu249
yeah, we should be able to do them as well - trivially since they follow
the same structure as other SoCs without crossbar.
Done some stuff in that department.
OMAP4 serial port is flaky - not sure if it is due to routing of GIC to
UART2 and not via WUGEN
IRQ branch: with my fix applied:
-
[...]
18: pandaboard-es: Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not
expected)
19: pandaboard-vanilla: Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not
expected)
If I read the log correctly, the serial port stops responding after a
while?
yeah - dug at the omap4 ones a bit, obviously once the deeper c states
are hit, we'd like wakeupgen to wakeup CPU else we will be sluggish in
the sense that the event is detected when some other wakeupgen enabled
interrupt takes place.
I realised that as well once I got a panda up and running.
Adding the following makes my panda work fine.
1: pandaboard-es: Boot PASS: http://slexy.org/raw/s20o8DaBvh
2: pandaboard-vanilla: Boot PASS: http://slexy.org/raw/s222JndDdh
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 1505135..8b6d50e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -371,8 +371,8 @@
twl: twl@48 {
reg = 0x48;
/* IRQ# = 7 */
- interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to gic */
- interrupt-parent = gic;
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to wakeupgen to gic */
+ interrupt-parent = wakeupgen;
};
[...]
I already fixed those in my tree, in a slightly different way: no need
to have an interrupt parent at all, as we're going to inherit the
default anyway.
I've pushed another version of the branch, with the crossbar rework
sitting *before* the WUGEN hacks. That should hopefully make bisection work.
If you can give it a shake, that'd be most appreciated. I'll repost the
branch in a couple of days.
Hmmm, I'm sensing a pattern here :) My email, only to the MLs, was
messed up for a few days. I probably missed it in there...
thx,
Jason.
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Re: [PATCH v12 0/9] Enable L2 cache support on Exynos4210/4x12 SoCs
On 01/07/2015 05:30 AM, Marek Szyprowski wrote:
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+ platforms by moving l2cache initialization to
common code. This will resolve too early call to l2cache init, what might
cause kmalloc failure in code added in next patches.
Next patch fixes access method to latency and filter settings in l2cache
driver.
Next four patches extend existing support for secure write in L2C driver
to account for design of secure firmware running on Exynos. Namely:
1) direct read access to certain registers is needed on Exynos, because
secure firmware calls set several registers at once,
2) not all boards are running secure firmware, so .write_sec callback
needs to be installed in Exynos firmware ops initialization code,
3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
is not allowed and so must use l2c_write_sec as well,
4) on certain boards, default value of prefetch register is incorrect
and must be overridden at L2C initialization.
For boards running with firmware that provides access to individual
L2C registers this series should introduce no functional changes. However
since the driver is widely used on other platforms I'd like to kindly ask
any interested people for testing.
Further three patches add implementation of .write_sec and .configure
callbacks for Exynos secure firmware and necessary DT nodes to enable
L2 cache.
Changes in this version tested on Exynos4412-based TRATS2 and OdroidU3+
boards (both with secure firmware). There should be no functional change
for Exynos boards running without secure firmware. OMAP based platforms
were tested by Nishanth Menon and Tony Lindgren.
Depends on:
- v3.19-rc2
Changelog:
Changes since v11:
(https://lkml.org/lkml/2015/1/5/254)
- Added changes suggested by Nishanth to 'ARM: l2c: use l2c_write_sec()
for restoring latency and filter regs' patch
- Fixed 'checkpatch --strict' issues
- Added Nishanth's and Tony's acked/tested tags
Changes since v10:
(https://lkml.org/lkml/2014/12/23/151)
- Added patch, which fixes access method to latency and filter settings
in l2cache
Changes since v9:
(https://lkml.org/lkml/2014/11/17/217)
- Rebased onto vanilla v3.19-rc1
- Added patch for Omap2+ (move l2cache initialization to common code), what
fixes too early initialization (kmalloc failure)
Changes since v8:
(http://lkml.org/lkml/2014/11/13/263)
- Rebased onto vanilla v3.18-rc3 and added required includes, which were
previously added by other patches
- Added Acked-by tags for Exynos part
Changes since v7:
(https://lkml.org/lkml/2014/10/29/158)
- rebased onto arm-soc/for-next kernel tree (depends on patches merged to
v3.18-rc3 and arm-soc/samsung/pm2 branch)
- removed 'ARM: l2c: unify L2C-310 OF initialization error messages' patch
(no longer needed)
Changes since v6:
(https://lkml.org/lkml/2014/10/27/233)
- changed PL310 to L2C-310 prefix in error messages
- added patch shortening the error message about incorrect associativity
Changes since v5:
(https://lkml.org/lkml/2014/9/24/364)
- rebased onto v3.18-rc2
- added error message about missing properties values
Changes since v4:
(https://lkml.org/lkml/2014/8/26/461)
- rewrote the code accessing l2x0_saved_regs from assembly code
- added comment and reworked unconditional call to SMC_CMD_L2X0INVALL
Patch summary:
Marek Szyprowski (2):
ARM: OMAP2+: use common l2cache initialization code
ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
Tomasz Figa (7):
ARM: l2c: Refactor the driver to use commit-like interface
ARM: l2c: Add interface to ask hypervisor to configure L2C
ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
not NULL
ARM: l2c: Add support for overriding prefetch settings
ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
ARM: EXYNOS: Add support for non-secure L2X0 resume
ARM: dts: exynos4: Add nodes for L2 cache controller
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
arch/arm/include/asm/outercache.h | 3 +
arch/arm/kernel/irq.c | 3 +-
arch/arm/mach-exynos/firmware.c| 50 +
arch/arm/mach-exynos/sleep.S | 46 +
arch/arm/mach-omap2/board-generic.c| 6 +
arch/arm/mach-omap2/common.h | 8 +
arch/arm/mach-omap2/omap4-common.c | 16 +-
arch/arm/mm/cache-l2x0.c | 272
-
11 files changed, 325
Re: [PATCH] ARM: dts: Revert disabling of smc91x for n900
* Nishanth Menon n...@ti.com [150107 07:47]: On 01/07/2015 03:57 AM, Pavel Machek wrote: On Tue 2015-01-06 08:59:03, Tony Lindgren wrote: * Pavel Machek pa...@ucw.cz [150106 00:03]: On Mon 2015-01-05 15:02:29, Tony Lindgren wrote: Revert ARM: dts: Disable smc91x on n900 until bootloader dependency is removed. We've now fixed the issues that caused problems with uninitialized hardware depending on the bootloader version. Mostly things got fixed with the following commits: 9a894953a97b (ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins) 7d2911c43815 (net: smc91x: Fix gpios for device tree based booting) Note that this only affects the early development boards with Ethernet that we still have in a few automated boot test systems. Signed-off-by: Tony Lindgren t...@atomide.com Normally, the early development boards should have separate dts file (then include common parts), no? In this case it won't matter. The GPMC hardware is there, the probe just fails if no smsc91x is found. Could you at least add a note to the dts file what is it? Because I always thought it is a bug. Sure, updated patch below. Can somebody please test boot it on a production n900 too to make sure it no longer causes issues? Actually... how do you manage your n900 to boot? Does it also boot from 0x? I believe I'm hitting dtb size limit (again), and 3.19-rc3 does not boot unless I somehow make dtb smaller... like the patch below. --- make dtb smaller so that it boots. I am using chained boot (NOLO-u-boot-kernel (zImage +dtb concatenated) on a real n900 I have the same issue as well. using omap2plus_defconfig. I was able to bisect next tags as follows: next-20141128 worked, next-20141201 stopped booting and the change was new dts addition, removing the dts addition helped next-20141201 boot as well. Current state: https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447 https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448 I had complained originally here: http://marc.info/?t=14194620311r=1w=2 Apologies on not following up on the thread, got distracted. Hmm strange a plain omap2plus_defconfig kernel boots just fine here. Also boots fine with appended DTB and 0x using something like: $ cat arch/arm/boot/zImage arch/arm/boot/dts/omap3-n900.dtb /tmp/zImage $ 0x -m /tmp/zImage -l -b My boot log is appended in case that provides any clues. Note that I'm only loading it with -l and not flashing it though. Regards, Tony ... [ 1.943] getting value of option 'RD flags set' [ 1.948] SETUP: WR VND DEVICEreq 42 value index length 001b [ 1.956] Image 'kernel' won't fit to the partition, still loading it (4814592 bytes, while maximum is 2097152 bytes) [ 1.967] Receiving kernel (length 4814592) [ 2.298] Image successfully received [ 2.302] SETUP: WR VND DEVICEreq 82 value index length [ 2.309] SETUP: WR STD INTERFACE SET_INTERFACE value index 0002 length [ 2.363] Boot requested (normal mode) [ 2.367] Serial console enabled [0.00] Booting Linux on physical CPU 0x0 [0.00] Initializing cgroup subsys cpuset [0.00] Initializing cgroup subsys cpu [0.00] Initializing cgroup subsys cpuacct [0.00] Linux version 3.19.0-rc1 (tmlind@sampyla) (gcc version 4.9.2 ( 4.9.2-10) ) #1148 SMP Wed Jan 7 08:27:45 PST 2015 [0.00] CPU: ARMv7 Processor [411fc083] revision 3 (ARMv7), cr=10c5387d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache [0.00] Machine model: Nokia N900 [0.00] cma: Reserved 16 MiB at 0x8e80 [0.00] Memory policy: Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] OMAP3430/3530 ES3.1 (l2cache iva sgx neon isp ) [0.00] PERCPU: Embedded 11 pages/cpu @cfc36000 s14912 r8192 d21952 u45056 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64704 [0.00] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 [0.00] PID hash table entries: 1024 (order: 0, 4096 bytes) [0.00] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) [0.00] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Memory: 223700K/261120K available (6215K kernel code, 674K rwdata, 2360K rodata, 428K init, 8221K bss, 21036K reserved, 16384K cma-reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xd080 - 0xff00 ( 744 MB) [0.00] lowmem : 0xc000 - 0xd000 ( 256 MB) [0.00] pkmap : 0xbfe0 - 0xc000
Re: [PATCH 0/5] irqchip: kill the GIC routable domain
On 12:21-20141210, Nishanth Menon wrote:
On 12/09/2014 12:40 PM, Marc Zyngier wrote:
On 09/12/14 18:17, Nishanth Menon wrote:
On 09:53-20141209, Marc Zyngier wrote:
On 08/12/14 22:41, Nishanth Menon wrote:
Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
assume you will squash as needed and repost with linux-omap mailing list
in CC.
Brilliant. I'll squash that into my tree and repost at some point.
K, it will be nice to have a reflow of the series based on v3.19-rc1
since there are dts dependencies and we dont want folks to have
regressions on their platforms of choice..
Obviously, my tests are basic boot tests and should get a few weeks(as
you already mentioned) on linux-next to get properly soaked
I increased the scope of testing knowing that WUGEN is present in many
A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
my testing.. Also a few notes:
Stuff like: am437x is a bit questionable (interrupt-parent probably
should be wugen?)
175: 0 GIC 39 tps65218
OMAP5: (should be wugen?)
308: 4323 0 GIC 106 OMAP UART2
411: 0 0 GIC 151 twl6040
405: 1 0 GIC 39 palmas
Well, I can't really tell. Someone with access to the documentation
should be able to find out.
AM437x: http://www.ti.com/lit/pdf/spruhl7
OMAP5: http://www.ti.com/lit/pdf/swpu249
yeah, we should be able to do them as well - trivially since they follow
the same structure as other SoCs without crossbar.
Done some stuff in that department.
OMAP4 serial port is flaky - not sure if it is due to routing of GIC to
UART2 and not via WUGEN
IRQ branch: with my fix applied:
-
[...]
18: pandaboard-es: Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not
expected)
19: pandaboard-vanilla: Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not
expected)
If I read the log correctly, the serial port stops responding after a
while?
yeah - dug at the omap4 ones a bit, obviously once the deeper c states
are hit, we'd like wakeupgen to wakeup CPU else we will be sluggish in
the sense that the event is detected when some other wakeupgen enabled
interrupt takes place.
I realised that as well once I got a panda up and running.
Adding the following makes my panda work fine.
1: pandaboard-es: Boot PASS: http://slexy.org/raw/s20o8DaBvh
2: pandaboard-vanilla: Boot PASS: http://slexy.org/raw/s222JndDdh
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 1505135..8b6d50e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -371,8 +371,8 @@
twl: twl@48 {
reg = 0x48;
/* IRQ# = 7 */
- interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to gic */
- interrupt-parent = gic;
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to wakeupgen to gic */
+ interrupt-parent = wakeupgen;
};
[...]
I already fixed those in my tree, in a slightly different way: no need
to have an interrupt parent at all, as we're going to inherit the
default anyway.
I've pushed another version of the branch, with the crossbar rework
sitting *before* the WUGEN hacks. That should hopefully make bisection work.
If you can give it a shake, that'd be most appreciated. I'll repost the
branch in a couple of days.
Did a quick run.. and thought of testing power management and found
that CPUFreq for my platforms are broken in v3.18-rc7 and my scripts
broke (so much for my cronjob testing daily boot... now I gotta add
some PM test as well.. Sigh..) anyways.. just boot log..
based on
irq/die-gic-arch-extn-die-die-die c0024cb irqchip: gic: Drop support
for gic_arch_extn
1: am335x-evm: Boot PASS: http://slexy.org/raw/s201YeK4dW
2: am335x-sk: Boot PASS: http://slexy.org/raw/s20nydiyVx
3: am3517-evm: Boot PASS: http://slexy.org/raw/s2aTrenePo
4: am437x-sk: Boot FAIL: http://slexy.org/raw/s20NNiEa4W
5: am43xx-epos: Boot PASS: http://slexy.org/raw/s2gghhhyOy
6: am43xx-gpevm: Boot PASS: http://slexy.org/raw/s2LY4Cb75N
7: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s2e8iJMUXu
8: beagleboard-vanilla: Boot PASS: http://slexy.org/raw/s20wqxUmvr
9: beaglebone-black: Boot PASS: http://slexy.org/raw/s21I0g2Ba3
10: beaglebone: Boot PASS: http://slexy.org/raw/s2lpED0qW4
11: craneboard: Boot PASS: http://slexy.org/raw/s230RKflY3
12: dra72x-evm: Boot FAIL: http://slexy.org/raw/s21fWVnjaB
13: dra7xx-evm: Boot PASS: http://slexy.org/raw/s20yEhfruO
14: OMAP3430-Labrador(LDP): Boot PASS: http://slexy.org/raw/s20qZaXwz0
15: n900: Boot PASS: http://slexy.org/raw/s21LNTXZP7
16: omap5-evm: Boot PASS:
Re: [PATCH 2/3] hwmon: Driver for OMAP3 temperature sensor
On Sat, Jan 03, 2015 at 10:18:58AM +0100, Pavel Machek wrote:
On Mon 2014-12-29 11:04:48, Guenter Roeck wrote:
On Mon, Dec 29, 2014 at 07:15:56PM +0100, Pavel Machek wrote:
On Mon 2014-12-29 12:01:03, Nishanth Menon wrote:
On Mon, Dec 29, 2014 at 11:52 AM, Grazvydas Ignotas nota...@gmail.com
wrote:
On Fri, Dec 26, 2014 at 2:34 PM, Sebastian Reichel s...@kernel.org
wrote:
OMAP34xx and OMAP36xx processors contain a register in the syscon
area,
which can be used to determine the SoCs temperature. This patch
provides
a DT based driver for the temperature sensor based on an older driver
written by Peter De Schrijver for the Nokia N900 and N9.
The sensor looks like an earlier iteration of sensors used in newer
OMAPs, which are already supported by maybe
drivers/thermal/ti-soc-thermal/ , maybe it would make sense to update
that driver instead?
Just to be clear - OMAP4 is the first time that the sensors were
reliable enough to be used.
When testing initial version of the patch, they seem to work very well
in the omap3 case.
Pavel,
can you look into the omap4 thermal driver to see if it can be used ?
After some fixes... yes, it seems to be same hardware.
So this should be the way to go, but then we have others claim that
it should not be done because the OMAP3 sensors are too unreliable
to use for thermal decisions. Not really sure where that leaves us.
I am kind of opposed to have similar drivers for similar chips
in two different subsystems.
Is it possible to add the patch below to the omap thermal driver
and not use it for thermal decisions ?
Guenter
Signed-off-by: Pavel Machek pa...@ucw.cz
diff --git a/drivers/thermal/ti-soc-thermal/Kconfig
b/drivers/thermal/ti-soc-thermal/Kconfig
index bd4c7be..a49495f 100644
--- a/drivers/thermal/ti-soc-thermal/Kconfig
+++ b/drivers/thermal/ti-soc-thermal/Kconfig
@@ -21,6 +21,15 @@ config TI_THERMAL
This includes trip points definitions, extrapolation rules and
CPU cooling device bindings.
+config OMAP3_THERMAL
+ bool Texas Instruments OMAP3 thermal support
+ depends on TI_SOC_THERMAL
+ depends on ARCH_OMAP3
+ help
+ If you say yes here you get thermal support for the Texas Instruments
+ OMAP3 SoC family. The current chip supported are:
+- OMAP3430
+
config OMAP4_THERMAL
bool Texas Instruments OMAP4 thermal support
depends on TI_SOC_THERMAL
diff --git a/drivers/thermal/ti-soc-thermal/Makefile
b/drivers/thermal/ti-soc-thermal/Makefile
index 1226b24..2b5b220 100644
--- a/drivers/thermal/ti-soc-thermal/Makefile
+++ b/drivers/thermal/ti-soc-thermal/Makefile
@@ -2,5 +2,6 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal.o
ti-soc-thermal-y := ti-bandgap.o
ti-soc-thermal-$(CONFIG_TI_THERMAL) += ti-thermal-common.o
ti-soc-thermal-$(CONFIG_DRA752_THERMAL) += dra752-thermal-data.o
+ti-soc-thermal-$(CONFIG_OMAP3_THERMAL) += omap3-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP5_THERMAL) += omap5-thermal-data.o
diff --git a/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
b/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
new file mode 100644
index 000..a79ebf2
--- /dev/null
+++ b/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
@@ -0,0 +1,99 @@
+/*
+ * OMAP3 thermal driver.
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Inc.
+ * Copyright (C) 2014 Pavel Machek pa...@ucw.cz
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include ti-thermal.h
+#include ti-bandgap.h
+
+/*
+ * OMAP34XX has one instance of thermal sensor for MPU
+ * need to describe the individual bit fields
+ */
+static struct temp_sensor_registers
+omap34xx_mpu_temp_sensor_registers = {
+ .temp_sensor_ctrl = 0,
+ .bgap_tempsoff_mask = 0, /* Unused, we don't have POWER_SWITCH */
+ .bgap_soc_mask = BIT(8),
+ .bgap_eocz_mask = BIT(7),
+ .bgap_dtemp_mask = 0x7f,
+
+ .bgap_mode_ctrl = 0,
+ .mode_ctrl_mask = 0,/* Unused, no MODE_CONFIG */
+
+ .bgap_efuse = 0,
+};
+
+/* Thresholds and limits for OMAP34XX MPU temperature sensor */
+static struct temp_sensor_data omap34xx_mpu_temp_sensor_data = {
+ .min_freq = 32768,
+ .max_freq = 32768,
+ .max_temp = -99000,
+ .min_temp = 99000,
+ .hyst_val = 5000,
+};
+
+/*
+ * Temperature values in milli
Re: [PATCH 05/23] ARM: OMAP2: CM: remove unused PLL functions
* Tero Kristo t-kri...@ti.com [141127 07:53]: omap2xxx_cm_get_pll_config and omap2xxx_cm_get_pll_status are not used for anything, so remove these. I'm picking up this one to into omap-for-v3.20/cleanup. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/23] ARM: OMAP24xx: clock: remove unused apll code
* Tero Kristo t-kri...@ti.com [141127 07:53]: APLL clock type is no longer needed as the legacy clock support is removed. I'm picking this patch into omap-for-v3.20/cleanup thanks. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/23] ARM: OMAP3+: PRM: remove prm_get_reset_sources declaration from headers
* Tero Kristo t-kri...@ti.com [141127 07:53]: There is no implementation for this anywhere, so remove it from the header files also. Picking up this too into omap-for-v3.20/cleanup. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
Marc, On 1/7/2015 9:42 AM, Marc Zyngier wrote: The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have landed in -next, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we already broke it for the OMAP WUGEN block, we might as well do it again for the TI crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die Comments welcome, M. Marc Zyngier (21): ARM: tegra: irq: nuke leftovers from non-DT support irqchip: tegra: add DT-based support for legacy interrupt controller ARM: tegra: skip gic_arch_extn setup if DT has a LIC node ARM: tegra: update DTs to expose legacy interrupt controller DT: tegra: add binding for the legacy interrupt controller ARM: tegra: remove old LIC support genirq: Add irqchip_set_wake_parent irqchip: crossbar: convert dra7 crossbar to stacked domains DT: update ti,irq-crossbar binding irqchip: GIC: get rid of routable domain DT: arm,gic: kill arm,routable-irqs ARM: omap: convert wakeupgen to stacked domains DT: omap4/5: add binding for the wake-up generator ARM: imx6: convert GPC to stacked domains ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding irqchip: gic: add an entry point to set up irqchip flags ARM: shmobile: remove use of gic_arch_extn.irq_set_wake ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags irqchip: gic: Drop support for gic_arch_extn Thanks a lot for killing those gic_arch_extn and cross-bar with newly added stacked domains. It cleans up the GIC code for better. Feel free to add my ack if you need one. Acked-by: Santosh Shilimkar ssant...@kernel.org Regards, Snatosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: 3.19 on Nokia n900: audio quality awful
Hi, On Tue, Jan 06, 2015 at 11:58:56PM +0100, Pavel Machek wrote: On Wed 2015-01-07 00:27:17, Aaro Koskinen wrote: On Tue, Jan 06, 2015 at 11:08:05PM +0100, Pavel Machek wrote: On Tue 2015-01-06 22:57:30, Aaro Koskinen wrote: Hi, On Tue, Jan 06, 2015 at 09:50:00PM +0100, Pavel Machek wrote: PS: Unfortunately, N900 will not boot using nfsroot in 3.16+ at least, and boot from MMC card is broken and has been for quite some time. USB networking works fine with 3.19-rc3 and also MMC card rootfs. Does nfsroot work for you? USB networking works as a module but not build-in. [Patch is available for this one.] u-SD card seems to have similar problem. If I try it after boot, I can access it ok, but using u-SD card for rootfs fails. If it works for you, it would be interesting to know. I haven't tried nfsroot, but I've been using USB networking for ssh for a couple of years without issues. I have g_ether as module. Also I recently switched rootfs to u-SD card, and it (MMC) works fine as builtin. But I'm mounting it from userspace (using builtin initramfs inside zImage), with a poll loop that waits for a device to appear. Maybe if you do it from kernel you need to use root wait/delay etc. options? Yes, it works if I mount it later. It fails when done directly using root=, even with rootwait etc. Hard to believe, yes, but try it. You can watch the results on console. Well, I tried and it works. 3.19-rc3 mounting logs are below. I used root=/dev/mmcblk0p2 rootwait. Note that the external MMC is mmcblk0 from kernel point of view. Without serial console I guess you could maybe capture the failure logs using mtdoops (assuming the kernel panics when it fails to mount the rootfs). mtdoops was used even in the sales model kernel, so there is MTD partition reserved already for it called log. I would also recommend using initramfs to do the mounting etc. Then you could use the framebuffer console to observe and debug some obvious issues (assuming the framebuffer works, it often regresses unfortunately...). A. ... [2.145721] Waiting for root device /dev/mmcblk0p2... [2.194335] mmc0: host does not support reading read-only switch, assuming write-enable [2.213775] mmc0: new high speed SDHC card at address [2.227905] mmcblk0: mmc0: SL32G 29.7 GiB [2.252227] mmcblk0: p1 p2 [2.381958] EXT4-fs (mmcblk0p2): couldn't mount as ext3 due to feature incompatibilities [2.399627] EXT4-fs (mmcblk0p2): couldn't mount as ext2 due to feature incompatibilities [2.420196] EXT4-fs (mmcblk0p2): INFO: recovery required on readonly filesystem [2.435485] EXT4-fs (mmcblk0p2): write access will be enabled during recovery[2.497375] mmc1: switch to bus width 2 failed [2.510620] mmc1: switch to bus width 1 failed [2.524658] mmc1: new high speed MMC card at address 0001 [2.541229] mmcblk1: mmc1:0001 MMC32G 29.8 GiB [2.553710] mmcblk1boot0: mmc1:0001 MMC32G partition 1 512 KiB [2.569854] mmcblk1boot1: mmc1:0001 MMC32G partition 2 512 KiB [2.587646] mmcblk1: p1 p2 p3 [2.827606] EXT4-fs (mmcblk0p2): recovery complete [2.848327] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null) [2.863464] VFS: Mounted root (ext4 filesystem) readonly on device 179:2. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] can: c_can: use regmap_update_bits() to modify RAMINIT register
use of regmap_read() and regmap_write() in c_can_hw_raminit_syscon()
is not safe as the RAMINIT register can be shared between different drivers
at least for TI SoCs.
To make the modification atomic we switch to using regmap_update_bits().
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/net/can/c_can/c_can_platform.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/c_can/c_can_platform.c
b/drivers/net/can/c_can/c_can_platform.c
index f363972..364209a 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -110,6 +110,10 @@ static void c_can_hw_raminit_syscon(const struct
c_can_priv *priv, bool enable)
*/
ctrl = ~(1 raminit-bits.start);
ctrl |= 1 raminit-bits.done;
+
+ /* we can't use regmap_update_bits here as it will bypass the write
+* if START is already 0 and DONE is already 1.
+*/
regmap_write(raminit-syscon, raminit-reg, ctrl);
ctrl = ~(1 raminit-bits.done);
@@ -118,12 +122,13 @@ static void c_can_hw_raminit_syscon(const struct
c_can_priv *priv, bool enable)
if (enable) {
/* Set start bit and wait for the done bit. */
ctrl |= 1 raminit-bits.start;
- regmap_write(raminit-syscon, raminit-reg, ctrl);
+ regmap_update_bits(raminit-syscon, raminit-reg, mask, ctrl);
/* clear START bit if start pulse is needed */
if (raminit-needs_pulse) {
ctrl = ~(1 raminit-bits.start);
- regmap_write(raminit-syscon, raminit-reg, ctrl);
+ regmap_update_bits(raminit-syscon, raminit-reg,
+ mask, ctrl);
}
ctrl |= 1 raminit-bits.done;
--
2.1.0
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Re: [PATCH] arch: arm: mach-omap2: omap_hwmod.c: Remove some unused functions
* Rickard Strandqvist rickard_strandqv...@spectrumdigital.se [141207 09:23]: Removes some functions that are not used anywhere: omap_hwmod_pad_route_irq() omap_hwmod_no_setup_reset() omap_hwmod_read_hardreset() omap_hwmod_del_initiator_dep() omap_hwmod_enable_clocks() omap_hwmod_reset() omap_hwmod_ocp_barrier() omap_hwmod_disable_clocks() omap_hwmod_add_initiator_dep() This was partially found by using a static code analysis program called cppcheck. Nice, we should probably run cppcheck for unused functions on regular basis as we're slowly removing the legacy booting support in favor of device tree based booting. Paul, I'm applying all your arch/arm/*omap*/ cppcheck patches into omap-for-v3.20/cleanup branch that can then be used as a base for other branches in case of conflicts. Richard, I've also unified the subject lines to start with ARM: OMAP2+: and so on to make my pull requests will look a bit nicer. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 3/3] of/unittest: fix trailing semi-colons on conditional selftest
The of_platform_populate() and of_platform_depopulate() tests
are not really being tested because of some additional trailing
semi-colons after the conditional checks on couple of selftest
macro usage. Remove them to properly run all the platform
tests.
Fixes: 851da976dc1d (of/unittest: Remove test devices after adding them)
Signed-off-by: Suman Anna s-a...@ti.com
---
drivers/of/unittest.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 844838e11ef1..c67e50264e82 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -765,11 +765,11 @@ static void __init of_selftest_platform_populate(void)
selftest(irq 0 irq != -EPROBE_DEFER, device parsing error failed
- %d\n, irq);
if (selftest(np = of_find_node_by_path(/testcase-data/platform-tests),
-No testcase data in device tree\n));
+No testcase data in device tree\n))
return;
if (selftest(!(rc = device_register(test_bus)),
-testbus registration failed; rc=%i\n, rc));
+testbus registration failed; rc=%i\n, rc))
return;
for_each_child_of_node(np, child) {
--
2.2.1
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[RFC PATCH 2/3] core: platform: fix an invalid kfree during of_platform_depopulate
Drivers can use of_platform_populate() to create platform devices for children of the device main node, and a complementary API of_platform_depopulate() is provided to delete these child devices. Any platform_data supplied for the OF devices through auxdata lookup data is populated directly in the device's platform_data field, unlike those created using platform API. The of_platform_depopulate() leverages the platform code for cleanup, and this will result in a kernel oops due to an invalid kfree on this direct populated platform_data. Fix this by resetting the platform data for OF devices during platform device cleanup. Signed-off-by: Suman Anna s-a...@ti.com --- drivers/base/platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 9421fed40905..129e69c8c894 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -200,6 +200,8 @@ static void platform_device_release(struct device *dev) struct platform_object *pa = container_of(dev, struct platform_object, pdev.dev); + if (pa-pdev.dev.of_node) + pa-pdev.dev.platform_data = NULL; of_device_node_put(pa-pdev.dev); kfree(pa-pdev.dev.platform_data); kfree(pa-pdev.mfd_cell); -- 2.2.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 0/3] of_platform_depopulate crash fixes
Hi Grant, Rob, I ran into two different kernel crashes when trying to use of_platform_depopulate() in my out-of-tree PRU remoteproc platform driver. The crashes are seen when the child nodes created in my driver do get supplied with some platform data (provided through auxdata), and have IOMEM resources of their own. Patches 1 and 2 have fixed the issues for me, and I would like to know if this is indeed the right approach to be taken, these touch both the OF and platform core. 1. release_resource crash [ 81.510769] Unable to handle kernel NULL pointer dereference at virtual address 0018 [ 81.519270] pgd = de4a [ 81.522115] [0018] *pgd=9e4c5831, *pte=, *ppte= [ 81.528688] Internal error: Oops: 17 [#1] SMP ARM [ 81.533600] Modules linked in: pruss_remoteproc(-) remoteproc virtio_ring virtio [last unloaded: virtio_rpmsg_bus] [ 81.544451] CPU: 0 PID: 78 Comm: rmmod Not tainted 3.19.0-rc3-00024-g05af4a776de5 #330 [ 81.552714] Hardware name: Generic AM33XX (Flattened Device Tree) [ 81.559074] task: de519140 ti: de4f task.ti: de4f [ 81.564724] PC is at release_resource+0x14/0x7c [ 81.569452] LR is at release_resource+0x10/0x7c [ 81.574181] pc : [c00429c4]lr : [c00429c0]psr: 6013 [ 81.574181] sp : de4f1ec0 ip : fp : [ 81.586163] r10: r9 : de4f r8 : c000e904 [ 81.591615] r7 : 0081 r6 : c04d673c r5 : de52ac00 r4 : de4aec40 [ 81.598427] r3 : r2 : r1 : r0 : c0923530 [ 81.605241] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 81.612688] Control: 10c5387d Table: 9e4a0019 DAC: 0015 [ 81.618684] Process rmmod (pid: 78, stack limit = 0xde4f0240) [ 81.624680] Stack: (0xde4f1ec0 to 0xde4f2000) [ 81.629231] 1ec0: 0001 de52ac00 c03a083c c094a7d0 de52ac00 c03a0b78 [ 81.637770] 1ee0: de52ac10 c04d67b8 c039b7e0 de1100c0 de4ae370 de12cc10 de12cc00 [ 81.646308] 1f00: c0915564 c04d6724 de12cc10 bf01f154 de12cc10 bf02135c de12cc44 c03a0714 [ 81.654846] 1f20: c03a06fc de12cc10 bf02135c c039ec8c bf02135c de12cc10 bf02135c c039f494 [ 81.663384] 1f40: bf02135c be854be8 0880 c039eb14 bf021480 c00b4198 c0164bc0 73757270 [ 81.671922] 1f60: 65725f73 65746f6d 636f7270 0001 de519140 c000e7d0 0001 [ 81.680460] 1f80: 10c5387d c0083074 000195dc 73757270 65725f73 e85c 000195dc 73757270 [ 81.688998] 1fa0: 65725f73 c000e740 000195dc 73757270 be854be8 0880 be854be8 0880 [ 81.697536] 1fc0: 000195dc 73757270 65725f73 0081 000aa7f8 d1b0 [ 81.706075] 1fe0: be854be0 be854bd0 00019368 b6f39bc0 6010 be854be8 [ 81.714630] [c00429c4] (release_resource) from [c03a083c] (platform_device_del+0x6c/0x9c) [ 81.723537] [c03a083c] (platform_device_del) from [c03a0b78] (platform_device_unregister+0xc/0x18) [ 81.733268] [c03a0b78] (platform_device_unregister) from [c04d67b8] (of_platform_device_destroy+0x7c/0x88) [ 81.743727] [c04d67b8] (of_platform_device_destroy) from [c039b7e0] (device_for_each_child+0x34/0x74) [ 81.753720] [c039b7e0] (device_for_each_child) from [c04d6724] (of_platform_depopulate+0x2c/0x44) [ 81.763359] [c04d6724] (of_platform_depopulate) from [bf01f154] (pruss_remove+0x28/0x58 [pruss_remoteproc]) [ 81.773900] [bf01f154] (pruss_remove [pruss_remoteproc]) from [c03a0714] (platform_drv_remove+0x18/0x30) [ 81.784163] [c03a0714] (platform_drv_remove) from [c039ec8c] (__device_release_driver+0x70/0xc4) [ 81.793701] [c039ec8c] (__device_release_driver) from [c039f494] (driver_detach+0xb4/0xb8) [ 81.802693] [c039f494] (driver_detach) from [c039eb14] (bus_remove_driver+0x4c/0x90) [ 81.811154] [c039eb14] (bus_remove_driver) from [c00b4198] (SyS_delete_module+0x118/0x1e0) [ 81.820157] [c00b4198] (SyS_delete_module) from [c000e740] (ret_fast_syscall+0x0/0x48) [ 81.828788] Code: e1a04000 e59f0068 eb164f84 e5943010 (e5932018) [ 81.835241] ---[ end trace 753a834bdbc86894 ]--- Segmentation fault There seems to be similar signatures seen before [1][2], and in some cases, the drivers used of_device_unregister in a loop in their remove. These all should migrate to of_platform_depopulate, but so far haven't seen any that did supply platform data. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/274412.html [2] http://www.spinics.net/lists/linux-usb/msg107171.html 2. platform_data kfree crash After fixing the first one, ran into the second crash, and this is due to the fact that platform_data is never allocated in the OF device registration path. [ 156.281310] Unable to handle kernel paging request at virtual address e1e4d4a4 [ 156.288853] pgd = de4f [ 156.291676] [e1e4d4a4] *pgd= [ 156.295420] Internal error: Oops: 5 [#1] SMP ARM [ 156.300241] Modules linked in: pruss_remoteproc(-) remoteproc virtio_ring virtio [last unloaded: virtio_rpmsg_bus] [
[RFC PATCH 1/3] of/device: manage resources similar to platform_device_add
Drivers can use of_platform_populate() to create platform devices
for children of the device main node, and a complementary API
of_platform_depopulate() is provided to delete these child platform
devices. The of_platform_depopulate() leverages the platform API
for performing the cleanup of these devices.
The platform device resources are managed differently between
of_device_add and platform_device_add, and this asymmetry causes
a kernel oops in platform_device_del during removal of the resources.
Manage the platform device resources similar to platform_device_add
to fix this kernel oops.
Signed-off-by: Suman Anna s-a...@ti.com
---
drivers/of/device.c | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 46d6c75c1404..fa27c1c71f29 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -50,6 +50,8 @@ EXPORT_SYMBOL(of_dev_put);
int of_device_add(struct platform_device *ofdev)
{
+ int i, ret;
+
BUG_ON(ofdev-dev.of_node == NULL);
/* name and id have to be set so that the platform bus doesn't get
@@ -63,7 +65,41 @@ int of_device_add(struct platform_device *ofdev)
if (!ofdev-dev.parent)
set_dev_node(ofdev-dev, of_node_to_nid(ofdev-dev.of_node));
- return device_add(ofdev-dev);
+ for (i = 0; i ofdev-num_resources; i++) {
+ struct resource *p, *r = ofdev-resource[i];
+
+ if (!r-name)
+ r-name = dev_name(ofdev-dev);
+
+ p = r-parent;
+ if (!p) {
+ if (resource_type(r) == IORESOURCE_MEM)
+ p = iomem_resource;
+ else if (resource_type(r) == IORESOURCE_IO)
+ p = ioport_resource;
+ }
+
+ if (p insert_resource(p, r)) {
+ dev_err(ofdev-dev, failed to claim resource %d\n,
+ i);
+ ret = -EBUSY;
+ goto failed;
+ }
+ }
+
+ ret = device_add(ofdev-dev);
+ if (ret == 0)
+ return ret;
+
+failed:
+ while (--i = 0) {
+ struct resource *r = ofdev-resource[i];
+ unsigned long type = resource_type(r);
+
+ if (type == IORESOURCE_MEM || type == IORESOURCE_IO)
+ release_resource(r);
+ }
+ return ret;
}
int of_device_register(struct platform_device *pdev)
--
2.2.1
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[PATCH v2 06/21] ARM: tegra: remove old LIC support
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c | 201 +---
arch/arm/mach-tegra/irq.h | 6 --
3 files changed, 2 insertions(+), 220 deletions(-)
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
#define TEGRA_ARM_INT_DIST_BASE0x50041000
#define TEGRA_ARM_INT_DIST_SIZESZ_4K
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
-
#define TEGRA_TMR1_BASE0x60005000
#define TEGRA_TMR1_SIZESZ_8
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index b37141d..a1befd3 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
#include board.h
#include iomap.h
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR 0x14
-#define ICTLR_CPU_IEP_FIR_SET 0x18
-#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-
-#define ICTLR_CPU_IER 0x20
-#define ICTLR_CPU_IER_SET 0x24
-#define ICTLR_CPU_IER_CLR 0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER 0x30
-#define ICTLR_COP_IER_SET 0x34
-#define ICTLR_COP_IER_CLR 0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS 5
-
#define SGI_MASK 0x
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
- IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
#ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
static void __iomem *tegra_gic_cpu_base;
#endif
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
}
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
- void __iomem *base;
- u32 mask;
-
- BUG_ON(irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
- base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
- __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return 0;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
- return 1;
-}
-
#ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
- u32 irq = d-hwirq;
- u32 index, mask;
-
- if (irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
- return -EINVAL;
-
- index = ((irq - FIRST_LEGACY_IRQ) / 32);
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
- if (enable)
- ictlr_wake_mask[index] |= mask;
- else
- ictlr_wake_mask[index] = ~mask;
-
- return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- /* Save interrupt state */
- cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
- cpu_iep[i] =
[PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.
The stacked irq domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-tegra.c | 335
2 files changed, 336 insertions(+)
create mode 100644 drivers/irqchip/irq-tegra.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..b4fc2e3
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,335 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR 0x14
+#define ICTLR_CPU_IEP_FIR_SET 0x18
+#define ICTLR_CPU_IEP_FIR_CLR 0x1c
+
+#define ICTLR_CPU_IER 0x20
+#define ICTLR_CPU_IER_SET 0x24
+#define ICTLR_CPU_IER_CLR 0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER 0x30
+#define ICTLR_COP_IER_SET 0x34
+#define ICTLR_COP_IER_CLR 0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS 5
+
+static int num_ictlrs;
+
+struct tegra_ictlr_info {
+ void __iomem *ictlr_reg_base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+ u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+ u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *tegra_ictlr_info;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long
reg)
+{
+ void __iomem *base = d-chip_data;
+ u32 mask;
+
+ mask = BIT(d-hwirq % 32);
+ writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+ irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+ irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+ irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+ return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+ u32 irq = d-hwirq;
+ u32 index, mask;
+
+ index = (irq / 32);
+ mask = BIT(irq % 32);
+ if (enable)
+ tegra_ictlr_info-ictlr_wake_mask[index] |= mask;
+ else
+ tegra_ictlr_info-ictlr_wake_mask[index] = ~mask;
+
+ /*
+* Do *not* call into the parent, as the GIC doesn't have any
+* wake-up facility...
+*/
+ return 0;
+}
+
+static int tegra_ictlr_suspend(void)
+{
+ unsigned long flags;
+ int i;
+
+ local_irq_save(flags);
+ for (i = 0; i num_ictlrs; i++) {
+ void __iomem *ictlr = tegra_ictlr_info-ictlr_reg_base[i];
+ /* Save interrupt state */
+ tegra_ictlr_info-cpu_ier[i] =
[PATCH v2 07/21] genirq: Add irqchip_set_wake_parent
This proves to be usefull with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
#endif
/* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
return -ENOSYS;
}
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data: Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+ data = data-parent_data;
+ if (data-chip-irq_set_wake)
+ return data-chip-irq_set_wake(data, on);
+
+ return -ENOSYS;
+}
#endif
/**
--
2.1.4
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[PATCH v2 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f70bed0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
/ {
compatible = nvidia,tegra114;
- interrupt-parent = gic;
+ interrupt-parent = ictlr;
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
+ };
+
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra114-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64,
+ 0x60004400 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..6ed6ca0 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
/ {
compatible = nvidia,tegra124;
- interrupt-parent = gic;
+ interrupt-parent = ictlr;
#address-cells = 2;
#size-cells = 2;
@@ -173,6 +173,7 @@
0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra124-ictlr, nvidia,tegra-ictlr;
+ reg = 0x0 0x60004000 0x0 0x40,
+ 0x0 0x60004100 0x0 0x40,
+ 0x0 0x60004200 0x0 0x40,
+ 0x0 0x60004300 0x0 0x40,
+ 0x0 0x60004400 0x0 0x40;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
+ };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..ab2f004 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
/ {
compatible = nvidia,tegra20;
- interrupt-parent = intc;
+ interrupt-parent = ictlr;
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+ interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+ interrupt-parent = intc;
};
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..c621e30
[PATCH v2 09/21] DT: update ti,irq-crossbar binding
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
Required properties:
- compatible : Should be ti,irq-crossbar
- reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt
controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be
routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
- crossbar_mpu: @4a02 {
+ crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
- ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further
details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as
a
-quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
- device_y@0x4a033000 {
- /* Direct mapped GIC SPI 1 used */
- interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
- ...
- };
--
2.1.4
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[PATCH v2 10/21] irqchip: GIC: get rid of routable domain
The only user of the so called routable domain functionnality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
}
static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
- gic_routable_irq_domain_ops-unmap(d, irq);
}
static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0]) {
- ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
- if (IS_ERR_VALUE(ret))
- return ret;
- }
+ if (!intspec[0])
+ *out_hwirq += 16;
*out_type = intspec[2] IRQ_TYPE_SENSE_MASK;
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
- return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
- struct device_node *controller,
- const u32 *intspec, unsigned int intsize,
- unsigned long *out_hwirq,
- unsigned int *out_type)
-{
- *out_hwirq += 16;
- return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
- .map = gic_routable_irq_domain_map,
- .unmap = gic_routable_irq_domain_unmap,
- .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
- gic_default_routable_irq_domain_ops;
-
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
- int nr_routable_irqs;
BUG_ON(gic_nr = MAX_GIC_NR);
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic-gic_irqs = gic_irqs;
if (node) { /* DT case */
- const struct irq_domain_ops *ops =
gic_irq_domain_hierarchy_ops;
-
- if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
- ops = gic_irq_domain_ops;
- gic_irqs = nr_routable_irqs;
- }
-
- gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+ gic-domain = irq_domain_add_linear(node, gic_irqs,
+
gic_irq_domain_hierarchy_ops,
+ gic);
} else {/* Non-DT case */
/*
* For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
void gic_migrate_target(unsigned int new_cpu_id);
unsigned long gic_get_sgir_physaddr(void);
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
- (const struct irq_domain_ops *ops)
-{
- gic_routable_irq_domain_ops = ops;
-}
[PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have landed in -next, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we already broke it for the OMAP WUGEN block, we might as well do it again for the TI crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die Comments welcome, M. Marc Zyngier (21): ARM: tegra: irq: nuke leftovers from non-DT support irqchip: tegra: add DT-based support for legacy interrupt controller ARM: tegra: skip gic_arch_extn setup if DT has a LIC node ARM: tegra: update DTs to expose legacy interrupt controller DT: tegra: add binding for the legacy interrupt controller ARM: tegra: remove old LIC support genirq: Add irqchip_set_wake_parent irqchip: crossbar: convert dra7 crossbar to stacked domains DT: update ti,irq-crossbar binding irqchip: GIC: get rid of routable domain DT: arm,gic: kill arm,routable-irqs ARM: omap: convert wakeupgen to stacked domains DT: omap4/5: add binding for the wake-up generator ARM: imx6: convert GPC to stacked domains ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding irqchip: gic: add an entry point to set up irqchip flags ARM: shmobile: remove use of gic_arch_extn.irq_set_wake ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags irqchip: gic: Drop support for gic_arch_extn Documentation/devicetree/bindings/arm/gic.txt | 6 - .../devicetree/bindings/arm/omap/crossbar.txt | 18 +- .../devicetree/bindings/arm/samsung/pmu.txt| 13 + .../interrupt-controller/nvidia,tegra-ictlr.txt| 39 +++ .../interrupt-controller/ti,omap4-wugen-mpu| 32 ++ arch/arm/boot/dts/am4372.dtsi | 11 +- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi| 43 ++- arch/arm/boot/dts/dra72-evm.dts| 1 - arch/arm/boot/dts/dra72x.dtsi | 3 +- arch/arm/boot/dts/dra74x.dtsi | 5 +- arch/arm/boot/dts/exynos4.dtsi | 3 + arch/arm/boot/dts/exynos5250.dtsi
[PATCH v2 01/21] ARM: tegra: irq: nuke leftovers from non-DT support
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-tegra/irq.c | 8 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ab95f53..7f87a50 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -283,13 +283,5 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_set_wake = tegra_set_wake; gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; - /* -* Check if there is a devicetree present, since the GIC will be -* initialized elsewhere under DT. -*/ - if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - tegra114_gic_cpu_pm_registration(); } -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/dra7-evm.dts | 2 +-
arch/arm/boot/dts/dra7.dtsi | 35 +++---
arch/arm/boot/dts/dra72-evm.dts | 1 -
arch/arm/boot/dts/dra72x.dtsi| 3 +-
arch/arm/boot/dts/dra74x.dtsi| 5 +-
arch/arm/mach-omap2/omap4-common.c | 4 -
drivers/irqchip/irq-crossbar.c | 202 ---
include/linux/irqchip/irq-crossbar.h | 11 --
8 files changed, 141 insertions(+), 122 deletions(-)
delete mode 100644 include/linux/irqchip/irq-crossbar.h
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..59ec0e6 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
#include skeleton.dtsi
#define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
/ {
#address-cells = 1;
#size-cells = 1;
compatible = ti,dra7xx;
- interrupt-parent = gic;
+ interrupt-parent = crossbar_mpu;
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
- arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
0x48212000 0x1000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
0x4500 0x1000;
- interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
- interrupts-extended = gic GIC_SPI 68
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart2;
clock-frequency = 4800;
status = disabled;
@@ -366,7 +366,7 @@
uart3: serial@4802 {
compatible = ti,omap4-uart;
reg = 0x4802 0x100;
- interrupts-extended = gic GIC_SPI 69
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart3;
clock-frequency = 4800;
status = disabled;
@@ -377,7 +377,7 @@
uart4: serial@4806e000 {
compatible = ti,omap4-uart;
reg = 0x4806e000 0x100;
- interrupts-extended = gic GIC_SPI 65
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI
[PATCH v2 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node
If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.
This is only a temporary measure until that code is removed for good.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/irq.c | 11 +++
arch/arm/mach-tegra/tegra.c | 1 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7f87a50..b37141d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -255,11 +255,21 @@ static void tegra114_gic_cpu_pm_registration(void)
static void tegra114_gic_cpu_pm_registration(void) { }
#endif
+static const struct of_device_id tegra_ictlr_match[] __initconst = {
+ { .compatible = nvidia,tegra-ictlr },
+ { }
+};
+
void __init tegra_init_irq(void)
{
int i;
void __iomem *distbase;
+ if (of_find_matching_node(NULL, tegra_ictlr_match))
+ goto skip_extn_setup;
+
+ tegra_legacy_irq_syscore_init();
+
distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f;
@@ -283,5 +293,6 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+skip_extn_setup:
tegra114_gic_cpu_pm_registration();
}
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af..c33fba7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -82,7 +82,6 @@ static void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
irqchip_init();
- tegra_legacy_irq_syscore_init();
}
static void __init tegra_dt_init(void)
--
2.1.4
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[PATCH v2 12/21] ARM: omap: convert wakeupgen to stacked domains
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like
this:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer
19: 233799 155916 GIC 27 arch_timer
23: 0 0 WUGEN 9 l3-dbg-irq
24: 1 0 WUGEN 10 l3-app-irq
27:282 0 WUGEN 13 omap-dma-engine
44: 0 0 4ae1.gpio 13 DMA
294: 0 0 WUGEN 20 gpmc
297:506 0 WUGEN 56 4807.i2c
298: 0 0 WUGEN 57 48072000.i2c
299: 0 0 WUGEN 61 4806.i2c
300: 0 0 WUGEN 62 4807a000.i2c
301: 8 0 WUGEN 60 4807c000.i2c
308: 2439 0 WUGEN 74 OMAP UART2
312:362 0 WUGEN 83 mmc2
313:502 0 WUGEN 86 mmc0
314: 13 0 WUGEN 94 mmc1
350: 0 0 PRCM pinctrl, pinctrl
406: 35155709 0 GIC 109 ehci_hcd:usb1
407: 0 0 WUGEN 7 palmas
409: 0 0 WUGEN 119 twl6040
410: 0 0 twl6040 5 twl6040_irq_ready
411: 0 0 twl6040 0 twl6040_irq_th
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 95334 902334 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4:479648 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am4372.dtsi | 11 ++-
arch/arm/boot/dts/dra7.dtsi | 12 ++-
arch/arm/boot/dts/dra72x.dtsi | 2 +-
arch/arm/boot/dts/dra74x.dtsi | 2 +-
arch/arm/boot/dts/omap4-duovero.dtsi | 2 -
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +-
arch/arm/boot/dts/omap4-sdp.dts | 8 +-
arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 -
arch/arm/boot/dts/omap4.dtsi | 18 -
arch/arm/boot/dts/omap5-cm-t54.dts| 1 -
arch/arm/boot/dts/omap5-uevm.dts | 2 -
arch/arm/boot/dts/omap5.dtsi | 24 --
arch/arm/mach-omap2/omap-wakeupgen.c | 125 +++---
arch/arm/mach-omap2/omap-wakeupgen.h | 1 -
arch/arm/mach-omap2/omap4-common.c| 1 -
15 files changed, 154 insertions(+), 65 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd..9d672a7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
/ {
compatible = ti,am4372, ti,am43;
- interrupt-parent = gic;
+ interrupt-parent = wakeupgen;
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
0x48240100 0x0100;
+ interrupt-parent = gic;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
};
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 59ec0e6..a5741ae 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -64,6 +64,14 @@
interrupt-parent = gic;
};
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@@ -92,7 +100,7 @@
reg = 0x4400 0x100,
0x4500 0x1000;
interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
- gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ wakeupgen GIC_SPI 10
[PATCH v2 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 3 +
arch/arm/boot/dts/exynos5250.dtsi | 3 +
arch/arm/boot/dts/exynos5420.dtsi | 3 +
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 126 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..adc189f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,8 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +255,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..c31007c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +232,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..1946c76c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,8 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..24fc7f8 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
-#include linux/irqchip/arm-gic.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
[PATCH v2 13/21] DT: omap4/5: add binding for the wake-up generator
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/ti,omap4-wugen-mpu| 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..16149d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,32 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controllerthat
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also refered to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+ are explicitely forbiden.
+
+Example:
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
--
2.1.4
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[PATCH v2 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
static void __init zynq_irq_init(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
}
--
2.1.4
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[PATCH v2 18/21] ARM: shmobile: remove use of gic_arch_extn.irq_set_wake
shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.
It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags function.
Acked-by: Simon Horman horms+rene...@verge.net.au
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-shmobile/intc-sh73a0.c | 7 +--
arch/arm/mach-shmobile/setup-r8a7779.c | 7 +--
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c
b/arch/arm/mach-shmobile/intc-sh73a0.c
index 9e36180..fd63ae6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,11 +252,6 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
-{
- return 0; /* always allow wakeup */
-}
-
#define PINTER0_PHYS 0xe69000a0
#define PINTER1_PHYS 0xe69000a4
#define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -318,8 +313,8 @@ void __init sh73a0_init_irq(void)
void __iomem *gic_cpu_base = IOMEM(0xf100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
- gic_arch_extn.irq_set_wake = sh73a0_set_wake;
register_intc_controller(intcs_desc);
register_intc_controller(intc_pint0_desc);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c
b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d17..989de2d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -713,14 +713,9 @@ void __init r8a7779_init_late(void)
}
#ifdef CONFIG_USE_OF
-static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
-{
- return 0; /* always allow wakeup */
-}
-
void __init r8a7779_init_irq_dt(void)
{
- gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
irqchip_init();
--
2.1.4
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[PATCH v2 05/21] DT: tegra: add binding for the legacy interrupt controller
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/nvidia,tegra-ictlr.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000..44fd873
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,39 @@
+NVIDIA Legacy Interrupt Controller
+
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+refered to as ictlr, hence the name of the binding.
+
+The HW block exposes a number of frames, each implementing a set of 32
+interrupts.
+
+Reguired properties:
+
+- compatible : should contain at least nvidia,tegra-ictlr.
+- reg : Specifies base physical address and size of the registers.
+ Each frame must be described separately.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+ are explicitely forbiden.
+
+Example:
+
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
--
2.1.4
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[PATCH v2 16/21] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v2 14/21] ARM: imx6: convert GPC to stacked domains
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 +-
arch/arm/boot/dts/imx6sl.dtsi | 5 +-
arch/arm/boot/dts/imx6sx.dtsi | 5 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 116 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..c16d428 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+ interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
@@ -694,8 +696,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..35099b7 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
ocram: sram@0090 {
@@ -603,7 +604,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..c476e67 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -131,7 +132,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
pmu {
@@ -700,7 +701,9 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
interrupts = GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
iomuxc: iomuxc@020e {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cfcdb62..7052302 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -102,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void
[PATCH v2 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
- arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
0xfff10100 0x100;
};
--
2.1.4
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[PATCH v2 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
*/
void __init ux500_init_irq(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
/*
--
2.1.4
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[PATCH v2 21/21] irqchip: gic: Drop support for gic_arch_extn
Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 54 -
include/linux/irqchip/arm-gic.h | 2 --
2 files changed, 56 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
#define NR_GIC_CPU_IF 8
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
- .irq_eoi= NULL,
- .irq_mask = NULL,
- .irq_unmask = NULL,
- .irq_retrigger = NULL,
- .irq_set_type = NULL,
- .irq_set_wake = NULL,
-};
-
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1
#endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
(gic_irq(d) / 32) * 4);
- if (gic_arch_extn.irq_mask)
- gic_arch_extn.irq_mask(d);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
- if (gic_arch_extn.irq_unmask)
- gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET +
(gic_irq(d) / 32) * 4);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_eoi_irq(struct irq_data *d)
{
- if (gic_arch_extn.irq_eoi) {
- raw_spin_lock(irq_controller_lock);
- gic_arch_extn.irq_eoi(d);
- raw_spin_unlock(irq_controller_lock);
- }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int
type)
if (type != IRQ_TYPE_LEVEL_HIGH type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
- raw_spin_lock(irq_controller_lock);
-
- if (gic_arch_extn.irq_set_type)
- gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
- raw_spin_unlock(irq_controller_lock);
-
return 0;
}
static int gic_retrigger(struct irq_data *d)
{
- if (gic_arch_extn.irq_retrigger)
- return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
}
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const
struct cpumask *mask_val,
}
#endif
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
- int ret = -ENXIO;
-
- if (gic_arch_extn.irq_set_wake)
- ret = gic_arch_extn.irq_set_wake(d, on);
-
- return ret;
-}
-
-#else
-#define gic_set_wake NULL
-#endif
-
static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
- .irq_set_wake = gic_set_wake,
};
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
set_handle_irq(gic_handle_irq);
}
- gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
struct device_node;
-extern struct irq_chip gic_arch_extn;
-
void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
--
2.1.4
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[PATCH v2 17/21] irqchip: gic: add an entry point to set up irqchip flags
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 5 +
include/linux/irqchip/arm-gic.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
+void gic_set_irqchip_flags(unsigned long flags)
+{
+ gic_chip.flags |= flags;
+}
+
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
extern struct irq_chip gic_arch_extn;
+void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
--
2.1.4
--
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