from:"Mugunthan V N"

[net-next PATCH 2/8] drivers: net: phy: at803x: seperate wol specific code to wol standard apis

2013-06-04 Thread Mugunthan V N

WOL is initilized in phy config_init, but there are standard apis
(set_wol/get_wol) for WOL in phy frame work. So this patch moves
WOL specific code from config_init to wol standard apis.

Cc: Matus Ujhelyi ujhely...@gmail.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/phy/at803x.c |   64 ++
 1 file changed, 48 insertions(+), 16 deletions(-)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index a1063e1..63444b7 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -32,10 +32,13 @@ MODULE_DESCRIPTION(Atheros 803x PHY driver);
 MODULE_AUTHOR(Matus Ujhelyi);
 MODULE_LICENSE(GPL);
 
-static void at803x_set_wol_mac_addr(struct phy_device *phydev)
+static int at803x_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
 {
struct net_device *ndev = phydev-attached_dev;
const u8 *mac;
+   int ret;
+   u32 value;
unsigned int i, offsets[] = {
AT803X_LOC_MAC_ADDR_32_47_OFFSET,
AT803X_LOC_MAC_ADDR_16_31_OFFSET,
@@ -43,30 +46,60 @@ static void at803x_set_wol_mac_addr(struct phy_device 
*phydev)
};
 
if (!ndev)
-   return;
+   return -ENODEV;
 
-   mac = (const u8 *) ndev-dev_addr;
+   if (wol-wolopts  WAKE_MAGIC) {
+   mac = (const u8 *) ndev-dev_addr;
 
-   if (!is_valid_ether_addr(mac))
-   return;
+   if (!is_valid_ether_addr(mac))
+   return -EFAULT;
 
-   for (i = 0; i  3; i++) {
-   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
+   for (i = 0; i  3; i++) {
+   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
  AT803X_DEVICE_ADDR);
-   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
+   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
  offsets[i]);
-   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
+   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
  AT803X_FUNC_DATA);
-   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
+   phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
  mac[(i * 2) + 1] | (mac[(i * 2)]  8));
+   }
+
+   value = phy_read(phydev, AT803X_INTR_ENABLE);
+   value |= AT803X_WOL_ENABLE;
+   ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
+   if (ret)
+   return ret;
+   value = phy_read(phydev, AT803X_INTR_STATUS);
+   } else {
+   value = phy_read(phydev, AT803X_INTR_ENABLE);
+   value = (~AT803X_WOL_ENABLE);
+   ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
+   if (ret)
+   return ret;
+   value = phy_read(phydev, AT803X_INTR_STATUS);
}
+
+   return ret;
+}
+
+static void at803x_get_wol(struct phy_device *phydev,
+  struct ethtool_wolinfo *wol)
+{
+   u32 value;
+
+   wol-supported = WAKE_MAGIC;
+   wol-wolopts = 0;
+
+   value = phy_read(phydev, AT803X_INTR_ENABLE);
+   if (value  AT803X_WOL_ENABLE)
+   wol-wolopts |= WAKE_MAGIC;
 }
 
 static int at803x_config_init(struct phy_device *phydev)
 {
int val;
u32 features;
-   int status;
 
features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI |
   SUPPORTED_FIBRE | SUPPORTED_BNC;
@@ -100,11 +133,6 @@ static int at803x_config_init(struct phy_device *phydev)
phydev-supported = features;
phydev-advertising = features;
 
-   /* enable WOL */
-   at803x_set_wol_mac_addr(phydev);
-   status = phy_write(phydev, AT803X_INTR_ENABLE, AT803X_WOL_ENABLE);
-   status = phy_read(phydev, AT803X_INTR_STATUS);
-
return 0;
 }
 
@@ -115,6 +143,8 @@ static struct phy_driver at803x_driver[] = {
.name   = Atheros 8035 ethernet,
.phy_id_mask= 0xffef,
.config_init= at803x_config_init,
+   .set_wol= at803x_set_wol,
+   .get_wol= at803x_get_wol,
.features   = PHY_GBIT_FEATURES,
.flags  = PHY_HAS_INTERRUPT,
.config_aneg= genphy_config_aneg,
@@ -128,6 +158,8 @@ static struct phy_driver at803x_driver[] = {
.name   = Atheros 8030 ethernet,
.phy_id_mask= 0xffef,
.config_init= at803x_config_init,
+   .set_wol= at803x_set_wol,
+   .get_wol= at803x_get_wol,
.features   = PHY_GBIT_FEATURES,
.flags  = PHY_HAS_INTERRUPT,
.config_aneg= genphy_config_aneg,
-- 
1.7.9.5

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[net-next PATCH 1/8] drivers: net: phy: at803x code cleanup on register and unregister driver

2013-06-04 Thread Mugunthan V N

Make use of phy_drivers_register/phy_drivers_unregister to register/unregister
multiple phy drivers in a single module.

Cc: Matus Ujhelyi ujhely...@gmail.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/phy/at803x.c |   35 ++-
 1 file changed, 10 insertions(+), 25 deletions(-)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 45cbc10..a1063e1 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -108,8 +108,9 @@ static int at803x_config_init(struct phy_device *phydev)
return 0;
 }
 
-/* ATHEROS 8035 */
-static struct phy_driver at8035_driver = {
+static struct phy_driver at803x_driver[] = {
+{
+   /* ATHEROS 8035 */
.phy_id = 0x004dd072,
.name   = Atheros 8035 ethernet,
.phy_id_mask= 0xffef,
@@ -121,10 +122,8 @@ static struct phy_driver at8035_driver = {
.driver = {
.owner = THIS_MODULE,
},
-};
-
-/* ATHEROS 8030 */
-static struct phy_driver at8030_driver = {
+}, {
+   /* ATHEROS 8030 */
.phy_id = 0x004dd076,
.name   = Atheros 8030 ethernet,
.phy_id_mask= 0xffef,
@@ -136,32 +135,18 @@ static struct phy_driver at8030_driver = {
.driver = {
.owner = THIS_MODULE,
},
-};
+} };
 
 static int __init atheros_init(void)
 {
-   int ret;
-
-   ret = phy_driver_register(at8035_driver);
-   if (ret)
-   goto err1;
-
-   ret = phy_driver_register(at8030_driver);
-   if (ret)
-   goto err2;
-
-   return 0;
-
-err2:
-   phy_driver_unregister(at8035_driver);
-err1:
-   return ret;
+   return phy_drivers_register(at803x_driver,
+   ARRAY_SIZE(at803x_driver));
 }
 
 static void __exit atheros_exit(void)
 {
-   phy_driver_unregister(at8035_driver);
-   phy_driver_unregister(at8030_driver);
+   return phy_drivers_unregister(at803x_driver,
+ ARRAY_SIZE(at803x_driver));
 }
 
 module_init(atheros_init);
-- 
1.7.9.5

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[net-next PATCH 6/8] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-06-04 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net-next PATCH 4/8] drivers: net: phy: at803x: add support for AT8031

2013-06-04 Thread Mugunthan V N

This patch adds support for Atheros 8031 phy driver.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/phy/at803x.c |   15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index dda07ed..1f7091b 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -183,6 +183,21 @@ static struct phy_driver at803x_driver[] = {
.driver = {
.owner = THIS_MODULE,
},
+}, {
+   /* ATHEROS 8031 */
+   .phy_id = 0x004dd074,
+   .name   = Atheros 8031 ethernet,
+   .phy_id_mask= 0xffef,
+   .config_init= at803x_config_init,
+   .set_wol= at803x_set_wol,
+   .get_wol= at803x_get_wol,
+   .features   = PHY_GBIT_FEATURES,
+   .flags  = PHY_HAS_INTERRUPT,
+   .config_aneg= genphy_config_aneg,
+   .read_status= genphy_read_status,
+   .driver = {
+   .owner = THIS_MODULE,
+   },
 } };
 
 static int __init atheros_init(void)
-- 
1.7.9.5

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[net-next PATCH 7/8] drivers: net: ethernet: cpsw: add phy-mode support to cpsw driver

2013-06-04 Thread Mugunthan V N

Adding phy-mode support to cpsw driver and updating the cpsw binding
documentation.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 Documentation/devicetree/bindings/net/cpsw.txt |6 ++
 drivers/net/ethernet/ti/cpsw.c |2 ++
 2 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
index 4f2ca6b..05d660e 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -28,6 +28,8 @@ Optional properties:
 Slave Properties:
 Required properties:
 - phy_id   : Specifies slave phy id
+- phy-mode : The interface between the SoC and the PHY (a string
+ that of_get_phy_mode() can understand)
 - mac-address  : Specifies slave MAC address
 
 Optional properties:
@@ -58,11 +60,13 @@ Examples:
cpts_clock_shift = 29;
cpsw_emac0: slave@0 {
phy_id = davinci_mdio, 0;
+   phy-mode = rgmii-txid;
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@1 {
phy_id = davinci_mdio, 1;
+   phy-mode = rgmii-txid;
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
@@ -84,11 +88,13 @@ Examples:
cpts_clock_shift = 29;
cpsw_emac0: slave@0 {
phy_id = davinci_mdio, 0;
+   phy-mode = rgmii-txid;
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@1 {
phy_id = davinci_mdio, 1;
+   phy-mode = rgmii-txid;
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 89a4c40..a45f64e 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1554,6 +1554,8 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
if (mac_addr)
memcpy(slave_data-mac_addr, mac_addr, ETH_ALEN);
 
+   slave_data-phy_if = of_get_phy_mode(slave_node);
+
if (data-dual_emac) {
if (of_property_read_u32(slave_node, 
dual_emac_res_vlan,
 prop)) {
-- 
1.7.9.5

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[net-next PATCH 5/8] ARM: OMAP2+: omap2plus_defconfig: Enable Atheros support

2013-06-04 Thread Mugunthan V N

Enable Atheros 803X phy driver support in defconfig which is present in
AM335x EVM and EVM Starter Kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/configs/omap2plus_defconfig |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/omap2plus_defconfig 
b/arch/arm/configs/omap2plus_defconfig
index 435d69b..aa21009 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -283,3 +283,4 @@ CONFIG_SOC_OMAP5=y
 CONFIG_TI_DAVINCI_MDIO=y
 CONFIG_TI_DAVINCI_CPDMA=y
 CONFIG_TI_CPSW=y
+CONFIG_AT803X_PHY=y
-- 
1.7.9.5

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Re: [net-next PATCH 1/8] drivers: net: phy: at803x code cleanup on register and unregister driver

2013-06-04 Thread Mugunthan V N


On 6/4/2013 5:32 PM, Sergei Shtylyov wrote:

Hello.

On 04-06-2013 10:10, Mugunthan V N wrote:

Make use of phy_drivers_register/phy_drivers_unregister to 
register/unregister

multiple phy drivers in a single module.



Cc: Matus Ujhelyi ujhely...@gmail.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
  drivers/net/phy/at803x.c |   35 ++-
  1 file changed, 10 insertions(+), 25 deletions(-)



diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 45cbc10..a1063e1 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -108,8 +108,9 @@ static int at803x_config_init(struct phy_device 
*phydev)

  return 0;
  }

-/* ATHEROS 8035 */
-static struct phy_driver at8035_driver = {
+static struct phy_driver at803x_driver[] = {
+{
+/* ATHEROS 8035 */
  .phy_id= 0x004dd072,
  .name= Atheros 8035 ethernet,
  .phy_id_mask= 0xffef,


That's improper indentation. Needs to be shifted by one tab.

This indentation is as per the coding style followed in all ethernet
phy drivers. If this need so to be changed, it must be a separate patch
for all the ethernet phy drivers.



@@ -136,32 +135,18 @@ static struct phy_driver at8030_driver = {
  .driver= {
  .owner = THIS_MODULE,
  },
-};
+} };


   Looks ugly...

This is also the same as per the style followed in ethernet phy drivers
Please refer the below grep output

$ grep -rnaI } }; drivers/net/phy/*
drivers/net/phy/at803x.c:201:} };
drivers/net/phy/bcm63xx.c:101:} };
drivers/net/phy/bcm87xx.c:217:} };
drivers/net/phy/broadcom.c:829:} };
drivers/net/phy/cicada.c:130:} };
drivers/net/phy/davicom.c:183:} };
drivers/net/phy/icplus.c:254:} };
drivers/net/phy/lxt.c:313:} };
drivers/net/phy/micrel.c:323:} };
drivers/net/phy/smsc.c:242:} };
drivers/net/phy/ste10Xp.c:113:} };
drivers/net/phy/vitesse.c:192:} };

Regards
Mugunthan V N
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[net-next PATCH 1/1] drivers: net: davinci_cpdma: remove CRC bytes from skb added by CPDMA

2013-05-30 Thread Mugunthan V N

Additional 4 bytes found in the skb is the CRC calculated by the
CPDMA hardware, check the CRC bit in CPDMA status field of
Descriptor and remove the CRC length from the skb. This extra
4 byte can be seen when capturing packets using tcpdump.
This has been tested in TI816x platform.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_cpdma.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c 
b/drivers/net/ethernet/ti/davinci_cpdma.c
index 49dfd59..a377bc7 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -64,6 +64,7 @@
 #define CPDMA_DESC_TO_PORT_EN  BIT(20)
 #define CPDMA_TO_PORT_SHIFT16
 #define CPDMA_DESC_PORT_MASK   (BIT(18) | BIT(17) | BIT(16))
+#define CPDMA_DESC_CRC_LEN 4
 
 #define CPDMA_TEARDOWN_VALUE   0xfffc
 
@@ -798,6 +799,10 @@ static int __cpdma_chan_process(struct cpdma_chan *chan)
status = -EBUSY;
goto unlock_ret;
}
+
+   if (status  CPDMA_DESC_PASS_CRC)
+   outlen -= CPDMA_DESC_CRC_LEN;
+
status  = status  (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
CPDMA_DESC_PORT_MASK);
 
-- 
1.7.9.5

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Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support

2013-05-30 Thread Mugunthan V N


On 5/28/2013 7:35 PM, Mugunthan V N wrote:

On 5/28/2013 3:06 AM, Tony Lindgren wrote:

* Mugunthan V N mugunthan...@ti.com [130526 11:28]:

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
  drivers/net/ethernet/ti/cpsw.c |   48 


  1 file changed, 48 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c 
b/drivers/net/ethernet/ti/cpsw.c

index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
  #include linux/if_vlan.h
#include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
#include cpsw_ale.h
  #include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
  bool irq_enabled;
  struct cpts *cpts;
  u32 emac_port;
+
+/* Two optional pin states - default  sleep */
+struct pinctrl*pinctrl;
+struct pinctrl_state*pins_def;
+struct pinctrl_state*pins_sleep;
  };

Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.

Regards,

Tony

Tony

I am using this for all the pins, in probe all the cpsw pins will be 
configured

and i have used the same in suspend/resume callback for power saving.


Tony

Do you have any comments on this, or is it ok with two pinctrl_state nodes?

Regards
Mugunthan V N

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Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support

2013-05-28 Thread Mugunthan V N


On 5/28/2013 3:06 AM, Tony Lindgren wrote:

* Mugunthan V N mugunthan...@ti.com [130526 11:28]:

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
  drivers/net/ethernet/ti/cpsw.c |   48 
  1 file changed, 48 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
  #include linux/if_vlan.h
  
  #include linux/platform_data/cpsw.h

+#include linux/pinctrl/consumer.h
  
  #include cpsw_ale.h

  #include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_def;
+   struct pinctrl_state*pins_sleep;
  };

Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.

Regards,

Tony

Tony

I am using this for all the pins, in probe all the cpsw pins will be 
configured

and i have used the same in suspend/resume callback for power saving.

Regards
Mugunthan V N
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Re: [net-next PATCH v2 1/6] net: cpsw: enhance pinctrl support

2013-05-26 Thread Mugunthan V N

On 5/26/2013 12:12 PM, David Miller wrote:

From: Mugunthan V N mugunthan...@ti.com
Date: Thu, 23 May 2013 18:00:23 +0530

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com

This still needs some work:

+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */

The second, third, fourth, and fifth lines are not tabbed correctly.  They
should all be two TABs and a SPACE.

Secondly, comments in the networking are to be formatted:

/* Like
 * this.
 */

Will fix this and will resubmit the next version today.

Regards
Mugunthan V N
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[net-next PATCH v3 0/6] Adding pinctrl PM support for CPSW and MDIO

2013-05-26 Thread Mugunthan V N

This patch series adds the following features
* Adding pinctrl PM support for CPSW and MDIO for Power Optimization
* Adding phy address to the CPSW node for EVMsk board

Changes from initial version
* Fixed the multiline function call indentation as per David Miller
  recommendation.

Changes from v2
* Fixed the multi comment style as per net coding style
* Fixed checkpatch error (more than 80 characters)


Hebbar Gururaja (1):
  net: cpsw: enhance pinctrl support

Mugunthan V N (5):
  net: davinci_mdio: enhance pinctrl support
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

 arch/arm/boot/dts/am335x-bone.dts  |   38 +
 arch/arm/boot/dts/am335x-evm.dts   |   36 
 arch/arm/boot/dts/am335x-evmsk.dts |   58 
 drivers/net/ethernet/ti/cpsw.c |   48 ++
 drivers/net/ethernet/ti/davinci_mdio.c |   45 +
 5 files changed, 225 insertions(+)

-- 
1.7.9.5

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[net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support

2013-05-26 Thread Mugunthan V N

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   48 
 1 file changed, 48 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
 #include linux/if_vlan.h
 
 #include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
 
 #include cpsw_ale.h
 #include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_def;
+   struct pinctrl_state*pins_sleep;
 };
 
 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,35 @@ static int cpsw_probe(struct platform_device *pdev)
 */
pm_runtime_enable(pdev-dev);
 
+   priv-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(priv-pinctrl)) {
+   priv-pins_def = pinctrl_lookup_state(priv-pinctrl,
+ PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(priv-pins_def))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(priv-pinctrl,
+priv-pins_def))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   priv-pins_sleep = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(priv-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+   priv-pins_def = ERR_PTR(-ENODATA);
+   priv-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
if (cpsw_probe_dt(priv-data, pdev)) {
pr_err(cpsw: platform data missing\n);
ret = -ENODEV;
@@ -1973,11 +2008,17 @@ static int cpsw_suspend(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(pdev-dev);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(priv-pins_sleep))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -1985,8 +2026,15 @@ static int cpsw_resume(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
pm_runtime_get_sync(pdev-dev);
+
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(priv-pins_def))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_def))
+   dev_err(dev, could not set default pins\n);
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
-- 
1.7.9.5

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[net-next PATCH v3 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

2013-05-26 Thread Mugunthan V N

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evm.dts |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..beb2fbf 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27  /* spi0_d0.gpio0_3, INPUT | 
MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -237,6 +263,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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[net-next PATCH v3 2/6] net: davinci_mdio: enhance pinctrl support

2013-05-26 Thread Mugunthan V N

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_mdio.c |   45 
 1 file changed, 45 insertions(+)

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c 
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..9e6aaeb 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
 #include linux/davinci_emac.h
 #include linux/of.h
 #include linux/of_device.h
+#include linux/pinctrl/consumer.h
 
 /*
  * This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus  *bus;
boolsuspended;
unsigned long   access_time; /* jiffies */
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_def;
+   struct pinctrl_state*pins_sleep;
 };
 
 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,35 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data-bus-parent   = dev;
data-bus-priv = data;
 
+   data-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(data-pinctrl)) {
+   data-pins_def = pinctrl_lookup_state(data-pinctrl,
+ PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(data-pins_def))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(data-pinctrl,
+data-pins_def))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   data-pins_sleep = pinctrl_lookup_state(data-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(data-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+   data-pins_def = ERR_PTR(-ENODATA);
+   data-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
pm_runtime_enable(pdev-dev);
pm_runtime_get_sync(pdev-dev);
data-clk = clk_get(pdev-dev, fck);
@@ -454,6 +489,11 @@ static int davinci_mdio_suspend(struct device *dev)
data-suspended = true;
spin_unlock(data-lock);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(data-pins_sleep))
+   if (pinctrl_select_state(data-pinctrl, data-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -465,6 +505,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(data-lock);
pm_runtime_get_sync(data-dev);
 
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(data-pins_def))
+   if (pinctrl_select_state(data-pinctrl, data-pins_def))
+   dev_err(dev, could not set default pins\n);
+
/* restart the scan state machine */
ctrl = __raw_readl(data-regs-control);
ctrl |= CONTROL_ENABLE;
-- 
1.7.9.5

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[net-next PATCH v3 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone

2013-05-26 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-bone.dts |   38 +
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts 
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..97294a6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17   /* gpmc_a8.gpio1_24, 
OUTPUT_PULLUP | MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x110 0x20  /* mii1_rxerr.mii1_rxerr, MODE0 
| INPUT */
+   0x114 0x0   /* mii1_txen.mii1_txen, MODE0 | 
OUTPUT */
+   0x118 0x20  /* mii1_rxdv.mii1_rxdv, MODE0 | 
INPUT_PULLDOWN */
+   0x11c 0x0   /* mii1_txd3.mii1_txd3, MODE0 | 
OUTPUT */
+   0x120 0x0   /* mii1_txd2.mii1_txd2, MODE0 | 
OUTPUT */
+   0x124 0x0   /* mii1_txd1.mii1_txd1, MODE0 | 
OUTPUT */
+   0x128 0x0   /* mii1_txd0.mii1_txd0, MODE0 | 
OUTPUT */
+   0x12c 0x20  /* mii1_txclk.mii1_txclk, MODE0 
| INPUT_PULLDOWN */
+   0x130 0x20  /* mii1_rxclk.mii1_rxclk, MODE0 
| INPUT_PULLDOWN */
+   0x134 0x20  /* mii1_rxd3.mii1_rxd3, MODE0 | 
INPUT_PULLDOWN */
+   0x138 0x20  /* mii1_rxd2.mii1_rxd2, MODE0 | 
INPUT_PULLDOWN */
+   0x13c 0x20  /* mii1_rxd1.mii1_rxd1, MODE0 | 
INPUT_PULLDOWN */
+   0x140 0x20  /* mii1_rxd0.mii1_rxd0, MODE0 | 
INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -136,3 +163,14 @@
 cpsw_emac1 {
phy_id = davinci_mdio, 1;
 };
+
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
-- 
1.7.9.5

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[net-next PATCH v3 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-05-26 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net-next PATCH v3 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk

2013-05-26 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |   50 
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..12cbe4e 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27   /* gpmc_ben0_cle.gpio2_5, INPUT 
| MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* Slave 2 */
+   0x40 0x2/* gpmc_a0.rgmii2_tctl, MODE2 
| OUTPUT */
+   0x44 0x22   /* gpmc_a1.rgmii2_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x48 0x2/* gpmc_a2.rgmii2_td3, MODE2 | 
OUTPUT */
+   0x4c 0x2/* gpmc_a3.rgmii2_td2, MODE2 | 
OUTPUT */
+   0x50 0x2/* gpmc_a4.rgmii2_td1, MODE2 | 
OUTPUT */
+   0x54 0x2/* gpmc_a5.rgmii2_td0, MODE2 | 
OUTPUT */
+   0x58 0x2/* gpmc_a6.rgmii2_tclk, MODE2 
| OUTPUT */
+   0x5c 0x22   /* gpmc_a7.rgmii2_rclk, MODE2 
| INPUT_PULLDOWN */
+   0x60 0x22   /* gpmc_a8.rgmii2_rd3, MODE2 | 
INPUT_PULLDOWN */
+   0x64 0x22   /* gpmc_a9.rgmii2_rd2, MODE2 | 
INPUT_PULLDOWN */
+   0x68 0x22   /* gpmc_a10.rgmii2_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x6c 0x22   /* gpmc_a11.rgmii2_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -249,6 +289,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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Re: [net-next resend PATCH 1/6] net: cpsw: enhance pinctrl support

2013-05-23 Thread Mugunthan V N

On 5/23/2013 12:27 PM, David Miller wrote:

From: Mugunthan V N mugunthan...@ti.com
Date: Tue, 21 May 2013 15:24:58 +0530

+   priv-pins_default = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_DEFAULT);

This is not indented correctly.

Argument on the second, and subsequent, lines of a function call
must start at the first column after the openning parenthesis of
the function call itself.

Please audit for this problem in your entire patch series, fix
it up, and resubmit the full set of patches.

Thanks.

Will fix it and submit the patch.

Regards
Mugunthan V N
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[net-next PATCH v2 0/6] Adding pinctrl PM support for CPSW and MDIO

2013-05-23 Thread Mugunthan V N

This patch series adds the following features
* Adding pinctrl PM support for CPSW and MDIO for Power Optimization
* Adding phy address to the CPSW node for EVMsk board

Changes from initial version
* Fixed the multiline function call indentation as per David Miller
  recommendation.

Hebbar Gururaja (1):
  net: cpsw: enhance pinctrl support

Mugunthan V N (5):
  net: davinci_mdio: enhance pinctrl support
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

 arch/arm/boot/dts/am335x-bone.dts  |   38 +
 arch/arm/boot/dts/am335x-evm.dts   |   36 
 arch/arm/boot/dts/am335x-evmsk.dts |   58 
 drivers/net/ethernet/ti/cpsw.c |   49 +++
 drivers/net/ethernet/ti/davinci_mdio.c |   46 +
 5 files changed, 227 insertions(+)

-- 
1.7.9.5

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[net-next PATCH v2 1/6] net: cpsw: enhance pinctrl support

2013-05-23 Thread Mugunthan V N

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   49 
 1 file changed, 49 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..1150f06 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
 #include linux/if_vlan.h
 
 #include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
 
 #include cpsw_ale.h
 #include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_default;
+   struct pinctrl_state*pins_sleep;
 };
 
 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev)
 */
pm_runtime_enable(pdev-dev);
 
+   priv-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(priv-pinctrl)) {
+   priv-pins_default = pinctrl_lookup_state(priv-pinctrl,
+ 
PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(priv-pins_default))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(priv-pinctrl,
+priv-pins_default))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   priv-pins_sleep = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(priv-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */
+   priv-pins_default = ERR_PTR(-ENODATA);
+   priv-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
if (cpsw_probe_dt(priv-data, pdev)) {
pr_err(cpsw: platform data missing\n);
ret = -ENODEV;
@@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(pdev-dev);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(priv-pins_sleep))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
pm_runtime_get_sync(pdev-dev);
+
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(priv-pins_default))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_default))
+   dev_err(dev, could not set default pins\n);
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
-- 
1.7.9.5

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[net-next PATCH v2 2/6] net: davinci_mdio: enhance pinctrl support

2013-05-23 Thread Mugunthan V N

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_mdio.c |   46 
 1 file changed, 46 insertions(+)

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c 
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..0026006 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
 #include linux/davinci_emac.h
 #include linux/of.h
 #include linux/of_device.h
+#include linux/pinctrl/consumer.h
 
 /*
  * This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus  *bus;
boolsuspended;
unsigned long   access_time; /* jiffies */
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_default;
+   struct pinctrl_state*pins_sleep;
 };
 
 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,36 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data-bus-parent   = dev;
data-bus-priv = data;
 
+   data-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(data-pinctrl)) {
+   data-pins_default = pinctrl_lookup_state(data-pinctrl,
+ 
PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(data-pins_default))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(data-pinctrl,
+data-pins_default))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   data-pins_sleep = pinctrl_lookup_state(data-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(data-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */
+   data-pins_default = ERR_PTR(-ENODATA);
+   data-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
pm_runtime_enable(pdev-dev);
pm_runtime_get_sync(pdev-dev);
data-clk = clk_get(pdev-dev, fck);
@@ -454,6 +490,11 @@ static int davinci_mdio_suspend(struct device *dev)
data-suspended = true;
spin_unlock(data-lock);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(data-pins_sleep))
+   if (pinctrl_select_state(data-pinctrl, data-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -465,6 +506,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(data-lock);
pm_runtime_get_sync(data-dev);
 
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(data-pins_default))
+   if (pinctrl_select_state(data-pinctrl, data-pins_default))
+   dev_err(dev, could not set default pins\n);
+
/* restart the scan state machine */
ctrl = __raw_readl(data-regs-control);
ctrl |= CONTROL_ENABLE;
-- 
1.7.9.5

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[net-next PATCH v2 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone

2013-05-23 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-bone.dts |   38 +
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts 
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..97294a6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17   /* gpmc_a8.gpio1_24, 
OUTPUT_PULLUP | MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x110 0x20  /* mii1_rxerr.mii1_rxerr, MODE0 
| INPUT */
+   0x114 0x0   /* mii1_txen.mii1_txen, MODE0 | 
OUTPUT */
+   0x118 0x20  /* mii1_rxdv.mii1_rxdv, MODE0 | 
INPUT_PULLDOWN */
+   0x11c 0x0   /* mii1_txd3.mii1_txd3, MODE0 | 
OUTPUT */
+   0x120 0x0   /* mii1_txd2.mii1_txd2, MODE0 | 
OUTPUT */
+   0x124 0x0   /* mii1_txd1.mii1_txd1, MODE0 | 
OUTPUT */
+   0x128 0x0   /* mii1_txd0.mii1_txd0, MODE0 | 
OUTPUT */
+   0x12c 0x20  /* mii1_txclk.mii1_txclk, MODE0 
| INPUT_PULLDOWN */
+   0x130 0x20  /* mii1_rxclk.mii1_rxclk, MODE0 
| INPUT_PULLDOWN */
+   0x134 0x20  /* mii1_rxd3.mii1_rxd3, MODE0 | 
INPUT_PULLDOWN */
+   0x138 0x20  /* mii1_rxd2.mii1_rxd2, MODE0 | 
INPUT_PULLDOWN */
+   0x13c 0x20  /* mii1_rxd1.mii1_rxd1, MODE0 | 
INPUT_PULLDOWN */
+   0x140 0x20  /* mii1_rxd0.mii1_rxd0, MODE0 | 
INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -136,3 +163,14 @@
 cpsw_emac1 {
phy_id = davinci_mdio, 1;
 };
+
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
-- 
1.7.9.5

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[net-next PATCH v2 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-05-23 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net-next PATCH v2 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

2013-05-23 Thread Mugunthan V N

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evm.dts |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..beb2fbf 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27  /* spi0_d0.gpio0_3, INPUT | 
MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -237,6 +263,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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[net-next PATCH v2 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk

2013-05-23 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |   50 
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..12cbe4e 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27   /* gpmc_ben0_cle.gpio2_5, INPUT 
| MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* Slave 2 */
+   0x40 0x2/* gpmc_a0.rgmii2_tctl, MODE2 
| OUTPUT */
+   0x44 0x22   /* gpmc_a1.rgmii2_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x48 0x2/* gpmc_a2.rgmii2_td3, MODE2 | 
OUTPUT */
+   0x4c 0x2/* gpmc_a3.rgmii2_td2, MODE2 | 
OUTPUT */
+   0x50 0x2/* gpmc_a4.rgmii2_td1, MODE2 | 
OUTPUT */
+   0x54 0x2/* gpmc_a5.rgmii2_td0, MODE2 | 
OUTPUT */
+   0x58 0x2/* gpmc_a6.rgmii2_tclk, MODE2 
| OUTPUT */
+   0x5c 0x22   /* gpmc_a7.rgmii2_rclk, MODE2 
| INPUT_PULLDOWN */
+   0x60 0x22   /* gpmc_a8.rgmii2_rd3, MODE2 | 
INPUT_PULLDOWN */
+   0x64 0x22   /* gpmc_a9.rgmii2_rd2, MODE2 | 
INPUT_PULLDOWN */
+   0x68 0x22   /* gpmc_a10.rgmii2_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x6c 0x22   /* gpmc_a11.rgmii2_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -249,6 +289,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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[net-next resend PATCH 0/6] Adding pinctrl PM support for CPSW and MDIO

2013-05-21 Thread Mugunthan V N

Resending the same patch series as it is dropped which was sent
during merge window

This patch series adds the following features
* Adding pinctrl PM support for CPSW and MDIO for Power Optimization
* Adding phy address to the CPSW node for EVMsk board

Hebbar Gururaja (1):
  net: cpsw: enhance pinctrl support

Mugunthan V N (5):
  net: davinci_mdio: enhance pinctrl support
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

 arch/arm/boot/dts/am335x-bone.dts  |   38 +
 arch/arm/boot/dts/am335x-evm.dts   |   36 
 arch/arm/boot/dts/am335x-evmsk.dts |   58 
 drivers/net/ethernet/ti/cpsw.c |   49 +++
 drivers/net/ethernet/ti/davinci_mdio.c |   46 +
 5 files changed, 227 insertions(+)

-- 
1.7.9.5

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[net-next resend PATCH 1/6] net: cpsw: enhance pinctrl support

2013-05-21 Thread Mugunthan V N

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   49 
 1 file changed, 49 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..4a6f94b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
 #include linux/if_vlan.h
 
 #include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
 
 #include cpsw_ale.h
 #include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_default;
+   struct pinctrl_state*pins_sleep;
 };
 
 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev)
 */
pm_runtime_enable(pdev-dev);
 
+   priv-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(priv-pinctrl)) {
+   priv-pins_default = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(priv-pins_default))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(priv-pinctrl,
+priv-pins_default))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   priv-pins_sleep = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(priv-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */
+   priv-pins_default = ERR_PTR(-ENODATA);
+   priv-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
if (cpsw_probe_dt(priv-data, pdev)) {
pr_err(cpsw: platform data missing\n);
ret = -ENODEV;
@@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(pdev-dev);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(priv-pins_sleep))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
pm_runtime_get_sync(pdev-dev);
+
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(priv-pins_default))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_default))
+   dev_err(dev, could not set default pins\n);
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
-- 
1.7.9.5

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[net-next resend PATCH 2/6] net: davinci_mdio: enhance pinctrl support

2013-05-21 Thread Mugunthan V N

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_mdio.c |   46 
 1 file changed, 46 insertions(+)

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c 
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..be81d3e 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
 #include linux/davinci_emac.h
 #include linux/of.h
 #include linux/of_device.h
+#include linux/pinctrl/consumer.h
 
 /*
  * This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus  *bus;
boolsuspended;
unsigned long   access_time; /* jiffies */
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_default;
+   struct pinctrl_state*pins_sleep;
 };
 
 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,36 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data-bus-parent   = dev;
data-bus-priv = data;
 
+   data-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(data-pinctrl)) {
+   data-pins_default = pinctrl_lookup_state(data-pinctrl,
+   PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(data-pins_default))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(data-pinctrl,
+data-pins_default))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   data-pins_sleep = pinctrl_lookup_state(data-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(data-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */
+   data-pins_default = ERR_PTR(-ENODATA);
+   data-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
pm_runtime_enable(pdev-dev);
pm_runtime_get_sync(pdev-dev);
data-clk = clk_get(pdev-dev, fck);
@@ -454,6 +490,11 @@ static int davinci_mdio_suspend(struct device *dev)
data-suspended = true;
spin_unlock(data-lock);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(data-pins_sleep))
+   if (pinctrl_select_state(data-pinctrl, data-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -465,6 +506,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(data-lock);
pm_runtime_get_sync(data-dev);
 
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(data-pins_default))
+   if (pinctrl_select_state(data-pinctrl, data-pins_default))
+   dev_err(dev, could not set default pins\n);
+
/* restart the scan state machine */
ctrl = __raw_readl(data-regs-control);
ctrl |= CONTROL_ENABLE;
-- 
1.7.9.5

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[net-next resend PATCH 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-05-21 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net-next resend PATCH 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk

2013-05-21 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |   50 
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..12cbe4e 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27   /* gpmc_ben0_cle.gpio2_5, INPUT 
| MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* Slave 2 */
+   0x40 0x2/* gpmc_a0.rgmii2_tctl, MODE2 
| OUTPUT */
+   0x44 0x22   /* gpmc_a1.rgmii2_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x48 0x2/* gpmc_a2.rgmii2_td3, MODE2 | 
OUTPUT */
+   0x4c 0x2/* gpmc_a3.rgmii2_td2, MODE2 | 
OUTPUT */
+   0x50 0x2/* gpmc_a4.rgmii2_td1, MODE2 | 
OUTPUT */
+   0x54 0x2/* gpmc_a5.rgmii2_td0, MODE2 | 
OUTPUT */
+   0x58 0x2/* gpmc_a6.rgmii2_tclk, MODE2 
| OUTPUT */
+   0x5c 0x22   /* gpmc_a7.rgmii2_rclk, MODE2 
| INPUT_PULLDOWN */
+   0x60 0x22   /* gpmc_a8.rgmii2_rd3, MODE2 | 
INPUT_PULLDOWN */
+   0x64 0x22   /* gpmc_a9.rgmii2_rd2, MODE2 | 
INPUT_PULLDOWN */
+   0x68 0x22   /* gpmc_a10.rgmii2_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x6c 0x22   /* gpmc_a11.rgmii2_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -249,6 +289,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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[net-next resend PATCH 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

2013-05-21 Thread Mugunthan V N

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evm.dts |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..beb2fbf 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27  /* spi0_d0.gpio0_3, INPUT | 
MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -237,6 +263,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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[net-next resend PATCH 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone

2013-05-21 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-bone.dts |   38 +
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts 
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..97294a6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17   /* gpmc_a8.gpio1_24, 
OUTPUT_PULLUP | MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x110 0x20  /* mii1_rxerr.mii1_rxerr, MODE0 
| INPUT */
+   0x114 0x0   /* mii1_txen.mii1_txen, MODE0 | 
OUTPUT */
+   0x118 0x20  /* mii1_rxdv.mii1_rxdv, MODE0 | 
INPUT_PULLDOWN */
+   0x11c 0x0   /* mii1_txd3.mii1_txd3, MODE0 | 
OUTPUT */
+   0x120 0x0   /* mii1_txd2.mii1_txd2, MODE0 | 
OUTPUT */
+   0x124 0x0   /* mii1_txd1.mii1_txd1, MODE0 | 
OUTPUT */
+   0x128 0x0   /* mii1_txd0.mii1_txd0, MODE0 | 
OUTPUT */
+   0x12c 0x20  /* mii1_txclk.mii1_txclk, MODE0 
| INPUT_PULLDOWN */
+   0x130 0x20  /* mii1_rxclk.mii1_rxclk, MODE0 
| INPUT_PULLDOWN */
+   0x134 0x20  /* mii1_rxd3.mii1_rxd3, MODE0 | 
INPUT_PULLDOWN */
+   0x138 0x20  /* mii1_rxd2.mii1_rxd2, MODE0 | 
INPUT_PULLDOWN */
+   0x13c 0x20  /* mii1_rxd1.mii1_rxd1, MODE0 | 
INPUT_PULLDOWN */
+   0x140 0x20  /* mii1_rxd0.mii1_rxd0, MODE0 | 
INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -136,3 +163,14 @@
 cpsw_emac1 {
phy_id = davinci_mdio, 1;
 };
+
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
-- 
1.7.9.5

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[net-next PATCH 0/6] Adding pinctrl PM support for CPSW and Davinci MDIO drivers

2013-05-03 Thread Mugunthan V N

This patch series adds the following features
* Adding pinctrl PM support for CPSW and MDIO for Power Optimization
* Adding phy address to the CPSW node for EVMsk board

Hebbar Gururaja (1):
  net: cpsw: enhance pinctrl support

Mugunthan V N (5):
  net: davinci_mdio: enhance pinctrl support
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

 arch/arm/boot/dts/am335x-bone.dts  |   38 +
 arch/arm/boot/dts/am335x-evm.dts   |   36 
 arch/arm/boot/dts/am335x-evmsk.dts |   58 
 drivers/net/ethernet/ti/cpsw.c |   49 +++
 drivers/net/ethernet/ti/davinci_mdio.c |   46 +
 5 files changed, 227 insertions(+)

-- 
1.7.9.5

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[net-next PATCH 1/6] net: cpsw: enhance pinctrl support

2013-05-03 Thread Mugunthan V N

From: Hebbar Gururaja gururaja.heb...@ti.com

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   49 
 1 file changed, 49 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..4a6f94b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
 #include linux/if_vlan.h
 
 #include linux/platform_data/cpsw.h
+#include linux/pinctrl/consumer.h
 
 #include cpsw_ale.h
 #include cpts.h
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_default;
+   struct pinctrl_state*pins_sleep;
 };
 
 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev)
 */
pm_runtime_enable(pdev-dev);
 
+   priv-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(priv-pinctrl)) {
+   priv-pins_default = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(priv-pins_default))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(priv-pinctrl,
+priv-pins_default))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   priv-pins_sleep = pinctrl_lookup_state(priv-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(priv-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */
+   priv-pins_default = ERR_PTR(-ENODATA);
+   priv-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
if (cpsw_probe_dt(priv-data, pdev)) {
pr_err(cpsw: platform data missing\n);
ret = -ENODEV;
@@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(pdev-dev);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(priv-pins_sleep))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
 {
struct platform_device  *pdev = to_platform_device(dev);
struct net_device   *ndev = platform_get_drvdata(pdev);
+   struct cpsw_priv*priv = netdev_priv(ndev);
 
pm_runtime_get_sync(pdev-dev);
+
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(priv-pins_default))
+   if (pinctrl_select_state(priv-pinctrl, priv-pins_default))
+   dev_err(dev, could not set default pins\n);
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
-- 
1.7.9.5

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[net-next PATCH 2/6] net: davinci_mdio: enhance pinctrl support

2013-05-03 Thread Mugunthan V N

Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:

- default on boot, resume
- sleep on suspend()

This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.

If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_mdio.c |   46 
 1 file changed, 46 insertions(+)

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c 
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..be81d3e 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
 #include linux/davinci_emac.h
 #include linux/of.h
 #include linux/of_device.h
+#include linux/pinctrl/consumer.h
 
 /*
  * This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus  *bus;
boolsuspended;
unsigned long   access_time; /* jiffies */
+
+   /* Two optional pin states - default  sleep */
+   struct pinctrl  *pinctrl;
+   struct pinctrl_state*pins_default;
+   struct pinctrl_state*pins_sleep;
 };
 
 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,36 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data-bus-parent   = dev;
data-bus-priv = data;
 
+   data-pinctrl = devm_pinctrl_get(pdev-dev);
+   if (!IS_ERR(data-pinctrl)) {
+   data-pins_default = pinctrl_lookup_state(data-pinctrl,
+   PINCTRL_STATE_DEFAULT);
+   /* enable pins to be muxed in and configured */
+   if (IS_ERR(data-pins_default))
+   dev_warn(pdev-dev, could not get default 
pinstate\n);
+   else
+   if (pinctrl_select_state(data-pinctrl,
+data-pins_default))
+   dev_err(pdev-dev,
+   could not set default pins\n);
+
+   data-pins_sleep = pinctrl_lookup_state(data-pinctrl,
+   PINCTRL_STATE_SLEEP);
+   if (IS_ERR(data-pins_sleep))
+   dev_warn(pdev-dev, could not get sleep pinstate\n);
+   } else {
+   /*
+   * Since we continue even when pinctrl node is not found,
+   * Invalidate pins as not available. This is to make sure that
+   * IS_ERR(pins_xxx) results in failure when used.
+   */
+   data-pins_default = ERR_PTR(-ENODATA);
+   data-pins_sleep = ERR_PTR(-ENODATA);
+
+   dev_warn(pdev-dev,
+pins are not configured from the driver\n);
+   }
+
pm_runtime_enable(pdev-dev);
pm_runtime_get_sync(pdev-dev);
data-clk = clk_get(pdev-dev, fck);
@@ -454,6 +490,11 @@ static int davinci_mdio_suspend(struct device *dev)
data-suspended = true;
spin_unlock(data-lock);
 
+   /* Optionally let pins go into sleep states */
+   if (!IS_ERR(data-pins_sleep))
+   if (pinctrl_select_state(data-pinctrl, data-pins_sleep))
+   dev_err(dev, could not set pins to sleep state\n);
+
return 0;
 }
 
@@ -465,6 +506,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(data-lock);
pm_runtime_get_sync(data-dev);
 
+   /* Optionaly enable pins to be muxed in and configured */
+   if (!IS_ERR(data-pins_default))
+   if (pinctrl_select_state(data-pinctrl, data-pins_default))
+   dev_err(dev, could not set default pins\n);
+
/* restart the scan state machine */
ctrl = __raw_readl(data-regs-control);
ctrl |= CONTROL_ENABLE;
-- 
1.7.9.5

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[net-next PATCH 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone

2013-05-03 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-bone.dts |   38 +
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts 
b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..60565f5 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17   /* gpmc_a8.gpio1_24, 
OUTPUT_PULLUP | MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x110 0x20  /* mii1_rxerr.mii1_rxerr, MODE0 
| INPUT */
+   0x114 0x0   /* mii1_txen.mii1_txen, MODE0 | 
OUTPUT */
+   0x118 0x20  /* mii1_rxdv.mii1_rxdv, MODE0 | 
INPUT_PULLDOWN */
+   0x11c 0x0   /* mii1_txd3.mii1_txd3, MODE0 | 
OUTPUT */
+   0x120 0x0   /* mii1_txd2.mii1_txd2, MODE0 | 
OUTPUT */
+   0x124 0x0   /* mii1_txd1.mii1_txd1, MODE0 | 
OUTPUT */
+   0x128 0x0   /* mii1_txd0.mii1_txd0, MODE0 | 
OUTPUT */
+   0x12c 0x20  /* mii1_txclk.mii1_txclk, MODE0 
| INPUT_PULLDOWN */
+   0x130 0x20  /* mii1_rxclk.mii1_rxclk, MODE0 
| INPUT_PULLDOWN */
+   0x134 0x20  /* mii1_rxd3.mii1_rxd3, MODE0 | 
INPUT_PULLDOWN */
+   0x138 0x20  /* mii1_rxd2.mii1_rxd2, MODE0 | 
INPUT_PULLDOWN */
+   0x13c 0x20  /* mii1_rxd1.mii1_rxd1, MODE0 | 
INPUT_PULLDOWN */
+   0x140 0x20  /* mii1_rxd0.mii1_rxd0, MODE0 | 
INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -136,3 +163,14 @@
 cpsw_emac1 {
phy_id = davinci_mdio, 1;
 };
+
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
-- 
1.7.9.5

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[net-next PATCH 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-05-03 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..f297b85 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net-next PATCH 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk

2013-05-03 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |   50 
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f297b85..d2c4b45 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27   /* gpmc_ben0_cle.gpio2_5, INPUT 
| MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* Slave 2 */
+   0x40 0x2/* gpmc_a0.rgmii2_tctl, MODE2 
| OUTPUT */
+   0x44 0x22   /* gpmc_a1.rgmii2_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x48 0x2/* gpmc_a2.rgmii2_td3, MODE2 | 
OUTPUT */
+   0x4c 0x2/* gpmc_a3.rgmii2_td2, MODE2 | 
OUTPUT */
+   0x50 0x2/* gpmc_a4.rgmii2_td1, MODE2 | 
OUTPUT */
+   0x54 0x2/* gpmc_a5.rgmii2_td0, MODE2 | 
OUTPUT */
+   0x58 0x2/* gpmc_a6.rgmii2_tclk, MODE2 
| OUTPUT */
+   0x5c 0x22   /* gpmc_a7.rgmii2_rclk, MODE2 
| INPUT_PULLDOWN */
+   0x60 0x22   /* gpmc_a8.rgmii2_rd3, MODE2 | 
INPUT_PULLDOWN */
+   0x64 0x22   /* gpmc_a9.rgmii2_rd2, MODE2 | 
INPUT_PULLDOWN */
+   0x68 0x22   /* gpmc_a10.rgmii2_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x6c 0x22   /* gpmc_a11.rgmii2_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -249,6 +289,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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[net-next PATCH 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

2013-05-03 Thread Mugunthan V N

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Todo:
- if an idle state is available for pins, add support for it.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evm.dts |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..e7f91e8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27  /* spi0_d0.gpio0_3, INPUT | 
MODE7 */
;
};
+
+   cpsw_default: cpsw_default {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+   ;
+   };
+
+   davinci_mdio_default: davinci_mdio_default {
+   pinctrl-single,pins = 
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
@@ -237,6 +263,16 @@
};
 };
 
+mac {
+   pinctrl-names = default;
+   pinctrl-0 = cpsw_default;
+};
+
+davinci_mdio {
+   pinctrl-names = default;
+   pinctrl-0 = davinci_mdio_default;
+};
+
 cpsw_emac0 {
phy_id = davinci_mdio, 0;
 };
-- 
1.7.9.5

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Re: [net-next PATCH 0/6] Adding pinctrl PM support for CPSW and Davinci MDIO drivers

2013-05-03 Thread Mugunthan V N


On 5/3/2013 1:12 PM, David Miller wrote:

Please read:

http://marc.info/?l=linux-netdevm=136730964130303w=2

Sorry, will resend the patch series one net is merged with net-next.

Regards
Mugunthan V N
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[net-next PATCH 1/1] drivers: net: cpsw: irq not disabled in cpsw isr in particular sequence

2013-05-02 Thread Mugunthan V N

In CPSW NAPI, after processing all interrupts IRQ is enabled and then book
keeping irq_enabled is updated. In random cases when a packet is transmitted
or received between processing packets and IRQ enabled, then just after
enabled IRQ and before irq_enabled is updated, ISR is called so IRQs are
not disabled as irq_enabled is still false and CPU gets locked in CPSW ISR.

By changing the sequence as update the irq_enabled and then enable IRQ
fixes the issue. This issue is not captured always as it is a timing issue
whether Tx or Rx IRQ is invoked between packet processing and enable IRQ.

Cc: Sebastian Siewior bige...@linutronix.de
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 59c4391..21a5b29 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -555,8 +555,8 @@ static int cpsw_poll(struct napi_struct *napi, int budget)
cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
prim_cpsw = cpsw_get_slave_priv(priv, 0);
if (prim_cpsw-irq_enabled == false) {
-   cpsw_enable_irq(priv);
prim_cpsw-irq_enabled = true;
+   cpsw_enable_irq(priv);
}
}
 
-- 
1.7.9.5

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[net-next PATCH v2 1/1] drivers: net: cpsw: fix kernel warn on cpsw irq enable

2013-04-30 Thread Mugunthan V N

With the commit a11fbba (net/cpsw: fix irq_disable() with threaded interrupts)
from Sebastian Siewior, a kernel warning is generated as below. This warning
is generated as the irq_enabled is not initialized for the primary interface
and in probe it is initialized for the second interface. This patch moves
irq_enabled initialization from second interface to primary interface.

[3.049173] net eth0: phy found : id is : 0x4dd074
[3.054552] net eth0: phy found : id is : 0x4dd074
[3.070421] [ cut here ]
[3.075308] WARNING: at kernel/irq/manage.c:437 enable_irq+0x3c/0x74()
[3.082173] Unbalanced enable for IRQ 56
[3.086299] Modules linked in:
[3.089557] [c001abcc] (unwind_backtrace+0x0/0xf0) from [c004294c] 
(warn_slowpath_common+0x4c/0x68)
[3.099450] [c004294c] (warn_slowpath_common+0x4c/0x68) from [c00429fc] 
(warn_slowpath_fmt+0x30/0x40)
[3.109521] [c00429fc] (warn_slowpath_fmt+0x30/0x40) from [c00a29fc] 
(enable_irq+0x3c/0x74)
[3.118681] [c00a29fc] (enable_irq+0x3c/0x74) from [c03a7818] 
(cpsw_ndo_open+0x61c/0x684)
[3.127669] [c03a7818] (cpsw_ndo_open+0x61c/0x684) from [c0445c08] 
(__dev_open+0x9c/0xf8)
[3.136646] [c0445c08] (__dev_open+0x9c/0xf8) from [c0445e34] 
(__dev_change_flags+0x78/0x13c)
[3.145988] [c0445e34] (__dev_change_flags+0x78/0x13c) from [c0445f64] 
(dev_change_flags+0x10/0x48)
[3.155884] [c0445f64] (dev_change_flags+0x10/0x48) from [c0736d88] 
(ip_auto_config+0x198/0x111c)
[3.165592] [c0736d88] (ip_auto_config+0x198/0x111c) from [c00086a4] 
(do_one_initcall+0x34/0x180)
[3.175309] [c00086a4] (do_one_initcall+0x34/0x180) from [c07078f8] 
(kernel_init_freeable+0xfc/0x1c8)
[3.185393] [c07078f8] (kernel_init_freeable+0xfc/0x1c8) from [c04f36ec] 
(kernel_init+0x8/0xe4)
[3.194929] [c04f36ec] (kernel_init+0x8/0xe4) from [c00133d0] 
(ret_from_fork+0x14/0x24)
[3.203712] ---[ end trace d6f979da080bc391 ]---

Cc: Sebastian Siewior bige...@linutronix.de
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
Changes from initial version:
* added previous commit summary
* changed secondary interface to second interface

 drivers/net/ethernet/ti/cpsw.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 4e2d224..59c4391 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1633,7 +1633,6 @@ static int cpsw_probe_dual_emac(struct platform_device 
*pdev,
priv_sl2-irqs_table[i] = priv-irqs_table[i];
priv_sl2-num_irqs = priv-num_irqs;
}
-   priv-irq_enabled = true;
ndev-features |= NETIF_F_HW_VLAN_CTAG_FILTER;
 
ndev-netdev_ops = cpsw_netdev_ops;
@@ -1679,6 +1678,7 @@ static int cpsw_probe(struct platform_device *pdev)
priv-msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
priv-rx_packet_max = max(rx_packet_max, 128);
priv-cpts = devm_kzalloc(pdev-dev, sizeof(struct cpts), GFP_KERNEL);
+   priv-irq_enabled = true;
if (!ndev) {
pr_err(error allocating cpts\n);
goto clean_ndev_ret;
-- 
1.7.9.5

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[net-next PATCH 1/1] drivers: net: cpsw: fix kernel warn on cpsw irq enable

2013-04-26 Thread Mugunthan V N

With the commit id a11fbba from Sebastian Siewior, a kernel warning is
generated as below. This warning is generated as the irq_enabled is not
initialized for the primary interface and in probe it is initialized for
the secondary interface. This patch moves irq_enabled initialization from
second interface to primary interface.

[3.049173] net eth0: phy found : id is : 0x4dd074
[3.054552] net eth0: phy found : id is : 0x4dd074
[3.070421] [ cut here ]
[3.075308] WARNING: at kernel/irq/manage.c:437 enable_irq+0x3c/0x74()
[3.082173] Unbalanced enable for IRQ 56
[3.086299] Modules linked in:
[3.089557] [c001abcc] (unwind_backtrace+0x0/0xf0) from [c004294c] 
(warn_slowpath_common+0x4c/0x68)
[3.099450] [c004294c] (warn_slowpath_common+0x4c/0x68) from [c00429fc] 
(warn_slowpath_fmt+0x30/0x40)
[3.109521] [c00429fc] (warn_slowpath_fmt+0x30/0x40) from [c00a29fc] 
(enable_irq+0x3c/0x74)
[3.118681] [c00a29fc] (enable_irq+0x3c/0x74) from [c03a7818] 
(cpsw_ndo_open+0x61c/0x684)
[3.127669] [c03a7818] (cpsw_ndo_open+0x61c/0x684) from [c0445c08] 
(__dev_open+0x9c/0xf8)
[3.136646] [c0445c08] (__dev_open+0x9c/0xf8) from [c0445e34] 
(__dev_change_flags+0x78/0x13c)
[3.145988] [c0445e34] (__dev_change_flags+0x78/0x13c) from [c0445f64] 
(dev_change_flags+0x10/0x48)
[3.155884] [c0445f64] (dev_change_flags+0x10/0x48) from [c0736d88] 
(ip_auto_config+0x198/0x111c)
[3.165592] [c0736d88] (ip_auto_config+0x198/0x111c) from [c00086a4] 
(do_one_initcall+0x34/0x180)
[3.175309] [c00086a4] (do_one_initcall+0x34/0x180) from [c07078f8] 
(kernel_init_freeable+0xfc/0x1c8)
[3.185393] [c07078f8] (kernel_init_freeable+0xfc/0x1c8) from [c04f36ec] 
(kernel_init+0x8/0xe4)
[3.194929] [c04f36ec] (kernel_init+0x8/0xe4) from [c00133d0] 
(ret_from_fork+0x14/0x24)
[3.203712] ---[ end trace d6f979da080bc391 ]---

Cc: Sebastian Siewior bige...@linutronix.de
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 4e2d224..59c4391 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1633,7 +1633,6 @@ static int cpsw_probe_dual_emac(struct platform_device 
*pdev,
priv_sl2-irqs_table[i] = priv-irqs_table[i];
priv_sl2-num_irqs = priv-num_irqs;
}
-   priv-irq_enabled = true;
ndev-features |= NETIF_F_HW_VLAN_CTAG_FILTER;
 
ndev-netdev_ops = cpsw_netdev_ops;
@@ -1679,6 +1678,7 @@ static int cpsw_probe(struct platform_device *pdev)
priv-msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
priv-rx_packet_max = max(rx_packet_max, 128);
priv-cpts = devm_kzalloc(pdev-dev, sizeof(struct cpts), GFP_KERNEL);
+   priv-irq_enabled = true;
if (!ndev) {
pr_err(error allocating cpts\n);
goto clean_ndev_ret;
-- 
1.7.9.5

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Re: [net-next PATCH 1/3] drivers: of: add phy fixup support in DT

2013-04-25 Thread Mugunthan V N

On 4/25/2013 1:26 PM, David Miller wrote:

From: Mugunthan V N mugunthan...@ti.com
Date: Mon, 22 Apr 2013 23:50:36 +0530

In earlier case phy fixup are added in board file as this is no more the case
so adding support for phy register fixup in Device Tree

Signed-off-by: Mugunthan V N mugunthan...@ti.com

When people put a series of undocumented PHY register writes using
constants, we tell them it's firmware.

If these PHY registers are actually documented in the driver, write a
function in that driver which does the programming sequence, then add
a property that the driver looks for in order to determine whether to
call that sequence or not.

I don't want people putting random PHY raw programming sequences and
other crap like that into the OF device nodes.  It's extremely
inelegant and inviting abuse.

Will modify the source as per your comments and will submit v2 patch set.

Regards
Mugunthan V N
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Re: [net-next PATCH 0/3] Adding phy register fixup in DT

2013-04-24 Thread Mugunthan V N


On 4/23/2013 1:32 PM, Sascha Hauer wrote:

On Mon, Apr 22, 2013 at 11:50:35PM +0530, Mugunthan V N wrote:

In earlier days phy fixup was added to phy frame work in board files.
As there won't be any board files here after the same has to be done in DT
This patch series adds the following features
* support for adding phy resigter fixup via DT
* adds phy id for EVMsk n DTS file
* adds phy fixup for AM335x EVM and EVMsk

Mugunthan V N (3):
   drivers: of: add phy fixup support in DT
   ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
   ARM: dts: AM33XX: add phy fixup for evm and evmsk boards

I generally do not offend to phy fixups from the devicetree. I see
though that becomes more and more common that we have to configure
the tx delays in phys.

The current way seems to be to hardcode register values for each board
which seems not very flexible and forces us to read phy datasheets
each time for a new board.

Wouldn't it make more sense to configure the actual delays (in ns) and
let the phy drivers figure out how to turn this into register values?

Not that I volunteer to write such things... :-/


There is no calculation done for enabling RGMII Tx internal delay. Its all
pre-calculated in Hardware (Either in Phy or EMAC)
In this patch as CPSW IP in AM335x doesn't support internal delay inside
SoC, so enabling the same in Phy and it is just a bit set in the phy debug
registers

Regards
Mugunthan V N
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Re: [PATCH] remove vlan tags in CPSW dual emac mode

2013-04-23 Thread Mugunthan V N


On 4/23/2013 9:48 PM, Markus Brunner wrote:

If operating in dual emac mode all packets sent by the CPSW contain vlan 
headers with the reserved VID 0,
which gets stripped away by all somewhat recent Linux versions. Operating 
systems without that behaviour will fail to communicate.
This patch fixes that behaviour by disabling the VLAN_AWARE mode as already 
described by the comment above.

Signed-off-by: Markus Brunner systemprogrammierung.brun...@gmail.com
Tested-by: Mark Jackson m...@newflow.co.uk

---
--- linux-3.9-rc8.orig/drivers/net/ethernet/ti/cpsw.c   2013-04-23 
17:26:11.0 +0200
+++ linux-3.9-rc8/drivers/net/ethernet/ti/cpsw.c2013-04-23 
17:36:25.0 +0200
@@ -751,9 +751,9 @@ static void cpsw_init_host_port(struct c
/* switch to vlan unaware mode */
cpsw_ale_control_set(priv-ale, priv-host_port, ALE_VLAN_AWARE,
 CPSW_ALE_VLAN_AWARE);
control_reg = readl(priv-regs-control);
-   control_reg |= CPSW_VLAN_AWARE;
+   control_reg = ~CPSW_VLAN_AWARE;
writel(control_reg, priv-regs-control);
fifo_mode = (priv-data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
 CPSW_FIFO_NORMAL_MODE;
writel(fifo_mode, priv-host_port_regs-tx_in_ctl);

Disabling VLAN aware mode will enable switching mode and the feature of
separating the two down stream port is lost with this patch
Please check TRM for more info in *14.3.2.10.2 Dual Mac Mode* chapter

Regards
Mugunthan V N
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Re: [PATCH 0/3] Dual EMAC mode implementation of CPSW

2013-04-22 Thread Mugunthan V N


On 4/22/2013 7:37 PM, Mark Jackson wrote:

Mugunthan

Can you confirm that I'm actually trying to achieve the right thing ?

I have all along assumed that Dual EMAC mode would simply provide the
kernel will a pair of independent Ethernet ports.

Yes, it will provide two network interfaces for ex eth0 and eth1

All I am trying to do is to get both Ethernet ports working so I can
have one port on (say) 10.0.x.x and the other on (say) 10.1.x.x

This is perfectly correct

But there is all this reference to VLANs(in the source code and the TRM)
... I have not setup any VLANs.  Do I need to ?  If so, how ?

No need to setup any VLAN. VLAN are used to segregate the
two down stream ports and it will be taken care by the driver

Regards
Mugunthan V N
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[net-next PATCH 0/3] Adding phy register fixup in DT

2013-04-22 Thread Mugunthan V N

In earlier days phy fixup was added to phy frame work in board files.
As there won't be any board files here after the same has to be done in DT
This patch series adds the following features
* support for adding phy resigter fixup via DT
* adds phy id for EVMsk n DTS file
* adds phy fixup for AM335x EVM and EVMsk

Mugunthan V N (3):
  drivers: of: add phy fixup support in DT
  ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
  ARM: dts: AM33XX: add phy fixup for evm and evmsk boards

 .../devicetree/bindings/net/phy-fixup.txt  |   26 ++
 arch/arm/boot/dts/am335x-evm.dts   |   10 +++
 arch/arm/boot/dts/am335x-evmsk.dts |   18 
 drivers/of/of_net.c|   92 
 include/linux/of_net.h |6 ++
 5 files changed, 152 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/phy-fixup.txt

-- 
1.7.9.5

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[net-next PATCH 1/3] drivers: of: add phy fixup support in DT

2013-04-22 Thread Mugunthan V N

In earlier case phy fixup are added in board file as this is no more the case
so adding support for phy register fixup in Device Tree

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 .../devicetree/bindings/net/phy-fixup.txt  |   26 ++
 drivers/of/of_net.c|   92 
 include/linux/of_net.h |6 ++
 3 files changed, 124 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/phy-fixup.txt

diff --git a/Documentation/devicetree/bindings/net/phy-fixup.txt 
b/Documentation/devicetree/bindings/net/phy-fixup.txt
new file mode 100644
index 000..460f76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/phy-fixup.txt
@@ -0,0 +1,26 @@
+Ethernet Phy fixup Device Tree Bindings
+---
+
+The following DT fields can be added to MDIO DT notes and can be used to
+add phy fix up needed
+
+Required properties:
+- phy-fixup-registers  : Will contain a array of register fix nodes which has
+ the following node parameters
+- phy-id   : Specifies the phy id for which the fix belongs to
+- phy-mask : Specifies the phy mask for which the fix belongs to
+- fixup-registers  : Specifies the fix up registers and values in array
+ of offset value pair
+Optional properties:
+
+Examples:
+
+davinci_mdio {
+   phy-fixup-registers = atheros_txclk_delay_fixup;
+
+   atheros_txclk_delay_fixup: atheros_txclk_delay_fixup {
+   phy-id = 0x4dd074;
+   phy-mask = 0xfffe;
+   fixup-registers = 0x1d 0x5 0x1e 0x100;
+   };
+};
diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
index ffab033..50ad671 100644
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -10,6 +10,7 @@
 #include linux/of_net.h
 #include linux/phy.h
 #include linux/export.h
+#include linux/of_net.h
 
 /**
  * It maps 'enum phy_interface_t' found in include/linux/phy.h
@@ -92,3 +93,94 @@ const void *of_get_mac_address(struct device_node *np)
return NULL;
 }
 EXPORT_SYMBOL(of_get_mac_address);
+
+static int __of_phy_fixup_cb(struct phy_device *phydev)
+{
+   struct device_node *node = phydev-bus-parent-of_node;
+   struct device_node *phy_fixup_node;
+   const __be32 *parp;
+   int lenp;
+   int i, j;
+
+   parp = of_get_property(node, phy-fixup-registers, lenp);
+   if (parp == NULL)
+   return 0;
+   lenp /= sizeof(void *);
+
+   for (i = 0; i  lenp; i++) {
+   u32 phy_id;
+   const __be32 *fixups;
+   int fixup_len;
+
+   phy_fixup_node = of_find_node_by_phandle(be32_to_cpup(parp+i));
+   if (of_property_read_u32(phy_fixup_node, phy-id, phy_id)) {
+   pr_err(Missing PHY id in Phy fixup\n);
+   return -EINVAL;
+   }
+   if (phy_id != phydev-phy_id)
+   continue;
+
+   fixups = of_get_property(phy_fixup_node, fixup-registers,
+fixup_len);
+   if (fixups == NULL) {
+   pr_err(Missing fixup registers in Phy fixup\n);
+   return -EINVAL;
+   }
+   fixup_len /= sizeof(void *);
+   for (j = 0; j  fixup_len; j += 2) {
+   u16 regnum = be32_to_cpup(fixups + j);
+   u16 val = be32_to_cpup(fixups + j + 1);
+   phy_write(phydev, regnum, val);
+   }
+   }
+
+   return 0;
+}
+
+int of_add_phy_fixup_register(struct device_node *node)
+{
+   struct device_node *phy_fixup_node;
+   const __be32 *parp;
+   int lenp;
+   int i;
+
+   parp = of_get_property(node, phy-fixup-registers, lenp);
+   if (parp == NULL)
+   return 0;
+   lenp /= sizeof(void *);
+
+   for (i = 0; i  lenp; i++) {
+   u32 phy_id;
+   u32 phy_mask;
+   const __be32 *fixups;
+   int fixup_len;
+
+   phy_fixup_node = of_find_node_by_phandle(be32_to_cpup(parp+i));
+   if (of_property_read_u32(phy_fixup_node, phy-id, phy_id)) {
+   pr_err(Missing PHY id in Phy fixup\n);
+   continue;
+   }
+
+   if (of_property_read_u32(phy_fixup_node, phy-mask,
+phy_mask)) {
+   pr_err(Missing PHY mask in Phy fixup\n);
+   continue;
+   }
+
+   fixups = of_get_property(phy_fixup_node, fixup-registers,
+fixup_len);
+   if (fixups == NULL) {
+   pr_err(Missing fixup registers in Phy fixup\n);
+   continue;
+   }
+   fixup_len /= sizeof(void

[net-next PATCH 2/3] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-04-22 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..f297b85 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net-next PATCH 3/3] ARM: dts: AM33XX: add phy fixup for evm and evmsk boards

2013-04-22 Thread Mugunthan V N

As RGMII tx clock internal delay is not supported in AM335x, the same has
to be enabled in phy. This patch adds support for enabling tx clock internal
delay via phy debug registers

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evm.dts   |   10 ++
 arch/arm/boot/dts/am335x-evmsk.dts |   10 ++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..72805c5 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -244,3 +244,13 @@
 cpsw_emac1 {
phy_id = davinci_mdio, 1;
 };
+
+davinci_mdio {
+   phy-fixup-registers = atheros_txclk_delay_fixup;
+
+   atheros_txclk_delay_fixup: atheros_txclk_delay_fixup {
+   phy-id = 0x4dd074;
+   phy-mask = 0xfffe;
+   fixup-registers = 0x1d 0x5 0x1e 0x100;
+   };
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f297b85..f398cb3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -256,3 +256,13 @@
 cpsw_emac1 {
phy_id = davinci_mdio, 1;
 };
+
+davinci_mdio {
+   phy-fixup-registers = atheros_txclk_delay_fixup;
+
+   atheros_txclk_delay_fixup: atheros_txclk_delay_fixup {
+   phy-id = 0x4dd074;
+   phy-mask = 0xfffe;
+   fixup-registers = 0x1d 0x5 0x1e 0x100;
+   };
+};
-- 
1.7.9.5

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Re: [PATCH 3/3] driver: net: ethernet: cpsw: dual emac interface implementation

2013-04-15 Thread Mugunthan V N


On 4/15/2013 12:50 AM, Mark Jackson wrote:

On 11/02/13 19:52, Mugunthan V N wrote:

The CPSW switch can act as Dual EMAC by segregating the switch ports
using VLAN and port VLAN as per the TRM description in
14.3.2.10.2 Dual Mac Mode

Following CPSW components will be common for both the interfaces.
* Interrupt source is common for both eth interfaces
* Interrupt pacing is common for both interfaces
* Hardware statistics is common for all the ports
* CPDMA is common for both eth interface
* CPTS is common for both the interface and it should not be enabled on
   both the interface as timestamping information doesn't contain port
   information.

Constrains
* Reserved VID of One port should not be used in other interface 
which will

   enable switching functionality
* Same VID must not be used in both the interface which will enable 
switching

   functionality

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---


@@ -1237,6 +1372,18 @@ static int cpsw_probe_dt(struct 
cpsw_platform_data *data,

  if (mac_addr)
  memcpy(slave_data-mac_addr, mac_addr, ETH_ALEN);

+if (data-dual_emac) {
+if (of_property_read_u32(node, dual_emac_res_vlan,
+ prop)) {


Shouldn't this be:-

if (of_property_read_u32(slave_node, dual_emac_res_vlan,
 ^^

... so we pick each VLAN id from the individual slaves ?


Good catch, will send a fixup patch for this.

Regards
Mugunthan V N
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Re: [PATCH 0/3] Dual EMAC mode implementation of CPSW

2013-04-15 Thread Mugunthan V N


On 4/15/2013 12:46 AM, Mark Jackson wrote:

On 11/02/13 19:52, Mugunthan V N wrote:

This patch series implements Dual EMAC mode implementation of CPSW
which acts as two standalone EMAC by segregating the switch using VIDs
and port VLAN

Mugunthan V N (3):
   driver: net: ethernet: davinci_cpdma: add support for directed packet
 and source port detection
   driver: net: ethernet: cpsw: make cpts as pointer
   driver: net: ethernet: cpsw: dual emac interface implementation

  Documentation/devicetree/bindings/net/cpsw.txt |2 +
  drivers/net/ethernet/ti/cpsw.c |  387 
+++-

  drivers/net/ethernet/ti/davinci_cpdma.c|   17 +-
  drivers/net/ethernet/ti/davinci_cpdma.h|4 +-
  drivers/net/ethernet/ti/davinci_emac.c |6 +-
  include/linux/platform_data/cpsw.h |3 +
  6 files changed, 338 insertions(+), 81 deletions(-)


I'm trying to get dual emac mode working, but I'm only having partial 
success.  We have a custom AM335x board with dual LAN8710 PYHs, but 
the basic design is based on the BeagleBone board.


I have the following in my .dts file:-

mac: ethernet@4a10 {
dual_emac = 1;
cpsw_emac0: slave@4a100200 {
dual_emac_res_vlan = 1;
};
cpsw_emac1: slave@4a100300 {
dual_emac_res_vlan = 2;
};
};

When I boot my board (across nfs via eth1):-

(a) the kernel is loaded (via tftp under U-Boot)
(b) the kernel mounts the nfsroot
(c) my init scripts are run (e.g. dropbear)
(d) the shell prompt appears

So far so good, but when I then try any shell command (e.g. ps) the 
nfs link just hangs.


Below is an extract from the boot messages:-

[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 3.9.0-rc6-00186-g5b55d70-dirty 
(mpfj@mpfj-nanobone) (gcc version 4.7.2 (Buildroot 
2013.02-00154-g851ceaa) ) #19 Sun Apr 14 19:50:21 BST 2013
[0.00] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), 
cr=10c53c7d
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing 
instruction cache
[0.00] Machine: Generic AM33XX (Flattened Device Tree), model: 
Newflow AM335x NanoBone

[0.00] Memory policy: ECC disabled, Data cache writeback
[0.00] CPU: All CPU(s) started in SVC mode.
[0.00] AM335X ES1.0 (neon )
[0.00] Built 1 zonelists in Zone order, mobility grouping on. 
Total pages: 64768
[0.00] Kernel command line: root=/dev/nfs 
nfsroot=10.1.0.111:/tftpboot/nanobone/rootfs rw 
ip=10.1.0.199:10.1.0.111:10.1.0.1:255.255.0.0::eth1:off 
console=ttyO0,115200

...
[1.424977] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[1.431443] davinci_mdio 4a101000.mdio: detected phy mask fffc
[1.440939] libphy: 4a101000.mdio: probed
[1.445266] davinci_mdio 4a101000.mdio: phy[0]: device 
4a101000.mdio:00, driver SMSC LAN8710/LAN8720
[1.454962] davinci_mdio 4a101000.mdio: phy[1]: device 
4a101000.mdio:01, driver SMSC LAN8710/LAN8720

[1.465059] Random MACID = a2:3f:fb:2c:47:d9
[1.472276] cpsw: Random MACID = ae:d5:c0:c0:27:03
[1.480588] rtc-ds1307 0-0068: setting system clock to 2013-04-14 
19:59:52 UTC (1365969592)

[1.491543] net eth1: initializing cpsw version 1.12 (0)
[1.516965] net eth1: phy found : id is : 0x7c0f1
[4.595479] libphy: 4a101000.mdio:01 - Link is Up - 100/Full
[4.625872] IP-Config: Complete:
[4.629307]  device=eth1, hwaddr=ae:d5:c0:c0:27:03, 
ipaddr=10.1.0.199, mask=255.255.0.0, gw=10.1.0.1

[4.639365]  host=10.1.0.199, domain=, nis-domain=(none)
[4.645359]  bootserver=10.1.0.111, rootserver=10.1.0.111, 
rootpath=

[4.674219] VFS: Mounted root (nfs filesystem) on device 0:12.
[4.682438] devtmpfs: mounted
[4.686042] Freeing init memory: 196K
Starting logging: OK
Initializing random number generator... done.
Starting network...
ip: RTNETLINK answers: File exists
[5.340677] net eth0: initializing cpsw version 1.12 (0)
[5.366463] net eth0: phy found : id is : 0x7c0f1
ip: RTNETLINK answers: File exists
ip: RTNETLINK answers: File exists
ip: RTNETLINK answers: File exists
Starting dropbear sshd: OK

Welcome to Buildroot
nanobone login: root
Password:
# ps
[   18.845266] nfs: server 10.1.0.111 not responding, still trying

At this point, I can disconnect my network cable from eth1 and connect 
to eth0, and back again which shows the PYHs appear to be detecting 
the link up/down status of each port.


[  562.675229] libphy: 4a101000.mdio:01 - Link is Down
[  567.885586] libphy: 4a101000.mdio:00 - Link is Up - 100/Full
[  571.965156] libphy: 4a101000.mdio:00 - Link is Down
[  575.014943] nfs: server 10.1.0.111 not responding, still trying
[  576.635412] libphy: 4a101000.mdio:01 - Link is Up - 100/Full
[  579.426051] nfs: server 10.1.0.111 OK

Notice that at the end, the nfs link appears to come back ok, but 
the ps command never completes.


Any ideas of what's going on ?


I have tried ping on both the interface fine

[net PATCH 1/1] drivers: net: ethernet: cpsw: get slave VLAN id from slave node instead of cpsw node

2013-04-15 Thread Mugunthan V N

Dual EMAC slave VLAN id must be got from slave node instead of cpsw node as
VLAN id for each slave will be different.

Reported-by: Mark Jackson mpfj-l...@mimc.co.uk
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 80cad06..4781d3d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1380,7 +1380,7 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
memcpy(slave_data-mac_addr, mac_addr, ETH_ALEN);
 
if (data-dual_emac) {
-   if (of_property_read_u32(node, dual_emac_res_vlan,
+   if (of_property_read_u32(slave_node, 
dual_emac_res_vlan,
 prop)) {
pr_err(Missing dual_emac_res_vlan in DT.\n);
slave_data-dual_emac_res_vlan = i+1;
-- 
1.7.9.5

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Re: [PATCH 0/3] Dual EMAC mode implementation of CPSW

2013-04-15 Thread Mugunthan V N


On 4/15/2013 10:58 PM, Mark Jackson wrote:

On 15/04/13 18:07, Mugunthan V N wrote:

On 4/15/2013 12:46 AM, Mark Jackson wrote:


snip



Notice that at the end, the nfs link appears to come back ok, but
the ps command never completes.

Any ideas of what's going on ?


I have tried ping on both the interface fine. Will verify with ps again
later in this week.
Can you provide below details details
- Are you using EVMsk or custom build EVM?


This is a custom board (based on the BeagleBone design) with dual 
Ethernet, NAND, NOR and FRAM.


The dual emac thing is (one of) the last things to get signed off, so 
I'm willing to assist in tracking this down.


After testing the scenario i may be able to send you an update later in 
this week.


Regards
Mugunthan V N
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Re: AM3517 DaVinci EMAC Ethernet performance issues

2013-04-04 Thread Mugunthan V N


On 4/4/2013 7:50 AM, CF Adad wrote:
We've done network captures on our link, and the problem is very 
strange. The iperf client transmits data quickly and steadily for a 
while, but then all the sudden just stops. In the captures you can see 
an ACK come back from the server for the frame that was just sent, but 
then instead of immediately sending the next one it just sits there 
for sometimes several seconds. Then, it suddenly picks back up and 
starts running again. It's as though it just paused due to lack of data. 

The same kind of issue was observed in different SoC with Davinci EMAC
and resolved by the patch below. Can you make sure the patch is applied
in your kernel and take the performance again.
https://git.kernel.org/cgit/linux/kernel/git/davem/net.git/commit/?id=7e51cde276ca820d526c6c21cf8147df595a36bf

Regards
Mugunthan V N
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[net-next PATCH 1/1] drivers: net: ethernet: ti: sparse warning fix for ti ethernet drivers

2013-03-27 Thread Mugunthan V N

fix for the below sparse warnings

drivers/net/ethernet/ti/davinci_cpdma.c:182:29: warning: incorrect type in 
assignment (different address spaces)
drivers/net/ethernet/ti/davinci_cpdma.c:182:29:expected void [noderef] 
asn:2*iomap
drivers/net/ethernet/ti/davinci_cpdma.c:182:29:got void *cpumap
drivers/net/ethernet/ti/davinci_cpdma.c:953:27: warning: symbol 'controls' was 
not declared. Should it be static?
drivers/net/ethernet/ti/cpsw.c:451:6: warning: symbol 'cpsw_tx_handler' was not 
declared. Should it be static?
drivers/net/ethernet/ti/cpsw.c:468:6: warning: symbol 'cpsw_rx_handler' was not 
declared. Should it be static?
drivers/net/ethernet/ti/cpsw_ale.c:151:5: warning: symbol 'cpsw_ale_match_addr' 
was not declared. Should it be static?
drivers/net/ethernet/ti/cpsw_ale.c:172:5: warning: symbol 'cpsw_ale_match_vlan' 
was not declared. Should it be static?

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c  |4 ++--
 drivers/net/ethernet/ti/cpsw_ale.c  |4 ++--
 drivers/net/ethernet/ti/davinci_cpdma.c |4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 7aebc0c..f4be85b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -448,7 +448,7 @@ static void cpsw_intr_disable(struct cpsw_priv *priv)
return;
 }
 
-void cpsw_tx_handler(void *token, int len, int status)
+static void cpsw_tx_handler(void *token, int len, int status)
 {
struct sk_buff  *skb = token;
struct net_device   *ndev = skb-dev;
@@ -465,7 +465,7 @@ void cpsw_tx_handler(void *token, int len, int status)
dev_kfree_skb_any(skb);
 }
 
-void cpsw_rx_handler(void *token, int len, int status)
+static void cpsw_rx_handler(void *token, int len, int status)
 {
struct sk_buff  *skb = token;
struct net_device   *ndev = skb-dev;
diff --git a/drivers/net/ethernet/ti/cpsw_ale.c 
b/drivers/net/ethernet/ti/cpsw_ale.c
index 7fa60d6..79f0b79 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c
@@ -148,7 +148,7 @@ static int cpsw_ale_write(struct cpsw_ale *ale, int idx, 
u32 *ale_entry)
return idx;
 }
 
-int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr, u16 vid)
+static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr, u16 vid)
 {
u32 ale_entry[ALE_ENTRY_WORDS];
int type, idx;
@@ -169,7 +169,7 @@ int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr, u16 
vid)
return -ENOENT;
 }
 
-int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
+static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
 {
u32 ale_entry[ALE_ENTRY_WORDS];
int type, idx;
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c 
b/drivers/net/ethernet/ti/davinci_cpdma.c
index ee13dc7..a6f5de9 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -179,7 +179,7 @@ cpdma_desc_pool_create(struct device *dev, u32 phys, u32 
hw_addr,
} else {
pool-cpumap = dma_alloc_coherent(dev, size, pool-phys,
  GFP_KERNEL);
-   pool-iomap = pool-cpumap;
+   pool-iomap = (void __iomem *) pool-cpumap;
pool-hw_addr = pool-phys;
}
 
@@ -950,7 +950,7 @@ struct cpdma_control_info {
 #define ACCESS_RW  (ACCESS_RO | ACCESS_WO)
 };
 
-struct cpdma_control_info controls[] = {
+static struct cpdma_control_info controls[] = {
[CPDMA_CMD_IDLE]  = {CPDMA_DMACONTROL,  3,  1,  ACCESS_WO},
[CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL,  4,  1,  ACCESS_RW},
[CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL,  2,  1,  ACCESS_RW},
-- 
1.7.9.5

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[net-next PATCH 0/2] network performance improvement patches for TI CPSW and Davinci EMAC drivers

2013-03-27 Thread Mugunthan V N

This patch series improves network performance of TI CPSW and Davinci EMAC
drivers during bulk transfer. During heavy Tx load CPDMA may run out of
descriptors and tx queue is stopped. When it descriptors are available it
is reported to the stack via netif_start_queue which doesn't schedule tx
queue immediately, so there can be dead time during continuous transfer,
this can be fixed by using netif_wake_queue api which will schedule tx queue
immediately.

Mugunthan V N (2):
  drivers: net: ethernet: cpsw: use netif_wake_queue() while restarting
tx queue
  drivers: net: ethernet: davinci_emac: use netif_wake_queue() while
restarting tx queue

 drivers/net/ethernet/ti/cpsw.c |2 +-
 drivers/net/ethernet/ti/davinci_emac.c |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[net-next PATCH 1/2] drivers: net: ethernet: cpsw: use netif_wake_queue() while restarting tx queue

2013-03-27 Thread Mugunthan V N

To restart tx queue use netif_wake_queue() intead of netif_start_queue()
so that net schedule will restart transmission immediately which will
increase network performance while doing huge data transfers.

Reported-by: Dan Franke dan.fra...@schneider-electric.com
Suggested-by: Sriramakrishnan A G s...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index f4be85b..61ecebf 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -458,7 +458,7 @@ static void cpsw_tx_handler(void *token, int len, int 
status)
 * queue is stopped then start the queue as we have free desc for tx
 */
if (unlikely(netif_queue_stopped(ndev)))
-   netif_start_queue(ndev);
+   netif_wake_queue(ndev);
cpts_tx_timestamp(priv-cpts, skb);
priv-stats.tx_packets++;
priv-stats.tx_bytes += len;
-- 
1.7.9.5

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[net-next PATCH 2/2] drivers: net: ethernet: davinci_emac: use netif_wake_queue() while restarting tx queue

2013-03-27 Thread Mugunthan V N

To restart tx queue use netif_wake_queue() intead of netif_start_queue()
so that net schedule will restart transmission immediately which will
increase network performance while doing huge data transfers.

Reported-by: Dan Franke dan.fra...@schneider-electric.com
Suggested-by: Sriramakrishnan A G s...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_emac.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/davinci_emac.c 
b/drivers/net/ethernet/ti/davinci_emac.c
index 8121a3d..6a0b477 100644
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -1053,7 +1053,7 @@ static void emac_tx_handler(void *token, int len, int 
status)
 * queue is stopped then start the queue as we have free desc for tx
 */
if (unlikely(netif_queue_stopped(ndev)))
-   netif_start_queue(ndev);
+   netif_wake_queue(ndev);
ndev-stats.tx_packets++;
ndev-stats.tx_bytes += len;
dev_kfree_skb_any(skb);
-- 
1.7.9.5

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[PATCH 1/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone

2013-03-25 Thread Mugunthan V N

Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-bone.dts |   25 -
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts 
b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..f90e665 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
 
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
-   pinctrl-0 = user_leds_s0;
+   pinctrl-0 = user_leds_s0 cpsw_s0;
 
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = 
@@ -36,6 +36,29 @@
0x60 0x17   /* gpmc_a8.gpio1_24, 
OUTPUT_PULLUP | MODE7 */
;
};
+
+   cpsw_s0: cpsw_s0 {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x110 0x20  /* mii1_rxerr.mii1_rxerr, MODE0 
| INPUT */
+   0x114 0x0   /* mii1_txen.mii1_txen, MODE0 | 
OUTPUT */
+   0x118 0x20  /* mii1_rxdv.mii1_rxdv, MODE0 | 
INPUT_PULLDOWN */
+   0x11c 0x0   /* mii1_txd3.mii1_txd3, MODE0 | 
OUTPUT */
+   0x120 0x0   /* mii1_txd2.mii1_txd2, MODE0 | 
OUTPUT */
+   0x124 0x0   /* mii1_txd1.mii1_txd1, MODE0 | 
OUTPUT */
+   0x128 0x0   /* mii1_txd0.mii1_txd0, MODE0 | 
OUTPUT */
+   0x12c 0x20  /* mii1_txclk.mii1_txclk, MODE0 
| INPUT_PULLDOWN */
+   0x130 0x20  /* mii1_rxclk.mii1_rxclk, MODE0 
| INPUT_PULLDOWN */
+   0x134 0x20  /* mii1_rxd3.mii1_rxd3, MODE0 | 
INPUT_PULLDOWN */
+   0x138 0x20  /* mii1_rxd2.mii1_rxd2, MODE0 | 
INPUT_PULLDOWN */
+   0x13c 0x20  /* mii1_rxd1.mii1_rxd1, MODE0 | 
INPUT_PULLDOWN */
+   0x140 0x20  /* mii1_rxd0.mii1_rxd0, MODE0 | 
INPUT_PULLDOWN */
+
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
-- 
1.7.9.5

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[PATCH 2/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk

2013-03-25 Thread Mugunthan V N

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evmsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |   38 +++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f297b85..9b29ad4 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
 
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
-   pinctrl-0 = user_leds_s0 gpio_keys_s0;
+   pinctrl-0 = user_leds_s0 gpio_keys_s0 cpsw_s0;
 
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = 
@@ -51,6 +51,42 @@
0x9c 0x27   /* gpmc_ben0_cle.gpio2_5, INPUT 
| MODE7 */
;
};
+
+   cpsw_s0: cpsw_s0 {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* Slave 2 */
+   0x40 0x2/* gpmc_a0.rgmii2_tctl, MODE2 
| OUTPUT */
+   0x44 0x22   /* gpmc_a1.rgmii2_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x48 0x2/* gpmc_a2.rgmii2_td3, MODE2 | 
OUTPUT */
+   0x4c 0x2/* gpmc_a3.rgmii2_td2, MODE2 | 
OUTPUT */
+   0x50 0x2/* gpmc_a4.rgmii2_td1, MODE2 | 
OUTPUT */
+   0x54 0x2/* gpmc_a5.rgmii2_td0, MODE2 | 
OUTPUT */
+   0x58 0x2/* gpmc_a6.rgmii2_tclk, MODE2 
| OUTPUT */
+   0x5c 0x22   /* gpmc_a7.rgmii2_rclk, MODE2 
| INPUT_PULLDOWN */
+   0x60 0x22   /* gpmc_a8.rgmii2_rd3, MODE2 | 
INPUT_PULLDOWN */
+   0x64 0x22   /* gpmc_a9.rgmii2_rd2, MODE2 | 
INPUT_PULLDOWN */
+   0x68 0x22   /* gpmc_a10.rgmii2_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x6c 0x22   /* gpmc_a11.rgmii2_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
-- 
1.7.9.5

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[PATCH 0/3] add pin-mux configuration for AM33xx CPSW

2013-03-25 Thread Mugunthan V N

Adding pinmux configuration to AM33xx board dts file.

Mugunthan V N (3):
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

 arch/arm/boot/dts/am335x-bone.dts  |   25 +++-
 arch/arm/boot/dts/am335x-evm.dts   |   24 ++-
 arch/arm/boot/dts/am335x-evmsk.dts |   38 +++-
 3 files changed, 84 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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[PATCH 3/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM

2013-03-25 Thread Mugunthan V N

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evm.dts |   24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..9327d7d 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,7 @@
 
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = default;
-   pinctrl-0 = matrix_keypad_s0 volume_keys_s0;
+   pinctrl-0 = matrix_keypad_s0 volume_keys_s0 cpsw_s0;
 
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins = 
@@ -44,6 +44,28 @@
0x154 0x27  /* spi0_d0.gpio0_3, INPUT | 
MODE7 */
;
};
+
+   cpsw_s0: cpsw_s0 {
+   pinctrl-single,pins = 
+   /* Slave 1 */
+   0x114 0x2   /* mii1_txen.rgmii1_tctl, MODE2 
| OUTPUT */
+   0x118 0x22  /* mii1_rxdv.rgmii1_rctl, MODE2 
| INPUT_PULLDOWN */
+   0x11c 0x2   /* mii1_txd3.rgmii1_td3, MODE2 
| OUTPUT */
+   0x120 0x2   /* mii1_txd2.rgmii1_td2, MODE2 
| OUTPUT */
+   0x124 0x2   /* mii1_txd1.rgmii1_td1, MODE2 
| OUTPUT */
+   0x128 0x2   /* mii1_txd0.rgmii1_td0, MODE2 
| OUTPUT */
+   0x12c 0x2   /* mii1_txclk.rgmii1_tclk, 
MODE2 | OUTPUT */
+   0x130 0x22  /* mii1_rxclk.rgmii1_rclk, 
MODE2 | INPUT_PULLDOWN */
+   0x134 0x22  /* mii1_rxd3.rgmii1_rd3, MODE2 
| INPUT_PULLDOWN */
+   0x138 0x22  /* mii1_rxd2.rgmii1_rd2, MODE2 
| INPUT_PULLDOWN */
+   0x13c 0x22  /* mii1_rxd1.rgmii1_rd1, MODE2 
| INPUT_PULLDOWN */
+   0x140 0x22  /* mii1_rxd0.rgmii1_rd0, MODE2 
| INPUT_PULLDOWN */
+
+   /* MDIO */
+   0x148 0x30  /* mdio_data.mdio_data, MODE0 | 
INPUT_PULLUP */
+   0x14c 0x10  /* mdio_clk.mdio_clk, MODE0 | 
OUTPUT_PULLUP */
+   ;
+   };
};
 
ocp {
-- 
1.7.9.5

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[RESEND PATCH 1/1] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-03-20 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[net PATCH 1/1] drivers: net: ethernet: ti: davinci_emac: fix usage of cpdma_check_free_tx_desc()

2013-03-15 Thread Mugunthan V N

Fix which was done in the following commit in cpsw driver has
to be taken forward to davinci emac driver as well.

commit d35162f89b8f00537d7b240b76d2d0e8b8d29aa0
Author: Daniel Mack zon...@gmail.com
Date:   Tue Mar 12 06:31:19 2013 +

net: ethernet: cpsw: fix usage of cpdma_check_free_tx_desc()

Commit fae50823d0 (net: ethernet: davinci_cpdma: Add boundary for rx
and tx descriptors) introduced a function to check the current
allocation state of tx packets. The return value is taken into account
to stop the netqork queue on the adapter in case there are no free
slots.

However, cpdma_check_free_tx_desc() returns 'true' if there is room in
the bitmap, not 'false', so the usage of the function is wrong.

Reported-by: Prabhakar Lad prabhakar.cse...@gmail.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/davinci_emac.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/davinci_emac.c 
b/drivers/net/ethernet/ti/davinci_emac.c
index 52c0536..ae1b77a 100644
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -1102,7 +1102,7 @@ static int emac_dev_xmit(struct sk_buff *skb, struct 
net_device *ndev)
/* If there is no more tx desc left free then we need to
 * tell the kernel to stop sending us tx frames.
 */
-   if (unlikely(cpdma_check_free_tx_desc(priv-txchan)))
+   if (unlikely(!cpdma_check_free_tx_desc(priv-txchan)))
netif_stop_queue(ndev);
 
return NETDEV_TX_OK;
-- 
1.7.9.5

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Re: [PATCH v3 net-next 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-03-14 Thread Mugunthan V N


On 3/13/2013 3:04 PM, Mark Jackson wrote:

On 18/02/13 08:19, Mugunthan V N wrote:

CPDMA interrupts are not properly acknowledged which leads to interrupt
storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
used for rx and tx respectively.

Reported-by: Pantelis Antonioupa...@antoniou-consulting.com
Signed-off-by: Mugunthan V Nmugunthan...@ti.com

Not sure if I'm seeing this same problem [1], but it doesn't appear fixed to me.

I've tried both mainline -rc2 and -next.

[1]https://lkml.org/lkml/2013/3/12/376

Without this patch, PG2.0 was not usable as CPSW interrupt was never acked
and CPU spent most of the time in CPSW ISR.

I have checked -rc2 and it is working fine.

Regards
Mugunthan V N
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[PATCH v2 4/5] driver: net: ethernet: cpsw: implement interrupt pacing via ethtool

2013-03-12 Thread Mugunthan V N

This patch implements support for interrupt pacing block of CPSW via ethtool
Inetrrupt pacing block is common of both the ethernet interface in
dual emac mode

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |  104 
 1 file changed, 104 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 83ce890..d6cf698 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -126,6 +126,13 @@ do {   
\
 #define CPSW_FIFO_DUAL_MAC_MODE(1  15)
 #define CPSW_FIFO_RATE_LIMIT_MODE  (2  15)
 
+#define CPSW_INTPACEEN (0x3f  16)
+#define CPSW_INTPRESCALE_MASK  (0x7FF  0)
+#define CPSW_CMINTMAX_CNT  63
+#define CPSW_CMINTMIN_CNT  2
+#define CPSW_CMINTMAX_INTVL(1000 / CPSW_CMINTMIN_CNT)
+#define CPSW_CMINTMIN_INTVL((1000 / CPSW_CMINTMAX_CNT) + 1)
+
 #define cpsw_enable_irq(priv)  \
do {\
u32 i;  \
@@ -164,6 +171,15 @@ struct cpsw_wr_regs {
u32 rx_en;
u32 tx_en;
u32 misc_en;
+   u32 mem_allign1[8];
+   u32 rx_thresh_stat;
+   u32 rx_stat;
+   u32 tx_stat;
+   u32 misc_stat;
+   u32 mem_allign2[8];
+   u32 rx_imax;
+   u32 tx_imax;
+
 };
 
 struct cpsw_ss_regs {
@@ -318,6 +334,8 @@ struct cpsw_priv {
struct cpsw_host_regs __iomem   *host_port_regs;
u32 msg_enable;
u32 version;
+   u32 coal_intvl;
+   u32 bus_freq_mhz;
struct net_device_stats stats;
int rx_packet_max;
int host_port;
@@ -616,6 +634,77 @@ static void cpsw_adjust_link(struct net_device *ndev)
}
 }
 
+static int cpsw_get_coalesce(struct net_device *ndev,
+   struct ethtool_coalesce *coal)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+
+   coal-rx_coalesce_usecs = priv-coal_intvl;
+   return 0;
+}
+
+static int cpsw_set_coalesce(struct net_device *ndev,
+   struct ethtool_coalesce *coal)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   u32 int_ctrl;
+   u32 num_interrupts = 0;
+   u32 prescale = 0;
+   u32 addnl_dvdr = 1;
+   u32 coal_intvl = 0;
+
+   if (!coal-rx_coalesce_usecs)
+   return -EINVAL;
+
+   coal_intvl = coal-rx_coalesce_usecs;
+
+   int_ctrl =  readl(priv-wr_regs-int_control);
+   prescale = priv-bus_freq_mhz * 4;
+
+   if (coal_intvl  CPSW_CMINTMIN_INTVL)
+   coal_intvl = CPSW_CMINTMIN_INTVL;
+
+   if (coal_intvl  CPSW_CMINTMAX_INTVL) {
+   /* Interrupt pacer works with 4us Pulse, we can
+* throttle further by dilating the 4us pulse.
+*/
+   addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
+
+   if (addnl_dvdr  1) {
+   prescale *= addnl_dvdr;
+   if (coal_intvl  (CPSW_CMINTMAX_INTVL * addnl_dvdr))
+   coal_intvl = (CPSW_CMINTMAX_INTVL
+   * addnl_dvdr);
+   } else {
+   addnl_dvdr = 1;
+   coal_intvl = CPSW_CMINTMAX_INTVL;
+   }
+   }
+
+   num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
+   writel(num_interrupts, priv-wr_regs-rx_imax);
+   writel(num_interrupts, priv-wr_regs-tx_imax);
+
+   int_ctrl |= CPSW_INTPACEEN;
+   int_ctrl = (~CPSW_INTPRESCALE_MASK);
+   int_ctrl |= (prescale  CPSW_INTPRESCALE_MASK);
+   writel(int_ctrl, priv-wr_regs-int_control);
+
+   cpsw_notice(priv, timer, Set coalesce to %d usecs.\n, coal_intvl);
+   if (priv-data.dual_emac) {
+   int i;
+
+   for (i = 0; i  priv-data.slaves; i++) {
+   priv = netdev_priv(priv-slaves[i].ndev);
+   priv-coal_intvl = coal_intvl;
+   }
+   } else {
+   priv-coal_intvl = coal_intvl;
+   }
+
+   return 0;
+}
+
 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 {
static char *leader = ;
@@ -838,6 +927,14 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpsw_info(priv, ifup, submitted %d rx descriptors\n, i);
}
 
+   /* Enable Interrupt pacing if configured */
+   if (priv-coal_intvl != 0) {
+   struct ethtool_coalesce coal;
+
+   coal.rx_coalesce_usecs = (priv-coal_intvl  4);
+   cpsw_set_coalesce(ndev, coal);
+   }
+
cpdma_ctlr_start(priv-dma);
cpsw_intr_enable(priv

[PATCH v2 5/5] drivers: net: ethernet: cpsw: implement get phy_id via ioctl

2013-03-12 Thread Mugunthan V N

Implement get phy_id via ioctl SIOCGMIIPHY. In switch mode active phy_id
is returned and in dual EMAC mode slave's specific phy_id is returned.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index d6cf698..8ff1d3d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1157,14 +1157,26 @@ static int cpsw_hwtstamp_ioctl(struct net_device *dev, 
struct ifreq *ifr)
 
 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 {
+   struct cpsw_priv *priv = netdev_priv(dev);
+   struct mii_ioctl_data *data = if_mii(req);
+   int slave_no = cpsw_slave_index(priv);
+
if (!netif_running(dev))
return -EINVAL;
 
+   switch (cmd) {
 #ifdef CONFIG_TI_CPTS
-   if (cmd == SIOCSHWTSTAMP)
+   case SIOCSHWTSTAMP:
return cpsw_hwtstamp_ioctl(dev, req);
 #endif
-   return -ENOTSUPP;
+   case SIOCGMIIPHY:
+   data-phy_id = priv-slaves[slave_no].phy-addr;
+   break;
+   default:
+   return -ENOTSUPP;
+   }
+
+   return 0;
 }
 
 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
-- 
1.7.9.5

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[PATCH v2 1/5] documentation: dt: bindings: cpsw: cleanup documentation

2013-03-12 Thread Mugunthan V N

Move all the slave note properties to separate section to reduce the
confusion between slave note properties and cpsw node properties

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 Documentation/devicetree/bindings/net/cpsw.txt |9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
index ecfdf75..8e49c42 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -18,13 +18,18 @@ Required properties:
 - cpts_active_slave: Specifies the slave to use for time stamping
 - cpts_clock_mult  : Numerator to convert input clock ticks into 
nanoseconds
 - cpts_clock_shift : Denominator to convert input clock ticks into 
nanoseconds
-- phy_id   : Specifies slave phy id
-- mac-address  : Specifies slave MAC address
 
 Optional properties:
 - ti,hwmods: Must be cpgmac0
 - no_bd_ram: Must be 0 or 1
 - dual_emac: Specifies Switch to act as Dual EMAC
+
+Slave Properties:
+Required properties:
+- phy_id   : Specifies slave phy id
+- mac-address  : Specifies slave MAC address
+
+Optional properties:
 - dual_emac_res_vlan   : Specifies VID to be used to segregate the ports
 
 Note: ti,hwmods field is used to fetch the base address and irq
-- 
1.7.9.5

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[PATCH v2 3/5] driver: net: ethernet: cpsw: implement ethtool get/set phy setting

2013-03-12 Thread Mugunthan V N

This patch implements get/set of the phy settings via ethtool apis

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 98aa17a..83ce890 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -139,6 +139,10 @@ do {   
\
disable_irq_nosync(priv-irqs_table[i]); \
} while (0);
 
+#define cpsw_slave_index(priv) \
+   ((priv-data.dual_emac) ? priv-emac_port : \
+   priv-data.active_slave)
+
 static int debug_level;
 module_param(debug_level, int, 0);
 MODULE_PARM_DESC(debug_level, cpsw debug level (NETIF_MSG bits));
@@ -1244,12 +1248,37 @@ static int cpsw_get_ts_info(struct net_device *ndev,
return 0;
 }
 
+static int cpsw_get_settings(struct net_device *ndev,
+struct ethtool_cmd *ecmd)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   int slave_no = cpsw_slave_index(priv);
+
+   if (priv-slaves[slave_no].phy)
+   return phy_ethtool_gset(priv-slaves[slave_no].phy, ecmd);
+   else
+   return -EOPNOTSUPP;
+}
+
+static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   int slave_no = cpsw_slave_index(priv);
+
+   if (priv-slaves[slave_no].phy)
+   return phy_ethtool_sset(priv-slaves[slave_no].phy, ecmd);
+   else
+   return -EOPNOTSUPP;
+}
+
 static const struct ethtool_ops cpsw_ethtool_ops = {
.get_drvinfo= cpsw_get_drvinfo,
.get_msglevel   = cpsw_get_msglevel,
.set_msglevel   = cpsw_set_msglevel,
.get_link   = ethtool_op_get_link,
.get_ts_info= cpsw_get_ts_info,
+   .get_settings   = cpsw_get_settings,
+   .set_settings   = cpsw_set_settings,
 };
 
 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
-- 
1.7.9.5

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[PATCH v2 0/5] cpsw interrupt pacing and get/set phy setting implementation

2013-03-12 Thread Mugunthan V N

This patch serires implements the following features in CPSW driver
* get/set phy link settings
* interrupt pacing
* get phy id via ioctl cmd SIOCGMIIPHY

Changes from initial version
* Made active-slave common for cpts, ethtool and SIOCGMIIPHY ioctl
* Cleaned CPSW DT binding documentation by seperating slave nodes
  under sub-section
* implemented get phy id via ioctl cmd SIOCGMIIPHY

Mugunthan V N (5):
  documentation: dt: bindings: cpsw: cleanup documentation
  drivers: net: ethernet: cpsw: change cpts_active_slave to
active_slave
  driver: net: ethernet: cpsw: implement ethtool get/set phy setting
  driver: net: ethernet: cpsw: implement interrupt pacing via ethtool
  drivers: net: ethernet: cpsw: implement get phy_id via ioctl

 Documentation/devicetree/bindings/net/cpsw.txt |   16 ++-
 arch/arm/boot/dts/am33xx.dtsi  |2 +-
 drivers/net/ethernet/ti/cpsw.c |  159 ++--
 include/linux/platform_data/cpsw.h |2 +-
 4 files changed, 165 insertions(+), 14 deletions(-)

-- 
1.7.9.5

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[PATCH v2 2/5] drivers: net: ethernet: cpsw: change cpts_active_slave to active_slave

2013-03-12 Thread Mugunthan V N

Change cpts_active_slave to active_slave so that the same DT property
can be used to ethtool and SIOCGMIIPHY.

CC: Richard Cochran richardcoch...@gmail.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 Documentation/devicetree/bindings/net/cpsw.txt |7 ---
 arch/arm/boot/dts/am33xx.dtsi  |2 +-
 drivers/net/ethernet/ti/cpsw.c |   10 +-
 include/linux/platform_data/cpsw.h |2 +-
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
index 8e49c42..4f2ca6b 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -15,7 +15,8 @@ Required properties:
 - mac_control  : Specifies Default MAC control register content
  for the specific platform
 - slaves   : Specifies number for slaves
-- cpts_active_slave: Specifies the slave to use for time stamping
+- active_slave : Specifies the slave to use for time stamping,
+ ethtool and SIOCGMIIPHY
 - cpts_clock_mult  : Numerator to convert input clock ticks into 
nanoseconds
 - cpts_clock_shift : Denominator to convert input clock ticks into 
nanoseconds
 
@@ -52,7 +53,7 @@ Examples:
rx_descs = 64;
mac_control = 0x20;
slaves = 2;
-   cpts_active_slave = 0;
+   active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
cpsw_emac0: slave@0 {
@@ -78,7 +79,7 @@ Examples:
rx_descs = 64;
mac_control = 0x20;
slaves = 2;
-   cpts_active_slave = 0;
+   active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
cpsw_emac0: slave@0 {
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..91fe4f1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -349,7 +349,7 @@
rx_descs = 64;
mac_control = 0x20;
slaves = 2;
-   cpts_active_slave = 0;
+   active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
reg = 0x4a10 0x800
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 01ffbc4..98aa17a 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -942,7 +942,7 @@ static void cpsw_ndo_change_rx_flags(struct net_device 
*ndev, int flags)
 
 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
 {
-   struct cpsw_slave *slave = priv-slaves[priv-data.cpts_active_slave];
+   struct cpsw_slave *slave = priv-slaves[priv-data.active_slave];
u32 ts_en, seq_id;
 
if (!priv-cpts-tx_enable  !priv-cpts-rx_enable) {
@@ -971,7 +971,7 @@ static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
if (priv-data.dual_emac)
slave = priv-slaves[priv-emac_port];
else
-   slave = priv-slaves[priv-data.cpts_active_slave];
+   slave = priv-slaves[priv-data.active_slave];
 
ctrl = slave_read(slave, CPSW2_CONTROL);
ctrl = ~CTRL_ALL_TS_MASK;
@@ -1282,12 +1282,12 @@ static int cpsw_probe_dt(struct cpsw_platform_data 
*data,
}
data-slaves = prop;
 
-   if (of_property_read_u32(node, cpts_active_slave, prop)) {
-   pr_err(Missing cpts_active_slave property in the DT.\n);
+   if (of_property_read_u32(node, active_slave, prop)) {
+   pr_err(Missing active_slave property in the DT.\n);
ret = -EINVAL;
goto error_ret;
}
-   data-cpts_active_slave = prop;
+   data-active_slave = prop;
 
if (of_property_read_u32(node, cpts_clock_mult, prop)) {
pr_err(Missing cpts_clock_mult property in the DT.\n);
diff --git a/include/linux/platform_data/cpsw.h 
b/include/linux/platform_data/cpsw.h
index 798fb80..bb3cd58 100644
--- a/include/linux/platform_data/cpsw.h
+++ b/include/linux/platform_data/cpsw.h
@@ -30,7 +30,7 @@ struct cpsw_platform_data {
u32 channels;   /* number of cpdma channels (symmetric) */
u32 slaves; /* number of slave cpgmac ports */
struct cpsw_slave_data  *slave_data;
-   u32 cpts_active_slave; /* time stamping slave */
+   u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
u32 cpts_clock_mult;  /* convert input clock ticks to nanoseconds */
u32 cpts_clock_shift; /* convert input clock ticks to nanoseconds */
u32 ale_entries;/* ale table size */
-- 
1.7.9.5

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Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting

2013-03-08 Thread Mugunthan V N


On 3/8/2013 8:23 PM, Ben Hutchings wrote:

On Fri, 2013-03-08 at 12:53 +0530, Mugunthan V N wrote:

On 3/8/2013 1:29 AM, Ben Hutchings wrote:

On Thu, 2013-03-07 at 14:24 +0100, Peter Korsgaard wrote:

M == Mugunthan V N mugunthan...@ti.com writes:

   M This patch implements get/set of the phy settings via ethtool apis
   M Signed-off-by: Mugunthan V N mugunthan...@ti.com
   M ---
   M  Documentation/devicetree/bindings/net/cpsw.txt |3 +++
   M  drivers/net/ethernet/ti/cpsw.c |   32 

   M  include/linux/platform_data/cpsw.h |1 +
   M  3 files changed, 36 insertions(+)

   M diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
   M index ecfdf75..8d61300 100644
   M --- a/Documentation/devicetree/bindings/net/cpsw.txt
   M +++ b/Documentation/devicetree/bindings/net/cpsw.txt
   M @@ -20,6 +20,7 @@ Required properties:
   M  - cpts_clock_shift: Denominator to convert input clock ticks into 
nanoseconds
   M  - phy_id  : Specifies slave phy id
   M  - mac-address : Specifies slave MAC address
   M +- ethtool-active-slave: Specifies the slave to use for ethtool 
command

That again sounds like something Linux specific rather than a hardware
property.

Yes, indeed.  Isn't it redundant with the phy_id?

Ben.

phy_id is part of slave data and will be present for both the slaves.
so phy_id cannot be used for get/set phy setting until phy framework
allows to change settings without going through eth interface.

Now I've looked at the examples in this file, I think I see what you're
getting at.  What confused me is that you're adding to a single list of
properties without a proper distinction of which devices they are
applied to.  It really ought to be properly divided between switch and
'slave' properties.

Will fix this in next patch series.

The 'active slave' property would also be needed for the SIOCGMIIPHY
ioctl and not just ethtool.  But it's really quite arbitrary.  Perhaps
each of them should have their own net device (as with DSA).
But if we have net device for each of the slaves then it is dual EMAC 
which will kill
hardware switching functionality. To achieve switching bridge has to be 
done and

there will be a performance drop as well.

As Peter Korsgaard mentioned we need to have infrastructure to handle CPSW
kind of hardware.

Regards
Mugunthan V N
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Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting

2013-03-08 Thread Mugunthan V N


On 3/8/2013 8:34 PM, Peter Korsgaard wrote:

Ben == Ben Hutchings bhutchi...@solarflare.com writes:

Hi,

  Ben The 'active slave' property would also be needed for the SIOCGMIIPHY
  Ben ioctl and not just ethtool.  But it's really quite arbitrary.  Perhaps
  Ben each of them should have their own net device (as with DSA).

Indeed, I think that would simplify all of this quite a bit.


I will update this in the next patch series

Regards
Mugunthan V N
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[PATCH 3/3] driver: net: ethernet: cpsw: implement interrupt pacing via ethtool

2013-03-07 Thread Mugunthan V N

This patch implements support for interrupt pacing block of CPSW via ethtool

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   95 
 1 file changed, 95 insertions(+)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index fa91eec..da7276d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -126,6 +126,13 @@ do {   
\
 #define CPSW_FIFO_DUAL_MAC_MODE(1  15)
 #define CPSW_FIFO_RATE_LIMIT_MODE  (2  15)
 
+#define CPSW_INTPACEEN (0x3f  16)
+#define CPSW_INTPRESCALE_MASK  (0x7FF  0)
+#define CPSW_CMINTMAX_CNT  63
+#define CPSW_CMINTMIN_CNT  2
+#define CPSW_CMINTMAX_INTVL(1000 / CPSW_CMINTMIN_CNT)
+#define CPSW_CMINTMIN_INTVL((1000 / CPSW_CMINTMAX_CNT) + 1)
+
 #define cpsw_enable_irq(priv)  \
do {\
u32 i;  \
@@ -160,6 +167,15 @@ struct cpsw_wr_regs {
u32 rx_en;
u32 tx_en;
u32 misc_en;
+   u32 mem_allign1[8];
+   u32 rx_thresh_stat;
+   u32 rx_stat;
+   u32 tx_stat;
+   u32 misc_stat;
+   u32 mem_allign2[8];
+   u32 rx_imax;
+   u32 tx_imax;
+
 };
 
 struct cpsw_ss_regs {
@@ -314,6 +330,8 @@ struct cpsw_priv {
struct cpsw_host_regs __iomem   *host_port_regs;
u32 msg_enable;
u32 version;
+   u32 coal_intvl;
+   u32 bus_freq_mhz;
struct net_device_stats stats;
int rx_packet_max;
int host_port;
@@ -612,6 +630,68 @@ static void cpsw_adjust_link(struct net_device *ndev)
}
 }
 
+static int cpsw_get_coalesce(struct net_device *ndev,
+   struct ethtool_coalesce *coal)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+
+   coal-rx_coalesce_usecs = priv-coal_intvl;
+   return 0;
+}
+
+static int cpsw_set_coalesce(struct net_device *ndev,
+   struct ethtool_coalesce *coal)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   u32 int_ctrl;
+   u32 num_interrupts = 0;
+   u32 prescale = 0;
+   u32 addnl_dvdr = 1;
+   u32 coal_intvl = 0;
+
+   if (!coal-rx_coalesce_usecs)
+   return -EINVAL;
+
+   coal_intvl = coal-rx_coalesce_usecs;
+
+   int_ctrl =  readl(priv-wr_regs-int_control);
+   prescale = priv-bus_freq_mhz * 4;
+
+   if (coal_intvl  CPSW_CMINTMIN_INTVL)
+   coal_intvl = CPSW_CMINTMIN_INTVL;
+
+   if (coal_intvl  CPSW_CMINTMAX_INTVL) {
+   /* Interrupt pacer works with 4us Pulse, we can
+* throttle further by dilating the 4us pulse.
+*/
+   addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
+
+   if (addnl_dvdr  1) {
+   prescale *= addnl_dvdr;
+   if (coal_intvl  (CPSW_CMINTMAX_INTVL * addnl_dvdr))
+   coal_intvl = (CPSW_CMINTMAX_INTVL
+   * addnl_dvdr);
+   } else {
+   addnl_dvdr = 1;
+   coal_intvl = CPSW_CMINTMAX_INTVL;
+   }
+   }
+
+   num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
+   writel(num_interrupts, priv-wr_regs-rx_imax);
+   writel(num_interrupts, priv-wr_regs-tx_imax);
+
+   int_ctrl |= CPSW_INTPACEEN;
+   int_ctrl = (~CPSW_INTPRESCALE_MASK);
+   int_ctrl |= (prescale  CPSW_INTPRESCALE_MASK);
+   writel(int_ctrl, priv-wr_regs-int_control);
+
+   cpsw_notice(priv, timer, Set coalesce to %d usecs.\n, coal_intvl);
+   priv-coal_intvl = coal_intvl;
+
+   return 0;
+}
+
 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 {
static char *leader = ;
@@ -834,6 +914,14 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpsw_info(priv, ifup, submitted %d rx descriptors\n, i);
}
 
+   /* Enable Interrupt pacing if configured */
+   if (priv-coal_intvl != 0) {
+   struct ethtool_coalesce coal;
+
+   coal.rx_coalesce_usecs = (priv-coal_intvl  4);
+   cpsw_set_coalesce(ndev, coal);
+   }
+
cpdma_ctlr_start(priv-dma);
cpsw_intr_enable(priv);
napi_enable(priv-napi);
@@ -1279,6 +1367,8 @@ static const struct ethtool_ops cpsw_ethtool_ops = {
.get_ts_info= cpsw_get_ts_info,
.get_settings   = cpsw_get_settings,
.set_settings   = cpsw_set_settings,
+   .get_coalesce   = cpsw_get_coalesce,
+   .set_coalesce   = cpsw_set_coalesce,
 };
 
 static void cpsw_slave_init

[PATCH 0/3] cpsw interrupt pacing and get/set phy setting implementation

2013-03-07 Thread Mugunthan V N

This patch serires implements the following features in CPSW driver
* get/set phy link settings
* interrupt pacing

Mugunthan V N (3):
  driver: net: ethernet: cpsw: implement ethtool get/set phy setting
  arm: dts: am33xx: add default ethtool slave to cpsw node
  driver: net: ethernet: cpsw: implement interrupt pacing via ethtool

 Documentation/devicetree/bindings/net/cpsw.txt |3 +
 arch/arm/boot/dts/am33xx.dtsi  |1 +
 drivers/net/ethernet/ti/cpsw.c |  127 
 include/linux/platform_data/cpsw.h |1 +
 4 files changed, 132 insertions(+)

-- 
1.7.9.5

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[PATCH 2/3] arm: dts: am33xx: add default ethtool slave to cpsw node

2013-03-07 Thread Mugunthan V N

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am33xx.dtsi |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..f8c83a1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -352,6 +352,7 @@
cpts_active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
+   ethtool-active-slave = 0;
reg = 0x4a10 0x800
   0x4a101200 0x100;
#address-cells = 1;
-- 
1.7.9.5

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[PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting

2013-03-07 Thread Mugunthan V N

This patch implements get/set of the phy settings via ethtool apis

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 Documentation/devicetree/bindings/net/cpsw.txt |3 +++
 drivers/net/ethernet/ti/cpsw.c |   32 
 include/linux/platform_data/cpsw.h |1 +
 3 files changed, 36 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
index ecfdf75..8d61300 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -20,6 +20,7 @@ Required properties:
 - cpts_clock_shift : Denominator to convert input clock ticks into 
nanoseconds
 - phy_id   : Specifies slave phy id
 - mac-address  : Specifies slave MAC address
+- ethtool-active-slave : Specifies the slave to use for ethtool command
 
 Optional properties:
 - ti,hwmods: Must be cpgmac0
@@ -50,6 +51,7 @@ Examples:
cpts_active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
+   ethtool-active-slave = 0;
cpsw_emac0: slave@0 {
phy_id = davinci_mdio, 0;
/* Filled in by U-Boot */
@@ -76,6 +78,7 @@ Examples:
cpts_active_slave = 0;
cpts_clock_mult = 0x8000;
cpts_clock_shift = 29;
+   ethtool-active-slave = 0;
cpsw_emac0: slave@0 {
phy_id = davinci_mdio, 0;
/* Filled in by U-Boot */
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 01ffbc4..fa91eec 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1244,12 +1244,41 @@ static int cpsw_get_ts_info(struct net_device *ndev,
return 0;
 }
 
+#define cpsw_slave_phy_index(priv) \
+   ((priv-data.dual_emac) ? priv-emac_port : \
+   priv-data.ethtool_active_slave)
+
+static int cpsw_get_settings(struct net_device *ndev,
+struct ethtool_cmd *ecmd)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   int slave_no = cpsw_slave_phy_index(priv);
+
+   if (priv-slaves[slave_no].phy)
+   return phy_ethtool_gset(priv-slaves[slave_no].phy, ecmd);
+   else
+   return -EOPNOTSUPP;
+}
+
+static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   int slave_no = cpsw_slave_phy_index(priv);
+
+   if (priv-slaves[slave_no].phy)
+   return phy_ethtool_sset(priv-slaves[slave_no].phy, ecmd);
+   else
+   return -EOPNOTSUPP;
+}
+
 static const struct ethtool_ops cpsw_ethtool_ops = {
.get_drvinfo= cpsw_get_drvinfo,
.get_msglevel   = cpsw_get_msglevel,
.set_msglevel   = cpsw_set_msglevel,
.get_link   = ethtool_op_get_link,
.get_ts_info= cpsw_get_ts_info,
+   .get_settings   = cpsw_get_settings,
+   .set_settings   = cpsw_set_settings,
 };
 
 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
@@ -1346,6 +1375,9 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
if (!of_property_read_u32(node, dual_emac, prop))
data-dual_emac = prop;
 
+   if (!of_property_read_u32(node, ethtool-active-slave, prop))
+   data-ethtool_active_slave = prop;
+
/*
 * Populate all the child nodes here...
 */
diff --git a/include/linux/platform_data/cpsw.h 
b/include/linux/platform_data/cpsw.h
index 798fb80..e87e5cb 100644
--- a/include/linux/platform_data/cpsw.h
+++ b/include/linux/platform_data/cpsw.h
@@ -39,6 +39,7 @@ struct cpsw_platform_data {
u32 mac_control;/* Mac control register */
u16 default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
booldual_emac;  /* Enable Dual EMAC mode */
+   u32 ethtool_active_slave; /* ethtool slave */
 };
 
 #endif /* __CPSW_H__ */
-- 
1.7.9.5

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Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting

2013-03-07 Thread Mugunthan V N


On 3/7/2013 6:54 PM, Peter Korsgaard wrote:

M == Mugunthan V N mugunthan...@ti.com writes:

  M This patch implements get/set of the phy settings via ethtool apis
  M Signed-off-by: Mugunthan V N mugunthan...@ti.com
  M ---
  M  Documentation/devicetree/bindings/net/cpsw.txt |3 +++
  M  drivers/net/ethernet/ti/cpsw.c |   32 

  M  include/linux/platform_data/cpsw.h |1 +
  M  3 files changed, 36 insertions(+)

  M diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
  M index ecfdf75..8d61300 100644
  M --- a/Documentation/devicetree/bindings/net/cpsw.txt
  M +++ b/Documentation/devicetree/bindings/net/cpsw.txt
  M @@ -20,6 +20,7 @@ Required properties:
  M  - cpts_clock_shift : Denominator to convert input clock ticks into 
nanoseconds
  M  - phy_id   : Specifies slave phy id
  M  - mac-address  : Specifies slave MAC address
  M +- ethtool-active-slave : Specifies the slave to use for ethtool command

That again sounds like something Linux specific rather than a hardware
property.

It would be good if all these special things (dual emac mode, vlan
handling, switching) could be handled using the existing kernel
(bridging/vlan) infrastructure, and the driver always just exposing 2
network interfaces instead of these configuration properties.

Switch and Dual Emac modes of operation of CPSW are two different 
features of the
hardware and packet routing between the slaves in the hardware are 
different in

both the modes.

If by default it is brought up as Dual EMAC then hardware switching is 
blocked and

use-cases like IP phone etc cannot be achieved.

Since CPSW as a hardware Switch, it cannot not be handled in existing kernel
feature.

Regards
Mugunthan V N
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Re: [PATCH 2/3] arm: dts: am33xx: add default ethtool slave to cpsw node

2013-03-07 Thread Mugunthan V N


On 3/7/2013 9:43 PM, Tony Lindgren wrote:

* Mugunthan V N mugunthan...@ti.com [130307 04:35]:

Can you please add a description and send this separately
so Benoit can queue it.



Will send this patch separately after this patch series has been
reviewed and accepted by netdev maintainer.

Regards
Mugunthan V N
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Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting

2013-03-07 Thread Mugunthan V N


On 3/8/2013 1:29 AM, Ben Hutchings wrote:

On Thu, 2013-03-07 at 14:24 +0100, Peter Korsgaard wrote:

M == Mugunthan V N mugunthan...@ti.com writes:

  M This patch implements get/set of the phy settings via ethtool apis
  M Signed-off-by: Mugunthan V N mugunthan...@ti.com
  M ---
  M  Documentation/devicetree/bindings/net/cpsw.txt |3 +++
  M  drivers/net/ethernet/ti/cpsw.c |   32 

  M  include/linux/platform_data/cpsw.h |1 +
  M  3 files changed, 36 insertions(+)

  M diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
  M index ecfdf75..8d61300 100644
  M --- a/Documentation/devicetree/bindings/net/cpsw.txt
  M +++ b/Documentation/devicetree/bindings/net/cpsw.txt
  M @@ -20,6 +20,7 @@ Required properties:
  M  - cpts_clock_shift : Denominator to convert input clock ticks into 
nanoseconds
  M  - phy_id   : Specifies slave phy id
  M  - mac-address  : Specifies slave MAC address
  M +- ethtool-active-slave : Specifies the slave to use for ethtool command

That again sounds like something Linux specific rather than a hardware
property.

Yes, indeed.  Isn't it redundant with the phy_id?

Ben.

phy_id is part of slave data and will be present for both the slaves.
so phy_id cannot be used for get/set phy setting until phy framework
allows to change settings without going through eth interface.

Regards
Mugunthan V N
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[PATCH v3 net-next 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-02-18 Thread Mugunthan V N

CPDMA interrupts are not properly acknowledged which leads to interrupt
storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
used for rx and tx respectively.

Reported-by: Pantelis Antoniou pa...@antoniou-consulting.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
Changes from v2:
* Changed the hardware register values from enumeration to defines

 drivers/net/ethernet/ti/cpsw.c  |   25 -
 drivers/net/ethernet/ti/davinci_cpdma.c |4 ++--
 drivers/net/ethernet/ti/davinci_cpdma.h |7 ++-
 3 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 4ceed6e..7e93df6 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -510,19 +510,21 @@ static int cpsw_poll(struct napi_struct *napi, int budget)
int num_tx, num_rx;
 
num_tx = cpdma_chan_process(priv-txch, 128);
-   num_rx = cpdma_chan_process(priv-rxch, budget);
-
-   if (num_rx || num_tx)
-   cpsw_dbg(priv, intr, poll %d rx, %d tx pkts\n,
-num_rx, num_tx);
+   if (num_tx)
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
 
+   num_rx = cpdma_chan_process(priv-rxch, budget);
if (num_rx  budget) {
napi_complete(napi);
cpsw_intr_enable(priv);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
cpsw_enable_irq(priv);
}
 
+   if (num_rx || num_tx)
+   cpsw_dbg(priv, intr, poll %d rx, %d tx pkts\n,
+num_rx, num_tx);
+
return num_rx;
 }
 
@@ -835,7 +837,8 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpdma_ctlr_start(priv-dma);
cpsw_intr_enable(priv);
napi_enable(priv-napi);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
 
if (priv-data.dual_emac)
priv-slaves[priv-emac_port].open_stat = true;
@@ -1075,7 +1078,9 @@ static void cpsw_ndo_tx_timeout(struct net_device *ndev)
cpdma_chan_start(priv-txch);
cpdma_ctlr_int_ctrl(priv-dma, true);
cpsw_intr_enable(priv);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
+
 }
 
 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
@@ -1094,7 +1099,9 @@ static void cpsw_ndo_poll_controller(struct net_device 
*ndev)
cpsw_interrupt(ndev-irq, priv);
cpdma_ctlr_int_ctrl(priv-dma, true);
cpsw_intr_enable(priv);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
+
 }
 #endif
 
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c 
b/drivers/net/ethernet/ti/davinci_cpdma.c
index 7d3bffd..68c3418 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -493,9 +493,9 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool 
enable)
return 0;
 }
 
-void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
+void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
 {
-   dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
+   dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
 }
 
 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h 
b/drivers/net/ethernet/ti/davinci_cpdma.h
index a97d6ab..d9bcc60 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.h
+++ b/drivers/net/ethernet/ti/davinci_cpdma.h
@@ -26,6 +26,11 @@
 
 #define CPDMA_RX_SOURCE_PORT(__status__)   ((__status__  16)  0x7)
 
+#define CPDMA_EOI_RX_THRESH0x0
+#define CPDMA_EOI_RX   0x1
+#define CPDMA_EOI_TX   0x2
+#define CPDMA_EOI_MISC 0x3
+
 struct cpdma_params {
struct device   *dev;
void __iomem*dmaregs;
@@ -88,7 +93,7 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, 
void *data,
 int cpdma_chan_process(struct cpdma_chan *chan, int quota);
 
 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
-void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr);
+void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
 
-- 
1.7.9.5

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Re: [PATCH 3/3] driver: net: ethernet: cpsw: dual emac interface implementation

2013-02-18 Thread Mugunthan V N


On 2/18/2013 7:06 PM, Peter Korsgaard wrote:

M == Mugunthan V N mugunthan...@ti.com writes:

  M The CPSW switch can act as Dual EMAC by segregating the switch ports
  M using VLAN and port VLAN as per the TRM description in
  M 14.3.2.10.2 Dual Mac Mode

  M Following CPSW components will be common for both the interfaces.
  M * Interrupt source is common for both eth interfaces
  M * Interrupt pacing is common for both interfaces
  M * Hardware statistics is common for all the ports
  M * CPDMA is common for both eth interface
  M * CPTS is common for both the interface and it should not be enabled on
  M   both the interface as timestamping information doesn't contain port
  M   information.

  M Constrains
  M * Reserved VID of One port should not be used in other interface which will
  M   enable switching functionality
  M * Same VID must not be used in both the interface which will enable 
switching
  M   functionality

  M Signed-off-by: Mugunthan V N mugunthan...@ti.com
  M ---
  M  Documentation/devicetree/bindings/net/cpsw.txt |2 +
  M  drivers/net/ethernet/ti/cpsw.c |  335 

  M  include/linux/platform_data/cpsw.h |3 +
  M  3 files changed, 288 insertions(+), 52 deletions(-)

  M diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
  M index 6ddd028..ecfdf75 100644
  M --- a/Documentation/devicetree/bindings/net/cpsw.txt
  M +++ b/Documentation/devicetree/bindings/net/cpsw.txt
  M @@ -24,6 +24,8 @@ Required properties:
  M  Optional properties:
  M  - ti,hwmods: Must be cpgmac0
  M  - no_bd_ram: Must be 0 or 1
  M +- dual_emac: Specifies Switch to act as Dual EMAC
  M +- dual_emac_res_vlan   : Specifies VID to be used to segregate the ports

You forgot to CC devicetree-discuss. Properties normally use dashes (-)
instead of underscores (_). These properties are more about
configuration and not hardware.

It is not clear to me from the description that dual_emac is a boolean
(0/1). Shouldn't dual_emacs_res_vlan be a property of the slave?

It would also be good to update the example below with this.
Since the series is already applied in net-next tree, i will submit a 
patch with incorporating

the above comments. Will add devicetree-discuss in my future patches.

Regards
Mugunthan V N
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Re: [PATCH v2 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-02-17 Thread Mugunthan V N

On 2/16/2013 1:35 AM, David Miller wrote:

From: Mugunthan V N mugunthan...@ti.com
Date: Thu, 14 Feb 2013 23:56:46 +0530

+enum {
+   CPDMA_EOI_RX_THRESH = 0,
+   CPDMA_EOI_RX,
+   CPDMA_EOI_TX,
+   CPDMA_EOI_MISC,
+};

Do not use enumerations for hardware register values, which must be
exact, otherwise you are potentially going to succumb to the vagaries
of C language enumeration value assignment.

Will change enum to define and submit next version patch.

Regards
Mugunthan V N
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Re: [PATCH v2 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-02-17 Thread Mugunthan V N


On 2/16/2013 1:35 AM, David Miller wrote:

Also please indicate, clearly, what tree your patch is targetted at.

Sorry for not mentioning the tree, will mention in the future patches.

Regards
Mugunthan V N
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[PATCH 1/1] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk

2013-02-14 Thread Mugunthan V N

Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 arch/arm/boot/dts/am335x-evmsk.dts |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts 
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..f297b85 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
 };
+
+cpsw_emac0 {
+   phy_id = davinci_mdio, 0;
+};
+
+cpsw_emac1 {
+   phy_id = davinci_mdio, 1;
+};
-- 
1.7.9.5

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[PATCH v2 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-02-14 Thread Mugunthan V N

CPDMA interrupts are not properly acknowledged which leads to interrupt
storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
used for rx and tx respectively.

Reported-by: Pantelis Antoniou pa...@antoniou-consulting.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
Changes from Initial Version:
* Changed Tx and Rx EOI seperated so that Tx interrupt will not be cleared
  without processing any txpackets so that none of the interrupt are missed
  or cleared without processing.

 drivers/net/ethernet/ti/cpsw.c  |   25 -
 drivers/net/ethernet/ti/davinci_cpdma.c |4 ++--
 drivers/net/ethernet/ti/davinci_cpdma.h |9 -
 3 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 4ceed6e..7e93df6 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -510,19 +510,21 @@ static int cpsw_poll(struct napi_struct *napi, int budget)
int num_tx, num_rx;
 
num_tx = cpdma_chan_process(priv-txch, 128);
-   num_rx = cpdma_chan_process(priv-rxch, budget);
-
-   if (num_rx || num_tx)
-   cpsw_dbg(priv, intr, poll %d rx, %d tx pkts\n,
-num_rx, num_tx);
+   if (num_tx)
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
 
+   num_rx = cpdma_chan_process(priv-rxch, budget);
if (num_rx  budget) {
napi_complete(napi);
cpsw_intr_enable(priv);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
cpsw_enable_irq(priv);
}
 
+   if (num_rx || num_tx)
+   cpsw_dbg(priv, intr, poll %d rx, %d tx pkts\n,
+num_rx, num_tx);
+
return num_rx;
 }
 
@@ -835,7 +837,8 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpdma_ctlr_start(priv-dma);
cpsw_intr_enable(priv);
napi_enable(priv-napi);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
 
if (priv-data.dual_emac)
priv-slaves[priv-emac_port].open_stat = true;
@@ -1075,7 +1078,9 @@ static void cpsw_ndo_tx_timeout(struct net_device *ndev)
cpdma_chan_start(priv-txch);
cpdma_ctlr_int_ctrl(priv-dma, true);
cpsw_intr_enable(priv);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
+
 }
 
 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
@@ -1094,7 +1099,9 @@ static void cpsw_ndo_poll_controller(struct net_device 
*ndev)
cpsw_interrupt(ndev-irq, priv);
cpdma_ctlr_int_ctrl(priv-dma, true);
cpsw_intr_enable(priv);
-   cpdma_ctlr_eoi(priv-dma);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
+   cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
+
 }
 #endif
 
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c 
b/drivers/net/ethernet/ti/davinci_cpdma.c
index 7d3bffd..68c3418 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -493,9 +493,9 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool 
enable)
return 0;
 }
 
-void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
+void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
 {
-   dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
+   dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
 }
 
 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h 
b/drivers/net/ethernet/ti/davinci_cpdma.h
index a97d6ab..ac65033 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.h
+++ b/drivers/net/ethernet/ti/davinci_cpdma.h
@@ -63,6 +63,13 @@ struct cpdma_chan_stats {
u32 teardown_dequeue;
 };
 
+enum {
+   CPDMA_EOI_RX_THRESH = 0,
+   CPDMA_EOI_RX,
+   CPDMA_EOI_TX,
+   CPDMA_EOI_MISC,
+};
+
 struct cpdma_ctlr;
 struct cpdma_chan;
 
@@ -88,7 +95,7 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, 
void *data,
 int cpdma_chan_process(struct cpdma_chan *chan, int quota);
 
 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
-void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr);
+void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
 
-- 
1.7.9.5

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[PATCH 0/3] Dual EMAC mode implementation of CPSW

2013-02-11 Thread Mugunthan V N

This patch series implements Dual EMAC mode implementation of CPSW
which acts as two standalone EMAC by segregating the switch using VIDs
and port VLAN

Mugunthan V N (3):
  driver: net: ethernet: davinci_cpdma: add support for directed packet
and source port detection
  driver: net: ethernet: cpsw: make cpts as pointer
  driver: net: ethernet: cpsw: dual emac interface implementation

 Documentation/devicetree/bindings/net/cpsw.txt |2 +
 drivers/net/ethernet/ti/cpsw.c |  387 +++-
 drivers/net/ethernet/ti/davinci_cpdma.c|   17 +-
 drivers/net/ethernet/ti/davinci_cpdma.h|4 +-
 drivers/net/ethernet/ti/davinci_emac.c |6 +-
 include/linux/platform_data/cpsw.h |3 +
 6 files changed, 338 insertions(+), 81 deletions(-)

-- 
1.7.9.5

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[PATCH 2/3] driver: net: ethernet: cpsw: make cpts as pointer

2013-02-11 Thread Mugunthan V N

As CPTS is common module for both EMAC in Dual EMAC mode so making cpts as
pointer.

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |   36 +---
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 8ac60c7..4b964bb 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -319,7 +319,7 @@ struct cpsw_priv {
/* snapshot of IRQ numbers */
u32 irqs_table[4];
u32 num_irqs;
-   struct cpts cpts;
+   struct cpts *cpts;
 };
 
 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -383,7 +383,7 @@ void cpsw_tx_handler(void *token, int len, int status)
 */
if (unlikely(netif_queue_stopped(ndev)))
netif_start_queue(ndev);
-   cpts_tx_timestamp(priv-cpts, skb);
+   cpts_tx_timestamp(priv-cpts, skb);
priv-stats.tx_packets++;
priv-stats.tx_bytes += len;
dev_kfree_skb_any(skb);
@@ -404,7 +404,7 @@ void cpsw_rx_handler(void *token, int len, int status)
}
if (likely(status = 0)) {
skb_put(skb, len);
-   cpts_rx_timestamp(priv-cpts, skb);
+   cpts_rx_timestamp(priv-cpts, skb);
skb-protocol = eth_type_trans(skb, ndev);
netif_receive_skb(skb);
priv-stats.rx_bytes += len;
@@ -760,7 +760,8 @@ static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
return NETDEV_TX_OK;
}
 
-   if (skb_shinfo(skb)-tx_flags  SKBTX_HW_TSTAMP  priv-cpts.tx_enable)
+   if (skb_shinfo(skb)-tx_flags  SKBTX_HW_TSTAMP 
+   priv-cpts-tx_enable)
skb_shinfo(skb)-tx_flags |= SKBTX_IN_PROGRESS;
 
skb_tx_timestamp(skb);
@@ -815,7 +816,7 @@ static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
struct cpsw_slave *slave = priv-slaves[priv-data.cpts_active_slave];
u32 ts_en, seq_id;
 
-   if (!priv-cpts.tx_enable  !priv-cpts.rx_enable) {
+   if (!priv-cpts-tx_enable  !priv-cpts-rx_enable) {
slave_write(slave, 0, CPSW1_TS_CTL);
return;
}
@@ -823,10 +824,10 @@ static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
seq_id = (30  CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
ts_en = EVENT_MSG_BITS  CPSW_V1_MSG_TYPE_OFS;
 
-   if (priv-cpts.tx_enable)
+   if (priv-cpts-tx_enable)
ts_en |= CPSW_V1_TS_TX_EN;
 
-   if (priv-cpts.rx_enable)
+   if (priv-cpts-rx_enable)
ts_en |= CPSW_V1_TS_RX_EN;
 
slave_write(slave, ts_en, CPSW1_TS_CTL);
@@ -841,10 +842,10 @@ static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
ctrl = slave_read(slave, CPSW2_CONTROL);
ctrl = ~CTRL_ALL_TS_MASK;
 
-   if (priv-cpts.tx_enable)
+   if (priv-cpts-tx_enable)
ctrl |= CTRL_TX_TS_BITS;
 
-   if (priv-cpts.rx_enable)
+   if (priv-cpts-rx_enable)
ctrl |= CTRL_RX_TS_BITS;
 
mtype = (30  TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
@@ -857,7 +858,7 @@ static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 {
struct cpsw_priv *priv = netdev_priv(dev);
-   struct cpts *cpts = priv-cpts;
+   struct cpts *cpts = priv-cpts;
struct hwtstamp_config cfg;
 
if (copy_from_user(cfg, ifr-ifr_data, sizeof(cfg)))
@@ -1086,7 +1087,7 @@ static int cpsw_get_ts_info(struct net_device *ndev,
SOF_TIMESTAMPING_RX_SOFTWARE |
SOF_TIMESTAMPING_SOFTWARE |
SOF_TIMESTAMPING_RAW_HARDWARE;
-   info-phc_index = priv-cpts.phc_index;
+   info-phc_index = priv-cpts-phc_index;
info-tx_types =
(1  HWTSTAMP_TX_OFF) |
(1  HWTSTAMP_TX_ON);
@@ -1272,6 +1273,11 @@ static int cpsw_probe(struct platform_device *pdev)
priv-dev  = ndev-dev;
priv-msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
priv-rx_packet_max = max(rx_packet_max, 128);
+   priv-cpts = devm_kzalloc(pdev-dev, sizeof(struct cpts), GFP_KERNEL);
+   if (!ndev) {
+   pr_err(error allocating cpts\n);
+   goto clean_ndev_ret;
+   }
 
/*
 * This may be required here for child devices.
@@ -1358,7 +1364,7 @@ static int cpsw_probe(struct platform_device *pdev)
switch (priv-version) {
case CPSW_VERSION_1:
priv-host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
-   priv-cpts.reg   = ss_regs + CPSW1_CPTS_OFFSET;
+   priv-cpts-reg   = ss_regs + CPSW1_CPTS_OFFSET;
dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
@@ -1369,7

[PATCH 3/3] driver: net: ethernet: cpsw: dual emac interface implementation

2013-02-11 Thread Mugunthan V N

The CPSW switch can act as Dual EMAC by segregating the switch ports
using VLAN and port VLAN as per the TRM description in
14.3.2.10.2 Dual Mac Mode

Following CPSW components will be common for both the interfaces.
* Interrupt source is common for both eth interfaces
* Interrupt pacing is common for both interfaces
* Hardware statistics is common for all the ports
* CPDMA is common for both eth interface
* CPTS is common for both the interface and it should not be enabled on
  both the interface as timestamping information doesn't contain port
  information.

Constrains
* Reserved VID of One port should not be used in other interface which will
  enable switching functionality
* Same VID must not be used in both the interface which will enable switching
  functionality

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 Documentation/devicetree/bindings/net/cpsw.txt |2 +
 drivers/net/ethernet/ti/cpsw.c |  335 
 include/linux/platform_data/cpsw.h |3 +
 3 files changed, 288 insertions(+), 52 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
index 6ddd028..ecfdf75 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -24,6 +24,8 @@ Required properties:
 Optional properties:
 - ti,hwmods: Must be cpgmac0
 - no_bd_ram: Must be 0 or 1
+- dual_emac: Specifies Switch to act as Dual EMAC
+- dual_emac_res_vlan   : Specifies VID to be used to segregate the ports
 
 Note: ti,hwmods field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 4b964bb..4ceed6e 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -122,6 +122,10 @@ do {   
\
 #define CPSW_VLAN_AWAREBIT(1)
 #define CPSW_ALE_VLAN_AWARE1
 
+#define CPSW_FIFO_NORMAL_MODE  (0  15)
+#define CPSW_FIFO_DUAL_MAC_MODE(1  15)
+#define CPSW_FIFO_RATE_LIMIT_MODE  (2  15)
+
 #define cpsw_enable_irq(priv)  \
do {\
u32 i;  \
@@ -254,7 +258,7 @@ struct cpsw_ss_regs {
 struct cpsw_host_regs {
u32 max_blks;
u32 blk_cnt;
-   u32 flow_thresh;
+   u32 tx_in_ctl;
u32 port_vlan;
u32 tx_pri_map;
u32 cpdma_tx_pri_map;
@@ -281,6 +285,9 @@ struct cpsw_slave {
u32 mac_control;
struct cpsw_slave_data  *data;
struct phy_device   *phy;
+   struct net_device   *ndev;
+   u32 port_vlan;
+   u32 open_stat;
 };
 
 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
@@ -320,15 +327,63 @@ struct cpsw_priv {
u32 irqs_table[4];
u32 num_irqs;
struct cpts *cpts;
+   u32 emac_port;
 };
 
 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
-#define for_each_slave(priv, func, arg...) \
-   do {\
-   int idx;\
-   for (idx = 0; idx  (priv)-data.slaves; idx++) \
-   (func)((priv)-slaves + idx, ##arg);\
+#define for_each_slave(priv, func, arg...) \
+   do {\
+   int idx;\
+   if (priv-data.dual_emac)   \
+   (func)((priv)-slaves + priv-emac_port, ##arg);\
+   else\
+   for (idx = 0; idx  (priv)-data.slaves; idx++) \
+   (func)((priv)-slaves + idx, ##arg);\
+   } while (0)
+#define cpsw_get_slave_ndev(priv, __slave_no__)
\
+   (priv-slaves[__slave_no__].ndev)
+#define cpsw_get_slave_priv(priv, __slave_no__)
\
+   ((priv-slaves[__slave_no__].ndev) ?\
+   netdev_priv(priv-slaves[__slave_no__].ndev) : NULL)\
+
+#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)
\
+   do {\
+   if (!priv-data.dual_emac)  \
+   break;  \
+   if (CPDMA_RX_SOURCE_PORT(status) == 1) {\
+   ndev = cpsw_get_slave_ndev(priv, 0

[PATCH 1/3] driver: net: ethernet: davinci_cpdma: add support for directed packet and source port detection

2013-02-11 Thread Mugunthan V N

* Introduced parameter to add port number for directed packet in 
cpdma_chan_submit
* Source port detection macro with DMA descriptor status

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c  |6 +++---
 drivers/net/ethernet/ti/davinci_cpdma.c |   17 +++--
 drivers/net/ethernet/ti/davinci_cpdma.h |4 +++-
 drivers/net/ethernet/ti/davinci_emac.c  |6 +++---
 4 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 888708c..8ac60c7 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -424,7 +424,7 @@ void cpsw_rx_handler(void *token, int len, int status)
return;
 
ret = cpdma_chan_submit(priv-rxch, skb, skb-data,
-   skb_tailroom(skb), GFP_KERNEL);
+   skb_tailroom(skb), 0, GFP_KERNEL);
}
WARN_ON(ret  0);
 }
@@ -705,7 +705,7 @@ static int cpsw_ndo_open(struct net_device *ndev)
if (!skb)
break;
ret = cpdma_chan_submit(priv-rxch, skb, skb-data,
-   skb_tailroom(skb), GFP_KERNEL);
+   skb_tailroom(skb), 0, GFP_KERNEL);
if (WARN_ON(ret  0))
break;
}
@@ -766,7 +766,7 @@ static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
skb_tx_timestamp(skb);
 
ret = cpdma_chan_submit(priv-txch, skb, skb-data,
-   skb-len, GFP_KERNEL);
+   skb-len, 0, GFP_KERNEL);
if (unlikely(ret != 0)) {
cpsw_err(priv, tx_err, desc submit failed\n);
goto fail;
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c 
b/drivers/net/ethernet/ti/davinci_cpdma.c
index afe14a6..ca25cc8 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -60,6 +60,9 @@
 #define CPDMA_DESC_EOQ BIT(28)
 #define CPDMA_DESC_TD_COMPLETE BIT(27)
 #define CPDMA_DESC_PASS_CRCBIT(26)
+#define CPDMA_DESC_TO_PORT_EN  BIT(20)
+#define CPDMA_TO_PORT_SHIFT16
+#define CPDMA_DESC_PORT_MASK   (BIT(18) | BIT(17) | BIT(16))
 
 #define CPDMA_TEARDOWN_VALUE   0xfffc
 
@@ -132,6 +135,14 @@ struct cpdma_chan {
 #define chan_write(chan, fld, v)   __raw_writel(v, (chan)-fld)
 #define desc_write(desc, fld, v)   __raw_writel((u32)(v), (desc)-fld)
 
+#define cpdma_desc_to_port(chan, mode, directed)   \
+   do {\
+   if (!is_rx_chan(chan)  ((directed == 1) ||\
+ (directed == 2))) \
+   mode |= (CPDMA_DESC_TO_PORT_EN |\
+(directed  CPDMA_TO_PORT_SHIFT));\
+   } while (0)
+
 /*
  * Utility constructs for a cpdma descriptor pool.  Some devices (e.g. davinci
  * emac) have dedicated on-chip memory for these descriptors.  Some other
@@ -664,7 +675,7 @@ static void __cpdma_chan_submit(struct cpdma_chan *chan,
 }
 
 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
- int len, gfp_t gfp_mask)
+ int len, int directed, gfp_t gfp_mask)
 {
struct cpdma_ctlr   *ctlr = chan-ctlr;
struct cpdma_desc __iomem   *desc;
@@ -694,6 +705,7 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, 
void *data,
 
buffer = dma_map_single(ctlr-dev, data, len, chan-dir);
mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+   cpdma_desc_to_port(chan, mode, directed);
 
desc_write(desc, hw_next,   0);
desc_write(desc, hw_buffer, buffer);
@@ -784,7 +796,8 @@ static int __cpdma_chan_process(struct cpdma_chan *chan)
status = -EBUSY;
goto unlock_ret;
}
-   status  = status  (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE);
+   status  = status  (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
+   CPDMA_DESC_PORT_MASK);
 
chan-head = desc_from_phys(pool, desc_read(desc, hw_next));
chan_write(chan, cp, desc_dma);
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h 
b/drivers/net/ethernet/ti/davinci_cpdma.h
index 8d2aeb2..a97d6ab 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.h
+++ b/drivers/net/ethernet/ti/davinci_cpdma.h
@@ -24,6 +24,8 @@
 #define __chan_linear(chan_num)((chan_num)  (CPDMA_MAX_CHANNELS - 1))
 #define chan_linear(chan)  __chan_linear((chan)-chan_num)
 
+#define CPDMA_RX_SOURCE_PORT(__status__)   ((__status__  16)  0x7)
+
 struct cpdma_params {
struct device   *dev;
void __iomem*dmaregs;
@@ -82,7 +84,7 @@ int cpdma_chan_dump(struct cpdma_chan *chan

[PATCH v4 0/2] Add CPSW VLAN Support

2013-02-05 Thread Mugunthan V N

CPSW is capable of filtering VLAN packets in hardware. This patch series
implements VLAN support to CPSW driver.
This patch series is tested on net-next with AM335x EVM with ping test.

Changes from initial version
* added vlan support to existing add/delete unicast/multicast apis
* Made driver as default VLAN enabled so that drivers need to be recompiled
  when stack is compiled with VLAN

Changes from V2
* Moved repeated code to static inline function
* Made vlan add/delete function return type to void as it is not used in
  the current driver implementation
* Modified cpsw_add_default_vlan for better readability
* changed BIT(1) port representation to defines

Changes from V3
* Dropped default VLAN id passing from DT, will find a way to pass it through
  ethtool or similar interface and submit the patch.

Mugunthan V N (2):
  drivers: net: cpsw: Add helper functions for VLAN ALE implementation
  drivers: net:ethernet: cpsw: add support for VLAN

 drivers/net/ethernet/ti/cpsw.c |  114 ++--
 drivers/net/ethernet/ti/cpsw_ale.c |  107 +
 drivers/net/ethernet/ti/cpsw_ale.h |   24 ++--
 include/linux/platform_data/cpsw.h |1 +
 4 files changed, 222 insertions(+), 24 deletions(-)

-- 
1.7.9.5

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[PATCH v4 2/2] drivers: net:ethernet: cpsw: add support for VLAN

2013-02-05 Thread Mugunthan V N

adding support for VLAN interface for cpsw.

CPSW VLAN Capability
* Can filter VLAN packets in Hardware

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |  106 +++-
 drivers/net/ethernet/ti/cpsw_ale.h |4 ++
 include/linux/platform_data/cpsw.h |1 +
 3 files changed, 109 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 534bf7b..888708c 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -32,6 +32,7 @@
 #include linux/of.h
 #include linux/of_net.h
 #include linux/of_device.h
+#include linux/if_vlan.h
 
 #include linux/platform_data/cpsw.h
 
@@ -118,6 +119,9 @@ do {
\
 #define TX_PRIORITY_MAPPING0x33221100
 #define CPDMA_TX_PRIORITY_MAP  0x76543210
 
+#define CPSW_VLAN_AWAREBIT(1)
+#define CPSW_ALE_VLAN_AWARE1
+
 #define cpsw_enable_irq(priv)  \
do {\
u32 i;  \
@@ -607,14 +611,40 @@ static void cpsw_slave_open(struct cpsw_slave *slave, 
struct cpsw_priv *priv)
}
 }
 
+static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
+{
+   const int vlan = priv-data.default_vlan;
+   const int port = priv-host_port;
+   u32 reg;
+   int i;
+
+   reg = (priv-version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
+  CPSW2_PORT_VLAN;
+
+   writel(vlan, priv-host_port_regs-port_vlan);
+
+   for (i = 0; i  2; i++)
+   slave_write(priv-slaves + i, vlan, reg);
+
+   cpsw_ale_add_vlan(priv-ale, vlan, ALE_ALL_PORTS  port,
+ ALE_ALL_PORTS  port, ALE_ALL_PORTS  port,
+ (ALE_PORT_1 | ALE_PORT_2)  port);
+}
+
 static void cpsw_init_host_port(struct cpsw_priv *priv)
 {
+   u32 control_reg;
+
/* soft reset the controller and initialize ale */
soft_reset(cpsw, priv-regs-soft_reset);
cpsw_ale_start(priv-ale);
 
/* switch to vlan unaware mode */
-   cpsw_ale_control_set(priv-ale, 0, ALE_VLAN_AWARE, 0);
+   cpsw_ale_control_set(priv-ale, priv-host_port, ALE_VLAN_AWARE,
+CPSW_ALE_VLAN_AWARE);
+   control_reg = readl(priv-regs-control);
+   control_reg |= CPSW_VLAN_AWARE;
+   writel(control_reg, priv-regs-control);
 
/* setup host port priority mapping */
__raw_writel(CPDMA_TX_PRIORITY_MAP,
@@ -650,6 +680,9 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpsw_init_host_port(priv);
for_each_slave(priv, cpsw_slave_open, priv);
 
+   /* Add default VLAN */
+   cpsw_add_default_vlan(priv);
+
/* setup tx dma to fixed prio and zero offset */
cpdma_control_set(priv-dma, CPDMA_TX_PRIO_FIXED, 1);
cpdma_control_set(priv-dma, CPDMA_RX_BUFFER_OFFSET, 0);
@@ -933,6 +966,73 @@ static void cpsw_ndo_poll_controller(struct net_device 
*ndev)
 }
 #endif
 
+static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
+   unsigned short vid)
+{
+   int ret;
+
+   ret = cpsw_ale_add_vlan(priv-ale, vid,
+   ALE_ALL_PORTS  priv-host_port,
+   0, ALE_ALL_PORTS  priv-host_port,
+   (ALE_PORT_1 | ALE_PORT_2)  priv-host_port);
+   if (ret != 0)
+   return ret;
+
+   ret = cpsw_ale_add_ucast(priv-ale, priv-mac_addr,
+priv-host_port, ALE_VLAN, vid);
+   if (ret != 0)
+   goto clean_vid;
+
+   ret = cpsw_ale_add_mcast(priv-ale, priv-ndev-broadcast,
+ALE_ALL_PORTS  priv-host_port,
+ALE_VLAN, vid, 0);
+   if (ret != 0)
+   goto clean_vlan_ucast;
+   return 0;
+
+clean_vlan_ucast:
+   cpsw_ale_del_ucast(priv-ale, priv-mac_addr,
+   priv-host_port, ALE_VLAN, vid);
+clean_vid:
+   cpsw_ale_del_vlan(priv-ale, vid, 0);
+   return ret;
+}
+
+static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
+   unsigned short vid)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+
+   if (vid == priv-data.default_vlan)
+   return 0;
+
+   dev_info(priv-dev, Adding vlanid %d to vlan filter\n, vid);
+   return cpsw_add_vlan_ale_entry(priv, vid);
+}
+
+static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
+   unsigned short vid)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+   int ret;
+
+   if (vid == priv-data.default_vlan)
+   return 0;
+
+   dev_info(priv-dev, removing vlanid %d from vlan filter\n, vid);
+   ret = cpsw_ale_del_vlan(priv-ale, vid, 0);
+   if (ret != 0)
+   return ret;
+
+   ret = cpsw_ale_del_ucast(priv-ale, priv-mac_addr,
+priv

[PATCH v4 1/2] drivers: net: cpsw: Add helper functions for VLAN ALE implementation

2013-02-05 Thread Mugunthan V N

Add helper functions for VLAN ALE implementations for Add, Delete
Dump VLAN related ALE entries

Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
 drivers/net/ethernet/ti/cpsw.c |8 +--
 drivers/net/ethernet/ti/cpsw_ale.c |  107 
 drivers/net/ethernet/ti/cpsw_ale.h |   20 +--
 3 files changed, 113 insertions(+), 22 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 9e63bff..534bf7b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -345,7 +345,7 @@ static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
/* program multicast address list into ALE register */
netdev_for_each_mc_addr(ha, ndev) {
cpsw_ale_add_mcast(priv-ale, (u8 *)ha-addr,
-   ALE_ALL_PORTS  priv-host_port, 0, 0);
+   ALE_ALL_PORTS  priv-host_port, 0, 0, 0);
}
}
 }
@@ -592,7 +592,7 @@ static void cpsw_slave_open(struct cpsw_slave *slave, 
struct cpsw_priv *priv)
slave_port = cpsw_get_slave_port(priv, slave-slave_num);
 
cpsw_ale_add_mcast(priv-ale, priv-ndev-broadcast,
-  1  slave_port, 0, ALE_MCAST_FWD_2);
+  1  slave_port, 0, 0, ALE_MCAST_FWD_2);
 
slave-phy = phy_connect(priv-ndev, slave-data-phy_id,
 cpsw_adjust_link, slave-data-phy_if);
@@ -624,9 +624,9 @@ static void cpsw_init_host_port(struct cpsw_priv *priv)
cpsw_ale_control_set(priv-ale, priv-host_port,
 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 
-   cpsw_ale_add_ucast(priv-ale, priv-mac_addr, priv-host_port, 0);
+   cpsw_ale_add_ucast(priv-ale, priv-mac_addr, priv-host_port, 0, 0);
cpsw_ale_add_mcast(priv-ale, priv-ndev-broadcast,
-  1  priv-host_port, 0, ALE_MCAST_FWD_2);
+  1  priv-host_port, 0, 0, ALE_MCAST_FWD_2);
 }
 
 static int cpsw_ndo_open(struct net_device *ndev)
diff --git a/drivers/net/ethernet/ti/cpsw_ale.c 
b/drivers/net/ethernet/ti/cpsw_ale.c
index 0e9ccc2..7fa60d6 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c
@@ -148,7 +148,7 @@ static int cpsw_ale_write(struct cpsw_ale *ale, int idx, 
u32 *ale_entry)
return idx;
 }
 
-static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr)
+int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr, u16 vid)
 {
u32 ale_entry[ALE_ENTRY_WORDS];
int type, idx;
@@ -160,6 +160,8 @@ static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 
*addr)
type = cpsw_ale_get_entry_type(ale_entry);
if (type != ALE_TYPE_ADDR  type != ALE_TYPE_VLAN_ADDR)
continue;
+   if (cpsw_ale_get_vlan_id(ale_entry) != vid)
+   continue;
cpsw_ale_get_addr(ale_entry, entry_addr);
if (memcmp(entry_addr, addr, 6) == 0)
return idx;
@@ -167,6 +169,22 @@ static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 
*addr)
return -ENOENT;
 }
 
+int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
+{
+   u32 ale_entry[ALE_ENTRY_WORDS];
+   int type, idx;
+
+   for (idx = 0; idx  ale-params.ale_entries; idx++) {
+   cpsw_ale_read(ale, idx, ale_entry);
+   type = cpsw_ale_get_entry_type(ale_entry);
+   if (type != ALE_TYPE_VLAN)
+   continue;
+   if (cpsw_ale_get_vlan_id(ale_entry) == vid)
+   return idx;
+   }
+   return -ENOENT;
+}
+
 static int cpsw_ale_match_free(struct cpsw_ale *ale)
 {
u32 ale_entry[ALE_ENTRY_WORDS];
@@ -274,19 +292,32 @@ int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
return 0;
 }
 
-int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)
+static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
+   int flags, u16 vid)
+{
+   if (flags  ALE_VLAN) {
+   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
+   cpsw_ale_set_vlan_id(ale_entry, vid);
+   } else {
+   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+   }
+}
+
+int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
+  int flags, u16 vid)
 {
u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
int idx;
 
-   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+   cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
+
cpsw_ale_set_addr(ale_entry, addr);
cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
cpsw_ale_set_secure(ale_entry, (flags  ALE_SECURE) ? 1 : 0);
cpsw_ale_set_blocked(ale_entry, (flags  ALE_BLOCKED) ? 1 : 0);
cpsw_ale_set_port_num(ale_entry, port

Re: [PATCH 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-01-31 Thread Mugunthan V N


On 1/31/2013 1:33 AM, Koen Kooi wrote:

Op 30 jan. 2013, om 20:56 heeft Mugunthan V N mugunthan...@ti.com het 
volgende geschreven:


CPDMA interrupts are not properly acknowledged which leads to interrupt
storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
used for rx and tx respectively.

A brief inspection shows that this still isn't following the TRM, but Pantelis' 
patch does. Can you please fix this driver to follow the TRM and make it work 
on both PG1.0 and PG2.0 instead of papering over bugs instead of fixing them 
properly?
Existing driver implementation is also complies with TRM. What Pantelis 
added

additionally are non-napi implementation, handled cpdma processed tx and rx
processing separately and renamed wr_reg as per TRM naming convention.. 
Also he
has added a dummy reading tx/rx stat which is mentioned in TRM, but this 
stat
is required only when using multichannel for data transfer. Current 
implementation
of CPSW driver uses only channel 0 of Tx and Rx channels respectively 
for transmission

and reading stat doesn't gets any effect in interrupt acknowledgment.

Since both tx and rx are processed in same napi api, so i have added 
interrupt

acknowledgment to the same existing api.

Regards
Mugunthan V N
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Re: [PATCH v2 1/2] drivers: net: cpsw: Add helper functions for VLAN ALE implementation

2013-01-31 Thread Mugunthan V N


On 1/31/2013 3:32 AM, Francois Romieu wrote:

Mugunthan V N mugunthan...@ti.com :
[...]

diff --git a/drivers/net/ethernet/ti/cpsw_ale.c 
b/drivers/net/ethernet/ti/cpsw_ale.c
index 0e9ccc2..18b88ce 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c

[...]

@@ -274,19 +292,26 @@ int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
return 0;
  }
  
-int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)

+int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
+  int flags, u16 vid)
  {
u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
int idx;
  
-	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);

+   if (flags  ALE_VLAN) {
+   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
+   cpsw_ale_set_vlan_id(ale_entry, vid);
+   } else {
+   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+   }
+

[...]

+   if (flags  ALE_VLAN) {
+   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
+   cpsw_ale_set_vlan_id(ale_entry, vid);
+   } else {
+   cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+   }
+

It could be fctored out.
Are you mentioning to have static inline function for the above two 
statements above?


[...]

@@ -362,6 +395,55 @@ int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int 
port_mask)
return 0;
  }
  
+int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,

+ int reg_mcast, int unreg_mcast)
+{

[...]

+int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)

[...]

Patch #2 doesn't use the returned status code.

Will modify the prototype to return void

Regards
Mugunthan V N
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Re: [PATCH v2 2/2] drivers: net:ethernet: cpsw: add support for VLAN

2013-01-31 Thread Mugunthan V N


On 1/31/2013 3:32 AM, Francois Romieu wrote:

Mugunthan V N mugunthan...@ti.com :
[...]

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt 
b/Documentation/devicetree/bindings/net/cpsw.txt
index 6ddd028..99696bf 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -24,6 +24,8 @@ Required properties:
  Optional properties:
  - ti,hwmods   : Must be cpgmac0
  - no_bd_ram   : Must be 0 or 1
+- default_vlan : Specifies Default VLAN for non tagged packets
+ ALE processing

Isn't it a device-tree hack for what should belong to a common API ?
Its a hardware feature which stack will not be aware of. It is used in 
the ALE filtering

process with a non-tagged packet arrives.


[...]

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index a40750e..6c66f01 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c

[...]

@@ -607,14 +611,41 @@ static void cpsw_slave_open(struct cpsw_slave *slave, 
struct cpsw_priv *priv)
}
  }
  
+static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)

+{
+   writel(priv-data.default_vlan, priv-host_port_regs-port_vlan);
+   if (priv-version == CPSW_VERSION_1) {
+   slave_write(priv-slaves[0], priv-data.default_vlan,
+   CPSW1_PORT_VLAN);
+   slave_write(priv-slaves[1], priv-data.default_vlan,
+   CPSW1_PORT_VLAN);
+   } else {
+   slave_write(priv-slaves[0], priv-data.default_vlan,
+   CPSW2_PORT_VLAN);
+   slave_write(priv-slaves[1], priv-data.default_vlan,
+   CPSW2_PORT_VLAN);
+   }
+   cpsw_ale_add_vlan(priv-ale, priv-data.default_vlan,
+   ALE_ALL_PORTS  priv-host_port,
+   ALE_ALL_PORTS  priv-host_port,
+   ALE_ALL_PORTS  priv-host_port,
+   (BIT(1) | BIT(2))  priv-host_port);
+}

static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
{
const int vlan = priv-data.default_vlan;
const int port = priv-host_port;
u32 reg;
int i;

reg = (priv-version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
  CPSW2_PORT_VLAN;

writel(vlan, priv-host_port_regs-port_vlan);

for (int i = 0; i  2; i++)
slave_write(priv-slaves + i, vlan, reg);

cpsw_ale_add_vlan(priv-ale, vlan, ALE_ALL_PORTS  port,
  ALE_ALL_PORTS  port, ALE_ALL_PORTS  port,
  (BIT(1) | BIT(2))  port);
}

... or somewhere between both. Your call.

Will modify the code as this looks simpler


[...]

@@ -933,6 +967,55 @@ static void cpsw_ndo_poll_controller(struct net_device 
*ndev)
  }
  #endif
  
+static inline void cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,

+   unsigned short vid)
+{
+   cpsw_ale_add_vlan(priv-ale, vid, ALE_ALL_PORTS  priv-host_port,
+   0, ALE_ALL_PORTS  priv-host_port,
+   (BIT(1) | BIT(2))  priv-host_port);

(BIT(1) | BIT(2)) is repeated a couple of times.

Will replace with port number defines.


[...]

+static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
+   unsigned short vid)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+
+   if (vid == priv-data.default_vlan)
+   return 0;
+
+   spin_lock(priv-lock);
+
+   dev_info(priv-dev, Adding vlanid %d to vlan filter\n, vid);
+   cpsw_add_vlan_ale_entry(priv, vid);
+
+   spin_unlock(priv-lock);
+   return 0;
+}
+
+static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
+   unsigned short vid)
+{
+   struct cpsw_priv *priv = netdev_priv(ndev);
+
+   if (vid == priv-data.default_vlan)
+   return 0;
+
+   spin_lock(priv-lock);
+
+   dev_info(priv-dev, removing vlanid %d from vlan filter\n, vid);
+   cpsw_ale_del_vlan(priv-ale, vid, 0);
+   cpsw_ale_del_ucast(priv-ale, priv-mac_addr,
+  priv-host_port, ALE_VLAN, vid);
+   cpsw_ale_del_mcast(priv-ale, priv-ndev-broadcast, 0, ALE_VLAN, vid);
+
+   spin_unlock(priv-lock);

What are you trying to achieve with the lock ?

It is not used anywhere else and both cpsw_ndo_vlan_rx_{add, kill}_vid are
called under RTNL.

Will remove the lock from both apis

Regards
Mugunthan V N
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Re: [PATCH 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly

2013-01-31 Thread Mugunthan V N


Pantelis

On 1/31/2013 4:52 PM, Pantelis Antoniou wrote:

Hi
On Jan 31, 2013, at 12:17 PM, Mugunthan V N wrote:


On 1/31/2013 1:33 AM, Koen Kooi wrote:

Op 30 jan. 2013, om 20:56 heeft Mugunthan V N mugunthan...@ti.com het 
volgende geschreven:


CPDMA interrupts are not properly acknowledged which leads to interrupt
storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
used for rx and tx respectively.

A brief inspection shows that this still isn't following the TRM, but Pantelis' 
patch does. Can you please fix this driver to follow the TRM and make it work 
on both PG1.0 and PG2.0 instead of papering over bugs instead of fixing them 
properly?

Existing driver implementation is also complies with TRM. What Pantelis added
additionally are non-napi implementation, handled cpdma processed tx and rx
processing separately and renamed wr_reg as per TRM naming convention.. Also he
has added a dummy reading tx/rx stat which is mentioned in TRM, but this stat
is required only when using multichannel for data transfer. Current 
implementation
of CPSW driver uses only channel 0 of Tx and Rx channels respectively for 
transmission
and reading stat doesn't gets any effect in interrupt acknowledgment.

Since both tx and rx are processed in same napi api, so i have added interrupt
acknowledgment to the same existing api.



First of all, this method of not needing to read the stat registers besides when
using multichannel for data transfers is never described anywhere in any manual,
or in the driver sources.

Secondly, I find the method of ack-ing all interrupt sources problematic.
Consider the following sequence

Rx-interrupt --- | |
   | IRQ handler |
   | schedules NAPI  |
   | disables interrupts -- | cpsw_poll()
   | | handle Rx
Tx-interrupt --- |-|-
   | | ack Rx  Tx IRQ
   | | enable interrupts

When will the Tx interrupt get handled? Is it guaranteed that the DMA
logic will assert the Tx interrupt when the interrupts are enabled, even
though the interrupt was previously acked? It is not clear in the TRM.
Need to check with the IP owner with this corner case. Simulating this 
will be difficult
because even if driver misses the interrupt in next rx/tx interrupt it 
will be serviced.


Another problem that I see is that the other interrupts (MISC) are not supposed
to be routed to the napi cpsw_poll() function at all. NAPI is for the tx/rx path
as far as I know.

I agree that napi should not be used for MISC interrupts.

Regards
Mugunthan V N




Regards
Mugunthan V N

Regards

-- Pantelis



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