[PATCH 1/2] arm64: dts: r8a77965: add FDP1 device nodes
From: Hoan Nguyen An
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 9c4f405..bef519f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1578,6 +1578,16 @@
status = "disabled";
};
+ fdp1@fe94 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe94 0 0x2400>;
+ interrupts = ;
+ clocks = < CPG_MOD 119>;
+ power-domains = < R8A77965_PD_A3VP>;
+ resets = < 119>;
+ renesas,fcp = <>;
+ };
+
fcpf0: fcp@fe95 {
compatible = "renesas,fcpf";
reg = <0 0xfe95 0 0x200>;
--
2.7.4
[PATCH 0/2] Add support fdp1 device for Salvator-XS M3-N
From: Hoan Nguyen An These patches add fdp1 device support for M3-N r8a77965 board. Please review for me, thank you! Hoan Nguyen An (2): arm64: dts: r8a77965: add FDP1 device nodes clk: renesas: r8a77965: Add FDP clock arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 ++ drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + 2 files changed, 11 insertions(+) -- 2.7.4
[PATCH 2/2] clk: renesas: r8a77965: Add FDP clock
From: Hoan Nguyen An
Signed-off-by: Hoan Nguyen An
---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 312f9fe..d0847dc 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[]
__initconst = {
};
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+ DEF_MOD("fdp0", 119,R8A77965_CLK_S0D1),
DEF_MOD("scif5",202,R8A77965_CLK_S3D4),
DEF_MOD("scif4",203,R8A77965_CLK_S3D4),
DEF_MOD("scif3",204,R8A77965_CLK_S3D4),
--
2.7.4
Re: [PATCH v2 5/7] arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
Hi Eugeniu,
On 23/08/18 18:14, Eugeniu Rosca wrote:
> Dear reviewers,
>
> On Thu, Aug 23, 2018 at 11:01:46AM +0200, Geert Uytterhoeven wrote:
>> Hi Sergei,
>>
>> On Thu, Aug 23, 2018 at 10:56 AM Sergei Shtylyov
>> wrote:
>>> On 8/23/2018 11:52 AM, Geert Uytterhoeven wrote:
>> According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
>> interfaces, similar to H3, M3-W and other SoCs from the same family.
>>
>> Add CAN placeholder nodes to avoid below DTC errors:
>> Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path
>> can0 not found
>> Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path
>> can1 not found
>>
>> These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
>> Fix them beforehand.
>>
>> CAN support is inspired from below commits:
>> - v4.7 commit 308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
>> - v4.11 commit 909c16252415 ("arm64: dts: r8a7796: Add CAN support")
>> - v4.12 commit bec0948e810f ("arm64: dts: r8a7796: Add reset control
>> properties")
>>
>> Signed-off-by: Eugeniu Rosca
>>
>> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> @@ -656,6 +656,22 @@
>>status = "disabled";
>>};
>>
>> + can0: can@e6c3 {
>> + compatible = "renesas,can-r8a77965",
>> + "renesas,rcar-gen3-can";
>> + reg = <0 0xe6c3 0 0x1000>;
>> + /* placeholder */
>> + status = "disabled";
>> + };
>
> This is probably more detail than is needed for a placeholder, but it
> looks correct so I think this is fine.
Indeed. Adding the "compatible" properties means they're no longer
placeholders, and will be probed by the driver, possibly leading to
undefined behavior.
>>>
>>> I don't think the disabled device nodes are actually probed.
>>
>> They will be by ulcb-kf.dtsi, after the addition of
>> r8a77965-m3nulcb-kf.dts, cfr.
>> the errors and rationale documented in the commit message.
>
> I took some time to examine the "52. Controller Area Network Interface
> (CAN interface)" chapter of HW SoC manual rev1.00 in detail and there is
> no difference mentioned between the SoCs (H3, M3-W, M3-N, D3, E3) which
> implement the two CAN (non-FD) interfaces. This is confirmed by the
> perfectly symmetrical can{0,1} configuration present in the H3,
> M3-W and D3 device tree sources:
>
> $ git grep -l can0 -- arch/arm64/boot/dts/renesas/r8*dtsi
> arch/arm64/boot/dts/renesas/r8a7795.dtsi
> arch/arm64/boot/dts/renesas/r8a7796.dtsi
> arch/arm64/boot/dts/renesas/r8a77995.dtsi
The problem is, until it's tested - we don't actually know it works.
Even 'identical' chips can have different changes between the revisions.
> So, to be honest, in my opinion, besides consuming time arguing about
> what a placeholder DTS node is (btw, commits [1] and [2] do include a
> compatible string while adding a "placeholder" node),
[1] is a special case. It's not actually going to probe a driver.
sources/linux$ git grep secure-ram
arch/arm/boot/dts/dra7.dtsi: compatible = "ti,secure-ram";
[2] is also a different case:
You can see in the patch that the 'placeholder' is used in the same
commit by sun9i-a80-cubieboard4.dts and sun9i-a80-optimus.dts
> we also force
> users to 'git blame' multiple times to reconstruct the history of CAN
> controller nodes on M3-N, while for H3, M3-W and D3 a single commit was
> enough to add the functionality.
>
> That said, I don't see any dmesg differences on M3NULCB between having
> and not having the compatible string in the can{0,1} nodes.
>
>> Hence please limit the placeholders to the absolute required minimum,
>> and thus drop the "compatible" and "status" properties.
>
> My understanding is that the lack of status is equivalent with
> 'status = "okay"' (i.e. enable the node), so I don't really see why
> 'status = "disabled"' should hurt for a placeholder, especially seeing
> a high number of commits [3] using 'status = "disabled"' by default.
It's not so much the 'status' field that hurts in this patch, but the
compatible matching.
The file r8a7795.dtsi is a SoC level description. It tries to describe
all the features provided by that SoC. But all of those features may not
be brought out on the "board", and so many are disabled by default.
- Essentially 'status = "disabled";'
is like saying - This node is good - but don't use it.
It's then up to the board file (Salvator-XS.dtb, ULCB.dtb
YourBoardHere.dtb ...) to enable the features that are available.
That's the case here in the KingFisher board.
The ulcb-kf.dtsi will override the CAN nodes and set 'status = Okay' to
enable the devices available on the KF board:
> {
>
Re: [PATCH v2 5/7] arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
Dear reviewers,
On Thu, Aug 23, 2018 at 11:01:46AM +0200, Geert Uytterhoeven wrote:
> Hi Sergei,
>
> On Thu, Aug 23, 2018 at 10:56 AM Sergei Shtylyov
> wrote:
> > On 8/23/2018 11:52 AM, Geert Uytterhoeven wrote:
> > >>> According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
> > >>> interfaces, similar to H3, M3-W and other SoCs from the same family.
> > >>>
> > >>> Add CAN placeholder nodes to avoid below DTC errors:
> > >>> Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path
> > >>> can0 not found
> > >>> Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path
> > >>> can1 not found
> > >>>
> > >>> These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
> > >>> Fix them beforehand.
> > >>>
> > >>> CAN support is inspired from below commits:
> > >>> - v4.7 commit 308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
> > >>> - v4.11 commit 909c16252415 ("arm64: dts: r8a7796: Add CAN support")
> > >>> - v4.12 commit bec0948e810f ("arm64: dts: r8a7796: Add reset control
> > >>> properties")
> > >>>
> > >>> Signed-off-by: Eugeniu Rosca
>
> > >>> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> > >>> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> > >>> @@ -656,6 +656,22 @@
> > >>>status = "disabled";
> > >>>};
> > >>>
> > >>> + can0: can@e6c3 {
> > >>> + compatible = "renesas,can-r8a77965",
> > >>> + "renesas,rcar-gen3-can";
> > >>> + reg = <0 0xe6c3 0 0x1000>;
> > >>> + /* placeholder */
> > >>> + status = "disabled";
> > >>> + };
> > >>
> > >> This is probably more detail than is needed for a placeholder, but it
> > >> looks correct so I think this is fine.
> > >
> > > Indeed. Adding the "compatible" properties means they're no longer
> > > placeholders, and will be probed by the driver, possibly leading to
> > > undefined behavior.
> >
> > I don't think the disabled device nodes are actually probed.
>
> They will be by ulcb-kf.dtsi, after the addition of
> r8a77965-m3nulcb-kf.dts, cfr.
> the errors and rationale documented in the commit message.
I took some time to examine the "52. Controller Area Network Interface
(CAN interface)" chapter of HW SoC manual rev1.00 in detail and there is
no difference mentioned between the SoCs (H3, M3-W, M3-N, D3, E3) which
implement the two CAN (non-FD) interfaces. This is confirmed by the
perfectly symmetrical can{0,1} configuration present in the H3,
M3-W and D3 device tree sources:
$ git grep -l can0 -- arch/arm64/boot/dts/renesas/r8*dtsi
arch/arm64/boot/dts/renesas/r8a7795.dtsi
arch/arm64/boot/dts/renesas/r8a7796.dtsi
arch/arm64/boot/dts/renesas/r8a77995.dtsi
So, to be honest, in my opinion, besides consuming time arguing about
what a placeholder DTS node is (btw, commits [1] and [2] do include a
compatible string while adding a "placeholder" node), we also force
users to 'git blame' multiple times to reconstruct the history of CAN
controller nodes on M3-N, while for H3, M3-W and D3 a single commit was
enough to add the functionality.
That said, I don't see any dmesg differences on M3NULCB between having
and not having the compatible string in the can{0,1} nodes.
> Hence please limit the placeholders to the absolute required minimum,
> and thus drop the "compatible" and "status" properties.
My understanding is that the lack of status is equivalent with
'status = "okay"' (i.e. enable the node), so I don't really see why
'status = "disabled"' should hurt for a placeholder, especially seeing
a high number of commits [3] using 'status = "disabled"' by default. At
least I ask for an explanation regarding this last part before
incrementing the version of this patch. TIA.
[1] fae3a9f023b7 ("ARM: dts: dra7: Add ti,secure-ram node to ocmcram1 node")
[2] 162669876bbe ("ARM: dts: sun9i: Switch to the AC100 RTC clock outputs for
osc32k")
[3] git blame arch/arm64/boot/dts/renesas/r8a7795.dtsi | grep disabled | awk
'{print $1}' | sort -u | wc -l
22
>
> Gr{oetje,eeting}s,
>
> Geert
Thanks,
Eugeniu.
[PATCH v4] arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support
Define the Condor/V3HSK board dependent parts of the DU and LVDS device
nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
Analog Devices ADV7511W HDMI transmitter...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
Reviewed-by: Ulrich Hecht
Reviewed-by: Laurent Pinchart
---
The patch is against the 'renesas-devel-20180822-v4.18' tag of Simon Horman's
'renesas.git' repo. The only driver support still unmerged seems to be the
R8A77980 LVDS support patches...
Changes in version 4:
- added the OSC1 clock node and a reference to it from the DU device node in
the V3HSK board DT;
- added Ulrich's and Laurent's tags.
Changes in version 2:
- added the V3HSK DT update, reworded the description, renamed the patch;
- added a space between the HDMI node name and a brace.
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 106 +++
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 129
2 files changed, 235 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -45,6 +45,56 @@
regulator-boot-on;
regulator-always-on;
};
+
+ d1_8v: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "D1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <_3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <_in>;
+ };
+ };
+ };
+ };
+
+ x1_clk: x1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <14850>;
+ };
};
{
@@ -74,6 +124,13 @@
};
};
+ {
+ clocks = < CPG_MOD 724>,
+<_clk>;
+ clock-names = "du.0", "dclkin.0";
+ status = "okay";
+};
+
_clk {
clock-frequency = <1666>;
};
@@ -102,6 +159,55 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <_8v>;
+ dvdd-supply = <_8v>;
+ pvdd-supply = <_8v>;
+ bgvdd-supply = <_8v>;
+ dvdd-3v-supply = <_3v>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <_in>;
+ };
+ };
+ };
};
{
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===
---
Re: [PATCH v3 2/2] arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support
On 08/22/2018 12:55 PM, Simon Horman wrote: >>> Define the Condor/V3HSK board dependent parts of the DU and LVDS device >>> nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and >>> Analog Devices ADV7511W HDMI transmitter... >>> >>> Based on the original (and large) patch by Vladimir Barinov. >>> >>> Signed-off-by: Vladimir Barinov >>> Signed-off-by: Sergei Shtylyov >>> >>> --- >>> Changes in version 2: >>> - added the V3HSK DT update, reworded the description, renamed the patch; >>> - added a space between the HDMI node name and a brace. >>> >>> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 106 >>> arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 120 >>> 2 files changed, 226 insertions(+) >> >> I would have split that in two patchees. > > I take your point but I think one is fine. Yeah, one patch here fits Arnd's criterion. :-) > Sergei, will you address the other review items? Done, about to repost... MBR, Sergei
[PATCH] arm64: dts: renesas: r8a774a1: Add CAN nodes
From: Chris Paterson
Add the device nodes for both RZ/G2M CAN channels.
Signed-off-by: Chris Paterson
Reviewed-by: Biju Das
---
This patch depends on:
https://lkml.org/lkml/2018/8/23/1049
https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg30550.html
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 5d0109a..cd204f5 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -816,6 +816,30 @@
status = "disabled";
};
+ can0: can@e6c3 {
+ compatible = "renesas,can-r8a774a1",
+"renesas,rzg-gen2-can";
+ reg = <0 0xe6c3 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 916>, <_clk>;
+ clock-names = "clkp1", "can_clk";
+ power-domains = < 32>;
+ resets = < 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6c38000 {
+ compatible = "renesas,can-r8a774a1",
+"renesas,rzg-gen2-can";
+ reg = <0 0xe6c38000 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 915>, <_clk>;
+ clock-names = "clkp1", "can_clk";
+ power-domains = < 32>;
+ resets = < 915>;
+ status = "disabled";
+ };
+
pwm0: pwm@e6e3 {
compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
reg = <0 0xe6e3 0 0x8>;
--
2.7.4
[PATCH] arm64: dts: renesas: r8a774a1: Add GPIO device nodes
Add GPIO device nodes to the DT of the r8a774a1 SoC.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
This patch depends on:
https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg30549.html
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b9d2da4..5d0109a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -200,6 +200,126 @@
status = "disabled";
};
+ gpio0: gpio@e605 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe605 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 0 16>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 912>;
+ power-domains = < 32>;
+ resets = < 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 32 29>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 911>;
+ power-domains = < 32>;
+ resets = < 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 64 15>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 910>;
+ power-domains = < 32>;
+ resets = < 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 96 16>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 909>;
+ power-domains = < 32>;
+ resets = < 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 128 18>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 908>;
+ power-domains = < 32>;
+ resets = < 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 160 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 907>;
+ power-domains = < 32>;
+ resets = < 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
[PATCH] arm64: dts: renesas: r8a774a1: Add pinctrl device node
This patch adds pinctrl device node for R8A774A1 SoC.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
This patch depends on:
https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg30339.html
https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg30539.html
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 5b2ee60..b9d2da4 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -200,6 +200,11 @@
status = "disabled";
};
+ pfc: pin-controller@e606 {
+ compatible = "renesas,pfc-r8a774a1";
+ reg = <0 0xe606 0 0x50c>;
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a774a1-cpg-mssr";
reg = <0 0xe615 0 0x0bb0>;
--
2.7.4
[PATCH 9/9] arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commits 41dbbf0c5 ("arm64: dts:
r8a7796: Add FCPF and FCPV instances"), 69490bc96 ("arm64: dts:
renesas: r8a7796: Point FDP1 via FCPF to IPMMU-VI0"), and cef942d0b
("arm64: dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 52 +++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index f23bbfd..5b2ee60 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1260,6 +1260,58 @@
resets = < 408>;
};
+ fcpf0: fcp@fe95 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe95 0 0x200>;
+ clocks = < CPG_MOD 615>;
+ power-domains = < 14>;
+ resets = < 615>;
+ };
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = < CPG_MOD 607>;
+ power-domains = < 14>;
+ resets = < 607>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = < CPG_MOD 603>;
+ power-domains = < 32>;
+ resets = < 603>;
+ iommus = <_vi0 8>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = < CPG_MOD 602>;
+ power-domains = < 32>;
+ resets = < 602>;
+ iommus = <_vi0 9>;
+ };
+
+ fcpvd2: fcp@fea37000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea37000 0 0x200>;
+ clocks = < CPG_MOD 601>;
+ power-domains = < 32>;
+ resets = < 601>;
+ iommus = <_vi0 10>;
+ };
+
+ fcpvi0: fcp@fe9af000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9af000 0 0x200>;
+ clocks = < CPG_MOD 611>;
+ power-domains = < 14>;
+ resets = < 611>;
+ iommus = <_vc0 19>;
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
--
2.7.4
[PATCH 7/9] arm64: dts: renesas: r8a774a1: Add PWM device nodes
This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
device tree.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 70 +++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1d847cf..34537ba 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -691,6 +691,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e3 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e3 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = < CPG_MOD 523>;
+ resets = < 523>;
+ power-domains = < 32>;
+ status = "disabled";
+ };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a774a1",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.7.4
[PATCH 8/9] arm64: dts: renesas: r8a774a1: Add audio support
From: Biju Das
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).
This work is based on similar work done on the R8A7796 SoC
by Kuninori Morimoto .
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 275 ++
1 file changed, 275 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 34537ba..f23bbfd 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -920,6 +920,281 @@
status = "disabled";
};
+ rcar_sound: sound@ec50 {
+ /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+ /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout : #clock-cells = <0>; <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>; <_sound N>;
+*/
+ compatible = "renesas,rcar_sound-r8a774a1",
"renesas,rcar_sound-gen3";
+ reg = <0 0xec50 0 0x1000>, /* SCU */
+ <0 0xec5a 0 0x100>, /* ADG */
+ <0 0xec54 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec74 0 0x200>; /* Audio DMAC peri
peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>,
+<_clk_c>,
+< CPG_CORE 10>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = < 32>;
+ resets = < 1005>,
+< 1006>, < 1007>,
+< 1008>, < 1009>,
+< 1010>, < 1011>,
+< 1012>, < 1013>,
+< 1014>, < 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = < 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = < 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+
[PATCH 6/9] arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
From: Biju Das
This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.
Based on work done for r8a7796 SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 66 ---
1 file changed, 61 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 856bd37..1d847cf 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -79,12 +79,59 @@
clocks =< CPG_CORE 0>;
};
+ a53_0: cpu@100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = < 5>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ clocks =< CPG_CORE 1>;
+ };
+
+ a53_1: cpu@101 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = < 6>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ clocks =< CPG_CORE 1>;
+ };
+
+ a53_2: cpu@102 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = < 7>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ clocks =< CPG_CORE 1>;
+ };
+
+ a53_3: cpu@103 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = < 8>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ clocks =< CPG_CORE 1>;
+ };
+
L2_CA57: cache-controller-0 {
compatible = "cache";
power-domains = < 12>;
cache-unified;
cache-level = <2>;
};
+
+ L2_CA53: cache-controller-1 {
+ compatible = "cache";
+ power-domains = < 21>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
extal_clk: extal {
@@ -108,6 +155,15 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <_0>, <_1>, <_2>, <_3>;
+ };
+
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -852,7 +908,7 @@
<0x0 0xf104 0 0x2>,
<0x0 0xf106 0 0x2>;
interrupts = ;
+ (GIC_CPU_MASK_SIMPLE(6) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = < CPG_MOD 408>;
clock-names = "clk";
power-domains = < 32>;
@@ -912,10 +968,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6)
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6)
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6)
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6)
| IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clocks - can be overridden by the
[PATCH 5/9] arm64: dts: renesas: r8a774a1: Add all MSIOF nodes
From: Biju Das
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.
Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven
and Simon Horman .
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 62 +++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index d2bb82b..856bd37 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -732,6 +732,68 @@
status = "disabled";
};
+ msiof0: spi@e6e9 {
+ compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e9 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 211>;
+ dmas = < 0x41>, < 0x40>,
+ < 0x41>, < 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < 32>;
+ resets = < 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea {
+ compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 210>;
+ dmas = < 0x43>, < 0x42>,
+ < 0x43>, < 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < 32>;
+ resets = < 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c0 {
+ compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c0 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 209>;
+ dmas = < 0x45>, < 0x44>;
+ dma-names = "tx", "rx";
+ power-domains = < 32>;
+ resets = < 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c1 {
+ compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c1 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 208>;
+ dmas = < 0x47>, < 0x46>;
+ dma-names = "tx", "rx";
+ power-domains = < 32>;
+ resets = < 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: sd@ee10 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
--
2.7.4
[PATCH 4/9] arm64: dts: renesas: r8a774a1: Add IPMMU device nodes
Add r8a774a1 IPMMU nodes.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73 +++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 9f42b7c..d2bb82b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -517,6 +517,79 @@
dma-channels = <16>;
};
+ ipmmu_ds0: mmu@e674 {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xe674 0 0x1000>;
+ renesas,ipmmu-main = <_mm 0>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ds1: mmu@e774 {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xe774 0 0x1000>;
+ renesas,ipmmu-main = <_mm 1>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_hc: mmu@e657 {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xe657 0 0x1000>;
+ renesas,ipmmu-main = <_mm 2>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: mmu@e67b {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xe67b 0 0x1000>;
+ interrupts = ,
+;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mp: mmu@ec67 {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xec67 0 0x1000>;
+ renesas,ipmmu-main = <_mm 4>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_pv0: mmu@fd80 {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xfd80 0 0x1000>;
+ renesas,ipmmu-main = <_mm 5>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_pv1: mmu@fd95 {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xfd95 0 0x1000>;
+ renesas,ipmmu-main = <_mm 6>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: mmu@fe6b {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xfe6b 0 0x1000>;
+ renesas,ipmmu-main = <_mm 8>;
+ power-domains = < 14>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: mmu@febd {
+ compatible = "renesas,ipmmu-r8a774a1";
+ reg = <0 0xfebd 0 0x1000>;
+ renesas,ipmmu-main = <_mm 9>;
+ power-domains = < 32>;
+ #iommu-cells = <1>;
+ };
+
avb: ethernet@e680 {
compatible = "renesas,etheravb-r8a774a1",
"renesas,etheravb-rcar-gen3";
--
2.7.4
[PATCH 3/9] arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support
From: Biju Das
Add thermal support for R8A774A1 (RZ/G2M) SoC.
Based on the work done for r8a7796 SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 60 +++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 5775451..9f42b7c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -165,6 +165,21 @@
#power-domain-cells = <1>;
};
+ tsc: thermal@e6198000 {
+ compatible = "renesas,r8a774a1-thermal";
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a 0 0x100>,
+ <0 0xe61a8000 0 0x100>;
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 522>;
+ power-domains = < 32>;
+ resets = < 522>;
+ #thermal-sensor-cells = <1>;
+ status = "okay";
+ };
+
intc_ex: interrupt-controller@e61c {
compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
#interrupt-cells = <2>;
@@ -715,6 +730,51 @@
};
};
+ thermal-zones {
+ sensor_thermal1: sensor-thermal1 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = < 0>;
+
+ trips {
+ sensor1_crit: sensor1-crit {
+ temperature = <12>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ sensor_thermal2: sensor-thermal2 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = < 1>;
+
+ trips {
+ sensor2_crit: sensor2-crit {
+ temperature = <12>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ };
+
+ sensor_thermal3: sensor-thermal3 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = < 2>;
+
+ trips {
+ sensor3_crit: sensor3-crit {
+ temperature = <12>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
--
2.7.4
[PATCH 1/9] arm64: dts: renesas: r8a774a1: Add SDHI nodes
Add SDHI nodes to the DT of the r8a774a1 SoC.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b9a3818..7640856 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -502,6 +502,54 @@
status = "disabled";
};
+ sdhi0: sd@ee10 {
+ compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+ reg = <0 0xee10 0 0x2000>;
+ interrupts = ;
+ clocks = < CPG_MOD 314>;
+ max-frequency = <2>;
+ power-domains = < 32>;
+ resets = < 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee12 {
+ compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+ reg = <0 0xee12 0 0x2000>;
+ interrupts = ;
+ clocks = < CPG_MOD 313>;
+ max-frequency = <2>;
+ power-domains = < 32>;
+ resets = < 313>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee14 {
+ compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+ reg = <0 0xee14 0 0x2000>;
+ interrupts = ;
+ clocks = < CPG_MOD 312>;
+ max-frequency = <2>;
+ power-domains = < 32>;
+ resets = < 312>;
+ status = "disabled";
+ };
+
+ sdhi3: sd@ee16 {
+ compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+ reg = <0 0xee16 0 0x2000>;
+ interrupts = ;
+ clocks = < CPG_MOD 311>;
+ max-frequency = <2>;
+ power-domains = < 32>;
+ resets = < 311>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
[PATCH 2/9] arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support
From: Biju Das
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774a1 device tree.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 142 ++
1 file changed, 142 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 7640856..5775451 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -14,6 +14,17 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 = _dvfs;
+ };
+
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@@ -170,6 +181,137 @@
resets = < 407>;
};
+ i2c0: i2c@e650 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+ reg = <0 0xe650 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 931>;
+ power-domains = < 32>;
+ resets = < 931>;
+ dmas = < 0x91>, < 0x90>,
+ < 0x91>, < 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 930>;
+ power-domains = < 32>;
+ resets = < 930>;
+ dmas = < 0x93>, < 0x92>,
+ < 0x93>, < 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e651 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+ reg = <0 0xe651 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 929>;
+ power-domains = < 32>;
+ resets = < 929>;
+ dmas = < 0x95>, < 0x94>,
+ < 0x95>, < 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 928>;
+ power-domains = < 32>;
+ resets = < 928>;
+ dmas = < 0x97>, < 0x96>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e66d8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 927>;
+ power-domains = < 32>;
+ resets = < 927>;
+ dmas = < 0x99>, < 0x98>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e66e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+ reg = <0
[PATCH 0/9] Add more support for r8a774a1
Dear All, This series adds SDHI, I2C, IIC, Thermal, IPMMU, MSIOF, A53, PWM, Audio and FCP support to the r8a774a1 SoC dtsi. There is a dependency with: https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg30528.html Thanks, Fab Biju Das (5): arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support arm64: dts: renesas: r8a774a1: Add all MSIOF nodes arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores arm64: dts: renesas: r8a774a1: Add audio support Fabrizio Castro (4): arm64: dts: renesas: r8a774a1: Add SDHI nodes arm64: dts: renesas: r8a774a1: Add IPMMU device nodes arm64: dts: renesas: r8a774a1: Add PWM device nodes arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 848 +- 1 file changed, 843 insertions(+), 5 deletions(-) -- 2.7.4
Re: [PATCH] mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS
On 08/23/2018 01:43 PM, Ulf Hansson wrote:
>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>>
>> Signed-off-by: Sergei Shtylyov
>
> Reviewed-by: Wolfram Sang
>
> Suggesting stable.
Stable looks at the Fixes: tags now. Should I add that?
>>>
>>> Yes, that would be great IMHO.
>>
>> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI
>> DMAC")
>>
>>Hopefully, Ulf uses patchwork. :-)
>
> I do. However, fixes tags doesn't seem to get picked up. Anyway, it's
I figured after writing... only patchwork.ozlabs.org seems to pick those up.
> easy for me to add them.
>
> Applied for fixes, thanks!
Thank you!
> Kind regards
> Uffe
MBR, Sergei
Re: [PATCH] mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS
On 22 August 2018 at 22:03, Sergei Shtylyov
wrote:
> On 08/22/2018 10:45 PM, Wolfram Sang wrote:
>
> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Wolfram Sang
Suggesting stable.
>>>
>>>Stable looks at the Fixes: tags now. Should I add that?
>>
>> Yes, that would be great IMHO.
>
> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI
> DMAC")
>
>Hopefully, Ulf uses patchwork. :-)
I do. However, fixes tags doesn't seem to get picked up. Anyway, it's
easy for me to add them.
Applied for fixes, thanks!
Kind regards
Uffe
Re: [PATCH v2] mmc: renesas_sdhi_internal_dmac: mask DMAC interrupts
On 22 August 2018 at 22:07, Sergei Shtylyov
wrote:
> On 08/22/2018 10:37 PM, Wolfram Sang wrote:
>
>>> I have encountered an interrupt storm during the eMMC chip probing (and
>>> the chip finally didn't get detected). It turned out that U-Boot left
>>> the SDHI DMA interrupts enabled while the Linux driver didn't use those.
>>> Masking those interrupts in renesas_sdhi_internal_dmac_request_dma() gets
>>> rid of both issues...
>>>
>>> Signed-off-by: Sergei Shtylyov
>>
>> Reviewed-by: Wolfram Sang
>
> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI
> DMAC")
>
> MBR, Sergei
Applied for fixes, thanks!
Kind regards
Uffe
Re: [PATCH] arm64: dts: renesas: salvator-common: Add GPIO keys support
Hi Laurent,
On Sun, Aug 19, 2018 at 9:44 PM Laurent Pinchart
wrote:
> The Salvator-X and XS boards have a 4 lines DIP switch and 3 push
> buttons connected to SoC GPIOs, meant to be used as general-purpose test
> keys. Add a corresponding node in DT, mapping (semi-randomly) the DIP
> switch to keys 1-4 and the push buttons to keys A-C.
>
> Signed-off-by: Laurent Pinchart
Given GP6_1[123] are not just wired to the 3 push buttons, but also to 3
LEDs, I wonder if we shouldn't postpone that part until Linux can handle
GPIOs connected to both?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] arm64: dts: renesas: salvator-common: Add GPIO keys support
Hi Simon,
On Wed, Aug 22, 2018 at 12:30 PM Simon Horman wrote:
> On Sun, Aug 19, 2018 at 10:44:55PM +0300, Laurent Pinchart wrote:
> > The Salvator-X and XS boards have a 4 lines DIP switch and 3 push
> > buttons connected to SoC GPIOs, meant to be used as general-purpose test
> > keys. Add a corresponding node in DT, mapping (semi-randomly) the DIP
>
> Arbitrary may be a better word choice than random.
>
> > switch to keys 1-4 and the push buttons to keys A-C.
> >
> > Signed-off-by: Laurent Pinchart
> > --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
> > + key-a {
> > + gpios = < 11 GPIO_ACTIVE_LOW>;
> > + linux,code = ;
> > + label = "TSW0";
>
> What does the 'T' in 'TSW' stand for? Toggle?
Tact Switch, cfr. the schematics.
> > @@ -567,6 +625,11 @@
> > function = "intc_ex";
> > };
> >
> > + keys_pins: keys {
> > + pins = "GP_5_17", "GP_5_20", "GP_5_22";
>
> I am curious to know why only some of the pins used above appear here.
GP5_23 has an external 100K pull-up, GP5_{17,20,22} don't.
GP6_1[123] have external 1K + 2K pull-upps.
>
> > + bias-pull-up;
> > + };
> > +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 5/5] arm64: dts: renesas: r8a774a1: Add RWDT node
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b771211..b9a3818 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -123,6 +123,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a774a1-wdt",
+"renesas,rcar-gen3-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = < CPG_MOD 402>;
+ power-domains = < 32>;
+ resets = < 402>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a774a1-cpg-mssr";
reg = <0 0xe615 0 0x0bb0>;
--
2.7.4
[PATCH 3/5] arm64: dts: renesas: r8a774a1: Add INTC-EX device node
Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 81fba7f..15d7785 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,22 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c {
+ compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c 0 0x200>;
+ interrupts = ;
+ clocks = < CPG_MOD 407>;
+ power-domains = < 32>;
+ resets = < 407>;
+ };
+
hscif0: serial@e654 {
compatible = "renesas,hscif-r8a774a1",
"renesas,rcar-gen3-hscif",
--
2.7.4
[PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
From: Fabrizio Castro
This patch adds the SoC specific part of the Ethernet AVB
device tree node.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 15d7785..b771211 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -350,6 +350,51 @@
dma-channels = <16>;
};
+ avb: ethernet@e680 {
+ compatible = "renesas,etheravb-r8a774a1",
+"renesas,etheravb-rcar-gen3";
+ reg = <0 0xe680 0 0x800>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = < CPG_MOD 812>;
+ power-domains = < 32>;
+ resets = < 812>;
+ phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a774a1",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.7.4
[PATCH 2/5] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
From: Fabrizio Castro
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 185 ++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4a4cf35..81fba7f 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,94 @@
#power-domain-cells = <1>;
};
+ hscif0: serial@e654 {
+ compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe654 0 0x60>;
+ interrupts = ;
+ clocks = < CPG_MOD 520>,
+< CPG_CORE 19>,
+<_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = < 0x31>, < 0x30>,
+ < 0x31>, < 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < 32>;
+ resets = < 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e655 {
+ compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe655 0 0x60>;
+ interrupts = ;
+ clocks = < CPG_MOD 519>,
+< CPG_CORE 19>,
+<_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = < 0x33>, < 0x32>,
+ < 0x33>, < 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < 32>;
+ resets = < 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e656 {
+ compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe656 0 0x60>;
+ interrupts = ;
+ clocks = < CPG_MOD 518>,
+< CPG_CORE 19>,
+<_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = < 0x35>, < 0x34>,
+ < 0x35>, < 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < 32>;
+ resets = < 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a {
+ compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe66a 0 0x60>;
+ interrupts = ;
+ clocks = < CPG_MOD 517>,
+< CPG_CORE 19>,
+<_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = < 0x37>, < 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = < 32>;
+ resets = < 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b {
+ compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe66b 0 0x60>;
+ interrupts = ;
+ clocks = < CPG_MOD 516>,
+< CPG_CORE 19>,
+<_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = < 0x39>, < 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = < 32>;
+ resets = < 516>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a774a1",
[PATCH 1/5] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 102 ++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8e63e9a..4a4cf35 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,108 @@
#power-domain-cells = <1>;
};
+ dmac0: dma-controller@e670 {
+ compatible = "renesas,dmac-r8a774a1",
+"renesas,rcar-dmac";
+ reg = <0 0xe670 0 0x1>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = < CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = < 32>;
+ resets = < 219>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac1: dma-controller@e730 {
+ compatible = "renesas,dmac-r8a774a1",
+"renesas,rcar-dmac";
+ reg = <0 0xe730 0 0x1>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = < CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = < 32>;
+ resets = < 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac2: dma-controller@e731 {
+ compatible = "renesas,dmac-r8a774a1",
+"renesas,rcar-dmac";
+ reg = <0 0xe731 0 0x1>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = < CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = < 32>;
+ resets = < 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
[PATCH 0/5] Add SYS-DMAC/INTC-EX/[H]SCIF/EAVB/RWDT support
This patch series aims to add support for SYS-DMAC/INTC-EX/SCIF/HSCIF/ EAVB/RWDT on RZ/G2M SoC dtsi. THis patch series based on renesas-devel-20180822-v4.18. Biju Das (3): arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes arm64: dts: renesas: r8a774a1: Add INTC-EX device node arm64: dts: renesas: r8a774a1: Add RWDT node Fabrizio Castro (2): arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes arm64: dts: renesas: r8a774a1: Add Ethernet AVB node arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 358 ++ 1 file changed, 358 insertions(+) -- 2.7.4
Re: [PATCH v2 5/7] arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
Hi Sergei,
On Thu, Aug 23, 2018 at 10:56 AM Sergei Shtylyov
wrote:
> On 8/23/2018 11:52 AM, Geert Uytterhoeven wrote:
> >>> According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
> >>> interfaces, similar to H3, M3-W and other SoCs from the same family.
> >>>
> >>> Add CAN placeholder nodes to avoid below DTC errors:
> >>> Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0
> >>> not found
> >>> Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1
> >>> not found
> >>>
> >>> These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
> >>> Fix them beforehand.
> >>>
> >>> CAN support is inspired from below commits:
> >>> - v4.7 commit 308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
> >>> - v4.11 commit 909c16252415 ("arm64: dts: r8a7796: Add CAN support")
> >>> - v4.12 commit bec0948e810f ("arm64: dts: r8a7796: Add reset control
> >>> properties")
> >>>
> >>> Signed-off-by: Eugeniu Rosca
> >>> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> >>> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> >>> @@ -656,6 +656,22 @@
> >>>status = "disabled";
> >>>};
> >>>
> >>> + can0: can@e6c3 {
> >>> + compatible = "renesas,can-r8a77965",
> >>> + "renesas,rcar-gen3-can";
> >>> + reg = <0 0xe6c3 0 0x1000>;
> >>> + /* placeholder */
> >>> + status = "disabled";
> >>> + };
> >>
> >> This is probably more detail than is needed for a placeholder, but it
> >> looks correct so I think this is fine.
> >
> > Indeed. Adding the "compatible" properties means they're no longer
> > placeholders, and will be probed by the driver, possibly leading to
> > undefined behavior.
>
> I don't think the disabled device nodes are actually probed.
They will be by ulcb-kf.dtsi, after the addition of
r8a77965-m3nulcb-kf.dts, cfr.
the errors and rationale documented in the commit message.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 5/7] arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
On 8/23/2018 11:52 AM, Geert Uytterhoeven wrote:
According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
interfaces, similar to H3, M3-W and other SoCs from the same family.
Add CAN placeholder nodes to avoid below DTC errors:
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0 not
found
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1 not
found
These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
Fix them beforehand.
CAN support is inspired from below commits:
- v4.7 commit 308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
- v4.11 commit 909c16252415 ("arm64: dts: r8a7796: Add CAN support")
- v4.12 commit bec0948e810f ("arm64: dts: r8a7796: Add reset control
properties")
Signed-off-by: Eugeniu Rosca
Reviewed-by: Kieran Bingham
---
Changes in v2:
- [Kieran Bingham] Improved commit description:
- Referenced the newer HW manual rev1.00 instead of rev0.55E.
- Kept the "true story" behind the patch. Just made it more clear.
- [Geert Uytterhoeven] Replaced CAN0 and CAN1 nodes with placeholders
(no CAN testing was done to validate the DTS configuration).
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 486aecacb22a..4da479d3c226 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -656,6 +656,22 @@
status = "disabled";
};
+ can0: can@e6c3 {
+ compatible = "renesas,can-r8a77965",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c3 0 0x1000>;
+ /* placeholder */
+ status = "disabled";
+ };
This is probably more detail than is needed for a placeholder, but it
looks correct so I think this is fine.
Indeed. Adding the "compatible" properties means they're no longer
placeholders, and will be probed by the driver, possibly leading to
undefined behavior.
I don't think the disabled device nodes are actually probed.
Hence please limit the placeholders to the absolute required minimum,
and thus drop the "compatible" and "status" properties.
OTOH, they're not needed (yet).
Gr{oetje,eeting}s,
Geert
MBR, Sergei
Re: [PATCH v2 5/7] arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
On Fri, Aug 17, 2018 at 3:53 PM Kieran Bingham
wrote:
> On 12/08/18 14:31, Eugeniu Rosca wrote:
> > According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
> > interfaces, similar to H3, M3-W and other SoCs from the same family.
> >
> > Add CAN placeholder nodes to avoid below DTC errors:
> > Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0
> > not found
> > Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1
> > not found
> >
> > These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
> > Fix them beforehand.
> >
> > CAN support is inspired from below commits:
> > - v4.7 commit 308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
> > - v4.11 commit 909c16252415 ("arm64: dts: r8a7796: Add CAN support")
> > - v4.12 commit bec0948e810f ("arm64: dts: r8a7796: Add reset control
> > properties")
> >
> > Signed-off-by: Eugeniu Rosca
>
> Reviewed-by: Kieran Bingham
>
>
> > ---
> > Changes in v2:
> > - [Kieran Bingham] Improved commit description:
> >- Referenced the newer HW manual rev1.00 instead of rev0.55E.
> >- Kept the "true story" behind the patch. Just made it more clear.
> > - [Geert Uytterhoeven] Replaced CAN0 and CAN1 nodes with placeholders
> >(no CAN testing was done to validate the DTS configuration).
> > ---
> > arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> > b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> > index 486aecacb22a..4da479d3c226 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> > @@ -656,6 +656,22 @@
> > status = "disabled";
> > };
> >
> > + can0: can@e6c3 {
> > + compatible = "renesas,can-r8a77965",
> > + "renesas,rcar-gen3-can";
> > + reg = <0 0xe6c3 0 0x1000>;
> > + /* placeholder */
> > + status = "disabled";
> > + };
>
> This is probably more detail than is needed for a placeholder, but it
> looks correct so I think this is fine.
Indeed. Adding the "compatible" properties means they're no longer
placeholders, and will be probed by the driver, possibly leading to
undefined behavior.
Hence please limit the placeholders to the absolute required minimum,
and thus drop the "compatible" and "status" properties.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 0/5] H3/M3-W cpuidle support
Hi Uli,
(with Khiem's address fixed (hopefully))
On Thu, Aug 23, 2018 at 10:22 AM Geert Uytterhoeven
wrote:
> On Fri, Aug 17, 2018 at 3:19 PM Ulrich Hecht wrote:
> > This series adds CPU idle support for H3 and M3-W. It's a straight
> > up-port from the BSP.
>
> Thanks for your series!
>
> > The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
> > dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
> > SoC?
>
> Alternatively, is this something that can be handled in the kernel using
> soc_device_match()?
Given many Salvator-X boards (incl. mine) also have M3-W ES1.0, and PSCI is
involved, I have to ask: is this a hardware (M3-W ES1.0) or firmware (PSCI)
issue?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 0/5] H3/M3-W cpuidle support
Hi Uli,
On Fri, Aug 17, 2018 at 3:19 PM Ulrich Hecht wrote:
> This series adds CPU idle support for H3 and M3-W. It's a straight
> up-port from the BSP.
Thanks for your series!
> The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
> dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
> SoC?
Alternatively, is this something that can be handled in the kernel using
soc_device_match()?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH] pinctrl: sh-pfc: r8a77990: Add DU pins, groups and function
This patch adds DU pins, groups and function for the R8A77990 (E3) SoC.
Signed-off-by: Laurent Pinchart
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 101 ++
1 file changed, 101 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index b81c807ac54d..00769ec9635e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1371,6 +1371,87 @@ static const unsigned int avb_avtp_capture_a_mux[] = {
AVB_AVTP_CAPTURE_A_MARK,
};
+/* - DU -
*/
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+ DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+ DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+ DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+ DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+ DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+ DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
+};
+static const unsigned int du_clk_in_1_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int du_clk_in_1_mux[] = {
+ DU_DOTCLKIN1_MARK
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU_DOTCLKOUT0_MARK
+};
+static const unsigned int du_sync_pins[] = {
+ /* VSYNC, HSYNC */
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_VSYNC_MARK, DU_HSYNC_MARK
+};
+static const unsigned int du_disp_cde_pins[] = {
+ /* DISP_CDE */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int du_disp_cde_mux[] = {
+ DU_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_DISP_MARK,
+};
+
/* - I2C
*/
static const unsigned int i2c1_a_pins[] = {
/* SCL, SDA */
@@ -1839,6 +1920,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_in_1),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_disp_cde),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c1_c),
@@ -1901,6 +1990,17 @@ static const char * const avb_groups[] = {
"avb_avtp_capture_a",
};
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_in_1",
+ "du_clk_out_0",
+ "du_sync",
+ "du_disp_cde",
+ "du_cde",
+ "du_disp",
+};
+
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@@ -1998,6 +2098,7 @@ static const char * const usb30_groups[] = {
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(i2c1),
