[PATCH] dt-bindings: pwm: renesas: tpu: fix "compatible" prop description
The "compatible" property description contradicts even the example given:
it only says that there must be a single value while the example has the
fallback value too -- which makes much more sense. Moreover, the generic
property value is misdocumented as being R-Car (and RZ/G1) specific...
Fixes: 382457e562bb ("pwm: renesas-tpu: Add DT support")
Fixes: 3ba111a01822 ("dt-bindings: pwm: renesas-tpu: Document r8a774[35]
support")
Signed-off-by: Sergei Shtylyov
---
This patch is against Linus' repo -- the 'fixes' branch in Thierry Reding's
repo is very outdated...
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Index: linux/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
===
--- linux.orig/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+++ linux/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
@@ -2,13 +2,14 @@
Required Properties:
- - compatible: should be one of the following.
+ - compatible: must contain one or more of the following:
- "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM
controller.
- "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM
controller.
- "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
- "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
- "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
-- "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller.
+- "renesas,tpu": for the generic TPU PWM controller; this is a fallback for
+the above .
- reg: Base address and length of each memory resource used by the PWM
controller hardware module.
[PATCH 4/4] ARM: dts: r8a77470: Add I2C4 support
Add I2C4 support to RZ/G1C (a.k.a. r8a77470) SoC specific
device tree.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm/boot/dts/r8a77470.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9e7f86d..9ec78d3 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -237,6 +237,20 @@
reg = <0 0xe630 0 0x2>;
};
+ i2c4: i2c@e652 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77470",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe652 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 927>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
--
2.7.4
[PATCH 2/4] dt-bindings: i2c: rcar: Document r8a7744 support
From: Biju Das Document i2c Device Tree support for RZ/G1N (R8A7744) SoC, which is compatible with R-Car Gen2 SoC family. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index 671e2a1..30c0485 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -3,6 +3,7 @@ I2C for R-Car platforms Required properties: - compatible: "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. + "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC. "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC. "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC. -- 2.7.4
[PATCH 3/4] dt-bindings: i2c: sh_mobile: Document r8a7744 support
From: Biju Das Document i2c Device Tree support for RZ/G1N (R8A7744) SoC, which is compatible with R-Car Gen2 SoC family. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt index 872673a..d81b626 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt @@ -5,6 +5,7 @@ Required properties: - "renesas,iic-r8a73a4" (R-Mobile APE6) - "renesas,iic-r8a7740" (R-Mobile A1) - "renesas,iic-r8a7743" (RZ/G1M) + - "renesas,iic-r8a7744" (RZ/G1N) - "renesas,iic-r8a7745" (RZ/G1E) - "renesas,iic-r8a774a1" (RZ/G2M) - "renesas,iic-r8a7790" (R-Car H2) -- 2.7.4
[PATCH 1/4] dt-bindings: i2c: rcar: Add r8a77470 support
Although the I2C IP found in the RZ/G1C is not exactly the same as the one found in the R-Car Gen2 family or R-Car Gen3 family, it can still be considered as compatible with R-Car Gen2 from a software perpective. This patch therefore documents the SoC specific compatible string, and the compatibility with Gen2 fallback is retained. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das --- Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index 39cd21d..671e2a1 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -4,6 +4,7 @@ Required properties: - compatible: "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. + "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC. "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC. "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. -- 2.7.4
[PATCH 0/4] Add RZ/G1C and RZ/G1N I2C related support
Dear All, this series documents the I2C controllers found in the RZ/G1C and RZ/G1N, and also adds I2C4 support to the RZ/G1C SoC specific dtsi. Thanks, Fab Biju Das (2): dt-bindings: i2c: rcar: Document r8a7744 support dt-bindings: i2c: sh_mobile: Document r8a7744 support Fabrizio Castro (2): dt-bindings: i2c: rcar: Add r8a77470 support ARM: dts: r8a77470: Add I2C4 support Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 2 ++ Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 1 + arch/arm/boot/dts/r8a77470.dtsi | 14 ++ 3 files changed, 17 insertions(+) -- 2.7.4
Re: [PATCH] drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled
On Fri, Sep 21, 2018 at 08:49:03PM +0900, Nguyen An Hoan wrote:
> @@ -66,8 +66,15 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
> /* Locate the DRM bridge from the encoder DT node. */
> bridge = of_drm_find_bridge(enc_node);
> if (!bridge) {
> +#if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI)
> ret = -EPROBE_DEFER;
> goto done;
> +#else
> + if (output == RCAR_DU_OUTPUT_HDMI0 ||
> + output == RCAR_DU_OUTPUT_HDMI1)
> + ret = 0;
> + goto done;
> +#endif
> }
This seems to make sense to me assuming there's no other encoder that
could possibly connected though I'm not 100% up to speed on the DRM
subsystem so it's possible I'm missing some framework feature that
should help here. I'm not a DRM expert though.
signature.asc
Description: PGP signature
Re: [PATCH] drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled
On Fri, Sep 21, 2018 at 08:49:02PM +0900, Nguyen An Hoan wrote: > From: Hoan Nguyen An > > Skip return EPROBE_DEFER when DRM_RCAR_DW_HDMI is disabled in case HDMI > initialize. > At this time, the rcar-du driver not be able to successfully initialize > if disable DRM_RCAR_DW_HDMI (rcar_du_probe return error), > so can not use other features such as RGB Analog, this patch to fix. Please don't send cover letters for single patches, if there is anything that needs saying put it in the changelog of the patch or after the --- if it's administrative stuff. This reduces mail volume and ensures that any important information is recorded in the changelog rather than being lost. signature.asc Description: PGP signature
[PATCH] dt-bindings: apmu: Document r8a7744 support
Document APMU and SMP enable method for RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- Documentation/devicetree/bindings/power/renesas,apmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt index e6f47c9..5f24586 100644 --- a/Documentation/devicetree/bindings/power/renesas,apmu.txt +++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt @@ -8,6 +8,7 @@ Required properties: - compatible: Should be "renesas,-apmu", "renesas,apmu" as fallback. Examples with soctypes are: - "renesas,r8a7743-apmu" (RZ/G1M) + - "renesas,r8a7744-apmu" (RZ/G1N) - "renesas,r8a7745-apmu" (RZ/G1E) - "renesas,r8a77470-apmu" (RZ/G1C) - "renesas,r8a7790-apmu" (R-Car H2) -- 2.7.4
RE: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
Hello Wolfram, Thank you for your feedback! > -Original Message- > From: Wolfram Sang > Sent: 21 September 2018 16:48 > To: Geert Uytterhoeven > Cc: Fabrizio Castro ; Laurent Pinchart > ; Geert Uytterhoeven > ; Linus Walleij ; > Linux-Renesas ; open > list:GPIO SUBSYSTEM ; Simon Horman > ; Chris Paterson > ; Biju Das ; Wolfram > Sang > Subject: Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups > > > > > 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to > > > the interface, keep the SD card pin groups as specified by this > > > patch, map all of the pins to the same bit in the POC register (as > > > per pin_to_pocctrl is concerned), and the board specific device tree > > > definitions would look like every other RZ/G1 or R-Car Gen2 boards > > > that support SDR* The only downside would be that the kernel would > > > read-modify-write the POC Control Register with the same value for > > > every line in the interface. > > I don't think this multiple RMW is a problem. > > > This looks the most sensible solution to me: just map in your > > .pin_to_pocctrl() method all pins of the interface to the single bit. > > I didn't fully get if this one bit controls only the CLK wire or all the > relevant wires? I assume it is the latter one. For that, option 2) is > totally fine with me. It is not super clear what the intended behaviour is from the HW User's manual indeed, but I have tested SDR50 and it seems to be working fine, which would indicate that the control bit in the POC Control Register is actually controlling all of the lines of the interface, and not just the CLK pin. Thanks, Fab Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
RE: [PATCH net-next] dt-bindings: net: ravb: Add support for r8a7744 SoC
Hi Sergei, Thanks for the feedback. > Subject: Re: [PATCH net-next] dt-bindings: net: ravb: Add support for > r8a7744 SoC > > Hello! > > On 09/21/2018 05:25 PM, Biju Das wrote: > > > Document RZ/G1N (R8A7744) SoC bindings. > > > > Signed-off-by: Biju Das > > Reviewed-by: Fabrizio Castro > > Reviewed-by: Sergei Shtylyov > > > --- > > Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt > b/Documentation/devicetree/bindings/net/renesas,ravb.txt > > index da249b7..3530256 100644 > > --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt > > +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt > > @@ -6,6 +6,7 @@ interface contains. > > Required properties: > > - compatible: Must contain one or more of the following: > >- "renesas,etheravb-r8a7743" for the R8A7743 SoC. > > + - "renesas,etheravb-r8a7744" for the R8A7744 SoC. > >Mmm, I thought it was decided to go with the full model #s, like with > R8A77470 below? For RZ/G1C case, there are 2 variants 1 with HDMI(R8A77470) and the other without HDMI(R8A77471). Current support is for R8A77470. > >- "renesas,etheravb-r8a7745" for the R8A7745 SoC. > >- "renesas,etheravb-r8a77470" for the R8A77470 SoC. > >- "renesas,etheravb-r8a7790" for the R8A7790 SoC. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
> > 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to > > the interface, keep the SD card pin groups as specified by this > > patch, map all of the pins to the same bit in the POC register (as > > per pin_to_pocctrl is concerned), and the board specific device tree > > definitions would look like every other RZ/G1 or R-Car Gen2 boards > > that support SDR* The only downside would be that the kernel would > > read-modify-write the POC Control Register with the same value for > > every line in the interface. I don't think this multiple RMW is a problem. > This looks the most sensible solution to me: just map in your > .pin_to_pocctrl() method all pins of the interface to the single bit. I didn't fully get if this one bit controls only the CLK wire or all the relevant wires? I assume it is the latter one. For that, option 2) is totally fine with me. signature.asc Description: PGP signature
[PATCH] dt-bindings: gpio: rcar: Add r8a7744 (RZ/G1N) support
Renesas RZ/G1N (R8A7744) SoC GPIO blocks are identical to the R-Car Gen2 family. Add support for its GPIO controllers. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 4018ee5..5968ccf 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -4,6 +4,7 @@ Required Properties: - compatible: should contain one or more of the following: - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller. +- "renesas,gpio-r8a7744": for R8A7744 (RZ/G1N) compatible GPIO controller. - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller. - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller. - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller. -- 2.7.4
[PATCH 2/2] clk: renesas: r7s9210: Convert some clocks to early
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 141 +
1 file changed, 90 insertions(+), 51 deletions(-)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index bd1dd4ff2051..eb9103cfa2ac 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -55,25 +55,25 @@ enum clk_ids {
static struct cpg_core_clk r7s9210_core_clks[] = {
/* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
+ /*".extal" exists as early clock */
/* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
- DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
+ /*".main" exists as early clock */
+ /*".pll"exists as early clock */
/* Core Clock Outputs */
DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
DEF_FIXED("p1", R7S9210_CLK_P1,CLK_PLL, 16, 1),
- DEF_FIXED("p1c",R7S9210_CLK_P1C, CLK_PLL, 16, 1),
+ /*"p1c" exists as early clock */
DEF_FIXED("p0", R7S9210_CLK_P0,CLK_PLL, 32, 1),
};
static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
- DEF_MOD_STB("ostm2", 34,R7S9210_CLK_P1C),
- DEF_MOD_STB("ostm1", 35,R7S9210_CLK_P1C),
- DEF_MOD_STB("ostm0", 36,R7S9210_CLK_P1C),
+ /* "ostm2" 36 exists as early clock */
+ /* "ostm1" 35 exists as early clock */
+ /* "ostm0" 34 exists as early clock */
DEF_MOD_STB("scif4", 43,R7S9210_CLK_P1C),
DEF_MOD_STB("scif3", 44,R7S9210_CLK_P1C),
@@ -91,6 +91,71 @@ static const struct mssr_mod_clk r7s9210_mod_clks[]
__initconst = {
};
+static struct cpg_core_clk r7s9210_early_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("p1c",R7S9210_CLK_P1C, CLK_PLL, 16, 1),
+};
+
+static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {
+ DEF_MOD_STB("ostm2", 34,R7S9210_CLK_P1C),
+ DEF_MOD_STB("ostm1", 35,R7S9210_CLK_P1C),
+ DEF_MOD_STB("ostm0", 36,R7S9210_CLK_P1C),
+};
+
+/* The clock dividers in the table vary based on DT and register settings */
+static void r7s9210_update_clk_table(struct clk *extal_clk, void __iomem *base)
+{
+ int i;
+ u16 frqcr;
+ u8 index;
+
+ /* If EXTAL is above 12MHz, then we know it is Mode 1 */
+ if (clk_get_rate(extal_clk) > 1200)
+ cpg_mode = 1;
+
+ frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
+ if (frqcr == 0x012)
+ index = 0;
+ else if (frqcr == 0x112)
+ index = 1;
+ else if (frqcr == 0x212)
+ index = 2;
+ else if (frqcr == 0x322)
+ index = 3;
+ else if (frqcr == 0x333)
+ index = 4;
+ else
+ BUG_ON(1); /* Illegal FRQCR value */
+
+ for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
+ switch (r7s9210_core_clks[i].id) {
+ case R7S9210_CLK_I:
+ r7s9210_core_clks[i].div = ratio_tab[index].i;
+ break;
+ case R7S9210_CLK_G:
+ r7s9210_core_clks[i].div = ratio_tab[index].g;
+ break;
+ case R7S9210_CLK_B:
+ r7s9210_core_clks[i].div = ratio_tab[index].b;
+ break;
+ case R7S9210_CLK_P1:
+ case R7S9210_CLK_P1C:
+ r7s9210_core_clks[i].div = ratio_tab[index].p1;
+ break;
+ case R7S9210_CLK_P0:
+ r7s9210_core_clks[i].div = 32;
+ break;
+ }
+ }
+}
+
struct clk * __init rza2_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
@@ -99,9 +164,6 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev,
struct clk *parent;
unsigned int mult = 1;
unsigned int div = 1;
- u16 frqcr;
- u8 index;
- int i;
parent = clks[core->parent];
if (IS_ERR(parent))
[PATCH 1/2] clk: renesas: cpg-mssr: Add early clock support
Add support for SoCs that need to register core and module clocks early in
order to use OF drivers that exclusively use macros such as
TIMER_OF_DECLARE.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/renesas-cpg-mssr.c | 106 ++---
drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++
2 files changed, 91 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index 3df764d3ab20..b4be3cc18505 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -127,6 +127,7 @@ struct cpg_mssr_priv {
struct device *dev;
void __iomem *base;
spinlock_t rmw_lock;
+ struct device_node *np;
struct clk **clks;
unsigned int num_core_clks;
@@ -141,6 +142,7 @@ struct cpg_mssr_priv {
} smstpcr_saved[ARRAY_SIZE(smstpcr)];
};
+struct cpg_mssr_priv *early_priv;
/**
* struct mstp_clock - MSTP gating clock
@@ -316,7 +318,7 @@ static void __init cpg_mssr_register_core_clk(const struct
cpg_core_clk *core,
switch (core->type) {
case CLK_TYPE_IN:
- clk = of_clk_get_by_name(priv->dev->of_node, core->name);
+ clk = of_clk_get_by_name(priv->np, core->name);
break;
case CLK_TYPE_FF:
@@ -877,42 +879,49 @@ static const struct dev_pm_ops cpg_mssr_pm = {
#define DEV_PM_OPS NULL
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
-static int __init cpg_mssr_probe(struct platform_device *pdev)
+static int cpg_mssr_common_init(struct device *dev, struct device_node *np,
+ const struct cpg_mssr_info *info)
{
- struct device *dev = >dev;
- struct device_node *np = dev->of_node;
- const struct cpg_mssr_info *info;
struct cpg_mssr_priv *priv;
unsigned int nclks, i;
- struct resource *res;
- struct clk **clks;
+ struct clk **clks = NULL;
int error;
+ bool early_init = dev ? false : true;
- info = of_device_get_match_data(dev);
if (info->init) {
error = info->init(dev);
if (error)
return error;
}
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ /* np is saved because dev->of_node doesn't exists during early init */
+ priv->np = np;
+
priv->dev = dev;
spin_lock_init(>rmw_lock);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ priv->base = of_iomap(np, 0);
+ if (IS_ERR(priv->base)) {
+ error = PTR_ERR(priv->base);
+ goto out_err;
+ }
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
- clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
- if (!clks)
- return -ENOMEM;
+ clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
+ if (!clks) {
+ error = -ENOMEM;
+ goto out_err;
+ }
+
+ if (early_init)
+ early_priv = priv;
+ else
+ dev_set_drvdata(dev, priv);
- dev_set_drvdata(dev, priv);
priv->clks = clks;
priv->num_core_clks = info->num_total_core_clks;
priv->num_mod_clks = info->num_hw_mod_clks;
@@ -923,16 +932,71 @@ static int __init cpg_mssr_probe(struct platform_device
*pdev)
for (i = 0; i < nclks; i++)
clks[i] = ERR_PTR(-ENOENT);
+ error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
+ if (error)
+ goto out_err;
+
+ return 0;
+
+out_err:
+ kfree(clks);
+ if (priv->base)
+ iounmap(priv->base);
+ kfree(priv);
+
+ return error;
+}
+
+void __init cpg_mssr_early_init(struct device_node *np,
+ const struct cpg_mssr_info *info)
+{
+ int error;
+ int i;
+
+ error = cpg_mssr_common_init(NULL, np, info);
+ if (error)
+ return;
+
+ for (i = 0; i < info->num_early_core_clks; i++)
+ cpg_mssr_register_core_clk(>early_core_clks[i], info,
+ early_priv);
+
+ for (i = 0; i < info->num_early_mod_clks; i++)
+ cpg_mssr_register_mod_clk(>early_mod_clks[i], info,
+ early_priv);
+
+}
+
+static int __init cpg_mssr_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct device_node *np = dev->of_node;
+ const struct cpg_mssr_info *info;
+ struct cpg_mssr_priv *priv;
+ unsigned int i;
+ int error;
+
+ info = of_device_get_match_data(dev);
+
+ if
[PATCH 0/2] clk: renesas: r7s9210: Add support for early clocks
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the ostm module clocks to be registers early in boot. This series add early clock support to cpg-mssr Here are some notes I took: * Switched to using of_iomap(cpg_np, 0) instead of platform_get_resource(pdev, IORESOURCE_MEM, 0) * All devm_xxx calls were replaced with the traditinal functions because 'dev' is not available for early probe * some functions are still using dev_dbg and dev_err for messages, but in early init, dev is set to NULL so it doesn't crash, the messages just look like this: (NULL device *): Core clock extal at 2400 Hz (NULL device *): clock (1, 35) is ostm1 at 6600 Hz * np was added to priv np is saved because dev->of_node doesn't exist during early init and we need to avoid using 'dev' for any function that will run during early init * all .init functions (r8_cpg_mssr_init) for the SoCs do not use dev, except for r8a7791_cpg_mssr_init for the lines: struct device_node *np = dev->of_node; of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr") But, so if early clock support was every needed for r8a7791 or r8a7793, that line will need to be changed. * In r7s9210-cpg-mssr.c, I moved updating the clock ratio table to a separate function (r7s9210_update_table) because it looks cleaner. Chris Brandt (2): clk: renesas: cpg-mssr: Add early clock support clk: renesas: r7s9210: Convert some clocks to early drivers/clk/renesas/r7s9210-cpg-mssr.c | 141 + drivers/clk/renesas/renesas-cpg-mssr.c | 106 - drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++ 3 files changed, 181 insertions(+), 72 deletions(-) -- 2.16.1
[PATCH] dt-bindings: serial: sh-sci: Document r8a7744 bindings
RZ/G1N (R8A7744) SoC also has the R-Car gen2 compatible SCIF, SCIFA, SCIFB, and HSCIF ports, so document the SoC specific bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index eaca9da..723abe0 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -14,6 +14,10 @@ Required properties: - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART. - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART. - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART. +- "renesas,scif-r8a7744" for R8A7744 (RZ/G1N) SCIF compatible UART. +- "renesas,scifa-r8a7744" for R8A7744 (RZ/G1N) SCIFA compatible UART. +- "renesas,scifb-r8a7744" for R8A7744 (RZ/G1N) SCIFB compatible UART. +- "renesas,hscif-r8a7744" for R8A7744 (RZ/G1N) HSCIF compatible UART. - "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART. - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. -- 2.7.4
[PATCH] ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi
PCIe is not populated by default on iWave RZ/G1N board. RZ/G1N board
is almost identical to RZ/G1M. In order to reuse the common dtsi for
both the boards, it is required to move pcie node from common dtsi
to board specific dts.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 4
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 4
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 4
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 5cae74e..ca9154dd 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -160,10 +160,6 @@
clock-frequency = <1>;
};
- {
- status = "okay";
-};
-
{
can0_pins: can0 {
groups = "can0_data_d";
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
index 3275451..0d006ae 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
@@ -14,3 +14,7 @@
model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b683db4..498e223 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -13,3 +13,7 @@
model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
};
+
+ {
+ status = "okay";
+};
--
2.7.4
[PATCH 0/8] phy: renesas: rcar-gen3-usb2: re-design for all R-Car Gen3 SoCs
This patch set is based on the linux-phy / next branch (the commit id is 53706a1168631fa5bf2e6d47de4647ea7e69f270). Since all R-Car Gen3 SoCs have dedicated otg pins in fact, the previous code was not good to handle it. So, this patch set changes the design for all R-Car Gen3 SoCs. Yoshihiro Shimoda (8): dt-bindings: rcar-gen3-phy-usb2: add no-otg-pins property phy: renesas: rcar-gen3-usb2: fix vbus_ctrl for role sysfs phy: renesas: rcar-gen3-usb2: Rename has_otg_pins to uses_otg_pins phy: renesas: rcar-gen3-usb2: Check a property to use otg pins phy: renesas: rcar-gen3-usb2: unify OBINTEN handling phy: renesas: rcar-gen3-usb2: change a condition "dr_mode" phy: renesas: rcar-gen3-usb2: add conditions for uses_otg_pins == false phy: renesas: rcar-gen3-usb2: add is_otg_channel to use "role" sysfs .../devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 + drivers/phy/renesas/phy-rcar-gen3-usb2.c | 80 +- 2 files changed, 48 insertions(+), 34 deletions(-) -- 1.9.1
[PATCH 6/8] phy: renesas: rcar-gen3-usb2: change a condition "dr_mode"
This patch changes a condition about dr_mode. If a device node has
any dr_mode ("host", "peripheral" or "otg"), this driver allows to
set "is_otg_channel" to true. Also, this patch keeps the dr_mode
value for future use.
Signed-off-by: Yoshihiro Shimoda
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index e7eaed9..93ab860 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -84,6 +84,7 @@ struct rcar_gen3_chan {
struct phy *phy;
struct regulator *vbus;
struct work_struct work;
+ enum usb_dr_mode dr_mode;
bool extcon_host;
bool uses_otg_pins;
};
@@ -436,7 +437,8 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device
*pdev)
dev_err(dev, "No irq handler (%d)\n", irq);
}
- if (of_usb_get_dr_mode_by_phy(dev->of_node, 0) == USB_DR_MODE_OTG) {
+ channel->dr_mode = of_usb_get_dr_mode_by_phy(dev->of_node, 0);
+ if (channel->dr_mode != USB_DR_MODE_UNKNOWN) {
int ret;
channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
--
1.9.1
[PATCH 3/4] ARM: dts: r8a77470: Add SDHI2 support
Add SoC specific device tree definitions for the SDHI2 interface.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm/boot/dts/r8a77470.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9aba350..9e7f86d 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -412,6 +412,21 @@
status = "disabled";
};
+ sdhi2: sd@ee16 {
+ compatible = "renesas,sdhi-r8a77470",
+"renesas,rcar-gen2-sdhi";
+ reg = <0 0xee16 0 0x328>;
+ interrupts = ;
+ clocks = < CPG_MOD 312>;
+ dmas = < 0xd3>, < 0xd4>,
+ < 0xd3>, < 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <9750>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 312>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
[PATCH 4/4] ARM: dts: iwg23s-sbc: Add uSD card support
Add uSD card support to the iwg23s single board computer powered
by the RZ/G1C SoC (a.k.a. r8a77470).
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
Hello Simon,
this patch can only be taken after patch "pinctrl: sh-pfc: r8a77470:
Add SDHI2 voltage switch" from this series appears on a release candidate
or a release.
Shall I re-send it at a later stage or are you happy to keep it around
and defer its application to when its dependency is sorted?
Thanks,
Fab
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 22da819..cd9c3fc 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -6,6 +6,7 @@
*/
/dts-v1/;
+#include
#include "r8a77470.dtsi"
/ {
model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
@@ -25,6 +26,29 @@
device_type = "memory";
reg = <0 0x4000 0 0x2000>;
};
+
+ vcc_sdhi2: regulator-vcc-sdhi2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+
+ enable-active-high;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+
+ gpios = < 24 GPIO_ACTIVE_LOW>;
+ gpios-states = <1>;
+ states = <330 1
+ 180 0>;
+ };
};
{
@@ -50,6 +74,18 @@
groups = "scif1_data_b";
function = "scif1";
};
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
};
{
@@ -58,3 +94,16 @@
status = "okay";
};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-1 = <_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <_sdhi2>;
+ vqmmc-supply = <_sdhi2>;
+ bus-width = <4>;
+ cd-gpios = < 20 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
--
2.7.4
[PATCH 2/4] pinctrl: sh-pfc: r8a77470: Add SDHI2 voltage switch
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI2 pins
capable of switching voltage. Please note that with the
RZ/G1C only 1 bit of the POC Control Register is used to
control each interface.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 9d3ed43..a1248e2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -17,7 +17,19 @@
PORT_GP_1(3, 27, fn, sfx), \
PORT_GP_1(3, 28, fn, sfx), \
PORT_GP_1(3, 29, fn, sfx), \
- PORT_GP_26(4, fn, sfx), \
+ PORT_GP_14(4, fn, sfx), \
+ PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_1(4, 20, fn, sfx), \
+ PORT_GP_1(4, 21, fn, sfx), \
+ PORT_GP_1(4, 22, fn, sfx), \
+ PORT_GP_1(4, 23, fn, sfx), \
+ PORT_GP_1(4, 24, fn, sfx), \
+ PORT_GP_1(4, 25, fn, sfx), \
PORT_GP_32(5, fn, sfx)
enum {
@@ -2321,9 +2333,27 @@ static const struct pinmux_cfg_reg pinmux_config_regs[]
= {
{ },
};
+static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ u32 *pocctrl)
+{
+ unsigned int _bank = pin >> 5;
+ unsigned int _pin = pin & 0x1f;
+ *pocctrl = 0xe60600b0;
+
+ if (_bank == 4 && _pin >= 14 && _pin <= 19)
+ return 1;
+
+ return -EINVAL;
+}
+
+static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
+ .pin_to_pocctrl = r8a77470_pin_to_pocctrl,
+};
+
#ifdef CONFIG_PINCTRL_PFC_R8A77470
const struct sh_pfc_soc_info r8a77470_pinmux_info = {
.name = "r8a77470_pfc",
+ .ops = _pinmux_ops,
.unlock_reg = 0xe606, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
--
2.7.4
[PATCH 8/8] phy: renesas: rcar-gen3-usb2: add is_otg_channel to use "role" sysfs
Even if a board doesn't have otg pins connection, this hardware can
change the role by a register setting. So, this patch adds
"is_otg_channel" for it.
Signed-off-by: Yoshihiro Shimoda
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 3f2efe5..9903aef 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -86,8 +86,19 @@ struct rcar_gen3_chan {
struct work_struct work;
enum usb_dr_mode dr_mode;
bool extcon_host;
+ bool is_otg_channel;
bool uses_otg_pins;
};
+/*
+ * Combination about is_otg_channel and uses_otg_pins:
+ *
+ * Parameters || Behaviors
+ * is_otg_channel | uses_otg_pins || irqs | role sysfs
+ * -+---++--+
+ * true| true || enabled | enabled
+ * true | false|| disabled | enabled
+ * false| any || disabled | disabled
+ */
static void rcar_gen3_phy_usb2_work(struct work_struct *work)
{
@@ -244,7 +255,7 @@ static ssize_t role_store(struct device *dev, struct
device_attribute *attr,
bool is_b_device;
enum phy_mode cur_mode, new_mode;
- if (!ch->uses_otg_pins || !ch->phy->init_count)
+ if (!ch->is_otg_channel || !ch->phy->init_count)
return -EIO;
if (!strncmp(buf, "host", strlen("host")))
@@ -282,7 +293,7 @@ static ssize_t role_show(struct device *dev, struct
device_attribute *attr,
{
struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
- if (!ch->uses_otg_pins || !ch->phy->init_count)
+ if (!ch->is_otg_channel || !ch->phy->init_count)
return -EIO;
return sprintf(buf, "%s\n", rcar_gen3_is_host(ch) ? "host" :
@@ -320,7 +331,7 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
/* Initialize otg part */
- if (channel->uses_otg_pins)
+ if (channel->is_otg_channel)
rcar_gen3_init_otg(channel);
return 0;
@@ -444,6 +455,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device
*pdev)
if (channel->dr_mode != USB_DR_MODE_UNKNOWN) {
int ret;
+ channel->is_otg_channel = true;
channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
"renesas,no-otg-pins");
channel->extcon = devm_extcon_dev_allocate(dev,
@@ -487,7 +499,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device
*pdev)
dev_err(dev, "Failed to register PHY provider\n");
ret = PTR_ERR(provider);
goto error;
- } else if (channel->uses_otg_pins) {
+ } else if (channel->is_otg_channel) {
int ret;
ret = device_create_file(dev, _attr_role);
@@ -507,7 +519,7 @@ static int rcar_gen3_phy_usb2_remove(struct platform_device
*pdev)
{
struct rcar_gen3_chan *channel = platform_get_drvdata(pdev);
- if (channel->uses_otg_pins)
+ if (channel->is_otg_channel)
device_remove_file(>dev, _attr_role);
pm_runtime_disable(>dev);
--
1.9.1
[PATCH 0/4] Add SDHI2 support to iwg23s
Dear All, this series adds SDHI2 support to the iwg23s. The RZ/G1C (the SoC powering the iwg23s) is slightly different from the other R-Car and RZ/G1 devices, in the sense that this device uses only one bit of the POC Control Register to control the voltage of the entire interface, as opposed to one bit per pin. There is a discussion on the ML that is going on about this: https://patchwork.kernel.org/patch/10604395/ and the patches from this series implement "option 2". Thanks, Fab Fabrizio Castro (4): dt-bindings: mmc: renesas_sdhi: Add r8a77470 support pinctrl: sh-pfc: r8a77470: Add SDHI2 voltage switch ARM: dts: r8a77470: Add SDHI2 support ARM: dts: iwg23s-sbc: Add uSD card support Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 49 ++ arch/arm/boot/dts/r8a77470.dtsi| 15 +++ drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 32 +- 4 files changed, 96 insertions(+), 1 deletion(-) -- 2.7.4
[PATCH 7/8] phy: renesas: rcar-gen3-usb2: add conditions for uses_otg_pins == false
If uses_otg_pins is set to false, this driver 1) should disable otg
related interruptions, and 2) should not get ID pin signal, to avoid
unexpected behaviors. So, this patch adds conditions for it.
Signed-off-by: Yoshihiro Shimoda
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 93ab860..3f2efe5 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -148,7 +148,7 @@ static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan
*ch, int enable)
void __iomem *usb2_base = ch->base;
u32 val = readl(usb2_base + USB2_OBINTEN);
- if (enable)
+ if (ch->uses_otg_pins && enable)
val |= USB2_OBINT_BITS;
else
val &= ~USB2_OBINT_BITS;
@@ -210,6 +210,9 @@ static void rcar_gen3_init_from_a_peri_to_a_host(struct
rcar_gen3_chan *ch)
static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
{
+ if (!ch->uses_otg_pins)
+ return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
+
return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}
--
1.9.1
[PATCH 2/8] phy: renesas: rcar-gen3-usb2: fix vbus_ctrl for role sysfs
This patch fixes and issue that the vbus_ctrl is disabled by
rcar_gen3_init_from_a_peri_to_a_host(), so a usb host cannot
supply the vbus.
Note that this condition will exit when the otg irq happens
even if we don't apply this patch.
Fixes: 9bb86777fb71 ("phy: rcar-gen3-usb2: add sysfs for usb role swap")
Signed-off-by: Yoshihiro Shimoda
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 3d57ea1..a6db25c 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -195,7 +195,7 @@ static void rcar_gen3_init_from_a_peri_to_a_host(struct
rcar_gen3_chan *ch)
val = readl(usb2_base + USB2_OBINTEN);
writel(val & ~USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
- rcar_gen3_enable_vbus_ctrl(ch, 0);
+ rcar_gen3_enable_vbus_ctrl(ch, 1);
rcar_gen3_init_for_host(ch);
writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
--
1.9.1
[PATCH 1/4] dt-bindings: mmc: renesas_sdhi: Add r8a77470 support
Document SDHI support for the RZ/G1C (a.k.a. R8A77470) SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index c434200..8f3a113 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -17,6 +17,7 @@ Required properties: "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC + "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC -- 2.7.4
RE: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
Hello Geert,
Thank you for your feedback!
> Subject: Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
>
> Hi Fabrizio,
>
> CC wolfram
>
> On Wed, Sep 19, 2018 at 12:19 PM Fabrizio Castro
> wrote:
> > Although this patch is pretty much standard, I would like to start a
> > discussion as while testing SDHI2 (which goes on the uSD
> connector on the bottom side of the iwg23s) I have come across an issue. The
> POC Control Register (IOCTRL6) of the RZ/G1C is
> structured in a completely different way from the other members of the RZ/G1
> family, only one bit is used to control the interface, as
> opposed to the usual one bit per pin layout.
> >
> > There are 3 possible ways to fix this:
> > 1) keep the clk pin of the interface in a pin group on its own in the PFC
> > driver (which means I would need to drop this patch or
> rework the pin groups with an additional patch), specify
> SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, keep the clk pin in a
> device tree node on its own in the board specific device tree and specify
> power-source only within the device tree node containing
> the clk line. The SD card device tree node in the board specific device tree
> would look like the following:
> > ...
> > pinctrl-0 = <_pins>, <_pins_clk>;
> > pinctrl-1 = <_pins>, <_pins_clk_uhs>;
> > pinctrl-names = "default", "state_uhs";
> >
>
> That matches the datasheet, which says the bit is for the CLK line,
> but that can't
> be true, as the voltage selection should affect other lines, too.
>
> > 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to the
> > interface, keep the SD card pin groups as specified by
> this patch, map all of the pins to the same bit in the POC register (as per
> pin_to_pocctrl is concerned), and the board specific device
> tree definitions would look like every other RZ/G1 or R-Car Gen2 boards that
> support SDR*
> > The only downside would be that the kernel would read-modify-write the POC
> > Control Register with the same value for every line in
> the interface.
>
> This looks the most sensible solution to me: just map in your
> .pin_to_pocctrl() method
> all pins of the interface to the single bit.
>
> > 3) specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, come up with
> > another macro for the other lines, keep the pin
> groups as specified by this patch, modify the logic of sh_pfc_pinconf_set and
> sh_pfc_pinconf_validate, and the board specific device
> tree would look like any other RZ/G1 or R-Car Gen2 board that supports SDR*
>
> This looks overly complex.
> So .pin_to_pocctrl() would need to return "ignore" for the other pins,
> which can work easily for the "set" case, but not for the "get" case.
>
> > I am not particularly enthusiastic about option 3), but option 1) and
> > option 2) seem equally sound to me.
> >
> > What do you think about this?
>
> I'd go for option 2.
Thank you for your advice, I am going to send a series implementing "option 2"
shortly.
Thanks,
Fab
>
> Wolfram: what do you think?
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
[PATCH] drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled
From: Hoan Nguyen An
Skip return EPROBE_DEFER when DRM_RCAR_DW_HDMI is disabled in case HDMI
initialize.
At this time, the rcar-du driver not be able to successfully initialize
if disable DRM_RCAR_DW_HDMI (rcar_du_probe return error),
so can not use other features such as RGB Analog, this patch to fix.
Signed-off-by: Hoan Nguyen An
---
drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index f9c933d..4dbc508 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -66,8 +66,15 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
/* Locate the DRM bridge from the encoder DT node. */
bridge = of_drm_find_bridge(enc_node);
if (!bridge) {
+#if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI)
ret = -EPROBE_DEFER;
goto done;
+#else
+ if (output == RCAR_DU_OUTPUT_HDMI0 ||
+ output == RCAR_DU_OUTPUT_HDMI1)
+ ret = 0;
+ goto done;
+#endif
}
ret = drm_encoder_init(rcdu->ddev, encoder, _funcs,
--
2.7.4
[PATCH] drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled
From: Hoan Nguyen An Skip return EPROBE_DEFER when DRM_RCAR_DW_HDMI is disabled in case HDMI initialize. At this time, the rcar-du driver not be able to successfully initialize if disable DRM_RCAR_DW_HDMI (rcar_du_probe return error), so can not use other features such as RGB Analog, this patch to fix. Hoan Nguyen An (1): drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 7 +++ 1 file changed, 7 insertions(+) -- 2.7.4
Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support
On 9/21/2018 10:35 AM, Simon Horman wrote:
Describe TPU in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
Simon Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77970.dtsi |8
arch/arm64/boot/dts/renesas/r8a77980.dtsi |9 +
2 files changed, 17 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -614,6 +614,14 @@
status = "disabled";
};
+ tpu: pwm@e6e8 {
+ compatible = "renesas,tpu-r8a77970", "renesas,tpu";
Oops, forgot to document the SoC specific binding...
I'm still not seeing the binding in my inbox.
> Could you post it or point me to a link to it?
Because I still haven't posted it. It turned out the bindings doc needs
some fixing 1st... :-/
+ reg = <0 0xe6e8 0 0x100>;
This register range seems a little small.
From my reading of the documentation 0x148 would be a more obvious choice.
Yeah, I've noticed that too -- will be fixed in v2.
Is the driver only accessing registers in in the 0x100 range for some
reason?
Yes, the registers beyond 0x100 are for the step motor control...
[...]
MBR, Sergei
RE: [PATCH] arm64: dts: renesas: revise properties for usb 2.0
Hi Simon-san, > From: Simon Horman, Sent: Friday, September 21, 2018 4:37 PM > > On Thu, Sep 20, 2018 at 05:55:00AM +, Yoshihiro Shimoda wrote: > > Hi Simon-san, > > > > > From: Simon Horman, Sent: Wednesday, September 5, 2018 7:33 PM > > > > > > On Fri, Aug 31, 2018 at 05:20:51PM +0900, Yoshihiro Shimoda wrote: > > > > R-Car Gen3 needs to enable/deassert clocks/resets of both usb 2.0 > > > > host (included phy) and peripheral. Otherwise, other side device > > > > cannot work correctly. So, this patch revises properties of clocks > > > > and resets. After that, each device driver can enable/deassert > > > > clocks/resets by its self. > > > > > > > > Notes: > > > > - To work the renesas_usbhs driver correctly when host side drivers > > > >are disabled and the renesas_usbhs driver doesn't have multiple > > > >clock management, this patch doesn't change the order of the clocks > > > >property in each hsusb node. > > > > - This patch doesn't have any side-effects even if the renesas_usbhs > > > >driver doesn't have reset_control and multiple clock management. > > > > > > > > Signed-off-by: Yoshihiro Shimoda > > > > > > Thanks Shimoda-san, > > > > > > This looks fine to me but I will wait to see if there are other reviews > > > before applying. > > > > > > Reviewed-by: Simon Horman > > > > Thank you for your review! > > However, since clock-names will be not used by renesas_usbhs driver, > > I'll submit v2 patch to remove the properties. > > Thanks, I'll wait for v2. I submitted v2 patch: https://patchwork.kernel.org/patch/10609245/ Best regards, Yoshihiro Shimoda
[PATCH v2] arm64: dts: renesas: revise properties for R-Car Gen3 SoCs' usb 2.0
R-Car Gen3 SoCs need to enable/deassert clocks/resets of both usb 2.0 host (included phy) and peripheral. Otherwise, other side device cannot work correctly. So, this patch revises properties of clocks and resets. After that, each device driver can enable/deassert clocks/resets by its self. Notes: - To work the renesas_usbhs driver correctly when host side drivers are disabled and the renesas_usbhs driver doesn't have multiple clock management, this patch doesn't change the order of the clocks property in each hsusb node. - This patch doesn't have any side-effects even if the renesas_usbhs driver doesn't have reset_control and multiple clock management. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Simon Horman --- This patch is based on the renesas.git / renesas-devel-20180919-v4.19-rc4 tag. This patch is related to the following patches which will be merged into v4.20: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-testing=0e4aeab775f9e9358c4bc522b87e9f6e2cfe0973 https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-testing=c29e240484ea17c756455149348e59523f462993 https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-testing=f181dbb4824130e84f46e5be5b49cf6456f96683 https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-testing=8e0d368a59bf87efa5ee4daea142527d01447864 https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-testing=3df0e240caba641e0d70640e3baf34d34c105176 Changes from v1: - Revise the subject and log a little. - Remove clock-names. - Add Simon-san's Reviewed-by. arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 +++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 12 ++-- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 12 ++-- 5 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 83077fd..b5f2273 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -697,7 +697,7 @@ "renesas,rcar-gen3-usbhs"; reg = <0 0xe659 0 0x100>; interrupts = ; - clocks = < CPG_MOD 704>; + clocks = < CPG_MOD 704>, < CPG_MOD 703>; dmas = <_dmac0 0>, <_dmac0 1>, <_dmac1 0>, <_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; @@ -705,7 +705,7 @@ phys = <_phy0>; phy-names = "usb"; power-domains = < R8A7795_PD_ALWAYS_ON>; - resets = < 704>; + resets = < 704>, < 703>; status = "disabled"; }; @@ -714,7 +714,7 @@ "renesas,rcar-gen3-usbhs"; reg = <0 0xe659c000 0 0x100>; interrupts = ; - clocks = < CPG_MOD 705>; + clocks = < CPG_MOD 705>, < CPG_MOD 700>; dmas = <_dmac2 0>, <_dmac2 1>, <_dmac3 0>, <_dmac3 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; @@ -722,7 +722,7 @@ phys = <_phy3>; phy-names = "usb"; power-domains = < R8A7795_PD_ALWAYS_ON>; - resets = < 705>; + resets = < 705>, < 700>; status = "disabled"; }; @@ -2097,11 +2097,11 @@ compatible = "generic-ohci"; reg = <0 0xee08 0 0x100>; interrupts = ; - clocks = < CPG_MOD 703>; + clocks = < CPG_MOD 703>, < CPG_MOD 704>; phys = <_phy0>; phy-names = "usb"; power-domains = < R8A7795_PD_ALWAYS_ON>; - resets = < 703>; + resets = < 703>, < 704>; status = "disabled"; }; @@ -2133,11 +2133,11 @@ compatible = "generic-ohci"; reg = <0 0xee0e 0 0x100>; interrupts = ; - clocks = < CPG_MOD 700>; + clocks = < CPG_MOD 700>, < CPG_MOD 705>; phys = <_phy3>; phy-names = "usb"; power-domains = < R8A7795_PD_ALWAYS_ON>; - resets = < 700>; + resets = < 700>, < 705>; status =
[ANNOUNCE] Renesas tree closing for v4.20
Hi, I would like to stop accepting non-bug-fix patches for v4.20 on Wednesday 26th September (next week) and get the last pull requests posted by the end of next week. This is in order for them to be sent before the release of v4.19-rc6, the deadline set by the ARM SoC maintainers. As patches should ideally progress from the renesas tree into linux-next before sending pull requests there is a few days lead time involved. Once the tree has closed for v4.20 I intend to begin queueing up patches for v4.21 as they are ready. Happy hacking!
Re: [PATCH] arm64: dts: renesas: revise properties for usb 2.0
On Thu, Sep 20, 2018 at 05:55:00AM +, Yoshihiro Shimoda wrote: > Hi Simon-san, > > > From: Simon Horman, Sent: Wednesday, September 5, 2018 7:33 PM > > > > On Fri, Aug 31, 2018 at 05:20:51PM +0900, Yoshihiro Shimoda wrote: > > > R-Car Gen3 needs to enable/deassert clocks/resets of both usb 2.0 > > > host (included phy) and peripheral. Otherwise, other side device > > > cannot work correctly. So, this patch revises properties of clocks > > > and resets. After that, each device driver can enable/deassert > > > clocks/resets by its self. > > > > > > Notes: > > > - To work the renesas_usbhs driver correctly when host side drivers > > >are disabled and the renesas_usbhs driver doesn't have multiple > > >clock management, this patch doesn't change the order of the clocks > > >property in each hsusb node. > > > - This patch doesn't have any side-effects even if the renesas_usbhs > > >driver doesn't have reset_control and multiple clock management. > > > > > > Signed-off-by: Yoshihiro Shimoda > > > > Thanks Shimoda-san, > > > > This looks fine to me but I will wait to see if there are other reviews > > before applying. > > > > Reviewed-by: Simon Horman > > Thank you for your review! > However, since clock-names will be not used by renesas_usbhs driver, > I'll submit v2 patch to remove the properties. Thanks, I'll wait for v2.
Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support
On Wed, Sep 19, 2018 at 11:21:49PM +0300, Sergei Shtylyov wrote:
> On 09/19/2018 11:02 PM, Sergei Shtylyov wrote:
>
> > Describe TPU in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov
> > Signed-off-by: Sergei Shtylyov
> >
> > ---
> > This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
> > Simon Horman's 'renesas.git' repo.
> >
> > arch/arm64/boot/dts/renesas/r8a77970.dtsi |8
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi |9 +
> > 2 files changed, 17 insertions(+)
> >
> > Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > ===
> > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > @@ -614,6 +614,14 @@
> > status = "disabled";
> > };
> >
> > + tpu: pwm@e6e8 {
> > + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
>
> Oops, forgot to document the SoC specific binding...
I'm still not seeing the binding in my inbox.
Could you post it or point me to a link to it?
>
> > + reg = <0 0xe6e8 0 0x100>;
This register range seems a little small.
>From my reading of the documentation 0x148 would be a more obvious choice.
Is the driver only accessing registers in in the 0x100 range for some
reason?
> > + clocks = < CPG_MOD 304>;
> > + power-domains = < R8A77970_PD_ALWAYS_ON>;
> > + #pwm-cells = <4>;
> > + status = "disabled";
> > + };
> >
> > vin0: video@e6ef {
> > compatible = "renesas,vin-r8a77970";
> > Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > ===
> > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > @@ -666,6 +666,15 @@
> > status = "disabled";
> > };
> >
> > + tpu: pwm@e6e8 {
> > + compatible = "renesas,tpu-r8a7798", "renesas,tpu";
>
>Same here. Plus forgot a zero at the end. :-/
>
> > + reg = <0 0xe6e8 0 0x100>;
> > + clocks = < CPG_MOD 304>;
> > + power-domains = < R8A77980_PD_ALWAYS_ON>;
> > + #pwm-cells = <4>;
> > + status = "disabled";
> > + };
> > +
> > vin0: video@e6ef {
> > compatible = "renesas,vin-r8a77980";
> > reg = <0 0xe6ef 0 0x1000>;
> >
>
> MBR, Sergei
>
Re: [PATCH] clk: renesas: r8a77970: add TPU clock
On Wed, Sep 19, 2018 at 09:10:40PM +0300, Sergei Shtylyov wrote:
> The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
> Matsushita, it was added in a later BSP version...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
>
> ---
> This patch is against the 'clk-renesas' branch of Geert's
> 'renesas-drivers.git'
> repo...
>
> drivers/clk/renesas/r8a77970-cpg-mssr.c |1 +
> 1 file changed, 1 insertion(+)
>
> Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
> ===
> --- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c
> +++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c
> @@ -127,6 +127,7 @@ static const struct mssr_mod_clk r8a7797
> DEF_MOD("cmt2", 301, R8A77970_CLK_R),
> DEF_MOD("cmt1", 302, R8A77970_CLK_R),
> DEF_MOD("cmt0", 303, R8A77970_CLK_R),
> + DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
> DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
> DEF_MOD("rwdt", 402, R8A77970_CLK_R),
> DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
>
Re: [PATCH] clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
On Wed, Sep 19, 2018 at 04:50:42PM +0200, Geert Uytterhoeven wrote:
> PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
> ---
> To be queued in clk-renesas-for-v4.20.
>
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 7e000d0705891a3f..9eb80180eea0b1a6 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[]
> __initconst = {
> /*
> * MD19 EXTAL (MHz) PLL0PLL1PLL3
> *
> - * 0 48 x 1 x100/4 x100/3 x100/3
> - * 1 48 x 1 x100/4 x100/3 x58/3
> + * 0 48 x 1 x100/1 x100/3 x100/3
> + * 1 48 x 1 x100/1 x100/3 x58/3
> */
> #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
>
> --
> 2.17.1
>
Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU core
Hi Fabrizio, Hi Geert, On Wed, Sep 19, 2018 at 10:21:13AM +, Fabrizio Castro wrote: > Hello Geert, > > Thank you for your feedback. > > > Subject: Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU > > core > > > > Perhaps "ARM: dts: r8a77470: Add SMP support"? > > Your proposal is with me, Simon do you want me to send a v2 for this? Thanks, I have applied this for v4.20 with the updated subject and Geert's review tag. > > > > On Mon, Sep 17, 2018 at 10:44 AM Fabrizio Castro > > wrote: > > > Add DT node for the Advanced Power Management Unit (APMU), add the > > > second CPU core, and use "renesas,apmu" as "enable-method". > > > > > > Signed-off-by: Fabrizio Castro > > > Reviewed-by: Biju Das > > > > Reviewed-by: Geert Uytterhoeven ... On Wed, Sep 19, 2018 at 10:24:00AM +, Fabrizio Castro wrote: > Hello Simon, > > Thank you for your feedback. > > > Subject: Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU > > core > > > > On Mon, Sep 17, 2018 at 10:53:16AM +0200, Geert Uytterhoeven wrote: > > > Perhaps "ARM: dts: r8a77470: Add SMP support"? > > > > > > On Mon, Sep 17, 2018 at 10:44 AM Fabrizio Castro > > > wrote: > > > > Add DT node for the Advanced Power Management Unit (APMU), add the > > > > second CPU core, and use "renesas,apmu" as "enable-method". > > > > > > > > Signed-off-by: Fabrizio Castro > > > > Reviewed-by: Biju Das > > > > > > Reviewed-by: Geert Uytterhoeven > > > > I would like to ask to what extent this has been tested with respect to > > CPU hotplug, suspend to RAM, and combinations thereof. > > Both CPU hotplug and STR were tested on their own and combined, I haven't > encountered any issue so far. On Wed, Sep 19, 2018 at 10:32:24AM +, Fabrizio Castro wrote: > Hello Simon, > > Thank you for your feedback. > > > Subject: Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU > > core > > > > On Wed, Sep 19, 2018 at 10:25:42AM +0200, Simon Horman wrote: > > > On Mon, Sep 17, 2018 at 10:53:16AM +0200, Geert Uytterhoeven wrote: > > > > Perhaps "ARM: dts: r8a77470: Add SMP support"? > > > > > > > > On Mon, Sep 17, 2018 at 10:44 AM Fabrizio Castro > > > > wrote: > > > > > Add DT node for the Advanced Power Management Unit (APMU), add the > > > > > second CPU core, and use "renesas,apmu" as "enable-method". > > > > > > > > > > Signed-off-by: Fabrizio Castro > > > > > Reviewed-by: Biju Das > > > > > > > > Reviewed-by: Geert Uytterhoeven > > > > > > I would like to ask to what extent this has been tested with respect to > > > CPU hotplug, suspend to RAM, and combinations thereof. > > > > And any details of firmware, bootloader, ... version stacks where this is > > supported. > > iW-RainboW-G23S SPI_LOADER(DDR3) V1.00 2016.03.25 > U-Boot 2013.01.01-gaa28b1d-dirty (Feb 01 2018 - 22:55:39) > > # cat /sys/devices/soc0/revision > ES2.0 > > I hope this helps. Thanks for your follow-up on the testing and environment, it does indeed help to give me confidence when applying this patch. ...
