Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Simon Horman]

On Wed, Aug 30, 2017 at 11:09:44AM +0200, Geert Uytterhoeven wrote:
> Hi Dirk,
> 
> On Tue, Aug 29, 2017 at 12:36 PM, Dirk Behme  wrote:
> > On 29.08.2017 11:44, Geert Uytterhoeven wrote:
> >> On Tue, Aug 29, 2017 at 11:15 AM, Dirk Behme 
> >> wrote:
> >>>
> >>> But ZG and with this module clock #112 is still missing, no?
> >>>
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e
> >>>
> >>>
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043
> >>
> >>
> >> The ZG bits in the FRQCRB register are documented to exist on R-Car D3
> >> only.
> >
> > ... what contradicts
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043
> >
> > and the 3DGE module clock in e.g. MSTPSR1 which is documented for H3 and
> > M3-W, too, and Table 8.1a List of Clocks [R-Car H3] ZG -> 3DGE etc.
> 
> That commit doesn't use CLK_TYPE_GEN3_ZG, but models ZG as PLL4/4,
> which matches the block diagram and the list of clocks.
> So that one is acceptable (modulo upstream (non)use of  the 3DGE module?).

I won't stand in the way of adding ZG support on the basis of non-use.

> Later, ZG is changed to use the non-documented bits, cfr.
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=054863e7a5855be9b4652c588c140d49bede4dc4
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds
> 

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Geert Uytterhoeven]

Hi Dirk,

On Tue, Aug 29, 2017 at 12:36 PM, Dirk Behme  wrote:
> On 29.08.2017 11:44, Geert Uytterhoeven wrote:
>> On Tue, Aug 29, 2017 at 11:15 AM, Dirk Behme 
>> wrote:
>>>
>>> But ZG and with this module clock #112 is still missing, no?
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e
>>>
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043
>>
>>
>> The ZG bits in the FRQCRB register are documented to exist on R-Car D3
>> only.
>
> ... what contradicts
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043
>
> and the 3DGE module clock in e.g. MSTPSR1 which is documented for H3 and
> M3-W, too, and Table 8.1a List of Clocks [R-Car H3] ZG -> 3DGE etc.

That commit doesn't use CLK_TYPE_GEN3_ZG, but models ZG as PLL4/4,
which matches the block diagram and the list of clocks.
So that one is acceptable (modulo upstream (non)use of  the 3DGE module?).

Later, ZG is changed to use the non-documented bits, cfr.
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=054863e7a5855be9b4652c588c140d49bede4dc4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Dirk Behme]

On 30.08.2017 08:48, Simon Horman wrote:

On Tue, Aug 29, 2017 at 12:36:50PM +0200, Dirk Behme wrote:

On 29.08.2017 11:44, Geert Uytterhoeven wrote:

Hi Dirk,

On Tue, Aug 29, 2017 at 11:15 AM, Dirk Behme  wrote:

But ZG and with this module clock #112 is still missing, no?

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043


The ZG bits in the FRQCRB register are documented to exist on R-Car D3
only.



... what contradicts

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043


Yes, there does seem to be a contradiction there.


and the 3DGE module clock in e.g. MSTPSR1 which is documented for H3 and
M3-W, too, and Table 8.1a List of Clocks [R-Car H3] ZG -> 3DGE etc.


Geert may have a different opinion but mine is not to add clocks
for which we don't have a near-term use in mainline.



In my opinion it would reduce the number of non-mainline patches needed 
and with this ease the use of mainline for nearly no cost.


There is always a discussion like "uh, we can't use mainline because it 
doesn't support xx (add a random number > 0) features and we have to 
apply xx (add a random number > 0) patches to make it work" I'd like to 
improve.


Best regards

Dirk

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Simon Horman]

On Tue, Aug 29, 2017 at 12:36:50PM +0200, Dirk Behme wrote:
> On 29.08.2017 11:44, Geert Uytterhoeven wrote:
> >Hi Dirk,
> >
> >On Tue, Aug 29, 2017 at 11:15 AM, Dirk Behme  wrote:
> >>But ZG and with this module clock #112 is still missing, no?
> >>
> >>https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e
> >>
> >>https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043
> >
> >The ZG bits in the FRQCRB register are documented to exist on R-Car D3
> >only.
> 
> 
> ... what contradicts
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043

Yes, there does seem to be a contradiction there.

> and the 3DGE module clock in e.g. MSTPSR1 which is documented for H3 and
> M3-W, too, and Table 8.1a List of Clocks [R-Car H3] ZG -> 3DGE etc.

Geert may have a different opinion but mine is not to add clocks
for which we don't have a near-term use in mainline.

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Dirk Behme]

On 29.08.2017 11:44, Geert Uytterhoeven wrote:

Hi Dirk,

On Tue, Aug 29, 2017 at 11:15 AM, Dirk Behme  wrote:

But ZG and with this module clock #112 is still missing, no?

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043


The ZG bits in the FRQCRB register are documented to exist on R-Car D3
only.



... what contradicts

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043

and the 3DGE module clock in e.g. MSTPSR1 which is documented for H3 and 
M3-W, too, and Table 8.1a List of Clocks [R-Car H3] ZG -> 3DGE etc.


Best regards

Dirk

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Geert Uytterhoeven]

Hi Dirk,

On Tue, Aug 29, 2017 at 11:15 AM, Dirk Behme  wrote:
> But ZG and with this module clock #112 is still missing, no?
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043

The ZG bits in the FRQCRB register are documented to exist on R-Car D3
only.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Dirk Behme]

On 29.08.2017 10:01, Geert Uytterhoeven wrote:

Hi Dirk,

On Tue, Aug 29, 2017 at 9:51 AM, Dirk Behme  wrote:

as mentioned previously since ages I'm back looking at the RCar3 status in
recent mainline (4.13-rc7). While doing so, it looks to me that some Z*
clock patches from recent BSP

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.9/rcar-3.5.8

are not in mainline clock configuration, yet. E.g.:

Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
Takeshi Kihara | clk: renesas: r8a7795: Add Z2 clock
Takeshi Kihara | clk: renesas: r8a7795: Add Z clock
Takeshi Kihara | clk: renesas: rcar-gen3: Adjust output of PLL4 as 3DGE
clock divider input
Takeshi Kihara | clk: renesas: rcar-gen3: Add ZG clock divider support
Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clock errata workaround in
PLL0 clk driver
Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clk driver support
Dien Pham | clk: renesas: rcar-gen3: Adjust output of PLL0, PLL2 as
SYSC-CPUs input
Takeshi Kihara | clk: renesas: rcar-gen3: Add Z2 clock divider support
Takeshi Kihara | clk: renesas: rcar-gen3: Add Z clock divider support

Are there any plans to pick these, already? Or, if not, would it be fine to
pick them from the BSP and just submit them here? Or is some major rework
needed?


Yes, this is WIP, cfr. "[PATCH v2 0/6] clk: renesas: r8a779[56]: Add Z and Z2
clock support" (https://www.spinics.net/lists/arm-kernel/msg602197.html).



Ok, many thanks! :)

But ZG and with this module clock #112 is still missing, no?

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=aa7b99b06d280e4151e

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?h=v4.9/rcar-3.5.8=a03bfd8abc9572800fb5043

Best regards

Dirk

Re: clk: renesas: rcar-gen3: Status of Z* clocks?

[Geert Uytterhoeven]

Hi Dirk,

On Tue, Aug 29, 2017 at 9:51 AM, Dirk Behme  wrote:
> as mentioned previously since ages I'm back looking at the RCar3 status in
> recent mainline (4.13-rc7). While doing so, it looks to me that some Z*
> clock patches from recent BSP
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.9/rcar-3.5.8
>
> are not in mainline clock configuration, yet. E.g.:
>
> Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
> Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
> Takeshi Kihara | clk: renesas: r8a7795: Add Z2 clock
> Takeshi Kihara | clk: renesas: r8a7795: Add Z clock
> Takeshi Kihara | clk: renesas: rcar-gen3: Adjust output of PLL4 as 3DGE
> clock divider input
> Takeshi Kihara | clk: renesas: rcar-gen3: Add ZG clock divider support
> Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clock errata workaround in
> PLL0 clk driver
> Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clk driver support
> Dien Pham | clk: renesas: rcar-gen3: Adjust output of PLL0, PLL2 as
> SYSC-CPUs input
> Takeshi Kihara | clk: renesas: rcar-gen3: Add Z2 clock divider support
> Takeshi Kihara | clk: renesas: rcar-gen3: Add Z clock divider support
>
> Are there any plans to pick these, already? Or, if not, would it be fine to
> pick them from the BSP and just submit them here? Or is some major rework
> needed?

Yes, this is WIP, cfr. "[PATCH v2 0/6] clk: renesas: r8a779[56]: Add Z and Z2
clock support" (https://www.spinics.net/lists/arm-kernel/msg602197.html).

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

clk: renesas: rcar-gen3: Status of Z* clocks?

[Dirk Behme]

Hi,

as mentioned previously since ages I'm back looking at the RCar3 status 
in recent mainline (4.13-rc7). While doing so, it looks to me that some 
Z* clock patches from recent BSP


https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.9/rcar-3.5.8

are not in mainline clock configuration, yet. E.g.:

Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
Takeshi Kihara | clk: renesas: r8a7795: Add ZG clock
Takeshi Kihara | clk: renesas: r8a7795: Add Z2 clock
Takeshi Kihara | clk: renesas: r8a7795: Add Z clock
Takeshi Kihara | clk: renesas: rcar-gen3: Adjust output of PLL4 as 3DGE 
clock divider input

Takeshi Kihara | clk: renesas: rcar-gen3: Add ZG clock divider support
Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clock errata workaround in 
PLL0 clk driver

Dien Pham | clk: renesas: rcar-gen3: Add PLL0 clk driver support
Dien Pham | clk: renesas: rcar-gen3: Adjust output of PLL0, PLL2 as 
SYSC-CPUs input

Takeshi Kihara | clk: renesas: rcar-gen3: Add Z2 clock divider support
Takeshi Kihara | clk: renesas: rcar-gen3: Add Z clock divider support

Are there any plans to pick these, already? Or, if not, would it be fine 
to pick them from the BSP and just submit them here? Or is some major 
rework needed?


Best regards

Dirk