Re: [PATCH 08/12] gpio/samsung: add GPC4 bank instance
On 4/17/12, Thomas Abraham wrote:
> From: Sangsu Park
>
> Add GPC4 bank instance which is included in rev1 of Exynos5.
>
> Cc: Grant Likely
> Signed-off-by: Sangsu Park
> ---
> arch/arm/mach-exynos/include/mach/gpio.h |9 ++---
> drivers/gpio/gpio-samsung.c |8
> 2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
> b/arch/arm/mach-exynos/include/mach/gpio.h
> index d7498af..df5612b 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -153,10 +153,11 @@ enum exynos4_gpio_number {
> #define EXYNOS5_GPIO_B2_NR (4)
> #define EXYNOS5_GPIO_B3_NR (4)
> #define EXYNOS5_GPIO_C0_NR (7)
> -#define EXYNOS5_GPIO_C1_NR (7)
> +#define EXYNOS5_GPIO_C1_NR (4)
> #define EXYNOS5_GPIO_C2_NR (7)
> #define EXYNOS5_GPIO_C3_NR (7)
> -#define EXYNOS5_GPIO_D0_NR (8)
> +#define EXYNOS5_GPIO_C4_NR (8)
> +#define EXYNOS5_GPIO_D0_NR (4)
> #define EXYNOS5_GPIO_D1_NR (8)
> #define EXYNOS5_GPIO_Y0_NR (6)
> #define EXYNOS5_GPIO_Y1_NR (4)
> @@ -199,7 +200,8 @@ enum exynos5_gpio_number {
> EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
> EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
> EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
> - EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
> + EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
> + EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
> EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
> EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
> EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
> @@ -242,6 +244,7 @@ enum exynos5_gpio_number {
> #define EXYNOS5_GPC1(_nr)(EXYNOS5_GPIO_C1_START + (_nr))
> #define EXYNOS5_GPC2(_nr)(EXYNOS5_GPIO_C2_START + (_nr))
> #define EXYNOS5_GPC3(_nr)(EXYNOS5_GPIO_C3_START + (_nr))
> +#define EXYNOS5_GPC4(_nr)(EXYNOS5_GPIO_C4_START + (_nr))
> #define EXYNOS5_GPD0(_nr)(EXYNOS5_GPIO_D0_START + (_nr))
> #define EXYNOS5_GPD1(_nr)(EXYNOS5_GPIO_D1_START + (_nr))
> #define EXYNOS5_GPY0(_nr)(EXYNOS5_GPIO_Y0_START + (_nr))
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index 4627787..0153bb9 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
> },
> }, {
> .chip = {
> + .base = EXYNOS5_GPC4(0),
> + .ngpio = EXYNOS5_GPIO_C4_NR,
> + .label = "GPC4",
> + },
> + }, {
> + .chip = {
> .base = EXYNOS5_GPD0(0),
> .ngpio = EXYNOS5_GPIO_D0_NR,
> .label = "GPD0",
> @@ -2880,6 +2886,8 @@ static __init int samsung_gpiolib_init(void)
> for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
> chip->base = gpx_base;
>
> + exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
'11' seems dangerous. I think you add comments here and above to know
'11' meaning.
> +
> chip = exynos5_gpios_1;
> nr_chips = ARRAY_SIZE(exynos5_gpios_1);
>
> --
> 1.6.6.rc2
>
> --
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Re: [PATCH 07/12] ARM: Exynos5: Modify the GIC physical address for static io-mapping
Hi,
On 4/17/12, Thomas Abraham wrote:
> From: Changhwan Youn
>
> Adapt to changes in GIC physical address in rev1 of Exynos5.
Does it different from rev0 and rev1? and does it support the rev1 only?
Thank you,
Kyungmin Park
>
> Signed-off-by: Changhwan Youn
> ---
> arch/arm/mach-exynos/common.c |4 ++--
> arch/arm/mach-exynos/include/mach/map.h |4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 35ac675..457d031 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -265,12 +265,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
> }, {
> .virtual= (unsigned long)S5P_VA_GIC_CPU,
> .pfn= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
> - .length = SZ_64K,
> + .length = SZ_8K,
> .type = MT_DEVICE,
> }, {
> .virtual= (unsigned long)S5P_VA_GIC_DIST,
> .pfn= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
> - .length = SZ_64K,
> + .length = SZ_4K,
> .type = MT_DEVICE,
> },
> };
> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
> index 0e2292d..648d59b 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -78,8 +78,8 @@
>
> #define EXYNOS4_PA_GIC_CPU 0x1048
> #define EXYNOS4_PA_GIC_DIST 0x1049
> -#define EXYNOS5_PA_GIC_CPU 0x1048
> -#define EXYNOS5_PA_GIC_DIST 0x1049
> +#define EXYNOS5_PA_GIC_CPU 0x10482000
> +#define EXYNOS5_PA_GIC_DIST 0x10481000
>
> #define EXYNOS4_PA_COREPERI 0x1050
> #define EXYNOS4_PA_TWD 0x10500600
> --
> 1.6.6.rc2
>
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Re: [PATCH 06/12] rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support
Hi,
It's already merged with different patch,
#ifdef CONFIG_OF
static const struct of_device_id s3c_rtc_dt_match[] = {
{
.compatible = "samsung,s3c2410-rtc",
.data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
}, {
.compatible = "samsung,s3c2416-rtc",
.data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
}, {
.compatible = "samsung,s3c2443-rtc",
.data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
}, {
.compatible = "samsung,s3c6410-rtc",
.data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
},
{},
};
MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
#else
#define s3c_rtc_dt_match NULL
#endif
Thank you,
Kyungmin Park
On 4/17/12, Thomas Abraham wrote:
> From: Heiko Stuebner
>
> Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block)
> and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416)
> introduced build-failures with enabled CONFIG_USE_OF option.
>
> This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of
> the of_device_id.data property.
>
> Reported-by: Sylwester Nawrocki
> Signed-off-by: Heiko Stuebner
> ---
> drivers/rtc/rtc-s3c.c | 18 +-
> 1 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
> index 9ccea13..c792b6d 100644
> --- a/drivers/rtc/rtc-s3c.c
> +++ b/drivers/rtc/rtc-s3c.c
> @@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct
> platform_device *pdev)
> if (pdev->dev.of_node) {
> const struct of_device_id *match;
> match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
> - return match->data;
> + return (int)match->data;
> }
> #endif
> return platform_get_device_id(pdev)->driver_data;
> @@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device
> *pdev)
> #ifdef CONFIG_OF
> static const struct of_device_id s3c_rtc_dt_match[] = {
> {
> - .compatible = "samsung,s3c2410-rtc"
> - .data = TYPE_S3C2410,
> + .compatible = "samsung,s3c2410-rtc",
> + .data = (void *)TYPE_S3C2410,
> }, {
> - .compatible = "samsung,s3c2416-rtc"
> - .data = TYPE_S3C2416,
> + .compatible = "samsung,s3c2416-rtc",
> + .data = (void *)TYPE_S3C2416,
> }, {
> - .compatible = "samsung,s3c2443-rtc"
> - .data = TYPE_S3C2443,
> + .compatible = "samsung,s3c2443-rtc",
> + .data = (void *)TYPE_S3C2443,
> }, {
> - .compatible = "samsung,s3c6410-rtc"
> - .data = TYPE_S3C64XX,
> + .compatible = "samsung,s3c6410-rtc",
> + .data = (void *)TYPE_S3C64XX,
> },
> {},
> };
> --
> 1.6.6.rc2
>
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Re: [PATCH 03/12] ARM: Exynos5: Add watchdog timer clock instance
On 4/17/12, Thomas Abraham wrote:
> Add watchdog timer clock instance for Exynos5 watchdog controller.
>
> Signed-off-by: Thomas Abraham
> ---
> arch/arm/mach-exynos/clock-exynos5.c |5 +
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> b/arch/arm/mach-exynos/clock-exynos5.c
> index ad3bec4..662615d 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -474,6 +474,11 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peris_ctrl,
> .ctrlbit= (1 << 20),
> }, {
> + .name = "watchdog",
> + .parent = &exynos5_clk_aclk_66.clk,
> + .enable = exynos5_clk_ip_peris_ctrl,
> + .ctrlbit= (1 << 19),
Hi,
Can you place this in order? It has same "exynos5_clk_ip_peris_ctrl",
but located under (1 << 20).
Thank you,
Kyungmin Park
> + }, {
> .name = "hsmmc",
> .devname= "exynos4-sdhci.0",
> .parent = &exynos5_clk_aclk_200.clk,
> --
> 1.6.6.rc2
>
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[PATCH 12/12] ARM: Exynos5: Update device tree enabled machine file
Add AUXDATA for i2c and MDMA controllers of Exynos5.
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/mach-exynos5-dt.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c89..8adc061 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,9 +43,14 @@ static const struct of_dev_auxdata
exynos5250_auxdata_lookup[] __initconst = {
"exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
"exynos4210-uart.3", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+ "s3c2440-i2c.0", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+ "s3c2440-i2c.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.3", NULL),
{},
};
--
1.6.6.rc2
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[PATCH 11/12] ARM: Exynos5: Update device tree source files
Updated Exynos5 device tree source files to reflect changes in rev1 of
Exynos5 SoC. This includes new additions to the Exynos5 dtsi and SMDK5250 dts
files and few minor fixes.
Signed-off-by: Thomas Abraham
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 52 +
arch/arm/boot/dts/exynos5250.dtsi | 44 +++-
2 files changed, 65 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b..bcc4b89 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,56 @@
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192
console=ttySAC1,115200";
};
+
+ i2c@12C6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <2>;
+ gpios = <&gpb3 0 2 3 0>,
+ <&gpb3 1 2 3 0>;
+
+ eeprom@50 {
+ compatible = "samsung,s524ad0xd1";
+ reg = <0x50>;
+ };
+ };
+
+ i2c@12C7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <2>;
+ gpios = <&gpb3 2 2 3 0>,
+ <&gpb3 3 2 3 0>;
+
+ eeprom@51 {
+ compatible = "samsung,s524ad0xd1";
+ reg = <0x51>;
+ };
+ };
+
+ i2c@12C8 {
+ status = "disabled";
+ };
+
+ i2c@12C9 {
+ status = "disabled";
+ };
+
+ i2c@12CA {
+ status = "disabled";
+ };
+
+ i2c@12CB {
+ status = "disabled";
+ };
+
+ i2c@12CC {
+ status = "disabled";
+ };
+
+ i2c@12CD {
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index dfc4335..76b7dba 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
- gic:interrupt-controller@1049 {
+ gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x1049 0x1000>, <0x1048 0x100>;
+ reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
};
watchdog {
@@ -42,30 +42,6 @@
interrupts = <0 43 0>, <0 44 0>;
};
- sdhci@1220 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x1220 0x100>;
- interrupts = <0 75 0>;
- };
-
- sdhci@1221 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x1221 0x100>;
- interrupts = <0 76 0>;
- };
-
- sdhci@1222 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x1222 0x100>;
- interrupts = <0 77 0>;
- };
-
- sdhci@1223 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x1223 0x100>;
- interrupts = <0 78 0>;
- };
-
serial@12C0 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C0 0x100>;
@@ -157,13 +133,13 @@
interrupts = <0 35 0>;
};
- mdma0: pdma@1080 {
+ mdma0: mdma@1080 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x1080 0x1000>;
interrupts = <0 33 0>;
};
- mdma1: pdma@11C1 {
+ mdma1: mdma@11C1 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C1 0x1000>;
interrupts = <0 124 0>;
@@ -242,6 +218,12 @@
#gpio-cells = <4>;
};
+ gpc4: gpio-controller@114002E0 {
+ compatible = "samsung,exynos4-gpio";
+ reg = <0x114002E0 0x20>;
+ #gpio-cells = <4>;
+ };
+
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
@@ -388,19 +370,19 @@
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
- reg = <0x10D10040 0x20>;
+ reg = <0x10D10060 0x20>;
#gpio-ce
[PATCH 10/12] ARM: Exynos: Redefine IRQ_MCT_L0,1 definition
From: Changhwan Youn
Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of Exynos5.
Signed-off-by: Changhwan Youn
---
arch/arm/mach-exynos/include/mach/irqs.h |4 ++--
arch/arm/mach-exynos/mct.c | 17 +++--
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 1161675..86e75f5 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -320,6 +320,8 @@
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
+#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -399,8 +401,6 @@
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9..b601fb8 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct
clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
+ int mct_lx_irq;
mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct
clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
+ mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+ EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
- evt->irq = EXYNOS4_IRQ_MCT_L0;
- setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+ evt->irq = mct_lx_irq;
+ setup_irq(mct_lx_irq, &mct_tick0_event_irq);
} else {
+ mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+ EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
- evt->irq = EXYNOS4_IRQ_MCT_L1;
- setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
- irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+ evt->irq = mct_lx_irq;
+ setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+ irq_set_affinity(mct_lx_irq, cpumask_of(1));
}
} else {
enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
- if (soc_is_exynos4210())
+ if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
mct_int_type = MCT_INT_PPI;
--
1.6.6.rc2
--
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[PATCH 09/12] ARM: Exynos5: Add pre-divider and fout mux clocks for bpll and mpll
From: Kisoo Yu
The fout clock of BPLL and MPLL have a selectable source in rev1 of
Exynos5. The clock options are a fixed divided by 2 clock and the
output of the PLL itself. Add support for these new clock instances.
Signed-off-by: Kisoo Yu
---
arch/arm/mach-exynos/clock-exynos5.c | 73 +++-
arch/arm/mach-exynos/include/mach/regs-clock.h |2 +
arch/arm/plat-s5p/clock.c | 11
3 files changed, 74 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 0230ba8..3aa3fed 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,6 +165,39 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
};
+static struct clk clk_fout_bpll_div2 = {
+ .name = "fout_bpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_bpll_fout_list[] = {
+ [0] = &clk_fout_bpll_div2,
+ [1] = &clk_fout_bpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_bpll_fout = {
+ .sources= exynos5_clkset_mout_bpll_fout_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+ .clk= {
+ .name = "mout_bpll_fout",
+ },
+ .sources = &exynos5_clkset_mout_bpll_fout,
+ .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+ [0] = &clk_fin_bpll,
+ [1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+struct clksrc_sources clk_src_bpll = {
+ .sources= clk_src_bpll_list,
+ .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
+};
+
static struct clksrc_clk exynos5_clk_mout_bpll = {
.clk= {
.name = "mout_bpll",
@@ -207,11 +240,43 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
};
+static struct clk clk_fout_mpll_div2 = {
+ .name = "fout_mpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_mpll_fout_list[] = {
+ [0] = &clk_fout_mpll_div2,
+ [1] = &clk_fout_mpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_mpll_fout = {
+ .sources= exynos5_clkset_mout_mpll_fout_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+ .clk= {
+ .name = "mout_mpll_fout",
+ },
+ .sources = &exynos5_clkset_mout_mpll_fout,
+ .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+struct clksrc_sources exynos5_clk_src_mpll = {
+ .sources= exynos5_clk_src_mpll_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
- .sources = &clk_src_mpll,
+ .sources = &exynos5_clk_src_mpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
};
@@ -1033,10 +1098,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
&exynos5_clk_sclk_apll,
&exynos5_clk_mout_bpll,
+ &exynos5_clk_mout_bpll_fout,
&exynos5_clk_mout_bpll_user,
&exynos5_clk_mout_cpll,
&exynos5_clk_mout_epll,
&exynos5_clk_mout_mpll,
+ &exynos5_clk_mout_mpll_fout,
&exynos5_clk_mout_mpll_user,
&exynos5_clk_vpllsrc,
&exynos5_clk_sclk_vpll,
@@ -1101,6 +1168,8 @@ static struct clk *exynos5_clks[] __initdata = {
&exynos5_clk_sclk_hdmi27m,
&exynos5_clk_sclk_hdmiphy,
&clk_fout_bpll,
+ &clk_fout_bpll_div2,
+ &clk_fout_mpll_div2,
&clk_fout_cpll,
&exynos5_clk_armclk,
};
@@ -1266,8 +1335,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
clk_fout_apll.ops = &exynos5_fout_apll_ops;
clk_fout_bpll.rate = bpll;
+ clk_fout_bpll_div2.rate = bpll >> 1;
clk_fout_cpll.rate = cpll;
clk_fout_mpll.rate = mpll;
+ clk_fout_mpll_div2.rate = mpll >> 1;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h
b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e9..834ab17 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -318,6 +318,8 @@
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
+#define EXYNOS5_PLL_
[PATCH 08/12] gpio/samsung: add GPC4 bank instance
From: Sangsu Park
Add GPC4 bank instance which is included in rev1 of Exynos5.
Cc: Grant Likely
Signed-off-by: Sangsu Park
---
arch/arm/mach-exynos/include/mach/gpio.h |9 ++---
drivers/gpio/gpio-samsung.c |8
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498af..df5612b 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
#define EXYNOS5_GPIO_B2_NR (4)
#define EXYNOS5_GPIO_B3_NR (4)
#define EXYNOS5_GPIO_C0_NR (7)
-#define EXYNOS5_GPIO_C1_NR (7)
+#define EXYNOS5_GPIO_C1_NR (4)
#define EXYNOS5_GPIO_C2_NR (7)
#define EXYNOS5_GPIO_C3_NR (7)
-#define EXYNOS5_GPIO_D0_NR (8)
+#define EXYNOS5_GPIO_C4_NR (8)
+#define EXYNOS5_GPIO_D0_NR (4)
#define EXYNOS5_GPIO_D1_NR (8)
#define EXYNOS5_GPIO_Y0_NR (6)
#define EXYNOS5_GPIO_Y1_NR (4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
- EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+ EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+ EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 4627787..0153bb9 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
},
}, {
.chip = {
+ .base = EXYNOS5_GPC4(0),
+ .ngpio = EXYNOS5_GPIO_C4_NR,
+ .label = "GPC4",
+ },
+ }, {
+ .chip = {
.base = EXYNOS5_GPD0(0),
.ngpio = EXYNOS5_GPIO_D0_NR,
.label = "GPD0",
@@ -2880,6 +2886,8 @@ static __init int samsung_gpiolib_init(void)
for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
chip->base = gpx_base;
+ exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
+
chip = exynos5_gpios_1;
nr_chips = ARRAY_SIZE(exynos5_gpios_1);
--
1.6.6.rc2
--
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[PATCH 07/12] ARM: Exynos5: Modify the GIC physical address for static io-mapping
From: Changhwan Youn
Adapt to changes in GIC physical address in rev1 of Exynos5.
Signed-off-by: Changhwan Youn
---
arch/arm/mach-exynos/common.c |4 ++--
arch/arm/mach-exynos/include/mach/map.h |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 35ac675..457d031 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -265,12 +265,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
}, {
.virtual= (unsigned long)S5P_VA_GIC_CPU,
.pfn= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
- .length = SZ_64K,
+ .length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual= (unsigned long)S5P_VA_GIC_DIST,
.pfn= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
- .length = SZ_64K,
+ .length = SZ_4K,
.type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 0e2292d..648d59b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -78,8 +78,8 @@
#define EXYNOS4_PA_GIC_CPU 0x1048
#define EXYNOS4_PA_GIC_DIST0x1049
-#define EXYNOS5_PA_GIC_CPU 0x1048
-#define EXYNOS5_PA_GIC_DIST0x1049
+#define EXYNOS5_PA_GIC_CPU 0x10482000
+#define EXYNOS5_PA_GIC_DIST0x10481000
#define EXYNOS4_PA_COREPERI0x1050
#define EXYNOS4_PA_TWD 0x10500600
--
1.6.6.rc2
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[PATCH 06/12] rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support
From: Heiko Stuebner
Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block)
and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416)
introduced build-failures with enabled CONFIG_USE_OF option.
This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of
the of_device_id.data property.
Reported-by: Sylwester Nawrocki
Signed-off-by: Heiko Stuebner
---
drivers/rtc/rtc-s3c.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 9ccea13..c792b6d 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct
platform_device *pdev)
if (pdev->dev.of_node) {
const struct of_device_id *match;
match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
- return match->data;
+ return (int)match->data;
}
#endif
return platform_get_device_id(pdev)->driver_data;
@@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id s3c_rtc_dt_match[] = {
{
- .compatible = "samsung,s3c2410-rtc"
- .data = TYPE_S3C2410,
+ .compatible = "samsung,s3c2410-rtc",
+ .data = (void *)TYPE_S3C2410,
}, {
- .compatible = "samsung,s3c2416-rtc"
- .data = TYPE_S3C2416,
+ .compatible = "samsung,s3c2416-rtc",
+ .data = (void *)TYPE_S3C2416,
}, {
- .compatible = "samsung,s3c2443-rtc"
- .data = TYPE_S3C2443,
+ .compatible = "samsung,s3c2443-rtc",
+ .data = (void *)TYPE_S3C2443,
}, {
- .compatible = "samsung,s3c6410-rtc"
- .data = TYPE_S3C64XX,
+ .compatible = "samsung,s3c6410-rtc",
+ .data = (void *)TYPE_S3C64XX,
},
{},
};
--
1.6.6.rc2
--
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[PATCH 05/12] ARM: Exynos5: Add MDMA0 clock instance
Add clock instance for MDMA0 controller.
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/clock-exynos5.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index fb95e9b..0230ba8 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -768,9 +768,14 @@ static struct clk exynos5_clk_pdma = {
.ctrlbit= (1 << 1),
};
+static struct clk exynos5_clk_mdma0 = {
+ .name = "dma",
+ .enable = exynos5_clk_ip_acp_ctrl,
+ .ctrlbit= (1 << 1),
+};
+
static struct clk exynos5_clk_mdma1 = {
.name = "dma",
- .devname= "dma-pl330.2",
.enable = exynos5_clk_ip_gen_ctrl,
.ctrlbit= (1 << 4),
};
@@ -1057,6 +1062,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
static struct clk *exynos5_clk_cdev[] = {
&exynos5_clk_pdma,
+ &exynos5_clk_mdma0,
&exynos5_clk_mdma1,
};
@@ -1082,7 +1088,8 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2",
&exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma),
- CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+ CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma0),
+ CLKDEV_INIT("dma-pl330.3", "apb_pclk", &exynos5_clk_mdma1),
};
static unsigned long exynos5_epll_get_rate(struct clk *clk)
--
1.6.6.rc2
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[PATCH 04/12] ARM: Exynos5: Remove duplicated instantiation of pdma clock
The clock of both the peripheral dma controllers is controlled by a single
clock gate. Hence remove the duplicate instantiation of the pdma clock.
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/clock-exynos5.c | 17 -
1 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 662615d..fb95e9b 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -762,16 +762,8 @@ static struct clk exynos5_init_clocks_on[] = {
}
};
-static struct clk exynos5_clk_pdma0 = {
+static struct clk exynos5_clk_pdma = {
.name = "dma",
- .devname= "dma-pl330.0",
- .enable = exynos5_clk_ip_fsys_ctrl,
- .ctrlbit= (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
- .name = "dma",
- .devname= "dma-pl330.1",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1 << 1),
};
@@ -1064,8 +1056,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
};
static struct clk *exynos5_clk_cdev[] = {
- &exynos5_clk_pdma0,
- &exynos5_clk_pdma1,
+ &exynos5_clk_pdma,
&exynos5_clk_mdma1,
};
@@ -1089,8 +1080,8 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2",
&exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2",
&exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2",
&exynos5_clk_sclk_mmc3.clk),
- CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
- CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+ CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma),
+ CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
};
--
1.6.6.rc2
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[PATCH 03/12] ARM: Exynos5: Add watchdog timer clock instance
Add watchdog timer clock instance for Exynos5 watchdog controller.
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/clock-exynos5.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index ad3bec4..662615d 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -474,6 +474,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit= (1 << 20),
}, {
+ .name = "watchdog",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peris_ctrl,
+ .ctrlbit= (1 << 19),
+ }, {
.name = "hsmmc",
.devname= "exynos4-sdhci.0",
.parent = &exynos5_clk_aclk_200.clk,
--
1.6.6.rc2
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[PATCH 02/12] ARM: Exynos5: Fix incorrect initialization of GIC
Use the of_irq_init() call to setup the gic which also properly registers
the gic device node pointer with gic irq domain, without which all interrupt
specifier translations for gic fail.
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/common.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 636d5f8..35ac675 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -532,11 +532,12 @@ void __init exynos4_init_irq(void)
s5p_init_irq(NULL, 0);
}
+#ifdef CONFIG_ARCH_EXYNOS5
void __init exynos5_init_irq(void)
{
int irq;
- gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ of_irq_init(exynos4_dt_irq_match);
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
@@ -551,6 +552,7 @@ void __init exynos5_init_irq(void)
*/
s5p_init_irq(NULL, 0);
}
+#endif /* CONFIG_ARCH_EXYNOS5 */
struct bus_type exynos4_subsys = {
.name = "exynos4-core",
--
1.6.6.rc2
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[PATCH 01/12] ARM: Exynos: Remove a new bus_type instance for Exynos5
A seperate bus_type instance is not required for Exynos5. The existing bus_type
instance used with Exynos4 is sufficient for both Exynos4 and Exynos5. This
also solves issue of uninitialized usage of exynos4_subsys in Exynos4 power
management code that is reused for Exynos5 also.
Signed-off-by: Thomas Abraham
---
arch/arm/mach-exynos/common.c | 19 ++-
1 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index e9e353b..636d5f8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -557,25 +557,13 @@ struct bus_type exynos4_subsys = {
.dev_name = "exynos4-core",
};
-struct bus_type exynos5_subsys = {
- .name = "exynos5-core",
- .dev_name = "exynos5-core",
-};
-
static struct device exynos4_dev = {
.bus= &exynos4_subsys,
};
-static struct device exynos5_dev = {
- .bus= &exynos5_subsys,
-};
-
static int __init exynos_core_init(void)
{
- if (soc_is_exynos5250())
- return subsys_system_register(&exynos5_subsys, NULL);
- else
- return subsys_system_register(&exynos4_subsys, NULL);
+ return subsys_system_register(&exynos4_subsys, NULL);
}
core_initcall(exynos_core_init);
@@ -662,10 +650,7 @@ static int __init exynos_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
- if (soc_is_exynos5250())
- return device_register(&exynos5_dev);
- else
- return device_register(&exynos4_dev);
+ return device_register(&exynos4_dev);
}
/* uart registration process */
--
1.6.6.rc2
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[PATCH 00/12] Updates for Exynos5250 Rev1.0 and device tree support
This patch series includes modifications to support Rev1.0 of Exynos5250 SoC and overrides the existing support for Rev0. It also includes basic device tree support (tested for UART, WDT, RTC, GPIO, I2C, GIC and DMA PL330). Changhwan Youn (2): ARM: Exynos5: Modify the GIC physical address for static io-mapping ARM: Exynos: Redefine IRQ_MCT_L0,1 definition Heiko Stuebner (1): rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support Kisoo Yu (1): ARM: Exynos5: Add pre-divider and fout mux clocks for bpll and mpll Sangsu Park (1): gpio/samsung: add GPC4 bank instance Thomas Abraham (7): ARM: Exynos: Remove a new bus_type instance for Exynos5 ARM: Exynos5: Fix incorrect initialization of GIC ARM: Exynos5: Add watchdog timer clock instance ARM: Exynos5: Remove duplicated instantiation of pdma clock ARM: Exynos5: Add MDMA0 clock instance ARM: Exynos5: Update device tree source files ARM: Exynos5: Update device tree enabled machine file arch/arm/boot/dts/exynos5250-smdk5250.dts | 52 + arch/arm/boot/dts/exynos5250.dtsi | 44 +++ arch/arm/mach-exynos/clock-exynos5.c | 98 +--- arch/arm/mach-exynos/common.c | 27 ++- arch/arm/mach-exynos/include/mach/gpio.h |9 ++- arch/arm/mach-exynos/include/mach/irqs.h |4 +- arch/arm/mach-exynos/include/mach/map.h|4 +- arch/arm/mach-exynos/include/mach/regs-clock.h |2 + arch/arm/mach-exynos/mach-exynos5-dt.c |7 ++- arch/arm/mach-exynos/mct.c | 17 +++-- arch/arm/plat-s5p/clock.c | 11 --- drivers/gpio/gpio-samsung.c|8 ++ drivers/rtc/rtc-s3c.c | 18 ++-- 13 files changed, 204 insertions(+), 97 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/2] regulator: add device tree support for max8997
On 17 April 2012 00:21, Mark Brown wrote: > On Sat, Mar 24, 2012 at 03:19:50PM +0530, Thomas Abraham wrote: >> Add device tree based discovery support for max8997. > > I tried to apply this but it's collided with some other changes in the > driver which have arrived in the meantime and the rejects were too large > to fix up. I suspect it's mostly just the change in parameters for > regulator_register(). Can you please regenerate against my current > topic/drivers branch? Hi Mark, Sure, I will do redo this patch based on your current 'topic/drivers' branch. Thanks, Thomas. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/2] regulator: add device tree support for max8997
On Sat, Mar 24, 2012 at 03:19:50PM +0530, Thomas Abraham wrote: > Add device tree based discovery support for max8997. I tried to apply this but it's collided with some other changes in the driver which have arrived in the meantime and the rejects were too large to fix up. I suspect it's mostly just the change in parameters for regulator_register(). Can you please regenerate against my current topic/drivers branch? signature.asc Description: Digital signature
Re: [PATCH v4 1/2] mfd: add irq domain support for max8997 interrupts
On Sat, Mar 24, 2012 at 03:19:49PM +0530, Thomas Abraham wrote: > Add irq domain support for max8997 interrupts. The reverse mapping method > used is linear mapping since the sub-drivers of max8997 such as regulator > and charger drivers can use the max8997 irq_domain to get the linux irq > number for max8997 interrupts. All uses of irq_base in platform data and > max8997 driver private data are removed. Applied, thanks. signature.asc Description: Digital signature
Re: [PATCH v4 1/2] mfd: add irq domain support for max8997 interrupts
Hi Mark, On Wed, Apr 04, 2012 at 10:22:57PM +0100, Mark Brown wrote: > On Sat, Mar 24, 2012 at 03:19:49PM +0530, Thomas Abraham wrote: > > Add irq domain support for max8997 interrupts. The reverse mapping method > > used is linear mapping since the sub-drivers of max8997 such as regulator > > and charger drivers can use the max8997 irq_domain to get the linux irq > > number for max8997 interrupts. All uses of irq_base in platform data and > > max8997 driver private data are removed. > > > Cc: MyungJoo Ham > > Signed-off-by: Thomas Abraham > > Acked-by: Grant Likely > > CCing in Samuel for the MFD review - review tends to be faster if you CC > maintainers! Samuel, there's a followup patch for the regulator API > which is likely to collide with some API updates so is it OK to merge > via regulator if the patch is OK? Yes, the patch looks fine, you can merge it through the regulator tree with my Acked-by: Samuel Ortiz if you think that's necessary. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Exynos: fix SYSMMU driver to work with power domains
Hello Marek, I have tested these patches on origen 3.4-rc2 with sysmmu_v12, and they work great ! Thank you for sharing them. Regards, Subash On 04/11/2012 08:04 PM, Marek Szyprowski wrote: Hi! These two patches fixes operation of the SYSMMU driver (v12 version [1]) with the new power domain driver based on generic power domains and runtime pw, which has been merged to Linux kernel v3.4-rc1. [1] https://lkml.org/lkml/2012/3/15/51 Best regards Marek Szyprowski Samsung Poland R&D Center Patch summary: Marek Szyprowski (2): iommu/exynos: fix runtime pm support ARM: Exynos4: update SYSMMU setup code for gen_pd power domain driver arch/arm/mach-exynos/dev-sysmmu.c |6 +- arch/arm/mach-exynos/pm_domains.c | 13 + drivers/iommu/exynos-iommu.c | 20 ++-- 3 files changed, 36 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 2/2] ARM: Exynos4: update SYSMMU setup code for gen_pd power domain driver
Hi, On Monday, April 16, 2012 12:10 PM KyongHo Cho wrote: > On Wed, Apr 11, 2012 at 11:34 PM, Marek Szyprowski > wrote: > > SYSMMU platform devices must be registered before setting up power > > domains to let power domain driver to correctly register also SYSMMU > > controller devices. This patch also registers SYSMMU controller devices > > to respective power domains. > > > > Signed-off-by: Marek Szyprowski > > Acked-by: Kyungmin Park > > --- > > arch/arm/mach-exynos/dev-sysmmu.c | 6 +- > > arch/arm/mach-exynos/pm_domains.c | 13 + > > 2 files changed, 18 insertions(+), 1 deletions(-) > > > > diff --git a/arch/arm/mach-exynos/dev-sysmmu.c > > b/arch/arm/mach-exynos/dev-sysmmu.c > > index c5b1ea3..3544638 100644 > > --- a/arch/arm/mach-exynos/dev-sysmmu.c > > +++ b/arch/arm/mach-exynos/dev-sysmmu.c > > @@ -271,4 +271,8 @@ static int __init init_sysmmu_platform_device(void) > > > > return 0; > > } > > -arch_initcall(init_sysmmu_platform_device); > > +/* > > + * SYSMMU platform devices must be registered before power domains > > + * see pm_domain.c, which use arch_initcall() > > + */ > > +core_initcall(init_sysmmu_platform_device); > I don't understand why init_sysmmu_platform_device() must be called before > exynos4_pm_init_power_domain()? > > Other devices also added by an arch_initcall() function which calls > mdesc->init_machine(). > I also was unable to find any reason to add devices before registering > the devices to pm domain. mdesc->init_machine is called before exynos4_pm_init_power_domain() from arch/arm/mach-exynos/pm_domain.c, although both are started from arch_initcall. In this case the order of linking defines the order of calls. exynos4_pm_init_power_domain() calls exynos_pm_add_dev_to_genpd() which in turn checks for pdev->dev.bus. All devices which have not been registered yet on the bus are simply skipped. Best regards -- Marek Szyprowski Samsung Poland R&D Center -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Exynos: fix SYSMMU driver to work with power domains
On Mon, Apr 16, 2012 at 7:01 PM, Kyungmin Park wrote: > On 4/16/12, KyongHo Cho wrote: >> On Sun, Apr 15, 2012 at 12:51 AM, Kukjin Kim wrote: >>> On 04/12/12 01:19, KyongHo Cho wrote: On Wed, Apr 11, 2012 at 11:34 PM, Marek Szyprowski wrote: > > Hi! > > These two patches fixes operation of the SYSMMU driver (v12 version [1]) > with the new power domain driver based on generic power domains and > runtime pw, which has been merged to Linux kernel v3.4-rc1. > Thanks, Marek. Your way of power gating is right and I will look into the changed runtime PM scheme in Exynos tree. >>> KyongHo, >>> >>> Do you want to upstream this series with your previous sysmmu (cleanup and >>> moving) patches? >>> >> >> Yes I hope so. >> Marek's patch corrects run-time power management in Exynos4 with System MMU. > > Hi, > > Next time, if you give Acked-By or Reviewed_by, then it's more helpful > to determine to merge or not. > I did not Ack it since he did not CC me. But, as you mentioned, I need to add my Reviewed-by after reviewing it. Thank you. KyongHo. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: Exynos4: update SYSMMU setup code for gen_pd power domain driver
On Wed, Apr 11, 2012 at 11:34 PM, Marek Szyprowski wrote: > SYSMMU platform devices must be registered before setting up power > domains to let power domain driver to correctly register also SYSMMU > controller devices. This patch also registers SYSMMU controller devices > to respective power domains. > > Signed-off-by: Marek Szyprowski > Acked-by: Kyungmin Park > --- > arch/arm/mach-exynos/dev-sysmmu.c | 6 +- > arch/arm/mach-exynos/pm_domains.c | 13 + > 2 files changed, 18 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/mach-exynos/dev-sysmmu.c > b/arch/arm/mach-exynos/dev-sysmmu.c > index c5b1ea3..3544638 100644 > --- a/arch/arm/mach-exynos/dev-sysmmu.c > +++ b/arch/arm/mach-exynos/dev-sysmmu.c > @@ -271,4 +271,8 @@ static int __init init_sysmmu_platform_device(void) > > return 0; > } > -arch_initcall(init_sysmmu_platform_device); > +/* > + * SYSMMU platform devices must be registered before power domains > + * see pm_domain.c, which use arch_initcall() > + */ > +core_initcall(init_sysmmu_platform_device); I don't understand why init_sysmmu_platform_device() must be called before exynos4_pm_init_power_domain()? Other devices also added by an arch_initcall() function which calls mdesc->init_machine(). I also was unable to find any reason to add devices before registering the devices to pm domain. Regards, KyongHo. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Exynos: fix SYSMMU driver to work with power domains
On 4/16/12, KyongHo Cho wrote: > On Sun, Apr 15, 2012 at 12:51 AM, Kukjin Kim wrote: >> On 04/12/12 01:19, KyongHo Cho wrote: >>> >>> On Wed, Apr 11, 2012 at 11:34 PM, Marek Szyprowski >>> wrote: Hi! These two patches fixes operation of the SYSMMU driver (v12 version [1]) with the new power domain driver based on generic power domains and runtime pw, which has been merged to Linux kernel v3.4-rc1. >>> Thanks, Marek. >>> >>> Your way of power gating is right >>> and I will look into the changed runtime PM scheme in Exynos tree. >>> >> KyongHo, >> >> Do you want to upstream this series with your previous sysmmu (cleanup and >> moving) patches? >> > > Yes I hope so. > Marek's patch corrects run-time power management in Exynos4 with System MMU. Hi, Next time, if you give Acked-By or Reviewed_by, then it's more helpful to determine to merge or not. Thank you, Kyungmin Park > > Thank you. > > KyongHo > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Exynos: fix SYSMMU driver to work with power domains
On Sun, Apr 15, 2012 at 12:51 AM, Kukjin Kim wrote: > On 04/12/12 01:19, KyongHo Cho wrote: >> >> On Wed, Apr 11, 2012 at 11:34 PM, Marek Szyprowski >> wrote: >>> >>> Hi! >>> >>> These two patches fixes operation of the SYSMMU driver (v12 version [1]) >>> with the new power domain driver based on generic power domains and >>> runtime pw, which has been merged to Linux kernel v3.4-rc1. >>> >> Thanks, Marek. >> >> Your way of power gating is right >> and I will look into the changed runtime PM scheme in Exynos tree. >> > KyongHo, > > Do you want to upstream this series with your previous sysmmu (cleanup and > moving) patches? > Yes I hope so. Marek's patch corrects run-time power management in Exynos4 with System MMU. Thank you. KyongHo -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
