Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Tomasz,
On 3 October 2012 17:25, Tomasz Figa t.f...@samsung.com wrote:
Hi Chander, Thomas,
I think this patch could be split into several smaller, while retaining
logical integrity of particular patches, e.g.:
- the change introduced to __clk_init (with proper description and rationale
why the generic code is being touched)
- generic exynos4 code
- exynos4210-specific code
- exynos4x12-specific code
- patch enabling common clock framework on exynos4.
Also, see some nitpicks inline.
On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
From: Thomas Abraham thomas.abra...@linaro.org
Register clocks for Exynos4 platfotms using common clock framework.
Also included are set of helper functions for clock registration
that can be reused on other Samsung platforms as well.
Cc: Mike Turquette mturque...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/common.h |3 +
arch/arm/mach-exynos/mct.c| 11 +-
arch/arm/plat-samsung/Kconfig |4 +-
drivers/clk/Makefile |1 +
drivers/clk/clk.c | 12 +-
drivers/clk/samsung/Makefile |6 +
drivers/clk/samsung/clk-exynos4.c | 585
+ drivers/clk/samsung/clk.c
| 231 +++
drivers/clk/samsung/clk.h | 190
10 files changed, 1037 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk-exynos4.c
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..4866ec7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -15,6 +15,7 @@ config ARCH_EXYNOS4
bool SAMSUNG EXYNOS4
default y
select HAVE_SMP
+ select COMMON_CLK
select MIGHT_HAVE_CACHE_L2X0
help
Samsung EXYNOS4 SoCs based systems
diff --git a/arch/arm/mach-exynos/common.h
b/arch/arm/mach-exynos/common.h index aed2eeb..2274431 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -21,6 +21,9 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
+void exynos4210_clk_init(void);
+void exynos4212_clk_init(void);
exynos4x12_clk_init?
+
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8..a7cace0 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -30,6 +30,8 @@
#include mach/regs-mct.h
#include asm/mach/time.h
+#include common.h
+
#define TICK_BASE_CNT1
enum {
@@ -457,7 +459,7 @@ static struct local_timer_ops exynos4_mct_tick_ops
__cpuinitdata = { static void __init exynos4_timer_resources(void)
{
struct clk *mct_clk;
- mct_clk = clk_get(NULL, xtal);
+ mct_clk = clk_get(NULL, fin_pll);
clk_rate = clk_get_rate(mct_clk);
@@ -478,6 +480,13 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
+#ifdef CONFIG_COMMON_CLK
+ if (soc_is_exynos4210())
+ exynos4210_clk_init();
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
+ exynos4212_clk_init();
exynos4x12_clk_init?
Ok.
+#endif
+
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
diff --git a/arch/arm/plat-samsung/Kconfig
b/arch/arm/plat-samsung/Kconfig index 9c3b90c..35b4cb8 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -26,7 +26,7 @@ config PLAT_S5P
select S5P_GPIO_DRVSTR
select SAMSUNG_GPIOLIB_4BIT
select PLAT_SAMSUNG
- select SAMSUNG_CLKSRC
+ select SAMSUNG_CLKSRC if !COMMON_CLK
select SAMSUNG_IRQ_VIC_TIMER
help
Base platform code for Samsung's S5P series SoC.
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
used by newer systems such as the S3C64XX.
config S5P_CLOCK
- def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+ def_bool ((ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
!COMMON_CLK) help
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 6327536..5f5b060 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_MMP) += mmp/
endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_U8500) += ux500/
+obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Tomasz,
On 3 October 2012 19:40, Tomasz Figa t.f...@samsung.com wrote:
Hi Chander, Thomas,
I can see one more problem here.
Based on the fact that sdhci-s3c driver receives only the endpoint gate
clock (hsmmc), doesn't the following setup make the driver unable to change
the frequency of this clock?
The driver never changes the clock frequency of the core system clocks
nor of the endpoint. There are internal dividers inside the sdhci
controller which are divide to acheive required clock speed.
Thanks,
Thomas.
On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
+static struct samsung_mux_clock exynos4_mux_clks[] = {
[snip]
+ MUXCLK(exynos4-sdhci.0, mout_mmc0, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 0, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc1, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 4, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc2, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 8, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc3, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 12, 4, 0),
[snip]
+};
+
+static struct samsung_div_clock exynos4_div_clks[] = {
[snip]
+ DIVCLK(exynos4-sdhci.0, div_mmc0, mout_mmc0, 0,
+ EXYNOS4_CLKDIV_FSYS1, 0, 4, 0),
+ DIVCLK(exynos4-sdhci.0, div_mmc0_pre, div_mmc0, 0,
+ EXYNOS4_CLKDIV_FSYS1, 8, 8, 0),
+ DIVCLK(exynos4-sdhci.1, div_mmc1, mout_mmc1, 0,
+ EXYNOS4_CLKDIV_FSYS1, 16, 4, 0),
+ DIVCLK(exynos4-sdhci.1, div_mmc1_pre, div_mmc1, 0,
+ EXYNOS4_CLKDIV_FSYS1, 24, 8, 0),
+ DIVCLK(exynos4-sdhci.2, div_mmc2, mout_mmc2, 0,
+ EXYNOS4_CLKDIV_FSYS2, 0, 4, 0),
+ DIVCLK(exynos4-sdhci.2, div_mmc2_pre, div_mmc2, 0,
+ EXYNOS4_CLKDIV_FSYS2, 8, 8, 0),
+ DIVCLK(exynos4-sdhci.3, div_mmc3, mout_mmc3, 0,
+ EXYNOS4_CLKDIV_FSYS2, 16, 4, 0),
+ DIVCLK(exynos4-sdhci.3, div_mmc3_pre, div_mmc3, 0,
+ EXYNOS4_CLKDIV_FSYS2, 24, 8, 0),
[snip]
+};
+
+struct samsung_gate_clock exynos4_gate_clks[] = {
[snip]
+ GATECLK(exynos4-sdhci.0, hsmmc0, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 5, hsmmc),
+ GATECLK(exynos4-sdhci.1, hsmmc1, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 6, hsmmc),
+ GATECLK(exynos4-sdhci.2, hsmmc2, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 7, hsmmc),
+ GATECLK(exynos4-sdhci.3, hsmmc3, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 8, hsmmc),
[snip]
+};
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Sylwester,
Thanks for reviewing this patch series.
On 6 October 2012 00:21, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
Hello,
On 10/01/2012 02:09 PM, chander.kash...@linaro.org wrote:
From: Thomas Abrahamthomas.abra...@linaro.org
Register clocks for Exynos4 platfotms using common clock framework.
Also included are set of helper functions for clock registration
that can be reused on other Samsung platforms as well.
Cc: Mike Turquettemturque...@linaro.org
Cc: Kukjin Kimkgene@samsung.com
Signed-off-by: Thomas Abrahamthomas.abra...@linaro.org
---
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/common.h |3 +
arch/arm/mach-exynos/mct.c| 11 +-
arch/arm/plat-samsung/Kconfig |4 +-
drivers/clk/Makefile |1 +
drivers/clk/clk.c | 12 +-
drivers/clk/samsung/Makefile |6 +
drivers/clk/samsung/clk-exynos4.c | 585
+
drivers/clk/samsung/clk.c | 231 +++
drivers/clk/samsung/clk.h | 190
10 files changed, 1037 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk-exynos4.c
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
...
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 56e4495..456c50b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1196,6 +1196,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
int __clk_init(struct device *dev, struct clk *clk)
{
int i, ret = 0;
+ u8 index;
struct clk *orphan;
struct hlist_node *tmp, *tmp2;
@@ -1259,6 +1260,7 @@ int __clk_init(struct device *dev, struct clk *clk)
__clk_lookup(clk-parent_names[i]);
}
+
clk-parent = __clk_init_parent(clk);
/*
@@ -1298,11 +1300,13 @@ int __clk_init(struct device *dev, struct clk *clk)
* this clock
*/
hlist_for_each_entry_safe(orphan, tmp, tmp2,clk_orphan_list,
child_node)
- for (i = 0; i orphan-num_parents; i++)
- if (!strcmp(clk-name, orphan-parent_names[i])) {
+ if (orphan-num_parents 1) {
+ index = orphan-ops-get_parent(orphan-hw);
+ if (!strcmp(clk-name, orphan-parent_names[index]))
__clk_reparent(orphan, clk);
- break;
- }
+ } else if (!strcmp(clk-name, orphan-parent_names[0])) {
+ __clk_reparent(orphan, clk);
+ }
As this touches generic code it should rather be put into a separate patch,
along with an explanation why such a change is needed.
There is fix for this in mainline now.
/*
* optional platform-specific magic
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000..69487f7
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,6 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000..74a6f03
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 platforms
+*/
+
+#includelinux/clk.h
+#includelinux/clkdev.h
+#includelinux/io.h
+#includelinux/clk-provider.h
+
+#includeplat/pll.h
+#includeplat/cpu.h
+#includemach/regs-clock.h
+#includemach/sysmmu.h
+#includeplat/map-s5p.h
+
+#include clk.h
+
+#define EXYNOS4_OP_MODE (S5P_VA_CHIPID + 8)
+
+static const char *pll_parent_names[] __initdata = { fin_pll };
+static const char *fin_pll_parents[] __initdata = { xxti, xusbxti };
+static const char *mout_apll_parents[] __initdata = { fin_pll,
fout_apll, };
+static const char *mout_mpll_parents[] __initdata = { fin_pll,
fout_mpll, };
+static const char *mout_epll_parents[] __initdata = { fin_pll,
fout_epll, };
+
+static const char *sclk_ampll_parents[] __initdata = {
+ mout_mpll, sclk_apll, };
+
+static const char *sclk_evpll_parents[] __initdata = {
+ mout_epll, mout_vpll, };
+
+static const char *mout_core_parents[] __initdata = {
+ mout_apll, mout_mpll, };
+
+static const char *mout_mfc_parents[] __initdata = {
+ mout_mfc0, mout_mfc1, };
+
+static const char *mout_dac_parents[] __initdata = {
+
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
On Monday 08 of October 2012 12:04:18 Thomas Abraham wrote: Hi Tomasz, On 3 October 2012 19:40, Tomasz Figa t.f...@samsung.com wrote: Hi Chander, Thomas, I can see one more problem here. Based on the fact that sdhci-s3c driver receives only the endpoint gate clock (hsmmc), doesn't the following setup make the driver unable to change the frequency of this clock? The driver never changes the clock frequency of the core system clocks nor of the endpoint. There are internal dividers inside the sdhci controller which are divide to acheive required clock speed. What is the use of sdhci_cmu_set_clock (which calls clk_set_rate) in sdhci- s3c, then? I think you are missing CLK_SET_RATE_PARENT flags in clocks of which rate can be changed by the driver. Best regards, -- Tomasz Figa Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/5] clk: exynos4: register clocks using common clock framework
Hi Thomas,
The whole series looks much better now. Although there is still one more
thing from my comments to previous version unresolved, see the inline
comment.
On Monday 08 of October 2012 02:10:52 Thomas Abraham wrote:
For legacy Exynos4 platforms, the available clocks are statically
listed and then registered using the common clock framework. On device
tree enabled exynos platfotms, the device tree is searched and all
clock nodes found are registered. Support for Exynos4210 and
Exynos4x12 platforms is included.
Cc: Mike Turquette mturque...@ti.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos4.c | 647
+ 2 files changed, 648
insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/samsung/clk-exynos4.c
[snip]
+ EXYNOS4_CLKSRC_MASK_CAM, 28, sclk_csis),
+ GATECLK(NULL, sclk_cam0, div_cam0, 0,
+ EXYNOS4_CLKSRC_MASK_CAM, 16, NULL),
+ GATECLK(NULL, sclk_cam1, div_cam1, 0,
+ EXYNOS4_CLKSRC_MASK_CAM, 20, NULL),
+ GATECLK(exynos4-fimc.0, sclk_fimc, div_fimc0, 0,
+ EXYNOS4_CLKSRC_MASK_CAM, 0, sclk_fimc),
+ GATECLK(exynos4-fimc.1, sclk_fimc, div_fimc1, 0,
+ EXYNOS4_CLKSRC_MASK_CAM, 4, sclk_fimc),
+ GATECLK(exynos4-fimc.2, sclk_fimc, div_fimc2, 0,
+ EXYNOS4_CLKSRC_MASK_CAM, 8, sclk_fimc),
+ GATECLK(exynos4-fimc.3, sclk_fimc, div_fimc3, 0,
+ EXYNOS4_CLKSRC_MASK_CAM, 12, sclk_fimc),
You cannot register more than one clock with the same platform name
(sclk_fimc). Shouldn't these names be appended with an index, just like
with div_fimc{0,1,2,3}?
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 00/16] pinctrl: samsung: Usability and extensibiltiy improvements
This patch series is a work on improving usability and extensibiltiy of the pinctrl-samsung driver. It consists of three main parts: - moving SoC-specific data to device tree - converting the driver to use one GPIO chip and one IRQ domain per pin bank - introducing generic wake-up interrupt capability description What the first part does is replacing static platform-specific data in pinctrl-samsung driver with data dynamically parsed from device tree. It aims at reducing the SoC-specific part of the driver and thus the amount of modifications to driver sources when adding support for next SoCs (like Exynos4x12). In addition, it extends the description of SoC-specific attributes to cover all mainlined Samsung SoCs, starting from s3c24xx and ending on latest Exynos5 series, with the exception of 4-bit banks with more than 8 pins on S3C64xx, which will be covered by futher patch(es). The second part attempts to simplify usage of the driver and fix several problems of current implementation, in particular: - Simplifies GPIO pin specification in device tree by using pin namespace local to pin bank instead of local to pin controller, e.g. gpios = gpj0 3 0; instead of gpios = pinctrl0 115 0; - Simplifies GPIO interrupt specification in device tree by using namespace local to pin bank (and equal to GPIO namespace), e.g. interrupt-parent = gpj0; interrupts = 3 0; instead of interrupt-parent = pinctrl0; interrupts = 115 0; - Simplifies internal GPIO pin to bank translation thanks to correspondence of particular GPIO chips to pin banks. This allows to remove the (costly in case of GPIO bit-banging drivers) lookup over all banks to find the one that the pin is from. Third part is focused on removing the static, hard-coded description of wake-up interrupt controller and wake-up interrupt layout. It defines a (mostly) generic (in scope of targetted SoCs) wake-up interrupt layout specification format that allows to specify which pin banks support wake-up interrupts and how they are handled (direct or multiplexed/chained). See particular patches for more detailed descriptions and the last patch for updated device tree bindings. Tomasz Figa (16): ARM: dts: exynos4210: Replace legacy GPIO bank nodes with pinctrl bank nodes pinctrl: exynos: Parse wakeup-eint parameters from DT pinctrl: samsung: Detect and handle unsupported configuration types pinctrl: samsung: Parse pin banks from DT pinctrl: exynos: Remove static SoC-specific data pinctrl: samsung: Parse bank-specific eint offset from DT pinctrl: samsung: Hold OF node of pin bank in bank struct pinctrl: samsung: Hold pointer to driver data in bank struct pinctrl: exynos: Use one IRQ domain per pin bank pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank pinctrl: samsung: Use one GPIO chip per pin bank pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT pinctrl: samsung: Parse offsets of particular registers from DT pinctrl: samsung: Add GPIO to IRQ translation Documentation: Update samsung-pinctrl device tree bindings documentation .../bindings/pinctrl/samsung-pinctrl.txt | 212 -- arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi| 459 + arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 + arch/arm/boot/dts/exynos4210.dtsi | 254 +--- drivers/pinctrl/pinctrl-exynos.c | 399 -- drivers/pinctrl/pinctrl-exynos.h | 184 + drivers/pinctrl/pinctrl-samsung.c | 392 ++ drivers/pinctrl/pinctrl-samsung.h | 87 ++-- 8 files changed, 1205 insertions(+), 784 deletions(-) create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi -- 1.7.12 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/16] ARM: dts: exynos4210: Replace legacy GPIO bank nodes with pinctrl bank nodes
Seuqential patches from this series introduce SoC-specific data parsing
from device tree.
This patch removes legacy GPIO bank nodes from exynos4210.dtsi and
replaces them with nodes and properties required for these patches.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi | 459
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 +
arch/arm/boot/dts/exynos4210.dtsi | 254 +
3 files changed, 474 insertions(+), 241 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi
b/arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi
new file mode 100644
index 000..ec91f40
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl-banks.dtsi
@@ -0,0 +1,459 @@
+/*
+ * Samsung's Exynos4210 SoC pinctrl banks device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos4210 SoC pin banks are listed as device tree nodes
+ * in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ pinctrl-bank-types {
+ bank_off: bank-off {
+ samsung,reg-names = func, dat, pud,
+ drv, conpdn, pudpdn;
+ samsung,reg-params = 0x00 4, 0x04 1, 0x08 2,
+ 0x0C 2, 0x10 2, 0x14 2;
+ };
+
+ bank_alive: bank-alive {
+ samsung,reg-names = func, dat, pud,
+ drv;
+ samsung,reg-params = 0x00 4, 0x04 1, 0x08 2,
+ 0x0C 2;
+ };
+ };
+
+ pinctrl@1140 {
+ gpa0: gpa0 {
+ gpio-controller;
+ samsung,pctl-offset = 0x000;
+ samsung,pin-count = 8;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x00;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ samsung,pctl-offset = 0x020;
+ samsung,pin-count = 6;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x04;
+ #interrupt-cells = 2;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ samsung,pctl-offset = 0x040;
+ samsung,pin-count = 8;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x08;
+ #interrupt-cells = 2;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ samsung,pctl-offset = 0x060;
+ samsung,pin-count = 5;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x0C;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ samsung,pctl-offset = 0x080;
+ samsung,pin-count = 5;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x10;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ samsung,pctl-offset = 0x0A0;
+ samsung,pin-count = 4;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x14;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ samsung,pctl-offset = 0x0C0;
+ samsung,pin-count = 4;
+ samsung,bank-type = bank_off;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ samsung,eint-offset = 0x18;
+
[PATCH 02/16] pinctrl: exynos: Parse wakeup-eint parameters from DT
This patch converts the pinctrl-exynos driver to parse wakeup interrupt
count and register offsets from device tree. It reduces the amount of
static platform-specific data and facilitates adding further SoC
variants to pinctrl-samsung driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 21362f4..b4b58d4 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -435,6 +435,8 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
struct device_node *np;
struct exynos_weint_data *weint_data;
int idx, irq;
+ u32 val;
+ int ret;
for_each_child_of_node(dev-of_node, np) {
if (of_match_node(exynos_wkup_irq_ids, np)) {
@@ -445,6 +447,26 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
if (!wkup_np)
return -ENODEV;
+ ret = of_property_read_u32(wkup_np, samsung,weint-count, val);
+ if (ret)
+ return -EINVAL;
+ d-ctrl-nr_wint = val;
+
+ ret = of_property_read_u32(wkup_np, samsung,weint-con, val);
+ if (ret)
+ return -EINVAL;
+ d-ctrl-weint_con = val;
+
+ ret = of_property_read_u32(wkup_np, samsung,weint-mask, val);
+ if (ret)
+ return -EINVAL;
+ d-ctrl-weint_mask = val;
+
+ ret = of_property_read_u32(wkup_np, samsung,weint-pend, val);
+ if (ret)
+ return -EINVAL;
+ d-ctrl-weint_pend = val;
+
d-wkup_irqd = irq_domain_add_linear(wkup_np, d-ctrl-nr_wint,
exynos_wkup_irqd_ops, d);
if (!d-wkup_irqd) {
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/16] pinctrl: samsung: Parse pin banks from DT
Currently SoC-specific properties such as list of pin banks, register
offsets and bitfield sizes are being taken from static data structures
residing in pinctrl-exynos.c.
This patch modifies the pinctrl-samsung driver to parse all SoC-specific
data from device tree, which will allow to remove the static data
structures and facilitate adding of further SoC variants to the
pinctrl-samsung driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 5 ++
drivers/pinctrl/pinctrl-samsung.c | 169 +-
drivers/pinctrl/pinctrl-samsung.h | 17 +++-
3 files changed, 187 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index b4b58d4..e3fa263 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -599,3 +599,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
.label = exynos4210-gpio-ctrl2,
},
};
+
+struct samsung_pin_ctrl_variant exynos4_pin_ctrl = {
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+};
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index c660fa5..e828a0e 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -46,6 +46,8 @@ struct pin_config {
{ samsung,pin-pud-pdn, PINCFG_TYPE_PUD_PDN },
};
+static unsigned int pin_base = 0;
+
/* check if the selector is a valid pin group selector */
static int samsung_get_group_count(struct pinctrl_dev *pctldev)
{
@@ -602,6 +604,8 @@ static int __init samsung_pinctrl_parse_dt(struct
platform_device *pdev,
u32 function;
if (of_find_property(cfg_np, interrupt-controller, NULL))
continue;
+ if (of_find_property(cfg_np, gpio-controller, NULL))
+ continue;
ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np,
drvdata-pctl, pin_list, npins);
@@ -778,6 +782,86 @@ static int __init samsung_gpiolib_unregister(struct
platform_device *pdev,
static const struct of_device_id samsung_pinctrl_dt_match[];
+static int samsung_pinctrl_parse_dt_bank_type(struct samsung_pin_bank *bank,
+ struct device_node *np)
+{
+ struct samsung_pin_bank *type = np-data;
+ int ret;
+ u32 val;
+
+ if (type) {
+ *bank = *type;
+ return 0;
+ }
+
+ type = kzalloc(sizeof(*type), GFP_KERNEL);
+ if (!type)
+ return -ENOMEM;
+
+ ret = of_property_read_u32(np, samsung,func-width, val);
+ if (ret)
+ return ret;
+ type-func_width = val;
+
+ ret = of_property_read_u32(np, samsung,pud-width, val);
+ if (!ret)
+ type-pud_width = val;
+
+ ret = of_property_read_u32(np, samsung,drv-width, val);
+ if (!ret)
+ type-drv_width = val;
+
+ ret = of_property_read_u32(np, samsung,conpdn-width, val);
+ if (!ret)
+ type-conpdn_width = val;
+
+ ret = of_property_read_u32(np, samsung,pudpdn-width, val);
+ if (!ret)
+ type-pudpdn_width = val;
+
+ *bank = *type;
+ np-data = type;
+
+ return 0;
+}
+
+static int samsung_pinctrl_parse_dt_bank(struct samsung_pin_bank *bank,
+ struct device_node *np)
+{
+ int ret;
+ u32 val;
+ struct device_node *type_np;
+
+ type_np = of_parse_phandle(np, samsung,bank-type, 0);
+ if (!type_np)
+ return -EINVAL;
+
+ ret = samsung_pinctrl_parse_dt_bank_type(bank, type_np);
+ if (ret)
+ return ret;
+
+ ret = of_property_read_u32(np, samsung,pctl-offset, val);
+ if (ret)
+ return ret;
+ bank-pctl_offset = val;
+
+ ret = of_property_read_u32(np, samsung,pin-count, val);
+ if (ret)
+ return ret;
+ bank-nr_pins = val;
+
+ bank-name = np-name;
+
+ if (!of_find_property(np, interrupt-controller, NULL)) {
+ bank-eint_type = EINT_TYPE_NONE;
+ return 0;
+ }
+
+ bank-eint_type = EINT_TYPE_GPIO;
+
+ return 0;
+}
+
/* retrieve the soc specific data */
static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
struct platform_device *pdev)
@@ -785,6 +869,14 @@ static struct samsung_pin_ctrl
*samsung_pinctrl_get_soc_data(
int id;
const struct of_device_id *match;
const struct device_node *node = pdev-dev.of_node;
+ struct device_node *bank_np;
+ struct samsung_pin_ctrl *ctrl;
+ struct samsung_pin_bank *banks, *b;
+ struct samsung_pin_ctrl_variant *variant;
+ unsigned int bank_cnt = 0;
+ unsigned int
[PATCH 06/16] pinctrl: samsung: Parse bank-specific eint offset from DT
Some SoCs, like Exynos4x12, have non-sequential layout of EINT control
registers and so current way of calculating register addresses does not
work correctly for them.
This patch adds parsing of samsung,eint-offset property from bank nodes
and uses the read values instead of calculating the offsets from bank
index.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 5 ++---
drivers/pinctrl/pinctrl-samsung.c | 5 +
drivers/pinctrl/pinctrl-samsung.h | 1 +
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 134fecf..340bfc2 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -146,7 +146,7 @@ static struct exynos_geint_data
*exynos_get_eint_data(irq_hw_number_t hw,
struct samsung_pin_bank *bank = d-ctrl-pin_banks;
struct exynos_geint_data *eint_data;
unsigned int nr_banks = d-ctrl-nr_banks, idx;
- unsigned int irq_base = 0, eint_offset = 0;
+ unsigned int irq_base = 0;
if (hw = d-ctrl-nr_gint) {
dev_err(d-dev, unsupported ext-gpio interrupt\n);
@@ -159,7 +159,6 @@ static struct exynos_geint_data
*exynos_get_eint_data(irq_hw_number_t hw,
if ((hw = irq_base) (hw (irq_base + bank-nr_pins)))
break;
irq_base += bank-nr_pins;
- eint_offset += 4;
}
if (idx == nr_banks) {
@@ -175,7 +174,7 @@ static struct exynos_geint_data
*exynos_get_eint_data(irq_hw_number_t hw,
eint_data-bank = bank;
eint_data-pin = hw - irq_base;
- eint_data-eint_offset = eint_offset;
+ eint_data-eint_offset = bank-eint_offset;
return eint_data;
}
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index e828a0e..962320b 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -859,6 +859,11 @@ static int samsung_pinctrl_parse_dt_bank(struct
samsung_pin_bank *bank,
bank-eint_type = EINT_TYPE_GPIO;
+ ret = of_property_read_u32(np, samsung,eint-offset, val);
+ if (ret)
+ return ret;
+ bank-eint_offset = val;
+
return 0;
}
diff --git a/drivers/pinctrl/pinctrl-samsung.h
b/drivers/pinctrl/pinctrl-samsung.h
index db1907c..72303f1 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -122,6 +122,7 @@ struct samsung_pin_bank {
u8 conpdn_width;
u8 pudpdn_width;
enum eint_type eint_type;
+ u32 eint_offset;
u32 irq_base;
const char *name;
};
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/16] pinctrl: samsung: Hold OF node of pin bank in bank struct
The node pointer will be used in extensions added by patches that will
follow.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-samsung.c | 1 +
drivers/pinctrl/pinctrl-samsung.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index 962320b..c988a4e 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -850,6 +850,7 @@ static int samsung_pinctrl_parse_dt_bank(struct
samsung_pin_bank *bank,
return ret;
bank-nr_pins = val;
+ bank-of_node = np;
bank-name = np-name;
if (!of_find_property(np, interrupt-controller, NULL)) {
diff --git a/drivers/pinctrl/pinctrl-samsung.h
b/drivers/pinctrl/pinctrl-samsung.h
index 72303f1..b7b74cc 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -111,6 +111,7 @@ struct samsung_pinctrl_drv_data;
* @eint_type: type of the external interrupt supported by the bank.
* @irq_base: starting controller local irq number of the bank.
* @name: name to be prefixed for each pin in this pin bank.
+ * @of_node: node of pin bank in device tree
*/
struct samsung_pin_bank {
u32 pctl_offset;
@@ -125,6 +126,8 @@ struct samsung_pin_bank {
u32 eint_offset;
u32 irq_base;
const char *name;
+
+ struct device_node *of_node;
};
/**
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 08/16] pinctrl: samsung: Hold pointer to driver data in bank struct
The pointer will be used by further extensions added to the driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-samsung.c | 20 +++-
drivers/pinctrl/pinctrl-samsung.h | 2 ++
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index c988a4e..63c76ec 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -870,11 +870,12 @@ static int samsung_pinctrl_parse_dt_bank(struct
samsung_pin_bank *bank,
/* retrieve the soc specific data */
static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
- struct platform_device *pdev)
+ struct platform_device *pdev,
+ struct samsung_pinctrl_drv_data *d)
{
int id;
const struct of_device_id *match;
- const struct device_node *node = pdev-dev.of_node;
+ struct device_node *node = pdev-dev.of_node;
struct device_node *bank_np;
struct samsung_pin_ctrl *ctrl;
struct samsung_pin_bank *banks, *b;
@@ -884,7 +885,7 @@ static struct samsung_pin_ctrl
*samsung_pinctrl_get_soc_data(
u32 val;
int ret;
- id = of_alias_get_id(pdev-dev.of_node, pinctrl);
+ id = of_alias_get_id(node, pinctrl);
if (id 0) {
dev_err(pdev-dev, failed to get alias id\n);
return NULL;
@@ -922,6 +923,7 @@ static struct samsung_pin_ctrl
*samsung_pinctrl_get_soc_data(
continue;
if (samsung_pinctrl_parse_dt_bank(b, bank_np))
return NULL;
+ b-drvdata = d;
b-pin_base = ctrl-nr_pins;
ctrl-nr_pins += b-nr_pins;
if (b-eint_type == EINT_TYPE_GPIO) {
@@ -979,18 +981,18 @@ static int __devinit samsung_pinctrl_probe(struct
platform_device *pdev)
return -ENODEV;
}
- ctrl = samsung_pinctrl_get_soc_data(pdev);
- if (!ctrl) {
- dev_err(pdev-dev, driver data not available\n);
- return -EINVAL;
- }
-
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata) {
dev_err(dev, failed to allocate memory for driver's
private data\n);
return -ENOMEM;
}
+
+ ctrl = samsung_pinctrl_get_soc_data(pdev, drvdata);
+ if (!ctrl) {
+ dev_err(pdev-dev, driver data not available\n);
+ return -EINVAL;
+ }
drvdata-ctrl = ctrl;
drvdata-dev = dev;
diff --git a/drivers/pinctrl/pinctrl-samsung.h
b/drivers/pinctrl/pinctrl-samsung.h
index b7b74cc..9e30081 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -112,6 +112,7 @@ struct samsung_pinctrl_drv_data;
* @irq_base: starting controller local irq number of the bank.
* @name: name to be prefixed for each pin in this pin bank.
* @of_node: node of pin bank in device tree
+ * @drvdata: link to controller driver data
*/
struct samsung_pin_bank {
u32 pctl_offset;
@@ -128,6 +129,7 @@ struct samsung_pin_bank {
const char *name;
struct device_node *of_node;
+ struct samsung_pinctrl_drv_data *drvdata;
};
/**
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 03/16] pinctrl: samsung: Detect and handle unsupported configuration types
This patch modifies the pinctrl-samsung driver to detect when width of a bit field is set to zero (which means that such configuraton type is not supported) and return an error instead of trying to modify an inexistent register. Signed-off-by: Tomasz Figa t.f...@samsung.com --- drivers/pinctrl/pinctrl-samsung.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index dd108a9..c660fa5 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -391,6 +391,9 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; } + if (!width) + return -EINVAL; + mask = (1 width) - 1; shift = pin_offset * width; data = readl(reg_base + cfg_reg); -- 1.7.12 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 09/16] pinctrl: exynos: Use one IRQ domain per pin bank
Instead of registering one IRQ domain for all pin banks of a pin
controller, this patch implements registration of per-bank domains.
At a cost of a little memory overhead (~2.5KiB for all GPIO interrupts
of Exynos4x12) it simplifies driver code and device tree sources,
because GPIO interrupts can be now specified per banks.
Example:
device {
/* ... */
interrupt-parent = gpa1;
interrupts = 3 0;
/* ... */
};
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 117 +++---
drivers/pinctrl/pinctrl-exynos.h | 12
drivers/pinctrl/pinctrl-samsung.c | 5 +-
drivers/pinctrl/pinctrl-samsung.h | 7 +--
4 files changed, 36 insertions(+), 105 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 340bfc2..53ed5d9 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -40,46 +40,46 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
static void exynos_gpio_irq_unmask(struct irq_data *irqd)
{
- struct samsung_pinctrl_drv_data *d = irqd-domain-host_data;
- struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
- unsigned long reg_mask = d-ctrl-geint_mask + edata-eint_offset;
+ struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = bank-drvdata;
+ unsigned long reg_mask = d-ctrl-geint_mask + bank-eint_offset;
unsigned long mask;
mask = readl(d-virt_base + reg_mask);
- mask = ~(1 edata-pin);
+ mask = ~(1 irqd-hwirq);
writel(mask, d-virt_base + reg_mask);
}
static void exynos_gpio_irq_mask(struct irq_data *irqd)
{
- struct samsung_pinctrl_drv_data *d = irqd-domain-host_data;
- struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
- unsigned long reg_mask = d-ctrl-geint_mask + edata-eint_offset;
+ struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = bank-drvdata;
+ unsigned long reg_mask = d-ctrl-geint_mask + bank-eint_offset;
unsigned long mask;
mask = readl(d-virt_base + reg_mask);
- mask |= 1 edata-pin;
+ mask |= 1 irqd-hwirq;
writel(mask, d-virt_base + reg_mask);
}
static void exynos_gpio_irq_ack(struct irq_data *irqd)
{
- struct samsung_pinctrl_drv_data *d = irqd-domain-host_data;
- struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
- unsigned long reg_pend = d-ctrl-geint_pend + edata-eint_offset;
+ struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = bank-drvdata;
+ unsigned long reg_pend = d-ctrl-geint_pend + bank-eint_offset;
- writel(1 edata-pin, d-virt_base + reg_pend);
+ writel(1 irqd-hwirq, d-virt_base + reg_pend);
}
static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{
- struct samsung_pinctrl_drv_data *d = irqd-domain-host_data;
+ struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = bank-drvdata;
struct samsung_pin_ctrl *ctrl = d-ctrl;
- struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
- struct samsung_pin_bank *bank = edata-bank;
- unsigned int shift = EXYNOS_EINT_CON_LEN * edata-pin;
+ unsigned int pin = irqd-hwirq;
+ unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
unsigned int con, trig_type;
- unsigned long reg_con = ctrl-geint_con + edata-eint_offset;
+ unsigned long reg_con = ctrl-geint_con + bank-eint_offset;
unsigned int mask;
switch (type) {
@@ -114,7 +114,7 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd,
unsigned int type)
writel(con, d-virt_base + reg_con);
reg_con = bank-pctl_offset;
- shift = edata-pin * bank-func_width;
+ shift = pin * bank-func_width;
mask = (1 bank-func_width) - 1;
con = readl(d-virt_base + reg_con);
@@ -136,81 +136,23 @@ static struct irq_chip exynos_gpio_irq_chip = {
.irq_set_type = exynos_gpio_irq_set_type,
};
-/*
- * given a controller-local external gpio interrupt number, prepare the handler
- * data for it.
- */
-static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
- struct samsung_pinctrl_drv_data *d)
-{
- struct samsung_pin_bank *bank = d-ctrl-pin_banks;
- struct exynos_geint_data *eint_data;
- unsigned int nr_banks = d-ctrl-nr_banks, idx;
- unsigned int irq_base = 0;
-
- if (hw = d-ctrl-nr_gint) {
- dev_err(d-dev, unsupported ext-gpio interrupt\n);
- return NULL;
- }
-
- for (idx = 0; idx nr_banks; idx++, bank++) {
-
[PATCH 10/16] pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
The pointer to gpio_chip passed to pin_to_reg_bank utility function is
used only to retrieve a pointer to samsung_pinctrl_drv_data structure.
This patch modifies the function and its users to pass a pointer to
samsung_pinctrl_drv_data directly.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-samsung.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index 6ae82d5..e63a365 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -252,14 +252,12 @@ static int samsung_pinmux_get_groups(struct pinctrl_dev
*pctldev,
* given a pin number that is local to a pin controller, find out the pin bank
* and the register base of the pin bank.
*/
-static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin,
- void __iomem **reg, u32 *offset,
+static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
+ unsigned pin, void __iomem **reg, u32 *offset,
struct samsung_pin_bank **bank)
{
- struct samsung_pinctrl_drv_data *drvdata;
struct samsung_pin_bank *b;
- drvdata = dev_get_drvdata(gc-dev);
b = drvdata-ctrl-pin_banks;
while ((pin = b-pin_base)
@@ -294,7 +292,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev
*pctldev, unsigned selector,
* pin function number in the config register.
*/
for (cnt = 0; cnt drvdata-pin_groups[group].num_pins; cnt++) {
- pin_to_reg_bank(drvdata-gc, pins[cnt] - drvdata-ctrl-base,
+ pin_to_reg_bank(drvdata, pins[cnt] - drvdata-ctrl-base,
reg, pin_offset, bank);
mask = (1 bank-func_width) - 1;
shift = pin_offset * bank-func_width;
@@ -331,10 +329,13 @@ static int samsung_pinmux_gpio_set_direction(struct
pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
struct samsung_pin_bank *bank;
+ struct samsung_pinctrl_drv_data *drvdata;
void __iomem *reg;
u32 data, pin_offset, mask, shift;
- pin_to_reg_bank(range-gc, offset, reg, pin_offset, bank);
+ drvdata = pinctrl_dev_get_drvdata(pctldev);
+
+ pin_to_reg_bank(drvdata, offset, reg, pin_offset, bank);
mask = (1 bank-func_width) - 1;
shift = pin_offset * bank-func_width;
@@ -368,7 +369,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev,
unsigned int pin,
u32 cfg_value, cfg_reg;
drvdata = pinctrl_dev_get_drvdata(pctldev);
- pin_to_reg_bank(drvdata-gc, pin - drvdata-ctrl-base, reg_base,
+ pin_to_reg_bank(drvdata, pin - drvdata-ctrl-base, reg_base,
pin_offset, bank);
switch (cfg_type) {
@@ -470,8 +471,11 @@ static void samsung_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
{
void __iomem *reg;
u32 pin_offset, data;
+ struct samsung_pinctrl_drv_data *drvdata;
- pin_to_reg_bank(gc, offset, reg, pin_offset, NULL);
+ drvdata = dev_get_drvdata(gc-dev);
+
+ pin_to_reg_bank(drvdata, offset, reg, pin_offset, NULL);
data = readl(reg + DAT_REG);
data = ~(1 pin_offset);
if (value)
@@ -484,8 +488,11 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned
offset)
{
void __iomem *reg;
u32 pin_offset, data;
+ struct samsung_pinctrl_drv_data *drvdata;
+
+ drvdata = dev_get_drvdata(gc-dev);
- pin_to_reg_bank(gc, offset, reg, pin_offset, NULL);
+ pin_to_reg_bank(drvdata, offset, reg, pin_offset, NULL);
data = readl(reg + DAT_REG);
data = pin_offset;
data = 1;
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/16] pinctrl: samsung: Use one GPIO chip per pin bank
This patch modifies the pinctrl-samsung driver to register one GPIO chip
per pin bank, instead of a single chip for all pin banks of the
controller.
It simplifies GPIO accesses a lot (constant time instead of looping
through the list of banks to find the right one) and should have a good
effect on performance of any bit-banging driver.
In addition it allows to reference GPIO pins by a phandle to the bank
node and a local pin offset inside of the bank (similar to previous
gpiolib driver), which is more clear and readable than using indices
relative to the whole pin controller.
Example:
device {
/* ... */
gpios = gpk0 4 0;
/* ... */
};
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-samsung.c | 119 --
drivers/pinctrl/pinctrl-samsung.h | 12 ++--
2 files changed, 81 insertions(+), 50 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index e63a365..4ffd14c 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -48,6 +48,11 @@ struct pin_config {
static unsigned int pin_base = 0;
+static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
+{
+ return container_of(gc, struct samsung_pin_bank, gpio_chip);
+}
+
/* check if the selector is a valid pin group selector */
static int samsung_get_group_count(struct pinctrl_dev *pctldev)
{
@@ -333,9 +338,12 @@ static int samsung_pinmux_gpio_set_direction(struct
pinctrl_dev *pctldev,
void __iomem *reg;
u32 data, pin_offset, mask, shift;
+ bank = gc_to_pin_bank(range-gc);
drvdata = pinctrl_dev_get_drvdata(pctldev);
- pin_to_reg_bank(drvdata, offset, reg, pin_offset, bank);
+ pin_offset = offset - bank-pin_base;
+ reg = drvdata-virt_base + bank-pctl_offset;
+
mask = (1 bank-func_width) - 1;
shift = pin_offset * bank-func_width;
@@ -469,17 +477,16 @@ static struct pinconf_ops samsung_pinconf_ops = {
/* gpiolib gpio_set callback function */
static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
+ struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
void __iomem *reg;
- u32 pin_offset, data;
- struct samsung_pinctrl_drv_data *drvdata;
+ u32 data;
- drvdata = dev_get_drvdata(gc-dev);
+ reg = bank-drvdata-virt_base + bank-pctl_offset;
- pin_to_reg_bank(drvdata, offset, reg, pin_offset, NULL);
data = readl(reg + DAT_REG);
- data = ~(1 pin_offset);
+ data = ~(1 offset);
if (value)
- data |= 1 pin_offset;
+ data |= 1 offset;
writel(data, reg + DAT_REG);
}
@@ -487,14 +494,13 @@ static void samsung_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
{
void __iomem *reg;
- u32 pin_offset, data;
- struct samsung_pinctrl_drv_data *drvdata;
+ u32 data;
+ struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
- drvdata = dev_get_drvdata(gc-dev);
+ reg = bank-drvdata-virt_base + bank-pctl_offset;
- pin_to_reg_bank(drvdata, offset, reg, pin_offset, NULL);
data = readl(reg + DAT_REG);
- data = pin_offset;
+ data = offset;
data = 1;
return data;
}
@@ -726,12 +732,16 @@ static int __init samsung_pinctrl_register(struct
platform_device *pdev,
return -EINVAL;
}
- drvdata-grange.name = samsung-pctrl-gpio-range;
- drvdata-grange.id = 0;
- drvdata-grange.base = drvdata-ctrl-base;
- drvdata-grange.npins = drvdata-ctrl-nr_pins;
- drvdata-grange.gc = drvdata-gc;
- pinctrl_add_gpio_range(drvdata-pctl_dev, drvdata-grange);
+ for (bank = 0; bank drvdata-ctrl-nr_banks; ++bank) {
+ pin_bank = drvdata-ctrl-pin_banks[bank];
+ pin_bank-grange.name = pin_bank-name;
+ pin_bank-grange.id = bank;
+ pin_bank-grange.pin_base = pin_bank-pin_base;
+ pin_bank-grange.base = pin_bank-gpio_chip.base;
+ pin_bank-grange.npins = pin_bank-gpio_chip.ngpio;
+ pin_bank-grange.gc = pin_bank-gpio_chip;
+ pinctrl_add_gpio_range(drvdata-pctl_dev, pin_bank-grange);
+ }
ret = samsung_pinctrl_parse_dt(pdev, drvdata);
if (ret) {
@@ -742,49 +752,68 @@ static int __init samsung_pinctrl_register(struct
platform_device *pdev,
return 0;
}
+static const struct gpio_chip samsung_gpiolib_chip = {
+ .set = samsung_gpio_set,
+ .get = samsung_gpio_get,
+ .direction_input = samsung_gpio_direction_input,
+ .direction_output = samsung_gpio_direction_output,
+ .owner = THIS_MODULE,
+};
+
/* register the gpiolib interface with the gpiolib subsystem */
static int __init
[PATCH 12/16] pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
This patch reworks wake-up interrupt handling in pinctrl-exynos driver,
so each pin bank, which provides wake-up interrupts, has its own IRQ
domain.
Information about whether given pin bank provides wake-up interrupts,
how many and whether they are separate or muxed are parsed from device
tree.
It gives following advantages:
- interrupts can be specified in device tree in a more readable way,
e.g. :
device {
/* ... */
interrupt-parent = gpx2;
interrupts = 4 0;
/* ... */
};
- the amount and layout of interrupts is not hardcoded in the driver
anymore
- bank and pin of each wake-up interrupt can be easily identified, to
allow operations, such as setting the pin to EINT function, from
irq_set_type() callback
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 159 +++---
drivers/pinctrl/pinctrl-exynos.h | 17 +++-
drivers/pinctrl/pinctrl-samsung.c | 9 ++-
drivers/pinctrl/pinctrl-samsung.h | 6 +-
4 files changed, 119 insertions(+), 72 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 53ed5d9..fa6a5be 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -218,46 +218,43 @@ static int exynos_eint_gpio_init(struct
samsung_pinctrl_drv_data *d)
static void exynos_wkup_irq_unmask(struct irq_data *irqd)
{
- struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
- unsigned int bank = irqd-hwirq / EXYNOS_EINT_MAX_PER_BANK;
- unsigned int pin = irqd-hwirq (EXYNOS_EINT_MAX_PER_BANK - 1);
- unsigned long reg_mask = d-ctrl-weint_mask + (bank 2);
+ struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = b-drvdata;
+ unsigned long reg_mask = d-ctrl-weint_mask + b-eint_offset;
unsigned long mask;
mask = readl(d-virt_base + reg_mask);
- mask = ~(1 pin);
+ mask = ~(1 irqd-hwirq);
writel(mask, d-virt_base + reg_mask);
}
static void exynos_wkup_irq_mask(struct irq_data *irqd)
{
- struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
- unsigned int bank = irqd-hwirq / EXYNOS_EINT_MAX_PER_BANK;
- unsigned int pin = irqd-hwirq (EXYNOS_EINT_MAX_PER_BANK - 1);
- unsigned long reg_mask = d-ctrl-weint_mask + (bank 2);
+ struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = b-drvdata;
+ unsigned long reg_mask = d-ctrl-weint_mask + b-eint_offset;
unsigned long mask;
mask = readl(d-virt_base + reg_mask);
- mask |= 1 pin;
+ mask |= 1 irqd-hwirq;
writel(mask, d-virt_base + reg_mask);
}
static void exynos_wkup_irq_ack(struct irq_data *irqd)
{
- struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
- unsigned int bank = irqd-hwirq / EXYNOS_EINT_MAX_PER_BANK;
- unsigned int pin = irqd-hwirq (EXYNOS_EINT_MAX_PER_BANK - 1);
- unsigned long pend = d-ctrl-weint_pend + (bank 2);
+ struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = b-drvdata;
+ unsigned long pend = d-ctrl-weint_pend + b-eint_offset;
- writel(1 pin, d-virt_base + pend);
+ writel(1 irqd-hwirq, d-virt_base + pend);
}
static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
{
- struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
- unsigned int bank = irqd-hwirq / EXYNOS_EINT_MAX_PER_BANK;
- unsigned int pin = irqd-hwirq (EXYNOS_EINT_MAX_PER_BANK - 1);
- unsigned long reg_con = d-ctrl-weint_con + (bank 2);
+ struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+ struct samsung_pinctrl_drv_data *d = bank-drvdata;
+ unsigned int pin = irqd-hwirq;
+ unsigned long reg_con = d-ctrl-weint_con + bank-eint_offset;
unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
unsigned long con, trig_type;
@@ -309,6 +306,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
struct exynos_weint_data *eintd = irq_get_handler_data(irq);
+ struct samsung_pin_bank *bank = eintd-bank;
struct irq_chip *chip = irq_get_chip(irq);
int eint_irq;
@@ -318,20 +316,20 @@ static void exynos_irq_eint0_15(unsigned int irq, struct
irq_desc *desc)
if (chip-irq_ack)
chip-irq_ack(desc-irq_data);
- eint_irq = irq_linear_revmap(eintd-domain, eintd-irq);
+ eint_irq = irq_linear_revmap(bank-irq_domain, eintd-irq);
generic_handle_irq(eint_irq);
chip-irq_unmask(desc-irq_data);
chained_irq_exit(chip, desc);
}
-static inline void exynos_irq_demux_eint(int
[PATCH 13/16] pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
Pins used as wake-up interrupts need to be configured as EINTs. This
patch adds the required configuration code to exynos_wkup_irq_set_type,
to set the pin as EINT when its interrupt trigger type is configured.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index fa6a5be..8cc8018 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -257,6 +257,7 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd,
unsigned int type)
unsigned long reg_con = d-ctrl-weint_con + bank-eint_offset;
unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
unsigned long con, trig_type;
+ unsigned int mask;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -288,6 +289,16 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd,
unsigned int type)
con = ~(EXYNOS_EINT_CON_MASK shift);
con |= trig_type shift;
writel(con, d-virt_base + reg_con);
+
+ reg_con = bank-pctl_offset;
+ shift = pin * bank-func_width;
+ mask = (1 bank-func_width) - 1;
+
+ con = readl(d-virt_base + reg_con);
+ con = ~(mask shift);
+ con |= EXYNOS_EINT_FUNC shift;
+ writel(con, d-virt_base + reg_con);
+
return 0;
}
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 14/16] pinctrl: samsung: Parse offsets of particular registers from DT
The order and availability of pin control registers vary with SoC.
This patch modifies the driver to parse register offsets from device
tree as a part of bank type definition.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-exynos.c | 12 ++---
drivers/pinctrl/pinctrl-samsung.c | 93 +--
drivers/pinctrl/pinctrl-samsung.h | 38 +---
3 files changed, 78 insertions(+), 65 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 8cc8018..f264d69 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -113,9 +113,9 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd,
unsigned int type)
con |= trig_type shift;
writel(con, d-virt_base + reg_con);
- reg_con = bank-pctl_offset;
- shift = pin * bank-func_width;
- mask = (1 bank-func_width) - 1;
+ reg_con = bank-pctl_offset + bank-regs[REG_FUNC].offset;
+ shift = pin * bank-regs[REG_FUNC].width;
+ mask = (1 bank-regs[REG_FUNC].width) - 1;
con = readl(d-virt_base + reg_con);
con = ~(mask shift);
@@ -290,9 +290,9 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd,
unsigned int type)
con |= trig_type shift;
writel(con, d-virt_base + reg_con);
- reg_con = bank-pctl_offset;
- shift = pin * bank-func_width;
- mask = (1 bank-func_width) - 1;
+ reg_con = bank-pctl_offset + bank-regs[REG_FUNC].offset;
+ shift = pin * bank-regs[REG_FUNC].width;
+ mask = (1 bank-regs[REG_FUNC].width) - 1;
con = readl(d-virt_base + reg_con);
con = ~(mask shift);
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index 215a7e5..495b226 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -273,10 +273,6 @@ static void pin_to_reg_bank(struct
samsung_pinctrl_drv_data *drvdata,
*offset = pin - b-pin_base;
if (bank)
*bank = b;
-
- /* some banks have two config registers in a single bank */
- if (*offset * b-func_width BITS_PER_LONG)
- *reg += 4;
}
/* enable or disable a pinmux function */
@@ -299,8 +295,9 @@ static void samsung_pinmux_setup(struct pinctrl_dev
*pctldev, unsigned selector,
for (cnt = 0; cnt drvdata-pin_groups[group].num_pins; cnt++) {
pin_to_reg_bank(drvdata, pins[cnt] - drvdata-ctrl-base,
reg, pin_offset, bank);
- mask = (1 bank-func_width) - 1;
- shift = pin_offset * bank-func_width;
+ mask = (1 bank-regs[REG_FUNC].width) - 1;
+ shift = pin_offset * bank-regs[REG_FUNC].width;
+ reg += bank-regs[REG_FUNC].offset;
data = readl(reg);
data = ~(mask shift);
@@ -342,10 +339,11 @@ static int samsung_pinmux_gpio_set_direction(struct
pinctrl_dev *pctldev,
drvdata = pinctrl_dev_get_drvdata(pctldev);
pin_offset = offset - bank-pin_base;
- reg = drvdata-virt_base + bank-pctl_offset;
+ reg = drvdata-virt_base + bank-pctl_offset
+ + bank-regs[REG_FUNC].offset;
- mask = (1 bank-func_width) - 1;
- shift = pin_offset * bank-func_width;
+ mask = (1 bank-regs[REG_FUNC].width) - 1;
+ shift = pin_offset * bank-regs[REG_FUNC].width;
data = readl(reg);
data = ~(mask shift);
@@ -382,20 +380,20 @@ static int samsung_pinconf_rw(struct pinctrl_dev
*pctldev, unsigned int pin,
switch (cfg_type) {
case PINCFG_TYPE_PUD:
- width = bank-pud_width;
- cfg_reg = PUD_REG;
+ width = bank-regs[REG_PUD].width;
+ cfg_reg = bank-regs[REG_PUD].offset;
break;
case PINCFG_TYPE_DRV:
- width = bank-drv_width;
- cfg_reg = DRV_REG;
+ width = bank-regs[REG_DRV].width;
+ cfg_reg = bank-regs[REG_DRV].offset;
break;
case PINCFG_TYPE_CON_PDN:
- width = bank-conpdn_width;
- cfg_reg = CONPDN_REG;
+ width = bank-regs[REG_CONPDN].width;
+ cfg_reg = bank-regs[REG_CONPDN].offset;
break;
case PINCFG_TYPE_PUD_PDN:
- width = bank-pudpdn_width;
- cfg_reg = PUDPDN_REG;
+ width = bank-regs[REG_PUDPDN].width;
+ cfg_reg = bank-regs[REG_PUDPDN].offset;
break;
default:
WARN_ON(1);
@@ -481,13 +479,14 @@ static void samsung_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
void __iomem *reg;
u32 data;
- reg = bank-drvdata-virt_base + bank-pctl_offset;
+ reg = bank-drvdata-virt_base + bank-pctl_offset
+
[PATCH 15/16] pinctrl: samsung: Add GPIO to IRQ translation
Some drivers require a way to translate GPIO pins to their IRQ numbers.
This patch adds the .to_irq() gpiolib callback to pinctrl-samsung
driver, which creates (if not present yet) and returns an IRQ mapping
for given GPIO pin.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
drivers/pinctrl/pinctrl-samsung.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index 495b226..8172c1e 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -26,6 +26,7 @@
#include linux/slab.h
#include linux/err.h
#include linux/gpio.h
+#include linux/irqdomain.h
#include core.h
#include pinctrl-samsung.h
@@ -528,6 +529,23 @@ static int samsung_gpio_direction_output(struct gpio_chip
*gc, unsigned offset,
}
/*
+ * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
+ * and a virtual IRQ, if not already present.
+ */
+static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+ struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
+ unsigned int virq;
+
+ if (!bank-irq_domain)
+ return -ENXIO;
+
+ virq = irq_create_mapping(bank-irq_domain, offset);
+
+ return (virq) ? : -ENXIO;
+}
+
+/*
* Parse the pin names listed in the 'samsung,pins' property and convert it
* into a list of gpio numbers are create a pin group from it.
*/
@@ -757,6 +775,7 @@ static const struct gpio_chip samsung_gpiolib_chip = {
.get = samsung_gpio_get,
.direction_input = samsung_gpio_direction_input,
.direction_output = samsung_gpio_direction_output,
+ .to_irq = samsung_gpio_to_irq,
.owner = THIS_MODULE,
};
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 16/16] Documentation: Update samsung-pinctrl device tree bindings documentation
Signed-off-by: Tomasz Figa t.f...@samsung.com --- .../bindings/pinctrl/samsung-pinctrl.txt | 212 ++--- 1 file changed, 187 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 03dee50..6ebc946 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -13,8 +13,35 @@ Required Properties: - reg: Base address of the pin controller hardware module and length of the address space it occupies. -- interrupts: interrupt specifier for the controller. The format and value of - the interrupt specifier depends on the interrupt parent for the controller. +- Pin bank types: Pin bank nodes reference pin bank types by their phandles to + determine low level bank parameters such as bit field availability and widths. + There is no restriction for placement of such nodes. A bank type node must + contain following properties: + + - samsung,reg-names: names of registers specified in samsung,reg-params +property. Allowed register names are: +- func - function configuration register (GPxCON) +- dat - input/output value register (GPxDAT) +- pud - pull-up/-down control register (GPxPUD) +- drv - driver strength control register (GPxDRV) +- conpdn - power-down state control register (GPxCONPDN) +- pudpdn - power-down pull-up/-down control register (GPxPUDPDN) + - samsung,reg-params: register specifiers for registers named by +samsung,reg-names property. Each specifier contains two cells: + - first cell: offset in bytes from first register of the bank + - second cell: bits in register used for single pin. + +- Pin banks as child nodes: Pin banks of the controller are represented by child + nodes of the controller node. Bank name is taken from name of the node. Each + bank node must contain following properties: + + - gpio-controller: identifies the node as a gpio controller and pin bank. + - samsung,pctrl-offset: offset to pin control registers of the bank. + - samsung,pin-count: number of pins in the bank. + - samsung,bank-type: phandle to a node defining bank type. + - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO +binding is used, the amount of cells must be specified as 2. See generic +GPIO binding documentation for description of particular cells. - Pin mux/config groups as child nodes: The pin mux (selecting pin function mode) and pin config (pull up/down, driver strength) settings are represented @@ -72,16 +99,30 @@ used as system wakeup events. A. External GPIO Interrupts: For supporting external gpio interrupts, the following properties should be specified in the pin-controller device node. -- interrupt-controller: identifies the controller node as interrupt-parent. -- #interrupt-cells: the value of this property should be 2. - - First Cell: represents the external gpio interrupt number local to the -external gpio interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt -- 1 = rising edge triggered -- 2 = falling edge triggered -- 3 = rising and falling edge triggered -- 4 = high level triggered -- 8 = low level triggered + - samsung,geint-con: offset of first EXT_INTxx_CON register. + - samsung,geint-mask: offset of first EXT_INTxx_MASK register. + - samsung,geint-pend: offset of first EXT_INTxx_PEND register. + - samsung,svc: offset of EXT_INT_SERVICE register. + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - interrupts: interrupt specifier for the controller. The format and value of + the interrupt specifier depends on the interrupt parent for the controller. + + In addition, following properties must be present in node of every bank + of pins supporting GPIO interrupts: + + - interrupt-controller: identifies the controller node as interrupt-parent. + - samsung,eint-offset: offset of register related to this bank from first + CON/MASK/PEND register. + - #interrupt-cells: the value of this property should be 2. + - First Cell: represents the external gpio interrupt number local to the + external gpio interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered B. External Wakeup Interrupts: For supporting external wakeup interrupts, a child node representing the external wakeup interrupt controller should be @@ -94,7 +135,18 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a found on Samsung Exynos4210 SoC. - interrupt-parent:
[PATCH] mmc: dw_mmc: enable controller interrupt before calling mmc_start_host
As mmc_start_host is getting called before enabling the dw_mmc controller
interrupt, there is a problem of missing the SDMMC_INT_CMD_DONE for the
very first command sent by the sdio_reset.
This problem occurs only when we disable MMC debugging i.e, MMC_DEBUG [=n].
Hence this patch enables the dw_mmc controller interrupt before mmc_start_host.
Signed-off-by: Yuvaraj CD yuvaraj...@samsung.com
---
drivers/mmc/host/dw_mmc.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a23af77..729c031 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2233,6 +2233,21 @@ int dw_mci_probe(struct dw_mci *host)
else
host-num_slots = ((mci_readl(host, HCON) 1) 0x1F) + 1;
+ /*
+* Enable interrupts for command done, data over, data empty, card det,
+* receive ready and error such as transmit, receive timeout, crc error
+*/
+ mci_writel(host, RINTSTS, 0x);
+ mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
+ SDMMC_INT_TXDR | SDMMC_INT_RXDR |
+ DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
+ mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt
*/
+
+ dev_info(host-dev, DW MMC controller at irq %d,
+%d bit host data width,
+%u deep fifo\n,
+host-irq, width, fifo_size);
+
/* We need at least one slot to succeed */
for (i = 0; i host-num_slots; i++) {
ret = dw_mci_init_slot(host, i);
@@ -2262,20 +2277,6 @@ int dw_mci_probe(struct dw_mci *host)
else
host-data_offset = DATA_240A_OFFSET;
- /*
-* Enable interrupts for command done, data over, data empty, card det,
-* receive ready and error such as transmit, receive timeout, crc error
-*/
- mci_writel(host, RINTSTS, 0x);
- mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
- SDMMC_INT_TXDR | SDMMC_INT_RXDR |
- DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
- mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt
*/
-
- dev_info(host-dev, DW MMC controller at irq %d,
-%d bit host data width,
-%u deep fifo\n,
-host-irq, width, fifo_size);
if (host-quirks DW_MCI_QUIRK_IDMAC_DTO)
dev_info(host-dev, Internal DMAC interrupt fix enabled.\n);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mmc: dw_mmc: enable controller interrupt before calling mmc_start_host
On 8 October 2012 17:59, Yuvaraj CD yuvaraj...@gmail.com wrote:
As mmc_start_host is getting called before enabling the dw_mmc controller
interrupt, there is a problem of missing the SDMMC_INT_CMD_DONE for the
very first command sent by the sdio_reset.
This problem occurs only when we disable MMC debugging i.e, MMC_DEBUG [=n].
Hence this patch enables the dw_mmc controller interrupt before
mmc_start_host.
Signed-off-by: Yuvaraj CD yuvaraj...@samsung.com
---
drivers/mmc/host/dw_mmc.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a23af77..729c031 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2233,6 +2233,21 @@ int dw_mci_probe(struct dw_mci *host)
else
host-num_slots = ((mci_readl(host, HCON) 1) 0x1F) + 1;
+ /*
+* Enable interrupts for command done, data over, data empty, card
det,
+* receive ready and error such as transmit, receive timeout, crc
error
+*/
+ mci_writel(host, RINTSTS, 0x);
+ mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
+ SDMMC_INT_TXDR | SDMMC_INT_RXDR |
+ DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
+ mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci
interrupt */
+
+ dev_info(host-dev, DW MMC controller at irq %d,
+%d bit host data width,
+%u deep fifo\n,
+host-irq, width, fifo_size);
+
Makes sense
Reviewed By: Girish K S girish.shivananja...@linaro.org
/* We need at least one slot to succeed */
for (i = 0; i host-num_slots; i++) {
ret = dw_mci_init_slot(host, i);
@@ -2262,20 +2277,6 @@ int dw_mci_probe(struct dw_mci *host)
else
host-data_offset = DATA_240A_OFFSET;
- /*
-* Enable interrupts for command done, data over, data empty, card
det,
-* receive ready and error such as transmit, receive timeout, crc
error
-*/
- mci_writel(host, RINTSTS, 0x);
- mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
- SDMMC_INT_TXDR | SDMMC_INT_RXDR |
- DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
- mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci
interrupt */
-
- dev_info(host-dev, DW MMC controller at irq %d,
-%d bit host data width,
-%u deep fifo\n,
-host-irq, width, fifo_size);
if (host-quirks DW_MCI_QUIRK_IDMAC_DTO)
dev_info(host-dev, Internal DMAC interrupt fix enabled.\n);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mmc: dw_mmc: enable controller interrupt before calling mmc_start_host
On Mon, Oct 8, 2012 at 9:59 AM, Yuvaraj CD yuvaraj...@gmail.com wrote: As mmc_start_host is getting called before enabling the dw_mmc controller interrupt, there is a problem of missing the SDMMC_INT_CMD_DONE for the very first command sent by the sdio_reset. This problem occurs only when we disable MMC debugging i.e, MMC_DEBUG [=n]. Hence this patch enables the dw_mmc controller interrupt before mmc_start_host. Signed-off-by: Yuvaraj CD yuvaraj...@samsung.com --- drivers/mmc/host/dw_mmc.c | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) Ideally I think it would be cleaner to break up the slot initialization into two parts, one that allocates and sets up the slot and the other that calls mmc_add_host, but that's a more substantial bit of work and would also complicate the error handling. This looks like it should be safe though, so: Acked-by: Will Newton will.new...@imgtec.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/4] ARM: EXYNOS: Kconfig cleanup
This patch series aims to consolidate low level Kconfig entries for Exynos
SoC series by adding missing or removing wrong dependencies, renaming
entries to match a single naming convention and introducing a common
parent entry for EXYNOS4212 and EXYNOS4412.
See particular patches for more detailed descriptions.
Tomasz Figa (4):
ARM: EXYNOS: Kconfig: Rename CPU_EXYNOS4210 to SOC_EXYNOS4210
ARM: EXYNOS: Kconfig: Sort out dependencies between options
ARM: EXYNOS: Kconfig: Group EXYNOS{4212,4412} into EXYNOS4X12
ARM: EXYNOS: Kconfig: Remove dependencies on particular SoCs from DT
machines
arch/arm/mach-exynos/Kconfig | 42 +++-
arch/arm/mach-exynos/Makefile| 4 +--
arch/arm/mach-exynos/common.h| 4 +--
arch/arm/plat-samsung/include/plat/cpu.h | 2 +-
drivers/cpufreq/Kconfig.arm | 4 +--
drivers/devfreq/Kconfig | 2 +-
drivers/mmc/host/sdhci-s3c.c | 2 +-
drivers/tty/serial/samsung.c | 3 +--
8 files changed, 30 insertions(+), 33 deletions(-)
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: EXYNOS: Kconfig: Rename CPU_EXYNOS4210 to SOC_EXYNOS4210
This patch renames CONFIG_CPU_EXYNOS4210 to CONFIG_SOC_EXYNOS4210 to match the convention used by rest of Exynos SoCs and correctly represent the reality (Exynos4210 is a SoC, not a CPU). Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/Kconfig | 14 +++--- arch/arm/mach-exynos/Makefile| 2 +- arch/arm/mach-exynos/common.h| 2 +- arch/arm/plat-samsung/include/plat/cpu.h | 2 +- drivers/cpufreq/Kconfig.arm | 2 +- drivers/devfreq/Kconfig | 2 +- drivers/mmc/host/sdhci-s3c.c | 2 +- drivers/tty/serial/samsung.c | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4372075..05dcd07 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -27,7 +27,7 @@ config ARCH_EXYNOS5 comment EXYNOS SoCs -config CPU_EXYNOS4210 +config SOC_EXYNOS4210 bool SAMSUNG EXYNOS4210 default y depends on ARCH_EXYNOS4 @@ -188,7 +188,7 @@ config MACH_SMDKC210 config MACH_SMDKV310 bool SMDKV310 - select CPU_EXYNOS4210 + select SOC_EXYNOS4210 select S5P_DEV_FIMD0 select S3C_DEV_RTC select S3C_DEV_WDT @@ -227,7 +227,7 @@ config MACH_SMDKV310 config MACH_ARMLEX4210 bool ARMLEX4210 - select CPU_EXYNOS4210 + select SOC_EXYNOS4210 select S3C_DEV_RTC select S3C_DEV_WDT select S3C_DEV_HSMMC @@ -241,7 +241,7 @@ config MACH_ARMLEX4210 config MACH_UNIVERSAL_C210 bool Mobile UNIVERSAL_C210 Board - select CPU_EXYNOS4210 + select SOC_EXYNOS4210 select S5P_HRT select CLKSRC_MMIO select HAVE_SCHED_CLOCK @@ -282,7 +282,7 @@ config MACH_UNIVERSAL_C210 config MACH_NURI bool Mobile NURI Board - select CPU_EXYNOS4210 + select SOC_EXYNOS4210 select S5P_GPIO_INT select S3C_DEV_WDT select S3C_DEV_RTC @@ -323,7 +323,7 @@ config MACH_NURI config MACH_ORIGEN bool ORIGEN - select CPU_EXYNOS4210 + select SOC_EXYNOS4210 select S3C_DEV_RTC select S3C_DEV_WDT select S3C_DEV_HSMMC @@ -404,7 +404,7 @@ comment Flattened Device Tree based board for EXYNOS SoCs config MACH_EXYNOS4_DT bool Samsung Exynos4 Machine using device tree depends on ARCH_EXYNOS4 - select CPU_EXYNOS4210 + select SOC_EXYNOS4210 select USE_OF select ARM_AMBA select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 9b58024..ceeb8c9 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -15,7 +15,7 @@ obj- := obj-$(CONFIG_ARCH_EXYNOS) += common.o obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o -obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o +obj-$(CONFIG_SOC_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index aed2eeb..054c786 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -45,7 +45,7 @@ void exynos5_setup_clocks(void); #define exynos5_setup_clocks() #endif -#ifdef CONFIG_CPU_EXYNOS4210 +#ifdef CONFIG_SOC_EXYNOS4210 void exynos4210_register_clocks(void); #else diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index ace4451..021fff0 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -102,7 +102,7 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_s5pv210() 0 #endif -#if defined(CONFIG_CPU_EXYNOS4210) +#if defined(CONFIG_SOC_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() #else # define soc_is_exynos4210() 0 diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 5961e64..ca4ede3 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -60,7 +60,7 @@ config ARM_EXYNOS_CPUFREQ If in doubt, say N. config ARM_EXYNOS4210_CPUFREQ - def_bool CPU_EXYNOS4210 + def_bool SOC_EXYNOS4210 help This adds the CPUFreq driver for Samsung EXYNOS4210 SoC (S5PV310 or S5PC210). diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index f6b0a6e2..8545069 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -67,7 +67,7 @@ comment DEVFREQ Drivers config ARM_EXYNOS4_BUS_DEVFREQ bool ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver - depends on CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412 + depends on SOC_EXYNOS4210 || CPU_EXYNOS4212
[PATCH 2/4] ARM: EXYNOS: Kconfig: Sort out dependencies between options
This patch modifies the dependencies between Exynos-related Kconfig
options to represent the real dependencies between code units more
closely.
Originally it was possible to enable ARCH_EXYNOS{4,5} without any
SOC_EXYNOS_{4,5}.* enabled, which could end with compilation or link
errors. Now ARCH_EXYNOS{4,5} is only selected when there is a
SOC_EXYNOS_{4,5}.* enabled, which requires it.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 15 ++-
drivers/devfreq/Kconfig | 2 +-
drivers/mmc/host/sdhci-s3c.c | 2 +-
drivers/tty/serial/samsung.c | 3 +--
4 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 05dcd07..9f91892 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -12,15 +12,14 @@ if ARCH_EXYNOS
menu SAMSUNG EXYNOS SoCs Support
config ARCH_EXYNOS4
- bool SAMSUNG EXYNOS4
- default y
+ def_bool n
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Samsung EXYNOS4 SoCs based systems
config ARCH_EXYNOS5
- bool SAMSUNG EXYNOS5
+ def_bool n
select HAVE_SMP
help
Samsung EXYNOS5 (Cortex-A15) SoC based systems
@@ -30,7 +29,7 @@ comment EXYNOS SoCs
config SOC_EXYNOS4210
bool SAMSUNG EXYNOS4210
default y
- depends on ARCH_EXYNOS4
+ select ARCH_EXYNOS4
select SAMSUNG_DMADEV
select ARM_CPU_SUSPEND if PM
select S5P_PM if PM
@@ -42,7 +41,7 @@ config SOC_EXYNOS4210
config SOC_EXYNOS4212
bool SAMSUNG EXYNOS4212
default y
- depends on ARCH_EXYNOS4
+ select ARCH_EXYNOS4
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
@@ -51,6 +50,7 @@ config SOC_EXYNOS4212
config SOC_EXYNOS4412
bool SAMSUNG EXYNOS4412
+ select ARCH_EXYNOS4
default y
depends on ARCH_EXYNOS4
select SAMSUNG_DMADEV
@@ -60,7 +60,7 @@ config SOC_EXYNOS4412
config SOC_EXYNOS5250
bool SAMSUNG EXYNOS5250
default y
- depends on ARCH_EXYNOS5
+ select ARCH_EXYNOS5
select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
@@ -176,8 +176,6 @@ config EXYNOS_SETUP_SPI
# machine support
-if ARCH_EXYNOS4
-
comment EXYNOS4210 Boards
config MACH_SMDKC210
@@ -397,7 +395,6 @@ config MACH_SMDK4412
select MACH_SMDK4212
help
Machine support for Samsung SMDK4412
-endif
comment Flattened Device Tree based board for EXYNOS SoCs
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 8545069..c559609 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -67,7 +67,7 @@ comment DEVFREQ Drivers
config ARM_EXYNOS4_BUS_DEVFREQ
bool ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver
- depends on SOC_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412
+ depends on ARCH_EXYNOS4
select ARCH_HAS_OPP
select DEVFREQ_GOV_SIMPLE_ONDEMAND
help
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index b090415..5e2083b 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -716,7 +716,7 @@ static const struct dev_pm_ops sdhci_s3c_pmops = {
#define SDHCI_S3C_PMOPS NULL
#endif
-#if defined(CONFIG_SOC_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+#if defined(CONFIG_ARCH_EXYNOS4)
static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
.sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
};
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 175ba6e..c689091 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1594,8 +1594,7 @@ static struct s3c24xx_serial_drv_data
s5pv210_serial_drv_data = {
#define S5PV210_SERIAL_DRV_DATA(kernel_ulong_t)NULL
#endif
-#if defined(CONFIG_SOC_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
- defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
+#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
.info = (struct s3c24xx_uart_info) {
.name = Samsung Exynos4 UART,
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4] ARM: EXYNOS: Kconfig: Group EXYNOS{4212,4412} into EXYNOS4X12
This patch adds CONFIG_EXYNOS4X12, which is automatically selected
whenever there is at least one SoC from Exynos4x12 line enabled. All the
shared dependencies of EXYNOS{4212,4412} are moved to this new
option.
This fixes build with Exynos4412 enabled and Exynos4212 and Exynos4210
disabled and also allows to simplify conditional compilation in several
places.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 15 +--
arch/arm/mach-exynos/Makefile | 2 +-
arch/arm/mach-exynos/common.h | 2 +-
drivers/cpufreq/Kconfig.arm | 2 +-
4 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9f91892..6ea95f0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -38,22 +38,25 @@ config SOC_EXYNOS4210
help
Enable EXYNOS4210 CPU support
-config SOC_EXYNOS4212
- bool SAMSUNG EXYNOS4212
- default y
+config SOC_EXYNOS4X12
+ def_bool n
select ARCH_EXYNOS4
select SAMSUNG_DMADEV
+ select ARM_CPU_SUSPEND if PM
select S5P_PM if PM
select S5P_SLEEP if PM
+
+config SOC_EXYNOS4212
+ bool SAMSUNG EXYNOS4212
+ select SOC_EXYNOS4X12
+ default y
help
Enable EXYNOS4212 SoC support
config SOC_EXYNOS4412
bool SAMSUNG EXYNOS4412
- select ARCH_EXYNOS4
+ select SOC_EXYNOS4X12
default y
- depends on ARCH_EXYNOS4
- select SAMSUNG_DMADEV
help
Enable EXYNOS4412 SoC support
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index ceeb8c9..f88fcb6 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
obj-$(CONFIG_SOC_EXYNOS4210) += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
+obj-$(CONFIG_SOC_EXYNOS4X12) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 054c786..a8cb3e6 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -52,7 +52,7 @@ void exynos4210_register_clocks(void);
#define exynos4210_register_clocks()
#endif
-#ifdef CONFIG_SOC_EXYNOS4212
+#ifdef CONFIG_SOC_EXYNOS4X12
void exynos4212_register_clocks(void);
#else
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index ca4ede3..d0ff91a 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -66,7 +66,7 @@ config ARM_EXYNOS4210_CPUFREQ
SoC (S5PV310 or S5PC210).
config ARM_EXYNOS4X12_CPUFREQ
- def_bool (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+ def_bool SOC_EXYNOS4X12
help
This adds the CPUFreq driver for Samsung EXYNOS4X12
SoC (EXYNOS4212 or EXYNOS4412).
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] ARM: EXYNOS: Kconfig: Remove dependencies on particular SoCs from DT machines
MACH_EXYNOS{4,5}_DT are used for whole SoC lines, so they should depend
on ARCH_EXYNOS{4,5} rather than on particular SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6ea95f0..2e82ce7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -404,7 +404,6 @@ comment Flattened Device Tree based board for EXYNOS SoCs
config MACH_EXYNOS4_DT
bool Samsung Exynos4 Machine using device tree
depends on ARCH_EXYNOS4
- select SOC_EXYNOS4210
select USE_OF
select ARM_AMBA
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
@@ -419,7 +418,6 @@ config MACH_EXYNOS4_DT
config MACH_EXYNOS5_DT
bool SAMSUNG EXYNOS5 Machine using device tree
depends on ARCH_EXYNOS5
- select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
help
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: exynos4: Enable serial controllers on Origen and SMDKV310
This patch adds status override of serial nodes to enable used serial ports
on Origen and SMDKV310 board.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts | 16
arch/arm/boot/dts/exynos4210-smdkv310.dts | 16
2 files changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index d1a1101..c7295fb 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,22 @@
status = okay;
};
+ serial@1380 {
+ status = okay;
+ };
+
+ serial@1381 {
+ status = okay;
+ };
+
+ serial@1382 {
+ status = okay;
+ };
+
+ serial@1383 {
+ status = okay;
+ };
+
gpio_keys {
compatible = gpio-keys;
#address-cells = 1;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index b87cca2..f634907 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,22 @@
status = okay;
};
+ serial@1380 {
+ status = okay;
+ };
+
+ serial@1381 {
+ status = okay;
+ };
+
+ serial@1382 {
+ status = okay;
+ };
+
+ serial@1383 {
+ status = okay;
+ };
+
keypad@100A {
samsung,keypad-num-rows = 2;
samsung,keypad-num-columns = 8;
--
1.7.12
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: exynos4: Enable serial controllers on Origen and SMDKV310
Hi Kgene, On Monday 08 of October 2012 15:12:48 Tomasz Figa wrote: This patch adds status override of serial nodes to enable used serial ports on Origen and SMDKV310 board. Signed-off-by: Tomasz Figa t.f...@samsung.com --- arch/arm/boot/dts/exynos4210-origen.dts | 16 arch/arm/boot/dts/exynos4210-smdkv310.dts | 16 2 files changed, 32 insertions(+) I think you missed this patch when applying Exynos dts reorganization patches. It is needed to enable serial ports on Origen and SMDKV310 boards. Could you apply it as well? Best regards, -- Tomasz Figa Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 15/32 v3] USB: ohci: merge ohci_finish_controller_resume with ohci_resume
Merge ohci_finish_controller_resume with ohci_resume as suggested by Alan
Stern. Since ohci_finish_controller_resume no longer exists, update the
various OHCI drivers to call ohci_resume() instead. Some drivers used to set
themselves the bit HCD_FLAG_HW_ACCESSIBLE, which is now handled by
ohci_resume().
Acked-by: Jingoo Han jg1@samsung.com
Acked-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Florian Fainelli flor...@openwrt.org
---
Changes in v3:
- rebased against greg's latest usb-next
Changes in v2:
- added Nicolas and Jingoo's Acked-by
drivers/usb/host/ohci-at91.c |2 +-
drivers/usb/host/ohci-ep93xx.c |2 +-
drivers/usb/host/ohci-exynos.c |5 +
drivers/usb/host/ohci-hcd.c | 41 +++--
drivers/usb/host/ohci-hub.c | 42 --
drivers/usb/host/ohci-omap.c |2 +-
drivers/usb/host/ohci-platform.c |2 +-
drivers/usb/host/ohci-pxa27x.c |2 +-
drivers/usb/host/ohci-s3c2410.c |3 +--
drivers/usb/host/ohci-spear.c|2 +-
drivers/usb/host/ohci-tmio.c |2 +-
11 files changed, 48 insertions(+), 57 deletions(-)
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 0bf72f9..908d84a 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -705,7 +705,7 @@ static int ohci_hcd_at91_drv_resume(struct platform_device
*pdev)
if (!clocked)
at91_start_clock();
- ohci_finish_controller_resume(hcd);
+ ohci_resume(hcd, false);
return 0;
}
#else
diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c
index dbfbd1d..a982f04 100644
--- a/drivers/usb/host/ohci-ep93xx.c
+++ b/drivers/usb/host/ohci-ep93xx.c
@@ -194,7 +194,7 @@ static int ohci_hcd_ep93xx_drv_resume(struct
platform_device *pdev)
ep93xx_start_hc(pdev-dev);
- ohci_finish_controller_resume(hcd);
+ ohci_resume(hcd, false);
return 0;
}
#endif
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 20a5008..929a494 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -252,10 +252,7 @@ static int exynos_ohci_resume(struct device *dev)
if (pdata pdata-phy_init)
pdata-phy_init(pdev, S5P_USB_PHY_HOST);
- /* Mark hardware accessible again as we are out of D3 state by now */
- set_bit(HCD_FLAG_HW_ACCESSIBLE, hcd-flags);
-
- ohci_finish_controller_resume(hcd);
+ ohci_resume(hcd, false);
return 0;
}
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 31a4616..8e17f17 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1007,13 +1007,50 @@ static int __maybe_unused ohci_suspend(struct usb_hcd
*hcd, bool do_wakeup)
static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
{
+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+ int port;
+ boolneed_reinit = false;
+
set_bit(HCD_FLAG_HW_ACCESSIBLE, hcd-flags);
/* Make sure resume from hibernation re-enumerates everything */
if (hibernated)
- ohci_usb_reset(hcd_to_ohci(hcd));
+ ohci_usb_reset(ohci);
+
+ /* See if the controller is already running or has been reset */
+ ohci-hc_control = ohci_readl(ohci, ohci-regs-control);
+ if (ohci-hc_control (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
+ need_reinit = true;
+ } else {
+ switch (ohci-hc_control OHCI_CTRL_HCFS) {
+ case OHCI_USB_OPER:
+ case OHCI_USB_RESET:
+ need_reinit = true;
+ }
+ }
+
+ /* If needed, reinitialize and suspend the root hub */
+ if (need_reinit) {
+ spin_lock_irq(ohci-lock);
+ ohci_rh_resume(ohci);
+ ohci_rh_suspend(ohci, 0);
+ spin_unlock_irq(ohci-lock);
+ }
+
+ /* Normally just turn on port power and enable interrupts */
+ else {
+ ohci_dbg(ohci, powerup ports\n);
+ for (port = 0; port ohci-num_ports; port++)
+ ohci_writel(ohci, RH_PS_PPS,
+ ohci-regs-roothub.portstatus[port]);
+
+ ohci_writel(ohci, OHCI_INTR_MIE, ohci-regs-intrenable);
+ ohci_readl(ohci, ohci-regs-intrenable);
+ msleep(20);
+ }
+
+ usb_hcd_resume_root_hub(hcd);
- ohci_finish_controller_resume(hcd);
return 0;
}
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index 2f3619e..db09dae 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -316,48 +316,6 @@ static int ohci_bus_resume (struct usb_hcd *hcd)
return rc;
}
-/* Carry out the final steps of resuming the controller device */
[PATCH 0/5] Adding usb2.0 host-phy support for exynos5250
This patchset is based on the work by Praveen Paneri for samsung-usbphy driver: http://comments.gmane.org/gmane.linux.kernel.samsung-soc/12653 Tested on smdk5250 target with usb-next branch along with arch patches for exynos5250: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/13042 http://thread.gmane.org/gmane.linux.kernel.samsung-soc/13048 Also tested successfully on smdkv310 for any break. Vivek Gautam (5): usb: phy: samsung: Add host phy support to samsung-phy driver ARM: S3C64XX: Add phy_type to pmu_isolation ARM: Exynos5250: Enabling samsung-usbphy driver usb: s5p-ehci: Adding phy driver support usb: exynos-ohci: Adding phy driver support .../devicetree/bindings/usb/samsung-usbphy.txt | 12 +- arch/arm/boot/dts/exynos5250.dtsi |5 + arch/arm/mach-exynos/Kconfig |1 + arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 10 + arch/arm/mach-exynos/setup-usb-phy.c | 45 ++- arch/arm/mach-s3c64xx/setup-usb-phy.c |2 +- arch/arm/plat-samsung/include/plat/usb-phy.h |3 +- drivers/usb/host/ehci-s5p.c| 62 +++- drivers/usb/host/ohci-exynos.c | 62 +++- drivers/usb/phy/Kconfig|1 - drivers/usb/phy/samsung-usbphy.c | 362 ++-- include/linux/platform_data/samsung-usbphy.h |9 +- 13 files changed, 497 insertions(+), 78 deletions(-) -- 1.7.6.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] usb: phy: samsung: Add host phy support to samsung-phy driver
This patch adds host phy support for samsung's exynos5250. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- drivers/usb/phy/Kconfig |1 - drivers/usb/phy/samsung-usbphy.c | 362 -- include/linux/platform_data/samsung-usbphy.h |9 +- 3 files changed, 344 insertions(+), 28 deletions(-) diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 313685f..1ce5b32 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -35,7 +35,6 @@ config MV_U3D_PHY config SAMSUNG_USBPHY bool Samsung USB PHY controller Driver - depends on USB_S3C_HSOTG select USB_OTG_UTILS help Enable this to support Samsung USB phy controller for samsung diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c index ee2dee0..504ef84 100644 --- a/drivers/usb/phy/samsung-usbphy.c +++ b/drivers/usb/phy/samsung-usbphy.c @@ -61,9 +61,114 @@ #define MHZ (1000*1000) #endif +/* EXYNOS5 */ +#define EXYNOS5_PHYHOST(0x00) + +#define EXYNOS5_PHYHOST_PHYSWRSTALL(0x1 31) + +#define EXYNOS5_PHYHOST_REFCLKSEL_MASK (0x3) +#define EXYNOS5_PHYHOST_REFCLKSEL(_x) ((_x) 19) +#define EXYNOS5_PHYHOST_REFCLKSEL_XTAL \ + EXYNOS5_PHYHOST_REFCLKSEL(0x0) +#define EXYNOS5_PHYHOST_REFCLKSEL_EXTL \ + EXYNOS5_PHYHOST_REFCLKSEL(0x1) +#define EXYNOS5_PHYHOST_REFCLKSEL_CLKCORE \ + EXYNOS5_PHYHOST_REFCLKSEL(0x2) + +#define EXYNOS5_PHYHOST_FSEL_MASK (0x7 16) +#define EXYNOS5_PHYHOST_FSEL(_x) ((_x) 16) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_50M(0x7) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_24M(0x5) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_20M(0x4) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K (0x3) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_12M(0x2) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_10M(0x1) +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K (0x0) + +#define EXYNOS5_PHYHOST_COMMONON_N (0x1 9) +#define EXYNOS5_PHYHOST_SIDDQ (0x1 6) +#define EXYNOS5_PHYHOST_FORCESLEEP (0x1 5) +#define EXYNOS5_PHYHOST_FORCESUSPEND (0x1 4) +#define EXYNOS5_PHYHOST_WORDINTERFACE (0x1 3) +#define EXYNOS5_PHYHOST_UTMISWRST (0x1 2) +#define EXYNOS5_PHYHOST_LINKSWRST (0x1 1) +#define EXYNOS5_PHYHOST_PHYSWRST (0x1 0) + +#define EXYNOS5_PHYHOST_TUNE0 (0x04) + +#define EXYNOS5_PHYHOST_TEST0 (0x08) + +#define EXYNOS5_PHYHSIC1 (0x10) + +#define EXYNOS5_PHYHSIC2 (0x20) + +#define EXYNOS5_PHYHSIC_REFCLKSEL_MASK (0x3) +#define EXYNOS5_PHYHSIC_REFCLKSEL (0x2 23) + +#define EXYNOS5_PHYHSIC_REFCLKDIV_MASK (0x7f) +#define EXYNOS5_PHYHSIC_REFCLKDIV(_x) ((_x) 16) +#define EXYNOS5_PHYHSIC_REFCLKDIV_12 \ + EXYNOS5_PHYHSIC_REFCLKDIV(0x24) +#define EXYNOS5_PHYHSIC_REFCLKDIV_15 \ + EXYNOS5_PHYHSIC_REFCLKDIV(0x1C) +#define EXYNOS5_PHYHSIC_REFCLKDIV_16 \ + EXYNOS5_PHYHSIC_REFCLKDIV(0x1A) +#define EXYNOS5_PHYHSIC_REFCLKDIV_19_2 \ + EXYNOS5_PHYHSIC_REFCLKDIV(0x15) +#define EXYNOS5_PHYHSIC_REFCLKDIV_20 \ + EXYNOS5_PHYHSIC_REFCLKDIV(0x14) + +#define EXYNOS5_PHYHSIC_SIDDQ (0x1 6) +#define EXYNOS5_PHYHSIC_FORCESLEEP (0x1 5) +#define EXYNOS5_PHYHSIC_FORCESUSPEND (0x1 4) +#define EXYNOS5_PHYHSIC_WORDINTERFACE (0x1 3) +#define EXYNOS5_PHYHSIC_UTMISWRST (0x1 2) +#define EXYNOS5_PHYHSIC_PHYSWRST (0x1 0) + +#define EXYNOS5_EHCICTRL (0x30) + +#define EXYNOS5_EHCICTRL_ENAINCRXALIGN (0x1 29) +#define EXYNOS5_EHCICTRL_ENAINCR4 (0x1 28) +#define EXYNOS5_EHCICTRL_ENAINCR8 (0x1 27) +#define EXYNOS5_EHCICTRL_ENAINCR16 (0x1 26) + +#define EXYNOS5_OHCICTRL (0x34) + +#define EXYNOS5_OHCICTRL_SUSPLGCY (0x1 3) +#define EXYNOS5_OHCICTRL_APPSTARTCLK (0x1 2) +#define EXYNOS5_OHCICTRL_CNTSEL(0x1 1) +#define EXYNOS5_OHCICTRL_CLKCKTRST (0x1 0) + +#define EXYNOS5_PHYOTG (0x38) + +#define EXYNOS5_PHYOTG_PHYLINK_SWRESET (0x1 14) +#define EXYNOS5_PHYOTG_LINKSWRST_UOTG (0x1 13) +#define EXYNOS5_PHYOTG_PHY0_SWRST (0x1 12) + +#define EXYNOS5_PHYOTG_REFCLKSEL_MASK (0x3 9) +#define EXYNOS5_PHYOTG_REFCLKSEL(_x) ((_x) 9) +#define EXYNOS5_PHYOTG_REFCLKSEL_XTAL \ + EXYNOS5_PHYOTG_REFCLKSEL(0x0) +#define EXYNOS5_PHYOTG_REFCLKSEL_EXTL \ + EXYNOS5_PHYOTG_REFCLKSEL(0x1) +#define
[PATCH 2/5] ARM: S3C64XX: Add phy_type to pmu_isolation
It adds 'type' argument to pmu_isolation function, aligning
with other platforms, which keeps track of usbphy_type.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/mach-s3c64xx/setup-usb-phy.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c
b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 3aee778..b7d1d95 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -13,7 +13,7 @@
#include mach/map.h
#include mach/regs-sys.h
-void s5p_usb_phy_pmu_isolation(int on)
+void s5p_usb_phy_pmu_isolation(int on, int type)
{
if (on) {
writel(readl(S3C64XX_OTHERS) ~S3C64XX_OTHERS_USBMASK,
--
1.7.6.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] ARM: Exynos5250: Enabling samsung-usbphy driver
Adding usbphy node for Exynos5250 along with the platform data.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/usb/samsung-usbphy.txt | 12 -
arch/arm/boot/dts/exynos5250.dtsi |5 ++
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/include/mach/map.h|1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 10
arch/arm/mach-exynos/setup-usb-phy.c | 45
arch/arm/plat-samsung/include/plat/usb-phy.h |3 +-
7 files changed, 66 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 7d54d59..35aaf91 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -1,11 +1,19 @@
* Samsung's usb phy transceiver
-The Samsung's phy transceiver is used for controlling usb otg phy for
-s3c-hsotg usb device controller.
+The Samsung's phy transceiver is used for controlling usb phy for
+s3c-hsotg as well as s5p-ehci and exynos-ohci device controllers
+across Samsung SOCs.
TODO: Adding the PHY binding with controller(s) according to the under
developement generic PHY driver.
+Exynos4210:
Required properties:
- compatible : should be samsung,exynos4210-usbphy
- reg : base physical address of the phy registers and length of memory mapped
region.
+
+Exynos5250:
+Required properties:
+- compatible : should be samsung,exynos5250-usbphy
+- reg : base physical address of the phy registers and length of memory mapped
+ region.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e..82bf042 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -218,6 +218,11 @@
#size-cells = 0;
};
+ usbphy {
+ compatible = samsung,exynos5250-usbphy;
+ reg = 0x1213 0x100;
+ };
+
amba {
#address-cells = 1;
#size-cells = 1;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4372075..e8e3d7b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
+ select EXYNOS4_SETUP_USB_PHY
help
Machine support for Samsung EXYNOS5 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS5 SoC based
board.
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 9694424..7f5eb03 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -195,6 +195,7 @@
#define EXYNOS4_PA_EHCI0x1258
#define EXYNOS4_PA_OHCI0x1259
#define EXYNOS4_PA_HSPHY 0x125B
+#define EXYNOS5_PA_HSPHY 0x1213
#define EXYNOS4_PA_MFC 0x1340
#define EXYNOS4_PA_UART0x1380
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8e..6d9528a 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,7 @@
#include linux/of_platform.h
#include linux/serial_core.h
+#include linux/platform_data/samsung-usbphy.h
#include asm/mach/arch.h
#include asm/hardware/gic.h
@@ -18,9 +19,16 @@
#include plat/cpu.h
#include plat/regs-serial.h
+#include plat/usb-phy.h
#include common.h
+static struct samsung_usbphy_data exynos5_usbphy_pdata = {
+ .pmu_isolation = s5p_usb_phy_pmu_isolation,
+ .phy_cfg_sel = s5p_usb_phy_cfg_sel,
+ .type = TYPE_HOST,
+};
+
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
@@ -72,6 +80,8 @@ static const struct of_dev_auxdata
exynos5250_auxdata_lookup[] __initconst = {
exynos-gsc.2, NULL),
OF_DEV_AUXDATA(samsung,exynos5-gsc, EXYNOS5_PA_GSC3,
exynos-gsc.3, NULL),
+ OF_DEV_AUXDATA(samsung,exynos5250-usbphy, EXYNOS5_PA_HSPHY,
+ s3c-usbphy, exynos5_usbphy_pdata),
{},
};
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c
b/arch/arm/mach-exynos/setup-usb-phy.c
index 1c62d20..039d246 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -14,10 +14,14 @@
#include linux/err.h
#include linux/io.h
#include linux/platform_device.h
+#include linux/platform_data/samsung-usbphy.h
#include mach/regs-pmu.h
#include mach/regs-usb-phy.h
#include plat/cpu.h
#include plat/usb-phy.h
[PATCH 4/5] usb: s5p-ehci: Adding phy driver support
Adding the transceiver to ehci driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/ehci-s5p.c | 62 +-
1 files changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 85b74be..ac22893 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -18,6 +18,7 @@
#include linux/of_gpio.h
#include linux/platform_data/usb-ehci-s5p.h
#include plat/usb-phy.h
+#include linux/usb/phy.h
#define EHCI_INSNREG00(base) (base + 0x90)
#define EHCI_INSNREG00_ENA_INCR16 (0x1 25)
@@ -32,6 +33,8 @@ struct s5p_ehci_hcd {
struct device *dev;
struct usb_hcd *hcd;
struct clk *clk;
+ struct usb_phy *phy;
+ struct s5p_ehci_platdata *pdata;
};
static const struct hc_driver s5p_ehci_hc_driver = {
@@ -65,6 +68,26 @@ static const struct hc_driver s5p_ehci_hc_driver = {
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
};
+static void s5p_ehci_phy_enable(struct s5p_ehci_hcd *s5p_ehci)
+{
+ struct platform_device *pdev = to_platform_device(s5p_ehci-dev);
+
+ if (s5p_ehci-phy)
+ usb_phy_init(s5p_ehci-phy);
+ else if (s5p_ehci-pdata-phy_init)
+ s5p_ehci-pdata-phy_init(pdev, S5P_USB_PHY_HOST);
+}
+
+static void s5p_ehci_phy_disable(struct s5p_ehci_hcd *s5p_ehci)
+{
+ struct platform_device *pdev = to_platform_device(s5p_ehci-dev);
+
+ if (s5p_ehci-phy)
+ usb_phy_shutdown(s5p_ehci-phy);
+ else if (s5p_ehci-pdata-phy_exit)
+ s5p_ehci-pdata-phy_exit(pdev, S5P_USB_PHY_HOST);
+}
+
static void s5p_setup_vbus_gpio(struct platform_device *pdev)
{
int err;
@@ -92,15 +115,10 @@ static int __devinit s5p_ehci_probe(struct platform_device
*pdev)
struct usb_hcd *hcd;
struct ehci_hcd *ehci;
struct resource *res;
+ struct usb_phy *phy;
int irq;
int err;
- pdata = pdev-dev.platform_data;
- if (!pdata) {
- dev_err(pdev-dev, No platform data defined\n);
- return -EINVAL;
- }
-
/*
* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
@@ -118,6 +136,20 @@ static int __devinit s5p_ehci_probe(struct platform_device
*pdev)
if (!s5p_ehci)
return -ENOMEM;
+ pdata = pdev-dev.platform_data;
+ if (!pdata) {
+ /* Fallback to Phy transceiver */
+ phy = devm_usb_get_phy(pdev-dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ dev_err(pdev-dev, no platform data or transceiver
defined\n);
+ return -EPROBE_DEFER;
+ } else {
+ s5p_ehci-phy = phy;
+ }
+ } else {
+ s5p_ehci-pdata = pdata;
+ }
+
s5p_ehci-dev = pdev-dev;
hcd = usb_create_hcd(s5p_ehci_hc_driver, pdev-dev,
@@ -163,8 +195,7 @@ static int __devinit s5p_ehci_probe(struct platform_device
*pdev)
goto fail_io;
}
- if (pdata-phy_init)
- pdata-phy_init(pdev, S5P_USB_PHY_HOST);
+ s5p_ehci_phy_enable(s5p_ehci);
ehci = hcd_to_ehci(hcd);
ehci-caps = hcd-regs;
@@ -184,6 +215,7 @@ static int __devinit s5p_ehci_probe(struct platform_device
*pdev)
fail_io:
clk_disable(s5p_ehci-clk);
+ s5p_ehci_phy_disable(s5p_ehci);
fail_clk:
usb_put_hcd(hcd);
return err;
@@ -191,14 +223,12 @@ fail_clk:
static int __devexit s5p_ehci_remove(struct platform_device *pdev)
{
- struct s5p_ehci_platdata *pdata = pdev-dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci-hcd;
usb_remove_hcd(hcd);
- if (pdata pdata-phy_exit)
- pdata-phy_exit(pdev, S5P_USB_PHY_HOST);
+ s5p_ehci_phy_disable(s5p_ehci);
clk_disable(s5p_ehci-clk);
@@ -222,14 +252,11 @@ static int s5p_ehci_suspend(struct device *dev)
struct s5p_ehci_hcd *s5p_ehci = dev_get_drvdata(dev);
struct usb_hcd *hcd = s5p_ehci-hcd;
bool do_wakeup = device_may_wakeup(dev);
- struct platform_device *pdev = to_platform_device(dev);
- struct s5p_ehci_platdata *pdata = pdev-dev.platform_data;
int rc;
rc = ehci_suspend(hcd, do_wakeup);
- if (pdata pdata-phy_exit)
- pdata-phy_exit(pdev, S5P_USB_PHY_HOST);
+ s5p_ehci_phy_disable(s5p_ehci);
clk_disable(s5p_ehci-clk);
@@ -240,13 +267,10 @@ static int s5p_ehci_resume(struct device *dev)
{
struct s5p_ehci_hcd *s5p_ehci = dev_get_drvdata(dev);
struct usb_hcd *hcd =
[PATCH 5/5] usb: exynos-ohci: Adding phy driver support
Adding the transceiver to ohci driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/ohci-exynos.c | 62 +++
1 files changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 20a5008..e0ed594 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -16,13 +16,36 @@
#include linux/platform_device.h
#include linux/platform_data/usb-exynos.h
#include plat/usb-phy.h
+#include linux/usb/phy.h
struct exynos_ohci_hcd {
struct device *dev;
struct usb_hcd *hcd;
struct clk *clk;
+ struct usb_phy *phy;
+ struct exynos4_ohci_platdata *pdata;
};
+static void exynos_ohci_phy_enable(struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct platform_device *pdev = to_platform_device(exynos_ohci-dev);
+
+ if (exynos_ohci-phy)
+ usb_phy_init(exynos_ohci-phy);
+ else if (exynos_ohci-pdata-phy_init)
+ exynos_ohci-pdata-phy_init(pdev, S5P_USB_PHY_HOST);
+}
+
+static void exynos_ohci_phy_disable(struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct platform_device *pdev = to_platform_device(exynos_ohci-dev);
+
+ if (exynos_ohci-phy)
+ usb_phy_shutdown(exynos_ohci-phy);
+ else if (exynos_ohci-pdata-phy_exit)
+ exynos_ohci-pdata-phy_exit(pdev, S5P_USB_PHY_HOST);
+}
+
static int ohci_exynos_start(struct usb_hcd *hcd)
{
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
@@ -81,15 +104,10 @@ static int __devinit exynos_ohci_probe(struct
platform_device *pdev)
struct usb_hcd *hcd;
struct ohci_hcd *ohci;
struct resource *res;
+ struct usb_phy *phy;
int irq;
int err;
- pdata = pdev-dev.platform_data;
- if (!pdata) {
- dev_err(pdev-dev, No platform data defined\n);
- return -EINVAL;
- }
-
/*
* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
@@ -105,6 +123,20 @@ static int __devinit exynos_ohci_probe(struct
platform_device *pdev)
if (!exynos_ohci)
return -ENOMEM;
+ pdata = pdev-dev.platform_data;
+ if (!pdata) {
+ /* Fallback to Phy transceiver */
+ phy = devm_usb_get_phy(pdev-dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR_OR_NULL(phy)) {
+ dev_err(pdev-dev, no platform data or transceiver
defined\n);
+ return -EPROBE_DEFER;
+ } else {
+ exynos_ohci-phy = phy;
+ }
+ } else {
+ exynos_ohci-pdata = pdata;
+ }
+
exynos_ohci-dev = pdev-dev;
hcd = usb_create_hcd(exynos_ohci_hc_driver, pdev-dev,
@@ -150,8 +182,7 @@ static int __devinit exynos_ohci_probe(struct
platform_device *pdev)
goto fail_io;
}
- if (pdata-phy_init)
- pdata-phy_init(pdev, S5P_USB_PHY_HOST);
+ exynos_ohci_phy_enable(exynos_ohci);
ohci = hcd_to_ohci(hcd);
ohci_hcd_init(ohci);
@@ -168,6 +199,7 @@ static int __devinit exynos_ohci_probe(struct
platform_device *pdev)
fail_io:
clk_disable(exynos_ohci-clk);
+ exynos_ohci_phy_disable(exynos_ohci);
fail_clken:
clk_put(exynos_ohci-clk);
fail_clk:
@@ -177,14 +209,12 @@ fail_clk:
static int __devexit exynos_ohci_remove(struct platform_device *pdev)
{
- struct exynos4_ohci_platdata *pdata = pdev-dev.platform_data;
struct exynos_ohci_hcd *exynos_ohci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = exynos_ohci-hcd;
usb_remove_hcd(hcd);
- if (pdata pdata-phy_exit)
- pdata-phy_exit(pdev, S5P_USB_PHY_HOST);
+ exynos_ohci_phy_disable(exynos_ohci);
clk_disable(exynos_ohci-clk);
clk_put(exynos_ohci-clk);
@@ -209,8 +239,6 @@ static int exynos_ohci_suspend(struct device *dev)
struct exynos_ohci_hcd *exynos_ohci = dev_get_drvdata(dev);
struct usb_hcd *hcd = exynos_ohci-hcd;
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
- struct platform_device *pdev = to_platform_device(dev);
- struct exynos4_ohci_platdata *pdata = pdev-dev.platform_data;
unsigned long flags;
int rc = 0;
@@ -229,8 +257,7 @@ static int exynos_ohci_suspend(struct device *dev)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, hcd-flags);
- if (pdata pdata-phy_exit)
- pdata-phy_exit(pdev, S5P_USB_PHY_HOST);
+ exynos_ohci_phy_disable(exynos_ohci);
clk_disable(exynos_ohci-clk);
@@ -244,13 +271,10 @@ static int exynos_ohci_resume(struct device *dev)
{
struct exynos_ohci_hcd *exynos_ohci = dev_get_drvdata(dev);
struct usb_hcd *hcd =
