[PATCH] ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor

2013-05-31 Thread Leela Krishna Amudala 
This patch reads the cpuid part number and if it matches with
cortex-A9, calls scu_enable()

Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
 arch/arm/mach-exynos/platsmp.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7..d9c6d0a 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -200,7 +200,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int 
max_cpus)
 {
int i;
 
-   if (!(soc_is_exynos5250() || soc_is_exynos5440()))
+   if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
scu_enable(scu_base_addr());
 
/*
-- 
1.7.10.4

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[PATCH 1/3] ARM: EXYNOS: uncompress - print debug messages if DEBUG_LL is defined

2013-05-31 Thread Tushar Behera 
Printing low-level debug messages make an assumption that the specified
UART port has been preconfigured by the bootloader. Incorrectly
specified UART port results in system getting stalled while printing the
message Uncompressing Linux... done, booting the kernel

This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since
the UART port might different for different board, it is not possible to
specify it correctly for every board that use a common defconfig file.

Calling this print subroutine only when DEBUG_LL fixes the problem. By
disabling DEBUG_LL in default config file, we would be able to boot
multiple boards with different default UART ports.

With this current approach, we miss the print Uncompressing Linux...
done, booting the kernel. when DEBUG_LL is not defined.

Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
 arch/arm/mach-exynos/include/mach/uncompress.h  |   11 ---
 arch/arm/plat-samsung/include/plat/uncompress.h |   10 +-
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h 
b/arch/arm/mach-exynos/include/mach/uncompress.h
index 2979995..730f69f 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -37,11 +37,16 @@ static void arch_detect_cpu(void)
chip_id = 20;
chip_id = 0xf;
 
+#ifdef CONFIG_DEBUG_LL
if (chip_id == 0x5)
-   uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * 
CONFIG_S3C_LOWLEVEL_UART_PORT);
+   uart_base = (volatile u8 *)EXYNOS5_PA_UART +
+   (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
else
-   uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * 
CONFIG_S3C_LOWLEVEL_UART_PORT);
-
+   uart_base = (volatile u8 *)EXYNOS4_PA_UART +
+   (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+   uart_base = NULL;
+#endif
/*
 * For preventing FIFO overrun or infinite loop of UART console,
 * fifo_max should be the minimum fifo size of all of the UART channels
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h 
b/arch/arm/plat-samsung/include/plat/uncompress.h
index 438b248..350032b 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -66,6 +66,9 @@ uart_rd(unsigned int reg)
 
 static void putc(int ch)
 {
+   if (!uart_base)
+   return;
+
if (uart_rd(S3C2410_UFCON)  S3C2410_UFCON_FIFOMODE) {
int level;
 
@@ -118,7 +121,12 @@ static void arch_decomp_error(const char *x)
 #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
 static inline void arch_enable_uart_fifo(void)
 {
-   u32 fifocon = uart_rd(S3C2410_UFCON);
+   u32 fifocon;
+
+   if (!uart_base)
+   return;
+
+   fifocon = uart_rd(S3C2410_UFCON);
 
if (!(fifocon  S3C2410_UFCON_FIFOMODE)) {
fifocon |= S3C2410_UFCON_RESETBOTH;
-- 
1.7.9.5

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[PATCH 0/3] Consolidate uncompress code for Samsung platform

2013-05-31 Thread Tushar Behera 
The patches are based on v3.10-rc3.

They are build tested for s3c2410_defconfig, s3c6400_defconfig,
s5p64x0_defconfig, s5pc100_defconfig, s5pv210_defconfig,
exynos4_defconfig and exynos_defconfig.

Since they affect all the Samsung boards, testing them on different
machines would be essential. Unfortunately I can only test on Exynos here.

Tested on Exynos5250 based Arndale board.

Tushar Behera (3):
  ARM: EXYNOS: uncompress - print debug messages if DEBUG_LL is defined
  ARM: SAMSUNG: Consolidate uncompress subroutine
  ARM: S5P64X0: Remove duplicate uncompress code

 arch/arm/mach-exynos/include/mach/uncompress.h  |   14 +-
 arch/arm/mach-s3c24xx/include/mach/uncompress.h |7 +
 arch/arm/mach-s3c64xx/include/mach/uncompress.h |7 +
 arch/arm/mach-s5p64x0/include/mach/uncompress.h |  163 ++-
 arch/arm/mach-s5pc100/include/mach/uncompress.h |6 +
 arch/arm/mach-s5pv210/include/mach/uncompress.h |6 +
 arch/arm/plat-samsung/include/plat/uncompress.h |   16 ++-
 7 files changed, 53 insertions(+), 166 deletions(-)

-- 
1.7.9.5

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[PATCH 3/3] ARM: S5P64X0: Remove duplicate uncompress code

2013-05-31 Thread Tushar Behera 
The uncompress code in S5P64X0 is almost same as the uncompress code
defined in plat-samsung. Better to reuse that code.

Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
 arch/arm/mach-s5p64x0/include/mach/uncompress.h |  163 ++-
 1 file changed, 8 insertions(+), 155 deletions(-)

diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h 
b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 19e0d64..b28a551 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -14,171 +14,24 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include mach/map.h
+#include plat/uncompress.h
 
-/*
- * cannot use commonly plat/uncompress.h
- * because uart base of S5P6440 and S5P6450 is different
- */
-
-typedef unsigned int upf_t;/* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-unsigned int fifo_mask;
-unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include plat/regs-serial.h
-#include plat/regs-watchdog.h
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX(14)
-
-unsigned long uart_base;
-
-static __inline__ void get_uart_base(void)
+static void arch_detect_cpu(void)
 {
unsigned int chipid;
 
chipid = *(const volatile unsigned int __force *) 0xE0100118;
 
-   uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
-
+#ifdef DEBUG_LL
if ((chipid  0xff000) == 0x5)
-   uart_base += 0xEC80;
+   uart_base = S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
else
-   uart_base += 0xEC00;
-}
-
-static __inline__ void uart_wr(unsigned int reg, unsigned int val)
-{
-   volatile unsigned int *ptr;
-
-   get_uart_base();
-   ptr = (volatile unsigned int *)(reg + uart_base);
-   *ptr = val;
-}
-
-static __inline__ unsigned int uart_rd(unsigned int reg)
-{
-   volatile unsigned int *ptr;
-
-   get_uart_base();
-   ptr = (volatile unsigned int *)(reg + uart_base);
-   return *ptr;
-}
-
-/*
- * we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
- */
-
-static void putc(int ch)
-{
-   if (uart_rd(S3C2410_UFCON)  S3C2410_UFCON_FIFOMODE) {
-   int level;
-
-   while (1) {
-   level = uart_rd(S3C2410_UFSTAT);
-   level = fifo_mask;
-
-   if (level  fifo_max)
-   break;
-   }
-
-   } else {
-   /* not using fifos */
-
-   while ((uart_rd(S3C2410_UTRSTAT)  S3C2410_UTRSTAT_TXE) != 
S3C2410_UTRSTAT_TXE)
-   barrier();
-   }
-
-   /* write byte to transmission register */
-   uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d, ad)\
-   do {\
-   *((volatile unsigned int __force *)(ad)) = (d); \
-   } while (0)
-
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-   putstr(\n\n);
-   putstr(x);
-   putstr(\n\n -- System resetting\n);
-
-   __raw_writel(0x4000, S3C2410_WTDAT);
-   __raw_writel(0x4000, S3C2410_WTCNT);
-   __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | 
S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-   while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-   u32 fifocon = uart_rd(S3C2410_UFCON);
-
-   if (!(fifocon  S3C2410_UFCON_FIFOMODE)) {
-   fifocon |= S3C2410_UFCON_RESETBOTH;
-   uart_wr(S3C2410_UFCON, fifocon);
-
-   /* wait for fifo reset to complete */
-   while (1) {
-   fifocon = uart_rd(S3C2410_UFCON);
-   if (!(fifocon  S3C2410_UFCON_RESETBOTH))
-   break;
-   }
-   }
-}
+   uart_base = S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 #else
-#define arch_enable_uart_fifo() do { } while(0)
+   uart_base = NULL;
 #endif
 
-static void arch_decomp_setup(void)
-{
-   /*
-* we may need to setup the uart(s) here if we are not running
-* on an BAST... the BAST will have left the uarts configured
-* after calling linux.
-*/
-
-   arch_detect_cpu();
-
-   /*
-* Enable the UART FIFOs if they where not enabled and our
-* configuration says we should turn them on.
-*/
-
-   arch_enable_uart_fifo();
+   fifo_mask = S3C2440_UFSTAT_TXMASK;
+

[PATCH 2/3] ARM: SAMSUNG: Consolidate uncompress subroutine

2013-05-31 Thread Tushar Behera 
For mach-exynos, uart_base is a pointer and the value is calculated
in the machine folder. For other machines, uart_base is defined as
a macro in platform directory. For symmetry, the uart_base macro
definition is removed and the uart_base calculation is moved to
specific machine folders.

This would help us consolidating uncompress subroutine for s5p64x0.

Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
 arch/arm/mach-exynos/include/mach/uncompress.h  |3 ---
 arch/arm/mach-s3c24xx/include/mach/uncompress.h |7 +++
 arch/arm/mach-s3c64xx/include/mach/uncompress.h |7 +++
 arch/arm/mach-s5pc100/include/mach/uncompress.h |6 ++
 arch/arm/mach-s5pv210/include/mach/uncompress.h |6 ++
 arch/arm/plat-samsung/include/plat/uncompress.h |6 ++
 6 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h 
b/arch/arm/mach-exynos/include/mach/uncompress.h
index 730f69f..30592fd 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -15,9 +15,6 @@
 #include asm/mach-types.h
 
 #include mach/map.h
-
-volatile u8 *uart_base;
-
 #include plat/uncompress.h
 
 static unsigned int __raw_readl(unsigned int ptr)
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h 
b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f8..638893e 100644
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
@@ -49,6 +49,13 @@ static void arch_detect_cpu(void)
fifo_mask = S3C2410_UFSTAT_TXMASK;
fifo_max = 15  S3C2410_UFSTAT_TXSHIFT;
}
+
+#ifdef CONFIG_DEBUG_LL
+   uart_base = (volatile u8 *) S3C_PA_UART +
+   (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+   uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h 
b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
index c6a82a2..d6f9188 100644
--- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -23,6 +23,13 @@ static void arch_detect_cpu(void)
/* we do not need to do any cpu detection here at the moment. */
fifo_mask = S3C2440_UFSTAT_TXMASK;
fifo_max = 63  S3C2440_UFSTAT_TXSHIFT;
+
+#ifdef CONFIG_DEBUG_LL
+   uart_base = (volatile u8 *)S3C_PA_UART +
+   (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+   uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h 
b/arch/arm/mach-s5pc100/include/mach/uncompress.h
index 01ccf53..c1242df 100644
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h
@@ -23,6 +23,12 @@ static void arch_detect_cpu(void)
/* we do not need to do any cpu detection here at the moment. */
fifo_mask = S3C2440_UFSTAT_TXMASK;
fifo_max = 63  S3C2440_UFSTAT_TXSHIFT;
+
+#ifdef CONFIG_DEBUG_LL
+   uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+   uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h 
b/arch/arm/mach-s5pv210/include/mach/uncompress.h
index ef977ea..2193812 100644
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h
@@ -21,6 +21,12 @@ static void arch_detect_cpu(void)
/* we do not need to do any cpu detection here at the moment. */
fifo_mask = S5PV210_UFSTAT_TXMASK;
fifo_max = 63  S5PV210_UFSTAT_TXSHIFT;
+
+#ifdef CONFIG_DEBUG_LL
+   uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
+#else
+   uart_base = NULL;
+#endif
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h 
b/arch/arm/plat-samsung/include/plat/uncompress.h
index 350032b..78274eb 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -21,6 +21,8 @@ typedef unsigned int upf_t;   /* cannot include 
linux/serial_core.h */
 unsigned int fifo_mask;
 unsigned int fifo_max;
 
+volatile u8 *uart_base;
+
 /* forward declerations */
 
 static void arch_detect_cpu(void);
@@ -37,10 +39,6 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX(14)
 
-#ifdef S3C_PA_UART
-#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * 
CONFIG_S3C_LOWLEVEL_UART_PORT)
-#endif
-
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
 {
-- 
1.7.9.5

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[PATCH v3 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx

2013-05-31 Thread Vikas Sajjan 
This patch adds set_rate and round_rate clk_ops for PLL36xx

Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
 drivers/clk/samsung/clk-pll.c |   59 +
 1 file changed, 59 insertions(+)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 9591560..7143ed89 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -210,6 +210,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char 
*name,
 #define PLL36XX_CON0_OFFSET(0x100)
 #define PLL36XX_CON1_OFFSET(0x104)
 
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR(3000)
+
 #define PLL36XX_KDIV_MASK  (0x)
 #define PLL36XX_MDIV_MASK  (0x1FF)
 #define PLL36XX_PDIV_MASK  (0x3F)
@@ -217,6 +220,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char 
*name,
 #define PLL36XX_MDIV_SHIFT (16)
 #define PLL36XX_PDIV_SHIFT (8)
 #define PLL36XX_SDIV_SHIFT (0)
+#define PLL36XX_KDIV_SHIFT (0)
+#define PLL36XX_LOCK_STAT_SHIFT(29)
 
 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -239,8 +244,57 @@ static unsigned long samsung_pll36xx_recalc_rate(struct 
clk_hw *hw,
return (unsigned long)fvco;
 }
 
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+   unsigned long parent_rate)
+{
+   struct samsung_clk_pll *pll = to_clk_pll(hw);
+   u32 tmp, pll_con0, pll_con1;
+   const struct samsung_pll_rate_table *rate;
+
+   rate = samsung_get_pll_settings(pll, drate);
+   if (!rate) {
+   pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+   drate, __clk_get_name(hw-clk));
+   return -EINVAL;
+   }
+
+   pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+   pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
+
+   /* Set PLL lock time. */
+   pll_writel(pll, (rate-pdiv * PLL36XX_LOCK_FACTOR),
+   PLL36XX_LOCK_OFFSET);
+
+/* Change PLL PMS values */
+   pll_con0 = ~((PLL36XX_MDIV_MASK  PLL36XX_MDIV_SHIFT) |
+   (PLL36XX_PDIV_MASK  PLL36XX_PDIV_SHIFT) |
+   (PLL36XX_SDIV_MASK  PLL36XX_SDIV_SHIFT));
+   pll_con0 |= (rate-mdiv  PLL36XX_MDIV_SHIFT) |
+   (rate-pdiv  PLL36XX_PDIV_SHIFT) |
+   (rate-sdiv  PLL36XX_SDIV_SHIFT);
+   pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+   pll_con1 = ~(PLL36XX_KDIV_MASK  PLL36XX_KDIV_SHIFT);
+   pll_con1 |= rate-kdiv  PLL36XX_KDIV_SHIFT;
+   pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+   /* wait_lock_time */
+   do {
+   cpu_relax();
+   tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+   } while (!(tmp  (1  PLL36XX_LOCK_STAT_SHIFT)));
+
+   return 0;
+}
+
 static const struct clk_ops samsung_pll36xx_clk_ops = {
.recalc_rate = samsung_pll36xx_recalc_rate,
+   .set_rate = samsung_pll36xx_set_rate,
+   .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+   .recalc_rate = samsung_pll36xx_recalc_rate,
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -264,6 +318,11 @@ struct clk * __init samsung_clk_register_pll36xx(const 
char *name,
init.parent_names = pname;
init.num_parents = 1;
 
+   if (rate_table  rate_count)
+   init.ops = samsung_pll36xx_clk_ops;
+   else
+   init.ops = samsung_pll36xx_clk_min_ops;
+
pll-hw.init = init;
pll-base = base;
pll-rate_table = rate_table;
-- 
1.7.9.5

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[PATCH v3 0/6] Add generic set_rate clk_ops for PLL35xx and PLL36xx for samsung SoCs

2013-05-31 Thread Vikas Sajjan 
This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
for PLL35xx  PLL36xx and usues clk-base instead of clk-con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
values for supported rates that needs to be changed for changing
corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35xx and PLL36xx

changes since v2:
- Added new patch to reorder the MUX registration for mout_vpllsrc MUX
before the PLL registrations. And to add the alias for the mout_vpllsrc 
MUX.
- Added a check to confirm parent rate while registrating the PLL
rate tables.

changes since v1:
- removed sorting and bsearch
- modified the definition of struct samsung_pll_rate_table
- added generic round_rate()
- rectified the ops assignment for rate table passed as NULL
  during PLL registration

Is rebased on branch kgene's for-next
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome 
tree.


Vikas Sajjan (3):
  clk: samsung: Add set_rate() clk_ops for PLL36xx
  clk: samsung: Add alias for mout_vpllsrc and reorder MUX registration
for it
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk-base instead of directly using clk-con0 for
PLL3xxx
  clk: samsung: Add support to register rate_table for PLL3xxx
  clk: samsung: Add set_rate() clk_ops for PLL35xx

 drivers/clk/samsung/clk-exynos4.c|   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   69 +--
 drivers/clk/samsung/clk-pll.c|  226 ++
 drivers/clk/samsung/clk-pll.h|   35 +-
 drivers/clk/samsung/clk.h|2 +
 5 files changed, 300 insertions(+), 42 deletions(-)

-- 
1.7.9.5

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[PATCH v3 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx

2013-05-31 Thread Vikas Sajjan 
From: Yadwinder Singh Brar yadi.b...@samsung.com

To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx  PLL36xx and usues clk-base instead of clk-con0.

Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
 drivers/clk/samsung/clk-exynos4.c|   10 ---
 drivers/clk/samsung/clk-exynos5250.c |   14 -
 drivers/clk/samsung/clk-pll.c|   54 ++
 drivers/clk/samsung/clk-pll.h|4 +--
 4 files changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c 
b/drivers/clk/samsung/clk-exynos4.c
index d0940e6..cf7d4e7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -97,12 +97,14 @@
 #define GATE_IP_PERIL  0xc950
 #define E4210_GATE_IP_PERIR0xc960
 #define GATE_BLOCK 0xc970
+#define E4X12_MPLL_LOCK0x10008
 #define E4X12_MPLL_CON00x10108
 #define SRC_DMC0x10200
 #define SRC_MASK_DMC   0x10300
 #define DIV_DMC0   0x10500
 #define DIV_DMC1   0x10504
 #define GATE_IP_DMC0x10900
+#define APLL_LOCK  0x14000
 #define APLL_CON0  0x14100
 #define E4210_MPLL_CON00x14108
 #define SRC_CPU0x14200
@@ -1019,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, 
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
-   reg_base + APLL_CON0);
+   reg_base + APLL_LOCK);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
-   reg_base + E4X12_MPLL_CON0);
+   reg_base + E4X12_MPLL_LOCK);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
-   reg_base + EPLL_CON0);
+   reg_base + EPLL_LOCK);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
-   reg_base + VPLL_CON0);
+   reg_base + VPLL_LOCK);
}
 
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..687b580 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
 
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
-   reg_base + 0x100);
+   reg_base);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
-   reg_base + 0x4100);
+   reg_base + 0x4000);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
-   reg_base + 0x20110);
+   reg_base + 0x20010);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
-   reg_base + 0x10150);
+   reg_base + 0x10050);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
-   reg_base + 0x10120);
+   reg_base + 0x10020);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
-   reg_base + 0x10130);
+   reg_base + 0x10030);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
-   reg_base + 0x10140);
+   reg_base + 0x10040);
 
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..a7d8ad9 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -13,9 +13,24 @@
 #include clk.h
 #include clk-pll.h
 
+struct samsung_clk_pll {
+   struct clk_hw   hw;
+   const void __iomem  *base;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+#define pll_readl(pll, offset) \
+   __raw_readl((void __iomem *)(pll-base + (offset)));
+#define pll_writel(pll, val, offset)   \
+   __raw_writel(val, (void __iomem *)(pll-base + (offset)));
+
 /*
  * PLL35xx Clock Type
  */
+#define PLL35XX_LOCK_OFFSET(0x0)
+#define PLL35XX_CON0_OFFSET(0x100)
+#define PLL35XX_CON1_OFFSET(0x104)
 
 #define PLL35XX_MDIV_MASK   (0x3FF)
 #define

[PATCH v3 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx

2013-05-31 Thread Vikas Sajjan 
From: Yadwinder Singh Brar yadi.b...@samsung.com

This patch add set_rate() and round_rate() for PLL35xx

Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
 drivers/clk/samsung/clk-pll.c |  103 -
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 8226528..9591560 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -27,6 +27,36 @@ struct samsung_clk_pll {
 #define pll_writel(pll, val, offset)   \
__raw_writel(val, (void __iomem *)(pll-base + (offset)));
 
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+   struct samsung_clk_pll *pll, unsigned long rate)
+{
+   const struct samsung_pll_rate_table  *rate_table = pll-rate_table;
+   int i;
+
+   for (i = 0; i  pll-rate_count; i++) {
+   if (rate == rate_table[i].rate)
+   return rate_table[i];
+   }
+
+   return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+   unsigned long drate, unsigned long *prate)
+{
+   struct samsung_clk_pll *pll = to_clk_pll(hw);
+   const struct samsung_pll_rate_table *rate_table = pll-rate_table;
+   int i;
+
+   /* Assumming rate_table is in descending order */
+   for (i = 0; i  pll-rate_count; i++) {
+   if (drate = rate_table[i].rate)
+   return rate_table[i].rate;
+   }
+
+   /* return minimum supported value */
+   return rate_table[i - 1].rate;
+}
 /*
  * PLL35xx Clock Type
  */
@@ -34,12 +64,17 @@ struct samsung_clk_pll {
 #define PLL35XX_CON0_OFFSET(0x100)
 #define PLL35XX_CON1_OFFSET(0x104)
 
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR(270)
+
 #define PLL35XX_MDIV_MASK   (0x3FF)
 #define PLL35XX_PDIV_MASK   (0x3F)
 #define PLL35XX_SDIV_MASK   (0x7)
+#define PLL35XX_LOCK_STAT_MASK  (0x1)
 #define PLL35XX_MDIV_SHIFT  (16)
 #define PLL35XX_PDIV_SHIFT  (8)
 #define PLL35XX_SDIV_SHIFT  (0)
+#define PLL35XX_LOCK_STAT_SHIFT(29)
 
 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -59,8 +94,70 @@ static unsigned long samsung_pll35xx_recalc_rate(struct 
clk_hw *hw,
return (unsigned long)fvco;
 }
 
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+   if ((mdiv != ((pll_con  PLL35XX_MDIV_SHIFT)  PLL35XX_MDIV_MASK)) ||
+   (pdiv != ((pll_con  PLL35XX_PDIV_SHIFT)  PLL35XX_PDIV_MASK)))
+   return 1;
+   else
+   return 0;
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+   unsigned long prate)
+{
+   struct samsung_clk_pll *pll = to_clk_pll(hw);
+   const struct samsung_pll_rate_table *rate;
+   u32 tmp;
+
+   /* Get required rate settings from table */
+   rate = samsung_get_pll_settings(pll, drate);
+   if (!rate) {
+   pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+   drate, __clk_get_name(hw-clk));
+   return -EINVAL;
+   }
+
+   tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+   if (!(samsung_pll35xx_mp_change(rate-mdiv, rate-pdiv, tmp))) {
+   /* If only s change, change just s value only*/
+   tmp = ~(PLL35XX_SDIV_MASK  PLL35XX_SDIV_SHIFT);
+   tmp |= rate-sdiv  PLL35XX_SDIV_SHIFT;
+   pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+   } else {
+   /* Set PLL lock time. */
+   pll_writel(pll, rate-pdiv * PLL35XX_LOCK_FACTOR,
+   PLL35XX_LOCK_OFFSET);
+
+   /* Change PLL PMS values */
+   tmp = ~((PLL35XX_MDIV_MASK  PLL35XX_MDIV_SHIFT) |
+   (PLL35XX_PDIV_MASK  PLL35XX_PDIV_SHIFT) |
+   (PLL35XX_SDIV_MASK  PLL35XX_SDIV_SHIFT));
+   tmp |= (rate-mdiv  PLL35XX_MDIV_SHIFT) |
+   (rate-pdiv  PLL35XX_PDIV_SHIFT) |
+   (rate-sdiv  PLL35XX_SDIV_SHIFT);
+   pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+   /* wait_lock_time */
+   do {
+   cpu_relax();
+   tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+   } while (!(tmp  (PLL35XX_LOCK_STAT_MASK
+PLL35XX_LOCK_STAT_SHIFT)));
+   }
+
+   return 0;
+}
+
 static const struct clk_ops samsung_pll35xx_clk_ops = {
.recalc_rate = samsung_pll35xx_recalc_rate,
+   .round_rate = samsung_pll_round_rate,
+   .set_rate = samsung_pll35xx_set_rate,
+};
+
+static const

[PATCH v3 2/6] clk: samsung: Add support to register rate_table for PLL3xxx

2013-05-31 Thread Vikas Sajjan 
From: Yadwinder Singh Brar yadi.b...@samsung.com

This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.

Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
 drivers/clk/samsung/clk-exynos4.c|8 
 drivers/clk/samsung/clk-exynos5250.c |   14 +++---
 drivers/clk/samsung/clk-pll.c|   14 --
 drivers/clk/samsung/clk-pll.h|   35 --
 4 files changed, 56 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c 
b/drivers/clk/samsung/clk-exynos4.c
index cf7d4e7..beff8a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np, 
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
-   reg_base + APLL_LOCK);
+   reg_base + APLL_LOCK, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
-   reg_base + E4X12_MPLL_LOCK);
+   reg_base + E4X12_MPLL_LOCK, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
-   reg_base + EPLL_LOCK);
+   reg_base + EPLL_LOCK, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
-   reg_base + VPLL_LOCK);
+   reg_base + VPLL_LOCK, NULL, 0);
}
 
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
 
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
-   reg_base);
+   reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
-   reg_base + 0x4000);
+   reg_base + 0x4000, NULL, 0);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
-   reg_base + 0x20010);
+   reg_base + 0x20010, NULL, 0);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
-   reg_base + 0x10050);
+   reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
-   reg_base + 0x10020);
+   reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
-   reg_base + 0x10030);
+   reg_base + 0x10030, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
-   reg_base + 0x10040);
+   reg_base + 0x10040, NULL, 0);
 
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index a7d8ad9..8226528 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -16,6 +16,8 @@
 struct samsung_clk_pll {
struct clk_hw   hw;
const void __iomem  *base;
+   const struct samsung_pll_rate_table *rate_table;
+   unsigned int rate_count;
 };
 
 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
-   const char *pname, const void __iomem *base)
+   const char *pname, const void __iomem *base,
+   const struct samsung_pll_rate_table *rate_table,
+   const unsigned int rate_count)
 {
struct samsung_clk_pll *pll;
struct clk *clk;
@@ -82,6 +86,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char 
*name,
 
pll-hw.init = init;
pll-base = base;
+   pll-rate_table = rate_table;
+   pll-rate_count = rate_count;
 
clk = clk_register(NULL, pll-hw);
if (IS_ERR(clk)) {
@@ -137,7 +143,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
-   const char *pname, const void __iomem *base)
+   const char *pname, const void __iomem *base,
+

[PATCH v3 6/6] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

2013-05-31 Thread Vikas Sajjan 
Adds the EPLL and VPLL freq table for exynos5250 SoC.

Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
 drivers/clk/samsung/clk-exynos5250.c |   48 +++---
 drivers/clk/samsung/clk.h|2 ++
 2 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index b0e6680..0566421 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -473,11 +473,32 @@ static __initdata struct of_device_id ext_clk_match[] = {
{ },
 };
 
+static const struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
+   /* sorted in descending order */
+   /* PLL_36XX_RATE(rate, m, p, s, k) */
+   PLL_36XX_RATE(26600, 266, 3, 3, 0),
+   PLL_36XX_RATE(7050, 94, 2, 4, 0),
+};
+
+static const struct samsung_pll_rate_table epll_24mhz_tbl[] = {
+   /* sorted in descending order */
+   /* PLL_36XX_RATE(rate, m, p, s, k) */
+   PLL_36XX_RATE(19200, 48, 3, 1, 0),
+   PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+   PLL_36XX_RATE(18000, 45, 3, 1, 0),
+   PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+   PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+   PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+   PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+   PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
 /* register exynox5250 clocks */
 void __init exynos5250_clk_init(struct device_node *np)
 {
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+   unsigned long fin_pll_rate, mout_vpllsrc_rate;
 
if (np) {
reg_base = of_iomap(np, 0);
@@ -497,6 +518,9 @@ void __init exynos5250_clk_init(struct device_node *np)
samsung_clk_register_mux(exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
 
+   fin_pll_rate = _get_rate(fin_pll);
+   mout_vpllsrc_rate = _get_rate(mout_vpllsrc);
+
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
@@ -507,10 +531,28 @@ void __init exynos5250_clk_init(struct device_node *np)
reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
reg_base + 0x10020, NULL, 0);
-   epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
-   reg_base + 0x10030, NULL, 0);
-   vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
+
+   if (fin_pll_rate == (24 * MHZ)) {
+   epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
+   reg_base + 0x10030, epll_24mhz_tbl,
+   ARRAY_SIZE(epll_24mhz_tbl));
+   } else {
+   pr_warn(Exynos5250: valid epll rate_table missing for\n
+   parent fin_pll:%lu hz\n, fin_pll_rate);
+   epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
+   reg_base + 0x10030, NULL, 0);
+   }
+
+   if (mout_vpllsrc_rate == (24 * MHZ)) {
+   vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc
+   , reg_base + 0x10040, vpll_24mhz_tbl,
+   ARRAY_SIZE(vpll_24mhz_tbl));
+   } else {
+   pr_warn(Exynos5250: valid vpll rate_table missing for\n
+   parent mout_vpllsrc_rate:%lu hz\n, mout_vpllsrc_rate);
+   samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
reg_base + 0x10040, NULL, 0);
+   }
 
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index e4ad6ea..c997649 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -20,6 +20,8 @@
 #include linux/of.h
 #include linux/of_address.h
 
+#define MHZ (1000*1000)
+
 /**
  * struct samsung_clock_alias: information about mux clock
  * @id: platform specific id of the clock.
-- 
1.7.9.5

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[PATCH v3 5/6] clk: samsung: Add alias for mout_vpllsrc and reorder MUX registration for it

2013-05-31 Thread Vikas Sajjan 
While trying to get rate of mout_vpllsrc MUX (parent) for registering the
fout_vpll (child), we found get rate was failing.

So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.
Its also adds the alias for the mout_vpllsrc MUX.

Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
 drivers/clk/samsung/clk-exynos5250.c |9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index ddf10ca..b0e6680 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -207,6 +207,11 @@ struct samsung_fixed_factor_clock 
exynos5250_fixed_factor_clks[] __initdata = {
FFACTOR(none, fout_bplldiv2, fout_bpll, 1, 2, 0),
 };
 
+struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
+   MUX_A(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP2, 0, 1,
+   mout_vpllsrc),
+};
+
 struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, mout_apll, mout_apll_p, SRC_CPU, 0, 1),
MUX(none, mout_cpu, mout_cpu_p, SRC_CPU, 16, 1),
@@ -214,7 +219,6 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = 
{
MUX(none, sclk_mpll, mout_mpll_p, SRC_CORE1, 8, 1),
MUX(none, mout_bpll_fout, mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
MUX(none, sclk_bpll, mout_bpll_p, SRC_CDREX, 0, 1),
-   MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP2, 0, 1),
MUX(none, sclk_vpll, mout_vpll_p, SRC_TOP2, 16, 1),
MUX(none, sclk_epll, mout_epll_p, SRC_TOP2, 12, 1),
MUX(none, sclk_cpll, mout_cpll_p, SRC_TOP2, 8, 1),
@@ -490,6 +494,9 @@ void __init exynos5250_clk_init(struct device_node *np)
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
ext_clk_match);
 
+   samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+   ARRAY_SIZE(exynos5250_pll_pmux_clks));
+
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
-- 
1.7.9.5

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2013-05-31 Thread yyyyyy...@libero.it 
Hello dear!!

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[PATCH RFC] exynos4-is: Add support for Exynos5250 MIPI-CSIS

2013-05-31 Thread Sylwester Nawrocki 
Add compatible property for the Exynos5250 and enable the frame start
and frame end interrupts. These interrupts are needed for the Exynos5
FIMC-IS firmware. The driver enables those interrupts only where they
are available, depending on the 'compatible' property. This can be
optimized further, by exposing some API at the subdev driver, so the
host driver can enable extra interrupts only for the image processing
chains involving FIMC-IS.

Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Shaik/ Arun,

Can you please review/test this patch on an Exynos5 SoC ?
I have only tested it on Exynos4412. It is based on patch
https://linuxtv.org/patch/17125/

Thanks,
Sylwester

 .../bindings/media/samsung-mipi-csis.txt   |4 +-
 drivers/media/platform/exynos4-is/mipi-csis.c  |   67 
 2 files changed, 58 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt 
b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
index 5f8e28e..be45f0b 100644
--- a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
+++ b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
@@ -5,8 +5,8 @@ Required properties:

 - compatible : samsung,s5pv210-csis for S5PV210 (S5PC110),
samsung,exynos4210-csis for Exynos4210 (S5PC210),
-   samsung,exynos4212-csis for Exynos4212/Exynos4412
-   SoC series;
+   samsung,exynos4212-csis for Exynos4212/Exynos4412,
+   samsung,exynos5250-csis for Exynos5250;
 - reg: offset and length of the register set for the device;
 - interrupts  : should contain MIPI CSIS interrupt; the format of the
interrupt specifier depends on the interrupt controller;
diff --git a/drivers/media/platform/exynos4-is/mipi-csis.c 
b/drivers/media/platform/exynos4-is/mipi-csis.c
index ae99803..69a3d26 100644
--- a/drivers/media/platform/exynos4-is/mipi-csis.c
+++ b/drivers/media/platform/exynos4-is/mipi-csis.c
@@ -1,8 +1,8 @@
 /*
- * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
+ * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
  *
- * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
- * Sylwester Nawrocki s.nawro...@samsung.com
+ * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
+ * Author: Sylwester Nawrocki s.nawro...@samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -66,11 +66,12 @@ MODULE_PARM_DESC(debug, Debug level (0-2));

 /* Interrupt mask */
 #define S5PCSIS_INTMSK 0x10
-#define S5PCSIS_INTMSK_EN_ALL  0xf000103f
 #define S5PCSIS_INTMSK_EVEN_BEFORE (1  31)
 #define S5PCSIS_INTMSK_EVEN_AFTER  (1  30)
 #define S5PCSIS_INTMSK_ODD_BEFORE  (1  29)
 #define S5PCSIS_INTMSK_ODD_AFTER   (1  28)
+#define S5PCSIS_INTMSK_FRAME_END   (1  27)
+#define S5PCSIS_INTMSK_FRAME_START (1  26)
 #define S5PCSIS_INTMSK_ERR_SOT_HS  (1  12)
 #define S5PCSIS_INTMSK_ERR_LOST_FS (1  5)
 #define S5PCSIS_INTMSK_ERR_LOST_FE (1  4)
@@ -78,6 +79,8 @@ MODULE_PARM_DESC(debug, Debug level (0-2));
 #define S5PCSIS_INTMSK_ERR_ECC (1  2)
 #define S5PCSIS_INTMSK_ERR_CRC (1  1)
 #define S5PCSIS_INTMSK_ERR_UNKNOWN (1  0)
+#define S5PCSIS_INTMSK_EXYNOS4_EN_ALL  0xf000103f
+#define S5PCSIS_INTMSK_EXYNOS5_EN_ALL  0xfc00103f

 /* Interrupt source */
 #define S5PCSIS_INTSRC 0x14
@@ -88,6 +91,8 @@ MODULE_PARM_DESC(debug, Debug level (0-2));
 #define S5PCSIS_INTSRC_ODD_AFTER   (1  28)
 #define S5PCSIS_INTSRC_ODD (0x3  28)
 #define S5PCSIS_INTSRC_NON_IMAGE_DATA  (0xff  28)
+#define S5PCSIS_INTSRC_FRAME_END   (1  27)
+#define S5PCSIS_INTSRC_FRAME_START (1  26)
 #define S5PCSIS_INTSRC_ERR_SOT_HS  (0xf  12)
 #define S5PCSIS_INTSRC_ERR_LOST_FS (1  5)
 #define S5PCSIS_INTSRC_ERR_LOST_FE (1  4)
@@ -155,6 +160,9 @@ static const struct s5pcsis_event s5pcsis_events[] = {
{ S5PCSIS_INTSRC_EVEN_AFTER,Non-image data after even frame },
{ S5PCSIS_INTSRC_ODD_BEFORE,Non-image data before odd frame },
{ S5PCSIS_INTSRC_ODD_AFTER, Non-image data after odd frame },
+   /* Frame start/end */
+   { S5PCSIS_INTSRC_FRAME_START,   Frame Start },
+   { S5PCSIS_INTSRC_FRAME_END, Frame End },
 };
 #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)

@@ -163,6 +171,11 @@ struct csis_pktbuf {
unsigned int len;
 };

+struct csis_drvdata {
+   /* Mask of all used interrupts in S5PCSIS_INTMSK register */
+   u32 interrupt_mask;
+};
+
 /**
  * struct csis_state - the driver's internal state data structure
  * @lock: mutex serializing the subdev and power management operations,
@@ -175,6 +188,7 @@ struct

Re: [PATCH V4 03/30] thermal: exynos: Remove CPU_THERMAL dependency for using TMU driver

2013-05-31 Thread Eduardo Valentin 
On 14-05-2013 05:58, Amit Daniel Kachhap wrote:
 This patch removes the dependency on CPU_THERMAL for compiling TMU driver.
 This is useful for cases when only TMU controller needs to be initialised
 without cpu cooling action.


Agreed with your intention. I just do not know if it makes sense to make
this change at this point. Maybe after you have split the code?

The above concern is simply from a non-functional perspective. If you do
this at this point of your series, your driver may have compilation
issues at this specific commit, in case your config does not have
CONFIG_CPU_THERMAL.

I recommend you moving this patch further in your series, to a place
where you have isolated the code that depends on CPU_THERMAL.

 
 Acked-by: Kukjin Kim kgene@samsung.com
 Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
 ---
  drivers/thermal/samsung/Kconfig |1 -
  1 files changed, 0 insertions(+), 1 deletions(-)
 
 diff --git a/drivers/thermal/samsung/Kconfig b/drivers/thermal/samsung/Kconfig
 index 145a55d..b5ab971 100644
 --- a/drivers/thermal/samsung/Kconfig
 +++ b/drivers/thermal/samsung/Kconfig
 @@ -4,7 +4,6 @@ config ARCH_HAS_TMU
  config EXYNOS_THERMAL
   tristate Temperature sensor on Samsung EXYNOS
   depends on ARCH_HAS_TMU
 - depends on CPU_THERMAL
   help
 If you say yes here you get support for TMU (Thermal Management
 Unit) on SAMSUNG EXYNOS series of SoC. This helps in registering
 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin



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Description: OpenPGP digital signature

Re: [PATCH] ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor

2013-05-31 Thread Doug Anderson 
Leela,

On Fri, May 31, 2013 at 2:43 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
 This patch reads the cpuid part number and if it matches with
 cortex-A9, calls scu_enable()

 Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
 ---
  arch/arm/mach-exynos/platsmp.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
 index a0e8ff7..d9c6d0a 100644
 --- a/arch/arm/mach-exynos/platsmp.c
 +++ b/arch/arm/mach-exynos/platsmp.c
 @@ -200,7 +200,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int 
 max_cpus)
  {
 int i;

 -   if (!(soc_is_exynos5250() || soc_is_exynos5440()))
 +   if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 scu_enable(scu_base_addr());

 /*

Thanks for sending upstream.  For reference, our local version is here
https://gerrit.chromium.org/gerrit/#/c/56804/.

This is much better than listing every single non-A9 exynos in a big
if test.  ;)

Reviewed-by: Doug Anderson diand...@chromium.org
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[PATCH RFC v2] exynos4-is: Add support for Exynos5250 MIPI-CSIS

2013-05-31 Thread Sylwester Nawrocki 
Add compatible property for the Exynos5250 and enable the frame start
and frame end interrupts. These interrupts are needed for the Exynos5
FIMC-IS firmware. The driver enables those interrupt only where available,
depending on the 'compatible' property. This can be optimized further,
by exposing some API at the subdev driver, so the host driver can enable
extra interrupts only for the image processing chains involving FIMC-IS.

Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---

I've forgotten to squash a chunk swapping bits in the definitions of
the FRAME_START/FRAME_END bits in S5PCSIS_INTMSK and S5PCSIS_INTSRC
registers. Sorry about that.

Thanks,
Sylwester
---
 .../bindings/media/samsung-mipi-csis.txt   |4 +-
 drivers/media/platform/exynos4-is/mipi-csis.c  |   67 
 2 files changed, 58 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt 
b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
index 5f8e28e..be45f0b 100644
--- a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
+++ b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
@@ -5,8 +5,8 @@ Required properties:

 - compatible : samsung,s5pv210-csis for S5PV210 (S5PC110),
samsung,exynos4210-csis for Exynos4210 (S5PC210),
-   samsung,exynos4212-csis for Exynos4212/Exynos4412
-   SoC series;
+   samsung,exynos4212-csis for Exynos4212/Exynos4412,
+   samsung,exynos5250-csis for Exynos5250;
 - reg: offset and length of the register set for the device;
 - interrupts  : should contain MIPI CSIS interrupt; the format of the
interrupt specifier depends on the interrupt controller;
diff --git a/drivers/media/platform/exynos4-is/mipi-csis.c 
b/drivers/media/platform/exynos4-is/mipi-csis.c
index ae99803..0fe80e3 100644
--- a/drivers/media/platform/exynos4-is/mipi-csis.c
+++ b/drivers/media/platform/exynos4-is/mipi-csis.c
@@ -1,8 +1,8 @@
 /*
- * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
+ * Samsung S5P/EXYNOS SoC series MIPI-CSI receiver driver
  *
- * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
- * Sylwester Nawrocki s.nawro...@samsung.com
+ * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
+ * Author: Sylwester Nawrocki s.nawro...@samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -66,11 +66,12 @@ MODULE_PARM_DESC(debug, Debug level (0-2));

 /* Interrupt mask */
 #define S5PCSIS_INTMSK 0x10
-#define S5PCSIS_INTMSK_EN_ALL  0xf000103f
 #define S5PCSIS_INTMSK_EVEN_BEFORE (1  31)
 #define S5PCSIS_INTMSK_EVEN_AFTER  (1  30)
 #define S5PCSIS_INTMSK_ODD_BEFORE  (1  29)
 #define S5PCSIS_INTMSK_ODD_AFTER   (1  28)
+#define S5PCSIS_INTMSK_FRAME_START (1  27)
+#define S5PCSIS_INTMSK_FRAME_END   (1  26)
 #define S5PCSIS_INTMSK_ERR_SOT_HS  (1  12)
 #define S5PCSIS_INTMSK_ERR_LOST_FS (1  5)
 #define S5PCSIS_INTMSK_ERR_LOST_FE (1  4)
@@ -78,6 +79,8 @@ MODULE_PARM_DESC(debug, Debug level (0-2));
 #define S5PCSIS_INTMSK_ERR_ECC (1  2)
 #define S5PCSIS_INTMSK_ERR_CRC (1  1)
 #define S5PCSIS_INTMSK_ERR_UNKNOWN (1  0)
+#define S5PCSIS_INTMSK_EXYNOS4_EN_ALL  0xf000103f
+#define S5PCSIS_INTMSK_EXYNOS5_EN_ALL  0xfc00103f

 /* Interrupt source */
 #define S5PCSIS_INTSRC 0x14
@@ -88,6 +91,8 @@ MODULE_PARM_DESC(debug, Debug level (0-2));
 #define S5PCSIS_INTSRC_ODD_AFTER   (1  28)
 #define S5PCSIS_INTSRC_ODD (0x3  28)
 #define S5PCSIS_INTSRC_NON_IMAGE_DATA  (0xff  28)
+#define S5PCSIS_INTSRC_FRAME_START (1  27)
+#define S5PCSIS_INTSRC_FRAME_END   (1  26)
 #define S5PCSIS_INTSRC_ERR_SOT_HS  (0xf  12)
 #define S5PCSIS_INTSRC_ERR_LOST_FS (1  5)
 #define S5PCSIS_INTSRC_ERR_LOST_FE (1  4)
@@ -155,6 +160,9 @@ static const struct s5pcsis_event s5pcsis_events[] = {
{ S5PCSIS_INTSRC_EVEN_AFTER,Non-image data after even frame },
{ S5PCSIS_INTSRC_ODD_BEFORE,Non-image data before odd frame },
{ S5PCSIS_INTSRC_ODD_AFTER, Non-image data after odd frame },
+   /* Frame start/end */
+   { S5PCSIS_INTSRC_FRAME_START,   Frame Start },
+   { S5PCSIS_INTSRC_FRAME_END, Frame End },
 };
 #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)

@@ -163,6 +171,11 @@ struct csis_pktbuf {
unsigned int len;
 };

+struct csis_drvdata {
+   /* Mask of all used interrupts in S5PCSIS_INTMSK register */
+   u32 interrupt_mask;
+};
+
 /**
  * struct csis_state - the driver's internal state data structure
  * @lock: mutex serializing the subdev and power management operations,
@@ -175,6 +188,7 @@ struct csis_pktbuf

Re: [PATCH V4 22/30] thermal: exynos: Add support for exynos5440 TMU sensor.

2013-05-31 Thread Eduardo Valentin 
Amit and Jonghwa,

On 18-05-2013 01:23, jonghwa3@samsung.com wrote:
 On 2013년 05월 14일 18:58, Amit Daniel Kachhap wrote:
 
 This patch modifies TMU controller to add changes needed to work with
 exynos5440 platform. This sensor registers 3 instance of the tmu controller
 with the thermal zone and hence reports 3 temperature output. This controller
 supports upto five trip points. For critical threshold the driver uses the
 core driver thermal framework for shutdown.

 Acked-by: Kukjin Kim kgene@samsung.com
 Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
 ---
  .../devicetree/bindings/thermal/exynos-thermal.txt |   28 -
  drivers/thermal/samsung/exynos_tmu.c   |   43 
 +--
  drivers/thermal/samsung/exynos_tmu.h   |6 +++
  drivers/thermal/samsung/exynos_tmu_data.h  |2 +
  4 files changed, 72 insertions(+), 7 deletions(-)

 diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt 
 b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
 index 535fd0e..970eeba 100644

cut

 +goto out;
 
 
 I have a question about your implementation for supporting EXYNOS5440.
 I don't know exactly how EXYNO5440's tmu is working, but just guess it would 
 be
 similar with other EXYNOS series's without number of thermal sensors. 
 (exclusive
 register map and threshold level). Due to the multiple number of thermal 
 sensor
 in EXYNOS5440, it have multiple thermal zone devices and that's why it just
 leave interrupt pin in pending if interrupt is not its, right?
 
 So, my curious is, why we make all platform devices for each of thermal zone
 devices? Why don't you just handle all thermal zone devices with one platform
 device?
 
 Yes, It's probably right to make multiple devices node to support them, 
 because
 it has different physical hardware(sensors). But we have one TMU , don't we?
 (Maybe my assumption is wrong, I assume that it has one TMU because it looks
 like it has only one irq line.). If I'm right, I think it is better to manage
 all thermal zone devices with one platform device. Then, we don't need to 
 leave
 irq handler with leaving it pendded like above and also we may not need other
 your patches like adding base_common iomem variable.
 
 I'd like to listen your opinion about this.
 


I understand the concern risen by Jonghwa. In fact, this is a bit
confusing. The way I have decided to design the driver for TI
(drivers/thermal/ti-soc-thermal under thermal tree next branch) is to
have one platform device for the bandgap IP (that would be probably
equivalent of  your TMU).

Reasoning is to have a exact match between platform device and real HW
device interface. Thus its device resources are belonging to one single
device node. In TIs case, the resources, regarding IRQs, IO map area,
registers, etc, are belonging to the bandgap IP not to sensors. That
alone convinced me to use one single device node, instead of several,
per sensor. In fact, for OMAP devices it is a bit more complicated as
the bandgap is actually behind the control module, which holds the
interface. But that is another story.

So, in this case I decided to have 1 single platform device representing
the bandgap IP, which exposes and handles several thermal zones (one per
sensor). And of course, owns and manages all related resources (IRQ,
gpio and IO mem area).

To what I have understood of your case, I believe it is the very same
case, so I would recommend reusing the proposed design.

Keep in mind that this obviously does not stop you of having different
policies or trip setups per sensor. The framework is flexible in this sense.

I hope this helps.

 Thanks,
 Jonghwa
 
 +}
  
  exynos_report_trigger(data-reg_conf);
  mutex_lock(data-lock);
 @@ -358,7 +390,7 @@ static void exynos_tmu_work(struct work_struct *work)
  
  clk_disable(data-clk);
  mutex_unlock(data-lock);
 -
 +out:
  enable_irq(data-irq);
  }
  
 @@ -520,7 +552,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
  return ret;
  
  if (pdata-type == SOC_ARCH_EXYNOS ||
 -pdata-type == SOC_ARCH_EXYNOS4210)
 +pdata-type == SOC_ARCH_EXYNOS4210 ||
 +pdata-type == SOC_ARCH_EXYNOS5440)
  data-soc = pdata-type;
  else {
  ret = -EINVAL;
 diff --git a/drivers/thermal/samsung/exynos_tmu.h 
 b/drivers/thermal/samsung/exynos_tmu.h
 index 65443d7..9151a30 100644
 --- a/drivers/thermal/samsung/exynos_tmu.h
 +++ b/drivers/thermal/samsung/exynos_tmu.h
 @@ -44,6 +44,7 @@ enum trigger_type {
  enum soc_type {
  SOC_ARCH_EXYNOS4210 = 1,
  SOC_ARCH_EXYNOS,
 +SOC_ARCH_EXYNOS5440,
  };
  
  /**
 @@ -132,6 +133,8 @@ enum soc_type {
   * @emul_temp_shift: shift bits of emulation temperature.
   * @emul_time_shift: shift bits of emulation time.
   * @emul_time_mask: mask bits of emulation time.
 + * @tmu_irqstatus: register

Re: [PATCH v3 2/6] clk: samsung: Add support to register rate_table for PLL3xxx

2013-05-31 Thread Doug Anderson 
Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan vikas.saj...@linaro.org wrote:
 From: Yadwinder Singh Brar yadi.b...@samsung.com

 This patch defines a common rate_table which will contain recommended p, m, s,
 k values for supported rates that needs to be changed for changing
 corresponding PLL's rate.

 Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
 ---
  drivers/clk/samsung/clk-exynos4.c|8 
  drivers/clk/samsung/clk-exynos5250.c |   14 +++---
  drivers/clk/samsung/clk-pll.c|   14 --
  drivers/clk/samsung/clk-pll.h|   35 
 --
  4 files changed, 56 insertions(+), 15 deletions(-)

This looks good to me.  Hopefully Tomasz agrees.  Tomasz: if you
haven't been following this thread, see
https://patchwork.kernel.org/patch/2643351/ for how we resolved the
constant vs. calculated input clock.

Reviewed-by: Doug Anderson diand...@chromium.org
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Re: [PATCH v3 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx

2013-05-31 Thread Doug Anderson 
Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan vikas.saj...@linaro.org wrote:
 +static long samsung_pll_round_rate(struct clk_hw *hw,
 +   unsigned long drate, unsigned long *prate)
 +{
 +   struct samsung_clk_pll *pll = to_clk_pll(hw);
 +   const struct samsung_pll_rate_table *rate_table = pll-rate_table;
 +   int i;
 +
 +   /* Assumming rate_table is in descending order */
 +   for (i = 0; i  pll-rate_count; i++) {
 +   if (drate = rate_table[i].rate)
 +   return rate_table[i].rate;
 +   }
 +
 +   /* return minimum supported value */
 +   return rate_table[i - 1].rate;
 +}
  /*
   * PLL35xx Clock Type
   */

You seem to have lost a carriage return between v2 and v3.  I will add
it locally before applying.  This still looks good though and already
has my Reviewed-by.

-Doug
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Re: [PATCH v3 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx

2013-05-31 Thread Doug Anderson 
Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan vikas.saj...@linaro.org wrote:
  struct clk * __init samsung_clk_register_pll36xx(const char *name,
 @@ -264,6 +318,11 @@ struct clk * __init samsung_clk_register_pll36xx(const 
 char *name,
 init.parent_names = pname;
 init.num_parents = 1;

 +   if (rate_table  rate_count)
 +   init.ops = samsung_pll36xx_clk_ops;
 +   else
 +   init.ops = samsung_pll36xx_clk_min_ops;
 +
 pll-hw.init = init;
 pll-base = base;
 pll-rate_table = rate_table;

Interesting.  In the gerrit review you sent for v2 you properly
removed the line:

  init.ops = samsung_pll36xx_clk_ops;

...but the v2 you posted upstream didn't have that removal.  You've
also lost it in v3.  Perhaps you can add that back in?  I'll do it
locally before applying.


-Doug
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Re: [PATCH v3 5/6] clk: samsung: Add alias for mout_vpllsrc and reorder MUX registration for it

2013-05-31 Thread Doug Anderson 
Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan vikas.saj...@linaro.org wrote:
 While trying to get rate of mout_vpllsrc MUX (parent) for registering the
 fout_vpll (child), we found get rate was failing.

 So this patch moves the mout_vpllsrc MUX out of the existing common list
 and registers the mout_vpllsrc MUX before the PLL registrations.
 Its also adds the alias for the mout_vpllsrc MUX.

I think the moving makes sense, but not the alias.  IMHO global
aliases should be avoided unless they can be strongly justified.

In part 6 of this series I see where you're using the alias but I
don't think you need it.  In your case you are a clock provider, so I
think you can use __clk_lookup(mout_vpllsrc) to find your clock.

I will post an update on our gerrit and you can see what you think.
If someone on the list thinks that using __clk_lookup() is a bad idea
and they'd rather see the global alias, please shout.


-Doug
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Re: [PATCH v3 6/6] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

2013-05-31 Thread Doug Anderson 
Vikas and Yadwinder,

On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan vikas.saj...@linaro.org wrote:
 Adds the EPLL and VPLL freq table for exynos5250 SoC.

 Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
 ---
  drivers/clk/samsung/clk-exynos5250.c |   48 
 +++---
  drivers/clk/samsung/clk.h|2 ++
  2 files changed, 47 insertions(+), 3 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos5250.c 
 b/drivers/clk/samsung/clk-exynos5250.c
 index b0e6680..0566421 100644
 --- a/drivers/clk/samsung/clk-exynos5250.c
 +++ b/drivers/clk/samsung/clk-exynos5250.c
 @@ -473,11 +473,32 @@ static __initdata struct of_device_id ext_clk_match[] = 
 {
 { },
  };

 +static const struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
 +   /* sorted in descending order */
 +   /* PLL_36XX_RATE(rate, m, p, s, k) */
 +   PLL_36XX_RATE(26600, 266, 3, 3, 0),
 +   PLL_36XX_RATE(7050, 94, 2, 4, 0),

Would be nice to include the comment that you included in our gerrit:
that the 70.5 is not in the manual but is used by exynos5250-snow.


 +   fin_pll_rate = _get_rate(fin_pll);
 +   mout_vpllsrc_rate = _get_rate(mout_vpllsrc);

This line is why you added an alias for mout_vpllsrc.  I'd rather not
see that since it also exports the clock to other places.

I've changed this to use __clk_lookup().  That function _is_ exported
by linux/clk-provider.h and we are a clock provider, so it seems
legit to use that.  ...and it's nice not to have an extra clock alias.

See my changes to https://gerrit.chromium.org/gerrit/#/c/56797/ for
an example.


 @@ -507,10 +531,28 @@ void __init exynos5250_clk_init(struct device_node *np)
 reg_base + 0x10050, NULL, 0);
 cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
 reg_base + 0x10020, NULL, 0);
 -   epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
 -   reg_base + 0x10030, NULL, 0);
 -   vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
 +
 +   if (fin_pll_rate == (24 * MHZ)) {
 +   epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
 +   reg_base + 0x10030, epll_24mhz_tbl,
 +   ARRAY_SIZE(epll_24mhz_tbl));
 +   } else {
 +   pr_warn(Exynos5250: valid epll rate_table missing for\n
 +   parent fin_pll:%lu hz\n, fin_pll_rate);

nit: use %s and __func__ rather than adding Exynos5250 hardcoded in here?


-Doug
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Re: [PATCH] ARM: EXYNOS: Consolidate multiple low-level UART port definitions

2013-05-31 Thread Kevin Hilman 
Tushar Behera tushar.beh...@linaro.org writes:

 There are two definitions for low-level UART ports for Exynos platform.
 CONFIG_S3C_LOWLEVEL_UART_PORT is used for printing Uncompressing
 Linux... done, booting the kernel. and CONFIG_S3C_UART for other
 low-level messages.

 The assumption for both the uart ports is that they are pre-configured
 in the bootloader. Since they are essentially the same always, it
 would be good to consolidate them to use only one macro, in this case
 'DEBUG_S3C_UART' would be a better option.

 'DEBUG_S3C_UART' is defined only if DEBUG_LL is enabled. We can safely
 disable this option when DEBUG_LL is not defined and we can boot various
 boards with different UART port settings. Only drawback of this
 approach is that when DEBUG_LL is not defined, we would be missing the
 print Uncompressing Linux... done, booting the kernel.

Perfectly acceptable to me (and already the case on OMAP.)

 Since CONFIG_S3C_LOWLEVEL_UART_PORT is still used by other Samsung
 boards, the consolidation applies only for ARCH_EXYNOS.

 Signed-off-by: Tushar Behera tushar.beh...@linaro.org

Acked-by: Kevin Hilman khil...@linaro.org

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[PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

2013-05-31 Thread Doug Anderson 
The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations.  Fix our rate
recalculation to do this correctly.

Before doing this, I tried setting EPLL on exynos5250 to:
  rate, m, p, s, k = 8000, 107, 2, 4, 43691

This rate is exactly from the table in the exynos5250 user manual.

I read this back as 80750003 with:
  cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate

After this patch, it reads back as 8003

  mw 0x10020130 a06b0204
  mw 0x10020134 aaab

Signed-off-by: Doug Anderson diand...@chromium.org
---
This patch is based upon another in-flight patch to avoid conflicts:
  clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
  https://patchwork.kernel.org/patch/2629751/

 drivers/clk/samsung/clk-pll.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 01f17cf..26416bb 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -115,7 +115,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct 
clk_hw *hw,
unsigned long parent_rate)
 {
struct samsung_clk_pll *pll = to_clk_pll(hw);
-   u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+   u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+   s16 kdiv;
u64 fvco = parent_rate;
 
pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
@@ -123,7 +124,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct 
clk_hw *hw,
mdiv = (pll_con0  PLL36XX_MDIV_SHIFT)  PLL36XX_MDIV_MASK;
pdiv = (pll_con0  PLL36XX_PDIV_SHIFT)  PLL36XX_PDIV_MASK;
sdiv = (pll_con0  PLL36XX_SDIV_SHIFT)  PLL36XX_SDIV_MASK;
-   kdiv = pll_con1  PLL36XX_KDIV_MASK;
+   kdiv = (s16)(pll_con1  PLL36XX_KDIV_MASK);
 
fvco *= (mdiv  16) + kdiv;
do_div(fvco, (pdiv  sdiv));
-- 
1.8.2.1

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Re: [PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

2013-05-31 Thread Vikas Sajjan 
Hi Doug,

Looks good to me.

On 1 June 2013 00:28, Doug Anderson diand...@chromium.org wrote:
 The KDIV value is often listed as unsigned but it needs to be treated
 as a 16-bit signed value when using it in calculations.  Fix our rate
 recalculation to do this correctly.

 Before doing this, I tried setting EPLL on exynos5250 to:
   rate, m, p, s, k = 8000, 107, 2, 4, 43691

 This rate is exactly from the table in the exynos5250 user manual.

 I read this back as 80750003 with:
   cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate

 After this patch, it reads back as 8003

   mw 0x10020130 a06b0204
   mw 0x10020134 aaab

 Signed-off-by: Doug Anderson diand...@chromium.org


Reviewed-by: Vikas Sajjan vikas.saj...@linaro.org


 ---
 This patch is based upon another in-flight patch to avoid conflicts:
   clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
   https://patchwork.kernel.org/patch/2629751/

  drivers/clk/samsung/clk-pll.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

 diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
 index 01f17cf..26416bb 100644
 --- a/drivers/clk/samsung/clk-pll.c
 +++ b/drivers/clk/samsung/clk-pll.c
 @@ -115,7 +115,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct 
 clk_hw *hw,
 unsigned long parent_rate)
  {
 struct samsung_clk_pll *pll = to_clk_pll(hw);
 -   u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
 +   u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
 +   s16 kdiv;
 u64 fvco = parent_rate;

 pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
 @@ -123,7 +124,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct 
 clk_hw *hw,
 mdiv = (pll_con0  PLL36XX_MDIV_SHIFT)  PLL36XX_MDIV_MASK;
 pdiv = (pll_con0  PLL36XX_PDIV_SHIFT)  PLL36XX_PDIV_MASK;
 sdiv = (pll_con0  PLL36XX_SDIV_SHIFT)  PLL36XX_SDIV_MASK;
 -   kdiv = pll_con1  PLL36XX_KDIV_MASK;
 +   kdiv = (s16)(pll_con1  PLL36XX_KDIV_MASK);

 fvco *= (mdiv  16) + kdiv;
 do_div(fvco, (pdiv  sdiv));
 --
 1.8.2.1




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Re: [PATCH 2/3] ARM: SAMSUNG: Consolidate uncompress subroutine

2013-05-31 Thread Olof Johansson 
On Fri, May 31, 2013 at 05:19:03PM +0530, Tushar Behera wrote:
 For mach-exynos, uart_base is a pointer and the value is calculated
 in the machine folder. For other machines, uart_base is defined as
 a macro in platform directory. For symmetry, the uart_base macro
 definition is removed and the uart_base calculation is moved to
 specific machine folders.
 
 This would help us consolidating uncompress subroutine for s5p64x0.

Sorry, reading these in order and didn't go through all of them.

Same comment here, you can use config_enabled() and return early instead of
adding ifdefs.


-Olof
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Re: [PATCH 1/3] ARM: EXYNOS: uncompress - print debug messages if DEBUG_LL is defined

2013-05-31 Thread Olof Johansson 
On Fri, May 31, 2013 at 05:19:02PM +0530, Tushar Behera wrote:
 Printing low-level debug messages make an assumption that the specified
 UART port has been preconfigured by the bootloader. Incorrectly
 specified UART port results in system getting stalled while printing the
 message Uncompressing Linux... done, booting the kernel
 
 This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since
 the UART port might different for different board, it is not possible to
 specify it correctly for every board that use a common defconfig file.
 
 Calling this print subroutine only when DEBUG_LL fixes the problem. By
 disabling DEBUG_LL in default config file, we would be able to boot
 multiple boards with different default UART ports.
 
 With this current approach, we miss the print Uncompressing Linux...
 done, booting the kernel. when DEBUG_LL is not defined.
 
 Signed-off-by: Tushar Behera tushar.beh...@linaro.org
 ---
  arch/arm/mach-exynos/include/mach/uncompress.h  |   11 ---
  arch/arm/plat-samsung/include/plat/uncompress.h |   10 +-
  2 files changed, 17 insertions(+), 4 deletions(-)
 
 diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h 
 b/arch/arm/mach-exynos/include/mach/uncompress.h
 index 2979995..730f69f 100644
 --- a/arch/arm/mach-exynos/include/mach/uncompress.h
 +++ b/arch/arm/mach-exynos/include/mach/uncompress.h
 @@ -37,11 +37,16 @@ static void arch_detect_cpu(void)
   chip_id = 20;
   chip_id = 0xf;
  
 +#ifdef CONFIG_DEBUG_LL
   if (chip_id == 0x5)
 - uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * 
 CONFIG_S3C_LOWLEVEL_UART_PORT);
 + uart_base = (volatile u8 *)EXYNOS5_PA_UART +
 + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
   else
 - uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * 
 CONFIG_S3C_LOWLEVEL_UART_PORT);
 -
 + uart_base = (volatile u8 *)EXYNOS4_PA_UART +
 + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 +#else
 + uart_base = NULL;
 +#endif

You can do:

if (!config_enabled(CONFIG_DEBUG_LL))
return;

Since uart_base will be set to 0 by being in BSS anyway.


-Olof
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