[PATCH V2 RE-SEND 7/7] MAINTAINERS: add maintainer for Samsung sxgbe driver
Signed-off-by: Byungho An --- MAINTAINERS |9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b2cf5cf..344702c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7497,6 +7497,15 @@ S: Supported L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) F: drivers/clk/samsung/ +SAMSUNG SXGBE DRIVERS +M: Byungho An +M: Girish K S +M: Siva Reddy Kallam +M: Vipul Pandya +S: Supported +L: net...@vger.kernel.org +F: drivers/net/ethernet/samsung/ + SERIAL DRIVERS M: Greg Kroah-Hartman L: linux-ser...@vger.kernel.org -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: ref: virt-v7.c switching to non_secure mode
Hi Christoffer / uboot,
We are able to figure out the issue. PERIPHBASE returned on ARNDALE board was
0x1050 and adding GIC offset was creating an incorrect address.
Setting CONFIG_ARM_GIC_BASE_ADDRESS as 0x1048 in arndale.h solves the issue.
The u-boot code needs to be fixed for arndale right ? Please confirm
Regards
Manish
armdev Team @FTM
On 13-Mar-2014, at 11:20 am, armdev wrote:
> Got a mail that Andre is not with linaro, Adding Christoffer Dall
>
> On 13-Mar-2014, at 11:17 am, armdev wrote:
>
>> Hi Andrey ,
>>
>> This is wrt your patch set which enabled the switch to non-sec and hip mode
>> in armv7.
>> We have a small piece of code which we run in hypmode using the bootm
>> command on arndale board
>>
>> While this code was trying to access the GICD_ISENABLR0 (0x10481100), read
>> was always returning 0, while as per the reset value it should be
>> 0x. Debugged more in u-boot and added prints.
>>
>> This is the log, our observation is that in _nonsec_init() there is
>> something that is causing the issue. Now It can be an issue or a gap in our
>> understanding. Ideally we should be able to read the GICD_ISENABLR value as
>> 0x.
>> Can you please help us in find out how to read GIC values properly in hyp
>> mode.
>>
>> armv7_switch_nonsec
>> cpsr =61d3
>> REGS
>> Before write to group regs
>> cpsr =61d3
>> REGS
>> Before _nonsec_init()
>> cpsr =61d3
>> REGS
>> After _nonsec_init()
>> cpsr =61d3
>> REGS 0
>>
>> HYP mode: successful.
>> armv7_switch_hyp
>> cpsr =61da
>> REGS 0
>>
>> Here is the diff of our modifications. (just added prints)
>> diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
>> index 2cd604f..f38f125 100644
>> --- a/arch/arm/cpu/armv7/virt-v7.c
>> +++ b/arch/arm/cpu/armv7/virt-v7.c
>> @@ -107,6 +107,10 @@ int armv7_switch_hyp(void)
>> printf("HYP mode: switch not successful.\n");
>> return -1;
>> }
>> +printf("HYP mode: successful.\n");
>> +printf("%s \r\n",__FUNCTION__);
>> +printf("cpsr =%x\n", read_cpsr());
>> +printf("REGS %x \n", *(uint32_t*)0x10481100);
>>
>> return 0;
>> }
>> @@ -116,6 +120,10 @@ int armv7_switch_nonsec(void)
>> unsigned int reg;
>> unsigned itlinesnr, i;
>>
>> +printf("%s \r\n",__FUNCTION__);
>> +printf("cpsr =%x\n", read_cpsr());
>> +printf("REGS %x \n", *(uint32_t*)0x10481100);
>> +
>> /* check whether the CPU supports the security extensions */
>> reg = read_id_pfr1();
>> if ((reg & 0xF0) == 0) {
>> @@ -140,6 +148,9 @@ int armv7_switch_nonsec(void)
>> /* TYPER[4:0] contains an encoded number of available interrupts */
>> itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
>>
>> +printf("Before write to group regs \r\n");
>> +printf("cpsr =%x\n", read_cpsr());
>> +printf("REGS %x \n", *(uint32_t*)0x10481100);
>> /* set all bits in the GIC group registers to one to allow access
>> * from non-secure state. The first 32 interrupts are private per
>> * CPU and will be set later when enabling the GIC for each core
>> @@ -147,11 +158,19 @@ int armv7_switch_nonsec(void)
>> for (i = 1; i <= itlinesnr; i++)
>> writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
>>
>> -smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
>> -smp_kick_all_cpus();
>> +//smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
>> +//smp_kick_all_cpus();
>>
>> +printf("Before _nonsec_init() \r\n");
>> +printf("cpsr =%x\n", read_cpsr());
>> +printf("REGS %x \n", *(uint32_t*)0x10481100);
>> /* call the non-sec switching code on this CPU also */
>> _nonsec_init();
>>
>> +printf("After _nonsec_init() \r\n");
>> +printf("cpsr =%x\n", read_cpsr());
>> +printf("REGS %x \n", *(uint32_t*)0x10481100);
>> +
>> +
>> return 0;
>> }
>> diff --git a/include/configs/arndale.h b/include/configs/arndale.h
>> index 515facf..53a1212 100644
>> --- a/include/configs/arndale.h
>> +++ b/include/configs/arndale.h
>> @@ -62,7 +62,6 @@
>> /* select serial console configuration */
>> #define CONFIG_BAUDRATE 115200
>> #define EXYNOS5_DEFAULT_UART_OFFSET 0x01
>> -#define CONFIG_SILENT_CONSOLE
>>
>> /* Console configuration */
>> #define CONFIG_CONSOLE_MUX
>> @@ -249,4 +248,7 @@
>> /* Enable Time Command */
>> #define CONFIG_CMD_TIME
>>
>> +/* Enable jump to hypervisor */
>> +#define CONFIG_ARMV7_VIRT
>> +#define CONFIG_SMP_PEN_ADDR 0x0
>> #endif /* __CONFIG_H */
>>
>
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[PATCH V2 RE-SEND 6/7] net: sxgbe: add ethtool related functions support Samsung sxgbe
From: Vipul Pandya
This patch adds ethtool related functions.
Signed-off-by: Vipul Pandya
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h | 28 +-
drivers/net/ethernet/samsung/sxgbe_ethtool.c | 509 +-
drivers/net/ethernet/samsung/sxgbe_main.c| 14 +-
drivers/net/ethernet/samsung/sxgbe_reg.h |6 +
4 files changed, 538 insertions(+), 19 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index b029181..1f65194 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -42,8 +42,12 @@ struct sxgbe_mtl_ops;
#define SXGBE_RX_QUEUES 16
/* Max/Min RI Watchdog Timer count value */
-#define SXGBE_MAX_DMA_RIWT 0xff
-#define SXGBE_MIN_DMA_RIWT 0x20
+/* Calculated based how much time does it take to fill 256KB Rx memory
+ * at 10Gb speed at 156MHz clock rate and considered little less then
+ * the actual value.
+ */
+#define SXGBE_MAX_DMA_RIWT 0x70
+#define SXGBE_MIN_DMA_RIWT 0x01
/* Tx coalesce parameters */
#define SXGBE_COAL_TX_TIMER4
@@ -203,6 +207,20 @@ enum dma_irq_status {
#define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num)\
for (queue_num = 0; queue_num < max_queues; queue_num++)
+#define DRV_VERSION "1.0.0"
+
+#define SXGBE_MAX_RX_CHANNELS 16
+#define SXGBE_MAX_TX_CHANNELS 16
+
+#define START_MAC_REG_OFFSET 0x
+#define MAX_MAC_REG_OFFSET 0x0DFC
+#define START_MTL_REG_OFFSET 0x1000
+#define MAX_MTL_REG_OFFSET 0x18FC
+#define START_DMA_REG_OFFSET 0x3000
+#define MAX_DMA_REG_OFFSET 0x38FC
+
+#define REG_SPACE_SIZE 0x2000
+
/* sxgbe statistics counters */
struct sxgbe_extra_stats {
/* TX/RX IRQ events */
@@ -484,7 +502,8 @@ struct sxgbe_priv_data {
int oldlink;
int speed;
int oldduplex;
- unsigned int flow_ctrl;
+ u8 rx_pause;
+ u8 tx_pause;
unsigned int pause;
struct mii_bus *mii;
int mii_irq[PHY_MAX_ADDR];
@@ -504,6 +523,7 @@ struct sxgbe_priv_data {
u32 adv_ts;
int use_riwt;
spinlock_t ptp_lock;
+ struct ptp_clock *ptp_clock;
/* EEE-LPI specific members */
struct timer_list eee_ctrl_timer;
@@ -542,4 +562,6 @@ const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv);
bool sxgbe_eee_init(struct sxgbe_priv_data * const priv);
+int sxgbe_set_flow_ctrl(struct sxgbe_priv_data *priv, int rx, int tx);
+
#endif /* __SXGBE_COMMON_H__ */
diff --git a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
index 89b1450..6a16f05 100644
--- a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
+++ b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
@@ -12,12 +12,17 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include
#include
#include
#include
+#include
#include
+#include
#include "sxgbe_common.h"
+#include "sxgbe_reg.h"
+#include "sxgbe_dma.h"
struct sxgbe_stats {
char stat_string[ETH_GSTRING_LEN];
@@ -33,17 +38,106 @@ struct sxgbe_stats {
}
static const struct sxgbe_stats sxgbe_gstrings_stats[] = {
+ /* TX/RX IRQ events */
+ SXGBE_STAT(tx_process_stopped_irq),
+ SXGBE_STAT(tx_ctxt_desc_err),
+ SXGBE_STAT(tx_threshold),
+ SXGBE_STAT(rx_threshold),
+ SXGBE_STAT(tx_pkt_n),
+ SXGBE_STAT(rx_pkt_n),
+ SXGBE_STAT(normal_irq_n),
+ SXGBE_STAT(tx_normal_irq_n),
+ SXGBE_STAT(rx_normal_irq_n),
+ SXGBE_STAT(napi_poll),
+ SXGBE_STAT(tx_clean),
+ SXGBE_STAT(tx_reset_ic_bit),
+ SXGBE_STAT(rx_process_stopped_irq),
+ SXGBE_STAT(rx_underflow_irq),
+
+ /* Bus access errors */
+ SXGBE_STAT(fatal_bus_error_irq),
+ SXGBE_STAT(tx_read_transfer_err),
+ SXGBE_STAT(tx_write_transfer_err),
+ SXGBE_STAT(tx_desc_access_err),
+ SXGBE_STAT(tx_buffer_access_err),
+ SXGBE_STAT(tx_data_transfer_err),
+ SXGBE_STAT(rx_read_transfer_err),
+ SXGBE_STAT(rx_write_transfer_err),
+ SXGBE_STAT(rx_desc_access_err),
+ SXGBE_STAT(rx_buffer_access_err),
+ SXGBE_STAT(rx_data_transfer_err),
+ SXGBE_STAT(pmt_irq_event_n),
+
+ /* EEE-LPI stats */
SXGBE_STAT(tx_lpi_entry_n),
SXGBE_STAT(tx_lpi_exit_n),
SXGBE_STAT(rx_lpi_entry_n),
SXGBE_STAT(rx_lpi_exit_n),
SXGBE_STAT(eee_wakeup_error_n),
- SXGBE_STAT(pmt_irq_event_n),
+
+ /* RX specific */
+ /* L2 error */
+ SXGBE_STAT(rx_code_gmii_err),
+ SXGBE_STAT(rx_watchdog_err),
+ SXGBE_STAT(rx_crc_err),
+ SXGBE_STAT(rx_gaint_pkt_err),
+ SXGBE_STAT(ip_hdr_err),
+ SXGBE_STAT(ip_payload_err),
+ SXGBE_STAT(overflow_error),
+
+ /* L2 Pkt type */
+ SXGBE_STAT(len_pkt),
+ SXGBE_STAT(mac_ctl_pkt),
[PATCH V2 RE-SEND 5/7] net: sxgbe: add WOL(Wakeup-On-Lan)support for Samsung sxgbe
From: Girish K S
This patch adds support for wake up on magic frame arrival.
Also remote wake up on all other packets (unicast, multicast
broadcast) is supported.
Signed-off-by: Girish K S
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h | 15 ++
drivers/net/ethernet/samsung/sxgbe_core.c | 29 ++
drivers/net/ethernet/samsung/sxgbe_ethtool.c | 47
drivers/net/ethernet/samsung/sxgbe_main.c | 71 +
drivers/net/ethernet/samsung/sxgbe_mtl.c | 43 ++-
drivers/net/ethernet/samsung/sxgbe_mtl.h |4 ++
drivers/net/ethernet/samsung/sxgbe_platform.c |4 ++
drivers/net/ethernet/samsung/sxgbe_reg.h |3 ++
8 files changed, 215 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index 68e8ad4..b029181 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -121,9 +121,18 @@ struct sxgbe_mtl_ops;
#define RX_ENTRY_LPI_MODE 0x40
#define RX_EXIT_LPI_MODE 0x80
+/* PMT mode bits */
+#define PMT_PWRDWN BIT(0)
+#define PMT_MGPKT_EN BIT(1)
+#define PMT_RWKPKT_EN BIT(2)
+#define PMT_GUCAST_EN BIT(9)
+
/* EEE-LPI Interrupt status flag */
#define LPI_INT_STATUS BIT(5)
+/* PMT Interrupt status */
+#define PMT_INT_STATUS BIT(4)
+
/* EEE-LPI Default timer values */
#define LPI_LINK_STATUS_TIMER 0x3E8
#define LPI_MAC_WAIT_TIMER 0x00
@@ -225,6 +234,7 @@ struct sxgbe_extra_stats {
unsigned long rx_desc_access_err;
unsigned long rx_buffer_access_err;
unsigned long rx_data_transfer_err;
+ unsigned long pmt_irq_event_n;
/* EEE-LPI stats */
unsigned long tx_lpi_entry_n;
@@ -502,6 +512,11 @@ struct sxgbe_priv_data {
int eee_enabled;
int eee_active;
int tx_lpi_timer;
+
+ /* PM-WOL specific members */
+ int wolopts;
+ int wolenabled;
+ int wol_irq;
};
/* Function prototypes */
diff --git a/drivers/net/ethernet/samsung/sxgbe_core.c
b/drivers/net/ethernet/samsung/sxgbe_core.c
index 5885fd6..334d196 100644
--- a/drivers/net/ethernet/samsung/sxgbe_core.c
+++ b/drivers/net/ethernet/samsung/sxgbe_core.c
@@ -78,12 +78,41 @@ static int sxgbe_core_host_irq_status(void __iomem *ioaddr,
if (unlikely(irq_status & LPI_INT_STATUS))
status |= sxgbe_get_lpi_status(ioaddr, irq_status);
+ if (unlikely(irq_status & PMT_INT_STATUS)) {
+ /* clear the PMT bits 5 and 6 by reading the PMT status reg */
+ readl(ioaddr + SXGBE_CORE_PMT_CTL_STATUS_REG);
+ x->pmt_irq_event_n++;
+ }
+
return status;
}
/* Set power management mode (e.g. magic frame) */
static void sxgbe_core_pmt(void __iomem *ioaddr, unsigned long mode)
{
+ unsigned int pmt = 0;
+
+ if (mode & WAKE_MAGIC) {
+ pr_debug("WOL Magic frame\n");
+ pmt |= PMT_MGPKT_EN;
+ }
+ if (mode & WAKE_UCAST) {
+ pr_debug("WOL on global unicast\n");
+ pmt |= PMT_GUCAST_EN;
+ }
+ if (mode & (WAKE_MCAST | WAKE_BCAST)) {
+ pr_debug("WOL on any other packet\n");
+ pmt |= PMT_RWKPKT_EN;
+ }
+
+ writel(pmt, ioaddr + SXGBE_CORE_PMT_CTL_STATUS_REG);
+
+ /* Enable power down bit if any of the requested mode is enabled */
+ if (pmt) {
+ writel(SXGBE_RX_ENABLE, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+ pmt |= PMT_PWRDWN;
+ writel(pmt, ioaddr + SXGBE_CORE_PMT_CTL_STATUS_REG);
+ }
}
/* Set/Get Unicast MAC addresses */
diff --git a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
index 9083300..89b1450 100644
--- a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
+++ b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
@@ -12,6 +12,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include
#include
#include
#include
@@ -37,6 +38,7 @@ static const struct sxgbe_stats sxgbe_gstrings_stats[] = {
SXGBE_STAT(rx_lpi_entry_n),
SXGBE_STAT(rx_lpi_exit_n),
SXGBE_STAT(eee_wakeup_error_n),
+ SXGBE_STAT(pmt_irq_event_n),
};
#define SXGBE_STATS_LEN ARRAY_SIZE(sxgbe_gstrings_stats)
@@ -80,9 +82,54 @@ static int sxgbe_ethtool_set_eee(struct net_device *dev,
return phy_ethtool_set_eee(priv->phydev, edata);
}
+static void sxgbe_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+ struct sxgbe_priv_data *priv = netdev_priv(dev);
+
+ wol->wolopts = 0;
+ if (!device_can_wakeup(priv->device)) {
+ dev_err(priv->device, "cannot wakeup device\n");
+ return;
+ }
+
+ if (priv->hw_cap.pmt_magic_frame)
+ wol->supported |= WAKE_MAGIC;
+
[PATCH V2 RE-SEND 3/7] net: sxgbe: add EEE(Energy Efficient Ethernet) for Samsung sxgbe
From: Girish K S
Added support for the EEE(Energy Efficient Ethernet)
in 10G ethernet driver.
Signed-off-by: Girish K S
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h | 54 +
drivers/net/ethernet/samsung/sxgbe_core.c | 86 +-
drivers/net/ethernet/samsung/sxgbe_ethtool.c | 47
drivers/net/ethernet/samsung/sxgbe_main.c | 152 -
drivers/net/ethernet/samsung/sxgbe_platform.c |4 +
drivers/net/ethernet/samsung/sxgbe_reg.h |5 +
6 files changed, 346 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index 3f16220..21d8ee6 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -115,6 +115,33 @@ struct sxgbe_mtl_ops;
#define RX_PTP_SIGNAL 0x0A
#define RX_PTP_RESV_MSG0x0F
+/* EEE-LPI mode flags*/
+#define TX_ENTRY_LPI_MODE 0x10
+#define TX_EXIT_LPI_MODE 0x20
+#define RX_ENTRY_LPI_MODE 0x40
+#define RX_EXIT_LPI_MODE 0x80
+
+/* EEE-LPI Interrupt status flag */
+#define LPI_INT_STATUS BIT(5)
+
+/* EEE-LPI Default timer values */
+#define LPI_LINK_STATUS_TIMER 0x3E8
+#define LPI_MAC_WAIT_TIMER 0x00
+
+/* EEE-LPI Control and status definitions */
+#define LPI_CTRL_STATUS_TXABIT(19)
+#define LPI_CTRL_STATUS_PLSDIS BIT(18)
+#define LPI_CTRL_STATUS_PLSBIT(17)
+#define LPI_CTRL_STATUS_LPIEN BIT(16)
+#define LPI_CTRL_STATUS_TXRSTP BIT(11)
+#define LPI_CTRL_STATUS_RXRSTP BIT(10)
+#define LPI_CTRL_STATUS_RLPIST BIT(9)
+#define LPI_CTRL_STATUS_TLPIST BIT(8)
+#define LPI_CTRL_STATUS_RLPIEX BIT(3)
+#define LPI_CTRL_STATUS_RLPIEN BIT(2)
+#define LPI_CTRL_STATUS_TLPIEX BIT(1)
+#define LPI_CTRL_STATUS_TLPIEN BIT(0)
+
enum dma_irq_status {
tx_hard_error = BIT(0),
tx_bump_tc = BIT(1),
@@ -199,6 +226,13 @@ struct sxgbe_extra_stats {
unsigned long rx_buffer_access_err;
unsigned long rx_data_transfer_err;
+ /* EEE-LPI stats */
+ unsigned long tx_lpi_entry_n;
+ unsigned long tx_lpi_exit_n;
+ unsigned long rx_lpi_entry_n;
+ unsigned long rx_lpi_exit_n;
+ unsigned long eee_wakeup_error_n;
+
/* RX specific */
/* L2 error */
unsigned long rx_code_gmii_err;
@@ -306,6 +340,13 @@ struct sxgbe_core_ops {
unsigned char feature_index);
/* adjust SXGBE speed */
void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
+
+ /* EEE-LPI specific operations */
+ void (*set_eee_mode)(void __iomem *ioaddr);
+ void (*reset_eee_mode)(void __iomem *ioaddr);
+ void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
+ const int tw);
+ void (*set_eee_pls)(void __iomem *ioaddr, const int link);
};
const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
@@ -367,6 +408,8 @@ struct sxgbe_hw_features {
/* IEEE 1588-2008 */
unsigned int atime_stamp;
+ unsigned int eee;
+
unsigned int tx_csum_offload;
unsigned int rx_csum_offload;
unsigned int multi_macaddr;
@@ -447,6 +490,14 @@ struct sxgbe_priv_data {
u32 adv_ts;
int use_riwt;
spinlock_t ptp_lock;
+
+ /* EEE-LPI specific members */
+ struct timer_list eee_ctrl_timer;
+ bool tx_path_in_lpi_mode;
+ int lpi_irq;
+ int eee_enabled;
+ int eee_active;
+ int tx_lpi_timer;
};
/* Function prototypes */
@@ -469,4 +520,7 @@ int sxgbe_restore(struct net_device *ndev);
const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
+void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv);
+bool sxgbe_eee_init(struct sxgbe_priv_data * const priv);
+
#endif /* __SXGBE_COMMON_H__ */
diff --git a/drivers/net/ethernet/samsung/sxgbe_core.c
b/drivers/net/ethernet/samsung/sxgbe_core.c
index 17eea58..bf93b16 100644
--- a/drivers/net/ethernet/samsung/sxgbe_core.c
+++ b/drivers/net/ethernet/samsung/sxgbe_core.c
@@ -47,11 +47,38 @@ static void sxgbe_core_dump_regs(void __iomem *ioaddr)
{
}
+static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status)
+{
+ int status = 0;
+ int lpi_status;
+
+ /* Reading this register shall clear all the LPI status bits */
+ lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
+
+ if (lpi_status & LPI_CTRL_STATUS_TLPIEN)
+ status |= TX_ENTRY_LPI_MODE;
+ if (lpi_status & LPI_CTRL_STATUS_TLPIEX)
+ status |= TX_EXIT_LPI_MODE;
+ if (lpi_status & LPI_CTRL_STATUS_RLPIEN)
+ status |= RX_ENTRY_LPI_MODE;
+ if (lpi_status & LPI_CTRL_STATUS_RLPIEX)
+ status |= RX_EXIT_LPI_MODE;
+
+ return status;
+}
+
/* Handle extra events on specific interrupts hw dependent */
static int sxgbe_core_host_irq_status(void
[PATCH V2 RE-SEND 2/7] net: sxgbe: add TSO support for Samsung sxgbe
From: Vipul Pandya
Enable TSO during initialization for each DMA channels
Signed-off-by: Vipul Pandya
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_desc.c | 47 +++---
drivers/net/ethernet/samsung/sxgbe_desc.h | 17 +--
drivers/net/ethernet/samsung/sxgbe_dma.c | 10
drivers/net/ethernet/samsung/sxgbe_dma.h |2 +
drivers/net/ethernet/samsung/sxgbe_main.c | 75 ++---
5 files changed, 130 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_desc.c
b/drivers/net/ethernet/samsung/sxgbe_desc.c
index 9a93553..fa21236 100644
--- a/drivers/net/ethernet/samsung/sxgbe_desc.c
+++ b/drivers/net/ethernet/samsung/sxgbe_desc.c
@@ -28,6 +28,16 @@ static void sxgbe_init_tx_desc(struct sxgbe_tx_norm_desc *p)
p->tdes23.tx_rd_des23.own_bit = 0;
}
+static void sxgbe_tx_desc_enable_tse(struct sxgbe_tx_norm_desc *p, u8 is_tse,
+u32 total_hdr_len, u32 tcp_hdr_len,
+u32 tcp_payload_len)
+{
+ p->tdes23.tx_rd_des23.tse_bit = is_tse;
+ p->tdes23.tx_rd_des23.buf1_size = total_hdr_len;
+ p->tdes23.tx_rd_des23.tcp_hdr_len = tcp_hdr_len / 4;
+ p->tdes23.tx_rd_des23.tx_pkt_len.tcp_payload_len = tcp_payload_len;
+}
+
/* Assign buffer lengths for descriptor */
static void sxgbe_prepare_tx_desc(struct sxgbe_tx_norm_desc *p, u8 is_fd,
int buf1_len, int pkt_len, int cksum)
@@ -102,36 +112,47 @@ static int sxgbe_get_tx_timestamp_status(struct
sxgbe_tx_norm_desc *p)
}
/* TX Context Descripto Specific */
-static void sxgbe_init_tx_ctxtdesc(struct sxgbe_tx_ctxt_desc *p)
+static void sxgbe_tx_ctxt_desc_set_ctxt(struct sxgbe_tx_ctxt_desc *p)
{
p->ctxt_bit = 1;
- p->own_bit = 0;
}
/* Set the owner of TX context descriptor */
-static void sxgbe_set_tx_ctxt_owner(struct sxgbe_tx_ctxt_desc *p)
+static void sxgbe_tx_ctxt_desc_set_owner(struct sxgbe_tx_ctxt_desc *p)
{
p->own_bit = 1;
}
/* Get the owner of TX context descriptor */
-static int sxgbe_get_tx_ctxt_owner(struct sxgbe_tx_ctxt_desc *p)
+static int sxgbe_tx_ctxt_desc_get_owner(struct sxgbe_tx_ctxt_desc *p)
{
return p->own_bit;
}
/* Set TX mss in TX context Descriptor */
-static void sxgbe_tx_ctxt_desc_setmss(struct sxgbe_tx_ctxt_desc *p, int mss)
+static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, u16 mss)
{
p->maxseg_size = mss;
}
/* Get TX mss from TX context Descriptor */
-static int sxgbe_tx_ctxt_desc_getmss(struct sxgbe_tx_ctxt_desc *p)
+static int sxgbe_tx_ctxt_desc_get_mss(struct sxgbe_tx_ctxt_desc *p)
{
return p->maxseg_size;
}
+/* Set TX tcmssv in TX context Descriptor */
+static void sxgbe_tx_ctxt_desc_set_tcmssv(struct sxgbe_tx_ctxt_desc *p)
+{
+ p->tcmssv = 1;
+}
+
+/* Reset TX ostc in TX context Descriptor */
+static void sxgbe_tx_ctxt_desc_reset_ostc(struct sxgbe_tx_ctxt_desc *p)
+{
+ p->ostc = 0;
+}
+
/* Set IVLAN information */
static void sxgbe_tx_ctxt_desc_set_ivlantag(struct sxgbe_tx_ctxt_desc *p,
int is_ivlanvalid, int ivlan_tag,
@@ -177,13 +198,13 @@ static void sxgbe_tx_ctxt_desc_set_tstamp(struct
sxgbe_tx_ctxt_desc *p,
}
}
/* Close TX context descriptor */
-static void sxgbe_close_tx_ctxt_desc(struct sxgbe_tx_ctxt_desc *p)
+static void sxgbe_tx_ctxt_desc_close(struct sxgbe_tx_ctxt_desc *p)
{
p->own_bit = 1;
}
/* WB status of context descriptor */
-static int sxgbe_get_tx_ctxt_cde(struct sxgbe_tx_ctxt_desc *p)
+static int sxgbe_tx_ctxt_desc_get_cde(struct sxgbe_tx_ctxt_desc *p)
{
return p->ctxt_desc_err;
}
@@ -432,6 +453,7 @@ static u64 sxgbe_get_rx_timestamp(struct sxgbe_rx_ctxt_desc
*p)
static const struct sxgbe_desc_ops desc_ops = {
.init_tx_desc = sxgbe_init_tx_desc,
+ .tx_desc_enable_tse = sxgbe_tx_desc_enable_tse,
.prepare_tx_desc = sxgbe_prepare_tx_desc,
.tx_vlanctl_desc = sxgbe_tx_vlanctl_desc,
.set_tx_owner = sxgbe_set_tx_owner,
@@ -443,11 +465,20 @@ static const struct sxgbe_desc_ops desc_ops = {
.get_tx_len = sxgbe_get_tx_len,
.tx_enable_tstamp = sxgbe_tx_enable_tstamp,
.get_tx_timestamp_status = sxgbe_get_tx_timestamp_status,
+ .tx_ctxt_desc_set_ctxt = sxgbe_tx_ctxt_desc_set_ctxt,
+ .tx_ctxt_desc_set_owner = sxgbe_tx_ctxt_desc_set_owner,
+ .get_tx_ctxt_owner = sxgbe_tx_ctxt_desc_get_owner,
+ .tx_ctxt_desc_set_mss = sxgbe_tx_ctxt_desc_set_mss,
+ .tx_ctxt_desc_get_mss = sxgbe_tx_ctxt_desc_get_mss,
+ .tx_ctxt_desc_set_tcmssv = sxgbe_tx_ctxt_desc_set_tcmssv,
+ .tx_ctxt_desc_reset_ostc = sxgbe_tx_ctxt_desc_reset_ostc,
.tx_ctxt_desc_set_ivlantag = sxgbe_tx_ctxt_desc_set_ivlantag,
.tx_ctxt_desc_get_ivlantag = sxgbe_tx_ctxt_desc_get_ivlantag,
.tx_ctxt_desc_set_vlantag = sxgbe_tx_ctxt
[PATCH V2 RE-SEND 4/7] net: sxgbe: add Checksum offload support for Samsung sxgbe
From: Vipul Pandya
This patch adds TX and RX checksum offload support.
Signed-off-by: Vipul Pandya
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h |6 +++-
drivers/net/ethernet/samsung/sxgbe_core.c | 20
drivers/net/ethernet/samsung/sxgbe_desc.c | 27
drivers/net/ethernet/samsung/sxgbe_desc.h |6 ++--
drivers/net/ethernet/samsung/sxgbe_main.c | 46 ---
5 files changed, 84 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index 21d8ee6..68e8ad4 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -347,6 +347,10 @@ struct sxgbe_core_ops {
void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
const int tw);
void (*set_eee_pls)(void __iomem *ioaddr, const int link);
+
+ /* Enable disable checksum offload operations */
+ void (*enable_rx_csum)(void __iomem *ioaddr);
+ void (*disable_rx_csum)(void __iomem *ioaddr);
};
const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
@@ -462,7 +466,7 @@ struct sxgbe_priv_data {
struct net_device *dev;
struct device *device;
struct sxgbe_ops *hw;/* sxgbe specific ops */
- int no_csum_insertion;
+ int rxcsum_insertion;
spinlock_t lock;
spinlock_t stats_lock;
diff --git a/drivers/net/ethernet/samsung/sxgbe_core.c
b/drivers/net/ethernet/samsung/sxgbe_core.c
index bf93b16..5885fd6 100644
--- a/drivers/net/ethernet/samsung/sxgbe_core.c
+++ b/drivers/net/ethernet/samsung/sxgbe_core.c
@@ -217,6 +217,24 @@ static void sxgbe_set_eee_timer(void __iomem *ioaddr,
writel(value, ioaddr + SXGBE_CORE_LPI_TIMER_CTRL);
}
+static void sxgbe_enable_rx_csum(void __iomem *ioaddr)
+{
+ u32 ctrl;
+
+ ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+ ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE;
+ writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+}
+
+static void sxgbe_disable_rx_csum(void __iomem *ioaddr)
+{
+ u32 ctrl;
+
+ ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+ ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE;
+ writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+}
+
const struct sxgbe_core_ops core_ops = {
.core_init = sxgbe_core_init,
.dump_regs = sxgbe_core_dump_regs,
@@ -233,6 +251,8 @@ const struct sxgbe_core_ops core_ops = {
.reset_eee_mode = sxgbe_reset_eee_mode,
.set_eee_timer = sxgbe_set_eee_timer,
.set_eee_pls = sxgbe_set_eee_pls,
+ .enable_rx_csum = sxgbe_enable_rx_csum,
+ .disable_rx_csum = sxgbe_disable_rx_csum,
};
const struct sxgbe_core_ops *sxgbe_get_core_ops(void)
diff --git a/drivers/net/ethernet/samsung/sxgbe_desc.c
b/drivers/net/ethernet/samsung/sxgbe_desc.c
index fa21236..8d9ee61 100644
--- a/drivers/net/ethernet/samsung/sxgbe_desc.c
+++ b/drivers/net/ethernet/samsung/sxgbe_desc.c
@@ -47,6 +47,9 @@ static void sxgbe_prepare_tx_desc(struct sxgbe_tx_norm_desc
*p, u8 is_fd,
p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.total_pkt_len = pkt_len;
+ if (cksum)
+ p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.cksum_ctl =
+ cic_full;
}
/* Set VLAN control information */
@@ -250,31 +253,40 @@ static int sxgbe_get_rx_ld_status(struct
sxgbe_rx_norm_desc *p)
/* Return the RX status looking at the WB fields */
-static void sxgbe_rx_wbstatus(struct sxgbe_rx_norm_desc *p,
- struct sxgbe_extra_stats *x)
+static int sxgbe_rx_wbstatus(struct sxgbe_rx_norm_desc *p,
+struct sxgbe_extra_stats *x, int *checksum)
{
+ int status = 0;
+ *checksum = CHECKSUM_UNNECESSARY;
if (p->rdes23.rx_wb_des23.err_summary) {
switch (p->rdes23.rx_wb_des23.err_l2_type) {
case RX_GMII_ERR:
+ status = -EINVAL;
x->rx_code_gmii_err++;
break;
case RX_WATCHDOG_ERR:
+ status = -EINVAL;
x->rx_watchdog_err++;
break;
case RX_CRC_ERR:
+ status = -EINVAL;
x->rx_crc_err++;
break;
case RX_GAINT_ERR:
+ status = -EINVAL;
x->rx_gaint_pkt_err++;
break;
case RX_IP_HDR_ERR:
+ *checksum = CHECKSUM_NONE;
x->ip_hdr_err++;
break;
case RX_PAYLOAD_ERR:
+ *checksum = CHECKSUM_NONE;
x->ip_payload_err++;
break;
case RX_OVERFLOW_ERR:
+ status = -EINVAL
[PATCH V2 RE-SEND 0/7] add new Samsung SXGbE driver
Hi all, This is 2nd posting for Samsung SXGbE driver and just re-sending because of line wrapping in previous posting. Changes since v1: - changed name of driver to SXGbE as per Ben's comment - squashed Joe's neatening for many stuff in original patches Byungho An (1): MAINTAINERS: add maintainer for Samsung sxgbe driver Girish K S (2): net: sxgbe: add EEE(Energy Efficient Ethernet) for Samsung sxgbe net: sxgbe: add WOL(Wakeup-On-Lan)support for Samsung sxgbe Siva Reddy (1): net: sxgbe: add basic framework for Samsung 10Gb ethernet driver Vipul Pandya (3): net: sxgbe: add TSO support for Samsung sxgbe net: sxgbe: add Checksum offload support for Samsung sxgbe net: sxgbe: add ethtool related functions support Samsung sxgbe .../devicetree/bindings/net/samsung-sxgbe.txt | 39 + MAINTAINERS|9 + drivers/net/ethernet/Kconfig |1 + drivers/net/ethernet/Makefile |1 + drivers/net/ethernet/samsung/Kconfig |7 + drivers/net/ethernet/samsung/Makefile |4 + drivers/net/ethernet/samsung/sxgbe_common.h| 571 + drivers/net/ethernet/samsung/sxgbe_core.c | 290 +++ drivers/net/ethernet/samsung/sxgbe_desc.c | 515 drivers/net/ethernet/samsung/sxgbe_desc.h | 298 +++ drivers/net/ethernet/samsung/sxgbe_dma.c | 381 +++ drivers/net/ethernet/samsung/sxgbe_dma.h | 51 + drivers/net/ethernet/samsung/sxgbe_ethtool.c | 628 + drivers/net/ethernet/samsung/sxgbe_main.c | 2447 drivers/net/ethernet/samsung/sxgbe_mdio.c | 274 +++ drivers/net/ethernet/samsung/sxgbe_mtl.c | 279 +++ drivers/net/ethernet/samsung/sxgbe_mtl.h | 108 + drivers/net/ethernet/samsung/sxgbe_platform.c | 272 +++ drivers/net/ethernet/samsung/sxgbe_reg.h | 491 drivers/net/ethernet/samsung/sxgbe_xpcs.c | 92 + drivers/net/ethernet/samsung/sxgbe_xpcs.h | 38 + include/linux/sxgbe_platform.h | 54 + 22 files changed, 6850 insertions(+) Thanks, Byungho An -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 3/3] ARM: dts: add dts files for xyref5260 board
On 13 March 2014 10:31, Rahul Sharma wrote:
> Thanks Pankaj,
>
> On 13 March 2014 06:19, Pankaj Dubey wrote:
>> Hi Rahul,
>>
>>
>> On 03/13/2014 12:16 AM, Rahul Sharma wrote:
>>>
>>> The patch adds the dts files for xyref5260 board which
>>> is based on Exynos5260 Evt0 sample.
>>>
>>> Signed-off-by: Rahul Sharma
>>> ---
>>> arch/arm/boot/dts/Makefile |1 +
>>> arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 110
>>> +++
>>> 2 files changed, 111 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index b9d6a8b..5a391bf 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>>> exynos5250-arndale.dtb \
>>> exynos5250-smdk5250.dtb \
>>> exynos5250-snow.dtb \
>>> + exynos5260-xyref5260-evt0.dtb \
>>> exynos5420-arndale-octa.dtb \
>>> exynos5420-smdk5420.dtb \
>>> exynos5440-sd5v1.dtb \
>>> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>>> b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>>> new file mode 100644
>>> index 000..d7d0aeb
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>>> @@ -0,0 +1,110 @@
>>> +/*
>>> + * SAMSUNG XYREF5260 EVT0 board device tree source
>>> + *
>>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>>> + * http://www.samsung.com
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> +*/
>>> +
>>> +/dts-v1/;
>>> +#include "exynos5260.dtsi"
>>> +
>>> +/ {
>>> + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
>>> + compatible = "samsung,xyref5260", "samsung,exynos5260";
>>> +
>>> + memory {
>>> + reg = <0x2000 0x8000>;
>>> + };
>>> +
>>> + chosen {
>>> + bootargs = "console=ttySAC2,115200";
>>> + };
>>> +
>>> + clocks {
>>> + fin_pll: xxti {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <2400>;
>>> + clock-output-names = "fin_pll";
>>> + #clock-cells = <0>;
>>> + };
>>> +
>>> + xrtcxti: xrtcxti {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <32768>;
>>> + clock-output-names = "xrtcxti";
>>> + };
>>
>>
>> clock-cells property is missing here.
>>
>
I have added #clock-cells only for clocks which
are supposed to be referred. IMO we don't need it otherwise.
>
>>
>>> +
>>> + spdif_extclk: ioclk_spdif_extclk {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <49152000>;
>>> + clock-output-names = "ioclk_spdif_extclk";
>>> + };
>>
>>
>> ditto.
>>
>>> + };
>>> +};
>>
>>
>> May I know why other phyclocks and ioclks have not been added?
>>
>
> Phyclocks should be added in SoC file. Please refer the other patch.
>
> Ioclocks have 2 dimensions. 1) A board may or may not have these.
> But if board doesn't have them, we may end up with orphans in clock
> tree. 2) Adding them in SoC is not meaningful because rate is board
> dependent and cannot be mentioned in SoC file. Without rate, probe
> will not be successful.
>
> What I followed here is adding IO clocks which are resulting into
> orphan clocks.
>
> What we can do is to allow the registration of fixed-io-clocks in clock
> driver which are provided without RATE? If this looks good, I can post
> the respective patch for clock driver and dt correction.
>
> I want to request experts to comment on this.
>
> Regards,
> Rahul Sharma
>
>>
>>> +
>>> +&pinctrl_0 {
>>> + hdmi_hpd_irq: hdmi-hpd-irq {
>>> + samsung,pins = "gpx3-7";
>>> + samsung,pin-function = <0>;
>>> + samsung,pin-pud = <1>;
>>> + samsung,pin-drv = <0>;
>>> + };
>>> +};
>>> +
>>> +&uart0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart1 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart2 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&uart3 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&mmc_0 {
>>> + status = "okay";
>>> + num-slots = <1>;
>>> + broken-cd;
>>> + bypass-smu;
>>> + supports-highspeed;
>>> + supports-hs200-mode; /* 200 Mhz */
>>> + card-detect-delay = <200>;
>>> + samsung,dw-mshc-ciu-div = <3>;
>>> + samsung,dw-mshc-sdr-timing = <0 4>;
>>> + samsung,dw-mshc-ddr-timing = <0 2>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_c
Re: [PATCH v5 4/5] clk/exynos5260: add macros and documentation for exynos5260
On 13 March 2014 06:53, Pankaj Dubey wrote:
> Hi Rahul,
>
>
> On 03/12/2014 11:56 PM, Rahul Sharma wrote:
>>
>> Add macros which are used as Clock IDs in DT and clock file.
>> It also adds the documentation for the exynos5260 clocks.
>>
>> Signed-off-by: Rahul Sharma
>> ---
>> .../devicetree/bindings/clock/exynos5260-clock.txt | 55 +
>> include/dt-bindings/clock/exynos5260-clk.h | 233
>>
>> 2 files changed, 288 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/exynos5260-clock.txt
>> create mode 100644 include/dt-bindings/clock/exynos5260-clk.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
>> new file mode 100644
>> index 000..4128892
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
>> @@ -0,0 +1,55 @@
>> +* Samsung Exynos5260 Clock Controller
>> +
>> +The Exynos5260 clock controller encapsulate all CMUs which are
>> +instantiaited independently from the device-tree. As a whole, these
>> +CMUs generates and supplies clocks to various controllers within
>> +the Exynos5260 SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following.
>> + "exynos5260-clock-top"
>> + "exynos5260-clock-peri"
>> + "exynos5260-clock-egl"
>> + "exynos5260-clock-kfc"
>> + "exynos5260-clock-g2d"
>> + "exynos5260-clock-mif"
>> + "exynos5260-clock-mfc"
>> + "exynos5260-clock-g3d"
>> + "exynos5260-clock-fsys"
>> + "exynos5260-clock-aud"
>> + "exynos5260-clock-isp"
>> + "exynos5260-clock-gscl"
>> + "exynos5260-clock-disp"
>> +
>> +- reg: physical base address of the controller and length of memory
>> mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +The following is the list of clocks generated by each controller. Each
>> +clock is assigned with a MACRO constant. These constants are defined in
>> +"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to
>
>
> nit: s/clk/clock
>
Oops. I will change this.
>
>> +specify the clock, which they want to consume.
>> +
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> + cmu_disp: clock-controller@0x1455 {
>> + compatible = "exynos5260-clock-disp";
>> + reg = <0x1455 0x1>;
>> + #clock-cells = <1>;
>> + };
>> +
>> +Example 2: UART controller node that consumes the clock generated by the
>> + peri clock controller. Refer to the standard clock
>> bindings for
>> + information about 'clocks' and 'clock-names' property.
>> +
>> + serial@12C0 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C0 0x100>;
>> + interrupts = <0 146 0>;
>> + clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri
>> PERI_SCLK_UART0>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + status = "disabled";
>> + };
>
>
> Isn't it better that we should add binding information about fixed-clocks
> (phyclocks and ioclks) here?
>
Binding for "fixed-clocks" are applicable for the above clocks. We don't
need to add them here. Did you mean something different ?
>
>> +
>> diff --git a/include/dt-bindings/clock/exynos5260-clk.h
>> b/include/dt-bindings/clock/exynos5260-clk.h
>> new file mode 100644
>> index 000..d6f4391
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/exynos5260-clk.h
>> @@ -0,0 +1,233 @@
>> +/*
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Provides Constants for Exynos5260 clocks.
>> +*/
>> +
>> +#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
>> +#define _DT_BINDINGS_CLK_EXYNOS5260_H
>> +
>> +/*
>> + * Clock names:X_YY_
>> + * |---| || |--|
>> + * cmu type IP
>> + */
>> +
>> +/* List Of Clocks For CMU_TOP */
>> +#define FIN_PLL1
>
>
> This should be removed now.
>
>
>> +#define TOP_FOUT_DISP_PLL 2
>> +#define TOP_FOUT_AUD_PLL 3
>> +#define TOP_SCLK_MMC0 4
>> +#define TOP_SCLK_MMC1 5
>> +#define TOP_SCLK_MMC2 6
>> +#define TOP_SCLK_HDMIPHY 7
>> +#define TOP_SCLK_FIMD1 8
>> +#define TOP_MOUT_FIMD1 9
>> +#define TOP_MOUT_DISP_PLL 10
>> +#define TOP_HDMI_PHY_PIXEL_CLKO11
>
>
yea, I will remove these 2.
>
>
>> +#define TOP_NR_CLK 12
>> +
>> +/* List Of Clocks For CMU_EGL */
>> +#define EGL_FOUT_EGL_PLL 1
>> +#define EGL_FOUT_EGL_DPLL 2
>> +#define EGL_NR_CLK 3
>> +
>> +/* List Of Clocks For CMU_KFC */
>> +#define KFC_FOUT_KFC_PLL
Re: [PATCH v5 2/3] ARM: dts: add dts files for exynos5260 SoC
On 13 March 2014 06:28, Pankaj Dubey wrote:
> On 03/13/2014 12:16 AM, Rahul Sharma wrote:
>>
>> The patch adds the dts files for exynos5260.
>>
>> Signed-off-by: Pankaj Dubey
>> Signed-off-by: Rahul Sharma
>> Signed-off-by: Arun Kumar K
>> Reviewed-by: Tomasz Figa
>> ---
>> arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574
>> +
>> arch/arm/boot/dts/exynos5260.dtsi | 400
>> 2 files changed, 974 insertions(+)
>> create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
>> create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
>>
>> diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
>> b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
>> new file mode 100644
>> index 000..f6ee55e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
>> @@ -0,0 +1,574 @@
>> +/*
>> + * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as
>> device
>> + * tree nodes are listed in this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#define PIN_PULL_NONE 0
>> +#define PIN_PULL_DOWN 1
>> +#define PIN_PULL_UP3
>> +
>> +&pinctrl_0 {
>> + gpa0: gpa0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpa1: gpa1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpa2: gpa2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb0: gpb0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb1: gpb1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb2: gpb2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb3: gpb3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb4: gpb4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb5: gpb5 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd0: gpd0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd1: gpd1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd2: gpd2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpe0: gpe0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpe1: gpe1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf0: gpf0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf1: gpf1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpk0: gpk0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>>
Re: [PATCH v5 3/3] ARM: dts: add dts files for xyref5260 board
Thanks Pankaj,
On 13 March 2014 06:19, Pankaj Dubey wrote:
> Hi Rahul,
>
>
> On 03/13/2014 12:16 AM, Rahul Sharma wrote:
>>
>> The patch adds the dts files for xyref5260 board which
>> is based on Exynos5260 Evt0 sample.
>>
>> Signed-off-by: Rahul Sharma
>> ---
>> arch/arm/boot/dts/Makefile |1 +
>> arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 110
>> +++
>> 2 files changed, 111 insertions(+)
>> create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index b9d6a8b..5a391bf 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>> exynos5250-arndale.dtb \
>> exynos5250-smdk5250.dtb \
>> exynos5250-snow.dtb \
>> + exynos5260-xyref5260-evt0.dtb \
>> exynos5420-arndale-octa.dtb \
>> exynos5420-smdk5420.dtb \
>> exynos5440-sd5v1.dtb \
>> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>> b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>> new file mode 100644
>> index 000..d7d0aeb
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>> @@ -0,0 +1,110 @@
>> +/*
>> + * SAMSUNG XYREF5260 EVT0 board device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/dts-v1/;
>> +#include "exynos5260.dtsi"
>> +
>> +/ {
>> + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
>> + compatible = "samsung,xyref5260", "samsung,exynos5260";
>> +
>> + memory {
>> + reg = <0x2000 0x8000>;
>> + };
>> +
>> + chosen {
>> + bootargs = "console=ttySAC2,115200";
>> + };
>> +
>> + clocks {
>> + fin_pll: xxti {
>> + compatible = "fixed-clock";
>> + clock-frequency = <2400>;
>> + clock-output-names = "fin_pll";
>> + #clock-cells = <0>;
>> + };
>> +
>> + xrtcxti: xrtcxti {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "xrtcxti";
>> + };
>
>
> clock-cells property is missing here.
>
I have added #clock-cells only for clocks which
are supposed to be referred. IMO we need it otherwise.
>
>> +
>> + spdif_extclk: ioclk_spdif_extclk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <49152000>;
>> + clock-output-names = "ioclk_spdif_extclk";
>> + };
>
>
> ditto.
>
>> + };
>> +};
>
>
> May I know why other phyclocks and ioclks have not been added?
>
Phyclocks should be added in SoC file. Please refer the other patch.
Ioclocks have 2 dimensions. 1) A board may or may not have these.
But if board doesn't have them, we may end up with orphans in clock
tree. 2) Adding them in SoC is not meaningful because rate is board
dependent and cannot be mentioned in SoC file. Without rate, probe
will not be successful.
What I followed here is adding IO clocks which are resulting into
orphan clocks.
What we can do is to allow the registration of fixed-io-clocks in clock
driver which are provided without RATE? If this looks good, I can post
the respective patch for clock driver and dt correction.
I want to request experts to comment on this.
Regards,
Rahul Sharma
>
>> +
>> +&pinctrl_0 {
>> + hdmi_hpd_irq: hdmi-hpd-irq {
>> + samsung,pins = "gpx3-7";
>> + samsung,pin-function = <0>;
>> + samsung,pin-pud = <1>;
>> + samsung,pin-drv = <0>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> +
>> +&uart1 {
>> + status = "okay";
>> +};
>> +
>> +&uart2 {
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + status = "okay";
>> +};
>> +
>> +&mmc_0 {
>> + status = "okay";
>> + num-slots = <1>;
>> + broken-cd;
>> + bypass-smu;
>> + supports-highspeed;
>> + supports-hs200-mode; /* 200 Mhz */
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <0 4>;
>> + samsung,dw-mshc-ddr-timing = <0 2>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4
>> &sd0_bus8>;
>> +
>> + slot@0 {
>> + reg = <0>;
>> + bus-width = <8>;
>> + };
>> +};
>> +
>> +&mmc_2 {
>> + status = "okay";
>> + num-slots = <1>;
>> +
Re: How to get the complete reference manual for a samsung exynos5 Soc
Dear Tushar, Thanks for replying. We already have that basic version, also it is for the dual core. Can you please point to the version which is specific to each Soc (like the one for 5250 / 5410 / 5420). Best Regards armdev team On 13-Mar-2014, at 9:30 am, Tushar Behera wrote: > On 12 March 2014 22:07, armdev wrote: >> Hi, >> >> Our team is working on 3 samsung exynos boards (5250/5410/5420), But we were >> not able to find a reference manual that describes the hardware in detail. >> As this is the samsung soc mailing list, kindly advice us the means by which >> we can get a copy of the manual. >> > > You can find the user manual for Exynos5250 here[1]. > > [1] > http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf > >> Regards >> armdev team-- >> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" >> in >> the body of a message to majord...@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html > > > > -- > Tushar Behera -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: How to get the complete reference manual for a samsung exynos5 Soc
On 12 March 2014 22:07, armdev wrote: > Hi, > > Our team is working on 3 samsung exynos boards (5250/5410/5420), But we were > not able to find a reference manual that describes the hardware in detail. As > this is the samsung soc mailing list, kindly advice us the means by which we > can get a copy of the manual. > You can find the user manual for Exynos5250 here[1]. [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf > Regards > armdev team-- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Tushar Behera -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] clk: exynos-5420: Fix VPLL lock offset
Set it as per the user manual. Signed-off-by: Sachin Kamat --- drivers/clk/samsung/clk-exynos5420.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 60b26819bed5..7fd6bea467fd 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -33,7 +33,7 @@ #define RPLL_LOCK 0x10050 #define IPLL_LOCK 0x10060 #define SPLL_LOCK 0x10070 -#define VPLL_LOCK 0x10070 +#define VPLL_LOCK 0x10080 #define MPLL_LOCK 0x10090 #define CPLL_CON0 0x10120 #define DPLL_CON0 0x10128 -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 0/5] ARM: dts: exynos: Add missing dt data to bring kernel of Exynos4x12
Dear Kukjin, On 03/12/2014 08:21 PM, Tomasz Figa wrote: > Hi Chanwoo, > > On 12.03.2014 07:19, Chanwoo Choi wrote: >> This patch add missing dt data of Exynos4x12 to bring up kernel feature and >> code clean. This patchset is based on 'v3.15-next/dt-clk-exynos' branch. >> - git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git >> >> exynos4x12/exynos4412/exynos4212.dtsi >> - Add ADC (Analog and Digital Converter) to get raw data >> - Add PMU (Performance Monitoring Unit) for perf event >> - Add gps_alive power domain to remove power leakage when gps-alive isn't >> used >> - Remove duplicate dt data of interrput combiner controller >> >> exynos4412-trats.dts >> - Add ADC dt data with ntc thermistor child to read temperature >> >> Changes from v1: >> - Use clock macro name for Exynos4 instead of constant for ADC >> - Remove unnecessary description about patch content >> - Move gps-alive power domain's dt data from exynos4x12.dts to exynos4.dts >> - Move thermistor dt node outside of ADC dt node and modify node name of >> thermistor >> >> Chanwoo Choi (5): >>ARM: dts: exynos4x12: Add ADC's dt data to read raw data >>ARM: dts: exynos4x12: Add PMU dt data to support PMU(Perforamnce >> Monitoring Unit) >>ARM: dts: exynos4x12: Add GPS_ALIVE power domain >>ARM: dts: exynos: Move common dt data for interrupt combiner controller >>ARM: dts: exynos4412-trats2: Add ADC/themistor dt data to get temperature >> of SoC/battery >> >> arch/arm/boot/dts/exynos4.dtsi | 5 + >> arch/arm/boot/dts/exynos4212.dtsi | 13 - >> arch/arm/boot/dts/exynos4412-trats2.dts | 21 + >> arch/arm/boot/dts/exynos4412.dtsi | 14 -- >> arch/arm/boot/dts/exynos4x12.dtsi | 26 ++ >> 5 files changed, 60 insertions(+), 19 deletions(-) >> > > Reviewed-by: Tomasz Figa > Please review or comment this patchset. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 3/5] clk/samsung: add support for pll2650xx
Hi Rahul,
On 03/12/2014 11:56 PM, Rahul Sharma wrote:
Add support for pll2650xx in samsung pll file. This PLL variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma
---
drivers/clk/samsung/clk-pll.c | 101 +
drivers/clk/samsung/clk-pll.h |1 +
2 files changed, 102 insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 18e42ef..b07fad2 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1049,6 +1049,101 @@ static const struct clk_ops
samsung_pll2550xx_clk_min_ops = {
.recalc_rate = samsung_pll2550xx_recalc_rate,
};
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR 3000
+
+#define PLL2650XX_MDIV_SHIFT 9
+#define PLL2650XX_PDIV_SHIFT 3
+#define PLL2650XX_SDIV_SHIFT 0
+#define PLL2650XX_KDIV_SHIFT 0
+#define PLL2650XX_MDIV_MASK0x1ff
+#define PLL2650XX_PDIV_MASK0x3f
+#define PLL2650XX_SDIV_MASK0x7
+#define PLL2650XX_KDIV_MASK0x
+#define PLL2650XX_PLL_ENABLE_SHIFT 23
+#define PLL2650XX_PLL_LOCKTIME_SHIFT 21
+#define PLL2650XX_PLL_FOUTMASK_SHIFT 31
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+ mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+ kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con2;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+
+/* Change PLL PMS values */
+ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+ PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+ PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+ pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+ pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+ pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+ pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+ pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+ << PLL2650XX_KDIV_SHIFT;
+
+ /* Set PLL lock time. */
+ __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+ __raw_writel(pll_con0, pll->con_reg);
+ __raw_writel(pll_con2, pll->con_reg + 8);
+
+ do {
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+ .set_rate = samsung_pll2650xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -1157,6 +1252,12 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
else
init.ops = &samsung_pll2550xx_clk_ops;
break;
+ case pll_2650xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2650xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2650xx_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/
Re: [PATCH v5 4/5] clk/exynos5260: add macros and documentation for exynos5260
Hi Rahul,
On 03/12/2014 11:56 PM, Rahul Sharma wrote:
Add macros which are used as Clock IDs in DT and clock file.
It also adds the documentation for the exynos5260 clocks.
Signed-off-by: Rahul Sharma
---
.../devicetree/bindings/clock/exynos5260-clock.txt | 55 +
include/dt-bindings/clock/exynos5260-clk.h | 233
2 files changed, 288 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 include/dt-bindings/clock/exynos5260-clk.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
new file mode 100644
index 000..4128892
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
@@ -0,0 +1,55 @@
+* Samsung Exynos5260 Clock Controller
+
+The Exynos5260 clock controller encapsulate all CMUs which are
+instantiaited independently from the device-tree. As a whole, these
+CMUs generates and supplies clocks to various controllers within
+the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ "exynos5260-clock-top"
+ "exynos5260-clock-peri"
+ "exynos5260-clock-egl"
+ "exynos5260-clock-kfc"
+ "exynos5260-clock-g2d"
+ "exynos5260-clock-mif"
+ "exynos5260-clock-mfc"
+ "exynos5260-clock-g3d"
+ "exynos5260-clock-fsys"
+ "exynos5260-clock-aud"
+ "exynos5260-clock-isp"
+ "exynos5260-clock-gscl"
+ "exynos5260-clock-disp"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by each controller. Each
+clock is assigned with a MACRO constant. These constants are defined in
+"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to
nit: s/clk/clock
+specify the clock, which they want to consume.
+
+Example 1: An example of a clock controller node is listed below.
+
+ cmu_disp: clock-controller@0x1455 {
+ compatible = "exynos5260-clock-disp";
+ reg = <0x1455 0x1>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the
+ peri clock controller. Refer to the standard clock bindings for
+ information about 'clocks' and 'clock-names' property.
+
+ serial@12C0 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 146 0>;
+ clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri
PERI_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
Isn't it better that we should add binding information about fixed-clocks
(phyclocks and ioclks) here?
+
diff --git a/include/dt-bindings/clock/exynos5260-clk.h
b/include/dt-bindings/clock/exynos5260-clk.h
new file mode 100644
index 000..d6f4391
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5260-clk.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/*
+ * Clock names:X_YY_
+ * |---| || |--|
+ * cmu type IP
+ */
+
+/* List Of Clocks For CMU_TOP */
+#define FIN_PLL1
This should be removed now.
+#define TOP_FOUT_DISP_PLL 2
+#define TOP_FOUT_AUD_PLL 3
+#define TOP_SCLK_MMC0 4
+#define TOP_SCLK_MMC1 5
+#define TOP_SCLK_MMC2 6
+#define TOP_SCLK_HDMIPHY 7
+#define TOP_SCLK_FIMD1 8
+#define TOP_MOUT_FIMD1 9
+#define TOP_MOUT_DISP_PLL 10
+#define TOP_HDMI_PHY_PIXEL_CLKO11
ditto.
+#define TOP_NR_CLK 12
+
+/* List Of Clocks For CMU_EGL */
+#define EGL_FOUT_EGL_PLL 1
+#define EGL_FOUT_EGL_DPLL 2
+#define EGL_NR_CLK 3
+
+/* List Of Clocks For CMU_KFC */
+#define KFC_FOUT_KFC_PLL 1
+#define KFC_NR_CLK 2
+
+/* List Of Clocks For CMU_MIF */
+#define MIF_FOUT_MEM_PLL 1
+#define MIF_FOUT_BUS_PLL 2
+#define MIF_FOUT_MEDIA_PLL 3
+#define MIF_NR_CLK 4
+
+/* List Of Clocks For CMU_G3D */
+#define G3D_FOUT_G3D_PLL 1
+#define G3D_CLK_G3D_HPM2
+#define G3D_CLK_G3D3
+#define G3D_NR_CLK 4
+
+/* List Of Clocks For CMU_AUD */
+#define AUD_CLK_AUD_UART 1
+#define AUD_CLK_PCM2
+#define AUD_CLK_I2S3
+#define AUD_CLK_DMAC 4
+#define AUD_SCLK_AUD_UART 5
+#define AUD_SCLK_PCM
Re: [PATCH v5 2/3] ARM: dts: add dts files for exynos5260 SoC
On 03/13/2014 12:16 AM, Rahul Sharma wrote:
The patch adds the dts files for exynos5260.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Signed-off-by: Arun Kumar K
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574 +
arch/arm/boot/dts/exynos5260.dtsi | 400
2 files changed, 974 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 000..f6ee55e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,574 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define PIN_PULL_NONE 0
+#define PIN_PULL_DOWN 1
+#define PIN_PULL_UP3
+
+&pinctrl_0 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+
Re: [PATCH v5 3/3] ARM: dts: add dts files for xyref5260 board
Hi Rahul,
On 03/13/2014 12:16 AM, Rahul Sharma wrote:
The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.
Signed-off-by: Rahul Sharma
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 110 +++
2 files changed, 111 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..5a391bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 000..d7d0aeb
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,110 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5260.dtsi"
+
+/ {
+ model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
+ compatible = "samsung,xyref5260", "samsung,exynos5260";
+
+ memory {
+ reg = <0x2000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ xrtcxti: xrtcxti {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xrtcxti";
+ };
clock-cells property is missing here.
+
+ spdif_extclk: ioclk_spdif_extclk {
+ compatible = "fixed-clock";
+ clock-frequency = <49152000>;
+ clock-output-names = "ioclk_spdif_extclk";
+ };
ditto.
+ };
+};
May I know why other phyclocks and ioclks have not been added?
+
+&pinctrl_0 {
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ supports-hs200-mode; /* 200 Mhz */
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+};
--
Best Regards,
Pankaj Dubey
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Re: [PATCH] i2c-s3c2410: Leave the bus disabled unless it is in use
On Wed, Mar 12, 2014 at 08:27:14PM +0100, Wolfram Sang wrote: > On Fri, Feb 07, 2014 at 02:24:09PM +0530, Naveen Krishna Chatradhi wrote: > > From: Simon Glass > > > > There is a rather odd feature of the exynos i2c controller that if it > > is left enabled, it can lock itself up with the clk line held low. > > This makes the bus unusable. > > > > Unfortunately, the s3c24xx_i2c_set_master() function does not notice > > this, and reports a timeout. From then on the bus cannot be used until > > the AP is rebooted. > > > > The problem happens when any sort of interrupt occurs (e.g. due to a > > bus transition) when we are not in the middle of a transaction. We > > have seen many instances of this when U-Boot leaves the bus apparently > > happy, but Linux cannot access it. > > > > The current code is therefore pretty fragile. > > > > This fixes things by leaving the bus disabled unless we are actually > > in a transaction. We enable the bus at the start of the transaction and > > disable it at the end. That way we won't get interrupts and will not > > lock up the bus. > > > > It might be possible to clear pending interrupts on start-up, but this > > seems to be a more robust solution. We can't service interrupts when > > we are not in a transaction, and anyway would rather not lock up the > > bus while we try. > > > > Signed-off-by: Simon Glass > > Cc: Grant Grundler > > Signed-off-by: Naveen Krishna Chatradhi > > Acked-by: Kyungmin Park > > Applied to for-next, thanks! Do you consider this relevant for stable? signature.asc Description: Digital signature
Re: [PATCH] i2c: s3c2410: do not put a default class for the adapter
On Sat, Feb 15, 2014 at 04:10:39PM +0100, Wolfram Sang wrote: > On Fri, Feb 07, 2014 at 01:59:55PM +0530, Naveen Krishna Chatradhi wrote: > > From: Vincent Palatin > > > > Avoid adding I2C_CLASS_HWMON and I2C_CLASS_SPD class flags to all > > Samsung I2C adapters when the I2C mappings are defined in a device tree. > > So the drivers doing an auto-detection by probing busses won't mess-up > > sensitive I2C devices or trigger long timeouts on non-functional busses. > > > > Signed-off-by: Vincent Palatin > > Reviewed-by: Olof Johansson > > Tested-by: Vincent Palatin > > Reviewed-by: Doug Anderson Your Signed-off was missing BTW. > > I'd prefer to drop it in favour of this series: > > http://lkml.org/lkml/2014/2/10/836 > I'll go ahead and apply my patch. signature.asc Description: Digital signature
Re: [PATCH] i2c-s3c2410: Leave the bus disabled unless it is in use
On Fri, Feb 07, 2014 at 02:24:09PM +0530, Naveen Krishna Chatradhi wrote: > From: Simon Glass > > There is a rather odd feature of the exynos i2c controller that if it > is left enabled, it can lock itself up with the clk line held low. > This makes the bus unusable. > > Unfortunately, the s3c24xx_i2c_set_master() function does not notice > this, and reports a timeout. From then on the bus cannot be used until > the AP is rebooted. > > The problem happens when any sort of interrupt occurs (e.g. due to a > bus transition) when we are not in the middle of a transaction. We > have seen many instances of this when U-Boot leaves the bus apparently > happy, but Linux cannot access it. > > The current code is therefore pretty fragile. > > This fixes things by leaving the bus disabled unless we are actually > in a transaction. We enable the bus at the start of the transaction and > disable it at the end. That way we won't get interrupts and will not > lock up the bus. > > It might be possible to clear pending interrupts on start-up, but this > seems to be a more robust solution. We can't service interrupts when > we are not in a transaction, and anyway would rather not lock up the > bus while we try. > > Signed-off-by: Simon Glass > Cc: Grant Grundler > Signed-off-by: Naveen Krishna Chatradhi > Acked-by: Kyungmin Park Applied to for-next, thanks! signature.asc Description: Digital signature
Re: [PATCH 2/2 v4] i2c: exynos5: configure fifo_depth based on HSI2C module variant
On Fri, Feb 07, 2014 at 10:13:15AM +0530, Naveen Krishna Chatradhi wrote: > fifo_depth of the HSI2C is not constant > Exynos5420 and Exynos5250 supports fifo_depth of 64bytes > Exynos5260 supports fifo_depth of 16bytes. > > This patch configures the fifo_depth based on HSI2C modules version. > > Signed-off-by: Naveen Krishna Chatradhi > [For finding out the difference and initial contribution] > Signed-off-by: Pankaj Dubey I know Tomasz said differently, but I prefer the patches squashed (and the commit message extended). signature.asc Description: Digital signature
Re: [PATCH 1/2 v4] i2c: exynos5: add support for HSI2C on Exynos5260 SoC
On Fri, Feb 07, 2014 at 10:12:51AM +0530, Naveen Krishna Chatradhi wrote:
> This patch adds a new compatible and uses variant struct to support
> HSI2C module on Exynos5260. Updates the Documentation dt bindings.
> Also resets the module as an init sequence (Needed by Exynos5260).
>
> Signed-off-by: Naveen Krishna Chatradhi
This patch has clearly not been tested :( Build failure!
> +struct exynos_hsi2c_variant {
> + unsigned intfifo_depth;
> +};
Why so many tabs? In general, I'd prefer one space.
> - exynos5_i2c_init(i2c);
> + exynos5_i2c_reset(i2c);
Is this a related change?
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How to get the complete reference manual for a samsung exynos5 Soc
Hi, Our team is working on 3 samsung exynos boards (5250/5410/5420), But we were not able to find a reference manual that describes the hardware in detail. As this is the samsung soc mailing list, kindly advice us the means by which we can get a copy of the manual. Regards armdev team-- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/3] ARM: dts: add dts files for xyref5260 board
The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.
Signed-off-by: Rahul Sharma
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 110 +++
2 files changed, 111 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..5a391bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 000..d7d0aeb
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,110 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5260.dtsi"
+
+/ {
+ model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
+ compatible = "samsung,xyref5260", "samsung,exynos5260";
+
+ memory {
+ reg = <0x2000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ xrtcxti: xrtcxti {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xrtcxti";
+ };
+
+ spdif_extclk: ioclk_spdif_extclk {
+ compatible = "fixed-clock";
+ clock-frequency = <49152000>;
+ clock-output-names = "ioclk_spdif_extclk";
+ };
+ };
+};
+
+&pinctrl_0 {
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ supports-hs200-mode; /* 200 Mhz */
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+};
--
1.7.9.5
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[PATCH v5 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Pankaj Dubey
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/Kconfig |4
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 54162ef..69c00ca 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -29,6 +29,7 @@ config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
default y
select SOC_EXYNOS5250
+ select SOC_EXYNOS5260
select SOC_EXYNOS5420
select USB_ARCH_HAS_XHCI
help
@@ -65,6 +66,9 @@ config SOC_EXYNOS4412
config SOC_EXYNOS5250
bool
+config SOC_EXYNOS5260
+ bool
+
config SOC_EXYNOS5420
bool
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 37ea261..790009e 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -51,6 +51,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5260",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
--
1.7.9.5
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[PATCH v5 0/3] exynos: arch: add support for exynos5260 SoC
From: Rahul Sharma V5: 1) Removed SYSRAM related code. 2) Fixed mct clocks. 3) Add SoC and Board specifc fixed-rate clocks in respective files. V4: 1) Removed duplicate MMC Soc property from Board file. V3: 1) Addressed review comments from Tomasz figa. V2: 1) Split up DT patch into SoC and Board patch. This series is dependent on Sachin's patch "ARM: EXYNOS: Consolidate CPU init code" at http://comments.gmane.org/gmane.linux.kernel.samsung-soc/26560 This series is based on Kukjin's for-next branch at http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git Pankaj Dubey (1): ARM: EXYNOS: initial board support for exynos5260 SoC Rahul Sharma (2): ARM: dts: add dts files for exynos5260 SoC ARM: dts: add dts files for xyref5260 board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574 +++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 110 + arch/arm/boot/dts/exynos5260.dtsi | 400 arch/arm/mach-exynos/Kconfig|4 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + 6 files changed, 1090 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 2/3] ARM: dts: add dts files for exynos5260 SoC
The patch adds the dts files for exynos5260.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Signed-off-by: Arun Kumar K
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574 +
arch/arm/boot/dts/exynos5260.dtsi | 400
2 files changed, 974 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 000..f6ee55e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,574 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define PIN_PULL_NONE 0
+#define PIN_PULL_DOWN 1
+#define PIN_PULL_UP3
+
+&pinctrl_0 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-ce
Re: [PATCH V2 1/7] net: sxgbe: add basic framework for Samsung 10Gb ethernet driver
On Wed, Mar 12, 2014 at 01:28:00PM +, Byungho An wrote:
> From: Siva Reddy
>
> This patch adds support for Samsung 10Gb ethernet driver(sxgbe).
>
> - sxgbe core initialization
> - Tx and Rx support
> - MDIO support
> - ISRs for Tx and Rx
> - ifconfig support to driver
>
> Signed-off-by: Siva Reddy Kallam
> Signed-off-by: Vipul Pandya
> Signed-off-by: Girish K S
> Neatening-by: Joe Perches
> Signed-off-by: Byungho An
> ---
[...]
> diff --git a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
> b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
> new file mode 100644
> index 000..f2abf65
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
Please split the binding into a separate patch from the code (it makes
it far easier for us DT guys to find that portions relevant to use).
Is there any public documentation?
> @@ -0,0 +1,39 @@
> +* Samsung 10G Ethernet driver (SXGBE)
> +
> +Required properties:
> +- compatible: Should be "samsung,sxgbe-v2.0a"
> +- reg: Address and length of the register set for the device
> +- interrupt-parent: Should be the phandle for the interrupt controller
> + that services interrupts for this device
> +- interrupts: Should contain the SXGBE interrupts
How many, in which order, what are each of them for?
> +- samsung,burst-mapProgram the possible bursts supported by sxgbe
> +- samsung,fixed-burst Program the DMA to use the fixed burst mode
> +- samsung,adv-addr-modeprogram the DMA to use Enhanced address mode
What are valid values?
Units/types?
Please describe what these actually do.
> +- samsung,force_thresh_dma_modeForce DMA to use the threshold mode
> for
> + both tx and rx
Odd formatting here.
s/_/-/ in property names please.
When and why should this property be set in a dt?
> +- samsung,force_sf_dma_modeForce DMA to use the Store and Forward
> + mode for both tx and rx. This flag is
> + ignored if force_thresh_dma_mode is set.
Likewise, for all points.
[...]
> +/* Clean the tx descriptor as soon as the tx irq is received */
> +static void sxgbe_release_tx_desc(struct sxgbe_tx_norm_desc *p)
> +{
> + memset(p, 0, sizeof(struct sxgbe_tx_norm_desc));
You can use sizeof(*p) here.
[...]
> +static int sxgbe_probe_config_dt(struct platform_device *pdev,
> +struct sxgbe_plat_data *plat,
> +const char **mac)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct sxgbe_dma_cfg *dma_cfg;
> + u32 phy_addr;
> +
> + if (!np)
> + return -ENODEV;
> +
> + *mac = of_get_mac_address(np);
I see that of_get_mac_address returns a *void rather than *char, but
it's always a string of hex digits. Would it make sense to change the
of_get_mac_address prototype to return a char* ?
> + plat->interface = of_get_phy_mode(np);
> +
> + plat->bus_id = of_alias_get_id(np, "ethernet");
> + if (plat->bus_id < 0)
> + plat->bus_id = 0;
This wasn't mentioned in the binding.
> +
> + of_property_read_u32(np, "samsung,phy-addr", &plat->phy_addr);
Neither was this.
> +
> + plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
> + sizeof(struct
> sxgbe_mdio_bus_data),
> + GFP_KERNEL);
> +
> + if (of_device_is_compatible(np, "samsung,sxgbe-v2.0a"))
> + plat->pmt = 1;
Only one compatible string is documented. When would this _not_ be the
case?
[...]
> +static int sxgbe_platform_probe(struct platform_device *pdev)
> +{
> + int ret = 0;
> + int loop = 0;
> + int index1, index2;
> + struct resource *res;
> + struct device *dev = &pdev->dev;
> + void __iomem *addr = NULL;
> + struct sxgbe_priv_data *priv = NULL;
> + struct sxgbe_plat_data *plat_dat = NULL;
> + const char *mac = NULL;
> + int total_dma_channels = SXGBE_TX_QUEUES + SXGBE_RX_QUEUES;
> +
> + /* Get memory resource */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> +
> + addr = devm_ioremap_resource(dev, res);
> + if (IS_ERR(addr))
> + return PTR_ERR(addr);
> +
> + plat_dat = pdev->dev.platform_data;
This is a new dt-driven driver. Why would you need additional platform
data? Why can this information not come from dt?
> + if (pdev->dev.of_node) {
> + if (!plat_dat)
> + plat_dat = devm_kzalloc(&pdev->dev,
> + sizeof(struct
> sxgbe_plat_data),
> + GFP_KERNEL);
> + if (!plat_dat)
> + return -ENOMEM;
> +
> + ret = sxgbe_probe_config_dt(pdev, plat_dat, &mac);
>
[PATCH v5 4/5] clk/exynos5260: add macros and documentation for exynos5260
Add macros which are used as Clock IDs in DT and clock file.
It also adds the documentation for the exynos5260 clocks.
Signed-off-by: Rahul Sharma
---
.../devicetree/bindings/clock/exynos5260-clock.txt | 55 +
include/dt-bindings/clock/exynos5260-clk.h | 233
2 files changed, 288 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 include/dt-bindings/clock/exynos5260-clk.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
new file mode 100644
index 000..4128892
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
@@ -0,0 +1,55 @@
+* Samsung Exynos5260 Clock Controller
+
+The Exynos5260 clock controller encapsulate all CMUs which are
+instantiaited independently from the device-tree. As a whole, these
+CMUs generates and supplies clocks to various controllers within
+the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+ "exynos5260-clock-top"
+ "exynos5260-clock-peri"
+ "exynos5260-clock-egl"
+ "exynos5260-clock-kfc"
+ "exynos5260-clock-g2d"
+ "exynos5260-clock-mif"
+ "exynos5260-clock-mfc"
+ "exynos5260-clock-g3d"
+ "exynos5260-clock-fsys"
+ "exynos5260-clock-aud"
+ "exynos5260-clock-isp"
+ "exynos5260-clock-gscl"
+ "exynos5260-clock-disp"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by each controller. Each
+clock is assigned with a MACRO constant. These constants are defined in
+"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to
+specify the clock, which they want to consume.
+
+Example 1: An example of a clock controller node is listed below.
+
+ cmu_disp: clock-controller@0x1455 {
+ compatible = "exynos5260-clock-disp";
+ reg = <0x1455 0x1>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the
+ peri clock controller. Refer to the standard clock bindings for
+ information about 'clocks' and 'clock-names' property.
+
+ serial@12C0 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 146 0>;
+ clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri
PERI_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
diff --git a/include/dt-bindings/clock/exynos5260-clk.h
b/include/dt-bindings/clock/exynos5260-clk.h
new file mode 100644
index 000..d6f4391
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5260-clk.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/*
+ * Clock names:X_YY_
+ * |---| || |--|
+ * cmu type IP
+ */
+
+/* List Of Clocks For CMU_TOP */
+#define FIN_PLL1
+#define TOP_FOUT_DISP_PLL 2
+#define TOP_FOUT_AUD_PLL 3
+#define TOP_SCLK_MMC0 4
+#define TOP_SCLK_MMC1 5
+#define TOP_SCLK_MMC2 6
+#define TOP_SCLK_HDMIPHY 7
+#define TOP_SCLK_FIMD1 8
+#define TOP_MOUT_FIMD1 9
+#define TOP_MOUT_DISP_PLL 10
+#define TOP_HDMI_PHY_PIXEL_CLKO11
+#define TOP_NR_CLK 12
+
+/* List Of Clocks For CMU_EGL */
+#define EGL_FOUT_EGL_PLL 1
+#define EGL_FOUT_EGL_DPLL 2
+#define EGL_NR_CLK 3
+
+/* List Of Clocks For CMU_KFC */
+#define KFC_FOUT_KFC_PLL 1
+#define KFC_NR_CLK 2
+
+/* List Of Clocks For CMU_MIF */
+#define MIF_FOUT_MEM_PLL 1
+#define MIF_FOUT_BUS_PLL 2
+#define MIF_FOUT_MEDIA_PLL 3
+#define MIF_NR_CLK 4
+
+/* List Of Clocks For CMU_G3D */
+#define G3D_FOUT_G3D_PLL 1
+#define G3D_CLK_G3D_HPM2
+#define G3D_CLK_G3D3
+#define G3D_NR_CLK 4
+
+/* List Of Clocks For CMU_AUD */
+#define AUD_CLK_AUD_UART 1
+#define AUD_CLK_PCM2
+#define AUD_CLK_I2S3
+#define AUD_CLK_DMAC 4
+#define AUD_SCLK_AUD_UART 5
+#define AUD_SCLK_PCM 6
+#define AUD_SCLK_I2S 7
+#define AUD_NR_CLK 8
+
+/* List Of Clocks For CMU_MFC */
+#define MFC_CLK_MFC1
+#define MFC_CLK_SMMU2_MFCM12
+#define MFC_CLK_SMMU2_MFCM03
+#define MFC_NR_CLK
[PATCH v5 3/5] clk/samsung: add support for pll2650xx
Add support for pll2650xx in samsung pll file. This PLL variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma
---
drivers/clk/samsung/clk-pll.c | 101 +
drivers/clk/samsung/clk-pll.h |1 +
2 files changed, 102 insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 18e42ef..b07fad2 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1049,6 +1049,101 @@ static const struct clk_ops
samsung_pll2550xx_clk_min_ops = {
.recalc_rate = samsung_pll2550xx_recalc_rate,
};
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR 3000
+
+#define PLL2650XX_MDIV_SHIFT 9
+#define PLL2650XX_PDIV_SHIFT 3
+#define PLL2650XX_SDIV_SHIFT 0
+#define PLL2650XX_KDIV_SHIFT 0
+#define PLL2650XX_MDIV_MASK0x1ff
+#define PLL2650XX_PDIV_MASK0x3f
+#define PLL2650XX_SDIV_MASK0x7
+#define PLL2650XX_KDIV_MASK0x
+#define PLL2650XX_PLL_ENABLE_SHIFT 23
+#define PLL2650XX_PLL_LOCKTIME_SHIFT 21
+#define PLL2650XX_PLL_FOUTMASK_SHIFT 31
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+ mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+ kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con2;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+
+/* Change PLL PMS values */
+ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+ PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+ PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+ pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+ pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+ pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+ pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+ pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+ << PLL2650XX_KDIV_SHIFT;
+
+ /* Set PLL lock time. */
+ __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+ __raw_writel(pll_con0, pll->con_reg);
+ __raw_writel(pll_con2, pll->con_reg + 8);
+
+ do {
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+ .set_rate = samsung_pll2650xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -1157,6 +1252,12 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
else
init.ops = &samsung_pll2550xx_clk_ops;
break;
+ case pll_2650xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2650xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2650xx_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
in
[PATCH v5 2/5] clk/samsung: add support for pll2550xx
From: Pankaj Dubey
exynos5260 use pll2550xx and it has different bit fields
for P,M,S values as compared to pll2550. Support for
pll2550xx is added here.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Signed-off-by: Arun Kumar K
---
drivers/clk/samsung/clk-pll.c | 108 +
drivers/clk/samsung/clk-pll.h |1 +
2 files changed, 109 insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 1f310be..18e42ef 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -947,6 +947,108 @@ struct clk * __init samsung_clk_register_pll2550x(const
char *name,
return clk;
}
+/*
+ * PLL2550xx Clock Type
+ */
+
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL2550XX_LOCK_FACTOR 270
+
+#define PLL2550XX_M_MASK 0x3FF
+#define PLL2550XX_P_MASK 0x3F
+#define PLL2550XX_S_MASK 0x7
+#define PLL2550XX_LOCK_STAT_MASK 0x1
+#define PLL2550XX_M_SHIFT 9
+#define PLL2550XX_P_SHIFT 3
+#define PLL2550XX_S_SHIFT 0
+#define PLL2550XX_LOCK_STAT_SHIFT 21
+
+static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll->con_reg);
+ mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+ pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+ sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+ old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+
+ return mdiv != old_mdiv || pdiv != old_pdiv;
+}
+
+static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ tmp = __raw_readl(pll->con_reg);
+
+ if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
+ tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
+ __raw_writel(tmp, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+
+ /* Change PLL PMS values */
+ tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
+ (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
+ (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
+ tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
+ (rate->pdiv << PLL2550XX_P_SHIFT) |
+ (rate->sdiv << PLL2550XX_S_SHIFT);
+ __raw_writel(tmp, pll->con_reg);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
+ << PLL2550XX_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2550xx_clk_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll2550xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -1049,6 +1151,12 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
else
init.ops = &samsung_s3c2440_mpll_clk_ops;
break;
+ case pll_2550xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2550xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2550xx_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/drivers/c
[PATCH v5 0/5] clk: exynos: add support for exynos5260 SoC
From: Rahul Sharma
Add clock support for exynos5260 SoC.
This series is based on Tomasz Figa's samsung-next branch.
V5:
1) Include S3c2412 and S3c2443 in clock provider patch.
2) Added SCLK_TOP_FIMD with CLK_IGNORE_UNUSED due to Suspend
failure.
3) Moved exynos5260-clk.h to include/dt-bindings/clock.
4) Fix exynos5260_clk_sleep_init protoype for PM disabled.
5) Moved fixed clock registeration to DT.
6) Removed CLK_IGNORE_UNUSED flags from UART clocks. Earlier
facing issues because of RFS probing all TTYs.
V4:
1) Rework clock file as per Tomasz review comments at
http://www.spinics.net/lists/arm-kernel/msg310116.html.
V3:
1) Removed "samsung,exynos5260-clock" property from clock files.
2) Replaced "__SPIN_LOCK_UNLOCKED(lock)" with spin_lock_init.
3) Removed '(' and ')' around numeric constants in macros.
V2:
1) Move suspend resume handling to Exynos5410 Clock file.
2) Removed Unused Macros and Condition checks for Exynos5260.
3) Add spin lock to clock provider context.
4) Add clock provider context for Exynos5410.
5) Uniform implementation for callbacks for PLL2550xx.
6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
7) Replace aclk/pclk/hclk gates with combined gates.
8) Remove CLK_IGNORE_UNUSED flag for gate clocks.
Pankaj Dubey (1):
clk/samsung: add support for pll2550xx
Rahul Sharma (4):
clk/samsung: add support for multiple clock providers
clk/samsung: add support for pll2650xx
clk/exynos5260: add macros and documentation for exynos5260
clk/exynos5260: add clock file for exynos5260
.../devicetree/bindings/clock/exynos5260-clock.txt | 55 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos4.c | 47 +-
drivers/clk/samsung/clk-exynos5250.c | 25 +-
drivers/clk/samsung/clk-exynos5260.c | 1805
drivers/clk/samsung/clk-exynos5260.h | 448 +
drivers/clk/samsung/clk-exynos5420.c | 24 +-
drivers/clk/samsung/clk-exynos5440.c | 18 +-
drivers/clk/samsung/clk-pll.c | 223 ++-
drivers/clk/samsung/clk-pll.h |2 +
drivers/clk/samsung/clk-s3c2412.c | 29 +-
drivers/clk/samsung/clk-s3c2443.c | 46 +-
drivers/clk/samsung/clk-s3c64xx.c | 44 +-
drivers/clk/samsung/clk.c | 114 +-
drivers/clk/samsung/clk.h | 72 +-
include/dt-bindings/clock/exynos5260-clk.h | 233 +++
16 files changed, 3004 insertions(+), 182 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5260.c
create mode 100644 drivers/clk/samsung/clk-exynos5260.h
create mode 100644 include/dt-bindings/clock/exynos5260-clk.h
--
1.7.9.5
--
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[PATCH v5 1/5] clk/samsung: add support for multiple clock providers
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation, SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.
This layer is modified accordingly to enable the support
for multiple clock providers.
Clock file for exynos4, exynos5250, exynos5420, exynos5440,
S3c64xx, S3c2412 and S3c2443 are also modified as per changed
helper functions.
Signed-off-by: Rahul Sharma
---
drivers/clk/samsung/clk-exynos4.c| 47 +++---
drivers/clk/samsung/clk-exynos5250.c | 25 +---
drivers/clk/samsung/clk-exynos5420.c | 24 ---
drivers/clk/samsung/clk-exynos5440.c | 18 +++---
drivers/clk/samsung/clk-pll.c| 14 +++--
drivers/clk/samsung/clk-s3c2412.c| 29 +
drivers/clk/samsung/clk-s3c2443.c| 46 +++---
drivers/clk/samsung/clk-s3c64xx.c| 44 +++--
drivers/clk/samsung/clk.c| 114 ++
drivers/clk/samsung/clk.h| 72 ++---
10 files changed, 251 insertions(+), 182 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index b4f9672..57ed5a8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1043,7 +1043,7 @@ static unsigned long exynos4_get_xom(void)
return xom;
}
-static void __init exynos4_clk_register_finpll(void)
+static void __init exynos4_clk_register_finpll(struct samsung_clk_provider
*ctx)
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
@@ -1066,7 +1066,7 @@ static void __init exynos4_clk_register_finpll(void)
fclk.parent_name = NULL;
fclk.flags = CLK_IS_ROOT;
fclk.fixed_rate = finpll_f;
- samsung_clk_register_fixed_rate(&fclk, 1);
+ samsung_clk_register_fixed_rate(ctx, &fclk, 1);
}
@@ -1176,22 +1176,25 @@ static struct samsung_pll_clock
exynos4x12_plls[nr_plls] __initdata = {
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
{
+ struct samsung_clk_provider *ctx;
exynos4_soc = soc;
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
- samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
- samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+ samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
- exynos4_clk_register_finpll();
+ exynos4_clk_register_finpll(ctx);
if (exynos4_soc == EXYNOS4210) {
- samsung_clk_register_mux(exynos4210_mux_early,
+ samsung_clk_register_mux(ctx, exynos4210_mux_early,
ARRAY_SIZE(exynos4210_mux_early));
if (_get_rate("fin_pll") == 2400) {
@@ -1205,7 +1208,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4210_plls[vpll].rate_table =
exynos4210_vpll_rates;
- samsung_clk_register_pll(exynos4210_plls,
+ samsung_clk_register_pll(ctx, exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
if (_get_rate("fin_pll") == 2400) {
@@ -1217,42 +1220,42 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4x12_vpll_rates;
}
- samsung_clk_register_pll(exynos4x12_plls,
+ samsung_clk_register_pll(ctx, exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
}
- samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
ARRAY_SIZE(exynos4_fixed_rate_clks));
- samsung_clk_register_mux(exynos4_mux_clks,
+ samsung_clk_register_mux(ctx, exynos4_mux_clks,
ARRAY_SIZE(exynos4_mux_clks));
- samsung_clk_register_div(exynos4_div_clks,
+ samsung_clk_register_div(ctx, exynos4_div_clks,
ARRAY_SIZE(exynos4_div_clks));
- samsung_clk_register_gate(exynos4_gate_clks,
+ samsung_clk_register_gate(ctx, exynos4_gate_clks,
ARRAY_SIZE(exynos4_gate_clks));
if (exynos4_soc == EXYNOS4210) {
- samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
Re: [PATCH V2 0/7] add new Samsung sxgbe driver
On Wed, 2014-03-12 at 22:27 +0900, Byungho An wrote: > Hi all, [] > drivers/net/ethernet/samsung/sxgbe_main.c | 2447 > The patch set is word wrapped and can not be applied. Please resend without the word wrapping. Using Outlook can make this difficult. If possible, use git send-email. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 7/7] MAINTAINERS: add maintainer for Samsung sxgbe driver
From: Byungho An Signed-off-by: Byungho An --- MAINTAINERS |9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b2cf5cf..d4ce0a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7497,6 +7497,15 @@ S: Supported L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) F: drivers/clk/samsung/ +SAMSUNG SXGBE DRIVERS +M: Byungho An +M: Girish K S +M: Siva Reddy Kallam +M: Vipul Pandya +S: Supported +L: net...@vger.kernel.org +F: drivers/net/ethernet/samsung/ + SERIAL DRIVERS M: Greg Kroah-Hartman L: linux-ser...@vger.kernel.org -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 4/7] net: sxgbe: add Checksum offload support for Samsung sxgbe
From: Vipul Pandya
This patch adds TX and RX checksum offload support.
Signed-off-by: Vipul Pandya
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h |6 +++-
drivers/net/ethernet/samsung/sxgbe_core.c | 20
drivers/net/ethernet/samsung/sxgbe_desc.c | 27
drivers/net/ethernet/samsung/sxgbe_desc.h |6 ++--
drivers/net/ethernet/samsung/sxgbe_main.c | 46
---
5 files changed, 84 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index 1d848ce..39e21b6 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -351,6 +351,10 @@ struct sxgbe_core_ops {
void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
const int tw);
void (*set_eee_pls)(void __iomem *ioaddr, const int link);
+
+ /* Enable disable checksum offload operations */
+ void (*enable_rx_csum)(void __iomem *ioaddr);
+ void (*disable_rx_csum)(void __iomem *ioaddr);
};
const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
@@ -466,7 +470,7 @@ struct sxgbe_priv_data {
struct net_device *dev;
struct device *device;
struct sxgbe_ops *hw;/* sxgbe specific ops */
- int no_csum_insertion;
+ int rxcsum_insertion;
spinlock_t lock;
spinlock_t stats_lock;
diff --git a/drivers/net/ethernet/samsung/sxgbe_core.c
b/drivers/net/ethernet/samsung/sxgbe_core.c
index 3c4058d..b5a53c7 100644
--- a/drivers/net/ethernet/samsung/sxgbe_core.c
+++ b/drivers/net/ethernet/samsung/sxgbe_core.c
@@ -217,6 +217,24 @@ static void sxgbe_set_eee_timer(void __iomem *ioaddr,
writel(value, ioaddr + SXGBE_CORE_LPI_TIMER_CTRL);
}
+static void sxgbe_enable_rx_csum(void __iomem *ioaddr)
+{
+ u32 ctrl;
+
+ ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+ ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE;
+ writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+}
+
+static void sxgbe_disable_rx_csum(void __iomem *ioaddr)
+{
+ u32 ctrl;
+
+ ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+ ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE;
+ writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+}
+
const struct sxgbe_core_ops core_ops = {
.core_init = sxgbe_core_init,
.dump_regs = sxgbe_core_dump_regs,
@@ -233,6 +251,8 @@ const struct sxgbe_core_ops core_ops = {
.reset_eee_mode = sxgbe_reset_eee_mode,
.set_eee_timer = sxgbe_set_eee_timer,
.set_eee_pls = sxgbe_set_eee_pls,
+ .enable_rx_csum = sxgbe_enable_rx_csum,
+ .disable_rx_csum = sxgbe_disable_rx_csum,
};
const struct sxgbe_core_ops *sxgbe_get_core_ops(void)
diff --git a/drivers/net/ethernet/samsung/sxgbe_desc.c
b/drivers/net/ethernet/samsung/sxgbe_desc.c
index f223eb5..45e6676 100644
--- a/drivers/net/ethernet/samsung/sxgbe_desc.c
+++ b/drivers/net/ethernet/samsung/sxgbe_desc.c
@@ -47,6 +47,9 @@ static void sxgbe_prepare_tx_desc(struct
sxgbe_tx_norm_desc *p, u8 is_fd,
p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.total_pkt_len =
pkt_len;
+ if (cksum)
+ p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.cksum_ctl =
+ cic_full;
}
/* Set VLAN control information */
@@ -250,31 +253,40 @@ static int sxgbe_get_rx_ld_status(struct
sxgbe_rx_norm_desc *p)
/* Return the RX status looking at the WB fields */
-static void sxgbe_rx_wbstatus(struct sxgbe_rx_norm_desc *p,
- struct sxgbe_extra_stats *x)
+static int sxgbe_rx_wbstatus(struct sxgbe_rx_norm_desc *p,
+struct sxgbe_extra_stats *x, int *checksum)
{
+ int status = 0;
+ *checksum = CHECKSUM_UNNECESSARY;
if (p->rdes23.rx_wb_des23.err_summary) {
switch (p->rdes23.rx_wb_des23.err_l2_type) {
case RX_GMII_ERR:
+ status = -EINVAL;
x->rx_code_gmii_err++;
break;
case RX_WATCHDOG_ERR:
+ status = -EINVAL;
x->rx_watchdog_err++;
break;
case RX_CRC_ERR:
+ status = -EINVAL;
x->rx_crc_err++;
break;
case RX_GAINT_ERR:
+ status = -EINVAL;
x->rx_gaint_pkt_err++;
break;
case RX_IP_HDR_ERR:
+ *checksum = CHECKSUM_NONE;
x->ip_hdr_err++;
break;
case RX_PAYLOAD_ERR:
+ *checksum = CHECKSUM_NONE;
x->ip_payload_err++;
break;
case RX_OVERFLOW_ERR:
+ status = -EINVAL;
[PATCH V2 6/7] net: sxgbe: add ethtool related functions support Samsung sxgbe
From: Vipul Pandya
This patch adds ethtool related functions.
Signed-off-by: Vipul Pandya
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h | 28 +-
drivers/net/ethernet/samsung/sxgbe_ethtool.c | 509
+-
drivers/net/ethernet/samsung/sxgbe_main.c| 14 +-
drivers/net/ethernet/samsung/sxgbe_reg.h |6 +
4 files changed, 538 insertions(+), 19 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index d01cab0..47721b6 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -42,8 +42,12 @@ struct sxgbe_mtl_ops;
#define SXGBE_RX_QUEUES 16
/* Max/Min RI Watchdog Timer count value */
-#define SXGBE_MAX_DMA_RIWT 0xff
-#define SXGBE_MIN_DMA_RIWT 0x20
+/* Calculated based how much time does it take to fill 256KB Rx memory
+ * at 10Gb speed at 156MHz clock rate and considered little less then
+ * the actual value.
+ */
+#define SXGBE_MAX_DMA_RIWT 0x70
+#define SXGBE_MIN_DMA_RIWT 0x01
/* Tx coalesce parameters */
#define SXGBE_COAL_TX_TIMER4
@@ -206,6 +210,20 @@ enum dma_irq_status {
#define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num)\
for (queue_num = 0; queue_num < max_queues; queue_num++)
+#define DRV_VERSION "1.0.0"
+
+#define SXGBE_MAX_RX_CHANNELS 16
+#define SXGBE_MAX_TX_CHANNELS 16
+
+#define START_MAC_REG_OFFSET 0x
+#define MAX_MAC_REG_OFFSET 0x0DFC
+#define START_MTL_REG_OFFSET 0x1000
+#define MAX_MTL_REG_OFFSET 0x18FC
+#define START_DMA_REG_OFFSET 0x3000
+#define MAX_DMA_REG_OFFSET 0x38FC
+
+#define REG_SPACE_SIZE 0x2000
+
/* sxgbe statistics counters */
struct sxgbe_extra_stats {
/* TX/RX IRQ events */
@@ -488,7 +506,8 @@ struct sxgbe_priv_data {
int oldlink;
int speed;
int oldduplex;
- unsigned int flow_ctrl;
+ u8 rx_pause;
+ u8 tx_pause;
unsigned int pause;
struct mii_bus *mii;
int mii_irq[PHY_MAX_ADDR];
@@ -508,6 +527,7 @@ struct sxgbe_priv_data {
u32 adv_ts;
int use_riwt;
spinlock_t ptp_lock;
+ struct ptp_clock *ptp_clock;
/* EEE-LPI specific members */
struct timer_list eee_ctrl_timer;
@@ -546,4 +566,6 @@ const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv);
bool sxgbe_eee_init(struct sxgbe_priv_data * const priv);
+int sxgbe_set_flow_ctrl(struct sxgbe_priv_data *priv, int rx, int tx);
+
#endif /* __SXGBE_COMMON_H__ */
diff --git a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
index b3b5180..46198bf 100644
--- a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
+++ b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
@@ -12,12 +12,17 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include
#include
#include
#include
+#include
#include
+#include
#include "sxgbe_common.h"
+#include "sxgbe_reg.h"
+#include "sxgbe_dma.h"
struct sxgbe_stats {
char stat_string[ETH_GSTRING_LEN];
@@ -33,17 +38,106 @@ struct sxgbe_stats {
}
static const struct sxgbe_stats sxgbe_gstrings_stats[] = {
+ /* TX/RX IRQ events */
+ SXGBE_STAT(tx_process_stopped_irq),
+ SXGBE_STAT(tx_ctxt_desc_err),
+ SXGBE_STAT(tx_threshold),
+ SXGBE_STAT(rx_threshold),
+ SXGBE_STAT(tx_pkt_n),
+ SXGBE_STAT(rx_pkt_n),
+ SXGBE_STAT(normal_irq_n),
+ SXGBE_STAT(tx_normal_irq_n),
+ SXGBE_STAT(rx_normal_irq_n),
+ SXGBE_STAT(napi_poll),
+ SXGBE_STAT(tx_clean),
+ SXGBE_STAT(tx_reset_ic_bit),
+ SXGBE_STAT(rx_process_stopped_irq),
+ SXGBE_STAT(rx_underflow_irq),
+
+ /* Bus access errors */
+ SXGBE_STAT(fatal_bus_error_irq),
+ SXGBE_STAT(tx_read_transfer_err),
+ SXGBE_STAT(tx_write_transfer_err),
+ SXGBE_STAT(tx_desc_access_err),
+ SXGBE_STAT(tx_buffer_access_err),
+ SXGBE_STAT(tx_data_transfer_err),
+ SXGBE_STAT(rx_read_transfer_err),
+ SXGBE_STAT(rx_write_transfer_err),
+ SXGBE_STAT(rx_desc_access_err),
+ SXGBE_STAT(rx_buffer_access_err),
+ SXGBE_STAT(rx_data_transfer_err),
+ SXGBE_STAT(pmt_irq_event_n),
+
+ /* EEE-LPI stats */
SXGBE_STAT(tx_lpi_entry_n),
SXGBE_STAT(tx_lpi_exit_n),
SXGBE_STAT(rx_lpi_entry_n),
SXGBE_STAT(rx_lpi_exit_n),
SXGBE_STAT(eee_wakeup_error_n),
- SXGBE_STAT(pmt_irq_event_n),
+
+ /* RX specific */
+ /* L2 error */
+ SXGBE_STAT(rx_code_gmii_err),
+ SXGBE_STAT(rx_watchdog_err),
+ SXGBE_STAT(rx_crc_err),
+ SXGBE_STAT(rx_gaint_pkt_err),
+ SXGBE_STAT(ip_hdr_err),
+ SXGBE_STAT(ip_payload_err),
+ SXGBE_STAT(overflow_error),
+
+ /* L2 Pkt type */
+ SXGBE_STAT(len_pkt),
+ SXGBE_STAT(mac_ctl_pkt),
+
[PATCH V2 3/7] net: sxgbe: add EEE(Energy Efficient Ethernet) for Samsung sxgbe
From: Girish K S
Added support for the EEE(Energy Efficient Ethernet)in 10G ethernet driver.
Signed-off-by: Girish K S
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h | 54 +
drivers/net/ethernet/samsung/sxgbe_core.c | 86 +-
drivers/net/ethernet/samsung/sxgbe_ethtool.c | 47
drivers/net/ethernet/samsung/sxgbe_main.c | 152
-
drivers/net/ethernet/samsung/sxgbe_platform.c |4 +
drivers/net/ethernet/samsung/sxgbe_reg.h |5 +
6 files changed, 346 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index 5ebf6bd..1d848ce 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -118,6 +118,33 @@ struct sxgbe_mtl_ops;
#define RX_PTP_SIGNAL 0x0A
#define RX_PTP_RESV_MSG0x0F
+/* EEE-LPI mode flags*/
+#define TX_ENTRY_LPI_MODE 0x10
+#define TX_EXIT_LPI_MODE 0x20
+#define RX_ENTRY_LPI_MODE 0x40
+#define RX_EXIT_LPI_MODE 0x80
+
+/* EEE-LPI Interrupt status flag */
+#define LPI_INT_STATUS BIT(5)
+
+/* EEE-LPI Default timer values */
+#define LPI_LINK_STATUS_TIMER 0x3E8
+#define LPI_MAC_WAIT_TIMER 0x00
+
+/* EEE-LPI Control and status definitions */
+#define LPI_CTRL_STATUS_TXABIT(19)
+#define LPI_CTRL_STATUS_PLSDIS BIT(18)
+#define LPI_CTRL_STATUS_PLSBIT(17)
+#define LPI_CTRL_STATUS_LPIEN BIT(16)
+#define LPI_CTRL_STATUS_TXRSTP BIT(11)
+#define LPI_CTRL_STATUS_RXRSTP BIT(10)
+#define LPI_CTRL_STATUS_RLPIST BIT(9)
+#define LPI_CTRL_STATUS_TLPIST BIT(8)
+#define LPI_CTRL_STATUS_RLPIEX BIT(3)
+#define LPI_CTRL_STATUS_RLPIEN BIT(2)
+#define LPI_CTRL_STATUS_TLPIEX BIT(1)
+#define LPI_CTRL_STATUS_TLPIEN BIT(0)
+
enum dma_irq_status {
tx_hard_error = BIT(0),
tx_bump_tc = BIT(1),
@@ -202,6 +229,13 @@ struct sxgbe_extra_stats {
unsigned long rx_buffer_access_err;
unsigned long rx_data_transfer_err;
+ /* EEE-LPI stats */
+ unsigned long tx_lpi_entry_n;
+ unsigned long tx_lpi_exit_n;
+ unsigned long rx_lpi_entry_n;
+ unsigned long rx_lpi_exit_n;
+ unsigned long eee_wakeup_error_n;
+
/* RX specific */
/* L2 error */
unsigned long rx_code_gmii_err;
@@ -310,6 +344,13 @@ struct sxgbe_core_ops {
unsigned char feature_index);
/* adjust SXGBE speed */
void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
+
+ /* EEE-LPI specific operations */
+ void (*set_eee_mode)(void __iomem *ioaddr);
+ void (*reset_eee_mode)(void __iomem *ioaddr);
+ void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
+ const int tw);
+ void (*set_eee_pls)(void __iomem *ioaddr, const int link);
};
const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
@@ -371,6 +412,8 @@ struct sxgbe_hw_features {
/* IEEE 1588-2008 */
unsigned int atime_stamp;
+ unsigned int eee;
+
unsigned int tx_csum_offload;
unsigned int rx_csum_offload;
unsigned int multi_macaddr;
@@ -451,6 +494,14 @@ struct sxgbe_priv_data {
u32 adv_ts;
int use_riwt;
spinlock_t ptp_lock;
+
+ /* EEE-LPI specific members */
+ struct timer_list eee_ctrl_timer;
+ bool tx_path_in_lpi_mode;
+ int lpi_irq;
+ int eee_enabled;
+ int eee_active;
+ int tx_lpi_timer;
};
/* Function prototypes */
@@ -473,4 +524,7 @@ int sxgbe_restore(struct net_device *ndev);
const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
+void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv);
+bool sxgbe_eee_init(struct sxgbe_priv_data * const priv);
+
#endif /* __SXGBE_COMMON_H__ */
diff --git a/drivers/net/ethernet/samsung/sxgbe_core.c
b/drivers/net/ethernet/samsung/sxgbe_core.c
index 6b115b1..3c4058d 100644
--- a/drivers/net/ethernet/samsung/sxgbe_core.c
+++ b/drivers/net/ethernet/samsung/sxgbe_core.c
@@ -47,11 +47,38 @@ static void sxgbe_core_dump_regs(void __iomem *ioaddr)
{
}
+static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status)
+{
+ int status = 0;
+ int lpi_status;
+
+ /* Reading this register shall clear all the LPI status bits */
+ lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
+
+ if (lpi_status & LPI_CTRL_STATUS_TLPIEN)
+ status |= TX_ENTRY_LPI_MODE;
+ if (lpi_status & LPI_CTRL_STATUS_TLPIEX)
+ status |= TX_EXIT_LPI_MODE;
+ if (lpi_status & LPI_CTRL_STATUS_RLPIEN)
+ status |= RX_ENTRY_LPI_MODE;
+ if (lpi_status & LPI_CTRL_STATUS_RLPIEX)
+ status |= RX_EXIT_LPI_MODE;
+
+ return status;
+}
+
/* Handle extra events on specific interrupts hw dependent */
static int sxgbe_core_host_irq_status(void __
[PATCH V2 5/7] net: sxgbe: add WOL(Wakeup-On-Lan)support for Samsung sxgbe
From: Girish K S
This patch adds support for wake up on magic frame arrival.
Also remote wake up on all other packets (unicast, multicast broadcast) is
supported.
Signed-off-by: Girish K S
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_common.h | 15 ++
drivers/net/ethernet/samsung/sxgbe_core.c | 29 ++
drivers/net/ethernet/samsung/sxgbe_ethtool.c | 47
drivers/net/ethernet/samsung/sxgbe_main.c | 71
+
drivers/net/ethernet/samsung/sxgbe_mtl.c | 43 ++-
drivers/net/ethernet/samsung/sxgbe_mtl.h |4 ++
drivers/net/ethernet/samsung/sxgbe_platform.c |4 ++
drivers/net/ethernet/samsung/sxgbe_reg.h |3 ++
8 files changed, 215 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_common.h
b/drivers/net/ethernet/samsung/sxgbe_common.h
index 39e21b6..d01cab0 100644
--- a/drivers/net/ethernet/samsung/sxgbe_common.h
+++ b/drivers/net/ethernet/samsung/sxgbe_common.h
@@ -124,9 +124,18 @@ struct sxgbe_mtl_ops;
#define RX_ENTRY_LPI_MODE 0x40
#define RX_EXIT_LPI_MODE 0x80
+/* PMT mode bits */
+#define PMT_PWRDWN BIT(0)
+#define PMT_MGPKT_EN BIT(1)
+#define PMT_RWKPKT_EN BIT(2)
+#define PMT_GUCAST_EN BIT(9)
+
/* EEE-LPI Interrupt status flag */
#define LPI_INT_STATUS BIT(5)
+/* PMT Interrupt status */
+#define PMT_INT_STATUS BIT(4)
+
/* EEE-LPI Default timer values */
#define LPI_LINK_STATUS_TIMER 0x3E8
#define LPI_MAC_WAIT_TIMER 0x00
@@ -228,6 +237,7 @@ struct sxgbe_extra_stats {
unsigned long rx_desc_access_err;
unsigned long rx_buffer_access_err;
unsigned long rx_data_transfer_err;
+ unsigned long pmt_irq_event_n;
/* EEE-LPI stats */
unsigned long tx_lpi_entry_n;
@@ -506,6 +516,11 @@ struct sxgbe_priv_data {
int eee_enabled;
int eee_active;
int tx_lpi_timer;
+
+ /* PM-WOL specific members */
+ int wolopts;
+ int wolenabled;
+ int wol_irq;
};
/* Function prototypes */
diff --git a/drivers/net/ethernet/samsung/sxgbe_core.c
b/drivers/net/ethernet/samsung/sxgbe_core.c
index b5a53c7..2a239d1 100644
--- a/drivers/net/ethernet/samsung/sxgbe_core.c
+++ b/drivers/net/ethernet/samsung/sxgbe_core.c
@@ -78,12 +78,41 @@ static int sxgbe_core_host_irq_status(void __iomem
*ioaddr,
if (unlikely(irq_status & LPI_INT_STATUS))
status |= sxgbe_get_lpi_status(ioaddr, irq_status);
+ if (unlikely(irq_status & PMT_INT_STATUS)) {
+ /* clear the PMT bits 5 and 6 by reading the PMT status reg
*/
+ readl(ioaddr + SXGBE_CORE_PMT_CTL_STATUS_REG);
+ x->pmt_irq_event_n++;
+ }
+
return status;
}
/* Set power management mode (e.g. magic frame) */
static void sxgbe_core_pmt(void __iomem *ioaddr, unsigned long mode)
{
+ unsigned int pmt = 0;
+
+ if (mode & WAKE_MAGIC) {
+ pr_debug("WOL Magic frame\n");
+ pmt |= PMT_MGPKT_EN;
+ }
+ if (mode & WAKE_UCAST) {
+ pr_debug("WOL on global unicast\n");
+ pmt |= PMT_GUCAST_EN;
+ }
+ if (mode & (WAKE_MCAST | WAKE_BCAST)) {
+ pr_debug("WOL on any other packet\n");
+ pmt |= PMT_RWKPKT_EN;
+ }
+
+ writel(pmt, ioaddr + SXGBE_CORE_PMT_CTL_STATUS_REG);
+
+ /* Enable power down bit if any of the requested mode is enabled */
+ if (pmt) {
+ writel(SXGBE_RX_ENABLE, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
+ pmt |= PMT_PWRDWN;
+ writel(pmt, ioaddr + SXGBE_CORE_PMT_CTL_STATUS_REG);
+ }
}
/* Set/Get Unicast MAC addresses */
diff --git a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
index bf692e3..b3b5180 100644
--- a/drivers/net/ethernet/samsung/sxgbe_ethtool.c
+++ b/drivers/net/ethernet/samsung/sxgbe_ethtool.c
@@ -12,6 +12,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include
#include
#include
#include
@@ -37,6 +38,7 @@ static const struct sxgbe_stats sxgbe_gstrings_stats[] = {
SXGBE_STAT(rx_lpi_entry_n),
SXGBE_STAT(rx_lpi_exit_n),
SXGBE_STAT(eee_wakeup_error_n),
+ SXGBE_STAT(pmt_irq_event_n),
};
#define SXGBE_STATS_LEN ARRAY_SIZE(sxgbe_gstrings_stats)
@@ -80,9 +82,54 @@ static int sxgbe_ethtool_set_eee(struct net_device *dev,
return phy_ethtool_set_eee(priv->phydev, edata);
}
+static void sxgbe_get_wol(struct net_device *dev, struct ethtool_wolinfo
*wol)
+{
+ struct sxgbe_priv_data *priv = netdev_priv(dev);
+
+ wol->wolopts = 0;
+ if (!device_can_wakeup(priv->device)) {
+ dev_err(priv->device, "cannot wakeup device\n");
+ return;
+ }
+
+ if (priv->hw_cap.pmt_magic_frame)
+ wol->supported |= WAKE_MAGIC;
+
+
[PATCH V2 2/7] net: sxgbe: add TSO support for Samsung sxgbe
From: Vipul Pandya
Enable TSO during initialization for each DMA channels
Signed-off-by: Vipul Pandya
Neatening-by: Joe Perches
Signed-off-by: Byungho An
---
drivers/net/ethernet/samsung/sxgbe_desc.c | 47 +++---
drivers/net/ethernet/samsung/sxgbe_desc.h | 17 +--
drivers/net/ethernet/samsung/sxgbe_dma.c | 10
drivers/net/ethernet/samsung/sxgbe_dma.h |2 +
drivers/net/ethernet/samsung/sxgbe_main.c | 75
++---
5 files changed, 130 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/samsung/sxgbe_desc.c
b/drivers/net/ethernet/samsung/sxgbe_desc.c
index 7577375..f223eb5 100644
--- a/drivers/net/ethernet/samsung/sxgbe_desc.c
+++ b/drivers/net/ethernet/samsung/sxgbe_desc.c
@@ -28,6 +28,16 @@ static void sxgbe_init_tx_desc(struct sxgbe_tx_norm_desc
*p)
p->tdes23.tx_rd_des23.own_bit = 0;
}
+static void sxgbe_tx_desc_enable_tse(struct sxgbe_tx_norm_desc *p, u8
is_tse,
+u32 total_hdr_len, u32 tcp_hdr_len,
+u32 tcp_payload_len)
+{
+ p->tdes23.tx_rd_des23.tse_bit = is_tse;
+ p->tdes23.tx_rd_des23.buf1_size = total_hdr_len;
+ p->tdes23.tx_rd_des23.tcp_hdr_len = tcp_hdr_len / 4;
+ p->tdes23.tx_rd_des23.tx_pkt_len.tcp_payload_len = tcp_payload_len;
+}
+
/* Assign buffer lengths for descriptor */
static void sxgbe_prepare_tx_desc(struct sxgbe_tx_norm_desc *p, u8 is_fd,
int buf1_len, int pkt_len, int cksum)
@@ -102,36 +112,47 @@ static int sxgbe_get_tx_timestamp_status(struct
sxgbe_tx_norm_desc *p)
}
/* TX Context Descripto Specific */
-static void sxgbe_init_tx_ctxtdesc(struct sxgbe_tx_ctxt_desc *p)
+static void sxgbe_tx_ctxt_desc_set_ctxt(struct sxgbe_tx_ctxt_desc *p)
{
p->ctxt_bit = 1;
- p->own_bit = 0;
}
/* Set the owner of TX context descriptor */
-static void sxgbe_set_tx_ctxt_owner(struct sxgbe_tx_ctxt_desc *p)
+static void sxgbe_tx_ctxt_desc_set_owner(struct sxgbe_tx_ctxt_desc *p)
{
p->own_bit = 1;
}
/* Get the owner of TX context descriptor */
-static int sxgbe_get_tx_ctxt_owner(struct sxgbe_tx_ctxt_desc *p)
+static int sxgbe_tx_ctxt_desc_get_owner(struct sxgbe_tx_ctxt_desc *p)
{
return p->own_bit;
}
/* Set TX mss in TX context Descriptor */
-static void sxgbe_tx_ctxt_desc_setmss(struct sxgbe_tx_ctxt_desc *p, int
mss)
+static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, u16
mss)
{
p->maxseg_size = mss;
}
/* Get TX mss from TX context Descriptor */
-static int sxgbe_tx_ctxt_desc_getmss(struct sxgbe_tx_ctxt_desc *p)
+static int sxgbe_tx_ctxt_desc_get_mss(struct sxgbe_tx_ctxt_desc *p)
{
return p->maxseg_size;
}
+/* Set TX tcmssv in TX context Descriptor */
+static void sxgbe_tx_ctxt_desc_set_tcmssv(struct sxgbe_tx_ctxt_desc *p)
+{
+ p->tcmssv = 1;
+}
+
+/* Reset TX ostc in TX context Descriptor */
+static void sxgbe_tx_ctxt_desc_reset_ostc(struct sxgbe_tx_ctxt_desc *p)
+{
+ p->ostc = 0;
+}
+
/* Set IVLAN information */
static void sxgbe_tx_ctxt_desc_set_ivlantag(struct sxgbe_tx_ctxt_desc *p,
int is_ivlanvalid, int
ivlan_tag,
@@ -177,13 +198,13 @@ static void sxgbe_tx_ctxt_desc_set_tstamp(struct
sxgbe_tx_ctxt_desc *p,
}
}
/* Close TX context descriptor */
-static void sxgbe_close_tx_ctxt_desc(struct sxgbe_tx_ctxt_desc *p)
+static void sxgbe_tx_ctxt_desc_close(struct sxgbe_tx_ctxt_desc *p)
{
p->own_bit = 1;
}
/* WB status of context descriptor */
-static int sxgbe_get_tx_ctxt_cde(struct sxgbe_tx_ctxt_desc *p)
+static int sxgbe_tx_ctxt_desc_get_cde(struct sxgbe_tx_ctxt_desc *p)
{
return p->ctxt_desc_err;
}
@@ -432,6 +453,7 @@ static u64 sxgbe_get_rx_timestamp(struct
sxgbe_rx_ctxt_desc *p)
static const struct sxgbe_desc_ops desc_ops = {
.init_tx_desc = sxgbe_init_tx_desc,
+ .tx_desc_enable_tse = sxgbe_tx_desc_enable_tse,
.prepare_tx_desc = sxgbe_prepare_tx_desc,
.tx_vlanctl_desc = sxgbe_tx_vlanctl_desc,
.set_tx_owner = sxgbe_set_tx_owner,
@@ -443,11 +465,20 @@ static const struct sxgbe_desc_ops desc_ops = {
.get_tx_len = sxgbe_get_tx_len,
.tx_enable_tstamp = sxgbe_tx_enable_tstamp,
.get_tx_timestamp_status = sxgbe_get_tx_timestamp_status,
+ .tx_ctxt_desc_set_ctxt = sxgbe_tx_ctxt_desc_set_ctxt,
+ .tx_ctxt_desc_set_owner = sxgbe_tx_ctxt_desc_set_owner,
+ .get_tx_ctxt_owner = sxgbe_tx_ctxt_desc_get_owner,
+ .tx_ctxt_desc_set_mss = sxgbe_tx_ctxt_desc_set_mss,
+ .tx_ctxt_desc_get_mss = sxgbe_tx_ctxt_desc_get_mss,
+ .tx_ctxt_desc_set_tcmssv = sxgbe_tx_ctxt_desc_set_tcmssv,
+ .tx_ctxt_desc_reset_ostc = sxgbe_tx_ctxt_desc_reset_ostc,
.tx_ctxt_desc_set_ivlantag = sxgbe_tx_ctxt_desc_set_ivlantag,
.tx_ctxt_desc_get_ivlantag = sxgbe_tx_ctxt_desc_get_ivlantag,
.tx_ctxt_desc_set_vlantag = sxgbe_tx_ctxt_des
[PATCH V2 0/7] add new Samsung sxgbe driver
Hi all, This series adds Samsung sxgbe driver. Byungho An (1): MAINTAINERS: add maintainer for Samsung sxgbe driver Girish K S (2): net: sxgbe: add EEE(Energy Efficient Ethernet) for Samsung sxgbe net: sxgbe: add WOL(Wakeup-On-Lan)support for Samsung sxgbe Siva Reddy (1): net: sxgbe: add basic framework for Samsung 10Gb ethernet driver Vipul Pandya (3): net: sxgbe: add TSO support for Samsung sxgbe net: sxgbe: add Checksum offload support for Samsung sxgbe net: sxgbe: add ethtool related functions support Samsung sxgbe .../devicetree/bindings/net/samsung-sxgbe.txt | 39 + MAINTAINERS|9 + drivers/net/ethernet/Kconfig |1 + drivers/net/ethernet/Makefile |1 + drivers/net/ethernet/samsung/Kconfig |7 + drivers/net/ethernet/samsung/Makefile |4 + drivers/net/ethernet/samsung/sxgbe_common.h| 571 + drivers/net/ethernet/samsung/sxgbe_core.c | 290 +++ drivers/net/ethernet/samsung/sxgbe_desc.c | 515 drivers/net/ethernet/samsung/sxgbe_desc.h | 298 +++ drivers/net/ethernet/samsung/sxgbe_dma.c | 381 +++ drivers/net/ethernet/samsung/sxgbe_dma.h | 51 + drivers/net/ethernet/samsung/sxgbe_ethtool.c | 628 + drivers/net/ethernet/samsung/sxgbe_main.c | 2447 drivers/net/ethernet/samsung/sxgbe_mdio.c | 274 +++ drivers/net/ethernet/samsung/sxgbe_mtl.c | 279 +++ drivers/net/ethernet/samsung/sxgbe_mtl.h | 108 + drivers/net/ethernet/samsung/sxgbe_platform.c | 272 +++ drivers/net/ethernet/samsung/sxgbe_reg.h | 491 drivers/net/ethernet/samsung/sxgbe_xpcs.c | 92 + drivers/net/ethernet/samsung/sxgbe_xpcs.h | 38 + include/linux/sxgbe_platform.h | 54 + 22 files changed, 6850 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 0/5] ARM: dts: exynos: Add missing dt data to bring kernel of Exynos4x12
Hi Tomasz, On 03/12/2014 08:21 PM, Tomasz Figa wrote: > Hi Chanwoo, > > On 12.03.2014 07:19, Chanwoo Choi wrote: >> This patch add missing dt data of Exynos4x12 to bring up kernel feature and >> code clean. This patchset is based on 'v3.15-next/dt-clk-exynos' branch. >> - git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git >> >> exynos4x12/exynos4412/exynos4212.dtsi >> - Add ADC (Analog and Digital Converter) to get raw data >> - Add PMU (Performance Monitoring Unit) for perf event >> - Add gps_alive power domain to remove power leakage when gps-alive isn't >> used >> - Remove duplicate dt data of interrput combiner controller >> >> exynos4412-trats.dts >> - Add ADC dt data with ntc thermistor child to read temperature >> >> Changes from v1: >> - Use clock macro name for Exynos4 instead of constant for ADC >> - Remove unnecessary description about patch content >> - Move gps-alive power domain's dt data from exynos4x12.dts to exynos4.dts >> - Move thermistor dt node outside of ADC dt node and modify node name of >> thermistor >> >> Chanwoo Choi (5): >>ARM: dts: exynos4x12: Add ADC's dt data to read raw data >>ARM: dts: exynos4x12: Add PMU dt data to support PMU(Perforamnce >> Monitoring Unit) >>ARM: dts: exynos4x12: Add GPS_ALIVE power domain >>ARM: dts: exynos: Move common dt data for interrupt combiner controller >>ARM: dts: exynos4412-trats2: Add ADC/themistor dt data to get temperature >> of SoC/battery >> >> arch/arm/boot/dts/exynos4.dtsi | 5 + >> arch/arm/boot/dts/exynos4212.dtsi | 13 - >> arch/arm/boot/dts/exynos4412-trats2.dts | 21 + >> arch/arm/boot/dts/exynos4412.dtsi | 14 -- >> arch/arm/boot/dts/exynos4x12.dtsi | 26 ++ >> 5 files changed, 60 insertions(+), 19 deletions(-) >> > > Reviewed-by: Tomasz Figa > Thanks for your review. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: s2mps11: Add support for S2MPS14 clocks
On Wed, 2014-03-12 at 17:00 +0530, Yadwinder Singh Brar wrote:
> On Mon, Mar 10, 2014 at 6:04 PM, Krzysztof Kozlowski
> wrote:
> > This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the
> > s2mps11 clock driver.
> >
> > Signed-off-by: Krzysztof Kozlowski
> > ---
>
> Reviewed-by: Yadwinder Singh Brar
>
> Just a trivial thing, Kconfig description can also be updated.
Thanks for review.
I'll update the Kconfig in next version as I want also to change
sec-core driver after Lee's comment.
Best regards,
Krzysztof
>
> Regards,
> Yadwinder
>
> > drivers/clk/clk-s2mps11.c | 61
> > ++---
> > 1 file changed, 46 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
> > index 508875535e1e..8dafb552274f 100644
> > --- a/drivers/clk/clk-s2mps11.c
> > +++ b/drivers/clk/clk-s2mps11.c
> > @@ -1,7 +1,7 @@
> > /*
> > * clk-s2mps11.c - Clock driver for S2MPS11.
> > *
> > - * Copyright (C) 2013 Samsung Electornics
> > + * Copyright (C) 2013,2014 Samsung Electornics
> > *
> > * This program is free software; you can redistribute it and/or modify it
> > * under the terms of the GNU General Public License as published by the
> > @@ -13,10 +13,6 @@
> > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > * GNU General Public License for more details.
> > *
> > - * You should have received a copy of the GNU General Public License
> > - * along with this program; if not, write to the Free Software
> > - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
> > USA
> > - *
> > */
> >
> > #include
> > @@ -27,6 +23,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -125,7 +122,21 @@ static struct clk_init_data
> > s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
> > },
> > };
> >
> > -static struct device_node *s2mps11_clk_parse_dt(struct platform_device
> > *pdev)
> > +static struct clk_init_data s2mps14_clks_init[S2MPS11_CLKS_NUM] = {
> > + [S2MPS11_CLK_AP] = {
> > + .name = "s2mps14_ap",
> > + .ops = &s2mps11_clk_ops,
> > + .flags = CLK_IS_ROOT,
> > + },
> > + [S2MPS11_CLK_BT] = {
> > + .name = "s2mps14_bt",
> > + .ops = &s2mps11_clk_ops,
> > + .flags = CLK_IS_ROOT,
> > + },
> > +};
> > +
> > +static struct device_node *s2mps11_clk_parse_dt(struct platform_device
> > *pdev,
> > + struct clk_init_data *clks_init)
> > {
> > struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
> > struct device_node *clk_np;
> > @@ -145,9 +156,12 @@ static struct device_node *s2mps11_clk_parse_dt(struct
> > platform_device *pdev)
> > if (!clk_table)
> > return ERR_PTR(-ENOMEM);
> >
> > - for (i = 0; i < S2MPS11_CLKS_NUM; i++)
> > + for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
> > + if (!clks_init[i].name)
> > + continue; /* Skip clocks not present in some
> > devices */
> > of_property_read_string_index(clk_np, "clock-output-names",
> > i,
> > - &s2mps11_clks_init[i].name);
> > + &clks_init[i].name);
> > + }
> >
> > return clk_np;
> > }
> > @@ -158,6 +172,7 @@ static int s2mps11_clk_probe(struct platform_device
> > *pdev)
> > struct s2mps11_clk *s2mps11_clks, *s2mps11_clk;
> > struct device_node *clk_np = NULL;
> > unsigned int s2mps11_reg;
> > + struct clk_init_data *clks_init;
> > int i, ret = 0;
> > u32 val;
> >
> > @@ -168,25 +183,33 @@ static int s2mps11_clk_probe(struct platform_device
> > *pdev)
> >
> > s2mps11_clk = s2mps11_clks;
> >
> > - clk_np = s2mps11_clk_parse_dt(pdev);
> > - if (IS_ERR(clk_np))
> > - return PTR_ERR(clk_np);
> > -
> > switch (platform_get_device_id(pdev)->driver_data) {
> > case S2MPS11X:
> > s2mps11_reg = S2MPS11_REG_RTC_CTRL;
> > + clks_init = s2mps11_clks_init;
> > + break;
> > + case S2MPS14X:
> > + s2mps11_reg = S2MPS14_REG_RTCCTRL;
> > + clks_init = s2mps14_clks_init;
> > break;
> > case S5M8767X:
> > s2mps11_reg = S5M8767_REG_CTRL1;
> > + clks_init = s2mps11_clks_init;
> > break;
> > default:
> > dev_err(&pdev->dev, "Invalid device type\n");
> > return -EINVAL;
> > };
> >
> > + clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
> > + if (IS_ERR(clk_np))
> > + return PTR_ERR(clk_np);
> > +
> > for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) {
> > + if (!clks_init[i].name)
> > + continue; /* Skip clocks not present in s
Re: [PATCH 1/3] clk: s2mps11: Add support for S2MPS14 clocks
On Mon, Mar 10, 2014 at 6:04 PM, Krzysztof Kozlowski
wrote:
> This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the
> s2mps11 clock driver.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
Reviewed-by: Yadwinder Singh Brar
Just a trivial thing, Kconfig description can also be updated.
Regards,
Yadwinder
> drivers/clk/clk-s2mps11.c | 61
> ++---
> 1 file changed, 46 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
> index 508875535e1e..8dafb552274f 100644
> --- a/drivers/clk/clk-s2mps11.c
> +++ b/drivers/clk/clk-s2mps11.c
> @@ -1,7 +1,7 @@
> /*
> * clk-s2mps11.c - Clock driver for S2MPS11.
> *
> - * Copyright (C) 2013 Samsung Electornics
> + * Copyright (C) 2013,2014 Samsung Electornics
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License as published by the
> @@ -13,10 +13,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> - *
> */
>
> #include
> @@ -27,6 +23,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -125,7 +122,21 @@ static struct clk_init_data
> s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
> },
> };
>
> -static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev)
> +static struct clk_init_data s2mps14_clks_init[S2MPS11_CLKS_NUM] = {
> + [S2MPS11_CLK_AP] = {
> + .name = "s2mps14_ap",
> + .ops = &s2mps11_clk_ops,
> + .flags = CLK_IS_ROOT,
> + },
> + [S2MPS11_CLK_BT] = {
> + .name = "s2mps14_bt",
> + .ops = &s2mps11_clk_ops,
> + .flags = CLK_IS_ROOT,
> + },
> +};
> +
> +static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
> + struct clk_init_data *clks_init)
> {
> struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
> struct device_node *clk_np;
> @@ -145,9 +156,12 @@ static struct device_node *s2mps11_clk_parse_dt(struct
> platform_device *pdev)
> if (!clk_table)
> return ERR_PTR(-ENOMEM);
>
> - for (i = 0; i < S2MPS11_CLKS_NUM; i++)
> + for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
> + if (!clks_init[i].name)
> + continue; /* Skip clocks not present in some devices
> */
> of_property_read_string_index(clk_np, "clock-output-names", i,
> - &s2mps11_clks_init[i].name);
> + &clks_init[i].name);
> + }
>
> return clk_np;
> }
> @@ -158,6 +172,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
> struct s2mps11_clk *s2mps11_clks, *s2mps11_clk;
> struct device_node *clk_np = NULL;
> unsigned int s2mps11_reg;
> + struct clk_init_data *clks_init;
> int i, ret = 0;
> u32 val;
>
> @@ -168,25 +183,33 @@ static int s2mps11_clk_probe(struct platform_device
> *pdev)
>
> s2mps11_clk = s2mps11_clks;
>
> - clk_np = s2mps11_clk_parse_dt(pdev);
> - if (IS_ERR(clk_np))
> - return PTR_ERR(clk_np);
> -
> switch (platform_get_device_id(pdev)->driver_data) {
> case S2MPS11X:
> s2mps11_reg = S2MPS11_REG_RTC_CTRL;
> + clks_init = s2mps11_clks_init;
> + break;
> + case S2MPS14X:
> + s2mps11_reg = S2MPS14_REG_RTCCTRL;
> + clks_init = s2mps14_clks_init;
> break;
> case S5M8767X:
> s2mps11_reg = S5M8767_REG_CTRL1;
> + clks_init = s2mps11_clks_init;
> break;
> default:
> dev_err(&pdev->dev, "Invalid device type\n");
> return -EINVAL;
> };
>
> + clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
> + if (IS_ERR(clk_np))
> + return PTR_ERR(clk_np);
> +
> for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) {
> + if (!clks_init[i].name)
> + continue; /* Skip clocks not present in some devices
> */
> s2mps11_clk->iodev = iodev;
> - s2mps11_clk->hw.init = &s2mps11_clks_init[i];
> + s2mps11_clk->hw.init = &clks_init[i];
> s2mps11_clk->mask = 1 << i;
> s2mps11_clk->reg = s2mps11_reg;
>
> @@ -220,8 +243,12 @@ static int s2mps11_clk_probe(struct platform_device
> *pdev)
> }
>
> if (clk_table) {
> - for (i = 0; i < S2MPS11_CLKS_NUM; i++)
> + for (i = 0; i < S2MPS1
Re: [PATCHv2 0/5] ARM: dts: exynos: Add missing dt data to bring kernel of Exynos4x12
Hi Chanwoo, On 12.03.2014 07:19, Chanwoo Choi wrote: This patch add missing dt data of Exynos4x12 to bring up kernel feature and code clean. This patchset is based on 'v3.15-next/dt-clk-exynos' branch. - git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git exynos4x12/exynos4412/exynos4212.dtsi - Add ADC (Analog and Digital Converter) to get raw data - Add PMU (Performance Monitoring Unit) for perf event - Add gps_alive power domain to remove power leakage when gps-alive isn't used - Remove duplicate dt data of interrput combiner controller exynos4412-trats.dts - Add ADC dt data with ntc thermistor child to read temperature Changes from v1: - Use clock macro name for Exynos4 instead of constant for ADC - Remove unnecessary description about patch content - Move gps-alive power domain's dt data from exynos4x12.dts to exynos4.dts - Move thermistor dt node outside of ADC dt node and modify node name of thermistor Chanwoo Choi (5): ARM: dts: exynos4x12: Add ADC's dt data to read raw data ARM: dts: exynos4x12: Add PMU dt data to support PMU(Perforamnce Monitoring Unit) ARM: dts: exynos4x12: Add GPS_ALIVE power domain ARM: dts: exynos: Move common dt data for interrupt combiner controller ARM: dts: exynos4412-trats2: Add ADC/themistor dt data to get temperature of SoC/battery arch/arm/boot/dts/exynos4.dtsi | 5 + arch/arm/boot/dts/exynos4212.dtsi | 13 - arch/arm/boot/dts/exynos4412-trats2.dts | 21 + arch/arm/boot/dts/exynos4412.dtsi | 14 -- arch/arm/boot/dts/exynos4x12.dtsi | 26 ++ 5 files changed, 60 insertions(+), 19 deletions(-) Reviewed-by: Tomasz Figa Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH v2 00/21] Add DSI display support for Exynos based boards
On 12.03.2014 11:08, Inki Dae wrote: 2014-03-07 19:00 GMT+09:00 Andrzej Hajda : On 03/05/2014 03:56 AM, Inki Dae wrote: Hi Andrzej, Thanks for your contributions. 2014-02-12 20:31 GMT+09:00 Andrzej Hajda : Hi, This patchset adds drivers and bindings to the following devices: - Exynos DSI master, - S6E8AA0 DSI panel, - TC358764 DSI/LVDS bridge, - HV070WSA-100 LVDS panel. It adds also display support in DTS files for the following boards: - Exynos4210/Trats, - Exynos4412/Trats2, - Exynos5250/Arndale. Things worth mentioning: 1. I have implemented DSI/LVDS bridge using drm_panel framework, ie. the driver exposes drm_panel interface on DSI side, and interact with panels on LVDS side using drm_panel framework. This approach seems to me simpler and more natural than using drm_bridge. Can you give me more details about why you think better to use panel framework than using drm_bridge? "Simpler" and "more natural" are ambiguous to me. In this particular case DSI master expects on the other end any device having DSI slave interface, it could be panel or bridge. So it seems natural that both types of slave devices should expose the same interface also on programming level. Another problem with drm_bridge is that it is not scalable - if some manufacturer will decide to add another block between the bridge and the panel there is no drm component which can be used for it. Using drm_panel the way I have used in toshiba bridge makes scalability possible, it will be only a matter of adding a driver for new block and making proper links in device tree, I see no easy way of doing it with drm_bridge approach. Now drm_bridge may not cover all hardware. However drm_bridge has already been merged to mainline so I think we need to use drm_bridge somehow instead of using other one, and also we could extend drm_bridge if needed. It would be definitely impossible for a new framework to cover all hardware because there may be other hardware not appeared yet. That is what we are doing for mainline until now. Well, maybe drm_bridge has been merged, but so has been drm_panel. Moreover, merged code is not carved in stone, if there is a better option that could replace it, users of it can be converted to the new approach and the old one can be removed. As I believe Andrzej has demonstrated, drm_panel framework is clearly superior over drm_bridge and I can't think of any good reason why it couldn't become more generic and replace drm_bridge. Of course it can be renamed then to something more generic appropriately. Using same drm_panel framework for LDVS bridge and real panel drivers isn't reasonable to me as now because drm_panel framework would be for real panel device even if the use of drm_panel framework looks like suitable to LVDS bridge driver. I thought Sean's way, ptn3460 driver using drm_bride stuff, is good enough, and that would be why drm_bridge exists and why drm_encoder has drm_bridge. And I'm finding more generic way, how to handle LVDS bridge using super node so that LVDS bridge driver isn't embedded to connector drivers such as eDP and MIPI-DSI, and dt binding of LVDS bridge can be done at top level of Exynos drm. Once the binding is done, encoder of display bus driver will have drm_bridge object of LVDS bridge driver so that display bus driver can handle LVDS bridge driver. Could you explain what you mean by "dt binding of LVDS bridge can be done at top level of Exynos drm" ? How it will look like if there will be more bridges, one for DSI, one for HDMI, etc... What if there will be two bridges in one chain. How it will cope with video pipeline bindings? it was just my idea so I have no implementation about it yet. My idea is that crtc and encoder are binded at top level of Exynos drm as is. And for bridge support, the only difference is, in case that encoder driver has bridge, the dt binding of the encoder driver is done once last one between encoder and bridge driver is binded. It would mean that bridge driver can use driver model and it doesn't need to concern about probe order issue. For this, encoder driver with bridge, MIPI-DSI or eDP, would need to use component interfaces specific to Exynos drm. As a result, once the dt bindings of crtc and encoder are completed at top level, encoder driver has its own drm_bridge for bridge, and dt binding you proposed could be used without any change, and drm_panel could also be used only for real lcd panel driver. And below is a block diagram I think, DRM KMS / | \ / | \ crtc encoder connector | / \ | | / \ | | | drm_bridge drm_panel |
Re: [PATCH] clk: exynos4: Add clock ID for ppmuleft/right
Hi Chanwoo,
On 12/03/14 08:08, Chanwoo Choi wrote:
> There is no gate for the PPMU Left/Right to the LEFT/RIGHTBUS block.
> So, this patch add ppmuleft/right clock which is used to calculate memory bus
> utilization by using PPMU(Performance Profiling Monitoring Unit).
>
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Kyungmin Park
> ---
> drivers/clk/samsung/clk-exynos4.c | 2 ++
> include/dt-bindings/clock/exynos4.h | 26 ++
> 2 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c
> b/drivers/clk/samsung/clk-exynos4.c
> index 010f071..3819485 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -717,6 +717,8 @@ static struct samsung_gate_clock exynos4_gate_clks[]
> __initdata = {
> 0, 0),
> GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
> 0, 0),
> + GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
> + GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
> };
>
> /* list of gate clocks supported in exynos4210 soc */
> diff --git a/include/dt-bindings/clock/exynos4.h
> b/include/dt-bindings/clock/exynos4.h
> index 75aff33..cd7fecf 100644
> --- a/include/dt-bindings/clock/exynos4.h
> +++ b/include/dt-bindings/clock/exynos4.h
> @@ -215,20 +215,22 @@
> #define CLK_SPI1_ISP_SCLK381 /* Exynos4x12 only */
> #define CLK_UART_ISP_SCLK382 /* Exynos4x12 only */
> #define CLK_TMU_APBIF383
> +#define CLK_PPMULEFT 384
> +#define CLK_PPMURIGHT385
>
> /* mux clocks */
> -#define CLK_MOUT_FIMC0 384
You must not change the existing clock indices like this, use indexes
that are currently unused for CLK_PPMU* clocks.
If you do that the kernel would stop working with existing dtbs.
This interface is an ABI, so you can't just rearrange the indices
at will like this.
--
Regards,
Sylwester
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Re: [RFC PATCH v2 00/21] Add DSI display support for Exynos based boards
2014-03-07 19:00 GMT+09:00 Andrzej Hajda : > On 03/05/2014 03:56 AM, Inki Dae wrote: >> Hi Andrzej, >> >> Thanks for your contributions. >> >> 2014-02-12 20:31 GMT+09:00 Andrzej Hajda : >>> Hi, >>> >>> This patchset adds drivers and bindings to the following devices: >>> - Exynos DSI master, >>> - S6E8AA0 DSI panel, >>> - TC358764 DSI/LVDS bridge, >>> - HV070WSA-100 LVDS panel. >>> >>> It adds also display support in DTS files for the following boards: >>> - Exynos4210/Trats, >>> - Exynos4412/Trats2, >>> - Exynos5250/Arndale. >>> >>> Things worth mentioning: >>> >>> 1. I have implemented DSI/LVDS bridge using drm_panel framework, ie. >>> the driver exposes drm_panel interface on DSI side, and interact with >>> panels on LVDS side using drm_panel framework. This approach seems to >>> me simpler and more natural than using drm_bridge. >> Can you give me more details about why you think better to use panel >> framework than using drm_bridge? "Simpler" and "more natural" are >> ambiguous to me. > In this particular case DSI master expects on the other end > any device having DSI slave interface, it could be panel or bridge. > So it seems natural that both types of slave devices should expose > the same interface also on programming level. > Another problem with drm_bridge is that it is not scalable - > if some manufacturer will decide to add another block between the bridge > and the panel there is no drm component which can be used for it. > Using drm_panel the way I have used in toshiba bridge makes scalability > possible, > it will be only a matter of adding a driver for new block and making > proper links in device tree, I see no easy way of doing it with > drm_bridge approach. Now drm_bridge may not cover all hardware. However drm_bridge has already been merged to mainline so I think we need to use drm_bridge somehow instead of using other one, and also we could extend drm_bridge if needed. It would be definitely impossible for a new framework to cover all hardware because there may be other hardware not appeared yet. That is what we are doing for mainline until now. > > >> >> Using same drm_panel framework for LDVS bridge and real panel drivers >> isn't reasonable to me as now because drm_panel framework would be for >> real panel device even if the use of drm_panel framework looks like >> suitable to LVDS bridge driver. I thought Sean's way, ptn3460 driver >> using drm_bride stuff, is good enough, and that would be why >> drm_bridge exists and why drm_encoder has drm_bridge. >> >> And I'm finding more generic way, how to handle LVDS bridge using >> super node so that LVDS bridge driver isn't embedded to connector >> drivers such as eDP and MIPI-DSI, and dt binding of LVDS bridge can be >> done at top level of Exynos drm. Once the binding is done, encoder of >> display bus driver will have drm_bridge object of LVDS bridge driver >> so that display bus driver can handle LVDS bridge driver. > Could you explain what you mean by "dt binding of LVDS bridge can be > done at top level of Exynos drm" ? How it will look like if there > will be more bridges, one for DSI, one for HDMI, etc... What if there > will be two > bridges in one chain. How it will cope with video pipeline bindings? it was just my idea so I have no implementation about it yet. My idea is that crtc and encoder are binded at top level of Exynos drm as is. And for bridge support, the only difference is, in case that encoder driver has bridge, the dt binding of the encoder driver is done once last one between encoder and bridge driver is binded. It would mean that bridge driver can use driver model and it doesn't need to concern about probe order issue. For this, encoder driver with bridge, MIPI-DSI or eDP, would need to use component interfaces specific to Exynos drm. As a result, once the dt bindings of crtc and encoder are completed at top level, encoder driver has its own drm_bridge for bridge, and dt binding you proposed could be used without any change, and drm_panel could also be used only for real lcd panel driver. And below is a block diagram I think, DRM KMS / | \ / | \ crtc encoder connector | / \ | | / \ | | | drm_bridge drm_panel | | | | | | | | FIMD MIPI-DSILVDS bridgePanel Thanks, Inki Dae >> >> Will review your patch series soon. > Thanks in advance. > > Regards > Andrzej > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > http://lists.freed
[PATCH] clk: exynos4: Add clock ID for ppmuleft/right
There is no gate for the PPMU Left/Right to the LEFT/RIGHTBUS block.
So, this patch add ppmuleft/right clock which is used to calculate memory bus
utilization by using PPMU(Performance Profiling Monitoring Unit).
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 2 ++
include/dt-bindings/clock/exynos4.h | 26 ++
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 010f071..3819485 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -717,6 +717,8 @@ static struct samsung_gate_clock exynos4_gate_clks[]
__initdata = {
0, 0),
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
0, 0),
+ GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
+ GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
};
/* list of gate clocks supported in exynos4210 soc */
diff --git a/include/dt-bindings/clock/exynos4.h
b/include/dt-bindings/clock/exynos4.h
index 75aff33..cd7fecf 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -215,20 +215,22 @@
#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
#define CLK_TMU_APBIF 383
+#define CLK_PPMULEFT 384
+#define CLK_PPMURIGHT 385
/* mux clocks */
-#define CLK_MOUT_FIMC0 384
-#define CLK_MOUT_FIMC1 385
-#define CLK_MOUT_FIMC2 386
-#define CLK_MOUT_FIMC3 387
-#define CLK_MOUT_CAM0 388
-#define CLK_MOUT_CAM1 389
-#define CLK_MOUT_CSIS0 390
-#define CLK_MOUT_CSIS1 391
-#define CLK_MOUT_G3D0 392
-#define CLK_MOUT_G3D1 393
-#define CLK_MOUT_G3D 394
-#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
+#define CLK_MOUT_FIMC0 386
+#define CLK_MOUT_FIMC1 387
+#define CLK_MOUT_FIMC2 388
+#define CLK_MOUT_FIMC3 389
+#define CLK_MOUT_CAM0 390
+#define CLK_MOUT_CAM1 391
+#define CLK_MOUT_CSIS0 392
+#define CLK_MOUT_CSIS1 393
+#define CLK_MOUT_G3D0 394
+#define CLK_MOUT_G3D1 395
+#define CLK_MOUT_G3D 396
+#define CLK_ACLK400_MCUISP 397 /* Exynos4x12 only */
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
--
1.8.0
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