RE: [PATCH v2 01/10] usb: dwc2/gadget: report disconnect event from 'end session' irq
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
>
> This patch adds a call to s3c_hsotg_disconnect() from 'end session'
> interrupt (GOTGINT_SES_END_DET) to correctly notify gadget subsystem
> about unplugged usb cable. 'disconnected' interrupt (DISCONNINT) might
> look a bit more suitable for this event, but it is asserted only in
> host mode, so in device mode we need to use something else.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/usb/dwc2/gadget.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 7b5856fadd93..119c8a3effc2 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2279,6 +2279,12 @@ irq_retry:
> dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
>
> writel(otgint, hsotg->regs + GOTGINT);
> +
> + if (otgint & GOTGINT_SES_END_DET) {
> + if (hsotg->gadget.speed != USB_SPEED_UNKNOWN)
> + s3c_hsotg_disconnect(hsotg);
> + hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> + }
> }
>
> if (gintsts & GINTSTS_SESSREQINT) {
Does this mean we can get rid of the call to s3c_hsotg_disconnect in
s3c_hsotg_process_control after a SET_ADDRESS is received? If not,
then s3c_hsotg_disconnect will be called twice, once here after the
disconnect, and once again after the reconnect and SET_ADDRESS.
--
Paul
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RE: [PATCH v2 10/10] usb: dwc2/gadget: rework suspend/resume code to correctly restore gadget state
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
>
> Suspend/resume code assumed that the gadget was always enabled and
> connected to usb bus. This means that the actual state of the gadget
> (soft-enabled/disabled or connected/disconnected) was not correctly
> preserved on suspend/resume cycle. This patch fixes this issue.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/usb/dwc2/core.h | 4 +++-
> drivers/usb/dwc2/gadget.c | 43 +++
> 2 files changed, 30 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
> index bf015ab3b44c..3648b76a18b4 100644
> --- a/drivers/usb/dwc2/core.h
> +++ b/drivers/usb/dwc2/core.h
> @@ -210,7 +210,9 @@ struct s3c_hsotg {
> u8 ctrl_buff[8];
>
> struct usb_gadget gadget;
> - unsigned intsetup;
> + unsigned intsetup:1;
> + unsigned intconnected:1;
> + unsigned intenabled:1;
> unsigned long last_rst;
> struct s3c_hsotg_ep *eps;
> };
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 0d34cfc71bfb..c6c6cf982c90 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2925,6 +2925,8 @@ static int s3c_hsotg_udc_start(struct usb_gadget
> *gadget,
> spin_lock_irqsave(&hsotg->lock, flags);
> s3c_hsotg_init(hsotg);
> s3c_hsotg_core_init_disconnected(hsotg);
> + hsotg->enabled = 1;
> + hsotg->connected = 0;
> spin_unlock_irqrestore(&hsotg->lock, flags);
>
> dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
> @@ -2961,6 +2963,8 @@ static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
>
> hsotg->driver = NULL;
> hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> + hsotg->enabled = 0;
> + hsotg->connected = 0;
>
> spin_unlock_irqrestore(&hsotg->lock, flags);
>
> @@ -2999,11 +3003,14 @@ static int s3c_hsotg_pullup(struct usb_gadget
> *gadget, int is_on)
> dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on);
>
> spin_lock_irqsave(&hsotg->lock, flags);
> +
> if (is_on) {
> clk_enable(hsotg->clk);
> + hsotg->connected = 1;
> s3c_hsotg_core_connect(hsotg);
> } else {
> s3c_hsotg_core_disconnect(hsotg);
> + hsotg->connected = 0;
> clk_disable(hsotg->clk);
> }
>
> @@ -3652,16 +3659,18 @@ static int s3c_hsotg_suspend(struct platform_device
> *pdev, pm_message_t state)
> dev_info(hsotg->dev, "suspending usb gadget %s\n",
>hsotg->driver->driver.name);
>
> - spin_lock_irqsave(&hsotg->lock, flags);
> - s3c_hsotg_core_disconnect(hsotg);
> - s3c_hsotg_disconnect(hsotg);
> - hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> - spin_unlock_irqrestore(&hsotg->lock, flags);
> + if (hsotg->enabled) {
Hmm. Are you sure it's safe to check ->enabled outside of the spinlock?
What happens if s3c_hsotg_udc_stop() runs right after this, before the
spinlock is taken, and disables stuff? Sure, it's a tiny window, but
still...
--
Paul
> + int ep;
>
> - s3c_hsotg_phy_disable(hsotg);
> + spin_lock_irqsave(&hsotg->lock, flags);
> + if (hsotg->connected)
> + s3c_hsotg_core_disconnect(hsotg);
> + s3c_hsotg_disconnect(hsotg);
> + hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> + spin_unlock_irqrestore(&hsotg->lock, flags);
> +
> + s3c_hsotg_phy_disable(hsotg);
>
> - if (hsotg->driver) {
> - int ep;
> for (ep = 0; ep < hsotg->num_of_eps; ep++)
> s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
>
> @@ -3679,21 +3688,23 @@ static int s3c_hsotg_resume(struct platform_device
> *pdev)
> unsigned long flags;
> int ret = 0;
>
> - if (hsotg->driver) {
> + if (hsotg->driver)
> dev_info(hsotg->dev, "resuming usb gadget %s\n",
>hsotg->driver->driver.name);
>
> + if (hsotg->enabled) {
> clk_enable(hsotg->clk);
> ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
> - hsotg->supplies);
> - }
> + hsotg->supplies);
>
> - s3c_hsotg_phy_enable(hsotg);
> + s3c_hsotg_phy_enable(hsotg);
>
> - spin_lock_irqsave(&hsotg->lock, flags);
> - s3c_hsotg_core_init_disconnected(hsotg);
> - s3c_hsotg_core_connect(hsotg);
> - spin_unlock_irqrestore(&hsotg->lock, flags);
> + spin_lock_irqsave(&hsotg->lock, flags);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + if (hsotg->connected)
> + s3c_hsotg_core_connect(hsotg);
> + spin_unlock_irqrestore(&hsotg->lock, flags)
RE: [PATCH v2 09/10] usb: dwc2/gadget: fix calls to phy control functions in suspend/resume code
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
>
> This patch moves calls to phy enable/disable out of spinlock protected
> blocks in device suspend/resume to fix incorrect caller context. Phy
> related functions must not be called from atomic context. To protect
> device internal state from a race during suspend, a call to
> s3c_hsotg_core_disconnect() is added under a spinlock, what prevents any
> further activity on the usb bus.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/usb/dwc2/gadget.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index e8ffc080e6c7..0d34cfc71bfb 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -3653,11 +3653,13 @@ static int s3c_hsotg_suspend(struct platform_device
> *pdev, pm_message_t state)
>hsotg->driver->driver.name);
>
> spin_lock_irqsave(&hsotg->lock, flags);
> + s3c_hsotg_core_disconnect(hsotg);
> s3c_hsotg_disconnect(hsotg);
> - s3c_hsotg_phy_disable(hsotg);
> hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> spin_unlock_irqrestore(&hsotg->lock, flags);
>
> + s3c_hsotg_phy_disable(hsotg);
> +
> if (hsotg->driver) {
> int ep;
> for (ep = 0; ep < hsotg->num_of_eps; ep++)
> @@ -3686,8 +3688,9 @@ static int s3c_hsotg_resume(struct platform_device
> *pdev)
> hsotg->supplies);
> }
>
> - spin_lock_irqsave(&hsotg->lock, flags);
> s3c_hsotg_phy_enable(hsotg);
> +
> + spin_lock_irqsave(&hsotg->lock, flags);
> s3c_hsotg_core_init_disconnected(hsotg);
> s3c_hsotg_core_connect(hsotg);
> spin_unlock_irqrestore(&hsotg->lock, flags);
Acked-by: Paul Zimmerman
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RE: [PATCH v2 08/10] usb: dwc2/gadget: use soft-disconnect udc feature in pullup() method
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
>
> This patch moves udc initialization from pullup() method to
> s3c_hsotg_udc_start(), so that method ends with hardware fully
> initialized and left in soft-disconnected state. After this change, the
> pullup() method simply clears soft-disconnect start() when called with
> is_on=1. For completeness, a call to s3c_hsotg_core_disconnect() has
> been added when pullup() method is called with is_on=0, what puts the
> udc hardware back to soft-disconnected state.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/usb/dwc2/gadget.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 98adf8d17493..e8ffc080e6c7 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2883,6 +2883,7 @@ static int s3c_hsotg_udc_start(struct usb_gadget
> *gadget,
> struct usb_gadget_driver *driver)
> {
> struct s3c_hsotg *hsotg = to_hsotg(gadget);
> + unsigned long flags;
> int ret;
>
> if (!hsotg) {
> @@ -2921,7 +2922,13 @@ static int s3c_hsotg_udc_start(struct usb_gadget
> *gadget,
>
> s3c_hsotg_phy_enable(hsotg);
>
> + spin_lock_irqsave(&hsotg->lock, flags);
> + s3c_hsotg_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + spin_unlock_irqrestore(&hsotg->lock, flags);
> +
> dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
> +
> return 0;
>
> err:
> @@ -2994,9 +3001,9 @@ static int s3c_hsotg_pullup(struct usb_gadget *gadget,
> int is_on)
> spin_lock_irqsave(&hsotg->lock, flags);
> if (is_on) {
> clk_enable(hsotg->clk);
> - s3c_hsotg_core_init_disconnected(hsotg);
> s3c_hsotg_core_connect(hsotg);
> } else {
> + s3c_hsotg_core_disconnect(hsotg);
> clk_disable(hsotg->clk);
> }
>
Acked-by: Paul Zimmerman
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RE: [PATCH v2 07/10] usb: dwc2/gadget: move phy control calls out of pullup() method
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
>
> This patch moves phy enable/disable calls from pullup() method to
> udc_start/stop functions. This solves the issue related to limited caller
> context for PHY functions, because they cannot be called from non-sleeping
> context. This is also a preparation for using soft-disconnect feature of
> udc controller in pullup() method.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/usb/dwc2/gadget.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 5eb2473031c4..98adf8d17493 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2919,6 +2919,8 @@ static int s3c_hsotg_udc_start(struct usb_gadget
> *gadget,
> goto err;
> }
>
> + s3c_hsotg_phy_enable(hsotg);
> +
> dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
> return 0;
>
> @@ -2955,6 +2957,8 @@ static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
>
> spin_unlock_irqrestore(&hsotg->lock, flags);
>
> + s3c_hsotg_phy_disable(hsotg);
> +
> regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
>
> clk_disable(hsotg->clk);
> @@ -2989,13 +2993,11 @@ static int s3c_hsotg_pullup(struct usb_gadget
> *gadget, int is_on)
>
> spin_lock_irqsave(&hsotg->lock, flags);
> if (is_on) {
> - s3c_hsotg_phy_enable(hsotg);
> clk_enable(hsotg->clk);
> s3c_hsotg_core_init_disconnected(hsotg);
> s3c_hsotg_core_connect(hsotg);
> } else {
> clk_disable(hsotg->clk);
> - s3c_hsotg_phy_disable(hsotg);
> }
>
> hsotg->gadget.speed = USB_SPEED_UNKNOWN;
Acked-by: Paul Zimmerman
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RE: [PATCH v2 06/10] usb: dwc2/gadget: decouple setting soft-disconnect from s3c_hsotg_core_init
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
>
> This patch changes s3c_hsotg_core_init function to leave hardware in
> soft disconnect mode, so the moment of coupling the hardware to the usb
> bus can be later controlled by the separate functions for enabling and
> disabling soft disconnect mode. This patch is a preparation to rework
> pullup() method.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/usb/dwc2/gadget.c | 22 +-
> 1 file changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index c1dad46bbbdd..5eb2473031c4 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2124,7 +2124,7 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
> *
> * Issue a soft reset to the core, and await the core finishing it.
> */
> -static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
> +static void s3c_hsotg_core_init_disconnected(struct s3c_hsotg *hsotg)
> {
> s3c_hsotg_corereset(hsotg);
>
> @@ -2241,14 +2241,23 @@ static void s3c_hsotg_core_init(struct s3c_hsotg
> *hsotg)
> readl(hsotg->regs + DOEPCTL0));
>
> /* clear global NAKs */
> - writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
> + writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON,
> hsotg->regs + DCTL);
>
> /* must be at-least 3ms to allow bus to see disconnect */
> mdelay(3);
>
> hsotg->last_rst = jiffies;
> +}
> +
> +static void s3c_hsotg_core_disconnect(struct s3c_hsotg *hsotg)
> +{
> + /* set the soft-disconnect bit */
> + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
I'm not really happy with adding more uses of these __orr32, __bic32
functions. When I first saw those, I went 'wtf?", because with the
assembly-sounding names, they look like some special ARM instruction
or something.
But I guess cleaning that up can wait for a future patch series, so OK.
> +}
>
> +static void s3c_hsotg_core_connect(struct s3c_hsotg *hsotg)
> +{
> /* remove the soft-disconnect and let's go */
> __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
> }
> @@ -2348,7 +2357,8 @@ irq_retry:
> kill_all_requests(hsotg, &hsotg->eps[0],
> -ECONNRESET, true);
>
> - s3c_hsotg_core_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + s3c_hsotg_core_connect(hsotg);
> }
> }
> }
> @@ -2981,7 +2991,8 @@ static int s3c_hsotg_pullup(struct usb_gadget *gadget,
> int is_on)
> if (is_on) {
> s3c_hsotg_phy_enable(hsotg);
> clk_enable(hsotg->clk);
> - s3c_hsotg_core_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + s3c_hsotg_core_connect(hsotg);
> } else {
> clk_disable(hsotg->clk);
> s3c_hsotg_phy_disable(hsotg);
> @@ -3668,7 +3679,8 @@ static int s3c_hsotg_resume(struct platform_device
> *pdev)
>
> spin_lock_irqsave(&hsotg->lock, flags);
> s3c_hsotg_phy_enable(hsotg);
> - s3c_hsotg_core_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + s3c_hsotg_core_connect(hsotg);
> spin_unlock_irqrestore(&hsotg->lock, flags);
>
> return ret;
Acked-by: Paul Zimmerman
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RE: [PATCH v2 05/10] usb: dwc2/gadget: move setting last reset time to s3c_hsotg_core_init
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com] > Sent: Monday, October 20, 2014 3:46 AM > > This patch removes duplicated code and sets last_rst variable in the > function which does the hardware reset. > > Signed-off-by: Marek Szyprowski > --- > drivers/usb/dwc2/gadget.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c > index fd52a8b23649..c1dad46bbbdd 100644 > --- a/drivers/usb/dwc2/gadget.c > +++ b/drivers/usb/dwc2/gadget.c > @@ -2247,6 +2247,8 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg) > /* must be at-least 3ms to allow bus to see disconnect */ > mdelay(3); > > + hsotg->last_rst = jiffies; > + > /* remove the soft-disconnect and let's go */ > __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); > } > @@ -2347,7 +2349,6 @@ irq_retry: > -ECONNRESET, true); > > s3c_hsotg_core_init(hsotg); > - hsotg->last_rst = jiffies; > } > } > } > @@ -2908,7 +2909,6 @@ static int s3c_hsotg_udc_start(struct usb_gadget > *gadget, > goto err; > } > > - hsotg->last_rst = jiffies; > dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); > return 0; > > @@ -3667,7 +3667,6 @@ static int s3c_hsotg_resume(struct platform_device > *pdev) > } > > spin_lock_irqsave(&hsotg->lock, flags); > - hsotg->last_rst = jiffies; > s3c_hsotg_phy_enable(hsotg); > s3c_hsotg_core_init(hsotg); > spin_unlock_irqrestore(&hsotg->lock, flags); Acked-by: Paul Zimmerman -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 02/10] usb: dwc2/gadget: fix enumeration issues
> -Original Message- > From: Marek Szyprowski [mailto:m.szyprow...@samsung.com] > Sent: Monday, October 20, 2014 3:46 AM > > Excessive debug messages might cause timing issues that prevent correct > usb enumeration. This patch hides information about USB bus reset to let > driver enumerate fast enough to avoid making host angry. This fixes > endless enumeration and usb reset loop observed with some Linux hosts. > > Signed-off-by: Marek Szyprowski > Reviewed-by: Felipe Balbi > --- > drivers/usb/dwc2/gadget.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c > index 119c8a3effc2..8870e38c1d82 100644 > --- a/drivers/usb/dwc2/gadget.c > +++ b/drivers/usb/dwc2/gadget.c > @@ -2333,7 +2333,7 @@ irq_retry: > > u32 usb_status = readl(hsotg->regs + GOTGCTL); > > - dev_info(hsotg->dev, "%s: USBRst\n", __func__); > + dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); > dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", > readl(hsotg->regs + GNPTXSTS)); > Acked-by: Paul Zimmerman -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 4/5] regulator: max77802: Parse regulator operating mode properties
On Thu, Oct 23, 2014 at 11:28:09AM +0200, Javier Martinez Canillas wrote: Please fix your mailer to word wrap within paragraphs - you should know this by now :/ I've reflowed for legibility. > However this is an implementation detail and should not change the DT > bindings in the current version. Could you please let me know if you > have any issues with the other patches from this series so I can > address all of them when doing a re-spin? I can't recall anything but I'm not sure I looked at them in any detail. signature.asc Description: Digital signature
Re: [PATCH v3 0/9] PM / Domains: Fix race conditions during boot
On Fri, Oct 24, 2014 at 09:12:39AM -0700, Kevin Hilman wrote: > Ulf Hansson writes: > > There may be more than one device in a PM domain which then will be > > probed at different points in time. > > Depending on timing and runtime PM support, in for the device related > > driver/subsystem, a PM domain may be advised to power off after a > > successful probe sequence. > > A general requirement for a device within a PM domain, is that the > > PM domain must stay powered during the probe sequence. To cope with > > such requirement, let's add two new APIs, dev_pm_domain_get|put(). > I'm confused. Why arent' pm_runtime_get*() and pm_runtime_put*() working? > What's not explained here (or what I'm not understanding) is why a PM > domain is powering off if it has active devices. The issue AIUI is what happens during system boot - if one device in a domain probes and marks itself runtime idle then that will trigger domain powerdown even if there is another device in the domain that hasn't yet been probed. This can cause undesirable glitches (or worse) during boot depending on what's getting powered down. signature.asc Description: Digital signature
Re: [PATCH v3 0/9] PM / Domains: Fix race conditions during boot
Ulf Hansson writes: > Changes in v3: > -Rework the entire intermediate step which was suggested in v2. >That means solving the race condition, but also cope with PM domains >that are initialized in powered off state. > > Changes in v2: > -Added some acks. > -Updated commit messages. > -Included a wider audience of the patchset. V1 was lacking SoC >maintainers. > > Here are link to the first patchset, were some discussion started. > http://marc.info/?l=linux-pm&m=141208104729597&w=2 > > There may be more than one device in a PM domain which then will be > probed at different points in time. > > Depending on timing and runtime PM support, in for the device related > driver/subsystem, a PM domain may be advised to power off after a > successful probe sequence. > > A general requirement for a device within a PM domain, is that the > PM domain must stay powered during the probe sequence. To cope with > such requirement, let's add two new APIs, dev_pm_domain_get|put(). > > These APIs are intended to be invoked from subsystem-level code and the > calls between get/put needs to be balanced. > > dev_pm_domain_get(), tells the PM domain that it needs to increase a > usage count and to keep supplying power. dev_pm_domain_put(), does the > opposite. I'm confused. Why arent' pm_runtime_get*() and pm_runtime_put*() working? What's not explained here (or what I'm not understanding) is why a PM domain is powering off if it has active devices. Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5422-odroid-xu3: MCPM: only 6 of 8 CPUs coming online
Abhilash Kesavan writes: > On Thu, Oct 23, 2014 at 9:26 PM, Kevin Hilman wrote: >> Abhilash Kesavan writes: >> >>> The change was based on my reading of the platsmp file of the >>> Odroid-xu3 3.10 kernel and issues experienced previously. From what I >>> understand, the platsmp code in 3.10 kernel is trying to reset the A7s >>> and my change just bypasses the check (no magic here ). The change was >>> only suggested as a workaround to get 8 cores up using MCPM and not an >>> actual fix. I had explained this in my mail to Kevin. So, if this >>> were to be mainlined we would probably need to use something like >>> exynos_core_restart in mcpm along with the workaround. But, this is >>> all guesswork on my part and someone with knowledge of the 3.10 >>> kernel/bootloader needs to comment. >> >> Unfortunately, the harkernel tree git repo doesn't help understand where >> the change came from because an entire v3.10.y based Samsung BSP is >> checked into the tree on top of a v3.8.y kernel in a single commit !!! >> >> Abhilash, in the absence of the original author, could write up a patch >> with your change? >> >> Or, if you can help me with a detailed changelog, I can work on the patch. >> I don't have any exynos docs, so it would be good to have a description >> of what reading/writing to that register are actually doing. > > I could post a patch with an explanation of how I think the workaround > works, but there are a few issues: > - I am not completely confident that this is the best/right change. Maybe post as RFC. > - We are adding code to the exynos mcpm back-end to work-around a > bootloader setting for Odroid-xu3. We would have to make it specific > to odroid somehow as we do not require it for 5420/5800 chromebooks. Hmm, if you have an idea how/where to fix it in u-boot, I'd be glad to give that a try. I'm using the hardkernel u-boot repo: https://github.com/hardkernel/u-boot.git, branch odroidxu3-v2012.07, and would be happy to test any fixes there. > - This might solve the 8 core boot-up issue but other scenarios might > still fail like the one Joonyoung has already reported. I replied yesterday to that report, and the one Joonyoung reported exists with or without your proposed fix, so I don't think they're directly related. >> >> Also, can you explain what you meant by using exynos_core_restart? I >> don't see that function in mainline. > > It is present in linux-next and kgene's for-next branch as part of > this commit "ARM: EXYNOS: SWRESET is needed to boot secondary CPU on > exynos3250". OK, I see it now. Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5422-odroid-xu3: MCPM: only 6 of 8 CPUs coming online
Hello Kevin, On Thu, Oct 23, 2014 at 9:26 PM, Kevin Hilman wrote: > Abhilash Kesavan writes: > >> The change was based on my reading of the platsmp file of the >> Odroid-xu3 3.10 kernel and issues experienced previously. From what I >> understand, the platsmp code in 3.10 kernel is trying to reset the A7s >> and my change just bypasses the check (no magic here ). The change was >> only suggested as a workaround to get 8 cores up using MCPM and not an >> actual fix. I had explained this in my mail to Kevin. So, if this >> were to be mainlined we would probably need to use something like >> exynos_core_restart in mcpm along with the workaround. But, this is >> all guesswork on my part and someone with knowledge of the 3.10 >> kernel/bootloader needs to comment. > > Unfortunately, the harkernel tree git repo doesn't help understand where > the change came from because an entire v3.10.y based Samsung BSP is > checked into the tree on top of a v3.8.y kernel in a single commit !!! > > Abhilash, in the absence of the original author, could write up a patch > with your change? > > Or, if you can help me with a detailed changelog, I can work on the patch. > I don't have any exynos docs, so it would be good to have a description > of what reading/writing to that register are actually doing. I could post a patch with an explanation of how I think the workaround works, but there are a few issues: - I am not completely confident that this is the best/right change. - We are adding code to the exynos mcpm back-end to work-around a bootloader setting for Odroid-xu3. We would have to make it specific to odroid somehow as we do not require it for 5420/5800 chromebooks. - This might solve the 8 core boot-up issue but other scenarios might still fail like the one Joonyoung has already reported. > > Also, can you explain what you meant by using exynos_core_restart? I > don't see that function in mainline. It is present in linux-next and kgene's for-next branch as part of this commit "ARM: EXYNOS: SWRESET is needed to boot secondary CPU on exynos3250". Regards, Abhilash -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Fri, Oct 24, 2014 at 5:31 PM, Linus Walleij wrote: > On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan > wrote: > >> Can you please pick this series up. > > Yes, sorry for the delay. I've applied patches > 1,2,3,4. The patches to the DTS files should be taken > through whatever tree funnels arm64 dts files. Thank you for applying my patches. However, this version (v5) was based on Tomasz's clean-up series and makes use of structures such as "samsung_pin_bank_data" introduced by his series. It also marks the samsung_pin_ctrl instance as __initconst. Thus, patch 4 would cause compilation issues if Tomasz's clean-up patches have not been applied before it. My v4 version was independent of Tomasz's patch series and could be applied directly. Regards, Abhilash > > I hope Tomasz can rebase his nice > clean-up patches on top of this now. > > Yours, > Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
+Sylwester On Wed, Oct 8, 2014 at 11:18 AM, Abhilash Kesavan wrote: > Hi Tomasz, > > On Tue, Oct 7, 2014 at 9:46 AM, Kukjin Kim wrote: >> Tomasz Figa wrote: >>> >>> On 30.09.2014 17:12, Abhilash Kesavan wrote: >>> > Hi Tomasz, >>> > >>> > On Mon, Sep 22, 2014 at 2:22 PM, Tomasz Figa >>> > wrote: >>> >> Hi Abhilash, >>> >> >>> >> On 22.09.2014 06:47, Abhilash Kesavan wrote: >>> >>> Changes since v4: >>> >>> - Fixed comments from Tomasz Figa: >>> >>> - Changed the namespace prefix from exynos to samsung >>> >>> - Defined bindings to take all input clocks >>> >>> - Sorted the Kconfig entries alphabetically in clock Makefile >>> >>> - Used consistent 1 tab line breaks across the clock file >>> >>> - Statically initialized the samsung_cmu_info struct >>> >>> - Enabled exynos7 in the arm64 defconfig as per Catalin Marinas' >>> >>> comment. >>> >>> - Added Kukjin Kim's ack along with Thomas Abraham's tested and >>> >>> reviewed tags. >>> >>> >>> >> >>> >> The clock patches look good to me, but since they are doing quite a lot >>> >> of code moving I'd prefer to take them through clk tree. Based on the >>> >> fact that there are no code dependencies between clock patches and >>> >> remaining ones and Exynos7 is a new material for 3.18, I'm inclined to >>> >> apply them to my tree if nobody minds. >>> > >>> > Will you be picking up the clock changes soon ? >>> >>> I'd like to do so. Kukjin, since clock changes are a part of this >>> series, might I have your Ack for them to be applied separately? >>> >> Sure, I'm fine so please go ahead with my ack on the changes. >> >> Acked-by: Kukjin Kim >> >> Thanks for your asking. > > Can you please pick up the clock changes now that Kukjin has ack'ed it. Sylwester, you mentioned in another thread that Tomasz might not be available for the next few days. Could you please consider applying the clock changes in this series to samsung clk-next if they look OK ? Please take a look at clock changes at http://www.spinics.net/lists/arm-kernel/msg370673.html too. Regards, Abhilash -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 1/2] clk: samsung: exynos4415: Add clocks using common clock framework
Hi Chanwoo,
On 24/10/14 16:07, Chanwoo Choi wrote:
[...]
>> How about prefixing the table names below with "exynos4415", rather than
>> "samsung" ?
>
> 'struct samsung_fixed_factor_clock' is common for Exynos SoC.
>
> Do you means that add 'exynos4415' prefix as following:
> - fixed_factor_clks -> exynos4415_fixed_factor_clks
Yes, it makes sense IMHO, even though those symbols are static.
It's done like that in other SoC drivers, e.g. exynos3250.
>>> +static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
>>
>>> +};
>>> +
>>> +static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
>>> + FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2700),
>>> +};
>>> +
>>> +static struct samsung_mux_clock mux_clks[] __initdata = {
>>
>>> +};
>>> +
>>> +static struct samsung_div_clock div_clks[] __initdata = {
>>
>>> +};
>>> +
>>> +static struct samsung_gate_clock gate_clks[] __initdata = {
>
> Do you want to change structure naming as following?
> fixed_factor_clks -> exynos4415_fixed_factor_clks
> fixed_rate_clks -> exynos4415_fixed_rate_clks
> mux_clks -> exynos4415_mux_clks
> div_clks -> exynos4415_div_clks
> gate_clks -> exynos4415_gate_clks
Yes, please.
--
Thanks,
Sylwester
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Re: [PATCHv2 1/2] clk: samsung: exynos4415: Add clocks using common clock framework
Hi Sylwester,
On 10/24/2014 09:03 PM, Sylwester Nawrocki wrote:
> On 24/10/14 13:07, Chanwoo Choi wrote:
>> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
>> using common clock framework. The CMU (Clock Management Unit) of Exynos4415
>> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
>> and function clocks for individual IPs.
>>
>> Cc: Sylwester Nawrocki
>> Cc: Tomasz Figa
>> Signed-off-by: Chanwoo Choi
>> Signed-off-by: Tomasz Figa
>> Signed-off-by: Seung-Woo Kim
>> Acked-by: Kyungmin Park
>
> Thanks for the update, there are still couple issues pointed out
> by checkpatch.pl unfortunately, please see below.
> Please fix the errors, I added also some more comments inline below.
> In future please put DT binding documentation patch first in the
> series, before the actual driver patch.
>
> WARNING: kfree(NULL) is safe this check is probably not required
> #252: FILE: drivers/clk/samsung/clk-exynos4415.c:252:
> + if (clk_regs)
> + kfree(clk_regs);
>
> ERROR: space required after that ',' (ctx:VxV)
> #423: FILE: drivers/clk/samsung/clk-exynos4415.c:423:
> + 0,4),
>^
>
> WARNING: line over 80 characters
> #726: FILE: drivers/clk/samsung/clk-exynos4415.c:726:
> + "div_pxlasync_csis0_fimc", GATE_SCLK_CAM, 10,
> CLK_SET_RATE_PARENT, 0),
>
> WARNING: line over 80 characters
> #817: FILE: drivers/clk/samsung/clk-exynos4415.c:817:
> + GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
> 22,
>
> WARNING: line over 80 characters
> #875: FILE: drivers/clk/samsung/clk-exynos4415.c:875:
> + GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13, 0,
> 0),
>
> ERROR: space prohibited after that open parenthesis '('
> #920: FILE: drivers/clk/samsung/clk-exynos4415.c:920:
> + PLL_35XX_RATE( 96000, 320, 4, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #921: FILE: drivers/clk/samsung/clk-exynos4415.c:921:
> + PLL_35XX_RATE( 9, 300, 4, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #922: FILE: drivers/clk/samsung/clk-exynos4415.c:922:
> + PLL_35XX_RATE( 85000, 425, 6, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #923: FILE: drivers/clk/samsung/clk-exynos4415.c:923:
> + PLL_35XX_RATE( 8, 200, 3, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #924: FILE: drivers/clk/samsung/clk-exynos4415.c:924:
> + PLL_35XX_RATE( 7, 175, 3, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #925: FILE: drivers/clk/samsung/clk-exynos4415.c:925:
> + PLL_35XX_RATE( 66700, 667, 12, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #926: FILE: drivers/clk/samsung/clk-exynos4415.c:926:
> + PLL_35XX_RATE( 6, 400, 4, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #927: FILE: drivers/clk/samsung/clk-exynos4415.c:927:
> + PLL_35XX_RATE( 55000, 275, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #928: FILE: drivers/clk/samsung/clk-exynos4415.c:928:
> + PLL_35XX_RATE( 53300, 533, 6, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #929: FILE: drivers/clk/samsung/clk-exynos4415.c:929:
> + PLL_35XX_RATE( 52000, 260, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #930: FILE: drivers/clk/samsung/clk-exynos4415.c:930:
> + PLL_35XX_RATE( 5, 250, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #931: FILE: drivers/clk/samsung/clk-exynos4415.c:931:
> + PLL_35XX_RATE( 44000, 220, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #932: FILE: drivers/clk/samsung/clk-exynos4415.c:932:
> + PLL_35XX_RATE( 4, 200, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #933: FILE: drivers/clk/samsung/clk-exynos4415.c:933:
> + PLL_35XX_RATE( 35000, 175, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #934: FILE: drivers/clk/samsung/clk-exynos4415.c:934:
> + PLL_35XX_RATE( 3, 300, 3, 3),
> #935: FILE: drivers/clk/samsung/clk-exynos4415.c:935:
> + PLL_35XX_RATE( 26600, 266, 3, 3),
>
> ERROR: space prohibited after that open parenthesis '('
> #936: FILE: drivers/clk/samsung/clk-exynos4415.c:936:
> + PLL_35XX_RATE( 2, 200, 3, 3),
>
> ERROR: space prohibited after that open parenthesis '('
> #937: FILE: drivers/clk/samsung/clk-exynos4415.c:937:
> + PLL_35XX_RATE( 16000, 160, 3, 3),
>
> ERROR: space prohibited after that open parenthesis '('
> #938: FILE: drivers/clk/samsung/clk-exynos4415.c:938:
> + PLL_35XX_RATE( 1, 200, 3, 4),
>
> ERROR: space prohibited after that open parenthesis '('
> #948: FILE: drivers/clk/samsung/clk-exynos4415.c:948:
> + PLL_36XX_RATE( 9600, 128, 2, 4, 0),
>
> ERROR: space prohibited after that
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 24/10/14 15:18, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> > using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> > controls PLLs(Phase Locked Loops) and generates system clocks for CPU, >> > buses >> > and function clocks for individual IPs. > > There seems to be a lot in common here with other exynos4 variants in > clk-exynos4.c. Have you considered just adding support for the 4415 in > the existing driver? I would rather avoid mixing clock description tables for more SoCs in clk-exynos4.c. There is quite a few differences between exynos4x12 and exynos4415 clock controllers, I'm afraid merging exynos4415 support to clk-exynos4.c would just create more branches and made the code harder to follow, without much decrease in code size. The clock tree in single SoC is already complex, without consolidating support for several SoCs in one unit. -- Regards, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] ARM: dts: Add dts files for Exynos4415 SoC
Hi Daniel, On 10/24/2014 10:23 PM, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> This patch adds new exynos4415.dtsi to support Exynos4415 SoC >> based on Cortex-A9 quad cores and includes following dt nodes: > > There's a lot in common between your new exynos4415.dtsi and the > existing exynos4.dtsi. > Would it make more sense for the 4415 code to extend the existing > exynos4.dtsi like the other Exynos4 variants do? I explained the difference between Exynos4415 and existing Exynos4 series on mail-thread of exynos4415 clock controller. Exynos4415 has difference clock id from existing Exynos4 clock controller. because exynos4415 clock controller has fewer difference from Exynos4 series. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] ARM: dts: Add dts files for Exynos4415 SoC
On Fri, Oct 24, 2014 at 7:34 AM, Marek Szyprowski wrote: > Well, I also thought about such approach, but there are some fundamental > differences: > interrupt and clock controllers are completely different. Using a common > exynos4.dtsi > and overriding them in every node will result in a code, which is a bit hard > to follow. > IMHO with such differences justifies using separate base dtsi file. For the things that aren't in common, they are already split out into soc-specific files for the existing Exynos4 variants. Taking your example of the CMU, it already differs in different exynos4 versions therefore is not listed in exynos4.dtsi at all. So this argument only seems valid if the differences are really huge, or if you are also saying the existing exynos4 dts files are bad? Personally I have come to like the current layout, although would definitely appreciate the reference-based syntax mentioned by Tomasz, and this seems like a good opportunity to at least fix up exynos4.dtsi for that. Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
Hi Daniel, On 10/24/2014 10:18 PM, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses >> and function clocks for individual IPs. > > There seems to be a lot in common here with other exynos4 variants in > clk-exynos4.c. Have you considered just adding support for the 4415 in > the existing driver? Yes, It is difficult and to make existing clk-exynos4.c more complicated. Exynos4415 has fewer difference from existing clk-exynos4.c and different parent source of mux. For exmaple about PLL, There are different PLLs between Exynos4412 and Exynos4415. - Exynos4412 has APLL, MPLL, EPLL, VPLL. - Exynos4415 has APLL, EPLL, G3D_PLL, ISP_PLL, DISP_PLL and MPLL. Also, MPLL of Exynos4415 was included in CMU_DMC scope. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] ARM: dts: Add dts files for Exynos4415 SoC
Hello, On 2014-10-24 15:23, Daniel Drake wrote: On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: This patch adds new exynos4415.dtsi to support Exynos4415 SoC based on Cortex-A9 quad cores and includes following dt nodes: There's a lot in common between your new exynos4415.dtsi and the existing exynos4.dtsi. Would it make more sense for the 4415 code to extend the existing exynos4.dtsi like the other Exynos4 variants do? Well, I also thought about such approach, but there are some fundamental differences: interrupt and clock controllers are completely different. Using a common exynos4.dtsi and overriding them in every node will result in a code, which is a bit hard to follow. IMHO with such differences justifies using separate base dtsi file. Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] ARM: dts: Add dts files for Exynos4415 SoC
On 24.10.2014 15:23, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> This patch adds new exynos4415.dtsi to support Exynos4415 SoC >> based on Cortex-A9 quad cores and includes following dt nodes: > > There's a lot in common between your new exynos4415.dtsi and the > existing exynos4.dtsi. > Would it make more sense for the 4415 code to extend the existing > exynos4.dtsi like the other Exynos4 variants do? This would make sense, but then existing Exynos 4 device tree sources would have to be refactored to use reference-based syntax for extending nodes. (Which is desirable anyway, but adds quite a bit of effort and could be prone to conflicts.) I'd say that they could be merged later anyway. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 24.10.2014 15:18, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses >> and function clocks for individual IPs. > > There seems to be a lot in common here with other exynos4 variants in > clk-exynos4.c. Have you considered just adding support for the 4415 in > the existing driver? I tried when I was still at Samsung and the outcome was far from being nice. There are certain differences, such as separate address spaces of few clock controllers and different bit fields in apparently similar registers, which made resulting code quite ugly. Also another advantage of separate driver is that it can be made without duplicating initial fails of the driver for Exynos4, such as private bindings for external clocks or clock controllers in different power domains grouped together into one big logical clock controller, because at development time they looked so (contiguous address space). Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: PROBLEM: BUG appearing when trying to allocate interrupt on Exynos MCT after CPU hotplug
On 23/10/14 20:41, Stephen Boyd wrote: On 10/23/2014 07:06 AM, Russell King - ARM Linux wrote: On Thu, Oct 23, 2014 at 03:51:16PM +0200, Marcin Jabrzyk wrote: [1.] One line summary of the problem: "BUG: sleeping function called from invalid context at mm/slub.c:1250" after CPU hotplug I'm really not surprised. When SoC have MCT_INT_SPI interrupt it is being allocated after hotplugging of the CPU, secondary_start_kernel() is sending CPU boot notifications which are send when preemption and interrupts are disabled. Exynos_mct notification handler tries to set up and allocate IRQ for SPI type interrupt for started CPU and then BUG appears. There might be similar problem on qcom-timer I think just after looking on the code. There's no problem for qcom-timer because there are only PPIs on SMP platforms. Ok, so it's only a problem on Exynos platform for now. The CPU notifier is called via notify_cpu_starting(), which is called with interrupts disabled, and a reason code of CPU_STARTING. Interrupts at this point /must/ remain disabled. The Exynos code then goes on to call exynos4_local_timer_setup() which tries to reverse the free_irq() in exynos4_local_timer_stop() by calling request_irq(). Calling request_irq() with interrupts off has never been permissible. So, this code is wrong today, and it was also wrong when it was written. It /couldn't/ have been tested. It looks like this commit added this buggy code: commit ee98d27df6827b5ba4bd99cb7d5cb1239b6a1a31 Author: Stephen Boyd Date: Fri Feb 15 16:40:51 2013 -0800 ARM: EXYNOS4: Divorce mct from local timer API Separate the mct local timers from the local timer API. This will allow us to remove ARM local timer support in the near future and gets us closer to moving this driver to drivers/clocksource. Acked-by: Kukjin Kim Acked-by: Marc Zyngier Cc: Thomas Abraham Signed-off-by: Stephen Boyd I'm not so sure. It looks like in that patch I didn't change anything with respect to when things are called. In fact, it looks like we were calling setup_irq() there, but another patch around the same time changed that to request_irq() commit 7114cd749a12ff9fd64a2f6f04919760f45ab183 Author: Chander Kashyap Date: Wed Jun 19 00:29:35 2013 +0900 clocksource: exynos_mct: use (request/free)_irq calls for local timer registration Replace the (setup/remove)_irq calls for local timer registration with (request/free)_irq calls. This generalizes the local timer registration API. Suggested by Mark Rutland. Signed-off-by: Chander Kashyap Acked-by: Mark Rutland Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim I don't believe setup_irq() allocates anything so we should probably go back to using that over request_irq() or explore requesting the irqs once and then enabling/disabling instead. So what would be a better way to handle this? Going back to setup_irq or trying to enable/disable irqs on CPU hotplug? As this touched low level things and it's rare case for setting/enabling irqs just after CPU is coming back to life again. A good question would be: why doesn't this happen at boot time when CPU1 is first brought up? The conditions here are no different from hotplugging CPU1 back in. Do you see a similar warning on boot too? No the boot looks clean and there is not any sign of that problem. Probably because such checks are completely avoided until the system state is switched to SYSTEM_RUNNING (see the first if statement in __might_sleep()). It would be nice if we could remove that. That's most probably the reason of no warnings on boot process. Best regards, -- Marcin Jabrzyk Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] ARM: dts: Add dts files for Exynos4415 SoC
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: > This patch adds new exynos4415.dtsi to support Exynos4415 SoC > based on Cortex-A9 quad cores and includes following dt nodes: There's a lot in common between your new exynos4415.dtsi and the existing exynos4.dtsi. Would it make more sense for the 4415 code to extend the existing exynos4.dtsi like the other Exynos4 variants do? Thanks Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 > using common clock framework. The CMU (Clock Management Unit) of Exynos4415 > controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses > and function clocks for individual IPs. There seems to be a lot in common here with other exynos4 variants in clk-exynos4.c. Have you considered just adding support for the 4415 in the existing driver? Thanks Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv4 1/3] ARM: dts: Add board dts file for Exynos3250-based Rinato board
This patch add support for device tree sources for Samsung Rinato baord
(Gear 2) based on Exynos3250 SoC.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC thermistor
- I2S of Exynos3250
- TMU of Exynos3250
- MFC of Exynos3250
- Secure firmware for Exynos3250 secondary cpu boot
- Serial ports of Exynos3250
- gpio-key for power key
Signed-off-by: Chanwoo Choi
Signed-off-by: Inki Dae
Signed-off-by: Seung-Woo Kim
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/exynos3250-rinato.dts | 424
2 files changed, 426 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/exynos3250-rinato.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4a75e29..91cd4d0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -67,7 +67,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-rinato.dtb \
+ exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
new file mode 100644
index 000..8a18e68
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -0,0 +1,424 @@
+/*
+ * Samsung's Exynos3250 based Rinato board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Rinato board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250.dtsi"
+#include
+
+/ {
+ model = "Samsung Rinato board";
+ compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
+
+ aliases {
+ i2c7 = &i2c_max77836;
+ };
+
+ memory {
+ reg = <0x4000 0x1ff0>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC1,115200N8 root=/dev/mmcblk0p15
rootwait earlyprintk panic=5";
+ };
+
+ firmware@0205F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0205F000 0x1000>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ power_key {
+ interrupt-parent = <&gpx2>;
+ interrupts = <7 0>;
+ gpios = <&gpx2 7 1>;
+ linux,code = ;
+ label = "power key";
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ i2c_max77836: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ gpios = <&gpd0 2 0>, <&gpd0 3 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ max77836: subpmic@25 {
+ compatible = "maxim,max77836";
+ interrupt-parent = <&gpx1>;
+ interrupts = <5 0>;
+ reg = <0x25>;
+ wakeup;
+
+ muic: max77836-muic {
+ compatible = "maxim,max77836-muic";
+ };
+
+ regulators {
+ compatible = "maxim,max77836-regulator";
+ safeout_reg: SAFEOUT {
+ regulator-name = "SAFEOUT";
+ };
+
+ charger_reg: CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <45000>;
+ regulator-max-microamp = <475000>;
+ regulator-boot-on;
+ };
+
+ motor_reg: LDO1 {
+ regulator-name = "MOT_2.7V";
+ regulator-min-microvolt = <110>;
+ regulator-max-microvolt = <270>;
+ };
+
+ LDO2 {
+ regulator-name = "UNUSED_LDO2";
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <395>;
+
[PATCHv4 3/3] ARM: dts: Add sleep mode of regulator for exynos3250-rinato board
This patch add sleep mode of regulator for exynos3250-rinato board to optimize
power-consumption in sleep state.
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
Reviewed-by: Mark Brown
---
arch/arm/boot/dts/exynos3250-rinato.dts | 108
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 8ad9808..84380fa 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -157,6 +157,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo2_reg: LDO2 {
@@ -164,6 +168,10 @@
regulator-min-microvolt = <120>;
regulator-max-microvolt = <120>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo3_reg: LDO3 {
@@ -171,6 +179,10 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo4_reg: LDO4 {
@@ -178,6 +190,10 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo5_reg: LDO5 {
@@ -185,6 +201,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo6_reg: LDO6 {
@@ -192,6 +212,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo7_reg: LDO7 {
@@ -199,6 +223,10 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo8_reg: LDO8 {
@@ -206,6 +234,10 @@
regulator-min-microvolt = <300>;
regulator-max-microvolt = <300>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo9_reg: LDO9 {
@@ -213,12 +245,20 @@
regulator-min-microvolt = <120>;
regulator-max-microvolt = <120>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo10_reg: LDO10 {
regulator-name = "UNUSED_LDO10";
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo11_reg: LDO11 {
@@ -239,60 +279,100 @@
regulator-name = "CAM_AVDD_2.
[PATCHv4 2/3] ARM: dts: Add sleep mode pin configuration for exynos3250-rinato
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 16
arch/arm/boot/dts/exynos3250-rinato.dts | 154 ++
2 files changed, 170 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c1..5ab81c3 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -12,6 +12,22 @@
* published by the Free Software Foundation.
*/
+#define PIN_PULL_NONE 0
+#define PIN_PULL_DOWN 1
+#define PIN_PULL_UP3
+
+#define PIN_PDN_OUT0 0
+#define PIN_PDN_OUT1 1
+#define PIN_PDN_INPUT 2
+#define PIN_PDN_PREV 3
+
+#define PIN_SLP(_pin, _mode, _pull)\
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-con-pdn = ; \
+ samsung,pin-pud-pdn = ; \
+ }
+
&pinctrl_0 {
gpa0: gpa0 {
gpio-controller;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 8a18e68..8ad9808 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -422,3 +422,157 @@
&xusbxti {
clock-frequency = <2400>;
};
+
+&pinctrl_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep0>;
+
+ sleep0: sleep-state {
+ PIN_SLP(gpa0-0, INPUT, DOWN);
+ PIN_SLP(gpa0-1, INPUT, DOWN);
+ PIN_SLP(gpa0-2, INPUT, DOWN);
+ PIN_SLP(gpa0-3, INPUT, DOWN);
+ PIN_SLP(gpa0-4, INPUT, DOWN);
+ PIN_SLP(gpa0-5, INPUT, DOWN);
+ PIN_SLP(gpa0-6, INPUT, DOWN);
+ PIN_SLP(gpa0-7, INPUT, DOWN);
+
+ PIN_SLP(gpa1-0, INPUT, DOWN);
+ PIN_SLP(gpa1-1, INPUT, DOWN);
+ PIN_SLP(gpa1-2, INPUT, DOWN);
+ PIN_SLP(gpa1-3, INPUT, DOWN);
+ PIN_SLP(gpa1-4, INPUT, DOWN);
+ PIN_SLP(gpa1-5, INPUT, DOWN);
+
+ PIN_SLP(gpb-0, PREV, NONE);
+ PIN_SLP(gpb-1, PREV, NONE);
+ PIN_SLP(gpb-2, PREV, NONE);
+ PIN_SLP(gpb-3, PREV, NONE);
+ PIN_SLP(gpb-4, INPUT, DOWN);
+ PIN_SLP(gpb-5, INPUT, DOWN);
+ PIN_SLP(gpb-6, INPUT, DOWN);
+ PIN_SLP(gpb-7, INPUT, DOWN);
+
+ PIN_SLP(gpc0-0, INPUT, DOWN);
+ PIN_SLP(gpc0-1, INPUT, DOWN);
+ PIN_SLP(gpc0-2, INPUT, DOWN);
+ PIN_SLP(gpc0-3, INPUT, DOWN);
+ PIN_SLP(gpc0-4, INPUT, DOWN);
+
+ PIN_SLP(gpc1-0, INPUT, DOWN);
+ PIN_SLP(gpc1-1, INPUT, DOWN);
+ PIN_SLP(gpc1-2, INPUT, DOWN);
+ PIN_SLP(gpc1-3, INPUT, DOWN);
+ PIN_SLP(gpc1-4, INPUT, DOWN);
+
+ PIN_SLP(gpd0-0, INPUT, DOWN);
+ PIN_SLP(gpd0-1, INPUT, DOWN);
+ PIN_SLP(gpd0-2, INPUT, NONE);
+ PIN_SLP(gpd0-3, INPUT, NONE);
+
+ PIN_SLP(gpd1-0, INPUT, NONE);
+ PIN_SLP(gpd1-1, INPUT, NONE);
+ PIN_SLP(gpd1-2, INPUT, NONE);
+ PIN_SLP(gpd1-3, INPUT, NONE);
+ };
+};
+
+&pinctrl_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep1>;
+
+ sleep1: sleep-state {
+ PIN_SLP(gpe0-0, PREV, NONE);
+ PIN_SLP(gpe0-1, PREV, NONE);
+ PIN_SLP(gpe0-2, INPUT, DOWN);
+ PIN_SLP(gpe0-3, INPUT, UP);
+ PIN_SLP(gpe0-4, INPUT, DOWN);
+ PIN_SLP(gpe0-5, INPUT, DOWN);
+ PIN_SLP(gpe0-6, INPUT, DOWN);
+ PIN_SLP(gpe0-7, INPUT, DOWN);
+
+ PIN_SLP(gpe1-0, INPUT, DOWN);
+ PIN_SLP(gpe1-1, PREV, NONE);
+ PIN_SLP(gpe1-2, INPUT, DOWN);
+ PIN_SLP(gpe1-3, INPUT, DOWN);
+ PIN_SLP(gpe1-4, INPUT, DOWN);
+ PIN_SLP(gpe1-5, INPUT, DOWN);
+ PIN_SLP(gpe1-6, INPUT, DOWN);
+ PIN_SLP(gpe1-7, INPUT, NONE);
+
+ PIN_SLP(gpe2-0, INPUT, NONE);
+ PIN_SLP(gpe2-1, INPUT, NONE);
+ PIN_SLP(gpe2-2, INPUT, NONE);
+
+ PIN_SLP(gpk0-0, INPUT, DOWN);
+ PIN_SLP(gpk0-1, INPUT, DOWN);
+ PIN_SLP(gpk0-2, OUT0, NONE);
+ PIN_SLP(gpk0-3, INPUT, DOWN);
+ PIN_SLP(gpk0-4, INPUT, DOWN);
+ PIN_SLP(gpk0-5, INPUT, DOWN);
+ PIN_SLP(gpk0-6, INPUT, DOWN);
+ PIN_SLP(gpk0-7, INPUT, DOWN);
+
+ PIN_SLP(gpk1-0, INPUT, DOWN);
+ PIN_SLP(gpk1-1, INPUT, DOWN);
+
[PATCHv4 0/3] ARM: dts: Add new board dts file for Exynos3250-based Rinato board
This patchset adds new board dts file for Samsung Rinato board (Gear 2) which is based on Exynos3250 SoC and adds sleep mode pin configuration using pinctrl subsystem to reduce leakage power-consumption in sleep state. This patchset is based on linux-samsung.git (for-next branch). Changes from v3: - Fix wrong email address - Remove 'vemmc_reg' fixed regulator and then use 'ldo12_reg' for mshc_0 Changes from v2: - Separate patch3 from patchset[1] and then this patchset includes patch3. After applied patch3, the power-consumption of Rinato board is 0.6mA in suspend state. [1] [PATCHv5 0/3] regulator: of: Add support for parsing regulator suspend state : https://lkml.org/lkml/2014/10/10/161 - Change PDN (Power-down mode) state for GPE0-3 (BT_UART_RTS) because Rinato board uses UART1 for bluetooth device. BT_UART_RTS pin should be disabled in suspend state by setting high state of GPE0-3 - Turn on always the regulator state of VAP_VMIPI_1.0V because if VAP_VMIPI_1.0V is off state or would be not controlled by DRM driver, happen imprecise external abort. Changes from v1: - Remove useless brace - Remove unneeded 'regulators' keyword - Consolidate memory information in one entry Chanwoo Choi (3): ARM: dts: Add board dts file for Exynos3250-based Rinato board ARM: dts: Add sleep mode pin configuration for exynos3250-rinato ARM: dts: Add sleep mode of regulator for exynos3250-rinato board arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 16 + arch/arm/boot/dts/exynos3250-rinato.dts | 686 ++ 3 files changed, 704 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/exynos3250-rinato.dts -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 1/2] clk: samsung: exynos4415: Add clocks using common clock framework
Hi Sylwester,
On 10/24/2014 09:03 PM, Sylwester Nawrocki wrote:
> On 24/10/14 13:07, Chanwoo Choi wrote:
>> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
>> using common clock framework. The CMU (Clock Management Unit) of Exynos4415
>> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
>> and function clocks for individual IPs.
>>
>> Cc: Sylwester Nawrocki
>> Cc: Tomasz Figa
>> Signed-off-by: Chanwoo Choi
>> Signed-off-by: Tomasz Figa
>> Signed-off-by: Seung-Woo Kim
>> Acked-by: Kyungmin Park
>
> Thanks for the update, there are still couple issues pointed out
> by checkpatch.pl unfortunately, please see below.
> Please fix the errors, I added also some more comments inline below.
> In future please put DT binding documentation patch first in the
> series, before the actual driver patch.
I'm so sorry.
I'll fix it using checkpatch script right now.
Best Regards,
Chanwoo Choi
>
> WARNING: kfree(NULL) is safe this check is probably not required
> #252: FILE: drivers/clk/samsung/clk-exynos4415.c:252:
> + if (clk_regs)
> + kfree(clk_regs);
>
> ERROR: space required after that ',' (ctx:VxV)
> #423: FILE: drivers/clk/samsung/clk-exynos4415.c:423:
> + 0,4),
>^
>
> WARNING: line over 80 characters
> #726: FILE: drivers/clk/samsung/clk-exynos4415.c:726:
> + "div_pxlasync_csis0_fimc", GATE_SCLK_CAM, 10,
> CLK_SET_RATE_PARENT, 0),
>
> WARNING: line over 80 characters
> #817: FILE: drivers/clk/samsung/clk-exynos4415.c:817:
> + GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
> 22,
>
> WARNING: line over 80 characters
> #875: FILE: drivers/clk/samsung/clk-exynos4415.c:875:
> + GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13, 0,
> 0),
>
> ERROR: space prohibited after that open parenthesis '('
> #920: FILE: drivers/clk/samsung/clk-exynos4415.c:920:
> + PLL_35XX_RATE( 96000, 320, 4, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #921: FILE: drivers/clk/samsung/clk-exynos4415.c:921:
> + PLL_35XX_RATE( 9, 300, 4, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #922: FILE: drivers/clk/samsung/clk-exynos4415.c:922:
> + PLL_35XX_RATE( 85000, 425, 6, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #923: FILE: drivers/clk/samsung/clk-exynos4415.c:923:
> + PLL_35XX_RATE( 8, 200, 3, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #924: FILE: drivers/clk/samsung/clk-exynos4415.c:924:
> + PLL_35XX_RATE( 7, 175, 3, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #925: FILE: drivers/clk/samsung/clk-exynos4415.c:925:
> + PLL_35XX_RATE( 66700, 667, 12, 1),
>
> ERROR: space prohibited after that open parenthesis '('
> #926: FILE: drivers/clk/samsung/clk-exynos4415.c:926:
> + PLL_35XX_RATE( 6, 400, 4, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #927: FILE: drivers/clk/samsung/clk-exynos4415.c:927:
> + PLL_35XX_RATE( 55000, 275, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #928: FILE: drivers/clk/samsung/clk-exynos4415.c:928:
> + PLL_35XX_RATE( 53300, 533, 6, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #929: FILE: drivers/clk/samsung/clk-exynos4415.c:929:
> + PLL_35XX_RATE( 52000, 260, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #930: FILE: drivers/clk/samsung/clk-exynos4415.c:930:
> + PLL_35XX_RATE( 5, 250, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #931: FILE: drivers/clk/samsung/clk-exynos4415.c:931:
> + PLL_35XX_RATE( 44000, 220, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #932: FILE: drivers/clk/samsung/clk-exynos4415.c:932:
> + PLL_35XX_RATE( 4, 200, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #933: FILE: drivers/clk/samsung/clk-exynos4415.c:933:
> + PLL_35XX_RATE( 35000, 175, 3, 2),
>
> ERROR: space prohibited after that open parenthesis '('
> #934: FILE: drivers/clk/samsung/clk-exynos4415.c:934:
> + PLL_35XX_RATE( 3, 300, 3, 3),
> #935: FILE: drivers/clk/samsung/clk-exynos4415.c:935:
> + PLL_35XX_RATE( 26600, 266, 3, 3),
>
> ERROR: space prohibited after that open parenthesis '('
> #936: FILE: drivers/clk/samsung/clk-exynos4415.c:936:
> + PLL_35XX_RATE( 2, 200, 3, 3),
>
> ERROR: space prohibited after that open parenthesis '('
> #937: FILE: drivers/clk/samsung/clk-exynos4415.c:937:
> + PLL_35XX_RATE( 16000, 160, 3, 3),
>
> ERROR: space prohibited after that open parenthesis '('
> #938: FILE: drivers/clk/samsung/clk-exynos4415.c:938:
> + PLL_35XX_RATE( 1, 200, 3, 4),
>
> ERROR: space prohibited after that open parenthesis '('
> #948: FILE: drivers/clk/samsung/clk-exynos4415.c:948:
>
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On 24.10.2014 14:01, Linus Walleij wrote: > On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan > wrote: > >> Can you please pick this series up. > > Yes, sorry for the delay. I've applied patches > 1,2,3,4. The patches to the DTS files should be taken > through whatever tree funnels arm64 dts files. > > I hope Tomasz can rebase his nice > clean-up patches on top of this now. Unfortunately I have quite a busy week right now, preparing for relocation, so I will not be able to take care of this probably until next weekend when I settle in my destination place. Sorry for the delay. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 1/3] ARM: dts: Add board dts file for Exynos3250-based Rinato board
Hi Krzysztof,
On 10/24/2014 08:57 PM, Krzysztof Kozłowski wrote:
> On 24.10.2014 13:39, Chanwoo Choi wrote:
>> This patch add support for device tree sources for Samsung Rinato baord
>> (Gear 2) based on Exynos3250 SoC.
>>
>> This dts file support following features:
>> - eMMC
>> - Main PMIC (Samsung S2MPS14)
>> - Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
>> - RTC of Exynos3250
>> - ADC of Exynos3250 with NTC thermistor
>> - I2S of Exynos3250
>> - TMU of Exynos3250
>> - MFC of Exynos3250
>> - Secure firmware for Exynos3250 secondary cpu boot
>> - Serial ports of Exynos3250
>> - gpio-key for power key
>>
>> Signed-off-by: Chanwoo Choi
>> Signed-off-by: Inki Dae
>> Signed-off-by: Seung-Woo Kim
>> Signed-off-by: Jaehoon Chung
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/boot/dts/Makefile | 3 +-
>> arch/arm/boot/dts/exynos3250-rinato.dts | 433
>>
>> 2 files changed, 435 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/boot/dts/exynos3250-rinato.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 4a75e29..91cd4d0 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -67,7 +67,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
>> dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
>> da850-evm.dtb
>> dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
>> -dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>> +dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-rinato.dtb \
>> +exynos4210-origen.dtb \
>> exynos4210-smdkv310.dtb \
>> exynos4210-trats.dtb \
>> exynos4210-universal_c210.dtb \
>> diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
>> b/arch/arm/boot/dts/exynos3250-rinato.dts
>> new file mode 100644
>> index 000..be0ba8d
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250-rinato.dts
>> @@ -0,0 +1,433 @@
>> +/*
>> + * Samsung's Exynos3250 based Rinato board device tree source
>> + *
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Device tree source file for Samsung's Rinato board which is based on
>> + * Samsung Exynos3250 SoC.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +/dts-v1/;
>> +#include "exynos3250.dtsi"
>> +#include
>> +
>> +/ {
>> +model = "Samsung Rinato board";
>> +compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
>> +
>> +aliases {
>> +i2c7 = &i2c_max77836;
>> +};
>> +
>> +memory {
>> +reg = <0x4000 0x1ff0>;
>> +};
>> +
>> +chosen {
>> +bootargs = "console=ttySAC1,115200N8 root=/dev/mmcblk0p15
>> rootwait earlyprintk panic=5";
>> +};
>> +
>> +firmware@0205F000 {
>> +compatible = "samsung,secure-firmware";
>> +reg = <0x0205F000 0x1000>;
>> +};
>> +
>> +gpio_keys {
>> +compatible = "gpio-keys";
>> +
>> +power_key {
>> +interrupt-parent = <&gpx2>;
>> +interrupts = <7 0>;
>> +gpios = <&gpx2 7 1>;
>> +linux,code = ;
>> +label = "power key";
>> +debounce-interval = <10>;
>> +gpio-key,wakeup;
>> +};
>> +};
>> +
>> +vemmc_reg: voltage-regulator-0 {
>> +compatible = "regulator-fixed";
>> +regulator-name = "V_EMMC_2.8V-fixed";
>> +regulator-min-microvolt = <280>;
>> +regulator-max-microvolt = <280>;
>> +gpio = <&gpk0 2 0>;
>> +enable-active-high;
>> +};
>
> Hi Chanwoo,
>
> I wonder if this regulator-fixed is needed. The LDO11 and LDO12 has
> external GPIO control set up. So maybe this could be removed?
OK, I'll remove 'vemmc_reg' and then use ldo12_reg insead of 'vemmc_reg' on
mshc_0 dt node.
Best Regards,
Chanwoo Choi
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Re: [PATCHv2 1/2] clk: samsung: exynos4415: Add clocks using common clock framework
On 24/10/14 13:07, Chanwoo Choi wrote:
> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
> using common clock framework. The CMU (Clock Management Unit) of Exynos4415
> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
> and function clocks for individual IPs.
>
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Tomasz Figa
> Signed-off-by: Seung-Woo Kim
> Acked-by: Kyungmin Park
Thanks for the update, there are still couple issues pointed out
by checkpatch.pl unfortunately, please see below.
Please fix the errors, I added also some more comments inline below.
In future please put DT binding documentation patch first in the
series, before the actual driver patch.
WARNING: kfree(NULL) is safe this check is probably not required
#252: FILE: drivers/clk/samsung/clk-exynos4415.c:252:
+ if (clk_regs)
+ kfree(clk_regs);
ERROR: space required after that ',' (ctx:VxV)
#423: FILE: drivers/clk/samsung/clk-exynos4415.c:423:
+ 0,4),
^
WARNING: line over 80 characters
#726: FILE: drivers/clk/samsung/clk-exynos4415.c:726:
+ "div_pxlasync_csis0_fimc", GATE_SCLK_CAM, 10,
CLK_SET_RATE_PARENT, 0),
WARNING: line over 80 characters
#817: FILE: drivers/clk/samsung/clk-exynos4415.c:817:
+ GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
22,
WARNING: line over 80 characters
#875: FILE: drivers/clk/samsung/clk-exynos4415.c:875:
+ GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13, 0,
0),
ERROR: space prohibited after that open parenthesis '('
#920: FILE: drivers/clk/samsung/clk-exynos4415.c:920:
+ PLL_35XX_RATE( 96000, 320, 4, 1),
ERROR: space prohibited after that open parenthesis '('
#921: FILE: drivers/clk/samsung/clk-exynos4415.c:921:
+ PLL_35XX_RATE( 9, 300, 4, 1),
ERROR: space prohibited after that open parenthesis '('
#922: FILE: drivers/clk/samsung/clk-exynos4415.c:922:
+ PLL_35XX_RATE( 85000, 425, 6, 1),
ERROR: space prohibited after that open parenthesis '('
#923: FILE: drivers/clk/samsung/clk-exynos4415.c:923:
+ PLL_35XX_RATE( 8, 200, 3, 1),
ERROR: space prohibited after that open parenthesis '('
#924: FILE: drivers/clk/samsung/clk-exynos4415.c:924:
+ PLL_35XX_RATE( 7, 175, 3, 1),
ERROR: space prohibited after that open parenthesis '('
#925: FILE: drivers/clk/samsung/clk-exynos4415.c:925:
+ PLL_35XX_RATE( 66700, 667, 12, 1),
ERROR: space prohibited after that open parenthesis '('
#926: FILE: drivers/clk/samsung/clk-exynos4415.c:926:
+ PLL_35XX_RATE( 6, 400, 4, 2),
ERROR: space prohibited after that open parenthesis '('
#927: FILE: drivers/clk/samsung/clk-exynos4415.c:927:
+ PLL_35XX_RATE( 55000, 275, 3, 2),
ERROR: space prohibited after that open parenthesis '('
#928: FILE: drivers/clk/samsung/clk-exynos4415.c:928:
+ PLL_35XX_RATE( 53300, 533, 6, 2),
ERROR: space prohibited after that open parenthesis '('
#929: FILE: drivers/clk/samsung/clk-exynos4415.c:929:
+ PLL_35XX_RATE( 52000, 260, 3, 2),
ERROR: space prohibited after that open parenthesis '('
#930: FILE: drivers/clk/samsung/clk-exynos4415.c:930:
+ PLL_35XX_RATE( 5, 250, 3, 2),
ERROR: space prohibited after that open parenthesis '('
#931: FILE: drivers/clk/samsung/clk-exynos4415.c:931:
+ PLL_35XX_RATE( 44000, 220, 3, 2),
ERROR: space prohibited after that open parenthesis '('
#932: FILE: drivers/clk/samsung/clk-exynos4415.c:932:
+ PLL_35XX_RATE( 4, 200, 3, 2),
ERROR: space prohibited after that open parenthesis '('
#933: FILE: drivers/clk/samsung/clk-exynos4415.c:933:
+ PLL_35XX_RATE( 35000, 175, 3, 2),
ERROR: space prohibited after that open parenthesis '('
#934: FILE: drivers/clk/samsung/clk-exynos4415.c:934:
+ PLL_35XX_RATE( 3, 300, 3, 3),
#935: FILE: drivers/clk/samsung/clk-exynos4415.c:935:
+ PLL_35XX_RATE( 26600, 266, 3, 3),
ERROR: space prohibited after that open parenthesis '('
#936: FILE: drivers/clk/samsung/clk-exynos4415.c:936:
+ PLL_35XX_RATE( 2, 200, 3, 3),
ERROR: space prohibited after that open parenthesis '('
#937: FILE: drivers/clk/samsung/clk-exynos4415.c:937:
+ PLL_35XX_RATE( 16000, 160, 3, 3),
ERROR: space prohibited after that open parenthesis '('
#938: FILE: drivers/clk/samsung/clk-exynos4415.c:938:
+ PLL_35XX_RATE( 1, 200, 3, 4),
ERROR: space prohibited after that open parenthesis '('
#948: FILE: drivers/clk/samsung/clk-exynos4415.c:948:
+ PLL_36XX_RATE( 9600, 128, 2, 4, 0),
ERROR: space prohibited after that open parenthesis '('
#949: FILE: drivers/clk/samsung/clk-exynos4415.c:949:
+ PLL_36XX_RATE( 8400, 112, 2, 4, 0),
ERROR: space prohibited after that open parenthesis '('
#950: FILE: drivers/clk/samsung/clk-exynos4415.c:950:
+
Re: [PATCH v2 0/5] pinctrl: samsung: Data structure clean-up
On Wed, Oct 8, 2014 at 12:23 PM, Linus Walleij wrote: > On Thu, Oct 2, 2014 at 8:52 PM, Tomasz Figa wrote: > >> This series intends to clean up data structures used by pinctrl-samsung >> driver. >> More specifically, it separates initial compile time constants from data used >> at runtime, allowing unused variant data to be dropped and selected >> structures >> constified to improve safety. > > Thanks! > > The patches missed the v3.18 merge window, but I have queued them up as > the first thing to go into v3.19. I wrote somewhere else that this exploded somehow. I've merged Abhilash's patches so now this work needs to be rebased on top of his stuf... Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan wrote: > Can you please pick this series up. Yes, sorry for the delay. I've applied patches 1,2,3,4. The patches to the DTS files should be taken through whatever tree funnels arm64 dts files. I hope Tomasz can rebase his nice clean-up patches on top of this now. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 1/3] ARM: dts: Add board dts file for Exynos3250-based Rinato board
On 24.10.2014 13:39, Chanwoo Choi wrote:
> This patch add support for device tree sources for Samsung Rinato baord
> (Gear 2) based on Exynos3250 SoC.
>
> This dts file support following features:
> - eMMC
> - Main PMIC (Samsung S2MPS14)
> - Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
> - RTC of Exynos3250
> - ADC of Exynos3250 with NTC thermistor
> - I2S of Exynos3250
> - TMU of Exynos3250
> - MFC of Exynos3250
> - Secure firmware for Exynos3250 secondary cpu boot
> - Serial ports of Exynos3250
> - gpio-key for power key
>
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Inki Dae
> Signed-off-by: Seung-Woo Kim
> Signed-off-by: Jaehoon Chung
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/exynos3250-rinato.dts | 433
>
> 2 files changed, 435 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/exynos3250-rinato.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4a75e29..91cd4d0 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -67,7 +67,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
> dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
> da850-evm.dtb
> dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
> -dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
> +dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-rinato.dtb \
> + exynos4210-origen.dtb \
> exynos4210-smdkv310.dtb \
> exynos4210-trats.dtb \
> exynos4210-universal_c210.dtb \
> diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
> b/arch/arm/boot/dts/exynos3250-rinato.dts
> new file mode 100644
> index 000..be0ba8d
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos3250-rinato.dts
> @@ -0,0 +1,433 @@
> +/*
> + * Samsung's Exynos3250 based Rinato board device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * Device tree source file for Samsung's Rinato board which is based on
> + * Samsung Exynos3250 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos3250.dtsi"
> +#include
> +
> +/ {
> + model = "Samsung Rinato board";
> + compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
> +
> + aliases {
> + i2c7 = &i2c_max77836;
> + };
> +
> + memory {
> + reg = <0x4000 0x1ff0>;
> + };
> +
> + chosen {
> + bootargs = "console=ttySAC1,115200N8 root=/dev/mmcblk0p15
> rootwait earlyprintk panic=5";
> + };
> +
> + firmware@0205F000 {
> + compatible = "samsung,secure-firmware";
> + reg = <0x0205F000 0x1000>;
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> +
> + power_key {
> + interrupt-parent = <&gpx2>;
> + interrupts = <7 0>;
> + gpios = <&gpx2 7 1>;
> + linux,code = ;
> + label = "power key";
> + debounce-interval = <10>;
> + gpio-key,wakeup;
> + };
> + };
> +
> + vemmc_reg: voltage-regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_EMMC_2.8V-fixed";
> + regulator-min-microvolt = <280>;
> + regulator-max-microvolt = <280>;
> + gpio = <&gpk0 2 0>;
> + enable-active-high;
> + };
Hi Chanwoo,
I wonder if this regulator-fixed is needed. The LDO11 and LDO12 has
external GPIO control set up. So maybe this could be removed?
Best regards,
Krzysztof
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Re: [PATCHv3 2/3] ARM: dts: Add sleep mode pin configuration for exynos3250-rinato
Hi Tomasz, On 10/24/2014 08:48 PM, Tomasz Figa wrote: > Hi Chanwoo, > > On 24.10.2014 13:39, Chanwoo Choi wrote: >> This patch add sleep mode pin configuration using pinctrl subsystem >> to reduce leakage power-consumption of gpio pin in sleep state. >> >> Signed-off-by: Chanwoo Choi >> Acked-by: Kyungmin Park > > I suspect a typo in this email address. Kukjin, is this something you > could fix up when applying (other patches in this series have it correct)? Sorry about my mistake. I'll resend it right now. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 2/3] ARM: dts: Add sleep mode pin configuration for exynos3250-rinato
Hi Chanwoo, On 24.10.2014 13:39, Chanwoo Choi wrote: > This patch add sleep mode pin configuration using pinctrl subsystem > to reduce leakage power-consumption of gpio pin in sleep state. > > Signed-off-by: Chanwoo Choi > Acked-by: Kyungmin Park I suspect a typo in this email address. Kukjin, is this something you could fix up when applying (other patches in this series have it correct)? Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] ARM: EXYNOS: Add EXYNOS4415 SoC ID
Hi Tomasz, On 10/24/2014 08:43 PM, Tomasz Figa wrote: > Hi Chanwoo, > > On 20.10.2014 05:32, Chanwoo Choi wrote: >> This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC >> processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a >> target >> speed of 1.6GHz and provides 8.5GB/s memory bandwidth. >> >> Cc: Kukjin Kim >> Signed-off-by: Chanwoo Choi >> Acked-by: Kyungmin Park >> --- >> arch/arm/mach-exynos/Kconfig | 5 + >> arch/arm/mach-exynos/common.h | 8 >> arch/arm/mach-exynos/exynos.c | 2 ++ >> 3 files changed, 15 insertions(+) >> >> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig >> index 46f3c0d..349c867 100644 >> --- a/arch/arm/mach-exynos/Kconfig >> +++ b/arch/arm/mach-exynos/Kconfig >> @@ -75,6 +75,11 @@ config SOC_EXYNOS4412 >> default y >> depends on ARCH_EXYNOS4 >> >> +config SOC_EXYNOS4415 >> +bool "SAMSUNG EXYNOS4415" >> +default y >> +depends on ARCH_EXYNOS4 >> + >> config SOC_EXYNOS5250 >> bool "SAMSUNG EXYNOS5250" >> default y >> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h >> index d4d09bc..ffc0c22 100644 >> --- a/arch/arm/mach-exynos/common.h >> +++ b/arch/arm/mach-exynos/common.h >> @@ -21,6 +21,7 @@ >> #define EXYNOS4210_CPU_ID 0x4321 >> #define EXYNOS4212_CPU_ID 0x4322 >> #define EXYNOS4412_CPU_ID 0xE4412200 >> +#define EXYNOS4415_CPU_ID 0xE4415000 >> #define EXYNOS4_CPU_MASK0xFFFE >> >> #define EXYNOS5250_SOC_ID 0x4352 >> @@ -42,6 +43,7 @@ IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, >> EXYNOS3_SOC_MASK) >> IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) >> IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) >> IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) >> +IS_SAMSUNG_CPU(exynos4415, EXYNOS4415_CPU_ID, EXYNOS4_CPU_MASK) > > Is there a need for this legacy helper for this SoC? No, I'll drop it on next patchset. > >> IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) >> IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) >> IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) >> @@ -72,6 +74,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, >> EXYNOS5_SOC_MASK) >> # define soc_is_exynos4412()0 >> #endif >> >> +#if defined(CONFIG_SOC_EXYNOS4415) >> +# define soc_is_exynos4415()is_samsung_exynos4415() >> +#else >> +# define soc_is_exynos4415()0 >> +#endif > > Ditto. I'll drop it on next patchset. Best Regards, Chanwoo Choi > > Best regards, > Tomasz > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] ARM: EXYNOS: Add EXYNOS4415 SoC ID
Hi Chanwoo, On 20.10.2014 05:32, Chanwoo Choi wrote: > This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC > processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a > target > speed of 1.6GHz and provides 8.5GB/s memory bandwidth. > > Cc: Kukjin Kim > Signed-off-by: Chanwoo Choi > Acked-by: Kyungmin Park > --- > arch/arm/mach-exynos/Kconfig | 5 + > arch/arm/mach-exynos/common.h | 8 > arch/arm/mach-exynos/exynos.c | 2 ++ > 3 files changed, 15 insertions(+) > > diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig > index 46f3c0d..349c867 100644 > --- a/arch/arm/mach-exynos/Kconfig > +++ b/arch/arm/mach-exynos/Kconfig > @@ -75,6 +75,11 @@ config SOC_EXYNOS4412 > default y > depends on ARCH_EXYNOS4 > > +config SOC_EXYNOS4415 > + bool "SAMSUNG EXYNOS4415" > + default y > + depends on ARCH_EXYNOS4 > + > config SOC_EXYNOS5250 > bool "SAMSUNG EXYNOS5250" > default y > diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h > index d4d09bc..ffc0c22 100644 > --- a/arch/arm/mach-exynos/common.h > +++ b/arch/arm/mach-exynos/common.h > @@ -21,6 +21,7 @@ > #define EXYNOS4210_CPU_ID0x4321 > #define EXYNOS4212_CPU_ID0x4322 > #define EXYNOS4412_CPU_ID0xE4412200 > +#define EXYNOS4415_CPU_ID0xE4415000 > #define EXYNOS4_CPU_MASK 0xFFFE > > #define EXYNOS5250_SOC_ID0x4352 > @@ -42,6 +43,7 @@ IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, > EXYNOS3_SOC_MASK) > IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) > IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) > IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) > +IS_SAMSUNG_CPU(exynos4415, EXYNOS4415_CPU_ID, EXYNOS4_CPU_MASK) Is there a need for this legacy helper for this SoC? > IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) > IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) > IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) > @@ -72,6 +74,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, > EXYNOS5_SOC_MASK) > # define soc_is_exynos4412() 0 > #endif > > +#if defined(CONFIG_SOC_EXYNOS4415) > +# define soc_is_exynos4415() is_samsung_exynos4415() > +#else > +# define soc_is_exynos4415() 0 > +#endif Ditto. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv3 3/3] ARM: dts: Add sleep mode of regulator for exynos3250-rinato board
This patch add sleep mode of regulator for exynos3250-rinato board to optimize
power-consumption in sleep state.
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
Reviewed-by: Mark Brown
---
arch/arm/boot/dts/exynos3250-rinato.dts | 108
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 7256eec..8e828bc 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -166,6 +166,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo2_reg: LDO2 {
@@ -173,6 +177,10 @@
regulator-min-microvolt = <120>;
regulator-max-microvolt = <120>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo3_reg: LDO3 {
@@ -180,6 +188,10 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo4_reg: LDO4 {
@@ -187,6 +199,10 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo5_reg: LDO5 {
@@ -194,6 +210,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo6_reg: LDO6 {
@@ -201,6 +221,10 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo7_reg: LDO7 {
@@ -208,6 +232,10 @@
regulator-min-microvolt = <180>;
regulator-max-microvolt = <180>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo8_reg: LDO8 {
@@ -215,6 +243,10 @@
regulator-min-microvolt = <300>;
regulator-max-microvolt = <300>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo9_reg: LDO9 {
@@ -222,12 +254,20 @@
regulator-min-microvolt = <120>;
regulator-max-microvolt = <120>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo10_reg: LDO10 {
regulator-name = "UNUSED_LDO10";
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo11_reg: LDO11 {
@@ -248,60 +288,100 @@
regulator-name = "CAM_AVDD_2.
[PATCHv3 0/3] ARM: dts: Add new board dts file for Exynos3250-based Rinato board
This patchset adds new board dts file for Samsung Rinato board (Gear 2) which is based on Exynos3250 SoC and adds sleep mode pin configuration using pinctrl subsystem to reduce leakage power-consumption in sleep state. This patchset is based on linux-samsung.git (for-next branch). Changes from v2: - Separate patch3 from patchset[1] and then this patchset includes patch3. After applied patch3, the power-consumption of Rinato board is 0.6mA in suspend state. [1] [PATCHv5 0/3] regulator: of: Add support for parsing regulator suspend state : https://lkml.org/lkml/2014/10/10/161 - Change PDN (Power-down mode) state for GPE0-3 (BT_UART_RTS) because Rinato board uses UART1 for bluetooth device. BT_UART_RTS pin should be disabled in suspend state by setting high state of GPE0-3 - Turn on always the regulator state of VAP_VMIPI_1.0V because if VAP_VMIPI_1.0V is off state or would be not controlled by DRM driver, happen imprecise external abort. Changes from v1: - Remove useless brace - Remove unneeded 'regulators' keyword - Consolidate memory information in one entry Chanwoo Choi (3): ARM: dts: Add board dts file for Exynos3250-based Rinato board ARM: dts: Add sleep mode pin configuration for exynos3250-rinato ARM: dts: Add sleep mode of regulator for exynos3250-rinato board arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 16 + arch/arm/boot/dts/exynos3250-rinato.dts | 695 ++ 3 files changed, 713 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/exynos3250-rinato.dts -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv3 2/3] ARM: dts: Add sleep mode pin configuration for exynos3250-rinato
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 16
arch/arm/boot/dts/exynos3250-rinato.dts | 154 ++
2 files changed, 170 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c1..5ab81c3 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -12,6 +12,22 @@
* published by the Free Software Foundation.
*/
+#define PIN_PULL_NONE 0
+#define PIN_PULL_DOWN 1
+#define PIN_PULL_UP3
+
+#define PIN_PDN_OUT0 0
+#define PIN_PDN_OUT1 1
+#define PIN_PDN_INPUT 2
+#define PIN_PDN_PREV 3
+
+#define PIN_SLP(_pin, _mode, _pull)\
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-con-pdn = ; \
+ samsung,pin-pud-pdn = ; \
+ }
+
&pinctrl_0 {
gpa0: gpa0 {
gpio-controller;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index be0ba8d..7256eec 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -431,3 +431,157 @@
&xusbxti {
clock-frequency = <2400>;
};
+
+&pinctrl_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep0>;
+
+ sleep0: sleep-state {
+ PIN_SLP(gpa0-0, INPUT, DOWN);
+ PIN_SLP(gpa0-1, INPUT, DOWN);
+ PIN_SLP(gpa0-2, INPUT, DOWN);
+ PIN_SLP(gpa0-3, INPUT, DOWN);
+ PIN_SLP(gpa0-4, INPUT, DOWN);
+ PIN_SLP(gpa0-5, INPUT, DOWN);
+ PIN_SLP(gpa0-6, INPUT, DOWN);
+ PIN_SLP(gpa0-7, INPUT, DOWN);
+
+ PIN_SLP(gpa1-0, INPUT, DOWN);
+ PIN_SLP(gpa1-1, INPUT, DOWN);
+ PIN_SLP(gpa1-2, INPUT, DOWN);
+ PIN_SLP(gpa1-3, INPUT, DOWN);
+ PIN_SLP(gpa1-4, INPUT, DOWN);
+ PIN_SLP(gpa1-5, INPUT, DOWN);
+
+ PIN_SLP(gpb-0, PREV, NONE);
+ PIN_SLP(gpb-1, PREV, NONE);
+ PIN_SLP(gpb-2, PREV, NONE);
+ PIN_SLP(gpb-3, PREV, NONE);
+ PIN_SLP(gpb-4, INPUT, DOWN);
+ PIN_SLP(gpb-5, INPUT, DOWN);
+ PIN_SLP(gpb-6, INPUT, DOWN);
+ PIN_SLP(gpb-7, INPUT, DOWN);
+
+ PIN_SLP(gpc0-0, INPUT, DOWN);
+ PIN_SLP(gpc0-1, INPUT, DOWN);
+ PIN_SLP(gpc0-2, INPUT, DOWN);
+ PIN_SLP(gpc0-3, INPUT, DOWN);
+ PIN_SLP(gpc0-4, INPUT, DOWN);
+
+ PIN_SLP(gpc1-0, INPUT, DOWN);
+ PIN_SLP(gpc1-1, INPUT, DOWN);
+ PIN_SLP(gpc1-2, INPUT, DOWN);
+ PIN_SLP(gpc1-3, INPUT, DOWN);
+ PIN_SLP(gpc1-4, INPUT, DOWN);
+
+ PIN_SLP(gpd0-0, INPUT, DOWN);
+ PIN_SLP(gpd0-1, INPUT, DOWN);
+ PIN_SLP(gpd0-2, INPUT, NONE);
+ PIN_SLP(gpd0-3, INPUT, NONE);
+
+ PIN_SLP(gpd1-0, INPUT, NONE);
+ PIN_SLP(gpd1-1, INPUT, NONE);
+ PIN_SLP(gpd1-2, INPUT, NONE);
+ PIN_SLP(gpd1-3, INPUT, NONE);
+ };
+};
+
+&pinctrl_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep1>;
+
+ sleep1: sleep-state {
+ PIN_SLP(gpe0-0, PREV, NONE);
+ PIN_SLP(gpe0-1, PREV, NONE);
+ PIN_SLP(gpe0-2, INPUT, DOWN);
+ PIN_SLP(gpe0-3, INPUT, UP);
+ PIN_SLP(gpe0-4, INPUT, DOWN);
+ PIN_SLP(gpe0-5, INPUT, DOWN);
+ PIN_SLP(gpe0-6, INPUT, DOWN);
+ PIN_SLP(gpe0-7, INPUT, DOWN);
+
+ PIN_SLP(gpe1-0, INPUT, DOWN);
+ PIN_SLP(gpe1-1, PREV, NONE);
+ PIN_SLP(gpe1-2, INPUT, DOWN);
+ PIN_SLP(gpe1-3, INPUT, DOWN);
+ PIN_SLP(gpe1-4, INPUT, DOWN);
+ PIN_SLP(gpe1-5, INPUT, DOWN);
+ PIN_SLP(gpe1-6, INPUT, DOWN);
+ PIN_SLP(gpe1-7, INPUT, NONE);
+
+ PIN_SLP(gpe2-0, INPUT, NONE);
+ PIN_SLP(gpe2-1, INPUT, NONE);
+ PIN_SLP(gpe2-2, INPUT, NONE);
+
+ PIN_SLP(gpk0-0, INPUT, DOWN);
+ PIN_SLP(gpk0-1, INPUT, DOWN);
+ PIN_SLP(gpk0-2, OUT0, NONE);
+ PIN_SLP(gpk0-3, INPUT, DOWN);
+ PIN_SLP(gpk0-4, INPUT, DOWN);
+ PIN_SLP(gpk0-5, INPUT, DOWN);
+ PIN_SLP(gpk0-6, INPUT, DOWN);
+ PIN_SLP(gpk0-7, INPUT, DOWN);
+
+ PIN_SLP(gpk1-0, INPUT, DOWN);
+ PIN_SLP(gpk1-1, INPUT, DOWN);
+
[PATCHv3 1/3] ARM: dts: Add board dts file for Exynos3250-based Rinato board
This patch add support for device tree sources for Samsung Rinato baord
(Gear 2) based on Exynos3250 SoC.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC thermistor
- I2S of Exynos3250
- TMU of Exynos3250
- MFC of Exynos3250
- Secure firmware for Exynos3250 secondary cpu boot
- Serial ports of Exynos3250
- gpio-key for power key
Signed-off-by: Chanwoo Choi
Signed-off-by: Inki Dae
Signed-off-by: Seung-Woo Kim
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/exynos3250-rinato.dts | 433
2 files changed, 435 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/exynos3250-rinato.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4a75e29..91cd4d0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -67,7 +67,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-rinato.dtb \
+ exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
new file mode 100644
index 000..be0ba8d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -0,0 +1,433 @@
+/*
+ * Samsung's Exynos3250 based Rinato board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Rinato board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250.dtsi"
+#include
+
+/ {
+ model = "Samsung Rinato board";
+ compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
+
+ aliases {
+ i2c7 = &i2c_max77836;
+ };
+
+ memory {
+ reg = <0x4000 0x1ff0>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC1,115200N8 root=/dev/mmcblk0p15
rootwait earlyprintk panic=5";
+ };
+
+ firmware@0205F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0205F000 0x1000>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ power_key {
+ interrupt-parent = <&gpx2>;
+ interrupts = <7 0>;
+ gpios = <&gpx2 7 1>;
+ linux,code = ;
+ label = "power key";
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ vemmc_reg: voltage-regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_EMMC_2.8V-fixed";
+ regulator-min-microvolt = <280>;
+ regulator-max-microvolt = <280>;
+ gpio = <&gpk0 2 0>;
+ enable-active-high;
+ };
+
+ i2c_max77836: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ gpios = <&gpd0 2 0>, <&gpd0 3 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ max77836: subpmic@25 {
+ compatible = "maxim,max77836";
+ interrupt-parent = <&gpx1>;
+ interrupts = <5 0>;
+ reg = <0x25>;
+ wakeup;
+
+ muic: max77836-muic {
+ compatible = "maxim,max77836-muic";
+ };
+
+ regulators {
+ compatible = "maxim,max77836-regulator";
+ safeout_reg: SAFEOUT {
+ regulator-name = "SAFEOUT";
+ };
+
+ charger_reg: CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <45000>;
+ regulator-max-microamp = <475000>;
+ regulator-boot-on;
+ };
+
+ motor_reg: LDO1 {
+ regulator-name = "MOT_2.7V";
+ regulator-min-microvolt = <110>;
+ regulator-
[PATCHv2 1/2] clk: samsung: exynos4415: Add clocks using common clock framework
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 using common clock framework. The CMU (Clock Management Unit) of Exynos4415 controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses and function clocks for individual IPs. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Tomasz Figa Signed-off-by: Seung-Woo Kim Acked-by: Kyungmin Park --- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos4415.c | 1133 include/dt-bindings/clock/exynos4415.h | 360 ++ 3 files changed, 1494 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos4415.c create mode 100644 include/dt-bindings/clock/exynos4415.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8909c93..4561297 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o +obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c new file mode 100644 index 000..a4b6211 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos4415.c @@ -0,0 +1,1133 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Chanwoo Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos4415 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +#define SRC_LEFTBUS0x4200 +#define DIV_LEFTBUS0x4500 +#define GATE_IP_LEFTBUS0x4800 +#define GATE_IP_IMAGE 0x4930 +#define SRC_RIGHTBUS 0x8200 +#define DIV_RIGHTBUS 0x8500 +#define GATE_IP_RIGHTBUS 0x8800 +#define GATE_IP_PERIR 0x8960 +#define EPLL_LOCK 0xc010 +#define G3D_PLL_LOCK 0xc020 +#define DISP_PLL_LOCK 0xc030 +#define ISP_PLL_LOCK 0xc040 +#define EPLL_CON0 0xc110 +#define EPLL_CON1 0xc114 +#define EPLL_CON2 0xc118 +#define G3D_PLL_CON0 0xc120 +#define G3D_PLL_CON1 0xc124 +#define G3D_PLL_CON2 0xc128 +#define ISP_PLL_CON0 0xc130 +#define ISP_PLL_CON1 0xc134 +#define ISP_PLL_CON2 0xc138 +#define DISP_PLL_CON0 0xc140 +#define DISP_PLL_CON1 0xc144 +#define DISP_PLL_CON2 0xc148 +#define SRC_TOP0 0xc210 +#define SRC_TOP1 0xc214 +#define SRC_CAM0xc220 +#define SRC_TV 0xc224 +#define SRC_MFC0xc228 +#define SRC_G3D0xc22c +#define SRC_LCD0xc234 +#define SRC_ISP0xc238 +#define SRC_MAUDIO 0xc23c +#define SRC_FSYS 0xc240 +#define SRC_PERIL0 0xc250 +#define SRC_PERIL1 0xc254 +#define SRC_CAM1 0xc258 +#define SRC_TOP_ISP0 0xc25c +#define SRC_TOP_ISP1 0xc260 +#define SRC_MASK_TOP 0xc310 +#define SRC_MASK_CAM 0xc320 +#define SRC_MASK_TV0xc324 +#define SRC_MASK_LCD 0xc334 +#define SRC_MASK_ISP 0xc338 +#define SRC_MASK_MAUDIO0xc33c +#define SRC_MASK_FSYS 0xc340 +#define SRC_MASK_PERIL00xc350 +#define SRC_MASK_PERIL10xc354 +#define DIV_TOP0xc510 +#define DIV_CAM0xc520 +#define DIV_TV 0xc524 +#define DIV_MFC0xc528 +#define DIV_G3D0xc52c +#define DIV_LCD0xc534 +#define DIV_ISP0xc538 +#define DIV_MAUDIO 0xc53c +#define DIV_FSYS0 0xc540 +#define DIV_FSYS1 0xc544 +#define DIV_FSYS2 0xc548 +#define DIV_PERIL0 0xc550 +#define DIV_PERIL1 0xc554 +#define DIV_PERIL2 0xc558 +#define DIV_PERIL3 0xc55c +#define DIV_PERIL4 0xc560 +#define DIV_PERIL5 0xc564 +#define DIV_CAM1 0xc568 +#define DIV_TOP_ISP1 0xc56c +#define DIV_TOP_ISP0 0xc570 +#define CLKDIV2_RATIO 0xc580 +#define GATE_SCLK_CAM 0xc820 +#define GATE_SCLK_TV 0xc824 +#define GATE_SCLK_MFC 0xc828 +#define GATE_SCLK_G3D 0xc82c +#define GATE_SCLK_L
[PATCHv2 2/2] clk: samsung: Document binding for Exynos4415 clock controller
This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
.../devicetree/bindings/clock/exynos4415-clock.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos4415-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
new file mode 100644
index 000..847d98b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
@@ -0,0 +1,38 @@
+* Samsung Exynos4415 Clock Controller
+
+The Exynos4415 clock controller generates and supplies clock to various
+consumer devices within the Exynos4415 SoC.
+
+Required properties:
+
+- compatible: should be one of the following:
+ - "samsung,exynos4415-cmu" - for the main system clocks controller
+(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
+ - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
+Controller (DMC) domain clock controller.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4415.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ cmu: clock-controller@1003 {
+ compatible = "samsung,exynos4415-cmu";
+ reg = <0x1003 0x18000>;
+ #clock-cells = <1>;
+ };
+
+ cmu-dmc: clock-controller@105C {
+ compatible = "samsung,exynos4415-cmu-dmc";
+ reg = <0x105C 0x3000>;
+ #clock-cells = <1>;
+ };
--
1.8.5.5
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[PATCHv2 0/2] clk: samsung: Add clock controller driver for Exynos4415 SoC
This patch adds new clock controller device driver for Exynos4415 SoC. Changes from v1: - Separate only clock patches from Exynos4415 patchset[1] [1] [PATCH 0/5] Support new Exynos4415 SoC based on Cortex-A9 quad cores : https://lkml.org/lkml/2014/10/19/253 - Fix string issue on documentation file of Exynos4415 clock controller Chanwoo Choi (2): clk: samsung: exynos4415: Add clocks using common clock framework clk: samsung: Document binding for Exynos4415 clock controller .../devicetree/bindings/clock/exynos4415-clock.txt | 38 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos4415.c | 1133 include/dt-bindings/clock/exynos4415.h | 360 +++ 4 files changed, 1532 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos4415-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos4415.c create mode 100644 include/dt-bindings/clock/exynos4415.h -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 10/24/2014 07:54 PM, Sylwester Nawrocki wrote: > On 20/10/14 05:32, Chanwoo Choi wrote: >> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses >> and function clocks for individual IPs. >> >> Cc: Sylwester Nawrocki >> Cc: Tomasz Figa >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Tomasz Figa >> Signed-off-by: Seung-Woo Kim >> Acked-by: Kyungmin Park > > The patch looks good to me, I've applied it to my tree and will > be sending in a pull request to Mike next week, if there is no > objections. Thanks, I'll send new patchset(v2) for following Exynos4412 patches right now. clk: samsung: exynos4415: Add clocks using common clock framework clk: samsung: Document binding for Exynos4415 clock controller Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 20/10/14 05:32, Chanwoo Choi wrote: > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 > using common clock framework. The CMU (Clock Management Unit) of Exynos4415 > controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses > and function clocks for individual IPs. > > Cc: Sylwester Nawrocki > Cc: Tomasz Figa > Signed-off-by: Chanwoo Choi > Signed-off-by: Tomasz Figa > Signed-off-by: Seung-Woo Kim > Acked-by: Kyungmin Park The patch looks good to me, I've applied it to my tree and will be sending in a pull request to Mike next week, if there is no objections. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] clk: samsung: Document binding for Exynos4415 clock controller
Hi Sylwester,
On 10/24/2014 07:32 PM, Sylwester Nawrocki wrote:
> On 20/10/14 05:32, Chanwoo Choi wrote:
>> The Exynos4415 clocks are statically listed and registered using the
>> Samsung specific common clock helper functions. Both device tree based
>> clock lookup and clkdev based clock lookups are supported.
>
> I think the above text is not relevant, DT binding is not supposed
> to depend on any OS. Instead I would just put here something like:
>
> "This patch adds DT binding documentation for Exynos4415 SoC system
> clock controllers."
OK, I will modify it as your comment.
>
>> Cc: Sylwester Nawrocki
>> Cc: Tomasz Figa
>> Signed-off-by: Chanwoo Choi
>> Acked-by: Kyungmin Park
>> ---
>> .../devicetree/bindings/clock/exynos4415-clock.txt | 49
>> ++
>> 1 file changed, 49 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/exynos4415-clock.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
>> new file mode 100644
>> index 000..8aa4f4f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
>> @@ -0,0 +1,49 @@
>> +* Samsung Exynos4415 Clock Controller
>> +
>> +The Exynos4415 clock controller generates and supplies clock to various
>> +controllers within the Exynos4415 SoC.
>
> s/controllers/consumer devices/ ?
>
>> +
>> +Required Properties:
>
> s/P/p/ ?
I'll fix it.
>
>> +
>> +- compatible: should be one of the following.
>
> s/./:/ ?
I will change it (. -> :)
>
>> + - "samsung,exynos4415-cmu" - controller compatible with Exynos4415 SoC.
>
>>From current description it seems "samsung,exynos4415-cmu-dmc" is compatible
> with "samsung,exynos4415-cmu", which is not the case AFAIK.
> Perhaps we should change description here to something along the lines of:
>
> - "samsung,exynos4415-cmu" - for the main system clocks controller
> (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains),
>
>> + - "samsung,exynos4415-cmu-dmc" - controller compatible with
>> +Exynos4415 SoC for Dynamic Memory Controller domain.
>
> This seems unclear, how about
>
> - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
> Controller (DMC) domain clock controller.
>
> ?
OK, I'll modify it
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +Each clock is assigned an identifier and client nodes can use this
>> identifier
>> +to specify the clock which they consume.
>> +
>> +All available clocks are defined as preprocessor macros in
>> +dt-bindings/clock/exynos4415.h header and can be used in device
>> +tree sources.
>
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> +cmu: clock-controller@1003 {
>> +compatible = "samsung,exynos4415-cmu";
>> +reg = <0x1003 0x18000>;
>> +#clock-cells = <1>;
>> +};
>> +
>> +cmu-dmc: clock-controller@105C {
>> +compatible = "samsung,exynos4415-cmu-dmc";
>> +reg = <0x105C 0x3000>;
>> +#clock-cells = <1>;
>> +};
>> +
>> +Example 2: UART controller node that consumes the clock generated by the
>> clock
>> + controller. Refer to the standard clock bindings for information
>> + about 'clocks' and 'clock-names' property.
>> +
>> +serial_0: serial@1380 {
>> +compatible = "samsung,exynos4210-uart";
>> +reg = <0x1380 0x100>;
>> +interrupts = <0 109 0>;
>> +clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
>> +clock-names = "uart", "clk_uart_baud0";
>> +};
>
> I think we could omit those example snippets, it's all generic stuff and
> there is already plenty examples in descriptions of the DT binding for
> other SoCs.
OK, I'll drop this example.
Thanks for your review.
Best Regards,
Chanwoo Choi
>
> --
> Regards,
> Sylwester
>
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Re: [PATCH 3/5] clk: samsung: Document binding for Exynos4415 clock controller
On 20/10/14 05:32, Chanwoo Choi wrote:
> The Exynos4415 clocks are statically listed and registered using the
> Samsung specific common clock helper functions. Both device tree based
> clock lookup and clkdev based clock lookups are supported.
I think the above text is not relevant, DT binding is not supposed
to depend on any OS. Instead I would just put here something like:
"This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers."
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Acked-by: Kyungmin Park
> ---
> .../devicetree/bindings/clock/exynos4415-clock.txt | 49
> ++
> 1 file changed, 49 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/exynos4415-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
> b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
> new file mode 100644
> index 000..8aa4f4f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
> @@ -0,0 +1,49 @@
> +* Samsung Exynos4415 Clock Controller
> +
> +The Exynos4415 clock controller generates and supplies clock to various
> +controllers within the Exynos4415 SoC.
s/controllers/consumer devices/ ?
> +
> +Required Properties:
s/P/p/ ?
> +
> +- compatible: should be one of the following.
s/./:/ ?
> + - "samsung,exynos4415-cmu" - controller compatible with Exynos4415 SoC.
>From current description it seems "samsung,exynos4415-cmu-dmc" is compatible
with "samsung,exynos4415-cmu", which is not the case AFAIK.
Perhaps we should change description here to something along the lines of:
- "samsung,exynos4415-cmu" - for the main system clocks controller
(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains),
> + - "samsung,exynos4415-cmu-dmc" - controller compatible with
> +Exynos4415 SoC for Dynamic Memory Controller domain.
This seems unclear, how about
- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
Controller (DMC) domain clock controller.
?
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +
> +- #clock-cells: should be 1.
> +
> +Each clock is assigned an identifier and client nodes can use this identifier
> +to specify the clock which they consume.
> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/exynos4415.h header and can be used in device
> +tree sources.
> +Example 1: An example of a clock controller node is listed below.
> +
> + cmu: clock-controller@1003 {
> + compatible = "samsung,exynos4415-cmu";
> + reg = <0x1003 0x18000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu-dmc: clock-controller@105C {
> + compatible = "samsung,exynos4415-cmu-dmc";
> + reg = <0x105C 0x3000>;
> + #clock-cells = <1>;
> + };
> +
> +Example 2: UART controller node that consumes the clock generated by the
> clock
> +controller. Refer to the standard clock bindings for information
> +about 'clocks' and 'clock-names' property.
> +
> + serial_0: serial@1380 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x1380 0x100>;
> + interrupts = <0 109 0>;
> + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
> + clock-names = "uart", "clk_uart_baud0";
> + };
I think we could omit those example snippets, it's all generic stuff and
there is already plenty examples in descriptions of the DT binding for
other SoCs.
--
Regards,
Sylwester
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[PATCH] iommu: exynos: make driver multiarch friendly
Initialize all structures and register to iommu subsystem only on Exynos
compatible platforms.
Signed-off-by: Marek Szyprowski
Acked-by: Arnd Bergmann
---
drivers/iommu/exynos-iommu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 7423318..a77350e 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1188,6 +1189,11 @@ static int __init exynos_iommu_init(void)
{
int ret;
+ if (!of_machine_is_compatible("samsung,exynos3") &&
+ !of_machine_is_compatible("samsung,exynos4") &&
+ !of_machine_is_compatible("samsung,exynos5"))
+ return -ENODEV;
+
lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
if (!lv2table_kmem_cache) {
--
1.9.2
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Re: [RFC 1/2] PM / Domains: Power on domain early during system resume
On czw, 2014-10-23 at 19:20 +0300, Grygorii Strashko wrote: > Hi Krzysztof, > > On 10/23/2014 04:48 PM, Krzysztof Kozlowski wrote: > > When resuming the system the power domain has to be powered on early so > > any runtime PM aware devices could resume. > > > > This fixes following scenario reproduced on Exynos DRM: > > 1. Power domain is off before suspending the system. > > 2. System is suspended to RAM. > > 3. Resuming starts. The Exynos DRM driver resume callback is called. > > 4. The Exynos DRM driver calls drm_helper_resume_force_mode which turns > > the screen on by calling exynos_dsi_dpms with DRM_MODE_DPMS_ON. > > 5. The Exynos DSI driver calls pm_runtime_get. The driver runtime > > resumes and this should turn LCD power domain on. > > 6. Unfortunately the domain cannot be turned on because system resume is > > in progress and genpd->prepared_count is positive. > > Just interesting, what value will be returned by pm_runtime_enabled() > from any of your .resume() callback (for any device which belongs to > some Generic PM domain)? exynos_drm_resume: false exynos_dsi_enable: true Full backtrace leading to exynos_dsi_enable: [ 37.944830] [ cut here ] [ 37.944860] WARNING: CPU: 0 PID: 3125 at drivers/gpu/drm/exynos/exynos_drm_dsi.c:1360 exynos_dsi_dpms+0xc0/0x398() [ 37.944869] Modules linked in: [ 37.944883] CPU: 0 PID: 3125 Comm: bash Tainted: GW 3.17.0-next-20141020-00050-g844ed80678d5-dirty #479 [ 37.944923] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [ 37.944949] [] (show_stack) from [] (dump_stack+0x70/0xbc) [ 37.944977] [] (dump_stack) from [] (warn_slowpath_common+0x64/0x88) [ 37.944992] [] (warn_slowpath_common) from [] (warn_slowpath_null+0x1c/0x24) [ 37.945011] [] (warn_slowpath_null) from [] (exynos_dsi_dpms+0xc0/0x398) [ 37.945024] [] (exynos_dsi_dpms) from [] (exynos_drm_encoder_commit+0x24/0x40) [ 37.945044] [] (exynos_drm_encoder_commit) from [] (drm_crtc_helper_set_mode+0x400/0x4e8) [ 37.945057] [] (drm_crtc_helper_set_mode) from [] (drm_helper_resume_force_mode+0x68/0x124) [ 37.945083] [] (drm_helper_resume_force_mode) from [] (exynos_drm_resume+0x80/0x90) [ 37.945100] [] (exynos_drm_resume) from [] (platform_pm_resume+0x2c/0x4c) [ 37.945118] [] (platform_pm_resume) from [] (dpm_run_callback.isra.7+0x2c/0x64) [ 37.945130] [] (dpm_run_callback.isra.7) from [] (device_resume+0xac/0x180) [ 37.945141] [] (device_resume) from [] (dpm_resume+0xe8/0x20c) [ 37.945152] [] (dpm_resume) from [] (dpm_resume_end+0xc/0x18) [ 37.945175] [] (dpm_resume_end) from [] (suspend_devices_and_enter+0x230/0x3c8) [ 37.945190] [] (suspend_devices_and_enter) from [] (pm_suspend+0x268/0x29c) [ 37.945202] [] (pm_suspend) from [] (state_store+0x6c/0xbc) [ 37.945220] [] (state_store) from [] (kobj_attr_store+0x14/0x20) [ 37.945235] [] (kobj_attr_store) from [] (sysfs_kf_write+0x44/0x48) [ 37.945245] [] (sysfs_kf_write) from [] (kernfs_fop_write+0xc0/0x17c) [ 37.945268] [] (kernfs_fop_write) from [] (vfs_write+0xa0/0x1a8) [ 37.945282] [] (vfs_write) from [] (SyS_write+0x40/0x8c) [ 37.945299] [] (SyS_write) from [] (ret_fast_syscall+0x0/0x30) [ 37.945307] ---[ end trace e930e0edfd9a5ad2 ]--- > I'm asking, because as I can see Runtime PM can be disabled from > pm_genpd_prepare(). > > Thank you. > > Oh. I've just found that you might get this issue if you will try to do > suspend when PM domain is ON ;) > > Any way, In my opinion, It might be better to fix pm_genpd_prepare() so > it will not increment prepared_count when initial state of the GPD is > GPD_STATE_POWER_OFF. Seems it's needed only in opposite case - > when state of GPD has to be restored from pm_genpd_resume_noirq(). That sounds good but what about cases when the device will runtime resume during suspend (early at suspend)? Actually I seen this with framebuffer console. Right after starting suspend the console is flushed and poked which leads to powering on LCD. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
