s3c2443 hangs on msleep on resume from suspend
Hello. I'm developing on Samsung s3c2443 CPU and now my aim is to make suspend mode working properly. My kernel version is 3.6. Everything was OK, however Linux hanged on resume, if usb ohci driver was loaded. My investigation showed, that it hangs on msleep function, that is getting called in ohci_run() function in drivers/usb/host/ohci-hcd.c file. Exact line of code is [1]. I found on the web, that there was [2] similar problem on s3c2410. The reason of hang is that msleep locks the only working thread in system, and nobody can unlock it. The simple workaround is to replace msleep with mdelay. But the usage of msleep is in platform-independent usb-ohci code. That means, that other platforms somehow bypass this problem, and work with msleep correctly. But I will prefer to fix it in platform-depended, than to make workaround in common code. What bugs in platform-depended code could lead to such problem? I suggest, that there is some problem with sequence of resume actions, and usb resume happens much earlier, than it have to. But where exactly should I search for the problem? Thanks, Alexander. [1] http://lxr.free-electrons.com/source/drivers/usb/host/ohci-hcd.c?v=3.6;a=arm#L621 [2] http://osdir.com/ml/handhelds.openmoko.kernel/2008-05/msg00168.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
sdhci-s3c suspends immediately
Hello. I'm trying to bring up sdhci-s3c driver on S3C2443 SOC. It seems to initialize correctly, but immediately after that it get suspended by some force. This turns off all interrupts, so SD controller doesn't work. I don't know, where suspend command comes from, but whole system stay in working state. I've recorded some boot log with extended verbose for a driver. It is attached. I want to understand, why and where does this command come from. And how to turn it off. Now there is no suspend support working on my board, but i don't want to turn suspend (PM runtime) off at all, because it may be need to set it up in future. Please, help. sdhci: Secure Digital Host Controller Interface driver sdhci: Copyright(c) Pierre Ossman s3c-sdhci s3c-sdhci.1: clock source 0: mmc_busclk.0 (13350 Hz) s3c-sdhci s3c-sdhci.1: clock source 2: mmc_busclk.2 (9600 Hz) sdhci_add_host sdhci_clear_set_irqs clear -1 set 16711683 sdhci_clear_set_irqs clear -1 set 16711683 sdhci_set_card_detection 1 sdhci_clear_set_irqs clear 0 set 64 mmc0: SDHCI controller on samsung-hsmmc [s3c-sdhci.1] using PIO sdhci_set_card_detection 1 sdhci_clear_set_irqs clear 0 set 64 sdhci_runtime_suspend_host [c000e820] (unwind_backtrace+0x0/0x12c) from [c03948f4] (dump_stack+0x20/0x24) [c03948f4] (dump_stack+0x20/0x24) from [c02b0a8c] (sdhci_runtime_suspend_host+0x24/0x90) [c02b0a8c] (sdhci_runtime_suspend_host+0x24/0x90) from [c02b24a0] (sdhci_s3c_runtime_suspend+0x24/0x48) [c02b24a0] (sdhci_s3c_runtime_suspend+0x24/0x48) from [c01f4560] (pm_generic_runtime_suspend+0x40/0x54) [c01f4560] (pm_generic_runtime_suspend+0x40/0x54) from [c01f85c0] (__rpm_callback+0x40/0x5c) [c01f85c0] (__rpm_callback+0x40/0x5c) from [c01f8c38] (rpm_suspend+0x2b0/0x498) [c01f8c38] (rpm_suspend+0x2b0/0x498) from [c01f9b08] (__pm_runtime_suspend+0x50/0x60) [c01f9b08] (__pm_runtime_suspend+0x50/0x60) from [c01f4c08] (pm_generic_runtime_idle+0x58/0x60) [c01f4c08] (pm_generic_runtime_idle+0x58/0x60) from [c01f85c0] (__rpm_callback+0x40/0x5c) [c01f85c0] (__rpm_callback+0x40/0x5c) from [c01f902c] (rpm_idle+0x1a4/0x23c) [c01f902c] (rpm_idle+0x1a4/0x23c) from [c01f9180] (__pm_runtime_idle+0x50/0x60) [c01f9180] (__pm_runtime_idle+0x50/0x60) from [c01ef91c] (driver_probe_device+0x2f0/0x34c) [c01ef91c] (driver_probe_device+0x2f0/0x34c) from [c01ef9e4] (__driver_attach+0x6c/0x8c) [c01ef9e4] (__driver_attach+0x6c/0x8c) from [c01edccc] (bus_for_each_dev+0x64/0x94) [c01edccc] (bus_for_each_dev+0x64/0x94) from [c01ef260] (driver_attach+0x28/0x30) [c01ef260] (driver_attach+0x28/0x30) from [c01eec40] (bus_add_driver+0xd0/0x24c) [c01eec40] (bus_add_driver+0xd0/0x24c) from [c01eff9c] (driver_register+0xac/0x13c) [c01eff9c] (driver_register+0xac/0x13c) from [c01f1110] (platform_driver_register+0x54/0x68) [c01f1110] (platform_driver_register+0x54/0x68) from [c0517fc0] (sdhci_s3c_driver_init+0x14/0x1c) [c0517fc0] (sdhci_s3c_driver_init+0x14/0x1c) from [c00085c8] (do_one_initcall+0xb8/0x188) [c00085c8] (do_one_initcall+0xb8/0x188) from [c0391228] (kernel_init+0xfc/0x2a4) [c0391228] (kernel_init+0xfc/0x2a4) from [c0009250] (ret_from_fork+0x14/0x20) sdhci_clear_set_irqs clear -1 set 0 usbcore: registered new interface driver usbhid usbhid: USB HID core driver sdhci_clear_set_irqs clear -1 set 16711683 sdhci_set_card_detection 1 sdhci_clear_set_irqs clear 0 set 64 oprofile: hardware counters not available oprofile: using timer interrupt. TCP: cubic registered NET: Registered protocol family 17 rtc-ds1307 0-0068: setting system clock to 2013-04-12 11:56:23 UTC (1365767783) ALSA device list: No soundcards found. RAMDISK: cramfs filesystem found at block 0 RAMDISK: Loading 11468KiB [1 disk] into ram disk... sdhci_runtime_suspend_host [c000e820] (unwind_backtrace+0x0/0x12c) from [c03948f4] (dump_stack+0x20/0x24) [c03948f4] (dump_stack+0x20/0x24) from [c02b0a8c] (sdhci_runtime_suspend_host+0x24/0x90) [c02b0a8c] (sdhci_runtime_suspend_host+0x24/0x90) from [c02b24a0] (sdhci_s3c_runtime_suspend+0x24/0x48) [c02b24a0] (sdhci_s3c_runtime_suspend+0x24/0x48) from [c01f4560] (pm_generic_runtime_suspend+0x40/0x54) [c01f4560] (pm_generic_runtime_suspend+0x40/0x54) from [c01f85c0] (__rpm_callback+0x40/0x5c) [c01f85c0] (__rpm_callback+0x40/0x5c) from [c01f8c38] (rpm_suspend+0x2b0/0x498) [c01f8c38] (rpm_suspend+0x2b0/0x498) from [c01f9c38] (pm_runtime_work+0x80/0x9c) [c01f9c38] (pm_runtime_work+0x80/0x9c) from [c0032fc0] (process_one_work+0x26c/0x3e8) [c0032fc0] (process_one_work+0x26c/0x3e8) from [c00349d8] (worker_thread+0x290/0x394) [c00349d8] (worker_thread+0x290/0x394) from [c0039444] (kthread+0xb8/0xc4) [c0039444] (kthread+0xb8/0xc4) from [c0009250] (ret_from_fork+0x14/0x20) sdhci_clear_set_irqs clear -1 set 0 usb 1-1: new full-speed USB device number 2 using s3c2410-ohci sdhci_clear_set_irqs clear -1 set 16711683 sdhci_set_card_detection 1 sdhci_clear_set_irqs clear 0 set 64 sdhci_clear_set_irqs clear -1 set 16711683 sdhci_set_card_detection 1 sdhci_clear_set_irqs
Re: Help connect s3c2410-lcd device to SMDK2443
06.02.2013 02:17, Heiko Stübner пишет: Hi Alexander, Am Dienstag, 5. Februar 2013, 20:36:20 schrieb Alexander Varnin: Hello. I'm trying to setup s3c2410-lcd device on SMDK2443 with 3.6 kernel. On requesting interrupt it fails with EINVAL: ~ # dmesg | grep lcd s3c2410-lcd s3c2410-lcd: cannot get irq 32 - err -22 s3c2410-lcd: probe of s3c2410-lcd failed with error -16 If I remember correctly the s3c2443 has a new-style framebuffer. So using the s3c2410-fb/lcd driver is the wrong approach. The correct driver to use would be the s3cfb. Take a look at mach-smdk2416.c which uses this driver. The init for the s3c2443 should probably be similar. Also the irq you requested is a parent irq to different lcd-irqs in the sub- register on the s3c2443 and s3c2416. Therfore requesting it directly is disabled by the irq-subsystem. Hope that helps Heiko Thank you for help. I have used s3c-fb driver and all is ok. The interrupt is not busy by something else. Here is my table: ~ # cat /proc/interrupts CPU0 17: 0 s3c-ext0 s3c-mci 30: 409934 s3c S3C2410 Timer Tick 37: 0 s3c s3c-mci 42:416 s3c ohci_hcd:usb1 43: 0 s3c s3c2410-i2c 56: 1 s3c-ext uio_mcross 57: 72585 s3c-ext eth0 73: 63 s3c-uart1 s3c2440-uart 74:108 s3c-uart1 s3c2440-uart 97: 0 - s3c2410-wdt Err: Please, help me to find the reason. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Help connect s3c2410-lcd device to SMDK2443
Hello. I'm trying to setup s3c2410-lcd device on SMDK2443 with 3.6 kernel. On requesting interrupt it fails with EINVAL: ~ # dmesg | grep lcd s3c2410-lcd s3c2410-lcd: cannot get irq 32 - err -22 s3c2410-lcd: probe of s3c2410-lcd failed with error -16 The interrupt is not busy by something else. Here is my table: ~ # cat /proc/interrupts CPU0 17: 0 s3c-ext0 s3c-mci 30: 409934 s3c S3C2410 Timer Tick 37: 0 s3c s3c-mci 42:416 s3c ohci_hcd:usb1 43: 0 s3c s3c2410-i2c 56: 1 s3c-ext uio_mcross 57: 72585 s3c-ext eth0 73: 63 s3c-uart1 s3c2440-uart 74:108 s3c-uart1 s3c2440-uart 97: 0 - s3c2410-wdt Err: Please, help me to find the reason. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: S3C2443: introduce soc_is_s3c2443 macro
Signed-off-by: Alexander Varnin fenix...@mail.ru --- arch/arm/plat-samsung/include/plat/cpu.h | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index ace4451..613f492 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -23,6 +23,9 @@ extern unsigned long samsung_cpu_id; #define S3C24XX_CPU_ID 0x3240 #define S3C24XX_CPU_MASK 0xFFF0 +#define S3C2443_CPU_ID 0x32443001 +#define S3C2443_CPU_MASK 0x + #define S3C6400_CPU_ID 0x3640 #define S3C6410_CPU_ID 0x3641 #define S3C64XX_CPU_MASK 0xF000 @@ -52,6 +55,7 @@ static inline int is_samsung_##name(void) \ } IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) +IS_SAMSUNG_CPU(s3c2443, S3C2443_CPU_ID, S3C2443_CPU_MASK) IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) @@ -72,6 +76,12 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_s3c24xx() 0 #endif +#if defined(CONFIG_CPU_S3C2443) +# define soc_is_s3c2443() is_samsung_s3c2443() +#else +# define soc_is_s3c2443() 0 +#endif + #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) # define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) #else -- 1.7.2.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: S3C2443: Workaround for 2443 EXTINT error
S3C2443 CPU has a problem with incorrect reading from EXTINTn
registers. So s3c_irqext_type function wrongly modifies them.
So add special check to s3c_irqext_type, to handle this case.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
arch/arm/plat-s3c24xx/irq.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..bb36fc9 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -219,6 +219,21 @@ s3c_irqext_type(struct irq_data *data, unsigned int type)
}
value = __raw_readl(extint_reg);
+
+ if( (samsung_cpu_id 0xf) == 0x43001) //Hack for 2443 error
workaround
+ {
+ int i;
+ int fixed = 0;
+ if(extint_reg == S3C24XX_EXTINT1 || extint_reg == S3C24XX_EXTINT2)
+ for(i=0; i7;i++)
+ fixed |= (((value ((7-i)*4+1)) 7) | ((value
((7-i)*4-3)) 8)) i*4;
+ else
+ for(i=0; i7;i++)
+ fixed |= ( (value (7-i)*4) 0xf ) i*4;
+ fixed |= (((value1) 7) | ((value3) 8)) 27;
+ value = fixed;
+ }
+
value = (value ~(7 extint_offset)) | (newvalue extint_offset);
__raw_writel(value, extint_reg);
--
1.7.2.5
--
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Re: [PATCH 2/2] ARM: S3C2443: Workaround for 2443 EXTINT error
Sorry, an old version.
26.11.2012 12:40, Alexander Varnin пишет:
S3C2443 CPU has a problem with incorrect reading from EXTINTn
registers. So s3c_irqext_type function wrongly modifies them.
So add special check to s3c_irqext_type, to handle this case.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
arch/arm/plat-s3c24xx/irq.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..bb36fc9 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -219,6 +219,21 @@ s3c_irqext_type(struct irq_data *data, unsigned int type)
}
value = __raw_readl(extint_reg);
+
+ if( (samsung_cpu_id 0xf) == 0x43001) //Hack for 2443 error
workaround
+ {
+ int i;
+ int fixed = 0;
+ if(extint_reg == S3C24XX_EXTINT1 || extint_reg == S3C24XX_EXTINT2)
+ for(i=0; i7;i++)
+ fixed |= (((value ((7-i)*4+1)) 7) | ((value ((7-i)*4-3))
8)) i*4;
+ else
+ for(i=0; i7;i++)
+ fixed |= ( (value (7-i)*4) 0xf ) i*4;
+ fixed |= (((value1) 7) | ((value3) 8)) 27;
+ value = fixed;
+ }
+
value = (value ~(7 extint_offset)) | (newvalue extint_offset);
__raw_writel(value, extint_reg);
--
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[PATCH 2/2] ARM: S3C2443: Workaround for 2443 EXTINT error
S3C2443 CPU has a problem with incorrect reading from EXTINTn
registers. So s3c_irqext_type function wrongly modifies them.
So add special check to s3c_irqext_type, to handle this case.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
arch/arm/plat-s3c24xx/irq.c | 26 ++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..ed19996 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -219,6 +219,32 @@ s3c_irqext_type(struct irq_data *data, unsigned int type)
}
value = __raw_readl(extint_reg);
+
+ /*
+ * S3C2443 CPU has a problem with EXTINTn registers.
+ * Essentially register-reads returned transformed data, but the write
+ * is done according to the datasheet.
+ *
+ * There is hack introduced for 2443 error workaround.
+ *
+ * For detais refer to the document S3C2443 GUIDE TO EXTRA GPIO found
on the web.
+ *
+ * A. Varnin fenix...@mail.ru
+ */
+ if(soc_is_s3c2443())
+ {
+ int i;
+ int fixed = 0;
+ if(extint_reg == S3C24XX_EXTINT1 || extint_reg ==
S3C24XX_EXTINT2)
+ for(i=0; i7;i++)
+ fixed |= (((value ((7-i)*4+1)) 7) |
((value ((7-i)*4-3)) 8)) i*4;
+ else
+ for(i=0; i7;i++)
+ fixed |= ( (value (7-i)*4) 0xf ) i*4;
+ fixed |= (((value1) 7) | ((value3) 8)) 27;
+ value = fixed;
+ }
+
value = (value ~(7 extint_offset)) | (newvalue extint_offset);
__raw_writel(value, extint_reg);
--
1.7.2.5
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Re: [PATCH 2/2] ARM: S3C2443: Workaround for 2443 EXTINT error
Is it ok, to send only one last patch after changes, without the one,
who make macro?
26.11.2012 13:12, Heiko Stübner пишет:
Hi Alexander,
I think this patch needs a bit more love :-) .
Please run scripts/checkpatch.pl on it and fix all the reported problems.
And I'd change the comment to something like:
/*
* S3C2443 CPU has a problem with EXTINTn registers.
* Essentially register-reads return transformed data, but the write
* is done according to the datasheet.
*
* Fix this by transforming the read data to the correct format.
*
* For details refer to the document S3C2443 GUIDE TO EXTRA GPIO
*/
Especially the mail address does not need to be in the code - the git history
preserves the committer identity quite well.
Heiko
Am Montag, 26. November 2012, 09:44:41 schrieb Alexander Varnin:
S3C2443 CPU has a problem with incorrect reading from EXTINTn
registers. So s3c_irqext_type function wrongly modifies them.
So add special check to s3c_irqext_type, to handle this case.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
arch/arm/plat-s3c24xx/irq.c | 26 ++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..ed19996 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -219,6 +219,32 @@ s3c_irqext_type(struct irq_data *data, unsigned int
type) }
value = __raw_readl(extint_reg);
+
+ /*
+ * S3C2443 CPU has a problem with EXTINTn registers.
+ * Essentially register-reads returned transformed data, but the write
+ * is done according to the datasheet.
+ *
+ * There is hack introduced for 2443 error workaround.
+ *
+ * For detais refer to the document S3C2443 GUIDE TO EXTRA GPIO found
on
the web. + *
+ * A. Varnin fenix...@mail.ru
+ */
+ if(soc_is_s3c2443())
+ {
+ int i;
+ int fixed = 0;
+ if(extint_reg == S3C24XX_EXTINT1 || extint_reg ==
S3C24XX_EXTINT2)
+ for(i=0; i7;i++)
+ fixed |= (((value ((7-i)*4+1)) 7) | ((value
((7-
i)*4-3))
8)) i*4; + else
+ for(i=0; i7;i++)
+ fixed |= ( (value (7-i)*4) 0xf ) i*4;
+ fixed |= (((value1) 7) | ((value3) 8)) 27;
+ value = fixed;
+ }
+
value = (value ~(7 extint_offset)) | (newvalue extint_offset);
__raw_writel(value, extint_reg);
--
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[PATCH v2 2/2] ARM: S3C2443: Workaround for 2443 EXTINT error
S3C2443 CPU has a problem with incorrect reading from EXTINTn
registers. So s3c_irqext_type function wrongly modifies them.
So add special check to s3c_irqext_type, to handle this case.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
styling and comment fixes
arch/arm/plat-s3c24xx/irq.c | 25 +
1 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..b05c573 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -219,6 +219,31 @@ s3c_irqext_type(struct irq_data *data, unsigned int type)
}
value = __raw_readl(extint_reg);
+
+ /*
+* S3C2443 CPU has a problem with EXTINTn registers.
+* Essentially register-reads return transformed data, but the write
+* is done according to the datasheet.
+*
+* Fix this by transforming the read data to the correct format.
+*
+* For details refer to the document S3C2443 GUIDE TO EXTRA GPIO
+*/
+ if (soc_is_s3c2443()) {
+ int i;
+ int fixed = 0;
+ if (extint_reg == S3C24XX_EXTINT1
+ || extint_reg == S3C24XX_EXTINT2)
+ for (i = 0; i 7; i++)
+ fixed |= (((value ((7-i)*4+1)) 7)
+ | ((value ((7-i)*4-3)) 8)) i*4;
+ else
+ for (i = 0; i 7; i++)
+ fixed |= ((value (7-i)*4) 0xf) i*4;
+ fixed |= (((value1) 7) | ((value3) 8)) 27;
+ value = fixed;
+ }
+
value = (value ~(7 extint_offset)) | (newvalue extint_offset);
__raw_writel(value, extint_reg);
--
1.7.2.5
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Re: [PATCH] ARM: S3C2443: Workaround for 2443 EXTINT error
I've done it within another function, because otherwise users of other chips would pay for a one more runtime check, which they don't need. On the other hand, this function get called not so frequently, to make it valueable. The first version of my patch i've used internally worked as you said, so i can resend it. I want to ask more experienced users of s3c2443. If this problem occures on all s3c2443 chips, or only with some series of it? Maybe we need some more checks, not to break working cases. 24.11.2012 04:16, Heiko Stübner пишет: What does this do or what should it do? Also it gets calculated but never used? And please use scripts/checkpatch.pl to verify your patch follows coding guidelines, as this block is especially hard to read. So essentially register-reads somehow returned transformed data, but the write is done according to the datasheet. It would definitely be better to integrate it into the existing _irqext_type function instead of introducing a second one. The cpu_id is present in the samsung_cpu_id var and the list of cpus including the s3c2443 can be found in common.c. With this it would be possible to identify when the irq code is run on a s3c2443 machine and the original _irqext_type function could change the behaviour accordingly. Not sure if it would make sense to introduce soc_is_s3c2443() etc macros for this. And of course the actual block doing the transformation on read would need a more elaborate comment on the why and how, because in 3 years someone might not directly see what this does and why it was necessary. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: S3C2443: SPI clock channel setup is fixed
I also want to point, that irq resource in arch/arm/plat-samsung/devs.c
for s3c2410-spi driver on S3C2443 points to wrong IRQ (SPI0 instead of
SPI1). I've solved it with board specific code, but it is not most
correct way, i think.
20.11.2012 15:46, Kukjin Kim пишет:
Alexander Varnin wrote:
Actually, SPI channel 0 on 2443 is mapped to HS SPI controller,
and to enable s3c2410-spi controller, we should power on channel
1 in PCLKCON. There is no channel 0 SPI on s3c2443, so delete its
clock.
Signed-off-by: Alexander Varnin fenix...@mail.ru
Reviewed-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c24xx/clock-s3c2443.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c
b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 7f689ce..bdaba59 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -158,12 +158,6 @@ static struct clk init_clocks_off[] = {
.devname= s3c2410-spi.0,
.parent = clk_p,
.enable = s3c2443_clkcon_enable_p,
- .ctrlbit= S3C2443_PCLKCON_SPI0,
- }, {
- .name = spi,
- .devname= s3c2410-spi.1,
- .parent = clk_p,
- .enable = s3c2443_clkcon_enable_p,
.ctrlbit= S3C2443_PCLKCON_SPI1,
}
};
--
1.7.2.5
Applied, thanks.
K-Gene kg...@kernel.org
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[PATCH] ARM: S3C2443: Workaround for 2443 EXTINT error
S3C2443 CPU has a problem with incorrect reading from EXTINTn
registers. So s3c_irqext_type function wrongly modifies them.
So add special function for s3c2443, to handle this case.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
arch/arm/mach-s3c24xx/s3c2443.c |8
arch/arm/plat-s3c24xx/irq.c | 89 +++
2 files changed, 97 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index ab648ad..99eef31 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -67,8 +67,11 @@ void s3c2443_restart(char mode, const char *cmd)
__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
}
+extern int s3c2443_irqext_type(struct irq_data *data, unsigned int type);
+
int __init s3c2443_init(void)
{
+ struct irq_chip * chip;
printk(S3C2443: Initialising architecture\n);
s3c_nand_setname(s3c2412-nand);
@@ -81,6 +84,11 @@ int __init s3c2443_init(void)
s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
+ chip = irq_get_chip(IRQ_EINT0);
+ chip-irq_set_type=s3c2443_irqext_type;
+ chip = irq_get_chip(IRQ_EINT4);
+ chip-irq_set_type=s3c2443_irqext_type;
+
return device_register(s3c2443_dev);
}
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..9c815f3 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -224,7 +224,96 @@ s3c_irqext_type(struct irq_data *data, unsigned int type)
return 0;
}
+#if defined(CONFIG_CPU_S3C2443)
+int
+s3c2443_irqext_type(struct irq_data *data, unsigned int type)
+{
+ int i;
+ int fixed;
+ void __iomem *extint_reg;
+ void __iomem *gpcon_reg;
+ unsigned long gpcon_offset, extint_offset;
+ unsigned long newvalue = 0, value;
+
+ if ((data-irq = IRQ_EINT0) (data-irq = IRQ_EINT3)) {
+ gpcon_reg = S3C2410_GPFCON;
+ extint_reg = S3C24XX_EXTINT0;
+ gpcon_offset = (data-irq - IRQ_EINT0) * 2;
+ extint_offset = (data-irq - IRQ_EINT0) * 4;
+ } else if ((data-irq = IRQ_EINT4) (data-irq = IRQ_EINT7)) {
+ gpcon_reg = S3C2410_GPFCON;
+ extint_reg = S3C24XX_EXTINT0;
+ gpcon_offset = (data-irq - (EXTINT_OFF)) * 2;
+ extint_offset = (data-irq - (EXTINT_OFF)) * 4;
+ } else if ((data-irq = IRQ_EINT8) (data-irq = IRQ_EINT15)) {
+ gpcon_reg = S3C2410_GPGCON;
+ extint_reg = S3C24XX_EXTINT1;
+ gpcon_offset = (data-irq - IRQ_EINT8) * 2;
+ extint_offset = (data-irq - IRQ_EINT8) * 4;
+ } else if ((data-irq = IRQ_EINT16) (data-irq = IRQ_EINT23)) {
+ gpcon_reg = S3C2410_GPGCON;
+ extint_reg = S3C24XX_EXTINT2;
+ gpcon_offset = (data-irq - IRQ_EINT8) * 2;
+ extint_offset = (data-irq - IRQ_EINT16) * 4;
+ } else {
+ return -1;
+ }
+ /* Set the GPIO to external interrupt mode */
+ value = __raw_readl(gpcon_reg);
+ value = (value ~(3 gpcon_offset)) | (0x02 gpcon_offset);
+ __raw_writel(value, gpcon_reg);
+
+ /* Set the external interrupt to pointed trigger type */
+ switch (type)
+ {
+ case IRQ_TYPE_NONE:
+ printk(KERN_WARNING No edge setting!\n);
+ break;
+
+ case IRQ_TYPE_EDGE_RISING:
+ newvalue = S3C2410_EXTINT_RISEEDGE;
+ break;
+
+ case IRQ_TYPE_EDGE_FALLING:
+ newvalue = S3C2410_EXTINT_FALLEDGE;
+ break;
+
+ case IRQ_TYPE_EDGE_BOTH:
+ newvalue = S3C2410_EXTINT_BOTHEDGE;
+ break;
+
+ case IRQ_TYPE_LEVEL_LOW:
+ newvalue = S3C2410_EXTINT_LOWLEV;
+ break;
+
+ case IRQ_TYPE_LEVEL_HIGH:
+ newvalue = S3C2410_EXTINT_HILEV;
+ break;
+
+ default:
+ printk(KERN_ERR No such irq type %d, type);
+ return -1;
+ }
+
+ value = __raw_readl(extint_reg);
+ //Hack for 2443 error workaround
+ fixed = 0;
+ if(extint_reg == S3C24XX_EXTINT1 || extint_reg == S3C24XX_EXTINT2)
+ for(i=0; i7;i++)
+ fixed |= (((value ((7-i)*4+1)) 7) | ((value
((7-i)*4-3)) 8)) i*4;
+ else
+ for(i=0; i7;i++)
+ fixed |= ( (value (7-i)*4) 0xf ) i*4;
+fixed |= (((value1) 7) | ((value3) 8)) 27;
+ value = fixed;
+
+ value = (value ~(7 extint_offset)) | (newvalue extint_offset);
+ __raw_writel(value, extint_reg);
+
+ return 0;
+}
+#endif
[PATCH] ARM: S3C2443: SPI clock channel setup is fixed
Actually, SPI channel 0 on 2443 is mapped to HS SPI controller,
and to enable s3c2410-spi controller, we should power on channel
1 in PCLKCON. There is no channel 0 SPI on s3c2443, so delete its
clock.
Signed-off-by: Alexander Varnin fenix...@mail.ru
---
arch/arm/mach-s3c24xx/clock-s3c2443.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c
b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 7f689ce..bdaba59 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -158,12 +158,6 @@ static struct clk init_clocks_off[] = {
.devname= s3c2410-spi.0,
.parent = clk_p,
.enable = s3c2443_clkcon_enable_p,
- .ctrlbit= S3C2443_PCLKCON_SPI0,
- }, {
- .name = spi,
- .devname= s3c2410-spi.1,
- .parent = clk_p,
- .enable = s3c2443_clkcon_enable_p,
.ctrlbit= S3C2443_PCLKCON_SPI1,
}
};
--
1.7.2.5
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[PATCH] ARM: S3C2443: SPI clock channel setup is fixed
Actually, SPI channel 0 on 2443 is mapped to HS SPI controller,
and to enable s3c2410-spi controller, we should power on channel
1 in PCLKCON. There is no channel 0 SPI on s3c2443, so delete its
clock.
Signed-off-by: Alexander Varnin fenix...@mail.ru
Reviewed-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c24xx/clock-s3c2443.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c
b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 7f689ce..bdaba59 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -158,12 +158,6 @@ static struct clk init_clocks_off[] = {
.devname= s3c2410-spi.0,
.parent = clk_p,
.enable = s3c2443_clkcon_enable_p,
- .ctrlbit= S3C2443_PCLKCON_SPI0,
- }, {
- .name = spi,
- .devname= s3c2410-spi.1,
- .parent = clk_p,
- .enable = s3c2443_clkcon_enable_p,
.ctrlbit= S3C2443_PCLKCON_SPI1,
}
};
--
1.7.2.5
