[PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 using common clock framework. The CMU (Clock Management Unit) of Exynos4415 controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses and function clocks for individual IPs. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Tomasz Figa Signed-off-by: Seung-Woo Kim Acked-by: Kyungmin Park --- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos4415.c | 1133 include/dt-bindings/clock/exynos4415.h | 360 ++ 3 files changed, 1494 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos4415.c create mode 100644 include/dt-bindings/clock/exynos4415.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 6fb4bc6..d8535e6 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o +obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c new file mode 100644 index 000..a4b6211 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos4415.c @@ -0,0 +1,1133 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Chanwoo Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos4415 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +#define SRC_LEFTBUS0x4200 +#define DIV_LEFTBUS0x4500 +#define GATE_IP_LEFTBUS0x4800 +#define GATE_IP_IMAGE 0x4930 +#define SRC_RIGHTBUS 0x8200 +#define DIV_RIGHTBUS 0x8500 +#define GATE_IP_RIGHTBUS 0x8800 +#define GATE_IP_PERIR 0x8960 +#define EPLL_LOCK 0xc010 +#define G3D_PLL_LOCK 0xc020 +#define DISP_PLL_LOCK 0xc030 +#define ISP_PLL_LOCK 0xc040 +#define EPLL_CON0 0xc110 +#define EPLL_CON1 0xc114 +#define EPLL_CON2 0xc118 +#define G3D_PLL_CON0 0xc120 +#define G3D_PLL_CON1 0xc124 +#define G3D_PLL_CON2 0xc128 +#define ISP_PLL_CON0 0xc130 +#define ISP_PLL_CON1 0xc134 +#define ISP_PLL_CON2 0xc138 +#define DISP_PLL_CON0 0xc140 +#define DISP_PLL_CON1 0xc144 +#define DISP_PLL_CON2 0xc148 +#define SRC_TOP0 0xc210 +#define SRC_TOP1 0xc214 +#define SRC_CAM0xc220 +#define SRC_TV 0xc224 +#define SRC_MFC0xc228 +#define SRC_G3D0xc22c +#define SRC_LCD0xc234 +#define SRC_ISP0xc238 +#define SRC_MAUDIO 0xc23c +#define SRC_FSYS 0xc240 +#define SRC_PERIL0 0xc250 +#define SRC_PERIL1 0xc254 +#define SRC_CAM1 0xc258 +#define SRC_TOP_ISP0 0xc25c +#define SRC_TOP_ISP1 0xc260 +#define SRC_MASK_TOP 0xc310 +#define SRC_MASK_CAM 0xc320 +#define SRC_MASK_TV0xc324 +#define SRC_MASK_LCD 0xc334 +#define SRC_MASK_ISP 0xc338 +#define SRC_MASK_MAUDIO0xc33c +#define SRC_MASK_FSYS 0xc340 +#define SRC_MASK_PERIL00xc350 +#define SRC_MASK_PERIL10xc354 +#define DIV_TOP0xc510 +#define DIV_CAM0xc520 +#define DIV_TV 0xc524 +#define DIV_MFC0xc528 +#define DIV_G3D0xc52c +#define DIV_LCD0xc534 +#define DIV_ISP0xc538 +#define DIV_MAUDIO 0xc53c +#define DIV_FSYS0 0xc540 +#define DIV_FSYS1 0xc544 +#define DIV_FSYS2 0xc548 +#define DIV_PERIL0 0xc550 +#define DIV_PERIL1 0xc554 +#define DIV_PERIL2 0xc558 +#define DIV_PERIL3 0xc55c +#define DIV_PERIL4 0xc560 +#define DIV_PERIL5 0xc564 +#define DIV_CAM1 0xc568 +#define DIV_TOP_ISP1 0xc56c +#define DIV_TOP_ISP0 0xc570 +#define CLKDIV2_RATIO 0xc580 +#define GATE_SCLK_CAM 0xc820 +#define GATE_SCLK_TV 0xc824 +#define GATE_SCLK_MFC 0xc828 +#define GATE_SCLK_G3D 0xc82c +#define GATE_SCLK_LCD
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 20/10/14 05:32, Chanwoo Choi wrote: > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 > using common clock framework. The CMU (Clock Management Unit) of Exynos4415 > controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses > and function clocks for individual IPs. > > Cc: Sylwester Nawrocki > Cc: Tomasz Figa > Signed-off-by: Chanwoo Choi > Signed-off-by: Tomasz Figa > Signed-off-by: Seung-Woo Kim > Acked-by: Kyungmin Park The patch looks good to me, I've applied it to my tree and will be sending in a pull request to Mike next week, if there is no objections. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 10/24/2014 07:54 PM, Sylwester Nawrocki wrote: > On 20/10/14 05:32, Chanwoo Choi wrote: >> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses >> and function clocks for individual IPs. >> >> Cc: Sylwester Nawrocki >> Cc: Tomasz Figa >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Tomasz Figa >> Signed-off-by: Seung-Woo Kim >> Acked-by: Kyungmin Park > > The patch looks good to me, I've applied it to my tree and will > be sending in a pull request to Mike next week, if there is no > objections. Thanks, I'll send new patchset(v2) for following Exynos4412 patches right now. clk: samsung: exynos4415: Add clocks using common clock framework clk: samsung: Document binding for Exynos4415 clock controller Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 > using common clock framework. The CMU (Clock Management Unit) of Exynos4415 > controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses > and function clocks for individual IPs. There seems to be a lot in common here with other exynos4 variants in clk-exynos4.c. Have you considered just adding support for the 4415 in the existing driver? Thanks Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 24.10.2014 15:18, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses >> and function clocks for individual IPs. > > There seems to be a lot in common here with other exynos4 variants in > clk-exynos4.c. Have you considered just adding support for the 4415 in > the existing driver? I tried when I was still at Samsung and the outcome was far from being nice. There are certain differences, such as separate address spaces of few clock controllers and different bit fields in apparently similar registers, which made resulting code quite ugly. Also another advantage of separate driver is that it can be made without duplicating initial fails of the driver for Exynos4, such as private bindings for external clocks or clock controllers in different power domains grouped together into one big logical clock controller, because at development time they looked so (contiguous address space). Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
Hi Daniel, On 10/24/2014 10:18 PM, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses >> and function clocks for individual IPs. > > There seems to be a lot in common here with other exynos4 variants in > clk-exynos4.c. Have you considered just adding support for the 4415 in > the existing driver? Yes, It is difficult and to make existing clk-exynos4.c more complicated. Exynos4415 has fewer difference from existing clk-exynos4.c and different parent source of mux. For exmaple about PLL, There are different PLLs between Exynos4412 and Exynos4415. - Exynos4412 has APLL, MPLL, EPLL, VPLL. - Exynos4415 has APLL, EPLL, G3D_PLL, ISP_PLL, DISP_PLL and MPLL. Also, MPLL of Exynos4415 was included in CMU_DMC scope. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework
On 24/10/14 15:18, Daniel Drake wrote: > On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote: >> > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9 >> > using common clock framework. The CMU (Clock Management Unit) of Exynos4415 >> > controls PLLs(Phase Locked Loops) and generates system clocks for CPU, >> > buses >> > and function clocks for individual IPs. > > There seems to be a lot in common here with other exynos4 variants in > clk-exynos4.c. Have you considered just adding support for the 4415 in > the existing driver? I would rather avoid mixing clock description tables for more SoCs in clk-exynos4.c. There is quite a few differences between exynos4x12 and exynos4415 clock controllers, I'm afraid merging exynos4415 support to clk-exynos4.c would just create more branches and made the code harder to follow, without much decrease in code size. The clock tree in single SoC is already complex, without consolidating support for several SoCs in one unit. -- Regards, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
