Re: [RFC v3 PATCH v2 10/16] drm/exynos: dsi: add driver data to support Exynos5420
Hi Andrzej,
Thank you for comments.
On 05/05/2014 08:27 PM, Andrzej Hajda wrote:
On 04/27/2014 03:50 AM, YoungJun Cho wrote:
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Changelog v2:
- Moves exynos_dsi_enable_clocks() after exynos_dsi_reset()
(commented by Andrzej Hajda)
- Splits D-PHY control setting routines from PLL setting one
(commented by Andrzej Hajda)
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 154 ++-
1 file changed, 132 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 4a918ec..c18dba3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
#include
@@ -54,9 +55,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x)(((x) & 0xf) << 0)
@@ -200,6 +204,21 @@
#define DSIM_PLL_M(x) ((x) << 4)
#define DSIM_PLL_S(x) ((x) << 1)
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -233,6 +252,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZEDBIT(1)
#define DSIM_STATE_CMD_LPMBIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -262,11 +287,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+ { .compatible = "samsung,exynos5420-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+ { }
+};
I raise again issue of compatible string.
Since exynos5410 DSIM contains DSIM_VERSION register, it is better
to use this register instead of compatible string to distinguish
device versions. So as a compatible we should use the first exynos
chipset containing this field. AFAIK it is exynos5410.
So the only thing you should do is to change compatible string from
samsung,exynos5420-mipi-dsi to samsung,exynos5410-mipi-dsi.
I posted RFC v3 without this try.
Because there is no exynos5410 relevant DTS yet,
and making exynos5410 DTS is out of scope for this RFC.
It is irrelevant.
Ok, I'll fix it.
Thank you.
Best regards YJ
Regards
Andrzej
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+ return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -340,14 +393,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigne
Re: [RFC v3 PATCH v2 10/16] drm/exynos: dsi: add driver data to support Exynos5420
On 04/27/2014 03:50 AM, YoungJun Cho wrote:
> The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
> from the one in Exynos4 SoC.
>
> In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
> and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
> So this patch adds driver data to distinguish it.
>
> Changelog v2:
> - Moves exynos_dsi_enable_clocks() after exynos_dsi_reset()
> (commented by Andrzej Hajda)
> - Splits D-PHY control setting routines from PLL setting one
> (commented by Andrzej Hajda)
>
> Signed-off-by: YoungJun Cho
> Acked-by: Inki Dae
> Acked-by: Kyungmin Park
> ---
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 154
> ++-
> 1 file changed, 132 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index 4a918ec..c18dba3 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -17,6 +17,7 @@
>
> #include
> #include
> +#include
> #include
> #include
>
> @@ -54,9 +55,12 @@
>
> /* FIFO memory AC characteristic register */
> #define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
> -#define DSIM_PLLTMR_REG 0x50/* PLL timer register */
> #define DSIM_PHYACCHR_REG0x54/* D-PHY AC characteristic register */
> #define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
> +#define DSIM_PHYCTRL_REG 0x5c
> +#define DSIM_PHYTIMING_REG 0x64
> +#define DSIM_PHYTIMING1_REG 0x68
> +#define DSIM_PHYTIMING2_REG 0x6c
>
> /* DSIM_STATUS */
> #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
> @@ -200,6 +204,21 @@
> #define DSIM_PLL_M(x)((x) << 4)
> #define DSIM_PLL_S(x)((x) << 1)
>
> +/* DSIM_PHYTIMING */
> +#define DSIM_PHYTIMING_LPX(x)((x) << 8)
> +#define DSIM_PHYTIMING_HS_EXIT(x)((x) << 0)
> +
> +/* DSIM_PHYTIMING1 */
> +#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
> +#define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
> +#define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
> +#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
> +
> +/* DSIM_PHYTIMING2 */
> +#define DSIM_PHYTIMING2_HS_PREPARE(x)((x) << 16)
> +#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
> +#define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
> +
> #define DSI_MAX_BUS_WIDTH4
> #define DSI_NUM_VIRTUAL_CHANNELS 4
> #define DSI_TX_FIFO_SIZE 2048
> @@ -233,6 +252,12 @@ struct exynos_dsi_transfer {
> #define DSIM_STATE_INITIALIZED BIT(1)
> #define DSIM_STATE_CMD_LPM BIT(2)
>
> +struct exynos_dsi_driver_data {
> + unsigned int plltmr_reg;
> +
> + unsigned int has_freqband:1;
> +};
> +
> struct exynos_dsi {
> struct mipi_dsi_host dsi_host;
> struct drm_connector connector;
> @@ -262,11 +287,39 @@ struct exynos_dsi {
>
> spinlock_t transfer_lock; /* protects transfer_list */
> struct list_head transfer_list;
> +
> + struct exynos_dsi_driver_data *driver_data;
> };
>
> #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
> #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
>
> +static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
> + .plltmr_reg = 0x50,
> + .has_freqband = 1,
> +};
> +
> +static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
> + .plltmr_reg = 0x58,
> +};
> +
> +static struct of_device_id exynos_dsi_of_match[] = {
> + { .compatible = "samsung,exynos4210-mipi-dsi",
> + .data = &exynos4_dsi_driver_data },
> + { .compatible = "samsung,exynos5420-mipi-dsi",
> + .data = &exynos5_dsi_driver_data },
> + { }
> +};
I raise again issue of compatible string.
Since exynos5410 DSIM contains DSIM_VERSION register, it is better
to use this register instead of compatible string to distinguish
device versions. So as a compatible we should use the first exynos
chipset containing this field. AFAIK it is exynos5410.
So the only thing you should do is to change compatible string from
samsung,exynos5420-mipi-dsi to samsung,exynos5410-mipi-dsi.
>
> I posted RFC v3 without this try.
>
> Because there is no exynos5410 relevant DTS yet,
> and making exynos5410 DTS is out of scope for this RFC.
It is irrelevant.
Regards
Andrzej
> +
> +static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
> + struct platform_device *pdev)
> +{
> + const struct of_device_id *of_id =
> + of_match_device(exynos_dsi_of_match, &pdev->dev);
> +
> + return (struct exynos_dsi_driver_data *)of_id->data;
> +}
> +
> static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
> {
> if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
> @@ -340,14 +393,9 @@ static unsigned long ex
Re: [RFC v3 PATCH v2 10/16] drm/exynos: dsi: add driver data to support Exynos5420
Hi Sachin,
Thank you for comment.
I'll fix.
Thank you.
Best regards YJ
On 04/30/2014 12:26 AM, Sachin Kamat wrote:
On 27 April 2014 07:20, YoungJun Cho wrote:
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Changelog v2:
- Moves exynos_dsi_enable_clocks() after exynos_dsi_reset()
(commented by Andrzej Hajda)
- Splits D-PHY control setting routines from PLL setting one
(commented by Andrzej Hajda)
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 154 ++-
1 file changed, 132 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 4a918ec..c18dba3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
#include
@@ -54,9 +55,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -200,6 +204,21 @@
#define DSIM_PLL_M(x) ((x) << 4)
#define DSIM_PLL_S(x) ((x) << 1)
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -233,6 +252,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
Shouldn't this be static?
+ unsigned int plltmr_reg;
+
nit: stray blank line
+ unsigned int has_freqband:1;
+};
+
+static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
+{
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+ u32 reg;
+
+ if (driver_data->has_freqband)
+ return;
+
+ /* B D-PHY */
+ reg = 0x0af & 0x1ff;
Please use macros instead of magic numbers.
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Re: [RFC v3 PATCH v2 10/16] drm/exynos: dsi: add driver data to support Exynos5420
On 27 April 2014 07:20, YoungJun Cho wrote:
> The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
> from the one in Exynos4 SoC.
>
> In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
> and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
> So this patch adds driver data to distinguish it.
>
> Changelog v2:
> - Moves exynos_dsi_enable_clocks() after exynos_dsi_reset()
> (commented by Andrzej Hajda)
> - Splits D-PHY control setting routines from PLL setting one
> (commented by Andrzej Hajda)
>
> Signed-off-by: YoungJun Cho
> Acked-by: Inki Dae
> Acked-by: Kyungmin Park
> ---
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 154
> ++-
> 1 file changed, 132 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index 4a918ec..c18dba3 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -17,6 +17,7 @@
>
> #include
> #include
> +#include
> #include
> #include
>
> @@ -54,9 +55,12 @@
>
> /* FIFO memory AC characteristic register */
> #define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
> -#define DSIM_PLLTMR_REG0x50/* PLL timer register */
> #define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
> #define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1
> */
> +#define DSIM_PHYCTRL_REG 0x5c
> +#define DSIM_PHYTIMING_REG 0x64
> +#define DSIM_PHYTIMING1_REG0x68
> +#define DSIM_PHYTIMING2_REG0x6c
>
> /* DSIM_STATUS */
> #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
> @@ -200,6 +204,21 @@
> #define DSIM_PLL_M(x) ((x) << 4)
> #define DSIM_PLL_S(x) ((x) << 1)
>
> +/* DSIM_PHYTIMING */
> +#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
> +#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
> +
> +/* DSIM_PHYTIMING1 */
> +#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
> +#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
> +#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
> +#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
> +
> +/* DSIM_PHYTIMING2 */
> +#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
> +#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
> +#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
> +
> #define DSI_MAX_BUS_WIDTH 4
> #define DSI_NUM_VIRTUAL_CHANNELS 4
> #define DSI_TX_FIFO_SIZE 2048
> @@ -233,6 +252,12 @@ struct exynos_dsi_transfer {
> #define DSIM_STATE_INITIALIZED BIT(1)
> #define DSIM_STATE_CMD_LPM BIT(2)
>
> +struct exynos_dsi_driver_data {
Shouldn't this be static?
> + unsigned int plltmr_reg;
> +
nit: stray blank line
> + unsigned int has_freqband:1;
> +};
> +
> +static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
> +{
> + struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
> + u32 reg;
> +
> + if (driver_data->has_freqband)
> + return;
> +
> + /* B D-PHY */
> + reg = 0x0af & 0x1ff;
Please use macros instead of magic numbers.
--
With warm regards,
Sachin
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[RFC v3 PATCH v2 10/16] drm/exynos: dsi: add driver data to support Exynos5420
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Changelog v2:
- Moves exynos_dsi_enable_clocks() after exynos_dsi_reset()
(commented by Andrzej Hajda)
- Splits D-PHY control setting routines from PLL setting one
(commented by Andrzej Hajda)
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 154 ++-
1 file changed, 132 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 4a918ec..c18dba3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
#include
@@ -54,9 +55,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -200,6 +204,21 @@
#define DSIM_PLL_M(x) ((x) << 4)
#define DSIM_PLL_S(x) ((x) << 1)
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -233,6 +252,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -262,11 +287,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+ { .compatible = "samsung,exynos5420-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+ return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -340,14 +393,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -368,18 +416,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
"failed to find PLL PMS for requested frequency\n");
return -EFAULT;
}
+
