[linux-sunxi] Re: [PATCH] PWM kernel module for the Allwinner A10 SOC for 3.4 series kernels
Hi! I found these problems: When I set the period = 100hz PWM is not working. I read parameters period = 1 duty = 5000 duty_percent = 50 polarity = 0 pulse = 0 pin = PB2 run = 1 When I stop PWM output pin level remains high. Wishes: Level at the output pin when stopping PWM must match the parameter polarity. When I change the polarity must change the output pin level. Thanks! -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH u-boot-sunxi v2 12/13] ARM: sunxi: Add gmac clock macros
Add macros for gmac clock control, instead of using raw values.
Also add comment noting GMAC ahb gate is in second gate register,
to avoid confusion over same offset as EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index b4e540e..b39de3a 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -172,6 +172,8 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB_OHCI0 2
#define AHB_GATE_OFFSET_USB_EHCI0 1
#define AHB_GATE_OFFSET_USB0
+
+/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
#define CCM_AHB_GATE_GPS (0x1 26)
@@ -223,6 +225,12 @@ struct sunxi_ccm_reg {
#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
#define CCM_MBUS_CTRL_GATE (0x1 31)
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII (0x0 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 2)
+
#ifndef __ASSEMBLY__
int clock_init(void);
--
1.8.5.2
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[linux-sunxi] [PATCH u-boot-sunxi v2 00/13] Add GMAC support to u-boot
Hi everyone, This patch series add support for GMAC on Cubieboard2 and Cubietruck, using the designware driver already in u-boot. The patch series should be applied over the current 'sunxi' branch in linux-sunxi/u-boot-sunxi. The work was started by Jens Kuske (jemk), which enabled the GMAC on CubieTruck under 10/100 speeds. Then I added gigabit, pin drive level and Cubieboard 2 support. Ma Haijun picked out an incorrect mask in the pin setup code. There is one modification to the original driver, which reduces the DMA burst length, to a value supported by the GMAC. This should probably be upstreamed. The remaining patches are all sunxi specific. Adding GMAC support to other A20 boards shoule be as simple as adding the proper defines to boards.cfg. Cheers, ChenYu Changes from v1: * Moved gmac initialization code into glue layer under drivers/net * Added and switched to gmac clock macros instead of magic numbers * Added comment on ahb0 vs ahb1 for GMAC clock gate offset * Added explanatory message to Ma Haijun's commit Chen-Yu Tsai (8): ARM: sunxi: Enable support for gigabit PHYs ARM: sunxi: Add functions to set pin drive levels ARM: sunxi: Set drive level for GMAC pins ARM: sunxi: GMAC driver phy interface based on config ARM: sunxi: Do not select unused GMAC pins under RGMII mode ARM: sunxi: Let cubieboard2 use the GMAC driver ARM: sunxi: Add gmac clock macros ARM: sunxi: Move GMAC init code into separate glue layer driver Jens Kuske (4): net/designware: Reduce DMA burst length ARM: sunxi: Add GMAC base address and clocks ARM: sunxi: Add GMAC driver ARM: sunxi: Let cubietruck use the GMAC driver Ma Haijun (1): ARM: sunxi: fix gpio drive mask arch/arm/cpu/armv7/sunxi/board.c| 7 - arch/arm/cpu/armv7/sunxi/pinmux.c | 18 + arch/arm/include/asm/arch-sunxi/clock.h | 11 arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h | 4 +++ boards.cfg | 8 +++--- drivers/net/Makefile| 1 + drivers/net/designware.c| 2 +- drivers/net/sunxi_gmac.c| 45 + include/configs/sunxi-common.h | 10 include/netdev.h| 1 + 11 files changed, 102 insertions(+), 6 deletions(-) create mode 100644 drivers/net/sunxi_gmac.c -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH u-boot-sunxi v2 04/13] ARM: sunxi: Let cubietruck use the GMAC driver
From: Jens Kuske jensku...@gmail.com Signed-off-by: Jens Kuske jensku...@gmail.com --- boards.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.cfg b/boards.cfg index 5d147e2..405cf56 100644 --- a/boards.cfg +++ b/boards.cfg @@ -364,8 +364,8 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS - Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS - -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_EMAC,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS - -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_EMAC,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS - +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS - Active arm armv7 sunxi - sunxi Cubieboard_512 sun4i:CUBIEBOARD_512,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi Cubieboard_FEL sun4i:CUBIEBOARD,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi DNS_M82 sun4i:DNS_M82,SPL - -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH u-boot-sunxi v2 09/13] ARM: sunxi: Do not select unused GMAC pins under RGMII mode
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 386b16e..5d19a64 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -160,7 +160,12 @@ int cpu_eth_init(bd_t *bis)
#endif
/* Configure pin mux settings for GMAC */
- for (pin = SUNXI_GPA(0); pin = SUNXI_GPA(17); pin++) {
+ for (pin = SUNXI_GPA(0); pin = SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
+ /* skip unused pins in RGMII mode */
+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+ continue;
+#endif
sunxi_gpio_set_cfgpin(pin, 5);
sunxi_gpio_set_drv(pin, 3);
}
--
1.8.5.2
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[linux-sunxi] [PATCH u-boot-sunxi v2 13/13] ARM: sunxi: Move GMAC init code into separate glue layer driver
GMAC init code now exists in a glue layer driver under drivers/net,
instead of sunxi board initialization code. It has been cleaned up
to use macros for clock controls.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 32 +---
drivers/net/Makefile | 1 +
drivers/net/sunxi_gmac.c | 45
include/netdev.h | 1 +
4 files changed, 48 insertions(+), 31 deletions(-)
create mode 100644 drivers/net/sunxi_gmac.c
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 5d19a64..003570a 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -145,37 +145,7 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_SUNXI_EMAC
sunxi_emac_initialize(bis);
#else
- int pin;
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* Set up clock gating */
- setbits_le32(ccm-ahb_gate1, 0x1 AHB_GATE_OFFSET_GMAC);
-
- /* Set MII clock */
-#ifdef CONFIG_RGMII
- setbits_le32(ccm-gmac_clk_cfg, (0x1 2) | (0x2 0));
-#else
- setbits_le32(ccm-gmac_clk_cfg, 0);
-#endif
-
- /* Configure pin mux settings for GMAC */
- for (pin = SUNXI_GPA(0); pin = SUNXI_GPA(16); pin++) {
-#ifdef CONFIG_RGMII
- /* skip unused pins in RGMII mode */
- if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
- continue;
-#endif
- sunxi_gpio_set_cfgpin(pin, 5);
- sunxi_gpio_set_drv(pin, 3);
- }
-
-#ifdef CONFIG_RGMII
- designware_initialize(0, SUNXI_GMAC_BASE, 0x1,
PHY_INTERFACE_MODE_RGMII);
-#else
- designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_MII);
-#endif
-
+ sunxi_gmac_initialize(bis);
#endif
return 0;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d905fef..136479d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_SMC9) += smc9.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
+obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
new file mode 100644
index 000..b8b9016
--- /dev/null
+++ b/drivers/net/sunxi_gmac.c
@@ -0,0 +1,45 @@
+#include common.h
+#include netdev.h
+#include miiphy.h
+#include asm/gpio.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+
+int sunxi_gmac_initialize(bd_t *bis)
+{
+ int pin;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set up clock gating */
+ setbits_le32(ccm-ahb_gate1, 0x1 AHB_GATE_OFFSET_GMAC);
+
+ /* Set MII clock */
+#ifdef CONFIG_RGMII
+ setbits_le32(ccm-gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(ccm-gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
+
+ /* Configure pin mux settings for GMAC */
+ for (pin = SUNXI_GPA(0); pin = SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
+ /* skip unused pins in RGMII mode */
+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+ continue;
+#endif
+ sunxi_gpio_set_cfgpin(pin, 5);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+
+#ifdef CONFIG_RGMII
+ designware_initialize(0, SUNXI_GMAC_BASE, 0x1,
PHY_INTERFACE_MODE_RGMII);
+#else
+ designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_MII);
+#endif
+
+ return 0;
+}
diff --git a/include/netdev.h b/include/netdev.h
index 16ee4ce..300664e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -80,6 +80,7 @@ int skge_initialize(bd_t *bis);
int smc9_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
int sunxi_emac_initialize(bd_t *bis);
+int sunxi_gmac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
--
1.8.5.2
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[linux-sunxi] [PATCH u-boot-sunxi v2 01/13] net/designware: Reduce DMA burst length
From: Jens Kuske jensku...@gmail.com The GMAC module in Allwinner sunxi SoCs seems to have problems with burst lenghts 8. Signed-off-by: Jens Kuske jensku...@gmail.com --- drivers/net/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4..865abe1 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -154,7 +154,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) /* Resore the HW MAC address as it has been lost during MAC reset */ dw_write_hwaddr(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, + writel(FIXEDBURST | PRIORXTX_41 | BURST_8, dma_p-busmode); writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD | -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] mmc errors
Hans what can I provide that will help us troubleshoot this. The cpu is an A20 on the cubieboard2 Could this be an error in the defconf or some other script? On Sat, Dec 21, 2013 at 12:54 PM, Hans de Goede hdego...@redhat.com wrote: Hi, On 12/20/2013 08:27 PM, Jonathan Aquilina wrote: The problem is that boot up doesn't complete Ah, I had missed the mmc0: error -110 whilst initialising SD card error, that one is not normal. No idea what is going here ... Regards, Hans On Friday 20 December 2013 20:25:25 Hans de Goede wrote: Hi, On 12/20/2013 04:30 PM, Jonathan Aquilina wrote: Hey guys I am getting these errors 3[mmc-err] smc 0 err, cmd 52, RTO [4.099702] [mmc-err] smc 0 err, cmd 52, RTO 3[mmc-err] smc 0 err, cmd 52, RTO [4.108190] [mmc-err] smc 0 err, cmd 52, RTO 6[mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.120891] [mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B 6[mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.141002] [mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B 3[mmc-err] smc 0 err, cmd 5, RTO [4.155772] [mmc-err] smc 0 err, cmd 5, RTO 3[mmc-err] smc 0 err, cmd 5, RTO [4.164081] [mmc-err] smc 0 err, cmd 5, RTO 3[mmc-err] smc 0 err, cmd 5, RTO [4.172399] [mmc-err] smc 0 err, cmd 5, RTO 3[mmc-err] smc 0 err, cmd 5, RTO [4.180703] [mmc-err] smc 0 err, cmd 5, RTO 6[mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.193950] [mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B 6[mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.211685] [mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B 6[mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.231790] [mmc-msg] sdc0 set ios: clk 40Hz bm PP pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B 3[mmc-err] smc 0 err, cmd 2, RTO [4.247141] [mmc-err] smc 0 err, cmd 2, RTO 3[mmc-err] smc 0 err, cmd 2, RTO [4.255473] [mmc-err] smc 0 err, cmd 2, RTO 3[mmc-err] smc 0 err, cmd 2, RTO [4.263814] [mmc-err] smc 0 err, cmd 2, RTO 3[mmc-err] smc 0 err, cmd 2, RTO [4.272123] [mmc-err] smc 0 err, cmd 2, RTO 3mmc0: error -110 whilst initialising SD card [4.280665] mmc0: error -110 whilst initialising SD card 6[mmc-msg] sdc0 set ios: clk 40Hz bm OD pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.294322] [mmc-msg] sdc0 set ios: clk 40Hz bm OD pm ON vdd 3.3V width 1 timing LEGACY(SDR12) dt B 3[mmc-err] smc 0 err, cmd 1, RTO [4.307746] [mmc-err] smc 0 err, cmd 1, RTO 6[mmc-msg] sdc0 set ios: clk 0Hz bm OD pm OFF vdd 3.3V width 1 timing LEGACY(SDR12) dt B [4.320013] [mmc-msg] sdc0 set ios: clk 0Hz bm OD pm OFF vdd 3.3V width 1 timing LEGACY(SDR12) dt B 6[mmc-msg] sdc0 power off [4.331589] [mmc-msg] sdc0 power off I am wondering what the issue is the memory card is not the issue at least not on native linux on a non embedded system. These errors are caused by the linux mmc subsystem making calls which only work on sdio devices (ie sdio wifi cards) which fail on sd-cards. This is only done during initial probing of the card when the mmc subsys tries to find out what kind of card is exactly connected. They can safely be ignored. Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out. -- Jonathan Aquilina -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
