[linux-sunxi] [PATCH 1/4] clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to module 0
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 57 +++
1 file changed, 57 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 25d99b6..19d9e9e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -330,6 +330,47 @@ static void sun4i_get_mod0_factors(u32 *freq, u32
parent_rate,
/**
+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
+ * CLK_OUT rate is calculated as follows
+ * rate = (parent_rate p) / (m + 1);
+ */
+
+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
+ u8 *n, u8 *k, u8 *m, u8 *p)
+{
+ u8 div, calcm, calcp;
+
+ /* These clocks can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency */
+ if (*freq parent_rate)
+ *freq = parent_rate;
+
+ div = parent_rate / *freq;
+
+ if (div 32)
+ calcp = 0;
+ else if (div / 2 32)
+ calcp = 1;
+ else if (div / 4 32)
+ calcp = 2;
+ else
+ calcp = 3;
+
+ calcm = DIV_ROUND_UP(div, 1 calcp);
+
+ *freq = (parent_rate calcp) / calcm;
+
+ /* we were called to round the frequency, we can now return */
+ if (n == NULL)
+ return;
+
+ *m = calcm - 1;
+ *p = calcp;
+}
+
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
@@ -384,6 +425,14 @@ static struct clk_factors_config sun4i_mod0_config = {
.pwidth = 2,
};
+/* user manual says n but it's really p */
+static struct clk_factors_config sun7i_a20_out_config = {
+ .mshift = 8,
+ .mwidth = 5,
+ .pshift = 20,
+ .pwidth = 2,
+};
+
static const struct factors_data sun4i_pll1_data __initconst = {
.enable = 31,
.table = sun4i_pll1_config,
@@ -414,6 +463,13 @@ static const struct factors_data sun4i_mod0_data
__initconst = {
.getter = sun4i_get_mod0_factors,
};
+static const struct factors_data sun7i_a20_out_data __initconst = {
+ .enable = 31,
+ .mux = 24,
+ .table = sun7i_a20_out_config,
+ .getter = sun7i_a20_get_out_factors,
+};
+
static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
const struct factors_data *data)
{
@@ -912,6 +968,7 @@ static const struct of_device_id clk_factors_match[]
__initconst = {
{.compatible = allwinner,sun6i-a31-pll1-clk, .data =
sun6i_a31_pll1_data,},
{.compatible = allwinner,sun4i-apb1-clk, .data = sun4i_apb1_data,},
{.compatible = allwinner,sun4i-mod0-clk, .data = sun4i_mod0_data,},
+ {.compatible = allwinner,sun7i-a20-out-clk, .data =
sun7i_a20_out_data,},
{}
};
--
1.8.5.2
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Re: [linux-sunxi] Sun8i (A23) spotted in the wild.
On 22-12-13 07:30, Patrick Wood wrote: The boot_clock in the .fex file is given as 1008. Maybe because they copy/pasted the fex? look at the 'extreme_freq' in the dvfs I think it was oliver On Friday, December 20, 2013 8:46:32 PM UTC-5, Runzhong Yi wrote: It could be possible since A23 can run as high as 1.8Ghz. If the core run as 1650MHz then this mean the dram clock is 1/3 of the core clock. 2013/12/21 Patrick Wood patric...@gmail.com javascript:: Am I reading the fex file correctly? The DRAM is running at 552 MHz? On Friday, December 20, 2013 9:08:07 AM UTC-5, Luc Verhaegen wrote: On Thu, Dec 19, 2013 at 12:32:24AM +0100, Luc Verhaegen wrote: I tried to order myself one of those cheap Q88 tablets with an A13 just now. Big was my surprise when i got it and popped it open, as i was staring at an A23. Bad news all round really: * fully locked down android, no root, no adb. I will give another root exploit a try tomorrow. * our fel utility does not work. * we of course have no code for u-boot or linux yet. * nothing on the serial port. This device is a really serious GPL violator. They even went as far as removing all open source licenses from the About section under android settings. What we do know: * two obvious serial pads (which are not sending out anything atm) * it tries to boot off SD when a likely candidate is there * it has a 3.4.39 kernel, and the /proc/config.gz was world readable (this is where the string sun8i was found). * HW is an A23 which is a bga, with an AXP223 companion Board picture is available at the device page: http://linux-sunxi.org/Ippo_q8h http://linux-sunxi.org/Ippo_q8h Luc Verhaegen. In the meantime, adb access has been figured out and the device has been rooted. All is documented on the page. script.bin has been fetched, and is available from: http://dl.linux-sunxi.org/users/libv/ippo_q8h/ http://dl.linux-sunxi.org/users/libv/ippo_q8h/ Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com javascript:. For more options, visit https://groups.google.com/groups/opt_out https://groups.google.com/groups/opt_out. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] A39-based MELE Android source code.
Hi, all! Is there some buildable Android manifest for mele, which is current enough? My A39 mele frustratesm me somewhat as I have to reinstall it from mmc card each few days. As this device is too far from my everyday reach (as used by kid to watch youtube) I can use it only at tiny moments, when it is broken and needs to be reflashed, so I even unable to see wtf is on serial console. Also - have anybody tried to boot Allwinner's Android NFS-rooted over ethernet? Allwinner? Tom? Anyone? -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] Waiting for root device /dev/mmcblk0p2...
hi Puneet:
i don't clearly know the reason why the sdcard can not boot, but the board
failed to boot is private A20 board.
and cubietruck can boot form the same sdcard.
On Mon, Dec 23, 2013 at 7:12 PM, Puneet B punit...@gmail.com wrote:
Hi Baodang,
Still i have the issue.
Can you what will be reason.
Regards
Punith
On Saturday, December 21, 2013 6:43:24 PM UTC+5:30, Baodong Chen wrote:
tried same sdcard with cubietruck, ok to boot
On Sat, Dec 21, 2013 at 5:48 PM, Baodong Chen chenbd...@gmail.comwrote:
same issue.
i made a sdcard using debian rootfs and a kernel compiled by myself
today, and tried to boot from the sdcard but failed.
log shows: Waiting for root device /dev/mmcblk0p2...
On Sat, Dec 21, 2013 at 2:34 PM, Puneet B puni...@gmail.com wrote:
To boot android from sd card , i falllow this link
http://linux-sunxi.org/Boot_Android_from_SdCard
but it is booted up to kernel,
but file system is not booting.
Kindly tell me where i can indicate the file system partition.
i am using android 4.2 (sun7i) source code.
here is my boot.cmd:
setenv console 'ttyS0,115200'
setenv root '/dev/mmcblk0p2'
setenv panicarg 'panic=10'
setenv extra 'rootfstype=ext4 rootwait'
setenv loglevel '8'
setenv setargs 'setenv bootargs console=${console} root=${root}
loglevel=${loglevel} ${panicarg} ${extra}'
setenv kernel 'uImage'
setenv boot_mmc 'fatload mmc 0 0x4300 script.bin; fatload mmc 0
0x4800 ${kernel}; bootm 0x4800'
setenv bootcmd 'run setargs boot_mmc'
Regards
Punith
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Re: [linux-sunxi] Re: Upstreaming sunxi mmc support
Hi, On 12/23/2013 08:28 AM, Olliver Schinagl wrote: On 21-12-13 13:15, Hans de Goede wrote: Hi, On 12/20/2013 11:52 PM, Maxime Ripard wrote: Hi Hans, On Fri, Dec 20, 2013 at 08:22:56PM +0100, Hans de Goede wrote: Hi, On 12/20/2013 09:33 AM, Maxime Ripard wrote: Hi Hans, On Fri, Dec 20, 2013 at 08:29:46AM +0100, Hans de Goede wrote: Hi, On 12/19/2013 10:49 PM, Юрий Пухальский wrote: Good UTC night! Got somewhat further, yet still there are problems. Is there anything i should change in kernel cmdline maybe? Is this a sun5i device, iow A10s or A13 SOC based ? If so you need to build and boot with my sunxi-next u-boot branch: https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next The only time I've seen those clock update timeout errors is on sun5i with an unfixed uboot. It would be really great if it was to work without any changes in u-boot. I agree. For this to work we need to override the initial pll6 frequency we inherit from u-boot, which for sun5i is 2400 MHz, which PLL6 can be configured to given its factors, but will not actually work at. I believe this is actually a broken power-on-reset value in PLL6-cfg, rather then u-boot's fault. I do hope that even though all the below is valid and true, having u-boot exit with everything in a sane state is still a patch worth while? Given that the patch to fix this in u-boot has already been pushed, yes unless we revert that patch :) Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH 2/4] ARM: dts: sun7i: external clock outputs
Hi,
El 23/12/13 05:37, Chen-Yu Tsai escribió:
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
(,,,)
+ clk_out_a: clk_out_a@01c201f0 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-out-clk;
+ reg = 0x01c201f0 0x4;
+ clocks = osc24M_32k, osc32k, osc24M;
+ };
These nodes should, as per Maxime's recommendation, look more like
clk_out_a: clk@01c201f0 {
#clock-cells = 0;
compatible = allwinner,sun7i-a20-out-clk;
reg = 0x01c201f0 0x4;
clocks = osc24M_32k, osc32k, osc24M;
clk-output-names = clk_out_a;
};
Cheers,
Emilio
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[linux-sunxi] Re: [PATCH 2/4] ARM: dts: sun7i: external clock outputs
El 23/12/13 13:43, Chen-Yu Tsai escribió:
Hi,
On Tue, Dec 24, 2013 at 12:21 AM, Emilio López emi...@elopez.com.ar wrote:
Hi,
El 23/12/13 05:37, Chen-Yu Tsai escribió:
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
(,,,)
+ clk_out_a: clk_out_a@01c201f0 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-out-clk;
+ reg = 0x01c201f0 0x4;
+ clocks = osc24M_32k, osc32k, osc24M;
+ };
These nodes should, as per Maxime's recommendation, look more like
clk_out_a: clk@01c201f0 {
#clock-cells = 0;
compatible = allwinner,sun7i-a20-out-clk;
reg = 0x01c201f0 0x4;
clocks = osc24M_32k, osc32k, osc24M;
clk-output-names = clk_out_a;
};
I see. I was following the structure for the main clocks,
such as pll* or axi/ahb/apb, as the output clocks do not
have a specific device tied to them, and no worries that
a node name collision might happen. Do you plan to convert
the other clocks to this scheme as well? Or are they
considered reserved or special names?
Yes, with time they should be renamed. A quote from
http://devicetree.org/Device_Tree_Usage to give a bit of background
It is worth taking a moment to talk about naming conventions. Every node
must have a name in the form name[@unit-address].
name is a simple ascii string and can be up to 31 characters in
length. In general, nodes are named according to what kind of device it
represents. ie. A node for a 3com Ethernet adapter would be use the name
ethernet, not 3com509. [...]
Sibling nodes must be uniquely named, but it is normal for more than one
node to use the same generic name so long as the address is different
(ie, serial@101f1000 serial@101f2000).
Have a look at the last iteration of my patches, where I remade all the
mod0 nodes to fit with this.
Cheers,
Emilio
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[linux-sunxi] Re: [PATCH 1/4] clk: sunxi: Allwinner A20 output clock support
Quoting Emilio López (2013-12-23 08:23:47) Hi again, El 23/12/13 13:13, Emilio López escribió: Hi, El 23/12/13 05:37, Chen-Yu Tsai escribió: This patch adds support for the external clock outputs on the Allwinner A20 SoC. The clock outputs are similar to module 0 type clocks, with different offsets and widths for clock factors. Signed-off-by: Chen-Yu Tsai w...@csie.org This patch looks good to me, Acked-by: Emilio López emi...@elopez.com.ar --- drivers/clk/sunxi/clk-sunxi.c | 57 +++ 1 file changed, 57 insertions(+) Please add the new binding to the binding document; I just noticed it was missing. You can keep the Ack once you do so. Feel free to add this to your [PATCH v3 00/13] clk: sunxi: add PLL5 and PLL6 support pull request. Regards, Mike Cheers, Emilio -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
