Re: [linux-sunxi] YUYV vs NV12 with camera
On Mon, Feb 24, 2014 at 6:21 PM, Manuel Braga wrote: > On Mon, 24 Feb 2014 16:17:31 -0500 "jonsm...@gmail.com" > wrote: >> Compare it to these public Dropcams. They are using a slightly better >> image sensor - OV5630. 500Kb/s 720P h.264 high encoding. >> https://www.dropcam.com/cameras/featured >> >> CPU - http://www.ambarella.com/ >> >> I'd love to get that good of quality recording. > > You know who to go complain => Allwinner What I can't tell is if the hardware is good and the software is just messed up, or if the hardware is fundamentally broken. So maybe I can do an experiment. First I can save some uncompressed stills to assess the camera. Second, there is uncompressed test 720P video here. https://media.xiph.org/video/derf/ I can feed it through the compression hardware and compare to x86 software encoders. This works since there is no requirement to compress in real-time. There is no way to save real-time uncompressed video on the A20. It is just too fast. Would you happen to already have an app written that can compress the raw video? This will provide some good data for Allwinner if it show problems in the h264 encoder. -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH 1/5] clk: sun6i: Protect CPU clock
Hi Russell, El 24/02/14 21:01, Russell King - ARM Linux escribió: Hi Emilio. On Mon, Feb 24, 2014 at 08:38:44PM -0300, Emilio López wrote: Why is this so? Can't a clock be left enabled while nobody has a reference to it? I have looked around in Documentation/ (rather quickly I must say) and have not found any explicit mention that it is required to keep a reference to the clock while it's enabled. I'd appreciate it if you could explain this a bit more verbosely or point me to the relevant documents. First up, if you have a requirement that a clock be enabled, then is it not unreasonable to ensure that the clock is referenced? I was under the impression that the reference count was orthogonal to the clock status, but after getting that clarified, I can see your point. Secondly, what if we have code which scans the clocks in the system, shutting down those leaf clocks which appear to be unreferenced? Indeed, that would break things. Thirdly, the API (as I designed it) says so: /** * clk_put - "free" the clock source * @clk: clock source * * Note: drivers must ensure that all clk_enable calls made on this * clock source are balanced by clk_disable calls prior to calling * this function. * * clk_put should not be called from within interrupt context. */ void clk_put(struct clk *clk); which has been there since the API was first created - it's part of the contract between drivers using the API and implementers creating something which conforms to the API - which today means CCF. That's enough of a reason on its own :) I should have checked clk.h The intention here is that while there are any users holding a clk_get() reference on a clock, the clock is assumed to be required for some device, and the struct clk may not be kfree'd, nor may its state be changed in an unpredictable way to those drivers holding a reference to it. I understand now, thanks for the insight. I'll talk with Maxime and get this sorted out. As a side note, should drivers/base/power/clock_ops.c be fixed too? I have added Rafael to Cc. Cheers, Emilio -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH 1/5] clk: sun6i: Protect CPU clock
Hi Emilio. On Mon, Feb 24, 2014 at 08:38:44PM -0300, Emilio López wrote: > Why is this so? Can't a clock be left enabled while nobody has a > reference to it? I have looked around in Documentation/ (rather quickly > I must say) and have not found any explicit mention that it is required > to keep a reference to the clock while it's enabled. I'd appreciate it > if you could explain this a bit more verbosely or point me to the > relevant documents. First up, if you have a requirement that a clock be enabled, then is it not unreasonable to ensure that the clock is referenced? Secondly, what if we have code which scans the clocks in the system, shutting down those leaf clocks which appear to be unreferenced? Thirdly, the API (as I designed it) says so: /** * clk_put - "free" the clock source * @clk: clock source * * Note: drivers must ensure that all clk_enable calls made on this * clock source are balanced by clk_disable calls prior to calling * this function. * * clk_put should not be called from within interrupt context. */ void clk_put(struct clk *clk); which has been there since the API was first created - it's part of the contract between drivers using the API and implementers creating something which conforms to the API - which today means CCF. The intention here is that while there are any users holding a clk_get() reference on a clock, the clock is assumed to be required for some device, and the struct clk may not be kfree'd, nor may its state be changed in an unpredictable way to those drivers holding a reference to it. -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH 1/5] clk: sun6i: Protect CPU clock
Hello Russell,
El 24/02/14 13:30, Russell King - ARM Linux escribió:
On Mon, Feb 24, 2014 at 05:22:43PM +0100, Maxime Ripard wrote:
Right now, AHB is an indirect child clock of the CPU clock. If that happens to
change, since the CPU clock has no other consumers declared in Linux, it would
be shut down, which is not really a good idea.
Prevent this by forcing it enabled.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 23baad9..cedaf4b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1301,6 +1301,14 @@ static void __init sunxi_clock_protect(void)
clk_prepare_enable(clk);
clk_put(clk);
}
+
+ /* CPU clocks - sun6i */
+ clk = clk_get(NULL, "cpu");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
This is broken. I'm not sure what's difficult to grasp about the concept
of "while a clock is in use, you should keep a reference to that clock".
That implies that if you get a clock, and then enable it, you don't
put the clock until you've disabled it.
Why is this so? Can't a clock be left enabled while nobody has a
reference to it? I have looked around in Documentation/ (rather quickly
I must say) and have not found any explicit mention that it is required
to keep a reference to the clock while it's enabled. I'd appreciate it
if you could explain this a bit more verbosely or point me to the
relevant documents.
For what it's worth, I've seen this same pattern on
enable/disable_clock() on drivers/base/power/clock_ops.c as well.
Cheers,
Emilio
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Re: [linux-sunxi] YUYV vs NV12 with camera
On Mon, 24 Feb 2014 16:17:31 -0500 "jonsm...@gmail.com" wrote: > Compare it to these public Dropcams. They are using a slightly better > image sensor - OV5630. 500Kb/s 720P h.264 high encoding. > https://www.dropcam.com/cameras/featured > > CPU - http://www.ambarella.com/ > > I'd love to get that good of quality recording. You know who to go complain => Allwinner -- -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] YUYV vs NV12 with camera
Compare it to these public Dropcams. They are using a slightly better image sensor - OV5630. 500Kb/s 720P h.264 high encoding. https://www.dropcam.com/cameras/featured CPU - http://www.ambarella.com/ I'd love to get that good of quality recording. -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] YUYV vs NV12 with camera
On Mon, 24 Feb 2014 13:17:36 -0500 "jonsm...@gmail.com" wrote: > NV12 gives the correct color space (I was in NV21 earlier). This > camera must be wired in the opposite of the other ones I have. It is > also flipped left to right and I haven't figured out where to fix > that. > > Compressed image quality is very poor. This is 3Mb/s. > enc_fmt.profileIdc = 100; /* high profile */ This number goes direct to the output bitstream whatever is it value. Allwinner advertises that the hardware supports high profile, but is this really true? Or is there somekind of limit in the binary blob? I don't know enough of h264 codec internal details to check if or not the result really has high profile features. This should be checked. Another suspicious thing, in the recent openmax source code dumped, is hardcoded to use baseline profile only. By the way, you know that, few week ago, cubietech dumped a new android SDK that has openmax for cedar hardware. There is openmax source for decode and encode. Don't know if works or not. > enc_fmt.levelIdc = 31; > enc_fmt.qp_max = 40; > enc_fmt.qp_min = 20; > > https://drive.google.com/file/d/0B-2Z6FDzyIwrMFpsN3lvRnpRQVU/edit?usp=sharing Magic School Bus, one of the rare few North American cartoons that i liked to watch. -- -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Unable to boot Android from SD card
Hi, My tablet is A13a. my requirement is to connect external cam to the tablet, Unable to find the kernel configuration file from this tablet to add following. CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_COMMON=y CONFIG_VIDEO_MEDIA=y CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_USB_DRIVERS=y CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y So, i got cubieboard-tv-sdk compiled on 64bit ubuntu, Android image file got created. I followed the instructions from this web page. http://linux-sunxi.org/Boot_Android_from_SdCard Finally, when i try to boot from SD card it's not booting. Will this cubieboard-tv-sdk generated image file work on this A13a tablet? What is the error? Can anyone sort this out. Thanks -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] YUYV vs NV12 with camera
NV12 gives the correct color space (I was in NV21 earlier). This camera must be wired in the opposite of the other ones I have. It is also flipped left to right and I haven't figured out where to fix that. Compressed image quality is very poor. This is 3Mb/s. enc_fmt.profileIdc = 100; /* high profile */ enc_fmt.levelIdc = 31; enc_fmt.qp_max = 40; enc_fmt.qp_min = 20; https://drive.google.com/file/d/0B-2Z6FDzyIwrMFpsN3lvRnpRQVU/edit?usp=sharing -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: sun5i nand driver failed to format and init
Never mind, it seems we have already had a fix for this issue, there are 4 patches targeting the drivers/block/sunxi_nand code by Patrick Wood on September 17th 2013 in linux-sunxi repository actually fixed the issue. Specifically: 110ec1170a4770e711446a8e643caaf95c2bf675 sunxi-nand: Retry code from AW sun7i A20 NAND driver -Hunter On Monday, February 24, 2014 10:13:33 AM UTC-6, hunter hu wrote: > > Hi all, > > I am trying to install imagesfrom SD card to internal nand, first of all I > need to locate the internal nand device /dev/nand, however I could not. > > dmesg reveals that something went wrong when the driver loaded: > > here are the error messages: > > [0.424664] [NAND] nand driver version: 0x2 0x9 > [0.431936] PHY_PageReadSpare : too much ecc err,bank 0 block 7,page 0 > ... ...(tons of them) > [3.659593] PHY_PageReadSpare : too much ecc err,bank 0 block 7ff,page > 0 > [3.664674] [FORMAT_ERR] There is not enough valid block for using! > [3.670086] [FORMAT_ERR] There is not enough free blocks for distribute! > [3.673509] [FORMAT_ERR] Format nand disk failed! > [3.675872] [NAND]init_blklayer fail > > Any idea what's going on? Is the nand driver 0x2 0x9 itself buggy? or > something else? the stock Android runs well on the internal NAND, I doubt > this is a real hardware failure? I also tried using Livesuit to reflash > Android again, but after which it was the same dmesg. > > Thanks, > -Hunter > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH pre-v3 26/26] ARM: sunxi/dt: add cubietruck NAND partitions
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 7b48539..2728e9e 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -30,9 +30,49 @@
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "hw";
+ nand-rnd-mode = "hw";
onfi,nand-timing-mode = <0x1f>;
nand-ecc-strength = <40>;
nand-ecc-step-size = <1024>;
+
+ boot0@0 {
+ label = "boot0";
+ reg = /bits/ 64 <0x0 0x20>;
+ nand-ecc-mode = "hw_syndrome";
+ nand-randomizer-seeds = /bits/ 16
<0x4a80>;
+ };
+
+ boot0-rescue@20 {
+ label = "boot0-rescue";
+ reg = /bits/ 64 <0x20 0x20>;
+ nand-ecc-mode = "hw_syndrome";
+ nand-rnd-mode = "hw";
+ nand-randomizer-seeds = /bits/ 16
<0x4a80>;
+ };
+
+ main@20 {
+ label = "main";
+ reg = /bits/ 64 <0x40 0x1ffc0>;
+ nand-ecc-mode = "hw";
+ nand-rnd-mode = "hw";
+ nand-randomizer-seeds = /bits/ 16 <
+ 0x2b75 0x0bd0 0x5ca3 0x62d1
0x1c93 0x07e9 0x2162 0x3a72
+ 0x0d67 0x67f9 0x1be7 0x077d
0x032f 0x0dac 0x2716 0x2436
+ 0x7922 0x1510 0x3860 0x5287
0x480f 0x4252 0x1789 0x5a2d
+ 0x2a49 0x5e10 0x437f 0x4b4e
0x2f45 0x216e 0x5cb7 0x7130
+ 0x2a3f 0x60e4 0x4dc9 0x0ef0
0x0f52 0x1bb9 0x6211 0x7a56
+ 0x226d 0x4ea7 0x6f36 0x3692
0x38bf 0x0c62 0x05eb 0x4c55
+ 0x60f4 0x728c 0x3b6f 0x2037
0x7f69 0x0936 0x651a 0x4ceb
+ 0x6218 0x79f3 0x383f 0x18d9
0x4f05 0x5c82 0x2912 0x6f17
+ 0x6856 0x5938 0x1007 0x61ab
0x3e7f 0x57c2 0x542f 0x4f62
+ 0x7454 0x2eac 0x7739 0x42d4
0x2f90 0x435a 0x2e52 0x2064
+ 0x637c 0x66ad 0x2c90 0x0bad
0x759c 0x0029 0x0986 0x7126
+ 0x1ca7 0x1605 0x386a 0x27f5
0x1380 0x6d75 0x24c3 0x0f8e
+ 0x2b7a 0x1418 0x1fd1 0x7dc1
0x2d8e 0x43af 0x2267 0x7da3
+ 0x4e3d 0x1338 0x50db 0x454d
0x764d 0x40a3 0x42e6 0x262b
+ 0x2d2e 0x1aea 0x2e17 0x173d
0x3a6e 0x71bf 0x25f9 0x0a5d
+ 0x7c57 0x0fbe 0x46ce 0x4939
0x6b17 0x37bb 0x3e91 0x76db>;
+ };
};
};
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 19/26] mtd: nand: add support for NAND partitions
Add support for NAND partitions, and inderectly for per partition ECC
config.
Provide helper functions to add/delete/allocate nand partitions.
NAND core code now make use of the partition specific nand_ecc_ctrl struct
(if available) when doing read/write operations.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/Kconfig |4 +
drivers/mtd/nand/Makefile|2 +
drivers/mtd/nand/nand_base.c | 698 ++
drivers/mtd/nand/nand_bch.c | 16 +-
drivers/mtd/nand/nand_ecc.c |4 +-
include/linux/mtd/nand.h | 37 +++
6 files changed, 619 insertions(+), 142 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8a28c06..c712435 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -22,6 +22,10 @@ menuconfig MTD_NAND
if MTD_NAND
+config MTD_OF_NAND_PARTS
+ tristate
+ default n
+
config MTD_NAND_BCH
tristate
select BCH
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 34f45d8..404c18b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -51,4 +51,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
+obj-$(CONFIG_MTD_OF_NAND_PARTS)+= ofnandpart.o
+
nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 3e8a0d5..8496a7f 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1078,26 +1078,26 @@ static int nand_read_page_raw_syndrome(struct mtd_info
*mtd,
struct nand_chip *chip, uint8_t *buf,
int oob_required, int page)
{
- int eccsize = chip->ecc.size;
- int eccbytes = chip->ecc.bytes;
+ int eccsize = chip->cur_ecc->size;
+ int eccbytes = chip->cur_ecc->bytes;
uint8_t *oob = chip->oob_poi;
int steps, size;
- for (steps = chip->ecc.steps; steps > 0; steps--) {
+ for (steps = chip->cur_ecc->steps; steps > 0; steps--) {
chip->read_buf(mtd, buf, eccsize);
buf += eccsize;
- if (chip->ecc.prepad) {
- chip->read_buf(mtd, oob, chip->ecc.prepad);
- oob += chip->ecc.prepad;
+ if (chip->cur_ecc->prepad) {
+ chip->read_buf(mtd, oob, chip->cur_ecc->prepad);
+ oob += chip->cur_ecc->prepad;
}
chip->read_buf(mtd, oob, eccbytes);
oob += eccbytes;
- if (chip->ecc.postpad) {
- chip->read_buf(mtd, oob, chip->ecc.postpad);
- oob += chip->ecc.postpad;
+ if (chip->cur_ecc->postpad) {
+ chip->read_buf(mtd, oob, chip->cur_ecc->postpad);
+ oob += chip->cur_ecc->postpad;
}
}
@@ -1119,30 +1119,31 @@ static int nand_read_page_raw_syndrome(struct mtd_info
*mtd,
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- int i, eccsize = chip->ecc.size;
- int eccbytes = chip->ecc.bytes;
- int eccsteps = chip->ecc.steps;
+ int i, eccsize = chip->cur_ecc->size;
+ int eccbytes = chip->cur_ecc->bytes;
+ int eccsteps = chip->cur_ecc->steps;
uint8_t *p = buf;
uint8_t *ecc_calc = chip->buffers->ecccalc;
uint8_t *ecc_code = chip->buffers->ecccode;
- uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint32_t *eccpos = chip->cur_ecc->layout->eccpos;
unsigned int max_bitflips = 0;
- chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+ chip->cur_ecc->read_page_raw(mtd, chip, buf, 1, page);
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
- chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+ chip->cur_ecc->calculate(mtd, p, &ecc_calc[i]);
- for (i = 0; i < chip->ecc.total; i++)
+ for (i = 0; i < chip->cur_ecc->total; i++)
ecc_code[i] = chip->oob_poi[eccpos[i]];
- eccsteps = chip->ecc.steps;
+ eccsteps = chip->cur_ecc->steps;
p = buf;
for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
int stat;
- stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ stat = chip->cur_ecc->correct(mtd, p, &ecc_code[i],
+ &ecc_calc[i]);
if (stat < 0) {
mtd->ecc_stats.failed++;
} else {
@@ -1165,7 +1166,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct
nand_chip *chip,
uint32_t data_offs, uint32_t readlen, uin
[linux-sunxi] [PATCH pre-v3 25/26] mtd: nand: add sunxi randomizer support
Add support for the HW randomizer available in the sunxi IP.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/sunxi_nand.c | 507 -
1 file changed, 496 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index aaf1460..07b2731 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -171,6 +171,7 @@ struct sunxi_nand_hw_ecc {
struct sunxi_nand_part {
struct nand_part part;
struct nand_ecc_ctrl ecc;
+ struct nand_rnd_ctrl rnd;
};
static inline struct sunxi_nand_part *
@@ -179,6 +180,17 @@ to_sunxi_nand_part(struct nand_part *part)
return container_of(part, struct sunxi_nand_part, part);
}
+struct sunxi_nand_hw_rnd {
+ int page;
+ int column;
+ int nseeds;
+ u16 *seeds;
+ u16 *subseeds;
+ u16 (*step)(struct mtd_info *mtd, u16 state, int column, int *left);
+ int left;
+ u16 state;
+};
+
struct sunxi_nand_chip {
struct list_head node;
struct nand_chip nand;
@@ -380,6 +392,172 @@ static void sunxi_nfc_write_buf(struct mtd_info *mtd,
const uint8_t *buf,
}
}
+static u16 sunxi_nfc_hwrnd_step(struct sunxi_nand_hw_rnd *rnd, u16 state, int
count)
+{
+ state &= 0x7fff;
+ count *= 8;
+ while (count--)
+ state = ((state >> 1) |
+state >> 0) ^ (state >> 1)) & 1) << 14)) & 0x7fff;
+
+ return state;
+}
+
+static int sunxi_nfc_hwrnd_config(struct mtd_info *mtd, int page, int column,
+ enum nand_rnd_action action)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct sunxi_nand_hw_rnd *rnd = nand->cur_rnd->priv;
+ u16 state;
+
+ if (page < 0 && column < 0) {
+ rnd->page = -1;
+ rnd->column = -1;
+ return 0;
+ }
+
+ if (column < 0)
+ column = 0;
+ if (page < 0)
+ page = rnd->page;
+
+ if (page < 0)
+ return -EINVAL;
+
+ if (page != rnd->page && action == NAND_RND_READ) {
+ int status;
+
+ status = nand_page_get_status(mtd, page);
+ if (status == NAND_PAGE_STATUS_UNKNOWN) {
+ nand->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
+ sunxi_nfc_read_buf(mtd, nand->buffers->databuf,
+ mtd->writesize + mtd->oobsize);
+
+ if (nand_page_is_empty(mtd))
+ status = NAND_PAGE_EMPTY;
+ else
+ status = NAND_PAGE_FILLED;
+
+ nand_page_set_status(mtd, page, status);
+ nand->cmdfunc(mtd, NAND_CMD_RNDOUT, column, -1);
+ }
+ }
+
+ state = rnd->seeds[page % rnd->nseeds];
+ rnd->page = page;
+ rnd->column = column;
+
+ if (rnd->step) {
+ rnd->state = rnd->step(mtd, state, column, &rnd->left);
+ } else {
+ rnd->state = sunxi_nfc_hwrnd_step(rnd, state, column % 4096);
+ rnd->left = mtd->oobsize + mtd->writesize - column;
+ }
+
+ return 0;
+}
+
+static void sunxi_nfc_hwrnd_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+ struct sunxi_nand_hw_rnd *rnd = nand->cur_rnd->priv;
+ u32 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
+ int cnt;
+ int offs = 0;
+ int rndactiv;
+
+ tmp &= ~(NFC_RANDOM_DIRECTION | NFC_RANDOM_SEED | NFC_RANDOM_EN);
+ writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
+
+ if (rnd->page < 0) {
+ sunxi_nfc_write_buf(mtd, buf, len);
+ return;
+ }
+
+ while (len > offs) {
+ cnt = len - offs;
+ if (cnt > 1024)
+ cnt = 1024;
+
+ rndactiv = nand_rnd_is_activ(mtd, rnd->page, rnd->column,
+&cnt);
+ if (rndactiv > 0) {
+ writel(tmp | NFC_RANDOM_EN | (rnd->state << 16),
+ nfc->regs + NFC_REG_ECC_CTL);
+ if (rnd->left < cnt)
+ cnt = rnd->left;
+ }
+
+ sunxi_nfc_write_buf(mtd, buf + offs, cnt);
+
+ if (rndactiv > 0)
+ writel(tmp & ~NFC_RANDOM_EN,
+ nfc->regs + NFC_REG_ECC_CTL);
+
+ offs += cnt;
+ if (len <= offs)
+ break;
+
+ sunxi_nfc_hwrnd_config(mtd, -1, rnd->column + cnt,
NAND_RND_WRITE);
+ }
+}
+
+static void sunxi_nfc_hwrnd_read_buf(struct mtd_info *mtd, uint8_t *buf,
+
[linux-sunxi] [PATCH pre-v3 22/26] mtd: nand: add page status table (pst)
Page status table is an byte array storing pages status.
It defines 3 status:
- unknown: the page has not been read yet and we do not know its current
state
- empty: the page contains only FFs
- filled: the page has been filled with data
Care must be taken: an empty page does not mean it can be written, because
it might have already been written with only FFs.
These page status are useful to check wether the controller should try to
correct errors (using ECC) or a derandomize data (using a randomizer
block).
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/nand_base.c | 118 ++
include/linux/mtd/nand.h | 21
2 files changed, 139 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 8496a7f..4cdba89 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1046,6 +1046,102 @@ out:
EXPORT_SYMBOL(nand_lock);
/**
+ * nand_page_is_empty - check wether a NAND page contains only FFs
+ * @mtd: mtd info
+ *
+ * Reads the data stored in the databuf buffer and check if it contains only
+ * FFs.
+ *
+ * Return true if it does else return false.
+ */
+bool nand_page_is_empty(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ u8 *buf = chip->buffers->databuf;
+ int length = mtd->writesize + mtd->oobsize;
+ u32 pattern = 0x;
+
+ while (length) {
+ if (memcmp(&pattern, buf, sizeof(pattern)))
+ return false;
+ buf += sizeof(pattern);
+ length -= sizeof(pattern);
+ }
+
+ return true;
+}
+EXPORT_SYMBOL(nand_page_is_empty);
+
+/**
+ * nand_page_get_status - retrieve page status from the page status table (pst)
+ * @mtd: mtd info
+ * @page: page you want to get status on
+ *
+ * Return the page status.
+ */
+int nand_page_get_status(struct mtd_info *mtd, int page)
+{
+ struct nand_chip *chip = mtd->priv;
+ u8 shift = (page % 4) * 2;
+ uint64_t offset = page / 4;
+ int ret = NAND_PAGE_STATUS_UNKNOWN;
+
+ if (chip->pst)
+ ret = (chip->pst[offset] >> shift) & 0x3;
+
+ return ret;
+}
+EXPORT_SYMBOL(nand_page_get_status);
+
+/**
+ * nand_page_set_status - assign page status from in the page status table
+ * @mtd: mtd info
+ * @page: page you want to get status on
+ * @status:new status to assign
+ */
+void nand_page_set_status(struct mtd_info *mtd, int page,
+ enum nand_page_status status)
+{
+ struct nand_chip *chip = mtd->priv;
+ u8 shift;
+ uint64_t offset;
+
+ if (!chip->pst)
+ return;
+
+ shift = (page % 4) * 2;
+ offset = page / 4;
+ chip->pst[offset] &= ~(0x3 << shift);
+ chip->pst[offset] |= (status & 0x3) << shift;
+}
+EXPORT_SYMBOL(nand_page_set_status);
+
+/**
+ * nand_pst_create - create a page status table
+ * @mtd: mtd info
+ *
+ * Allocate a page status table and assign it to the mtd device.
+ *
+ * Returns 0 in case of success or -ERRNO in case of error.
+ */
+int nand_pst_create(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (chip->pst)
+ return 0;
+
+ chip->pst = kzalloc(mtd->size >>
+ (chip->page_shift + mtd->subpage_sft + 2),
+ GFP_KERNEL);
+ if (!chip->pst)
+ return -ENOMEM;
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_pst_create);
+
+/**
* nand_read_page_raw - [INTERN] read raw page data without ecc
* @mtd: mtd info structure
* @chip: nand chip info structure
@@ -2469,6 +2565,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t
to,
int bytes = mtd->writesize;
int cached = writelen > bytes && page != blockmask;
uint8_t *wbuf = buf;
+ int subpage;
/* Partial page write? */
if (unlikely(column || writelen < (mtd->writesize - 1))) {
@@ -2494,6 +2591,14 @@ static int nand_do_write_ops(struct mtd_info *mtd,
loff_t to,
if (ret)
break;
+ for (subpage = column / chip->subpagesize;
+subpage < (column + writelen) / chip->subpagesize;
+subpage++)
+ nand_page_set_status(mtd,
+(page << mtd->subpage_sft) +
+subpage,
+NAND_PAGE_FILLED);
+
writelen -= bytes;
if (!writelen)
break;
@@ -2897,6 +3002,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct
erase_info *instr,
int page, status, pages_per_block, ret, chipnr;
struct nand_chip *chip = mtd->priv;
loff_t len;
+ int i;
pr_debug("%s: start = 0x%012llx, len = %llu\n",
[linux-sunxi] [PATCH pre-v3 21/26] mtd: nand: add NAND partition support to the sunxi driver
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/Kconfig |1 +
drivers/mtd/nand/sunxi_nand.c | 63 -
2 files changed, 57 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index c712435..4cb75b0 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -517,6 +517,7 @@ config MTD_NAND_XWAY
config MTD_NAND_SUNXI
tristate "Support for NAND on Allwinner SoCs"
depends on ARCH_SUNXI
+ select MTD_OF_NAND_PARTS
help
Enables support for NAND Flash chips on Allwinner SoCs.
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index d300adb..aaf1460 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -168,6 +168,17 @@ struct sunxi_nand_hw_ecc {
struct nand_ecclayout layout;
};
+struct sunxi_nand_part {
+ struct nand_part part;
+ struct nand_ecc_ctrl ecc;
+};
+
+static inline struct sunxi_nand_part *
+to_sunxi_nand_part(struct nand_part *part)
+{
+ return container_of(part, struct sunxi_nand_part, part);
+}
+
struct sunxi_nand_chip {
struct list_head node;
struct nand_chip nand;
@@ -416,7 +427,7 @@ static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
int oob_required, int page)
{
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
- struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct nand_ecc_ctrl *ecc = chip->cur_ecc;
struct nand_ecclayout *layout = ecc->layout;
struct sunxi_nand_hw_ecc *data = ecc->priv;
int steps = mtd->writesize / ecc->size;
@@ -492,7 +503,7 @@ static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
const uint8_t *buf, int oob_required)
{
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
- struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct nand_ecc_ctrl *ecc = chip->cur_ecc;
struct nand_ecclayout *layout = ecc->layout;
struct sunxi_nand_hw_ecc *data = ecc->priv;
int offset;
@@ -559,7 +570,7 @@ static int sunxi_nfc_hw_syndrome_ecc_read_page(struct
mtd_info *mtd,
int page)
{
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
- struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct nand_ecc_ctrl *ecc = chip->cur_ecc;
struct sunxi_nand_hw_ecc *data = ecc->priv;
int steps = mtd->writesize / ecc->size;
unsigned int max_bitflips = 0;
@@ -623,7 +634,7 @@ static int sunxi_nfc_hw_syndrome_ecc_write_page(struct
mtd_info *mtd,
int oob_required)
{
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
- struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct nand_ecc_ctrl *ecc = chip->cur_ecc;
struct sunxi_nand_hw_ecc *data = ecc->priv;
int steps = mtd->writesize / ecc->size;
uint8_t *oob = chip->oob_poi;
@@ -980,6 +991,11 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd,
struct nand_ecc_ctrl *ecc,
ecc->strength = nand->ecc_strength_ds;
}
+ if ((!ecc->size || !ecc->strength) && ecc != &nand->ecc) {
+ ecc->size = nand->ecc.size;
+ ecc->strength = nand->ecc.strength;
+ }
+
ecc->mode = of_get_nand_ecc_mode(np);
switch (ecc->mode) {
case NAND_ECC_SOFT_BCH:
@@ -1007,12 +1023,39 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd,
struct nand_ecc_ctrl *ecc,
return 0;
}
+static void sunxi_nand_part_release(struct nand_part *part)
+{
+ kfree(to_sunxi_nand_part(part));
+}
+
+struct nand_part *sunxi_ofnandpart_parse(void *priv, struct mtd_info *master,
+struct device_node *pp)
+{
+ struct sunxi_nand_part *part;
+ int ret;
+
+ part = kzalloc(sizeof(*part), GFP_KERNEL);
+ part->part.release = sunxi_nand_part_release;
+
+ ret = sunxi_nand_ecc_init(master, &part->ecc, pp);
+ if (ret)
+ goto err;
+
+ part->part.ecc = &part->ecc;
+
+ return &part->part;
+
+err:
+ kfree(part);
+ return ERR_PTR(ret);
+}
+
static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
struct device_node *np)
{
const struct nand_sdr_timings *timings;
struct sunxi_nand_chip *chip;
- struct mtd_part_parser_data ppdata;
+ struct ofnandpart_data ppdata;
struct mtd_info *mtd;
struct nand_chip *nand;
int nsels;
@@ -1119,9 +1162,15 @@ static int sunxi_nand_chip_init(struct device *dev,
struct sunxi_nfc *nfc,
mtd->name = chip->default_name;
}
- ppdata.of_node = np;
- ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+ ppdata.node = np;
+ ppdata.parse = sunxi_of
[linux-sunxi] [PATCH pre-v3 24/26] of: mtd: add NAND randomizer mode retrieval
Signed-off-by: Boris BREZILLON
---
drivers/of/of_mtd.c| 35 +++
include/linux/of_mtd.h |6 ++
2 files changed, 41 insertions(+)
diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 8bdaa0b..0e2675f 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -84,6 +84,41 @@ int of_get_nand_ecc_strength(struct device_node *np)
EXPORT_SYMBOL_GPL(of_get_nand_ecc_strength);
/**
+ * It maps 'enum nand_rnd_modes_t' found in include/linux/mtd/nand.h
+ * into the device tree binding of 'nand-rnd', so that MTD
+ * device driver can get nand rnd from device tree.
+ */
+static const char *nand_rnd_modes[] = {
+ [NAND_RND_NONE] = "none",
+ [NAND_RND_SOFT] = "soft",
+ [NAND_RND_HW] = "hw",
+};
+
+/**
+ * of_get_nand_rnd_mode - Get nand randomizer mode for given device_node
+ * @np:Pointer to the given device_node
+ *
+ * The function gets randomizer mode string from property 'nand-rnd-mode',
+ * and return its index in nand_rnd_modes table, or errno in error case.
+ */
+int of_get_nand_rnd_mode(struct device_node *np)
+{
+ const char *pm;
+ int err, i;
+
+ err = of_property_read_string(np, "nand-rnd-mode", &pm);
+ if (err < 0)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(nand_rnd_modes); i++)
+ if (!strcasecmp(pm, nand_rnd_modes[i]))
+ return i;
+
+ return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_rnd_mode);
+
+/**
* of_get_nand_bus_width - Get nand bus witdh for given device_node
* @np:Pointer to the given device_node
*
diff --git a/include/linux/of_mtd.h b/include/linux/of_mtd.h
index c8310ae..9ec5bf6 100644
--- a/include/linux/of_mtd.h
+++ b/include/linux/of_mtd.h
@@ -17,6 +17,7 @@
int of_get_nand_ecc_mode(struct device_node *np);
int of_get_nand_ecc_step_size(struct device_node *np);
int of_get_nand_ecc_strength(struct device_node *np);
+int of_get_nand_rnd_mode(struct device_node *np);
int of_get_nand_bus_width(struct device_node *np);
bool of_get_nand_on_flash_bbt(struct device_node *np);
int of_get_nand_onfi_timing_mode(struct device_node *np);
@@ -38,6 +39,11 @@ static inline int of_get_nand_ecc_strength(struct
device_node *np)
return -ENOSYS;
}
+static inline int of_get_nand_rnd_mode(struct device_node *np)
+{
+ return -ENOSYS;
+}
+
static inline int of_get_nand_bus_width(struct device_node *np)
{
return -ENOSYS;
--
1.7.9.5
--
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[linux-sunxi] [PATCH pre-v3 23/26] mtd: nand: introduce a randomizer layer in the NAND framework
This patch introduce a new layer in the NAND framework to support both HW
and SW randomizers.
This randomization is required on some MLC/TLC NAND chips which do not
support large islands of same patterns.
The randomizer layer defines a nand_rnd_ctrl struct which is intended to
be used by NAND core functions or NAND drivers to randomize/derandomize
data stored on NAND chips.
The implementation can implement any of these functions:
- config: prepare a random transfer to/from the NAND chip
- write_buf: randomize and write data to the NAND chip
- read_buf: read and derandomize data from the NAND chip
read/write_buf functions are always called after a config call.
The config call specify the page, the column within the page and the action
that will take place after the config (either read or write).
If column is set to -1, the randomizer is disabled.
If page is set to -1, we keep working on the same page.
The randomizer layer provides helper functions that choose wether the
randomizer or the chip read/write_buf should be used.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/nand_base.c | 278 +-
include/linux/mtd/nand.h | 98 +++
2 files changed, 321 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 4cdba89..15e5783 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1046,6 +1046,62 @@ out:
EXPORT_SYMBOL(nand_lock);
/**
+ * nand_rnd_is_activ - check wether a region of a NAND page requires NAND
+ *randomizer to be disabled
+ * @mtd: mtd info
+ * @page: NAND page
+ * @column:offset within the page
+ * @len: len of the region
+ *
+ * Returns 1 if the randomizer should be enabled, 0 if not, or -ERR in case of
+ * error.
+ *
+ * In case of success len will contain the size of the region:
+ * - if the requested region fits in a NAND random region len will not change
+ * - else len will be replaced by the available length within the NAND random
+ *region
+ */
+int nand_rnd_is_activ(struct mtd_info *mtd, int page, int column, int *len)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_rnd_layout *layout = chip->cur_rnd->layout;
+ struct nand_rndfree *range;
+ int ret = 1;
+ int tmp;
+ int i;
+
+ if (!len || *len < 0 || column < 0 ||
+ column + *len > mtd->writesize + mtd->oobsize)
+ return -EINVAL;
+
+ if (layout) {
+ for (i = 0; i < layout->nranges; i++) {
+ range = &layout->ranges[i];
+ if (column + *len <= range->offset) {
+ break;
+ } else if (column >= range->offset + range->length) {
+ continue;
+ } else if (column < range->offset) {
+ tmp = range->offset - column;
+ if (*len > tmp)
+ *len = tmp;
+ break;
+ } else {
+ tmp = range->offset + range->length - column;
+ if (*len > tmp)
+ *len = tmp;
+ ret = 0;
+ break;
+ }
+
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(nand_rnd_is_activ);
+
+/**
* nand_page_is_empty - check wether a NAND page contains only FFs
* @mtd: mtd info
*
@@ -1154,9 +1210,14 @@ EXPORT_SYMBOL(nand_pst_create);
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- chip->read_buf(mtd, buf, mtd->writesize);
- if (oob_required)
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+ nand_rnd_config(mtd, page, 0, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, buf, mtd->writesize);
+ if (oob_required) {
+ nand_rnd_config(mtd, page, mtd->writesize, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+ }
+ nand_rnd_config(mtd, -1, -1, NAND_RND_READ);
+
return 0;
}
@@ -1178,28 +1239,40 @@ static int nand_read_page_raw_syndrome(struct mtd_info
*mtd,
int eccbytes = chip->cur_ecc->bytes;
uint8_t *oob = chip->oob_poi;
int steps, size;
+ int column = 0;
for (steps = chip->cur_ecc->steps; steps > 0; steps--) {
- chip->read_buf(mtd, buf, eccsize);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, buf, eccsize);
buf += eccsize;
+ column += eccsize;
if (chip->cur_ecc->prepad) {
- chip->read_buf(mtd, oob, chip->cur_ecc->prepad);
+
[linux-sunxi] [PATCH pre-v3 08/26] clk: sunxi: fix clk get factor
--- drivers/clk/sunxi/clk-sunxi.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..c06977a 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -310,7 +310,7 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, if (*freq > parent_rate) *freq = parent_rate; - div = parent_rate / *freq; + div = DIV_ROUND_UP(parent_rate, *freq); if (div < 16) calcp = 0; @@ -351,7 +351,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, if (*freq > parent_rate) *freq = parent_rate; - div = parent_rate / *freq; + div = DIV_ROUND_UP(parent_rate, *freq); if (div < 32) calcp = 0; -- 1.7.9.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH pre-v3 12/26] of: mtd: add documentation for the ONFI NAND timing mode property
Add documentation for the ONFI NAND timing mode property.
Signed-off-by: Boris BREZILLON
---
Documentation/devicetree/bindings/mtd/nand.txt |9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
b/Documentation/devicetree/bindings/mtd/nand.txt
index b53f92e..02b293c 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -5,6 +5,7 @@
"soft_bch".
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+<<< HEAD
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step.
@@ -19,3 +20,11 @@ errors per {size} bytes".
The interpretation of these parameters is implementation-defined, so not all
implementations must support all possible combinations. However,
implementations
are encouraged to further specify the value(s) they support.
+
+- onfi,nand-timing-mode: an integer encoding the supported ONFI timing modes of
+ the NAND chip. Each supported mode is represented as a bit position (i.e. :
+ mode 0 and 1 => (1 << 0) | (1 << 1) = 0x3).
+ This is only used when the chip does not support the ONFI standard.
+ The last bit set represent the closest mode fulfilling the NAND chip timings.
+ For a full description of the different timing modes see this document:
+ www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 11/26] of: mtd: add NAND timing mode retrieval support
Add a function to retrieve NAND timing mode (ONFI timing mode) from a given
DT node.
Signed-off-by: Boris BREZILLON
---
drivers/of/of_mtd.c| 19 +++
include/linux/of_mtd.h |8
2 files changed, 27 insertions(+)
diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index b7361ed..8bdaa0b 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -117,3 +117,22 @@ bool of_get_nand_on_flash_bbt(struct device_node *np)
return of_property_read_bool(np, "nand-on-flash-bbt");
}
EXPORT_SYMBOL_GPL(of_get_nand_on_flash_bbt);
+
+/**
+ * of_get_nand_timings - Get nand timings for the given device_node
+ * @np:Pointer to the given device_node
+ *
+ * return 0 on success errno other wise
+ */
+int of_get_nand_onfi_timing_mode(struct device_node *np)
+{
+ int err;
+ u32 mode;
+
+ err = of_property_read_u32(np, "onfi,nand-timing-mode", &mode);
+ if (err)
+ return err;
+
+ return mode;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_onfi_timing_mode);
diff --git a/include/linux/of_mtd.h b/include/linux/of_mtd.h
index e266caa..c8310ae 100644
--- a/include/linux/of_mtd.h
+++ b/include/linux/of_mtd.h
@@ -9,6 +9,8 @@
#ifndef __LINUX_OF_MTD_H
#define __LINUX_OF_MTD_H
+#include
+
#ifdef CONFIG_OF_MTD
#include
@@ -17,6 +19,7 @@ int of_get_nand_ecc_step_size(struct device_node *np);
int of_get_nand_ecc_strength(struct device_node *np);
int of_get_nand_bus_width(struct device_node *np);
bool of_get_nand_on_flash_bbt(struct device_node *np);
+int of_get_nand_onfi_timing_mode(struct device_node *np);
#else /* CONFIG_OF_MTD */
@@ -45,6 +48,11 @@ static inline bool of_get_nand_on_flash_bbt(struct
device_node *np)
return false;
}
+static inline int of_get_nand_onfi_timing_mode(struct device_node *np)
+{
+ return -ENOSYS;
+}
+
#endif /* CONFIG_OF_MTD */
#endif /* __LINUX_OF_MTD_H */
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 14/26] mtd: nand: add sunxi NFC dt bindings doc
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
new file mode 100644
index 000..4bf5b07
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
@@ -0,0 +1,48 @@
+Allwinner NAND Flash Controller (NFC)
+
+Required properties:
+- compatible : "allwinner,sun4i-nand".
+- reg : shall contain registers location and length for data and reg.
+- interrupts : shall define the nand controller interrupt.
+- #address-cells: shall be set to 1. Encode the nand CS.
+- #size-cells : shall be set to 0.
+- clocks : shall reference nand controller clocks.
+- clock-names : nand controller internal clock names. Shall contain :
+* "ahb_clk" : AHB gating clock
+* "sclk" : nand controller clock
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Optional properties:
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+- rb-gpios : shall contain the gpios used as R/B pins.
+- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
+ "soft_bch" or "none")
+
+see Documentation/devicetree/mtd/nand.txt for generic bindings.
+
+
+Examples:
+nfc: nand@01c03000 {
+ compatible = "allwinner,sun4i-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <0 37 1>;
+ clocks = <&ahb_gates 13>, <&nand_clk>;
+ clock-names = "ahb_clk", "sclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "soft_bch";
+ onfi,nand-timing-mode = <4>;
+ };
+};
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 15/26] ARM: dt/sunxi: add NFC node to Allwinner A20 SoC
Add NAND Flash controller node definition to the A20 SoC.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9ff0948..4c14ed8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -339,6 +339,17 @@
#size-cells = <1>;
ranges;
+ nfc: nand@01c03000 {
+ compatible = "allwinner,sun4i-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <0 37 4>;
+ clocks = <&ahb_gates 13>, <&nand_clk>;
+ clock-names = "ahb_clk", "sclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 13/26] mtd: nand: add sunxi NAND flash controller support
Add support for the sunxi NAND Flash Controller (NFC). Signed-off-by: Boris BREZILLON --- drivers/mtd/nand/Kconfig |6 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/sunxi_nand.c | 1276 + 3 files changed, 1283 insertions(+) create mode 100644 drivers/mtd/nand/sunxi_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 90ff447..8a28c06 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -510,4 +510,10 @@ config MTD_NAND_XWAY Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached to the External Bus Unit (EBU). +config MTD_NAND_SUNXI + tristate "Support for NAND on Allwinner SoCs" + depends on ARCH_SUNXI + help + Enables support for NAND Flash chips on Allwinner SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 0b8a822..34f45d8 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY)+= xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ +obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o nand-objs := nand_base.o nand_bbt.o diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c new file mode 100644 index 000..d300adb --- /dev/null +++ b/drivers/mtd/nand/sunxi_nand.c @@ -0,0 +1,1276 @@ +/* + * Copyright (C) 2013 Boris BREZILLON + * + * Derived from: + * https://github.com/yuq/sunxi-nfc-mtd + * Copyright (C) 2013 Qiang Yu + * + * https://github.com/hno/Allwinner-Info + * Copyright (C) 2013 Henrik Nordström + * + * Copyright (C) 2013 Dmitriy B. + * Copyright (C) 2013 Sergey Lapin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NFC_REG_CTL0x +#define NFC_REG_ST 0x0004 +#define NFC_REG_INT0x0008 +#define NFC_REG_TIMING_CTL 0x000C +#define NFC_REG_TIMING_CFG 0x0010 +#define NFC_REG_ADDR_LOW 0x0014 +#define NFC_REG_ADDR_HIGH 0x0018 +#define NFC_REG_SECTOR_NUM 0x001C +#define NFC_REG_CNT0x0020 +#define NFC_REG_CMD0x0024 +#define NFC_REG_RCMD_SET 0x0028 +#define NFC_REG_WCMD_SET 0x002C +#define NFC_REG_IO_DATA0x0030 +#define NFC_REG_ECC_CTL0x0034 +#define NFC_REG_ECC_ST 0x0038 +#define NFC_REG_DEBUG 0x003C +#define NFC_REG_ECC_CNT0 0x0040 +#define NFC_REG_ECC_CNT1 0x0044 +#define NFC_REG_ECC_CNT2 0x0048 +#define NFC_REG_ECC_CNT3 0x004c +#define NFC_REG_USER_DATA_BASE 0x0050 +#define NFC_REG_SPARE_AREA 0x00A0 +#define NFC_RAM0_BASE 0x0400 +#define NFC_RAM1_BASE 0x0800 + +/*define bit use in NFC_CTL*/ +#define NFC_EN (1 << 0) +#define NFC_RESET (1 << 1) +#define NFC_BUS_WIDYH (1 << 2) +#define NFC_RB_SEL (1 << 3) +#define NFC_CE_SEL (7 << 24) +#define NFC_CE_CTL (1 << 6) +#define NFC_CE_CTL1(1 << 7) +#define NFC_PAGE_SIZE (0xf << 8) +#define NFC_SAM(1 << 12) +#define NFC_RAM_METHOD (1 << 14) +#define NFC_DEBUG_CTL (1 << 31) + +/*define bit use in NFC_ST*/ +#define NFC_RB_B2R (1 << 0) +#define NFC_CMD_INT_FLAG (1 << 1) +#define NFC_DMA_INT_FLAG (1 << 2) +#define NFC_CMD_FIFO_STATUS(1 << 3) +#define NFC_STA(1 << 4) +#define NFC_NATCH_INT_FLAG (1 << 5) +#define NFC_RB_STATE0 (1 << 8) +#define NFC_RB_STATE1 (1 << 9) +#define NFC_RB_STATE2 (1 << 10) +#define NFC_RB_STATE3 (1 << 11) + +/*define bit use in NFC_INT*/ +#define NFC_B2R_INT_ENABLE (1 << 0) +#define NFC_CMD_INT_ENABLE (1 << 1) +#define NFC_DMA_INT_ENABLE (1 << 2) +#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \ +NFC_CMD_INT_ENABLE | \ +
[linux-sunxi] [PATCH pre-v3 10/26] mtd: nand: add ONFI timing mode to nand_timings converter
Add a converter to retrieve NAND timings from an ONFI NAND timing mode.
This only support SDR NAND timings for now.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/Makefile |2 +-
drivers/mtd/nand/nand_timings.c | 248 +++
include/linux/mtd/nand.h|4 +
3 files changed, 253 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/nand_timings.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index c970ce7..0b8a822 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -2,7 +2,7 @@
# linux/drivers/nand/Makefile
#
-obj-$(CONFIG_MTD_NAND) += nand.o
+obj-$(CONFIG_MTD_NAND) += nand.o nand_timings.o
obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o
obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o nand_hynix.o
diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
new file mode 100644
index 000..f66fe95
--- /dev/null
+++ b/drivers/mtd/nand/nand_timings.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (C) 2014 Boris BREZILLON
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include
+
+static const struct nand_sdr_timings onfi_sdr_timings[] = {
+ /* Mode 0 */
+ {
+ .tADL_min = 20,
+ .tALH_min = 2,
+ .tALS_min = 5,
+ .tAR_min = 25000,
+ .tCEA_max = 10,
+ .tCEH_min = 2,
+ .tCH_min = 2,
+ .tCHZ_max = 10,
+ .tCLH_min = 2,
+ .tCLR_min = 2,
+ .tCLS_min = 5,
+ .tCOH_min = 0,
+ .tCS_min = 7,
+ .tDH_min = 2,
+ .tDS_min = 4,
+ .tFEAT_max = 100,
+ .tIR_min = 1,
+ .tITC_max = 100,
+ .tRC_min = 10,
+ .tREA_max = 4,
+ .tREH_min = 3,
+ .tRHOH_min = 0,
+ .tRHW_min = 20,
+ .tRHZ_max = 20,
+ .tRLOH_min = 0,
+ .tRP_min = 5,
+ .tRST_max = 2500,
+ .tWB_max = 20,
+ .tRR_min = 4,
+ .tWC_min = 10,
+ .tWH_min = 3,
+ .tWHR_min = 12,
+ .tWP_min = 5,
+ .tWW_min = 10,
+ },
+ /* Mode 1 */
+ {
+ .tADL_min = 10,
+ .tALH_min = 1,
+ .tALS_min = 25000,
+ .tAR_min = 1,
+ .tCEA_max = 45000,
+ .tCEH_min = 2,
+ .tCH_min = 1,
+ .tCHZ_max = 5,
+ .tCLH_min = 1,
+ .tCLR_min = 1,
+ .tCLS_min = 25000,
+ .tCOH_min = 15000,
+ .tCS_min = 35000,
+ .tDH_min = 1,
+ .tDS_min = 2,
+ .tFEAT_max = 100,
+ .tIR_min = 0,
+ .tITC_max = 100,
+ .tRC_min = 5,
+ .tREA_max = 3,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 10,
+ .tRHZ_max = 10,
+ .tRLOH_min = 0,
+ .tRP_min = 25000,
+ .tRR_min = 2,
+ .tRST_max = 5,
+ .tWB_max = 10,
+ .tWC_min = 45000,
+ .tWH_min = 15000,
+ .tWHR_min = 8,
+ .tWP_min = 25000,
+ .tWW_min = 10,
+ },
+ /* Mode 2 */
+ {
+ .tADL_min = 10,
+ .tALH_min = 1,
+ .tALS_min = 15000,
+ .tAR_min = 1,
+ .tCEA_max = 3,
+ .tCEH_min = 2,
+ .tCH_min = 1,
+ .tCHZ_max = 5,
+ .tCLH_min = 1,
+ .tCLR_min = 1,
+ .tCLS_min = 15000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 15000,
+ .tFEAT_max = 100,
+ .tIR_min = 0,
+ .tITC_max = 100,
+ .tRC_min = 35000,
+ .tREA_max = 25000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 10,
+ .tRHZ_max = 10,
+ .tRLOH_min = 0,
+ .tRR_min = 2,
+ .tRST_max = 5,
+ .tWB_max = 10,
+ .tRP_min = 17000,
+ .tWC_min = 35000,
+ .tWH_min =
[linux-sunxi] [PATCH pre-v3 06/26] clk: sunxi: add clk factor determine_rate support
---
drivers/clk/sunxi/clk-factors.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 9e23264..3806d97 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw,
unsigned long rate,
return rate;
}
+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_p)
+{
+ struct clk *clk = hw->clk, *parent, *best_parent = NULL;
+ int i, num_parents;
+ unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
+
+ /* find the parent that can help provide the fastest rate <= rate */
+ num_parents = __clk_get_num_parents(clk);
+ for (i = 0; i < num_parents; i++) {
+ parent = clk_get_parent_by_index(clk, i);
+ if (!parent)
+ continue;
+ if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+ parent_rate = __clk_round_rate(parent, rate);
+ else
+ parent_rate = __clk_get_rate(parent);
+
+ child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
+
+ if (child_rate <= rate && child_rate > best_child_rate) {
+ best_parent = parent;
+ best = parent_rate;
+ best_child_rate = child_rate;
+ }
+ }
+
+ if (best_parent)
+ *best_parent_p = best_parent;
+ *best_parent_rate = best;
+
+ return best_child_rate;
+}
+
static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned
long rate,
}
const struct clk_ops clk_factors_ops = {
+ .determine_rate = clk_factors_determine_rate,
.recalc_rate = clk_factors_recalc_rate,
.round_rate = clk_factors_round_rate,
.set_rate = clk_factors_set_rate,
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 16/26] ARM: sunxi/dt: enable NAND on cubietruck board
Enable the NFC and describe the NAND flash connected to this controller.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61..7b48539 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -19,6 +19,23 @@
compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
soc@01c0 {
+ nfc: nand@01c03000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a
&nand_rb0_pins_a>;
+ status = "okay";
+
+ nand@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "hw";
+ onfi,nand-timing-mode = <0x1f>;
+ nand-ecc-strength = <40>;
+ nand-ecc-step-size = <1024>;
+ };
+ };
+
pinctrl@01c20800 {
led_pins_cubietruck: led_pins@0 {
allwinner,pins = "PH7", "PH11", "PH20", "PH21";
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 07/26] mtd: nand: fix erronous read_buf call in nand_write_page_raw_syndrome
read_buf is called in place of write_buf in the
nand_write_page_raw_syndrome function.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/nand_base.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 8b16479..14bcfc3 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2000,7 +2000,7 @@ static int nand_write_page_raw_syndrome(struct mtd_info
*mtd,
oob += chip->ecc.prepad;
}
- chip->read_buf(mtd, oob, eccbytes);
+ chip->write_buf(mtd, oob, eccbytes);
oob += eccbytes;
if (chip->ecc.postpad) {
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 20/26] mtd: nand: add DT NAND partition parser
Add ofnandpart_parse function to help parsing NAND partitions from DT.
This function should be called from NAND controller drivers just after the
nand_scan_tail in place of mtd_device_parse_register.
The caller can specify a parser function to retrieve HW specific
informations from the DT.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/ofnandpart.c | 104 +
include/linux/mtd/nand.h | 17 +++
2 files changed, 121 insertions(+)
create mode 100644 drivers/mtd/nand/ofnandpart.c
diff --git a/drivers/mtd/nand/ofnandpart.c b/drivers/mtd/nand/ofnandpart.c
new file mode 100644
index 000..293daee
--- /dev/null
+++ b/drivers/mtd/nand/ofnandpart.c
@@ -0,0 +1,104 @@
+/*
+ * NAND Flash partitions described by the OF (or flattened) device tree
+ *
+ * Copyright © 2014 Boris BREZILLON
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static inline bool node_has_compatible(struct device_node *pp)
+{
+ return of_get_property(pp, "compatible", NULL);
+}
+
+int ofnandpart_parse(struct mtd_info *master,
+const struct ofnandpart_data *data)
+{
+ struct device_node *node;
+ const char *partname;
+ struct device_node *pp;
+ int i;
+
+ if (!data)
+ return 0;
+
+ node = data->node;
+ if (!node)
+ return 0;
+
+ i = 0;
+ for_each_child_of_node(node, pp) {
+ const __be32 *reg;
+ int len;
+ int a_cells, s_cells;
+ uint64_t offset, size;
+ uint32_t mask_flags = 0;
+ struct nand_part *part;
+
+ if (node_has_compatible(pp))
+ continue;
+
+ reg = of_get_property(pp, "reg", &len);
+ if (!reg)
+ continue;
+
+ a_cells = of_n_addr_cells(pp);
+ s_cells = of_n_size_cells(pp);
+ offset = of_read_number(reg, a_cells);
+ size = of_read_number(reg + a_cells, s_cells);
+
+ partname = of_get_property(pp, "label", &len);
+ if (!partname)
+ partname = of_get_property(pp, "name", &len);
+
+ if (of_get_property(pp, "read-only", &len))
+ mask_flags |= MTD_WRITEABLE;
+
+ if (of_get_property(pp, "lock", &len))
+ mask_flags |= MTD_POWERUP_LOCK;
+
+ if (data->parse)
+ part = data->parse(data->priv, master, pp);
+ else
+ part = nandpart_alloc();
+
+ if (IS_ERR(part))
+ continue;
+
+ part->offset = offset;
+ part->master = master;
+ part->mtd.name = partname;
+ part->mtd.size = size;
+ part->mtd.flags = mask_flags;
+
+ if (nand_add_partition(master, part)) {
+ if (part->release)
+ part->release(part);
+ continue;
+ }
+
+ i++;
+ }
+
+ if (!i) {
+ of_node_put(pp);
+ pr_err("No valid partition found on %s\n", node->full_name);
+ }
+
+ return i;
+}
+EXPORT_SYMBOL(ofnandpart_parse);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Parser for NAND flash partitioning information in device
tree");
+MODULE_AUTHOR("Boris BREZILLON");
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8009dbe..213a809 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -886,6 +886,23 @@ void nand_del_partition(struct nand_part *part);
struct nand_part *nandpart_alloc(void);
/**
+ * struct ofnandpart_data - struct used to retrieve NAND partitions from a DT
+ * node
+ * @parse: driver specific parser function
+ * @priv: driver private data
+ * @node: OF node containing NAND partitions
+ */
+struct ofnandpart_data {
+ struct nand_part *(*parse)(void *priv, struct mtd_info *master,
+ struct device_node *pp);
+ void *priv;
+ struct device_node *node;
+};
+
+int ofnandpart_parse(struct mtd_info *master,
+const struct ofnandpart_data *data);
+
+/**
* struct nand_sdr_timings - SDR NAND chip timings
*
* This struct defines the timing requirements of a SDR NAND chip.
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 17/26] ARM: dt/sunxi: add NAND controller pin definitions
Define the NAND controller pin configs.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sun7i-a20.dtsi | 80 ++
1 file changed, 80 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4c14ed8..c8095c5 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -443,6 +443,86 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ nand_pins_a: nand_base0@0 {
+ allwinner,pins = "PC0", "PC1", "PC2",
+ "PC5", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14",
+ "PC15", "PC16";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs0_pins_a: nand_cs@0 {
+ allwinner,pins = "PC4";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs1_pins_a: nand_cs@1 {
+ allwinner,pins = "PC3";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs2_pins_a: nand_cs@2 {
+ allwinner,pins = "PC17";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs3_pins_a: nand_cs@3 {
+ allwinner,pins = "PC18";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs4_pins_a: nand_cs@4 {
+ allwinner,pins = "PC19";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs5_pins_a: nand_cs@5 {
+ allwinner,pins = "PC20";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs6_pins_a: nand_cs@6 {
+ allwinner,pins = "PC21";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs7_pins_a: nand_cs@7 {
+ allwinner,pins = "PC22";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_rb0_pins_a: nand_rb@0 {
+ allwinner,pins = "PC6";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_rb1_pins_a: nand_rb@1 {
+ allwinner,pins = "PC7";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
};
timer@01c20c00 {
--
1.7.9.5
--
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[linux-sunxi] [PATCH pre-v3 18/26] mtd: nand: take nand_ecc_ctrl initialization out of nand_scan_tail
Take ECC initialization code portion out of nand_scan_tail so that we can
re-use this implementation.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/nand_base.c | 72 +++---
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 14bcfc3..3e8a0d5 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3689,32 +3689,14 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
}
EXPORT_SYMBOL(nand_scan_ident);
-
-/**
- * nand_scan_tail - [NAND Interface] Scan for the NAND device
- * @mtd: MTD device structure
- *
- * This is the second phase of the normal nand_scan() function. It fills out
- * all the uninitialized function pointers with the defaults and scans for a
- * bad block table if appropriate.
+/*
+ * Initialize ECC struct:
+ * - fill ECC struct with default function/values when these ones are
undefined
+ * - fill ECC infos based on MTD device
*/
-int nand_scan_tail(struct mtd_info *mtd)
+static int nand_ecc_ctrl_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
{
int i;
- struct nand_chip *chip = mtd->priv;
- struct nand_ecc_ctrl *ecc = &chip->ecc;
-
- /* New bad blocks should be marked in OOB, flash-based BBT, or both */
- BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
- !(chip->bbt_options & NAND_BBT_USE_FLASH));
-
- if (!(chip->options & NAND_OWN_BUFFERS))
- chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
- if (!chip->buffers)
- return -ENOMEM;
-
- /* Set the internal oob buffer location, just after the page data */
- chip->oob_poi = chip->buffers->databuf + mtd->writesize;
/*
* If no default placement scheme is given, select an appropriate one.
@@ -3740,9 +3722,6 @@ int nand_scan_tail(struct mtd_info *mtd)
}
}
- if (!chip->write_page)
- chip->write_page = nand_write_page;
-
/*
* Check ECC mode, default to software if 3byte/512byte hardware ECC is
* selected and we have 256 byte pagesize fallback to software ECC
@@ -3909,6 +3888,47 @@ int nand_scan_tail(struct mtd_info *mtd)
}
ecc->total = ecc->steps * ecc->bytes;
+ return 0;
+}
+
+/**
+ * nand_scan_tail - [NAND Interface] Scan for the NAND device
+ * @mtd: MTD device structure
+ *
+ * This is the second phase of the normal nand_scan() function. It fills out
+ * all the uninitialized function pointers with the defaults and scans for a
+ * bad block table if appropriate.
+ */
+int nand_scan_tail(struct mtd_info *mtd)
+{
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+ /* New bad blocks should be marked in OOB, flash-based BBT, or both */
+ BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
+ !(chip->bbt_options & NAND_BBT_USE_FLASH));
+
+ if (!(chip->options & NAND_OWN_BUFFERS))
+ chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+ if (!chip->buffers)
+ return -ENOMEM;
+
+ /* Set the internal oob buffer location, just after the page data */
+ chip->oob_poi = chip->buffers->databuf + mtd->writesize;
+
+ if (!chip->write_page)
+ chip->write_page = nand_write_page;
+
+ /* Initialize ECC struct */
+ ret = nand_ecc_ctrl_init(mtd, ecc);
+ if (ret) {
+ if (!(chip->options & NAND_OWN_BUFFERS))
+ kfree(chip->buffers);
+
+ return ret;
+ }
+
/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
switch (ecc->steps) {
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 09/26] mtd: nand: define struct nand_timings
Define a struct containing the standard NAND timings as described in NAND
datasheets.
Signed-off-by: Boris BREZILLON
---
include/linux/mtd/nand.h | 49 ++
1 file changed, 49 insertions(+)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 389b3c5..f3ff3a3 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -846,4 +846,53 @@ static inline bool nand_is_slc(struct nand_chip *chip)
{
return chip->bits_per_cell == 1;
}
+
+/**
+ * struct nand_sdr_timings - SDR NAND chip timings
+ *
+ * This struct defines the timing requirements of a SDR NAND chip.
+ * These informations can be found in every NAND datasheets and the timings
+ * meaning are described in the ONFI specifications:
+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
+ * Parameters)
+ *
+ */
+
+struct nand_sdr_timings {
+ u32 tALH_min;
+ u32 tADL_min;
+ u32 tALS_min;
+ u32 tAR_min;
+ u32 tCEA_max;
+ u32 tCEH_min;
+ u32 tCH_min;
+ u32 tCHZ_max;
+ u32 tCLH_min;
+ u32 tCLR_min;
+ u32 tCLS_min;
+ u32 tCOH_min;
+ u32 tCS_min;
+ u32 tDH_min;
+ u32 tDS_min;
+ u32 tFEAT_max;
+ u32 tIR_min;
+ u32 tITC_max;
+ u32 tRC_min;
+ u32 tREA_max;
+ u32 tREH_min;
+ u32 tRHOH_min;
+ u32 tRHW_min;
+ u32 tRHZ_max;
+ u32 tRLOH_min;
+ u32 tRP_min;
+ u32 tRR_min;
+ u64 tRST_max;
+ u32 tWB_max;
+ u32 tWC_min;
+ u32 tWH_min;
+ u32 tWHR_min;
+ u32 tWP_min;
+ u32 tWW_min;
+};
+
#endif /* __LINUX_MTD_NAND_H */
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 03/26] mtd: nand: add hynix specific initializer
Add an hynix initiliazer to manage read retries on h27uxgt8t2a chip.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/Makefile |2 +-
drivers/mtd/nand/nand_hynix.c | 151 +
drivers/mtd/nand/nand_ids.c |3 +-
include/linux/mtd/nand.h |2 +
4 files changed, 156 insertions(+), 2 deletions(-)
create mode 100644 drivers/mtd/nand/nand_hynix.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 542b568..c970ce7 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -5,7 +5,7 @@
obj-$(CONFIG_MTD_NAND) += nand.o
obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o
obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
-obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
+obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o nand_hynix.o
obj-$(CONFIG_MTD_SM_COMMON)+= sm_common.o
obj-$(CONFIG_MTD_NAND_CAFE)+= cafe_nand.o
diff --git a/drivers/mtd/nand/nand_hynix.c b/drivers/mtd/nand/nand_hynix.c
new file mode 100644
index 000..c1d0017
--- /dev/null
+++ b/drivers/mtd/nand/nand_hynix.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2014 Boris BREZILLON
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+
+static u8 h27ucg8t2a_read_retry_regs[] = {
+ 0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf
+};
+
+struct hynix_read_retry {
+ u8 *regs;
+ u8 values[64];
+};
+
+struct hynix_nand {
+ struct hynix_read_retry read_retry;
+};
+
+int nand_setup_read_retry_hynix(struct mtd_info *mtd, int retry_mode)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct hynix_nand *hynix = chip->manuf_priv;
+ int offset = retry_mode * 8;
+ int status;
+ int i;
+
+ chip->cmdfunc(mtd, 0x36, -1, -1);
+ for (i = 0; i < 8; i++) {
+ int column = hynix->read_retry.regs[i];
+ column |= column << 8;
+ chip->cmdfunc(mtd, NAND_CMD_NONE, column, -1);
+ chip->write_byte(mtd, hynix->read_retry.values[offset + i]);
+ }
+ chip->cmdfunc(mtd, 0x16, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+
+ return 0;
+}
+
+static void h27ucg8t2a_cleanup(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ kfree(chip->manuf_priv);
+}
+
+static int h27ucg8t2a_init(struct mtd_info *mtd, const uint8_t *id)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct hynix_nand *hynix;
+ u8 buf[1024];
+ int i, j;
+ int ret;
+
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ chip->cmdfunc(mtd, 0x36, 0xff, -1);
+ chip->write_byte(mtd, 0x40);
+ chip->cmdfunc(mtd, NAND_CMD_NONE, 0xcc, -1);
+ chip->write_byte(mtd, 0x4d);
+ chip->cmdfunc(mtd, 0x16, -1, -1);
+ chip->cmdfunc(mtd, 0x17, -1, -1);
+ chip->cmdfunc(mtd, 0x04, -1, -1);
+ chip->cmdfunc(mtd, 0x19, -1, -1);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, 0x200);
+
+ chip->read_buf(mtd, buf, 2);
+ if (buf[0] != 0x8 || buf[1] != 0x8)
+ return -EINVAL;
+ chip->read_buf(mtd, buf, 1024);
+
+ ret = 0;
+ for (j = 0; j < 8; j++) {
+ for (i = 0; i < 64; i++) {
+ u8 *tmp = buf + (128 * j);
+ if ((tmp[i] | tmp[i + 64]) != 0xff) {
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ if (ret)
+ break;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ chip->cmdfunc(mtd, 0x38, -1, -1);
+ chip->select_chip(mtd, -1);
+
+ if (!ret) {
+ hynix = kzalloc(sizeof(*hynix), GFP_KERNEL);
+ if (!hynix)
+ return -ENOMEM;
+
+ hynix->read_retry.regs = h27ucg8t2a_read_retry_regs;
+ memcpy(hynix->read_retry.values, buf, 64);
+ chip->manuf_priv = hynix;
+ chip->setup_read_retry = nand_setup_read_retry_hynix;
+ chip->read_retries = 8;
+ chip->manuf_cleanup = h27ucg8t2a_cleanup;
+ }
+
+ return ret;
+}
+
+struct hynix_nand_initializer {
+ u8 id[6];
+ int (*init)(struct mtd_info *mtd, const uint8_t *id);
+};
+
+struct hynix_nand_initializer initializers[] = {
+ {
+
[linux-sunxi] [PATCH pre-v3 05/26] mtd: nand: Add a devicetree binding for ECC strength and ECC step size
From: Ezequiel Garcia
Some flashes can only be properly accessed when the ECC mode is
specified, so a way to describe such mode is required.
Together, the ECC strength and step size define the correction capability,
so that we say we will correct "{strength} bit errors per {size} bytes".
The interpretation of these parameters is implementation-defined, but they
often have ramifications on the formation, interpretation, and placement of
correction metadata on the flash. Not all implementations must support all
possible combinations. Implementations are encouraged to further define the
value(s) they support.
Acked-by: Grant Likely
Signed-off-by: Ezequiel Garcia
---
Documentation/devicetree/bindings/mtd/nand.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
b/Documentation/devicetree/bindings/mtd/nand.txt
index 03855c8..b53f92e 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -5,3 +5,17 @@
"soft_bch".
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+
+- nand-ecc-strength: integer representing the number of bits to correct
+per ECC step.
+
+- nand-ecc-step-size: integer representing the number of data bytes
+ that are covered by a single ECC step.
+
+The ECC strength and ECC step size properties define the correction capability
+of a controller. Together, they say a controller can correct "{strength} bit
+errors per {size} bytes".
+
+The interpretation of these parameters is implementation-defined, so not all
+implementations must support all possible combinations. However,
implementations
+are encouraged to further specify the value(s) they support.
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 00/26] mtd: nand: add sunxi NAND controller support
Hello, This is the pre version of the 3rd iteration of this patch series. Almost everything is implemented now: - HW ECC support - per partition ECC config - HW randomizer support - per partition randomizer config - read retry for Hynix 20nm 8GB nand The boot0 partition can be read/written from Linux, and you should be able to use UBI/UBIFS (even though UBIFS is not ready yet for MLC flashes). I'll try to send subsets of this series to the MTD ML, and get some features passed (per partition ECC has already been submitted). This work is base on linux-3.14-r4 and is also available on my git repo: https://github.com/bbrezillon/linux-sunxi Any feedback is welcome (either testing or reviews). Thanks for your time. Best Regards, Boris Boris BREZILLON (23): mtd: nand: add manufacturer specific init code infrastructure mtd: nand: add hynix specific initializer clk: sunxi: add clk factor determine_rate support mtd: nand: fix erronous read_buf call in nand_write_page_raw_syndrome clk: sunxi: fix clk get factor mtd: nand: define struct nand_timings mtd: nand: add ONFI timing mode to nand_timings converter of: mtd: add NAND timing mode retrieval support of: mtd: add documentation for the ONFI NAND timing mode property mtd: nand: add sunxi NAND flash controller support mtd: nand: add sunxi NFC dt bindings doc ARM: dt/sunxi: add NFC node to Allwinner A20 SoC ARM: sunxi/dt: enable NAND on cubietruck board ARM: dt/sunxi: add NAND controller pin definitions mtd: nand: take nand_ecc_ctrl initialization out of nand_scan_tail mtd: nand: add support for NAND partitions mtd: nand: add DT NAND partition parser mtd: nand: add NAND partition support to the sunxi driver mtd: nand: add page status table (pst) mtd: nand: introduce a randomizer layer in the NAND framework of: mtd: add NAND randomizer mode retrieval mtd: nand: add sunxi randomizer support ARM: sunxi/dt: add cubietruck NAND partitions Brian Norris (1): mtd: nand: fix off-by-one read retry mode counting Ezequiel Garcia (2): of_mtd: Add helpers to get ECC strength and ECC step size mtd: nand: Add a devicetree binding for ECC strength and ECC step size Documentation/devicetree/bindings/mtd/nand.txt | 23 + .../devicetree/bindings/mtd/sunxi-nand.txt | 48 + arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 57 + arch/arm/boot/dts/sun7i-a20.dtsi | 91 + drivers/clk/sunxi/clk-factors.c| 36 + drivers/clk/sunxi/clk-sunxi.c |4 +- drivers/mtd/nand/Kconfig | 11 + drivers/mtd/nand/Makefile |7 +- drivers/mtd/nand/nand_base.c | 1159 ++--- drivers/mtd/nand/nand_bch.c| 16 +- drivers/mtd/nand/nand_ecc.c|4 +- drivers/mtd/nand/nand_hynix.c | 151 ++ drivers/mtd/nand/nand_ids.c|3 +- drivers/mtd/nand/nand_timings.c| 248 +++ drivers/mtd/nand/ofnandpart.c | 104 ++ drivers/mtd/nand/sunxi_nand.c | 1810 drivers/of/of_mtd.c| 88 + include/linux/mtd/nand.h | 232 +++ include/linux/of_mtd.h | 26 + 19 files changed, 3897 insertions(+), 221 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt create mode 100644 drivers/mtd/nand/nand_hynix.c create mode 100644 drivers/mtd/nand/nand_timings.c create mode 100644 drivers/mtd/nand/ofnandpart.c create mode 100644 drivers/mtd/nand/sunxi_nand.c -- 1.7.9.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH pre-v3 01/26] mtd: nand: fix off-by-one read retry mode counting
From: Brian Norris
A flash may support N read retry voltage threshold modes, numbered 1
through N-1 (where mode 0 represents the initial state). However,
nand_do_read_ops() tries to use mode 0 through N.
This off-by-one error shows up, for instance, when using nanddump, and
we have cycled through available modes:
nand: setting READ RETRY mode 0
nand: setting READ RETRY mode 1
nand: setting READ RETRY mode 2
nand: setting READ RETRY mode 3
nand: setting READ RETRY mode 4
nand: setting READ RETRY mode 5
nand: setting READ RETRY mode 6
nand: setting READ RETRY mode 7
nand: setting READ RETRY mode 8
libmtd: error!: cannot read 8192 bytes from mtd0 (eraseblock 20, offset 0)
error 22 (Invalid argument)
nanddump: error!: mtd_read
Tested on Micron MT29F64G08CBCBBH1, with 8 retry modes.
Signed-off-by: Brian Norris
Acked-by: Huang Shijie
---
drivers/mtd/nand/nand_base.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 59eba5d..9715a7b 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1584,7 +1584,7 @@ read_retry:
}
if (mtd->ecc_stats.failed - ecc_failures) {
- if (retry_mode + 1 <= chip->read_retries) {
+ if (retry_mode + 1 < chip->read_retries) {
retry_mode++;
ret = nand_setup_read_retry(mtd,
retry_mode);
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 02/26] mtd: nand: add manufacturer specific init code infrastructure
Add new fields in nand_manufacturers and nand_chip struct to provide
manufacturer specific handling like read retries.
Signed-off-by: Boris BREZILLON
---
drivers/mtd/nand/nand_base.c |7 +++
include/linux/mtd/nand.h |4
2 files changed, 11 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 9715a7b..8b16479 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3610,6 +3610,13 @@ ident_done:
if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
chip->cmdfunc = nand_command_lp;
+ if (nand_manuf_ids[maf_idx].init) {
+ int err;
+ err = nand_manuf_ids[maf_idx].init(mtd, id_data);
+ if (err)
+ return ERR_PTR(err);
+ }
+
pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
*maf_id, *dev_id);
pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 32f8612..6189312 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -575,6 +575,9 @@ struct nand_chip {
int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
int feature_addr, uint8_t *subfeature_para);
int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
+ void (*manuf_cleanup)(struct mtd_info *mtd);
+
+ void *manuf_priv;
int chip_delay;
unsigned int options;
@@ -720,6 +723,7 @@ struct nand_flash_dev {
struct nand_manufacturers {
int id;
char *name;
+ int (*init)(struct mtd_info *mtd, const uint8_t *id);
};
extern struct nand_flash_dev nand_flash_ids[];
--
1.7.9.5
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[linux-sunxi] [PATCH pre-v3 04/26] of_mtd: Add helpers to get ECC strength and ECC step size
From: Ezequiel Garcia
This commit adds simple helpers to obtain the devicetree properties
that specify the ECC strength and ECC step size to use on a given
NAND controller.
Signed-off-by: Ezequiel Garcia
---
drivers/of/of_mtd.c| 34 ++
include/linux/of_mtd.h | 12
2 files changed, 46 insertions(+)
diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index a27ec94..b7361ed 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -50,6 +50,40 @@ int of_get_nand_ecc_mode(struct device_node *np)
EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
/**
+ * of_get_nand_ecc_step_size - Get ECC step size associated to
+ * the required ECC strength (see below).
+ * @np:Pointer to the given device_node
+ *
+ * return the ECC step size, or errno in error case.
+ */
+int of_get_nand_ecc_step_size(struct device_node *np)
+{
+ int ret;
+ u32 val;
+
+ ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
+ return ret ? ret : val;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_ecc_step_size);
+
+/**
+ * of_get_nand_ecc_strength - Get required ECC strength over the
+ * correspnding step size as defined by 'nand-ecc-size'
+ * @np:Pointer to the given device_node
+ *
+ * return the ECC strength, or errno in error case.
+ */
+int of_get_nand_ecc_strength(struct device_node *np)
+{
+ int ret;
+ u32 val;
+
+ ret = of_property_read_u32(np, "nand-ecc-strength", &val);
+ return ret ? ret : val;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_ecc_strength);
+
+/**
* of_get_nand_bus_width - Get nand bus witdh for given device_node
* @np:Pointer to the given device_node
*
diff --git a/include/linux/of_mtd.h b/include/linux/of_mtd.h
index cb32d9c..e266caa 100644
--- a/include/linux/of_mtd.h
+++ b/include/linux/of_mtd.h
@@ -13,6 +13,8 @@
#include
int of_get_nand_ecc_mode(struct device_node *np);
+int of_get_nand_ecc_step_size(struct device_node *np);
+int of_get_nand_ecc_strength(struct device_node *np);
int of_get_nand_bus_width(struct device_node *np);
bool of_get_nand_on_flash_bbt(struct device_node *np);
@@ -23,6 +25,16 @@ static inline int of_get_nand_ecc_mode(struct device_node
*np)
return -ENOSYS;
}
+static inline int of_get_nand_ecc_step_size(struct device_node *np)
+{
+ return -ENOSYS;
+}
+
+static inline int of_get_nand_ecc_strength(struct device_node *np)
+{
+ return -ENOSYS;
+}
+
static inline int of_get_nand_bus_width(struct device_node *np)
{
return -ENOSYS;
--
1.7.9.5
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Re: [linux-sunxi] YUYV vs NV12 with camera
On Mon, 24 Feb 2014 09:52:19 -0500 "jonsm...@gmail.com"
wrote:
> A few months ago I made this simple Android camera app that records a
> sample of camera footage in h.264 to a file. The goal is to sort out
> things on Android and then port over to Linux.
>
> https://github.com/jonsmirl/cam
Android and binary blobs, sorry i can't help.
>
> The app works in NV12 mode except the color space is messed up during
> replay on VLC. So I tried commenting out a few lines and switching to
> YUYV mode.
>
> } else if (!tryFmt(V4L2_PIX_FMT_YUYV)) {
> mCaptureFormat = V4L2_PIX_FMT_YUYV; // maybe usb camera
> printf("capture format: V4L2_PIX_FMT_YUYV \n");
>
> Putting the camera into this mode creates the bug I'm seeing on three
> other Allwinner Android devices I have here. The color space is ok,
> but something goes wrong in the buffering and the video frames are out
> of order. This is a good bug to fix since every device I have here has
> it.
Did you read all that previous thread named "Demo h264 encoding app"?
This exact problem was there, but as for my use case to get frames from
a camera isn't required, the camera code was removed.
My guess the problem is in camera side driver or how this application is
using V4L api.
The encoder binary blob works great, but only takes in a few color
formats, see here what was found that the hardware supports.
http://linux-sunxi.org/VE_Register_guide#MACC_ISP_CTRL
Suggestion, ignore the encoder for know, and verify what format are you
getting from the camera. Check what format is byte data in the actual
buffer, don't believe what V4L says.
>
> Also, what is the standard color space for a h.264 stream?
This is not a concern, the hardware always generates a valid bitstream,
independent of how the input buffer is set. You only have to set the
input buffer picture to the same format that hardware was set to.
But i never played a raw h264 bitstream in VLC, so don't know if works.
In mplayer tried didn't work, but in ffmpeg does.
Use mkvmerge to mux the raw bitstream into a mkv container, then you
don't need to worry about the player.
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[linux-sunxi] Re: [PATCH 1/5] clk: sun6i: Protect CPU clock
On Mon, Feb 24, 2014 at 05:22:43PM +0100, Maxime Ripard wrote:
> Right now, AHB is an indirect child clock of the CPU clock. If that happens to
> change, since the CPU clock has no other consumers declared in Linux, it would
> be shut down, which is not really a good idea.
>
> Prevent this by forcing it enabled.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi/clk-sunxi.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 23baad9..cedaf4b 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -1301,6 +1301,14 @@ static void __init sunxi_clock_protect(void)
> clk_prepare_enable(clk);
> clk_put(clk);
> }
> +
> + /* CPU clocks - sun6i */
> + clk = clk_get(NULL, "cpu");
> + if (!IS_ERR(clk)) {
> + clk_prepare_enable(clk);
> + clk_put(clk);
> + }
This is broken. I'm not sure what's difficult to grasp about the concept
of "while a clock is in use, you should keep a reference to that clock".
That implies that if you get a clock, and then enable it, you don't
put the clock until you've disabled it.
The only reason the core doesn't check for this kind of thing is that
a clock may be shared, so it's entirely possible for a correctly written
driver to have a clock which is still enabled at put time - but enabled
by an entirely different driver.
However, that's no excuse for this kind of sloppiness.
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[linux-sunxi] [PATCH 5/5] ARM: sun6i: dt: Add A31 DMA controller to DTSI
Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the
controller and the devices supported that can use DMA.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index af6f87c..ad6476a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -237,6 +237,15 @@
#size-cells = <1>;
ranges;
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun6i-a31-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&ahb1_gates 6>;
+ resets = <&ahb1_rst 6>;
+ #dma-cells = <1>;
+ };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun6i-a31-pinctrl";
reg = <0x01c20800 0x400>;
@@ -301,6 +310,8 @@
reg-io-width = <4>;
clocks = <&apb2_gates 16>;
resets = <&apb2_rst 16>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -312,6 +323,8 @@
reg-io-width = <4>;
clocks = <&apb2_gates 17>;
resets = <&apb2_rst 17>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -323,6 +336,8 @@
reg-io-width = <4>;
clocks = <&apb2_gates 18>;
resets = <&apb2_rst 18>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -334,6 +349,8 @@
reg-io-width = <4>;
clocks = <&apb2_gates 19>;
resets = <&apb2_rst 19>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -345,6 +362,8 @@
reg-io-width = <4>;
clocks = <&apb2_gates 20>;
resets = <&apb2_rst 20>;
+ dmas = <&dma 10>, <&dma 10>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -356,6 +375,8 @@
reg-io-width = <4>;
clocks = <&apb2_gates 21>;
resets = <&apb2_rst 21>;
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -365,6 +386,8 @@
interrupts = <0 65 4>;
clocks = <&ahb1_gates 20>, <&spi0_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
resets = <&ahb1_rst 20>;
status = "disabled";
};
@@ -375,6 +398,8 @@
interrupts = <0 66 4>;
clocks = <&ahb1_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
resets = <&ahb1_rst 21>;
status = "disabled";
};
@@ -385,6 +410,8 @@
interrupts = <0 67 4>;
clocks = <&ahb1_gates 22>, <&spi2_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma 25>, <&dma 25>;
+ dma-names = "rx", "tx";
resets = <&ahb1_rst 22>;
status = "disabled";
};
@@ -395,6 +422,8 @@
interrupts = <0 68 4>;
clocks = <&ahb1_gates 23>, <&spi3_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma 26>, <&dma 26>;
+ dma-names = "rx", "tx";
resets = <&ahb1_rst 23>;
status = "disabled";
};
--
1.9.0
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[linux-sunxi] [PATCH 1/5] clk: sun6i: Protect CPU clock
Right now, AHB is an indirect child clock of the CPU clock. If that happens to
change, since the CPU clock has no other consumers declared in Linux, it would
be shut down, which is not really a good idea.
Prevent this by forcing it enabled.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 23baad9..cedaf4b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1301,6 +1301,14 @@ static void __init sunxi_clock_protect(void)
clk_prepare_enable(clk);
clk_put(clk);
}
+
+ /* CPU clocks - sun6i */
+ clk = clk_get(NULL, "cpu");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
}
static void __init sunxi_init_clocks(void)
--
1.9.0
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[linux-sunxi] [PATCH 2/5] clk: sun6i: Reparent AHB clock on PLL6
In order for the DMA controller to work for SDRAM to devices transfers, the AHB
clock should be reparented on the PLL6.
Force that parenting in the clock driver.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index cedaf4b..6cfcd23 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1286,7 +1286,7 @@ static void __init of_sunxi_table_clock_setup(const
struct of_device_id *clk_mat
*/
static void __init sunxi_clock_protect(void)
{
- struct clk *clk;
+ struct clk *clk, *parent;
/* memory bus clock - sun5i+ */
clk = clk_get(NULL, "mbus");
@@ -1309,6 +1309,22 @@ static void __init sunxi_clock_protect(void)
clk_put(clk);
}
+ clk = clk_get(NULL, "ahb1_mux");
+ if (IS_ERR(clk)) {
+ pr_err("Couldn't get AHB1 Mux\n");
+ return;
+ }
+
+ parent = clk_get(NULL, "pll6");
+ if (IS_ERR(clk)) {
+ pr_err("Couldn't get PLL6\n");
+ return;
+ }
+
+ clk_set_parent(clk, parent);
+
+ clk_put(clk);
+ clk_put(parent);
}
static void __init sunxi_init_clocks(void)
--
1.9.0
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[linux-sunxi] [PATCH 3/5] clk: sun6i: Protect SDRAM gating bit
Prevent the SDRAM controller from being gated by force-enabling it in the clock
driver.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6cfcd23..d9b4a41 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1302,6 +1302,13 @@ static void __init sunxi_clock_protect(void)
clk_put(clk);
}
+ /* DDR Gating clock - sun6i */
+ clk = clk_get(NULL, "ahb1_sdram");
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
/* CPU clocks - sun6i */
clk = clk_get(NULL, "cpu");
if (!IS_ERR(clk)) {
--
1.9.0
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[linux-sunxi] [PATCH 0/5] Add support for the Allwinner A31 DMA Controller
Hi, This patchset adds support for the DMA controller found in the Allwinner A31 and A23 SoCs. This has been tested using the newly introduced SPI driver on an A31 EVK. Support for DMA-driven SPI transfers will be the subject of another patch serie. Thanks, Maxime Maxime Ripard (5): clk: sun6i: Protect CPU clock clk: sun6i: Reparent AHB clock on PLL6 clk: sun6i: Protect SDRAM gating bit DMA: sun6i: Add driver for the Allwinner A31 DMA controller ARM: sun6i: dt: Add A31 DMA controller to DTSI .../devicetree/bindings/dma/sun6i-dma.txt | 45 + arch/arm/boot/dts/sun6i-a31.dtsi | 29 + drivers/clk/sunxi/clk-sunxi.c | 33 +- drivers/dma/Kconfig| 8 + drivers/dma/Makefile | 1 + drivers/dma/sun6i-dma.c| 960 + 6 files changed, 1075 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/dma/sun6i-dma.txt create mode 100644 drivers/dma/sun6i-dma.c -- 1.9.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] sun5i nand driver failed to format and init
Hi all, I am trying to install imagesfrom SD card to internal nand, first of all I need to locate the internal nand device /dev/nand, however I could not. dmesg reveals that something went wrong when the driver loaded: here are the error messages: [0.424664] [NAND] nand driver version: 0x2 0x9 [0.431936] PHY_PageReadSpare : too much ecc err,bank 0 block 7,page 0 ... ...(tons of them) [3.659593] PHY_PageReadSpare : too much ecc err,bank 0 block 7ff,page 0 [3.664674] [FORMAT_ERR] There is not enough valid block for using! [3.670086] [FORMAT_ERR] There is not enough free blocks for distribute! [3.673509] [FORMAT_ERR] Format nand disk failed! [3.675872] [NAND]init_blklayer fail Any idea what's going on? Is the nand driver 0x2 0x9 itself buggy? or something else? the stock Android runs well on the internal NAND, I doubt this is a real hardware failure? I also tried using Livesuit to reflash Android again, but after which it was the same dmesg. Thanks, -Hunter -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] Fedora porting in A20.
On 24-02-14 15:23, Puneet B wrote: Hi HNO, I fallow this link to boot fedora 19 in my A20 board. http://docs.cubieboard.org/tutorials/cb2/installation/cb2_fedora_19_card_install my device is booted fine. then i set root passwd and created an user. but if login both as root and user , device is showing always incorrect password. i double check it. but same result. How can i change root passwd and create one more user. You may have set up the wrong keyboard locale? As the procedure is 'guaranteed to work' more or less on a US keyboard for sure. I've done the installation a few times in the last few weeks and it worked fine, on a regular US keyboard layout. Anyway, a quick and easy fix is to shutdown fedora from the SD card, eject it from the board and put it in a carddreader of some sort. Put it in your other linux PC and mount /dev/sdb3 (or whever it ends up as) e.g. the rootfs. Edit to /mnt/lib/systemd/system/serial-getty@.service and find the line that says ... agetty and add agetty -a root this makes agetty on the serial port always login as root so if you connect via the serial port, you dont' have to log in, you can then easily change passwords as root. Not sure how the serial port and the keyboard locale on the GUI will relate however! Oliver Regards Punith -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] YUYV vs NV12 with camera
A few months ago I made this simple Android camera app that records a
sample of camera footage in h.264 to a file. The goal is to sort out
things on Android and then port over to Linux.
https://github.com/jonsmirl/cam
The app works in NV12 mode except the color space is messed up during
replay on VLC. So I tried commenting out a few lines and switching to
YUYV mode.
} else if (!tryFmt(V4L2_PIX_FMT_YUYV)) {
mCaptureFormat = V4L2_PIX_FMT_YUYV; // maybe usb camera
printf("capture format: V4L2_PIX_FMT_YUYV \n");
Putting the camera into this mode creates the bug I'm seeing on three
other Allwinner Android devices I have here. The color space is ok,
but something goes wrong in the buffering and the video frames are out
of order. This is a good bug to fix since every device I have here has
it.
Also, what is the standard color space for a h.264 stream?
--
Jon Smirl
jonsm...@gmail.com
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Re: [U-Boot] [linux-sunxi] Re: [PATCH v2 3/3] ahci: provide sunxi SATA driver using AHCI platform framework
On Thu, 2014-02-20 at 14:06 -0600, Rob Herring wrote:
> On Thu, Feb 20, 2014 at 10:06 AM, Ian Campbell wrote:
> > On Thu, 2014-02-20 at 09:24 -0600, Rob Herring wrote:
> >> > +#define AHCI_PHYCS0R 0x00c0
> >> > +#define AHCI_PHYCS1R 0x00c4
> >> > +#define AHCI_PHYCS2R 0x00c8
> > [...]
> >> > +#define AHCI_RWCR 0x00fc
> >
> >> These registers are not sunxi specific, but part of a certain vendor's
> >> IP found in several SOCs. I can't tell you who, but it shouldn't be
> >> too hard to figure out.
> >
> > Actually, only the 4 above are used here and if I'm guessing which
> > certain vendor you mean correctly then the code for those has these in
> > its register map as reserved and doesn't touch them (this is true in
> > both of the similar drivers I looked at).
> >
> > The rest of the registers in that list did look a lot the DW part
> > (judging from the existing u-boot drivers) though.
>
> There may be others that do this setup in firmware.
Someone pointed me to http://linux-sunxi.org/Used_IP_cores which
suggests that while the SATA block is DW the PHY might be Allwinner's
own -- that would fit with having found a bunch of unusual registers in
a gap in the DW address map...
In v3 I'll drop all the unused #defines, which apart from being the sane
thing to do ought to make it look less like I'm duplicating DW stuff
here.
> >> > +#define BIT(x) (1< >> > +static u32 sunxi_getbits(u8 *reg, u8 mask, u8 shift)
> >> > +{
> >> > + return (readl(reg) >> shift) & mask;
> >> > +}
> >> > +
> >> > +static int sunxi_ahci_phy_init(u32 base)
> >> > +{
> >> [...magic...]
> >> > +
> >>
> >> I would guess this code or something very similar already exists in u-boot.
> >
> > I've had a look in the most obvious files in drivers/block/ and I don't
> > see anything. Perhaps I should look harder.
> >
> > FWIW I also couldn't find anything similar in linux/drivers/ata.
>
> I thought iMX needed something like this, but it doesn't look like it
> now. Perhaps they figured out the bootrom is doing all this and it is
> not really necessary to redo.
>
> I don't really have any concrete suggestions here. I'm just
> highlighting potential duplication.
Thanks for doing so, I don't want to be responsible for YASD (Yet
Another SATA Driver...)
> We already have 2 AHCI drivers in
> u-boot. I think dwc_ahsata.c is the cleaner implementation, but ahci.c
> is probably more well tested now. The Chromium folks have done various
> fixes as has Calxeda. I think dwc_ahsata.c is only used for i.MX and
> SATA is not the primary storage interface for most i.MX designs.
It looked to me like the ahci.c one was a better bet going forward,
since it seems more generic etc and it supports the "platform ahci"
model, which was a good fit. Also I knew ahci.c was good from my use on
the Calxeda platforms.
I could try switching to dwc_ahsata.c if people strongly prefer.
Ian.
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[linux-sunxi] Fedora porting in A20.
Hi HNO, I fallow this link to boot fedora 19 in my A20 board. http://docs.cubieboard.org/tutorials/cb2/installation/cb2_fedora_19_card_install my device is booted fine. then i set root passwd and created an user. but if login both as root and user , device is showing always incorrect password. i double check it. but same result. How can i change root passwd and create one more user. Regards Punith -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: sunxi-devel branch updated to 3.14-rc3
UBOOT git clone https://github.com/jwrdegoede/u-boot-sunxi.git -b sunxi-devel Kernel git clone https://github.com/jwrdegoede/linux-sunxi.git -b sunxi-devel sunxi-devel-jwr CONFIG http://pastebin.com/vUEp0zce BOOT.CMD setenv bootargs console=tty0 console=ttyS0,115200 hdmi.audio=EDID:0 disp.screen0_output_mode=EDID:1280x800p60 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait panic=10 ext4load mmc 0 0x4300 boot/script.bin ext4load mmc 0 0x4600 boot/uImage ext4load mmc 0 0x4900 boot/cubie2.dtb env set fdt_high bootm 0x4600 - 0x4900 Em domingo, 23 de fevereiro de 2014 22h40min34s UTC-3, Kenny MacDermid escreveu: > > On Sunday, 23 February 2014 08:32:34 UTC-4, Hans de Goede wrote: >> >> Hi All, >> >> I've just updated: >> https://github.com/linux-sunxi/linux-sunxi/commits/sunxi-devel >> to 3.14-rc3. >> > > Just gave this a try on my SDXC card and I can't get it past: > > Waiting for root device /dev/mmcblk0p3... > > I have /boot on mmcblk0p1 and / on mmcblkp3. > > It boots fine with: > > Linux Cubian 3.14.0-rc2-64776-g6500a8b-dirty #7 SMP Sat Feb 22 03:20:57 > UTC 2014 armv7l GNU/Linux > > I built the newest tree with the same config plus one extra option it > asked me about. The kernel version is: > > Linux-3.14.0-rc3-64784-g5c5ac3f (config: http://pastebin.com/P6ya1Gx2) > > Any ideas? > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH v3 1/4] ARM: sunxi: Add driver for sunxi usb phy
Hi,
On Sunday 23 February 2014 05:39 PM, Hans de Goede wrote:
> The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
> through a single set of registers. Besides this there are also some other
> phy related bits which need poking, which are per phy, but shared between the
> ohci and ehci controllers, so these are also controlled from this new phy
> driver.
>
> Signed-off-by: Hans de Goede
> ---
> .../devicetree/bindings/phy/sun4i-usb-phy.txt | 26 ++
> drivers/phy/Kconfig| 11 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-sun4i-usb.c| 329
> +
> 4 files changed, 367 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> create mode 100644 drivers/phy/phy-sun4i-usb.c
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> new file mode 100644
> index 000..a82361b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -0,0 +1,26 @@
> +Allwinner sun4i USB PHY
> +---
> +
> +Required properties:
> +- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
> + "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
> +- reg : a list of offset + length pairs
> +- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
> +- #phy-cells : from the generic phy bindings, must be 1
> +- clocks : phandle + clock specifier for the phy clock
> +- clock-names : "usb_phy"
> +- resets : a list of phandle + reset specifier pairs
> +- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i
> "usb2_reset"
> +
> +Example:
> + usbphy: phy@0x01c13400 {
> + #phy-cells = <1>;
> + compatible = "allwinner,sun4i-a10-usb-phy";
> + /* phy base regs, phy1 pmu reg, phy2 pmu reg */
> + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
> + reg-names = "phy_ctrl", "pmu1", "pmu2";
> + clocks = <&usb_clk 8>;
> + clock-names = "usb_phy";
> + resets = <&usb_clk 1>, <&usb_clk 2>;
> + reset-names = "usb1_reset", "usb2_reset";
> + };
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 4ef8755..6e336b4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,15 @@ config BCM_KONA_USB2_PHY
> help
> Enable this to support the Broadcom Kona USB 2.0 PHY.
>
> +config PHY_SUN4I_USB
> + tristate "Allwinner sunxi SoC USB PHY driver"
> + depends on ARCH_SUNXI
> + select GENERIC_PHY
recently some errors have been reported if you don't have depends on HAS_IOMEM.
Also add depends on CONFIG_OF.
> + help
> + Enable this to support the transceiver that is part of Allwinner
> + sunxi SoCs.
> +
> + This driver controls the entire USB PHY block, both the USB OTG
> + parts, as well as the 2 regular USB 2 host PHYs.
> +
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..9d4f8bb 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) +=
> phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> new file mode 100644
> index 000..31c4611
> --- /dev/null
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -0,0 +1,329 @@
> +/*
> + * Allwinner sun4i USB phy driver
> + *
> + * Copyright (C) 2014 Hans de Goede
> + *
> + * Based on code from
> + * Allwinner Technology Co., Ltd.
> + *
> + * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Author: Sylwester Nawrocki
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define REG_ISCR 0x00
> +#define REG_PHYCTL 0x04
> +#define REG_PHYBIST 0x08
> +#define REG_PHYTUNE 0x0c
> +
> +#define SUNXI_AHB_ICHR8_EN BIT(
[linux-sunxi] Re: [PATCH v3 0/4] ARM: sunxi: Add driver for sunxi usb phy + usb dts bindings
Hi, On Sunday 23 February 2014 05:39 PM, Hans de Goede wrote: > Hi Kishon, Maxime, > > Here is v3 of my sunxi-usb-phy driver it addresses all review remarks made > in response to v2, and as such this should be the final version, changes: > > -Fix check for wrong variable in error handling path pointed out by wens > -Switch to using reg-names to differentiate between the different register > ranges needed > > Kishon, can you please queue up the 1st patch of this series for 3.15 ? huh.. maybe I failed to notice that before but the $subject for that patch should be 'PHY: sunxi...' and not 'ARM: sunxi..'. Can you fix that up? Thanks Kishon > > Maxime, can you please add patches 2-4 to your dt-for-3.15 branch? Note these > are only the dtsi bits. > > I'm holding back all the board .dts patches until it is clear how we want to > deal with the ahci + usb regulator bits. Specifically I'm waiting for an > answer > to this question: > > "I hope this helps explain my reasoning, as said I'm fine with > either way, if you want to change over to a single file + > explicit enabling, let me know and I'll respin the ahci dts > patches. Note I'm going on vacation for a week starting Monday, > so you likely won't get a new version until next weekend." > > In my last reply to "[PATCH v6 17/18] ARM: sun4i: dt: Add ahci / sata support" > > I've a feeling you (Maxime) want me to rework things in to a single dtsi > for all common regulators + explicit enabling, which works for me, but before > doing the necessary refactoring I would like to hear that this is what you > want from you. > > Regards, > > Hans > > > p.s. > > I'm going on vacation for 5 days leaving tomorrow, so I won't send the > (refactored) board .dts file patches until next weekend. > > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH v3 1/4] ARM: sunxi: Add driver for sunxi usb phy
Hi, On Sun, Feb 23, 2014 at 01:09:09PM +0100, Hans de Goede wrote: > The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed > through a single set of registers. Besides this there are also some other > phy related bits which need poking, which are per phy, but shared between the > ohci and ehci controllers, so these are also controlled from this new phy > driver. > > Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH v7 13/15] ARM: sun4i: dt: Remove grouping + simple-bus compatible for regulators
On Sun, Feb 23, 2014 at 09:03:48AM +0100, Hans de Goede wrote: > Thanks, I assume this only applies to this patch, since we were still > discussing the common regulator bits of the ahci enablement dts patches ? Yes. > I'm not seeing any of your recent merges here: > https://github.com/mripard/linux/commits/sunxi/dt-for-3.15 > > Did you not push them, or am I looking at the wrong tree ? I forgot to push it. It's fixed now. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [linux-sunxi] [A20-Cubietruck] Arm Security extensions
Well, I was planning adding/testing support for these, but to say documentation is scarce would be a compliment. The true is that documentation is mostly nonexistent. There is a proof of concept userspace code by Emilio Lopez at https://bitbucket.org/emiliolopez/ss-poc and a patch to add support to the Security System to the linux-sunxi kernel by LABBE Corentin at https://groups.google.com/forum/#!topic/linux-sunxi/PWh42vMXLAs. On Wed, Feb 19, 2014 at 12:46 PM, Aaditya wrote: > Hello All, > > Does any anybody know whether A20 chip on Cubietruck board implements > ARM security extensions. > The A20 Manual does not mention any thing about ARM security extensions. > > Thanks, > Aaditya. > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/groups/opt_out. > -- Jorge Nerín -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH 0/7] Add Allwinner A10 SPI Controller Driver
On Sat, Feb 22, 2014 at 10:35:52PM +0100, Maxime Ripard wrote: > Hi, > > This patchset brings support for the SPI controller found in the > Allwinner A10 and derived SoCs. > > Even though the controller supports DMA, the driver only supports PIO > mode for now. This driver will be used to bring up and test DMA on the > SoC, so support for the DMA will come eventually. > > It doesn't support transfer larger than the FIFO size (64 bytes) for > now, It's one of the things that will be fixed whenever we will have > DMA support. Applied patches 2-7 to sunxi/dt-for-3.15 -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH 1/7] spi: sunxi: Add Allwinner A10 SPI controller driver
Hi, On Sun, Feb 23, 2014 at 11:15:30AM +0900, Mark Brown wrote: > On Sat, Feb 22, 2014 at 10:35:53PM +0100, Maxime Ripard wrote: > > The older Allwinner SoCs (A10, A13, A10s and A20) all have the > > same SPI controller. > > Applied, thanks. Please differentiate between these two devices in > the subject line when sending patches for example by using "sun6i" > and "sun4i". Ok, will do. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: How to enable SPI kernel support on sun7i device?
I'm using https://github.com/linux-sunxi/linux-sunxi sunxi-3.4 kernel, and at first glance at the file drivers/spi/Kconfig it seems that there is only sun4i and sun5i support. Looking at other threads in this list it seems that there exists support for sun7i devices, please could anybody tell in which repository could I find a kernel with spi sun7i support? El lunes, 24 de febrero de 2014 09:23:09 UTC+1, Daniel Mosquera escribió: > > Hi, > > I'm trying to use the SPI port in a sun7i board, but in linux-sunxi > documentation I can only find how to enable it for sun4i devices. > > Please can anybody explain how to enable SPI in sun7i devices? > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] How to enable SPI kernel support on sun7i device?
Hi, I'm trying to use the SPI port in a sun7i board, but in linux-sunxi documentation I can only find how to enable it for sun4i devices. Please can anybody explain how to enable SPI in sun7i devices? -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
