Re: [linux-sunxi] sun6i SPL support status update

2014-04-01 Thread Koen Kooi

Op 1 apr. 2014, om 21:55 heeft Olliver Schinagl  het 
volgende geschreven:

> On 03/31/2014 08:27 AM, Chen-Yu Tsai wrote:
>> Hi Hans,
>> 
>> On Sun, Mar 30, 2014 at 8:04 PM, Hans de Goede  wrote:
>>> Hi,
>>> 
>>> After wens pointed me to:
>>> http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;h=9275ca21ac99592c7d520a41c0914b359c27b913;hb=refs/heads/lichee/jb-4.2.2-a31
>>> 
>>> I've tried to get a full SPL going on sun6i. No luck sofar,
>>> dropping in dram_sun6i.[c,h] +pll5 config seems to get the dram
>>> going, at least get_ram_size() likes it. But I cannot get the
>>> mmc to work in the SPL. I've narrowed this down to 2  problems,
>>> which I believe are related:
>>> 
>>> 1) The mmc controller will simply not work with pll6 as source,
>>> after adding a test for the pll6 lock bit I believe this is caused
>>> by pll6 never locking.
>>> 
>>> 2) When switching the mmc controller clocksource to OSC24M, then
>>> it does work, but gets stuck reading the first sector from the card.
>>> I believe this happens because the card is only being supplied 3.0V'
>>> rather then 3.3V.
>>> 
>>> Note that the same code works fine in the no SPL u-boot when loaded
>>> through boot0 + boot1.
>>> 
>>> Likely wrong power supply voltages are the culprit in both cases
>>> (the A31 also has a vdd-pll power pin.
>>> 
>>> So it looks like the next step is to first get the pmic going in
>>> u-boot (which will be useful even if booted through boot0 + 1, to
>>> enable the nic-phy if nothing else).
>> 
>> The A23 lichee u-boot has drivers for P2WI (used in sun6i) and RSB
>> (reduced serial bus, used on A23):
> Are they not the same? I haven't looked I admit, I just figured they changed 
> the name a little to make it sound distinctive.
> 
> Are they similar at all? If so, I guess that the i2c vs p2wi discussion held 
> a few days ago is moot then :)

"2 wire interface" is a way of avoiding paying NXP royalties for I2C while 
still producing the same hardware :)

regards,

Koen


> 
> Olliver
>> 
>> https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/p2wi
>> https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/rsb
>> 
>> And also PMIC drivers:
>> 
>> https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/power
>> 
>> Judging from the code, my guess is AXP221 and AXP223 or differ in
>> the type of interface supported.
>> 
>> Hope this helps. :)
>> 
>>> And then see from there. Maybe I'll take a shot at this tonight,
>>> for now I'm going to spend some time with my family.
>> 
>> 
>> Cheers,
>> ChenYu
>> 
> 
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Re: [linux-sunxi] Re: Build sunxi-next for A20

2014-04-01 Thread Olliver Schinagl

On 04/01/2014 10:04 PM, hmandevt...@gmail.com wrote:

I saw that Hans have a 3.13 branch
https://github.com/jwrdegoede/linux-sunxi/tree/sunxi-3.13

so, is it possible to use sunxi-fedora-scripts
https://github.com/jwrdegoede/sunxi-fedora-scripts

to build uboot and kernel image with this kernel ?
As long as you realize that the 3.13 kernel miss a lot of features ... 
Things like display etc.


But I don't see why not :)

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Re: [linux-sunxi] Current u-boot crashes my cubietruck!

2014-04-01 Thread Olliver Schinagl

Top Posting!

I found the culprit. FAST_MBUS breaks it. After 48 hours of runs, 
enabling fast_mbus immediately breaks it even after boot.


Jens and Emilio hinted that the 3.4 driver reads the FEX file for the 
voltage. So the higher freq. runs at a lower voltage and that may cause it.


So I'll run without fast mbus for now, and it's stable again. Rock Solid 
if I may.


Sorry for all the noise :(

Olliver

On 03/30/2014 08:56 PM, Olliver Schinagl wrote:

On 03/30/2014 05:59 PM, Ian Campbell wrote:

On Sun, 2014-03-30 at 14:26 +0200, Olliver Schinagl wrote:

That said the sorts of random crashed you've been posting sound a lot
like either a DRAM issue or overheating. Either of which could be down
to u-boot setting up something wrong or bad hardware I suppose.

Overheating, maybe. It feels hottish to the touch, but can hold a finger
on it without any problem whatsoever. Not close to the pain point. So I
estimate < 50 C? Shouldn't be reason to be concerned imo.


Doesn't sound like it.


Power might be the problem, i see the input voltage under heavy load
drop to 4.65 Volts @ 0.9 amps


Could be that.


Have you checked the checksum of the tarball you are extracting and
tried unpacking it on a known good system?

The sha1sum matches, calculated on the board, so that's good. xz -d
completed successfully!

tar xvf fails however, with a big ass 5 page long oops.


I'd have thought that xz -d would be *far* more CPU intensive and
therefore liable to cause issues than tar xvf. If you were using
spinning rust rather than an SSD then I would be inclined to suspect the
power draw, but with you using an SSD I'm just not sure.


I agree! though even a heavily stressed CPU doesn't change power draw
hugely. Ssvb and I did some power tests a few months ago on the list.

Additionally! I should mention, my CT has a battery backup which should
be near full charge. a 1220 mAh battery, so even if the power supply
should drop to low or something, Wens assured me that the battery would
take over and no problem should be caused by bad power. Unless the
battery has run down of course, which I highly doubt, especially seeing
the constant current draw over USB.

So for now, I just hope it's not user error ...

Olliver



Ian.





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Re: [linux-sunxi] Re: Build sunxi-next for A20

2014-04-01 Thread hmandevteam
I saw that Hans have a 3.13 branch
https://github.com/jwrdegoede/linux-sunxi/tree/sunxi-3.13

so, is it possible to use sunxi-fedora-scripts
https://github.com/jwrdegoede/sunxi-fedora-scripts

to build uboot and kernel image with this kernel ?

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Re: [linux-sunxi] Current u-boot crashes my cubietruck!

2014-04-01 Thread Michal Suchanek
On 1 April 2014 15:48, Siarhei Siamashka  wrote:
> On Sun, 30 Mar 2014 20:56:57 +0200
> Olliver Schinagl  wrote:
>

> Too bad that really few people are willing or able to do the current
> draw measurements on their hardware. But at the same time, tweaking
> the CPU clock speed seems to be somewhat popular. It is not good when
> people overclock their CPU and decide that this is 'stable' after
> only letting it idle for a while. Then the very same people may
> encounter problems later and blame the first random thing that
> seems to be 'wrong' in their opinion, for example using the
> non-mainline kernel :-)
>
> To make power consumption measurements easier even for inexperienced
> users, I tried to hack on the AXP209 voltage/current monitoring support
> and sent some preliminary patches:
>
> https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg03447.html

This is very nice.

There is always this option
http://www.dx.com/p/usb-av-usb-power-current-voltage-tester-translucent-blue-silver-235090
but you still have to power down the board, find enough adaptors to
put that thing in between the board and the PSU, and then the
measurements aren't scriptable, anyway.

Thanks

Michal

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Re: [linux-sunxi] [PATCH u-boot-sunxi 00/23] Add sun6i / A31 support (no SPL)

2014-04-01 Thread Olliver Schinagl

Hans and Maxime

Many thanks for working on this! I just wanted to share my appreciation 
on the whole series.


Also I see you have found use of my random patches i was typing without 
compile testing, without hardware ;) Hans, I do hope you saw my my notes 
that i started to make on one of the github commits pointing out some 
obvious mistakes that I made while hacking late at night many months ago!


I hope you received my other e-mail as well?

Thanks you two! Well everybody for all the hacking!

Olliver

On 04/01/2014 01:28 PM, Hans de Goede wrote:

Hi All,

This patch series adds basic support for sun6i. There are some bits there
to get SPL support going (clock setup, axp related code has been tested in SPL
mode too), but DRAM setup is missing, so no SPL support.

This series will give you a u-boot.bin binary which can be used to generate
the u-boot.bin on an sdcard image generated by the allwinner tools.

This u-boot.bin supports reading from mmc, has proper fdt support, and
properly sets up all the power supply voltages on the axp221:
-properly power the gpio's and sdcard at 3.3v, rather then undervolt them at 3v
-activate ldo1, and thus give power to the phy, so now we can go and test wens
  gmac for a31 work

If there are no objections I plan to push this series to the u-boot-sunxi repo
sunxi branch in a couple of days. In the mean time you can find it here:
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221

Regards,

Hans



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Re: [linux-sunxi] sun6i SPL support status update

2014-04-01 Thread Olliver Schinagl

On 03/31/2014 08:27 AM, Chen-Yu Tsai wrote:

Hi Hans,

On Sun, Mar 30, 2014 at 8:04 PM, Hans de Goede  wrote:

Hi,

After wens pointed me to:
http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;h=9275ca21ac99592c7d520a41c0914b359c27b913;hb=refs/heads/lichee/jb-4.2.2-a31

I've tried to get a full SPL going on sun6i. No luck sofar,
dropping in dram_sun6i.[c,h] +pll5 config seems to get the dram
going, at least get_ram_size() likes it. But I cannot get the
mmc to work in the SPL. I've narrowed this down to 2  problems,
which I believe are related:

1) The mmc controller will simply not work with pll6 as source,
after adding a test for the pll6 lock bit I believe this is caused
by pll6 never locking.

2) When switching the mmc controller clocksource to OSC24M, then
it does work, but gets stuck reading the first sector from the card.
I believe this happens because the card is only being supplied 3.0V'
rather then 3.3V.

Note that the same code works fine in the no SPL u-boot when loaded
through boot0 + boot1.

Likely wrong power supply voltages are the culprit in both cases
(the A31 also has a vdd-pll power pin.

So it looks like the next step is to first get the pmic going in
u-boot (which will be useful even if booted through boot0 + 1, to
enable the nic-phy if nothing else).


The A23 lichee u-boot has drivers for P2WI (used in sun6i) and RSB
(reduced serial bus, used on A23):
Are they not the same? I haven't looked I admit, I just figured they 
changed the name a little to make it sound distinctive.


Are they similar at all? If so, I guess that the i2c vs p2wi discussion 
held a few days ago is moot then :)


Olliver


https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/p2wi
https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/rsb

And also PMIC drivers:

https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/power

Judging from the code, my guess is AXP221 and AXP223 or differ in
the type of interface supported.

Hope this helps. :)


And then see from there. Maybe I'll take a shot at this tonight,
for now I'm going to spend some time with my family.



Cheers,
ChenYu



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Re: [linux-sunxi] Current u-boot crashes my cubietruck!

2014-04-01 Thread Olliver Schinagl

On 03/30/2014 08:56 PM, Olliver Schinagl wrote:

On 03/30/2014 05:59 PM, Ian Campbell wrote:

On Sun, 2014-03-30 at 14:26 +0200, Olliver Schinagl wrote:

That said the sorts of random crashed you've been posting sound a lot
like either a DRAM issue or overheating. Either of which could be down
to u-boot setting up something wrong or bad hardware I suppose.

Overheating, maybe. It feels hottish to the touch, but can hold a finger
on it without any problem whatsoever. Not close to the pain point. So I
estimate < 50 C? Shouldn't be reason to be concerned imo.


Doesn't sound like it.


Power might be the problem, i see the input voltage under heavy load
drop to 4.65 Volts @ 0.9 amps


Could be that.


Have you checked the checksum of the tarball you are extracting and
tried unpacking it on a known good system?

The sha1sum matches, calculated on the board, so that's good. xz -d
completed successfully!

tar xvf fails however, with a big ass 5 page long oops.


I'd have thought that xz -d would be *far* more CPU intensive and
therefore liable to cause issues than tar xvf. If you were using
spinning rust rather than an SSD then I would be inclined to suspect the
power draw, but with you using an SSD I'm just not sure.


I agree! though even a heavily stressed CPU doesn't change power draw
hugely. Ssvb and I did some power tests a few months ago on the list.

Additionally! I should mention, my CT has a battery backup which should
be near full charge. a 1220 mAh battery, so even if the power supply
should drop to low or something, Wens assured me that the battery would
take over and no problem should be caused by bad power. Unless the
battery has run down of course, which I highly doubt, especially seeing
the constant current draw over USB.

So for now, I just hope it's not user error ...

It is not, it is FAST_MBUS,

the board is still happily compiling, 24 hours later, latest u-boot, but 
without FAST_MBUS. It managed to do about 43 compiles this time :)


So for now, FAST_MBUS should be conciderd an 'overclocking option'. I'll 
try to enable it again;a nd maybe tune the voltage a little higher, then 
again; i don't have time fort hat right now ...


Olliver


Olliver



Ian.





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[linux-sunxi] [PATCHv2 3.4 2/4] sunxi: axp20x: Human readable label for the temperature sensor

2014-04-01 Thread Siarhei Siamashka
Signed-off-by: Siarhei Siamashka 
---
 drivers/power/axp_power/axp20-mfd.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/power/axp_power/axp20-mfd.h 
b/drivers/power/axp_power/axp20-mfd.h
index 0021fb5..6ec26f6 100644
--- a/drivers/power/axp_power/axp20-mfd.h
+++ b/drivers/power/axp_power/axp20-mfd.h
@@ -39,6 +39,8 @@ show_temp(struct device *dev, struct device_attribute 
*devattr, char *buf)
return sprintf(buf, "264800\n");
if (attr->index == 2)
return sprintf(buf, "-144700\n");
+   if (attr->index == 3)
+   return sprintf(buf, "AXP20X temperature\n");
return sprintf(buf, "%d\n", data->temperature * 100);
 }
 
@@ -46,11 +48,13 @@ show_temp(struct device *dev, struct device_attribute 
*devattr, char *buf)
 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0);
 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL, 1);
 static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, NULL, 2);
+static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_temp, NULL, 3);
 
 static struct attribute *axp20_attributes[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
+   &sensor_dev_attr_temp1_label.dev_attr.attr,
NULL
 };
 
-- 
1.8.3.2

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[linux-sunxi] [PATCHv2 3.4 1/4] sunxi: axp20x: Fix misuse of the lowest 4-bits of temperature ADC

2014-04-01 Thread Siarhei Siamashka
Apparently bitwise '&' operator was supposed to be used here
instead of logical '&&'.

Signed-off-by: Siarhei Siamashka 
---
 drivers/power/axp_power/axp20-mfd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/power/axp_power/axp20-mfd.h 
b/drivers/power/axp_power/axp20-mfd.h
index 214856e..0021fb5 100644
--- a/drivers/power/axp_power/axp20-mfd.h
+++ b/drivers/power/axp_power/axp20-mfd.h
@@ -88,7 +88,7 @@ static struct axp_mfd_chip *axp20_update_device(struct device 
*dev)
low = 0;
}
 
-   data->temperature = -1447 + ((high << 4) + (low && 0x0F));
+   data->temperature = -1447 + ((high << 4) + (low & 0x0F));
data->last_updated = jiffies;
data->valid = 1;
}
-- 
1.8.3.2

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[linux-sunxi] [PATCHv2 3.4 4/4] sunxi: axp20x: Calculate moving average for ACIN voltage/current/power

2014-04-01 Thread Siarhei Siamashka
As long as somebody is regularly accessing axp20x hwmon sysfs entries,
maintain a work queue for 25Hz periodic sampling of ACIN voltage/current
information. And calculate moving average using this data. This periodic
sampling stops after ~1 minute from the last access to axp20x hwmon sysfs.

Comparison of the current draw (in mA) for different workloads, measured
by the axp20x hwmon averaged stats (on the left side) and with a multimeter
(on the right side). The following sunxi based hardware has been tested
(without anything extra connected to USB/SATA):

Olinuxino-Lime (Allwinner A10):
   300  315
   555  590
   990 1060

Cubietruck (Allwinner A20):
   215  240
   310  345
   730  800

Cubieboard2 (Allwinner A20):
80  245
   180  415
   325  610
   490  820

Mele A2000 (Allwinner A10):
   180  450
   280  560
   450  770

AXP209 on Olinuxino-Lime and Cubietruck reports reasonably accurate
results. But not so much for the other devices.

v2: The decision whether to run periodic sampling is now fully
automatic. No configuration is needed. And no parasitic background
activity is expected when nobody is interested in axp20x hwmon
sysfs data.

Signed-off-by: Siarhei Siamashka 
---
 drivers/power/axp_power/axp-mfd.c   |  4 +++
 drivers/power/axp_power/axp20-mfd.h | 68 +
 include/linux/mfd/axp-mfd.h |  3 ++
 3 files changed, 69 insertions(+), 6 deletions(-)

diff --git a/drivers/power/axp_power/axp-mfd.c 
b/drivers/power/axp_power/axp-mfd.c
index cfa894a..6fd1264 100644
--- a/drivers/power/axp_power/axp-mfd.c
+++ b/drivers/power/axp_power/axp-mfd.c
@@ -365,6 +365,10 @@ static int __devexit axp_mfd_remove(struct i2c_client 
*client)
 
 #ifdef CONFIG_AXP_HWMON
if (chip->itm_enabled == 1) {
+   cancel_delayed_work(&axp_hwmon_work);
+   flush_workqueue(wq);
+   destroy_workqueue(wq);
+
hwmon_device_unregister(chip->hwmon_dev);
sysfs_remove_group(&client->dev.kobj, &axp20_group);
}
diff --git a/drivers/power/axp_power/axp20-mfd.h 
b/drivers/power/axp_power/axp20-mfd.h
index 4244d49..fe7aeb1 100644
--- a/drivers/power/axp_power/axp20-mfd.h
+++ b/drivers/power/axp_power/axp20-mfd.h
@@ -28,13 +28,14 @@
 #include 
 #include 
 
-static struct axp_mfd_chip *axp20_update_device(struct device *dev);
+static struct
+axp_mfd_chip *axp20_update_device(struct device *dev, int from_wq);
 
 static ssize_t
 show_temp(struct device *dev, struct device_attribute *devattr, char *buf)
 {
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
-   struct axp_mfd_chip *data = axp20_update_device(dev);
+   struct axp_mfd_chip *data = axp20_update_device(dev, 0);
if (attr->index == 1)
return sprintf(buf, "264800\n");
if (attr->index == 2)
@@ -49,9 +50,11 @@ show_acin_voltage(struct device *dev, struct 
device_attribute *devattr,
  char *buf)
 {
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
-   struct axp_mfd_chip *data = axp20_update_device(dev);
+   struct axp_mfd_chip *data = axp20_update_device(dev, 0);
if (attr->index == 3)
return sprintf(buf, "ACIN voltage\n");
+   if (attr->index == 4)
+   return sprintf(buf, "%d\n", data->acin_avg_voltage / 64);
return sprintf(buf, "%d\n", data->acin_voltage);
 }
 
@@ -60,9 +63,11 @@ show_acin_current(struct device *dev, struct 
device_attribute *devattr,
  char *buf)
 {
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
-   struct axp_mfd_chip *data = axp20_update_device(dev);
+   struct axp_mfd_chip *data = axp20_update_device(dev, 0);
if (attr->index == 3)
return sprintf(buf, "ACIN current\n");
+   if (attr->index == 4)
+   return sprintf(buf, "%d\n", data->acin_avg_current / 64);
return sprintf(buf, "%d\n", data->acin_current);
 }
 
@@ -70,9 +75,11 @@ static ssize_t
 show_acin_power(struct device *dev, struct device_attribute *devattr, char 
*buf)
 {
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
-   struct axp_mfd_chip *data = axp20_update_device(dev);
+   struct axp_mfd_chip *data = axp20_update_device(dev, 0);
if (attr->index == 3)
return sprintf(buf, "ACIN power\n");
+   if (attr->index == 4)
+   return sprintf(buf, "%d\n", data->acin_avg_power / 64);
return sprintf(buf, "%d\n", data->acin_power);
 }
 
@@ -82,10 +89,13 @@ static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, 
NULL, 2);
 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_temp, NULL, 3);
 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_acin_voltage, NULL, 0);
 static SENSOR_DEVICE_ATTR(

[linux-sunxi] [PATCHv2 3.4 3/4] sunxi: axp20x: Report voltage, current and power for ACIN connector

2014-04-01 Thread Siarhei Siamashka
These measurements for ACIN (adapter input) are just the momentary
values sampled from ADC. But in order to have something more practical,
a lot of values need to be sampled and averaged. Just obtaining a
single output from the 'sensors' tool is not very meaningful,
because the momentary current draw changes very fast and within
a rather wide range (jumping up and down +-50% is not very uncommon).

To make accurate measurements possible at least from the userland,
it is unreasonable to limit the frequency of sysfs hwmon entries
update to just one read per two seconds. So this limitation has
been relaxed to allow polling at 50Hz.

v2: The measurement of ACIN current is done before anything else
because it is the most volatile parameter. And we want to
reduce the chances of the results being skewed by the CPU
activity related to reading the hwmon sysfs entry itself.

Signed-off-by: Siarhei Siamashka 
---
 drivers/power/axp_power/axp20-mfd.h | 92 +++--
 include/linux/mfd/axp-mfd.h |  3 ++
 2 files changed, 80 insertions(+), 15 deletions(-)

diff --git a/drivers/power/axp_power/axp20-mfd.h 
b/drivers/power/axp_power/axp20-mfd.h
index 6ec26f6..4244d49 100644
--- a/drivers/power/axp_power/axp20-mfd.h
+++ b/drivers/power/axp_power/axp20-mfd.h
@@ -44,17 +44,60 @@ show_temp(struct device *dev, struct device_attribute 
*devattr, char *buf)
return sprintf(buf, "%d\n", data->temperature * 100);
 }
 
+static ssize_t
+show_acin_voltage(struct device *dev, struct device_attribute *devattr,
+ char *buf)
+{
+   struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+   struct axp_mfd_chip *data = axp20_update_device(dev);
+   if (attr->index == 3)
+   return sprintf(buf, "ACIN voltage\n");
+   return sprintf(buf, "%d\n", data->acin_voltage);
+}
+
+static ssize_t
+show_acin_current(struct device *dev, struct device_attribute *devattr,
+ char *buf)
+{
+   struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+   struct axp_mfd_chip *data = axp20_update_device(dev);
+   if (attr->index == 3)
+   return sprintf(buf, "ACIN current\n");
+   return sprintf(buf, "%d\n", data->acin_current);
+}
+
+static ssize_t
+show_acin_power(struct device *dev, struct device_attribute *devattr, char 
*buf)
+{
+   struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+   struct axp_mfd_chip *data = axp20_update_device(dev);
+   if (attr->index == 3)
+   return sprintf(buf, "ACIN power\n");
+   return sprintf(buf, "%d\n", data->acin_power);
+}
 
 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0);
 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL, 1);
 static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, NULL, 2);
 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_temp, NULL, 3);
+static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_acin_voltage, NULL, 0);
+static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, show_acin_voltage, NULL, 3);
+static SENSOR_DEVICE_ATTR(curr1_input, S_IRUGO, show_acin_current, NULL, 0);
+static SENSOR_DEVICE_ATTR(curr1_label, S_IRUGO, show_acin_current, NULL, 3);
+static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, show_acin_power, NULL, 0);
+static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, show_acin_power, NULL, 3);
 
 static struct attribute *axp20_attributes[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_label.dev_attr.attr,
+   &sensor_dev_attr_in0_input.dev_attr.attr,
+   &sensor_dev_attr_in0_label.dev_attr.attr,
+   &sensor_dev_attr_curr1_input.dev_attr.attr,
+   &sensor_dev_attr_curr1_label.dev_attr.attr,
+   &sensor_dev_attr_power1_input.dev_attr.attr,
+   &sensor_dev_attr_power1_label.dev_attr.attr,
NULL
 };
 
@@ -62,6 +105,25 @@ static const struct attribute_group axp20_group = {
.attrs = axp20_attributes,
 };
 
+static int axp_read_adc(struct device *dev, struct i2c_client *client, int reg)
+{
+   int err;
+   u8 high, low;
+
+   err = __axp_read(client, reg, &high);
+   if (err) {
+   dev_err(dev, "AXP Error while reading REG 0x%02X\n", reg);
+   high = 0;
+   }
+
+   err = __axp_read(client, reg + 1, &low);
+   if (err) {
+   dev_err(dev, "AXP Error while reading REG 0x%02X\n", reg + 1);
+   low = 0;
+   }
+
+   return (high << 4) + (low & 0x0F);
+}
 
 /*
  *  * function that update the status of the chips (temperature)
@@ -70,29 +132,29 @@ static struct axp_mfd_chip *axp20_update_device(struct 
device *dev)
 {
struct i2c_client *client = to_i2c_client(dev);
struct axp_mfd_chip *data = i2c_get_clientdata(client);
-   int err;
-   u8 high, low;
+   int adc_value;
 
mutex_lo

[linux-sunxi] [PATCHv2 3.4 0/4] Use AXP209 for the power consumption measurements

2014-04-01 Thread Siarhei Siamashka
These patches allow reasonably accurate voltage, current and power
consumption measurements on at least some of the Allwinner A10/A20 based
development boards using lm-sensors or by directly reading from sysfs.

So that some basic power consumption measurements can be done even by ordinary
users. Without access to lab power supplies, multimeters, cutting wires
and/or soldering :-)

These patches are also available here:
https://github.com/ssvb/linux-sunxi/commits/20140401-axp209-hwmon-v2

Example of a Cubietruck running under heavy load:

$ sensors
axp20_mfd-i2c-0-34
Adapter: sunxi-i2c.0
ACIN voltage:+5.03 V  (avg =  +5.01 V)
AXP20X temperature:  +57.6 C  (low  = -144.7 C, high = +264.8 C)
ACIN power:   3.02 W  (avg =   3.50 W)
ACIN current:+0.60 A  (avg =  +0.70 A)

For testing it is possible to run something like:

$ while sleep 5; do sensors; done;

And then try different CPU / GPU workloads. The reported 'avg' numbers
on the Cubietruck and on the A10-LIME should be pretty close to the numbers
measured by other methods (no more than 10% difference observed in my
tests). However there are some limitations. For example, USB peripherals
are apparently bypassing AXP209 on the Cubietruck and are not accounted
for. There is no such problem with the A10-LIME.

Some other devices (such as Cubieboard2 and Mele A2000) are showing
unrealistically low current draw. Apparently even more stuff is bypassing
AXP209 there. Or maybe just the calibration is off.

If anyone also has some means to measure voltage/current on some sunxi
hardware, please compare it with the information reported by the 'sensors'
tool after applying these patches and report your findings. Thanks.


v2: The decision whether to run periodic sampling is now fully
automatic. No configuration is needed. And no parasitic background
activity is expected when nobody is interested in axp20x hwmon
sysfs data.

Siarhei Siamashka (4):
  sunxi: axp20x: Fix misuse of the lowest 4-bits of temperature ADC
  sunxi: axp20x: Human readable label for the temperature sensor
  sunxi: axp20x: Report voltage, current and power for ACIN connector
  sunxi: axp20x: Calculate moving average for ACIN voltage/current/power

 drivers/power/axp_power/axp-mfd.c   |   4 +
 drivers/power/axp_power/axp20-mfd.h | 156 
 include/linux/mfd/axp-mfd.h |   6 ++
 3 files changed, 149 insertions(+), 17 deletions(-)

-- 
1.8.3.2

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[linux-sunxi] [PATCH RESEND v5] ARM: sun4i: spi: Allow transfers larger than FIFO size

2014-04-01 Thread Alexandru Gagniuc
SPI transfers were limited to one FIFO depth, which is 64 bytes.
This was an artificial limitation, however, as the hardware can handle
much larger bursts. To accommodate this, we enable the interrupt when
the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt
handler. The 3/4 ratio was chosen arbitrarily, with the intention to
reduce the potential number of interrupts.

Since the SUN4I_CTL_TP bit is set, the hardware will pause
transmission whenever the FIFO is full, so there is no risk of losing
data if we can't service the interrupt in time.

For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to
replenish the FIFO on large SPI bursts. This requires more care in
when the interrupt is left enabled, as this interrupt will continually
trigger when the FIFO is less than 1/4 full, even though we
acknowledge it.

Signed-off-by: Alexandru Gagniuc 
Acked-by: Maxime Ripard 
---

Changes from v4:
 * use min3() instead of two if statements in sun4i_spi_fill_fifo()
 * fix trivial whitespace issue in if statement in sun4i_spi_handler()
 * use consistent style in assigning 'reg' in the added functions.

 drivers/spi/spi-sun4i.c | 71 ++---
 1 file changed, 62 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index 3f82705..d80ceba 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -47,6 +47,8 @@
 #define SUN4I_CTL_TP   BIT(18)

 #define SUN4I_INT_CTL_REG  0x0c
+#define SUN4I_INT_CTL_RF_F34   BIT(4)
+#define SUN4I_INT_CTL_TF_E34   BIT(12)
 #define SUN4I_INT_CTL_TC   BIT(16)

 #define SUN4I_INT_STA_REG  0x10
@@ -62,11 +64,14 @@
 #define SUN4I_CLK_CTL_CDR1(div)(((div) & 
SUN4I_CLK_CTL_CDR1_MASK) << 8)
 #define SUN4I_CLK_CTL_DRS  BIT(12)

+#define SUN4I_MAX_XFER_SIZE0xff
+
 #define SUN4I_BURST_CNT_REG0x20
-#define SUN4I_BURST_CNT(cnt)   ((cnt) & 0xff)
+#define SUN4I_BURST_CNT(cnt)   ((cnt) & SUN4I_MAX_XFER_SIZE)

 #define SUN4I_XMIT_CNT_REG 0x24
-#define SUN4I_XMIT_CNT(cnt)((cnt) & 0xff)
+#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
+

 #define SUN4I_FIFO_STA_REG 0x28
 #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
@@ -97,6 +102,27 @@ static inline void sun4i_spi_write(struct sun4i_spi *sspi, 
u32 reg, u32 value)
writel(value, sspi->base_addr + reg);
 }

+static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
+{
+   u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
+   reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
+   return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
+}
+
+static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
+{
+   u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
+   reg |= mask;
+   sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
+}
+
+static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 
mask)
+{
+   u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
+   reg &= ~mask;
+   sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
+}
+
 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
 {
u32 reg, cnt;
@@ -119,10 +145,13 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi 
*sspi, int len)

 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
 {
+   u32 cnt;
u8 byte;

-   if (len > sspi->len)
-   len = sspi->len;
+   /* See how much data we can fit */
+   cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
+
+   len = min3(len, (int)cnt, sspi->len);

while (len--) {
byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
@@ -175,8 +204,8 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
int ret = 0;
u32 reg;

-   /* We don't support transfer larger than the FIFO */
-   if (tfr->len > SUN4I_FIFO_DEPTH)
+   /* This is the maximum SPI burst size supported by the hardware */
+   if (tfr->len > SUN4I_MAX_XFER_SIZE)
return -EINVAL;

reinit_completion(&sspi->done);
@@ -274,7 +303,10 @@ static int sun4i_spi_transfer_one(struct spi_master 
*master,
sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);

/* Enable the interrupts */
-   sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
+   sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC | 
SUN4I_INT_CTL_RF_F34);
+   /* Only enable Tx FIFO interrupt if we really need it */
+   if (tx_len > SUN4I_FIFO_DEPTH)
+   sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);

/* Start the transfer */
reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
@@ -287,8 +319,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master,

[linux-sunxi] Re: [PATCH v5] ARM: sun4i: spi: Allow transfers larger than FIFO size

2014-04-01 Thread Maxime Ripard
On Mon, Mar 31, 2014 at 09:16:51PM -0500, Alexandru Gagniuc wrote:
> SPI transfers were limited to one FIFO depth, which is 64 bytes.
> This was an artificial limitation, however, as the hardware can handle
> much larger bursts. To accommodate this, we enable the interrupt when
> the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt
> handler. The 3/4 ratio was chosen arbitrarily, with the intention to
> reduce the potential number of interrupts.
> 
> Since the SUN4I_CTL_TP bit is set, the hardware will pause
> transmission whenever the FIFO is full, so there is no risk of losing
> data if we can't service the interrupt in time.
> 
> For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to
> replenish the FIFO on large SPI bursts. This requires more care in
> when the interrupt is left enabled, as this interrupt will continually
> trigger when the FIFO is less than 1/4 full, even though we
> acknowledge it.
> 
> Signed-off-by: Alexandru Gagniuc 
> Acked-by: Maxime Ripard 

Hmmm, you forgot to Cc Mark Brown. Please resubmit it Ccing whoever
shows up using get_maintainer, otherwise, your patch won't be applied.

You also forgot the changes between this version and the previous one.

Thanks!
Maxime

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[linux-sunxi] Megafeis A08 wiki page.

2014-04-01 Thread Luc Verhaegen
Hi,

I have create the http://linux-sunxi.org/Megafeis_a08 device page and 
have done most of the work for you. Please fill in the blanks still and 
verify the information there.

Thanks.

Luc Verhaegen.

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Re: [linux-sunxi] A31 u-boot with axp221 support now available

2014-04-01 Thread Maxime Ripard
On Tue, Apr 01, 2014 at 01:18:53PM +0200, Hans de Goede wrote:
> Hi,
> 
> On 04/01/2014 12:19 PM, Maxime Ripard wrote:
> > On Tue, Apr 01, 2014 at 01:12:21AM +0200, Hans de Goede wrote:
> >> Hi All,
> >>
> >> Here is a branch of u-boot for the A31 with preliminary axp221
> >> support:
> >>
> >> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221
> >>
> >> Many thanks to Olliver for the initial p2wi and axp221 code, it was
> >> a good starting point. Note still no SPL, this is to be loaded
> >> from boot00 + boot1.
> >>
> >> Advantages over the allwinner generated images u-boot are:
> >> -fdt support
> >> -axp221 code will properly power the gpio's and sdcard at 3.3v, rather
> >> then undervolt them at 3v
> >> -axp221 code will activate ldo1, and thus give power to the phy,
> >> so now we can go and test wens gmac for a31 work
> > 
> > Cool! Thanks a lot for that.
> > 
> > How do you load it usually? From a SD Card? 
> 
> Yes I use your a31-sdcard.img and replace u-boot.bin in the linux dir
> with one built from scratch.

Ok.

> > Have you tried flashing to the NAND?
> 
> No.

Ok. I will then. My MMC slot starts to wear off, so the MMC is not
really an option anymore. I used to use fastboot, but I guess moving
it to the NAND, and use the GMAC then.

> Note I've finished up my sun6i patch series (which includes your initial
> work) to make it ready for pushing to the official u-boot-sunxi git
> repo. So if you're going to play with this, please make sure you've
> the latest code from:
> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221
> 
> (no functional changes, just cleanups / FIXUP patches merging)

Yeah, I saw that. Thanks a lot for your efforts.

Maxime

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Re: [linux-sunxi] Current u-boot crashes my cubietruck!

2014-04-01 Thread Siarhei Siamashka
On Sun, 30 Mar 2014 20:56:57 +0200
Olliver Schinagl  wrote:

> On 03/30/2014 05:59 PM, Ian Campbell wrote:
> > On Sun, 2014-03-30 at 14:26 +0200, Olliver Schinagl wrote:
> >>> That said the sorts of random crashed you've been posting sound a lot
> >>> like either a DRAM issue or overheating. Either of which could be down
> >>> to u-boot setting up something wrong or bad hardware I suppose.
> >> Overheating, maybe. It feels hottish to the touch, but can hold a finger
> >> on it without any problem whatsoever. Not close to the pain point. So I
> >> estimate < 50 C? Shouldn't be reason to be concerned imo.
> >
> > Doesn't sound like it.
> >
> >> Power might be the problem, i see the input voltage under heavy load
> >> drop to 4.65 Volts @ 0.9 amps
> >
> > Could be that.
> >
> >>> Have you checked the checksum of the tarball you are extracting and
> >>> tried unpacking it on a known good system?
> >> The sha1sum matches, calculated on the board, so that's good. xz -d
> >> completed successfully!
> >>
> >> tar xvf fails however, with a big ass 5 page long oops.
> >
> > I'd have thought that xz -d would be *far* more CPU intensive and
> > therefore liable to cause issues than tar xvf. If you were using
> > spinning rust rather than an SSD then I would be inclined to suspect the
> > power draw, but with you using an SSD I'm just not sure.
> 
> I agree! though even a heavily stressed CPU doesn't change power draw 
> hugely. Ssvb and I did some power tests a few months ago on the list.

I'm not sure if I can really agree with this statement. Heavily
stressed CPU can draw a *lot* of power. Especially if it is
overclocked and overvolted:

https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg00906.html

There is also a recent discussion thread in the cubieboard support
mailing list:

https://groups.google.com/forum/#!topic/cubieboard/9WMBFAL7JBE

It looks like the failures reported there are caused by overheating,
when the temperature is gradually increasing under constant CPU load.
And it appears that the cubieboard folks are providing pre-built images
which set the CPU clock speed 1008MHz. This may make a significant
difference.

Too bad that really few people are willing or able to do the current
draw measurements on their hardware. But at the same time, tweaking
the CPU clock speed seems to be somewhat popular. It is not good when
people overclock their CPU and decide that this is 'stable' after
only letting it idle for a while. Then the very same people may
encounter problems later and blame the first random thing that
seems to be 'wrong' in their opinion, for example using the
non-mainline kernel :-)

To make power consumption measurements easier even for inexperienced
users, I tried to hack on the AXP209 voltage/current monitoring support
and sent some preliminary patches:

https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg03447.html

-- 
Best regards,
Siarhei Siamashka

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[linux-sunxi] initlogo.rle file size miss-match error

2014-04-01 Thread Dave McLaughlin
I have followed the instructions on how to create a new initlogo file but 
the size does not match when init tries to use it.

I used the following on a png file that is 800 x 480 and the file size is 
119,306 bytes.

After I run *convert -depth 8 initlogo.png rgb:initlogo.raw* the .raw file 
is 1,152,000 bytes in size. This is close to what the BMP version would be 
and that I assume includes header info. 1,152,054

I then run* rgb2565 -rle < initilogo.raw > initlogo.rle* and the file size 
is now 206,156 bytes

When init creates fbsize for it, it uses 800 x 480 x 4 which is 1,536,6000 
and this does not match the 206,156 and these 2 values show as in boot

init: width = 800
init: height = 480
init: s.st_size = 206156
init: logo match failed!fbsize = 153600

What am I doing wrong that I can't see??

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[linux-sunxi] [PATCH u-boot-sunxi 22/23] ARM: sun6i: Hookup axp221

2014-04-01 Thread Hans de Goede
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/board.c |  9 +++--
 board/sunxi/board.c  | 17 -
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f01d38b..832d22c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -111,13 +111,10 @@ void s_init(void)
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
-
-#ifdef CONFIG_SUN6I
-   printf("sun6i SPL support is not yet complete\n");
-   hang();
-#else
-   sunxi_board_init();
 #endif
+/* No SPL on sun6i, so we do sunxi_board_init() from non spl there */
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUN6I)
+   sunxi_board_init();
 #endif
 }
 
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index ddc66cc..3893d5e 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -18,6 +18,9 @@
 #ifdef CONFIG_AXP209_POWER
 #include 
 #endif
+#ifdef CONFIG_AXP221_POWER
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -74,10 +77,11 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SUN6I)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUN6I)
 void sunxi_board_init(void)
 {
int power_failed = 0;
+#if !defined(CONFIG_SUN6I)
unsigned long ramsize;
 
printf("DRAM:");
@@ -85,6 +89,7 @@ void sunxi_board_init(void)
printf(" %lu MiB\n", ramsize >> 20);
if (!ramsize)
hang();
+#endif
 
 #ifdef CONFIG_AXP152_POWER
power_failed = axp152_init();
@@ -105,7 +110,16 @@ void sunxi_board_init(void)
power_failed |= axp209_set_ldo3(2800);
power_failed |= axp209_set_ldo4(2800);
 #endif
+#ifdef CONFIG_AXP221_POWER
+   power_failed = axp221_init();
+   power_failed |= axp221_set_dcdc1(3300);
+   power_failed |= axp221_set_dcdc2(1200);
+   power_failed |= axp221_set_dcdc3(1260);
+   power_failed |= axp221_set_dcdc4(1200);
+   power_failed |= axp221_set_dcdc5(1500);
+#endif
 
+#if !defined(CONFIG_SUN6I)
/*
 * Only clock up the CPU to full speed if we are reasonably
 * assured it's being powered with suitable core voltage
@@ -118,6 +132,7 @@ void sunxi_board_init(void)
 #endif
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
+#endif
 }
 #endif
 
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 03/23] ARM: sunxi: Setup the A31 UART0 muxing

2014-04-01 Thread Hans de Goede
From: Maxime Ripard 

Signed-off-by: Maxime Ripard 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/board.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 50fcc06..0d954da 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -62,6 +62,10 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+   sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2);
+   sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2);
+   sunxi_gpio_set_pull(SUNXI_GPH(21), 1);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 16/23] ARM: sun6i: Add support for the new power control module found on the A31

2014-04-01 Thread Hans de Goede
From: Oliver Schinagl 

To setup clocks and control voltages.

HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile  |   1 +
 arch/arm/cpu/armv7/sunxi/prcm.c|  37 +
 arch/arm/include/asm/arch-sunxi/prcm.h | 238 +
 3 files changed, 276 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 1cbac1c..4607fa2 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-y += board.o
 obj-y  += clock.o
 obj-y  += pinmux.o
 obj-y  += watchdog.o
+obj-$(CONFIG_SUN6I)+= prcm.o
 obj-$(CONFIG_SUN4I)+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)+= clock_sun4i.o
 obj-$(CONFIG_SUN6I)+= clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644
index 000..8f9bea9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -0,0 +1,37 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl 
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. 
+ * Berg Xing 
+ * Tom Cubie 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void prcm_init_apb0(void)
+{
+   struct sunxi_prcm_reg *prcm =
+   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+   u32 reg_val;
+
+   reg_val = readl(&prcm->apb0_gate);
+   reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+   writel(reg_val, &prcm->apb0_gate);
+
+   reg_val = readl(&prcm->apb0_reset);
+   reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+   writel(reg_val, &prcm->apb0_reset);
+}
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 000..85af1f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,238 @@
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl 
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. 
+ * Berg Xing 
+ * Tom Cubie 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+   __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+   __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+   __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+   __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+   __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+   __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) <<0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+   __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+   __PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __P

[linux-sunxi] [PATCH u-boot-sunxi 13/23] ARM: sun6i: Add initial clock setup for SPL

2014-04-01 Thread Hans de Goede
With this patch and built with SPL,NO_AXP options added, it is possible
to build a non-functional SPL for the A31, which will properly load and
print its banner on the serial console:

U-Boot SPL 2014.04-rc2-01254-g7e81174-dirty (Mar 28 2014 - 21:09:16)
Board: Colombus
sun6i SPL support is not yet complete

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile |  4 +++-
 arch/arm/cpu/armv7/sunxi/board.c  |  5 +
 arch/arm/cpu/armv7/sunxi/clock.c  | 19 ++-
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 18 ++
 board/sunxi/board.c   |  5 ++---
 include/configs/sunxi-common.h|  2 ++
 6 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 3a506f5..724f0ae 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -27,7 +27,9 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
-obj-y  += dram.o
+obj-$(CONFIG_SUN4I)+= dram.o
+obj-$(CONFIG_SUN5I)+= dram.o
+obj-$(CONFIG_SUN7I)+= dram.o
 ifdef CONFIG_SPL_FEL
 obj-y  += start.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 0d954da..f01d38b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -112,8 +112,13 @@ void s_init(void)
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
+#ifdef CONFIG_SUN6I
+   printf("sun6i SPL support is not yet complete\n");
+   hang();
+#else
sunxi_board_init();
 #endif
+#endif
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index a178eea..05b8d27 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -21,6 +21,19 @@ static void clock_init_safe(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
/* Set safe defaults until PMU is configured */
+#if defined(CONFIG_SUN6I)
+   /* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
+   writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+  ATB_DIV_2 << ATB_DIV_SHIFT |
+  CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+  &ccm->cpu_axi_cfg);
+   writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
+   sdelay(200);
+   writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+  ATB_DIV_2 << ATB_DIV_SHIFT |
+  CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+  &ccm->cpu_axi_cfg);
+#else
writel(AXI_DIV_1 << AXI_DIV_SHIFT |
   AHB_DIV_2 << AHB_DIV_SHIFT |
   APB0_DIV_1 << APB0_DIV_SHIFT |
@@ -33,6 +46,7 @@ static void clock_init_safe(void)
   APB0_DIV_1 << APB0_DIV_SHIFT |
   CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
   &ccm->cpu_ahb_apb0_cfg);
+#endif
 #ifdef CONFIG_SUN7I
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
   &ccm->ahb_gate0);
@@ -59,6 +73,9 @@ int clock_init(void)
/* open the clock for uart */
sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
 
+   /* deassert uart reset */
+   sr32((u32 *)SUN6I_ABP2_RESET_BASE, 16 + CONFIG_CONS_INDEX - 1, 1, 1);
+
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 #else
@@ -126,7 +143,7 @@ int clock_twi_onoff(int port, int state)
return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SUN6I)
 #define PLL1_CFG(N, K, M, P)   (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \
 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
 (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 2f20d5d..1d15c4d 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -141,6 +141,23 @@ struct sunxi_ccm_reg {
 #define APB2_FACTOR_M  0
 #define APB2_FACTOR_N  0
 
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT  0
+#define ATB_DIV_SHIFT  8
+#define CPU_CLK_SRC_SHIFT  16
+
+#define AXI_DIV_1  0
+#define AXI_DIV_2  1
+#define AXI_DIV_3  2
+#define AXI_DIV_4  3
+#define ATB_DIV_1  0
+#define ATB_DIV_2  1
+#define ATB_DIV_4  2
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1   2
+
+#define PLL1_CFG_DEFAULT   0x90011b21
+
 #define PLL6_CFG_DEFAULT   0x90041911
 
 #define AHB_GATE_OFFSET_MMC3   11
@@ -155,6 +172,7 @@ struct sunxi_ccm_reg {
 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
 
 #define SUN6I_ABP1_RESET_BASE  0x01c20

[linux-sunxi] [PATCH u-boot-sunxi 02/23] ARM: sunxi: Add basic A31 support

2014-04-01 Thread Hans de Goede
From: Maxime Ripard 

Add a new sun6i machine that doesn't do much for now.

Signed-off-by: Maxime Ripard 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/board.c|  2 +-
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  2 ++
 boards.cfg  |  1 +
 include/configs/sun6i.h | 43 +
 include/configs/sunxi-common.h  |  2 ++
 5 files changed, 49 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/sun6i.h

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 9b3d5a2..50fcc06 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -86,7 +86,7 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c 
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index a388a53..f8a2efd 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -18,6 +18,8 @@ int print_cpuinfo(void)
 #elif defined CONFIG_SUN5I
/* TODO: Distinguish A13/A10s */
puts("CPU:   Allwinner A13/A10s (SUN5I)\n");
+#elif defined CONFIG_SUN6I
+   puts("CPU:   Allwinner A31 (SUN6I)\n");
 #elif defined CONFIG_SUN7I
puts("CPU:   Allwinner A20 (SUN7I)\n");
 #else
diff --git a/boards.cfg b/boards.cfg
index f1a5d07..2beb4bb 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -386,6 +386,7 @@ Active  arm armv7  sunxi   -
   sunxi
 Active  arm armv7  sunxi   -   sunxi   
Coby_MID9742 sun4i:COBY_MID9742,SPL 

   -
 Active  arm armv7  sunxi   -   sunxi   
Iteaduino_Plus_A10   
sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245  
-
 Active  arm armv7  sunxi   -   sunxi   
Iteaduino_Plus_A20   
sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245  
-
+Active  arm armv7  sunxi   -   sunxi   
Colombus sun6i:COLOMBUS 

   -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard   
sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard2  
sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS 
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard2_FEL  
sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS 
  -
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
new file mode 100644
index 000..543b39a
--- /dev/null
+++ b/include/configs/sun6i.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom 
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton 
+ * (C) Copyright 2013 Maxime Ripard 
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+#define CONFIG_SUN6I   /* sun6i SoC generation */
+
+#define CONFIG_SYS_PROMPT  "sun6i# "
+#define CONFIG_MACH_TYPE 

[linux-sunxi] [PATCH u-boot-sunxi 11/23] ARM: sun6i: Fix clock_twi_onoff for sun6i

2014-04-01 Thread Hans de Goede
Note this is something I noticed while working on the clock stuff for the
mmc support. Likely more work is needed to get twi to work on sun6i, this
is just a first step.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 273aa3f..a178eea 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -116,8 +116,12 @@ int clock_twi_onoff(int port, int state)
if (port > 2)
return -1;
 
-   /* set the apb1 clock gate for twi */
+   /* set the apb clock gate for twi */
+#if defined(CONFIG_SUN6I)
+   sr32(&ccm->apb2_gate, 0 + port, 1, state);
+#else
sr32(&ccm->apb1_gate, 0 + port, 1, state);
+#endif
 
return 0;
 }
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 20/23] ARM: sun6i: Add new p2wi controller driver

2014-04-01 Thread Hans de Goede
From: Oliver Schinagl 

The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.

HdG: Various fixes to the code
HdG: Move AXP221 specific bits out of the p2wi code

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile  |   1 +
 arch/arm/cpu/armv7/sunxi/p2wi.c| 120 
 arch/arm/include/asm/arch-sunxi/p2wi.h | 142 +
 3 files changed, 263 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/p2wi.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/p2wi.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 4607fa2..b39ea02 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clock.o
 obj-y  += pinmux.o
 obj-y  += watchdog.o
 obj-$(CONFIG_SUN6I)+= prcm.o
+obj-$(CONFIG_SUN6I)+= p2wi.o
 obj-$(CONFIG_SUN4I)+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)+= clock_sun4i.o
 obj-$(CONFIG_SUN6I)+= clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
new file mode 100644
index 000..343fa0b
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -0,0 +1,120 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl 
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. 
+ * Berg Xing 
+ * Tom Cubie 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void p2wi_init(void)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+   /* Enable p2wi and PIO clk, and de-assert their resets */
+   prcm_init_apb0();
+
+   sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
+   sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+
+   /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+   writel(P2WI_CTRL_RESET, &p2wi->ctrl);
+   sdelay(0x100);
+   writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+  &p2wi->cc);
+}
+
+int p2wi_set_pmu_address(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+   int i;
+
+   writel(P2WI_PM_DEV_ADDR(slave_addr) |
+  P2WI_PM_CTRL_ADDR(ctrl_reg) |
+  P2WI_PM_INIT_DATA(init_data) |
+  P2WI_PM_INIT_SEND,
+  &p2wi->pm);
+   for (i = 0xff; i != 0; i--)
+   if (!(readl(&p2wi->pm) & P2WI_PM_INIT_SEND))
+   break;
+   if (readl(&p2wi->pm) & P2WI_PM_INIT_SEND)
+   return -EFAULT;
+
+   return 0;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+   int i, ret = 0;
+   u8 reg;
+
+   writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+   writel(P2WI_DATA_NUM_BYTES(1) |
+  P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
+   writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+   writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+   for (i = 0xff; i != 0; i--) {
+   reg = readl(&p2wi->status);
+   if (reg & P2WI_STAT_TRANS_ERR) {
+   ret = -EIO;
+   break;
+}
+   if (reg & P2WI_STAT_TRANS_DONE)
+   break;
+}
+
+   if (i == 0)
+   ret = -ETIME;
+
+   *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
+   writel(reg, &p2wi->status); /* Clear status bits */
+   return ret;
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+   int i, ret = 0;
+   u8 reg;
+
+   writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+   writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
+   writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
+   writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+   writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+   for (i = 0xff; i != 0; i--) {
+   reg = readl(&p2wi->status);
+   if (reg & P2WI_STAT_TRANS_ERR) {
+   ret = -EIO;
+   break;
+}
+   if (reg & P2WI_STAT_TRANS_DONE)
+   break;
+}
+
+   if (i == 0)
+   ret = -ETIME;
+
+   writel(reg, &p2wi->status); /* Clear status bits */
+   return ret;
+}
diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h 
b/arch/arm/include/asm/arch-sunxi/p2wi.h
new file mode 100644

[linux-sunxi] [PATCH u-boot-sunxi 05/23] ARM: sun6i: Setup the UART0 clocks

2014-04-01 Thread Hans de Goede
From: Maxime Ripard 

Signed-off-by: Maxime Ripard 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index a344971..c4b19da 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -56,6 +56,15 @@ int clock_init(void)
clock_init_safe();
 #endif
 
+#if defined(CONFIG_SUN6I)
+   /* uart clock source is apb2 */
+   sr32(&ccm->apb2_div, 24, 2, APB2_CLK_SRC_OSC24M);
+   sr32(&ccm->apb2_div, 16, 2, APB2_FACTOR_N);
+   sr32(&ccm->apb2_div, 0, 5, APB2_FACTOR_M);
+
+   /* open the clock for uart */
+   sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
+#else
/* uart clock source is apb1 */
sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
@@ -63,6 +72,7 @@ int clock_init(void)
 
/* open the clock for uart */
sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
+#endif
 
 #ifdef CONFIG_NAND_SUNXI
/* nand clock source is osc24m */
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 14/23] ARM: sunxi: Split clock code into common, sun4i and sun6i code

2014-04-01 Thread Hans de Goede
Rather then having effectively 2 copies of a function through
 #ifdef CONFIG_SUN6I ... #else ... #endif, really make 2 copies of the
function in 2 separate C-files, this is much easier to read and maintain.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile   |   4 +
 arch/arm/cpu/armv7/sunxi/clock.c| 185 +---
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c  | 160 +++
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c  |  73 +
 arch/arm/include/asm/arch-sunxi/clock.h |   2 +
 5 files changed, 240 insertions(+), 184 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun4i.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 724f0ae..1cbac1c 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -12,6 +12,10 @@ obj-y+= board.o
 obj-y  += clock.o
 obj-y  += pinmux.o
 obj-y  += watchdog.o
+obj-$(CONFIG_SUN4I)+= clock_sun4i.o
+obj-$(CONFIG_SUN5I)+= clock_sun4i.o
+obj-$(CONFIG_SUN6I)+= clock_sun6i.o
+obj-$(CONFIG_SUN7I)+= clock_sun4i.o
 ifdef DEBUG
 obj-y  += early_print.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 05b8d27..c07a975 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -14,89 +14,12 @@
 #include 
 #include 
 
-#ifdef CONFIG_SPL_BUILD
-static void clock_init_safe(void)
-{
-   struct sunxi_ccm_reg * const ccm =
-   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-   /* Set safe defaults until PMU is configured */
-#if defined(CONFIG_SUN6I)
-   /* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
-   writel(AXI_DIV_3 << AXI_DIV_SHIFT |
-  ATB_DIV_2 << ATB_DIV_SHIFT |
-  CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
-  &ccm->cpu_axi_cfg);
-   writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
-   sdelay(200);
-   writel(AXI_DIV_3 << AXI_DIV_SHIFT |
-  ATB_DIV_2 << ATB_DIV_SHIFT |
-  CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
-  &ccm->cpu_axi_cfg);
-#else
-   writel(AXI_DIV_1 << AXI_DIV_SHIFT |
-  AHB_DIV_2 << AHB_DIV_SHIFT |
-  APB0_DIV_1 << APB0_DIV_SHIFT |
-  CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
-  &ccm->cpu_ahb_apb0_cfg);
-   writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
-   sdelay(200);
-   writel(AXI_DIV_1 << AXI_DIV_SHIFT |
-  AHB_DIV_2 << AHB_DIV_SHIFT |
-  APB0_DIV_1 << APB0_DIV_SHIFT |
-  CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
-  &ccm->cpu_ahb_apb0_cfg);
-#endif
-#ifdef CONFIG_SUN7I
-   writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
-  &ccm->ahb_gate0);
-#endif
-   writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
-}
-#endif
-
 int clock_init(void)
 {
-   struct sunxi_ccm_reg *const ccm =
-   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
 #ifdef CONFIG_SPL_BUILD
clock_init_safe();
 #endif
-
-#if defined(CONFIG_SUN6I)
-   /* uart clock source is apb2 */
-   sr32(&ccm->apb2_div, 24, 2, APB2_CLK_SRC_OSC24M);
-   sr32(&ccm->apb2_div, 16, 2, APB2_FACTOR_N);
-   sr32(&ccm->apb2_div, 0, 5, APB2_FACTOR_M);
-
-   /* open the clock for uart */
-   sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
-
-   /* deassert uart reset */
-   sr32((u32 *)SUN6I_ABP2_RESET_BASE, 16 + CONFIG_CONS_INDEX - 1, 1, 1);
-
-   /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
-   writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
-#else
-   /* uart clock source is apb1 */
-   sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
-   sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
-   sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
-
-   /* open the clock for uart */
-   sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
-#endif
-
-#ifdef CONFIG_NAND_SUNXI
-   /* nand clock source is osc24m */
-   sr32(&ccm->nand_sclk_cfg, 24, 2, NAND_CLK_SRC_OSC24);
-   sr32(&ccm->nand_sclk_cfg, 16, 2, NAND_CLK_DIV_N);
-   sr32(&ccm->nand_sclk_cfg, 0, 4, NAND_CLK_DIV_M);
-   sr32(&ccm->nand_sclk_cfg, 31, 1, CLK_GATE_OPEN);
-   /* open clock for nand */
-   sr32(&ccm->ahb_gate0, AHB_GATE_OFFSET_NAND, 1, CLK_GATE_OPEN);
-#endif
+   clock_init_uart();
 
return 0;
 }
@@ -124,109 +47,3 @@ unsigned int clock_get_pll6(void)
int k = ((rval >> 4) & 3) + 1;
return 2400 * n * k / 2;
 }
-
-int clock_twi_onoff(int port, int state)
-{
-   struct sunxi_ccm_reg *const ccm =
-   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-   if (port > 2)
-   return -1;
-
-   /* set the apb clock gate for twi */
-#if defined(CONFIG_SUN6I)
-   sr32(&ccm->apb2_gate, 0 + port, 1

[linux-sunxi] [PATCH u-boot-sunxi 12/23] ARM: sun6i: sun6i can have upto 2G RAM

2014-04-01 Thread Hans de Goede
Signed-off-by: Hans de Goede 
---
 include/configs/sunxi-common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 212b621..09edc71 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -57,7 +57,7 @@
 /* A10 has 1 banks of DRAM, we use only bank 1 in U-Boot */
 #define CONFIG_NR_DRAM_BANKS   1
 #define PHYS_SDRAM_0   CONFIG_SYS_SDRAM_BASE
-#ifdef CONFIG_SUN7I
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I)
 #define PHYS_SDRAM_0_SIZE  0x8000 /* 2 GiB */
 #else
 #define PHYS_SDRAM_0_SIZE  0x4000 /* 1 GiB */
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 19/23] ARM: sun6i: Define P2WI GPIO pins

2014-04-01 Thread Hans de Goede
From: Oliver Schinagl 

P2WI needs 2 pins configured from the GPIO pins. This adds defines to be
used for that.

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 00326a4..8de6bc1 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -152,6 +152,9 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_PULL_UP 1
 #define SUNXI_GPIO_PULL_DOWN   2
 
+#define SUNXI_GPL0_R_P2WI_SCK  3
+#define SUNXI_GPL1_R_P2WI_SDA  3
+
 int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 09/23] ARM: sunxi-mmc: Simplify data_buf1_sz calculations

2014-04-01 Thread Hans de Goede
Since SDXC_DES_BUFFER_MAX_LEN is always a power of 2,
"(SDXC_DES_BUFFER_MAX_LEN - 1) & SDXC_DES_BUFFER_MAX_LEN" is just a really
complicated way of writing 0.

Since writing 0 to data_buf1_sz means transfer SDXC_DES_BUFFER_MAX_LEN bytes,
there is no need to set remain to SDXC_DES_BUFFER_MAX_LEN when it is 0.

Signed-off-by: Hans de Goede 
---
 drivers/mmc/sunxi_mmc.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 3adb151..4573621 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -359,8 +359,6 @@ static int mmc_trans_data_by_dma(struct mmc *mmc, struct 
mmc_data *data)
buff = data->flags & MMC_DATA_READ ?
(unsigned char *)data->dest : (unsigned char *)data->src;
remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
-   if (!remain)
-   remain = SDXC_DES_BUFFER_MAX_LEN;
 
flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
for (i = 0; i < buff_frag_num; i++, des_idx++) {
@@ -369,9 +367,7 @@ static int mmc_trans_data_by_dma(struct mmc *mmc, struct 
mmc_data *data)
pdes[des_idx].own = 1;
pdes[des_idx].dic = 1;
if (buff_frag_num > 1 && i != buff_frag_num - 1)
-   pdes[des_idx].data_buf1_sz =
-   (SDXC_DES_BUFFER_MAX_LEN -
-1) & SDXC_DES_BUFFER_MAX_LEN;
+   pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */
else
pdes[des_idx].data_buf1_sz = remain;
 
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 10/23] ARM: sunxi-mmc: Add mmc support for sun6i / A31

2014-04-01 Thread Hans de Goede
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock.c  |  3 +++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 21 +
 drivers/mmc/sunxi_mmc.c   |  9 -
 include/configs/sunxi-common.h|  2 --
 4 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index e3c8fef..273aa3f 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -58,6 +58,9 @@ int clock_init(void)
 
/* open the clock for uart */
sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
+
+   /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+   writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 #else
/* uart clock source is apb1 */
sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 147e6c9..2f20d5d 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -141,4 +141,25 @@ struct sunxi_ccm_reg {
 #define APB2_FACTOR_M  0
 #define APB2_FACTOR_N  0
 
+#define PLL6_CFG_DEFAULT   0x90041911
+
+#define AHB_GATE_OFFSET_MMC3   11
+#define AHB_GATE_OFFSET_MMC2   10
+#define AHB_GATE_OFFSET_MMC1   9
+#define AHB_GATE_OFFSET_MMC0   8
+#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6   (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define SUN6I_ABP1_RESET_BASE  0x01c202c0
+
+#define ABP1_RESET_OFFSET_MMC3 11
+#define ABP1_RESET_OFFSET_MMC2 10
+#define ABP1_RESET_OFFSET_MMC1 9
+#define ABP1_RESET_OFFSET_MMC0 8
+#define ABP1_RESET_OFFSET_MMC(n)   (ABP1_RESET_OFFSET_MMC0 + (n))
+
 #endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4573621..4cb5dc7 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -77,7 +77,7 @@ struct sunxi_mmc_des {
u32 data_buf1_sz:13;
u32 data_buf2_sz:13;
u32 reserverd2_1:6;
-#elif defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#elif defined(CONFIG_SUN5I) || defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I)
 #define SDXC_DES_NUM_SHIFT 16
 #define SDXC_DES_BUFFER_MAX_LEN(1 << SDXC_DES_NUM_SHIFT)
u32 data_buf1_sz:16;
@@ -203,6 +203,13 @@ static int mmc_clk_io_on(int sdc_no)
rval |= 1 << AHB_GATE_OFFSET_MMC(sdc_no);
writel(rval, &ccm->ahb_gate0);
 
+#if defined(CONFIG_SUN6I)
+   /* unassert reset */
+   rval = readl(SUN6I_ABP1_RESET_BASE);
+   rval |= 1 << ABP1_RESET_OFFSET_MMC(sdc_no);
+   writel(rval, SUN6I_ABP1_RESET_BASE);
+#endif
+
/* config mod clock */
pll_clk = clock_get_pll6();
/* should be close to 100 MHz but no more, so round up */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index dd7c668..212b621 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -81,7 +81,6 @@
 
 /* mmc config */
 /* Can't use MMC slot 0 if the UART is directed there */
-#ifndef CONFIG_SUN6I
 #if !defined CONFIG_UART0_PORT_F || CONFIG_MMC_SUNXI_SLOT != 0
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -94,7 +93,6 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0   /* first detected MMC 
controller */
 #endif
-#endif
 
 /* 4MB of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (4 << 20))
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 17/23] ARM: sun6i: Properly setup the PLL LDO in clock_init_safe

2014-04-01 Thread Hans de Goede
This fixes me being unable to use PLL6 as clock-source for the mmc controller.
Unfortunately the DRAM controller situation is a mess. Someone will need
to put a lot of time into getting DRAM going before we can do SPL on sun6i.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index e44a460..c8886b9 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #ifdef CONFIG_SPL_BUILD
@@ -21,6 +22,19 @@ void clock_init_safe(void)
 {
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+   struct sunxi_prcm_reg * const prcm =
+   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+   /* Set PLL ldo voltage without this PLL6 does not work properly */
+   writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+   PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
+   PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
+   writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+   PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
+   PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
+   writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+   PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
+   &prcm->pll_ctrl1);
 
/* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
writel(AXI_DIV_3 << AXI_DIV_SHIFT |
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 01/23] ARM: sunxi: Compile DRAM related code only when building SPL

2014-04-01 Thread Hans de Goede
From: Maxime Ripard 

The code of DRAM initialization is only of interest when building the SPL. Move
it to the CONFIG_SPL-only list of files to build.

Signed-off-by: Maxime Ripard 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 83b7c1a..3a506f5 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -8,7 +8,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 obj-y  += timer.o
-obj-y  += dram.o
 obj-y  += board.o
 obj-y  += clock.o
 obj-y  += pinmux.o
@@ -28,6 +27,7 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
+obj-y  += dram.o
 ifdef CONFIG_SPL_FEL
 obj-y  += start.o
 endif
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 15/23] ARM: sun6i: Add base address for the new controllers in A31

2014-04-01 Thread Hans de Goede
From: Oliver Schinagl 

A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 arch/arm/include/asm/arch-sunxi/cpu.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
b/arch/arm/include/asm/arch-sunxi/cpu.h
index f0a8c48..c14cf8e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -95,6 +95,11 @@
 #define SUNXI_MALI400_BASE 0x01c4
 #define SUNXI_GMAC_BASE0x01c5
 
+#define SUNXI_DRAM_COM_BASE0x01c62000
+#define SUNXI_DRAM_CTL_BASE0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE0x01c66000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE  0x01d0
 
@@ -105,6 +110,10 @@
 #define SUNXI_MP_BASE  0x01e8
 #define SUNXI_AVG_BASE 0x01ea
 
+#define SUNXI_PRCM_BASE0x01f01400
+#define SUNXI_R_PIO_BASE   0x01f02c00
+#define SUNXI_P2WI_BASE0x01f03400
+
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE0x3f50
 
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 07/23] ARM: sunxi-mmc: Make mmc mod clk div pll clk freq independent

2014-04-01 Thread Hans de Goede
Change how we calculate the mod clk div so that it will work for a pll clk
of 600 or 1200 too.

Signed-off-by: Hans de Goede 
---
 drivers/mmc/sunxi_mmc.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index cf065f4..1c71bfc 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -140,7 +140,7 @@ static int mmc_clk_io_on(int sdc_no)
 {
unsigned int pin;
unsigned int rval;
-   unsigned int pll5_clk;
+   unsigned int pll_clk;
unsigned int divider;
struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
@@ -204,14 +204,12 @@ static int mmc_clk_io_on(int sdc_no)
writel(rval, &ccm->ahb_gate0);
 
/* config mod clock */
-   pll5_clk = clock_get_pll5();
-   if (pll5_clk > 4)
-   divider = 4;
-   else
-   divider = 3;
+   pll_clk = clock_get_pll5();
+   /* should be close to 100 MHz but no more, so round up */
+   divider = ((pll_clk + ) / 1) - 1;
writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL5 | divider,
   mmchost->mclkreg);
-   mmchost->mod_clk = pll5_clk / (divider + 1);
+   mmchost->mod_clk = pll_clk / (divider + 1);
 
dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100);
dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100);
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 21/23] ARM: sun6i: Add basic axp221 driver

2014-04-01 Thread Hans de Goede
From: Oliver Schinagl 

The A31 uses the AXP221 pmic for various voltages.

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 boards.cfg |  2 +-
 drivers/power/Makefile |  1 +
 drivers/power/axp221.c | 56 ++
 include/axp221.h   | 25 +++
 include/configs/sunxi-common.h |  4 +--
 5 files changed, 85 insertions(+), 3 deletions(-)
 create mode 100644 drivers/power/axp221.c
 create mode 100644 include/axp221.h

diff --git a/boards.cfg b/boards.cfg
index 2beb4bb..b0335de 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -386,7 +386,7 @@ Active  arm armv7  sunxi   -
   sunxi
 Active  arm armv7  sunxi   -   sunxi   
Coby_MID9742 sun4i:COBY_MID9742,SPL 

   -
 Active  arm armv7  sunxi   -   sunxi   
Iteaduino_Plus_A10   
sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245  
-
 Active  arm armv7  sunxi   -   sunxi   
Iteaduino_Plus_A20   
sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245  
-
-Active  arm armv7  sunxi   -   sunxi   
Colombus sun6i:COLOMBUS 

   -
+Active  arm armv7  sunxi   -   sunxi   
Colombus sun6i:COLOMBUS,AXP221_POWER

   -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard   
sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard2  
sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS 
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard2_FEL  
sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS 
  -
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index dc64e4d..04bd996 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_AXP152_POWER) += axp152.o
 obj-$(CONFIG_AXP209_POWER) += axp209.o
+obj-$(CONFIG_AXP221_POWER) += axp221.o
 obj-$(CONFIG_EXYNOS_TMU)   += exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)   += ftpmu010.o
 obj-$(CONFIG_TPS6586X_POWER)   += tps6586x.o
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
new file mode 100644
index 000..a17b8a8
--- /dev/null
+++ b/drivers/power/axp221.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2013 Oliver Schinagl 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int axp221_set_dcdc1(unsigned int mvolt)
+{
+   return p2wi_write(AXP221_DCDC1_CTRL, (mvolt - 1600) / 100);
+}
+
+int axp221_set_dcdc2(unsigned int mvolt)
+{
+   return p2wi_write(AXP221_DCDC2_CTRL, (mvolt - 600) / 20);
+}
+
+int axp221_set_dcdc3(unsigned int mvolt)
+{
+   return p2wi_write(AXP221_DCDC3_CTRL, (mvolt - 600) / 20);
+}
+
+int axp221_set_dcdc4(unsigned int mvolt)
+{
+   return p2wi_write(AXP221_DCDC4_CTRL, (mvolt - 600) / 20);
+}
+
+int axp221_set_dcdc5(unsigned int mvolt)
+{
+   return p2wi_write(AXP221_DCDC5_CTRL, (mvolt - 600) / 20);
+}
+
+int axp221_init(void)
+{
+   u8 axp_chip_id;
+   int ret;
+
+   p2wi_init();
+   ret = p2wi_set_pmu_address(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
+  AXP221_INIT_DATA);
+   if (ret)
+   return ret;
+
+   ret = p2wi_read(AXP221_CHIP_ID, &axp_chip_id);
+   if (ret)
+   return ret;
+
+   if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
+   return -ENODEV;
+
+   return 0;
+}
diff --git a/include/axp221.h b/include/axp221.h
new file mode 100644
index 000..497134c
--- /dev/null
+++ b/include/axp221.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013 Oliver Schinagl 
+ *
+ * X-Powers AXP221 Power Management IC driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#define AXP221_CHIP_ADDR 0x68
+#define AXP221_CTRL_ADDR 0x3e
+#define AXP221_INIT_DATA 0x3e
+
+

[linux-sunxi] [PATCH u-boot-sunxi 04/23] ARM: sunxi: Add sun6i clock controller structure

2014-04-01 Thread Hans de Goede
From: Maxime Ripard 

The A31 has a new clock controller of its own. Add the structure representing
this controller register layout.

HdG: Move sun4i ccm register definitions to clock-sun4i.h and put the new
sun6i ccm register definitions in clock-sun6i.h

Signed-off-by: Maxime Ripard 
Signed-off-by: Hans de Goede 
---
 arch/arm/include/asm/arch-sunxi/clock.h   | 227 +
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 233 ++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 144 
 3 files changed, 383 insertions(+), 221 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun4i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock.h 
b/arch/arm/include/asm/arch-sunxi/clock.h
index ef03d5b..d701e20 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -11,230 +11,15 @@
 
 #include 
 
-/* clock control module regs definition */
-
-struct sunxi_ccm_reg {
-   u32 pll1_cfg;   /* 0x00 pll1 control */
-   u32 pll1_tun;   /* 0x04 pll1 tuning */
-   u32 pll2_cfg;   /* 0x08 pll2 control */
-   u32 pll2_tun;   /* 0x0c pll2 tuning */
-   u32 pll3_cfg;   /* 0x10 pll3 control */
-   u8 res0[0x4];
-   u32 pll4_cfg;   /* 0x18 pll4 control */
-   u8 res1[0x4];
-   u32 pll5_cfg;   /* 0x20 pll5 control */
-   u32 pll5_tun;   /* 0x24 pll5 tuning */
-   u32 pll6_cfg;   /* 0x28 pll6 control */
-   u32 pll6_tun;   /* 0x2c pll6 tuning */
-   u32 pll7_cfg;   /* 0x30 pll7 control */
-   u32 pll1_tun2;  /* 0x34 pll5 tuning2 */
-   u8 res2[0x4];
-   u32 pll5_tun2;  /* 0x3c pll5 tuning2 */
-   u8 res3[0xc];
-   u32 pll_lock_dbg;   /* 0x4c pll lock time debug */
-   u32 osc24m_cfg; /* 0x50 osc24m control */
-   u32 cpu_ahb_apb0_cfg;   /* 0x54 cpu,ahb and apb0 divide ratio */
-   u32 apb1_clk_div_cfg;   /* 0x58 apb1 clock dividor */
-   u32 axi_gate;   /* 0x5c axi module clock gating */
-   u32 ahb_gate0;  /* 0x60 ahb module clock gating 0 */
-   u32 ahb_gate1;  /* 0x64 ahb module clock gating 1 */
-   u32 apb0_gate;  /* 0x68 apb0 module clock gating */
-   u32 apb1_gate;  /* 0x6c apb1 module clock gating */
-   u8 res4[0x10];
-   u32 nand_sclk_cfg;  /* 0x80 nand sub clock control */
-   u32 ms_sclk_cfg;/* 0x84 memory stick sub clock control */
-   u32 sd0_clk_cfg;/* 0x88 sd0 clock control */
-   u32 sd1_clk_cfg;/* 0x8c sd1 clock control */
-   u32 sd2_clk_cfg;/* 0x90 sd2 clock control */
-   u32 sd3_clk_cfg;/* 0x94 sd3 clock control */
-   u32 ts_clk_cfg; /* 0x98 transport stream clock control */
-   u32 ss_clk_cfg; /* 0x9c */
-   u32 spi0_clk_cfg;   /* 0xa0 */
-   u32 spi1_clk_cfg;   /* 0xa4 */
-   u32 spi2_clk_cfg;   /* 0xa8 */
-   u32 pata_clk_cfg;   /* 0xac */
-   u32 ir0_clk_cfg;/* 0xb0 */
-   u32 ir1_clk_cfg;/* 0xb4 */
-   u32 iis_clk_cfg;/* 0xb8 */
-   u32 ac97_clk_cfg;   /* 0xbc */
-   u32 spdif_clk_cfg;  /* 0xc0 */
-   u32 keypad_clk_cfg; /* 0xc4 */
-   u32 sata_clk_cfg;   /* 0xc8 */
-   u32 usb_clk_cfg;/* 0xcc */
-   u32 gps_clk_cfg;/* 0xd0 */
-   u32 spi3_clk_cfg;   /* 0xd4 */
-   u8 res5[0x28];
-   u32 dram_clk_cfg;   /* 0x100 */
-   u32 be0_clk_cfg;/* 0x104 */
-   u32 be1_clk_cfg;/* 0x108 */
-   u32 fe0_clk_cfg;/* 0x10c */
-   u32 fe1_clk_cfg;/* 0x110 */
-   u32 mp_clk_cfg; /* 0x114 */
-   u32 lcd0_ch0_clk_cfg;   /* 0x118 */
-   u32 lcd1_ch0_clk_cfg;   /* 0x11c */
-   u32 csi_isp_clk_cfg;/* 0x120 */
-   u8 res6[0x4];
-   u32 tvd_clk_reg;/* 0x128 */
-   u32 lcd0_ch1_clk_cfg;   /* 0x12c */
-   u32 lcd1_ch1_clk_cfg;   /* 0x130 */
-   u32 csi0_clk_cfg;   /* 0x134 */
-   u32 csi1_clk_cfg;   /* 0x138 */
-   u32 ve_clk_cfg; /* 0x13c */
-   u32 audio_codec_clk_cfg;/* 0x140 */
-   u32 avs_clk_cfg;/* 0x144 */
-   u32 ace_clk_cfg;/* 0x148 */
-   u32 lvds_clk_cfg;   /* 0x14c */
-   u32 hdmi_clk_cfg;   /* 0x150 */
-   u32 mali_clk_cfg;   /* 0x154 */
-   u8 res7[0x4];
-   u32 mbus_clk_cfg;   /* 0x15c */
-   u8 res8[0x4];
-   u32 gmac_clk_cfg;   /* 0x164 */
-};
-
-/* apb1 bit field */
-#define APB1_CLK_SRC_OSC24M0
-#define APB1_FACTOR_M  0
-#define APB1_FACTOR_N  0
-
-/* clock divide */
-#define AXI_DIV_SHIFT  (0)
-#define AXI_DIV_1  0
-#define AXI_DIV_2  

[linux-sunxi] [PATCH u-boot-sunxi 23/23] ARM: sun6i: Enable dldo1 by default

2014-04-01 Thread Hans de Goede
This is used by the ethernet-phy on various boards.

Signed-off-by: Hans de Goede 
---
 board/sunxi/board.c|  3 +++
 boards.cfg |  2 +-
 drivers/power/axp221.c | 17 +
 include/axp221.h   |  5 +
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3893d5e..386b03e 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -117,6 +117,9 @@ void sunxi_board_init(void)
power_failed |= axp221_set_dcdc3(1260);
power_failed |= axp221_set_dcdc4(1200);
power_failed |= axp221_set_dcdc5(1500);
+#ifdef CONFIG_ENABLE_DLDO1_POWER
+   power_failed |= axp221_set_dldo1(3300);
+#endif
 #endif
 
 #if !defined(CONFIG_SUN6I)
diff --git a/boards.cfg b/boards.cfg
index b0335de..c50acaa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -386,7 +386,7 @@ Active  arm armv7  sunxi   -
   sunxi
 Active  arm armv7  sunxi   -   sunxi   
Coby_MID9742 sun4i:COBY_MID9742,SPL 

   -
 Active  arm armv7  sunxi   -   sunxi   
Iteaduino_Plus_A10   
sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245  
-
 Active  arm armv7  sunxi   -   sunxi   
Iteaduino_Plus_A20   
sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245  
-
-Active  arm armv7  sunxi   -   sunxi   
Colombus sun6i:COLOMBUS,AXP221_POWER

   -
+Active  arm armv7  sunxi   -   sunxi   
Colombus 
sun6i:COLOMBUS,AXP221_POWER,ENABLE_DLDO1_POWER  
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard   
sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard2  
sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS 
  -
 Active  arm armv7  sunxi   -   sunxi   
Cubieboard2_FEL  
sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS 
  -
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index a17b8a8..6ce6a1b 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -34,6 +34,23 @@ int axp221_set_dcdc5(unsigned int mvolt)
return p2wi_write(AXP221_DCDC5_CTRL, (mvolt - 600) / 20);
 }
 
+int axp221_set_dldo1(unsigned int mvolt)
+{
+   int ret;
+   u8 val;
+
+   ret = p2wi_write(AXP221_DLDO1_CTRL, (mvolt - 700) / 100);
+   if (ret)
+   return ret;
+
+   ret = p2wi_read(AXP221_OUTPUT_CTRL2, &val);
+   if (ret)
+   return ret;
+
+   val |= 1 << 3;
+   return p2wi_write(AXP221_OUTPUT_CTRL2, val);
+}
+
 int axp221_init(void)
 {
u8 axp_chip_id;
diff --git a/include/axp221.h b/include/axp221.h
index 497134c..c3a6cf4 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -11,6 +11,10 @@
 #define AXP221_INIT_DATA 0x3e
 
 #define AXP221_CHIP_ID 0x03
+#define AXP221_OUTPUT_CTRL10x10
+#define AXP221_OUTPUT_CTRL20x12
+#define AXP221_OUTPUT_CTRL30x13
+#define AXP221_DLDO1_CTRL  0x15
 #define AXP221_DCDC1_CTRL  0x21
 #define AXP221_DCDC2_CTRL  0x22
 #define AXP221_DCDC3_CTRL  0x23
@@ -22,4 +26,5 @@ int axp221_set_dcdc2(unsigned int mvolt);
 int axp221_set_dcdc3(unsigned int mvolt);
 int axp221_set_dcdc4(unsigned int mvolt);
 int axp221_set_dcdc5(unsigned int mvolt);
+int axp221_set_dldo1(unsigned int mvolt);
 int axp221_init(void);
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 06/23] ARM: sunxi: Enable pll6 by default on all models

2014-04-01 Thread Hans de Goede
So that we can use it as a clocksource for modules, ie for mmc. This
allows discoupling the actual mmc clock rate we get from the ram speed,
and will lead to getting exact clockspeeds for mmc rather then something
approximately right.

As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.

This has been tested on sun4i, sun5i and sun7i.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock.c  | 18 +++---
 arch/arm/include/asm/arch-sunxi/clock.h   |  1 +
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |  7 +--
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index c4b19da..e3c8fef 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -33,17 +33,11 @@ static void clock_init_safe(void)
   APB0_DIV_1 << APB0_DIV_SHIFT |
   CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
   &ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN5I
-   /* Power on reset default for PLL6 is 2400 MHz, which is faster then
-* it can reliable do :|  Set it to a 600 MHz instead. */
-   writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
-#endif
 #ifdef CONFIG_SUN7I
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
   &ccm->ahb_gate0);
-   writel(0x1 << PLL6_ENABLE_OFFSET | readl(&ccm->pll6_cfg),
-  &ccm->pll6_cfg);
 #endif
+   writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 }
 #endif
 
@@ -101,6 +95,16 @@ unsigned int clock_get_pll5(void)
return 2400 * n * k / p;
 }
 
+unsigned int clock_get_pll6(void)
+{
+   struct sunxi_ccm_reg *const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+   uint32_t rval = readl(&ccm->pll6_cfg);
+   int n = (rval >> 8) & 0x1f;
+   int k = ((rval >> 4) & 3) + 1;
+   return 2400 * n * k / 2;
+}
+
 int clock_twi_onoff(int port, int state)
 {
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h 
b/arch/arm/include/asm/arch-sunxi/clock.h
index d701e20..26b30bf 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -26,6 +26,7 @@ int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_pll1(int hz);
 unsigned int clock_get_pll5(void);
+unsigned int clock_get_pll6(void);
 #endif
 
 #endif /* _SUNXI_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 68105d7..a85d541 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -117,12 +117,7 @@ struct sunxi_ccm_reg {
 
 #define PLL1_CFG_DEFAULT   0xa1005000
 
-#ifdef CONFIG_SUN5I
-#define PLL6_CFG_DEFAULT   0x21009911
-#endif
-#ifdef CONFIG_SUN7I
-#define PLL6_ENABLE_OFFSET 31
-#endif
+#define PLL6_CFG_DEFAULT   0xa1009911
 
 #ifdef CONFIG_SUN5I
 #define AHB_CLK_SRC_AXI0
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 08/23] ARM: sunxi-mmc: Use pll6 as clock source

2014-04-01 Thread Hans de Goede
This discouples the actual mmc clock rate we get from the ram speed,
which leads to getting exact clockspeeds for mmc rather then something
approximately right.

As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.

This has been tested on sun4i, sun5i and sun7i.

Signed-off-by: Hans de Goede 
---
 drivers/mmc/sunxi_mmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1c71bfc..3adb151 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -204,10 +204,10 @@ static int mmc_clk_io_on(int sdc_no)
writel(rval, &ccm->ahb_gate0);
 
/* config mod clock */
-   pll_clk = clock_get_pll5();
+   pll_clk = clock_get_pll6();
/* should be close to 100 MHz but no more, so round up */
divider = ((pll_clk + ) / 1) - 1;
-   writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL5 | divider,
+   writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
   mmchost->mclkreg);
mmchost->mod_clk = pll_clk / (divider + 1);
 
-- 
1.9.0

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[linux-sunxi] [PATCH u-boot-sunxi 18/23] ARM: sun6i: Add support for gpio bank L

2014-04-01 Thread Hans de Goede
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/pinmux.c  | 12 
 arch/arm/include/asm/arch-sunxi/gpio.h | 19 ++-
 drivers/gpio/sunxi_gpio.c  |  6 ++
 3 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c 
b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 832545f..3fdd337 100644
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -15,8 +15,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_CFG_INDEX(pin);
u32 offset = GPIO_CFG_OFFSET(pin);
-   struct sunxi_gpio *pio =
-   &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+   struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
 
@@ -29,8 +28,7 @@ int sunxi_gpio_get_cfgpin(u32 pin)
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_CFG_INDEX(pin);
u32 offset = GPIO_CFG_OFFSET(pin);
-   struct sunxi_gpio *pio =
-   &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+   struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
cfg = readl(&pio->cfg[0] + index);
cfg >>= offset;
@@ -43,8 +41,7 @@ int sunxi_gpio_set_drv(u32 pin, u32 val)
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_DRV_INDEX(pin);
u32 offset = GPIO_DRV_OFFSET(pin);
-   struct sunxi_gpio *pio =
-   &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+   struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val);
 
@@ -56,8 +53,7 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_PULL_INDEX(pin);
u32 offset = GPIO_PULL_OFFSET(pin);
-   struct sunxi_gpio *pio =
-   &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+   struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, offset);
 
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index c368adb..00326a4 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -10,6 +10,7 @@
 #define _SUNXI_GPIO_H
 
 #include 
+#include 
 
 /*
  * sunxi has 9 banks of gpio, they are:
@@ -27,6 +28,15 @@
 #define SUNXI_GPIO_G   6
 #define SUNXI_GPIO_H   7
 #define SUNXI_GPIO_I   8
+#define SUNXI_GPIO_BANKS 9
+
+/*
+ * sun6i has atleast 1 additional bank, note banks J K don't exist!
+ * PL0 - PL1 at the very least is known.
+ *
+ * Note this bank is at a different register offset!
+ */
+#define SUNXI_GPIO_L   9
 
 struct sunxi_gpio {
u32 cfg[4];
@@ -44,11 +54,15 @@ struct sunxi_gpio_int {
 };
 
 struct sunxi_gpio_reg {
-   struct sunxi_gpio gpio_bank[9];
+   struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
u8 res[0xbc];
struct sunxi_gpio_int gpio_int;
 };
 
+#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \
+   &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+   (struct sunxi_gpio *)SUNXI_R_PIO_BASE)
+
 #define GPIO_BANK(pin) ((pin) >> 5)
 #define GPIO_NUM(pin)  ((pin) & 0x1f)
 
@@ -71,6 +85,7 @@ struct sunxi_gpio_reg {
 #define SUNXI_GPIO_G_NR32
 #define SUNXI_GPIO_H_NR32
 #define SUNXI_GPIO_I_NR32
+#define SUNXI_GPIO_L_NR32
 
 #define SUNXI_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + 0)
@@ -85,6 +100,7 @@ enum sunxi_gpio_number {
SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+   SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),
 };
 
 /* SUNXI GPIO number definitions */
@@ -97,6 +113,7 @@ enum sunxi_gpio_number {
 #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
 #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
 
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT   0
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 5434da1..0c50a8f 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -19,8 +19,7 @@ static int sunxi_gpio_output(u32 pin, u32 val)
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
-   struct sunxi_gpio *pio =
-   &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+   struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
dat = readl(&pio->dat);
if (val)
@@ -38,8 +37,7 @@ static int sunxi_gpio_input(u32 pin)
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
-   struct sunxi_gpio *pio =
-   &((struct sunxi_gpio_reg *

[linux-sunxi] [PATCH u-boot-sunxi 00/23] Add sun6i / A31 support (no SPL)

2014-04-01 Thread Hans de Goede
Hi All,

This patch series adds basic support for sun6i. There are some bits there
to get SPL support going (clock setup, axp related code has been tested in SPL
mode too), but DRAM setup is missing, so no SPL support.

This series will give you a u-boot.bin binary which can be used to generate
the u-boot.bin on an sdcard image generated by the allwinner tools.

This u-boot.bin supports reading from mmc, has proper fdt support, and
properly sets up all the power supply voltages on the axp221:
-properly power the gpio's and sdcard at 3.3v, rather then undervolt them at 3v
-activate ldo1, and thus give power to the phy, so now we can go and test wens
 gmac for a31 work

If there are no objections I plan to push this series to the u-boot-sunxi repo
sunxi branch in a couple of days. In the mean time you can find it here:
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221

Regards,

Hans

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Re: [linux-sunxi] A31 u-boot with axp221 support now available

2014-04-01 Thread Hans de Goede
Hi,

On 04/01/2014 12:19 PM, Maxime Ripard wrote:
> On Tue, Apr 01, 2014 at 01:12:21AM +0200, Hans de Goede wrote:
>> Hi All,
>>
>> Here is a branch of u-boot for the A31 with preliminary axp221
>> support:
>>
>> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221
>>
>> Many thanks to Olliver for the initial p2wi and axp221 code, it was
>> a good starting point. Note still no SPL, this is to be loaded
>> from boot00 + boot1.
>>
>> Advantages over the allwinner generated images u-boot are:
>> -fdt support
>> -axp221 code will properly power the gpio's and sdcard at 3.3v, rather
>> then undervolt them at 3v
>> -axp221 code will activate ldo1, and thus give power to the phy,
>> so now we can go and test wens gmac for a31 work
> 
> Cool! Thanks a lot for that.
> 
> How do you load it usually? From a SD Card? 

Yes I use your a31-sdcard.img and replace u-boot.bin in the linux dir
with one built from scratch.

> Have you tried flashing to the NAND?

No.

Note I've finished up my sun6i patch series (which includes your initial
work) to make it ready for pushing to the official u-boot-sunxi git
repo. So if you're going to play with this, please make sure you've
the latest code from:
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221

(no functional changes, just cleanups / FIXUP patches merging)

Regards,

Hans

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Re: [linux-sunxi] A31 u-boot with axp221 support now available

2014-04-01 Thread Maxime Ripard
On Tue, Apr 01, 2014 at 01:12:21AM +0200, Hans de Goede wrote:
> Hi All,
> 
> Here is a branch of u-boot for the A31 with preliminary axp221
> support:
> 
> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221
> 
> Many thanks to Olliver for the initial p2wi and axp221 code, it was
> a good starting point. Note still no SPL, this is to be loaded
> from boot00 + boot1.
> 
> Advantages over the allwinner generated images u-boot are:
> -fdt support
> -axp221 code will properly power the gpio's and sdcard at 3.3v, rather
> then undervolt them at 3v
> -axp221 code will activate ldo1, and thus give power to the phy,
> so now we can go and test wens gmac for a31 work

Cool! Thanks a lot for that.

How do you load it usually? From a SD Card? Have you tried flashing to
the NAND?

Maxime

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[linux-sunxi] Re: control USB Power from linux

2014-04-01 Thread Vincenzo Li Vigni
OK. It did work in this (ugly) way:

USB1 USB2
ON ON ./devmem2 0x1c2090c w 0x180078
ON OFF ./devmem2 0x1c2090c w 0x180038
OFF ON  ./devmem2 0x1c2090c w 0x180070
OFF OFF  ./devmem2 0x1c2090c w 0x180030

USB1 is (for me) the upper usb port. 0x1c2090c is the memory address of 
Port H Data register and the last argument is the word to write in that 
register. You can get devmem2 (direct access to memory using /dev/mem) on 
the web or attached here (binary compiled for A10 here: 
https://dl.dropboxusercontent.com/u/848639/keep/devmem2).
NOTE that this works on the Cubieboard (A10) only, since it provides an 
electronic switch on both usb ports. Maybe you can use a similar approach 
on other boards with similar switches on board.
Hope it helps,

Vincenzo

Il giorno martedì 24 settembre 2013 08:01:25 UTC+2, mahdi taheri ha scritto:
>
>
> 
>
>
> On Monday, September 23, 2013 10:59:34 PM UTC-7, stu@gmail.com wrote:
>>
>> I want to control the power off my Usb Device conected to cubieboard 
>> (power off - power on the device  by usb1-drv or usb2-drv  )
>>
>> I googled a lot and find this article 
>> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/270060.aspx
>> but it is not for cubie can anybody help me for this issue?
>>
>> according to attached image it must be a way to control USB1-DRV from 
>> Linux.
>> I have checked the usb power at startup and i see the power goes on when 
>> in terminal  report [sw-ehci1]: Set USB Power ON , but i dont know how it 
>> works.
>>
>> <6>hub 2-0:1.0: USB hub found
>> [1.894384] hub 2-0:1.0: USB hub found
>> <6>hub 2-0:1.0: 1 port detected
>> [1.901073] hub 2-0:1.0: 1 port detected
>> [sw-ehci2]: open clock
>> [1.907602] [sw-ehci2]: open clock
>> [sw-ehci2]: Set USB Power ON
>> [1.923679] [sw-ehci2]: Set USB Power ON
>>
>>
>> if any body has an idea please help. 
>>
>>

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/*
 * devmem2.c: Simple program to read/write from/to any location in memory.
 *
 *  Copyright (C) 2000, Jan-Derk Bakker (j.d.bak...@its.tudelft.nl)
 *  modified 2005 by Alessandro Rubini, to make it less verbose
 *
 *
 * This software has been developed for the LART computing board
 * (http://www.lart.tudelft.nl/). The development has been sponsored by
 * the Mobile MultiMedia Communications (http://www.mmc.tudelft.nl/)
 * and Ubiquitous Communications (http://www.ubicom.tudelft.nl/)
 * projects.
 *
 * The author can be reached at:
 *
 *  Jan-Derk Bakker
 *  Information and Communication Theory Group
 *  Faculty of Information Technology and Systems
 *  Delft University of Technology
 *  P.O. Box 5031
 *  2600 GA Delft
 *  The Netherlands
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
  
#define FATAL do { fprintf(stderr, "Error at line %d, file %s (%d) [%s]\n", \
  __LINE__, __FILE__, errno, strerror(errno)); exit(1); } while(0)
 
#define MAP_SIZE 4096UL
#define MAP_MASK (MAP_SIZE - 1)

int verbose = 0;
int main(int argc, char **argv) {
 int fd;
 void *map_base, *virt_addr; 
 unsigned long read_result, writeval;
 int wid;
 char format[16];
 off_t target;
 int access_type = 'w';
	

 setuid(0); /* try */

 if(argc < 2) {
	  fprintf(stderr, "\nUsage:\t%s { address } [ type [ data ] ]\n"
		  "\taddress : memory address to act upon\n"
		  "\ttype: access operation type : [b]yte, [h]alfword, [w]ord\n"
		  "\tdata: data to be written\n\n",
		  argv[0]);
	  exit(1);
 }
 target = strtoul(argv[1], 0, 0);

 if(argc > 2)
	  access_type = tolower(argv[2][0]);


 if((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) FATAL;
 if (verbose) {
	  printf("/dev/mem opened.\n"); 
	  fflush(stdout);
 }

 /* Map one page */
 map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, target & ~MAP_MASK);
 if(map_base == (void *) -1) FATAL;
 if (verbose) {
	

Re: [linux-sunxi] A31 u-boot with axp221 support now available

2014-04-01 Thread Hans de Goede
Hi,

On 04/01/2014 05:29 AM, Chen-Yu Tsai wrote:
> Hi,
> 
> On Tue, Apr 1, 2014 at 7:12 AM, Hans de Goede  wrote:
>> Hi All,
>>
>> Here is a branch of u-boot for the A31 with preliminary axp221
>> support:
>>
>> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-a31-axp221
>>
>> Many thanks to Olliver for the initial p2wi and axp221 code, it was
>> a good starting point. Note still no SPL, this is to be loaded
>> from boot00 + boot1.
>>
>> Advantages over the allwinner generated images u-boot are:
>> -fdt support
>> -axp221 code will properly power the gpio's and sdcard at 3.3v, rather
>> then undervolt them at 3v
>> -axp221 code will activate ldo1, and thus give power to the phy,
>> so now we can go and test wens gmac for a31 work
> 
> nitpick: the proper name is dldo1, as seen in the datasheet.

Yeah I already have it as dldo1 in the code.

> Hope you get SPL working soon. :)

I guess I was not clear before, I do not plan to work any further on the
SPL. I don't have the time / energy to tackle the dram issue. I was hoping
that all my other work on this, which means you can now build the SPL,
and it will have working clocks, uart and can talk to the axp would be enough
of a head-start to get someone else to go and tackle the dram controller
issue ...

Regards,

Hans

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