[linux-sunxi] Re: Default cpufreq governor: performance vs. interactive/ondemand

[Thomas Kaiser]

Thomas Kaiser wrote:
>
> I have no multimeter that would be precise enough so I rely on the thermal 
> sensors in the 2 SoCs I used to show the difference the clockspeed makes 
> depending on dvfs settings. 


I bought a powermeter in the meantime and get a difference of ~250mW idle 
consumption on a Banana Pi M3 (A83T) when switching between interactive and 
performance (between 2.9/3W with interactive and 3.2W with performance) 
with the following settings:

scaling_max_freq: 180 (@1080 mV defined in dvfs table)
scaling_min_freq: 48 (@840 mV defined in dvfs table)

Then I defined dvfs settings where all cpufreq operating points share the 
same 1080mV and tested again. I couldn't measure a difference in 
consumption realiably but the SoC's internal sensor showed at least some 
differences. On the left Vcore set statically to 1080mV and on the right 
the very same test with dynamic voltage frequency scaling and voltage being 
adjusted between 840mV and 1080mV when walking through 
_scaling_available_frequencies_:

http://linux-sunxi.org/File:A83T_Vcore_static_vs_dvfs.png

I still believe that my consumption measurements are too unrealiable to 
draw any conclusions from. But in the meantime I believe there's some 
evidence that the whole discussion about power savings or waste of energy 
due to different cpufreq governors is totally useless if the dvfs settings 
aren't considered as well. Since based on my tests with A20, H3 and A83T 
the clockspeed alone wasn't that important regarding consumption and 
internal SoC temperatures. But the voltage was.

Therefore I find it a bit hard to draw _any_ conclusions from these two 
sets of practical tests that are referenced here since the used dvfs 
settings aren't mentioned (or I missed it):

http://linux-sunxi.org/Cpufreq#The_.22performance.22_governor

"The practical tests 
 
show 
 that 
there is not much power consumption difference between idling at 60MHz and 
idling at 1008MHz (a ~1.5x difference on Cortex-A8, almost no difference on 
Cortex-A7)"

In my tests it made a huge or nearly no difference to switch between both 
governors -- based on the dvfs settings defined: the higher the voltage 
difference therein the more difference in consumption. While I still 
understand that a switch to performance seemed like a good idea two years 
ago when OS images with 60MHz _scaling_min_freq_ and fantasy or ondemand 
governor were used, I doubt it's the right approach when taking dvfs 
settings into account.

IMO a better approach is to choose interactive and adjust scaling_min_freq 
to the cpufreq with the lowest voltage defined in the dvfs table (or maybe 
one above). At least my tests made with the H3 recently showed nearly no 
difference whether the H3 idled at 240 or 720 MHz (both defined with the 
lowest voltage in the dvfs table) therefore I chose 720 as 
_scaling_min_freq_ and the system behaves as snappy as with performance:

http://linux-sunxi.org/File:H3_testing_cpufreq_limits.png

I can't test that with an A10 board since I don't own one. But might the 
test results from back then ("a ~1.5x difference on Cortex-A8, almost no 
difference on Cortex-A7") not be related more to dvfs settings than A8 vs. 
A7?

Thx,

Thomas

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[linux-sunxi] Re: [PATCH 0/4] ARM: sun9i: Support Allwinner A80 NMI controller

[Jason Cooper]

Chen-Yu,

On Thu, Dec 03, 2015 at 04:20:09PM +0800, Chen-Yu Tsai wrote:
> This series extends support to the A80 SoC. This is needed to add
> support for the PMICs. A complete series, including PMIC support,
> can be found here:
> 
> https://github.com/wens/linux/tree/axp809

I'll pull all but the last patch in this series into a separate, stable
branch you can base off of at some point today.

thx,

Jason.

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Re: [linux-sunxi] a20-olinuxino-micro openocd

[Benjamin Henrion]

On Fri, Dec 4, 2015 at 3:43 PM,   wrote:
> Hi there,
>
> does anybody know about support for openocd, arm-usb-tiny-h, 
> a20-olinuxino-micro.
>
> I have tried several openocd scripts, but cannot communicate with the board.
>
> jtag is connected like described in the manual.

openocd has an autodetect feature, have you tried it?

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[linux-sunxi] Re: [PATCH 1/7] pinctrl: sunxi: Add A80 special pin controller

[Rob Herring]

On Tue, Dec 01, 2015 at 01:47:19PM +0800, Chen-Yu Tsai wrote:
> From: Maxime Ripard 
> 
> Like the previous designs, the A80 has a special pin controller for the
> critical pins, like the PMIC bus.
> 
> Add a driver for this controller.
> 
> Signed-off-by: Maxime Ripard 
> [wens: Add A80 compatible strings to bindings doc; fix pin function
>names based on v1.3 datasheet; constify of_device_id table]
> Signed-off-by: Chen-Yu Tsai 
> ---
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   2 +

For the binding:

Acked-by: Rob Herring 

>  drivers/pinctrl/sunxi/Kconfig  |   5 +
>  drivers/pinctrl/sunxi/Makefile |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c| 181 
> +
>  4 files changed, 189 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
> 
> diff --git 
> a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
> b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index b321b26780dc..b3b6c2f210d7 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -18,6 +18,8 @@ Required properties:
>"allwinner,sun8i-a23-r-pinctrl"
>"allwinner,sun8i-a33-pinctrl"
>"allwinner,sun8i-a83t-pinctrl"
> +  "allwinner,sun9i-a80-pinctrl"
> +  "allwinner,sun9i-a80-r-pinctrl"
>  
>  - reg: Should contain the register physical address and length for the
>pin controller.
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index e68fd951129a..0252b3fa41ce 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -55,4 +55,9 @@ config PINCTRL_SUN9I_A80
>   def_bool MACH_SUN9I
>   select PINCTRL_SUNXI_COMMON
>  
> +config PINCTRL_SUN9I_A80_R
> + def_bool MACH_SUN9I
> + depends on RESET_CONTROLLER
> + select PINCTRL_SUNXI_COMMON
> +
>  endif
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index e08029034510..0b4b827f314b 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R)   += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)  += pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80)  += pinctrl-sun9i-a80.o
> +obj-$(CONFIG_PINCTRL_SUN9I_A80_R)+= pinctrl-sun9i-a80-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c 
> b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
> new file mode 100644
> index ..42547ffa20a8
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
> @@ -0,0 +1,181 @@
> +/*
> + * Allwinner A80 SoCs special pins pinctrl driver.
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + * Maxime Ripard 
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> +   SUNXI_FUNCTION(0x0, "gpio_in"),
> +   SUNXI_FUNCTION(0x1, "gpio_out"),
> +   SUNXI_FUNCTION(0x3, "s_uart"),/* TX */
> +   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> +   SUNXI_FUNCTION(0x0, "gpio_in"),
> +   SUNXI_FUNCTION(0x1, "gpio_out"),
> +   SUNXI_FUNCTION(0x3, "s_uart"),/* RX */
> +   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> +   SUNXI_FUNCTION(0x0, "gpio_in"),
> +   SUNXI_FUNCTION(0x1, "gpio_out"),
> +   SUNXI_FUNCTION(0x3, "s_jtag"),/* TMS */
> +   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
> +   SUNXI_FUNCTION(0x0, "gpio_in"),
> +   SUNXI_FUNCTION(0x1, "gpio_out"),
> +   SUNXI_FUNCTION(0x3, "s_jtag"),/* TCK */
> +   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
> +   SUNXI_FUNCTION(0x0, "gpio_in"),
> +   SUNXI_FUNCTION(0x1, "gpio_out"),
> +   SUNXI_FUNCTION(0x3, "s_jtag"),/* TDO */
> +   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
> +   SUNXI_FUNCTION(0x0, "gpio_in"),
> +   SUNXI_FUNCTION(0x1, 

Re: [linux-sunxi] Re: i2s audio codec support for sun7i

[Puneet B]

Hi

I did only playback in my A20 setup, for record may be you need to
configure codec register properly.
and also check your machine driver is configure properly for capture the
audio.



On Wed, Dec 2, 2015 at 5:26 PM,  wrote:

> Dear Punith
>
> my codec is working as playback device.
> i am trying to work with as capture device.
>
> i connect tlv320aic via i2s and i am contorlling tlv's registers as
> manually using i2c. it is working while play mode.
>
> my console logs is below.
>
> and i sniffed i2s data in of A20 , the sound signal is exist.
>
> do you have any idea why not work capture?
>
> root@marsboard:/var/app/sound# aplay -l
>  List of PLAYBACK Hardware Devices 
> card 0: sunxicodec [sunxi-CODEC], device 0: M1 PCM [sunxi PCM]
>   Subdevices: 1/1
>   Subdevice #0: subdevice #0
> card 1: sunxisndi2s [sunxi-sndi2s], device 0: SUNXI-I2S sndi2s-0 []
>   Subdevices: 1/1
>   Subdevice #0: subdevice #0
>
> root@marsboard:/var/app/sound# arecord -l
>  List of CAPTURE Hardware Devices 
> card 0: sunxicodec [sunxi-CODEC], device 0: M1 PCM [sunxi PCM]
>   Subdevices: 1/1
>   Subdevice #0: subdevice #0
> card 1: sunxisndi2s [sunxi-sndi2s], device 0: SUNXI-I2S sndi2s-0 []
>   Subdevices: 1/1
>   Subdevice #0: subdevice #0
> root@marsboard:/var/app/sound#
>
> root@marsboard:/var/app/sound# arecord - /dev/null -D hw:1,0 -f S16_LE
> Recording WAVE '/dev/null' : Signed 16 bit Little Endian, Rate 8000 Hz,
> Mono
> Hardware PCM card 1 'sunxi-sndi2s' device 0 subdevice 0
> Its setup is:
>   stream   : CAPTURE
>   access   : RW_INTERLEAVED
>   format   : S16_LE
>   subformat: STD
>   channels : 1
>   rate : 8000
>   exact rate   : 8000 (8000/1)
>   msbits   : 16
>   buffer_size  : 8192
>   period_size  : 2048
>   period_time  : 256000
>   tstamp_mode  : NONE
>   period_step  : 1
>   avail_min: 2048
>   period_event : 0
>   start_threshold  : 1
>   stop_threshold   : 8192
>   silence_threshold: 0
>   silence_size : 0
>   boundary : 1073741824
>   appl_ptr : 0
>   hw_ptr   : 0
> arecord: pcm_read:1801: read error: Input/output error
>
>
>
>
>
>
>
> On Saturday, April 4, 2015 at 11:25:36 AM UTC+2, Puneet B wrote:
> > You need to check codec driver and please aware of that whatever you are
> doing in machine driver should be supported
> > from codec driver.
> >
> >
> > Check the difference of codec drivers.
> >
> > Regards
> > Punith
> >
> >
> >
> > On Sat, Apr 4, 2015 at 1:59 PM, OMER AYGOR EYZA TEKNOLOJİ <
> oay...@eyzateknoloji.com> wrote:
> >
> >
> > hi
> >
> > i tried your machine code and log is like this:
> >
> > root@marsboard:~# mplayer -ao alsa:device=hw=2.0 a.mp3
> > MPlayer2 UNKNOWN (C) 2000-2012 MPlayer Team
> > mplayer: could not connect to socket
> > mplayer: No such file or directory
> > Failed to open LIRC support. You will not be able to use your remote
> control.
> >
> > Playing a.mp3.
> > Detected file format: MPEG audio layer 2/3 (libavformat)
> > [mp3 @ 0xb5b3c558]max_analyze_duration reached
> > [mp3 @ 0xb5b3c558]Estimating duration from bitrate, this may be
> inaccurate
> > [lavf] stream 0: audio (mp3), -aid 0
> > Clip info:
> >  title: Overprotected
> >  artist: Britney Spears
> >  genre: Other
> > Load subtitles in .
> >
> ==
> > Requested audio codec family [mpg123] (afm=mpg123) not available.
> > Enable it at compilation.
> > Opening audio decoder: [ffmpeg] FFmpeg/libavcodec audio decoders
> > AUDIO: 44100 Hz, 2 ch, floatle, 128.0 kbit/4.54% (ratio: 16000->352800)
> > Selected audio codec: [ffmp3float] afm: ffmpeg (FFmpeg MPEG layer-3
> audio)
> >
> ==
> > [AO_ALSA] Format floatle is not psupported by hardware, trying default.
> > uneet rx51_hw_params
> > [   47.143600] puneet rx51_hw_params
> > puneet@TLV320AIC3100 aic31xx_set_dai_fmt
> > [   47.151019] puneet@TLV320AIC3100 aic31xx_set_dai_fmt
> > puneet@TLV320AIC3100 aic31xx_change_page
> > [   47.159817] puneet@TLV320AIC3100 aic31xx_change_page
> > ##+ aic31xx_set_dai_fmt (4101)
> > [   47.169024] ##+ aic31xx_set_dai_fmt (4101)
> > ##- aic31xx_set_dai_fmt (0)
> > [   47.175716] ##- aic31xx_set_dai_fmt (0)
> > puneet@TLV320AIC3100 aic31xx_set_dai_sysclk
> > [   47.184386] puneet@TLV320AIC3100 aic31xx_set_dai_sysclk
> > ##aic31xx_set_dai_sysclk clk_id(0) (5644800)
> > [   47.193734] ##aic31xx_set_dai_sysclk clk_id(0) (5644800)
> > <1>Invalid frequency to set DAI system clock
> > [   47.203381] Invalid frequency to set DAI system clock
> > puneet@TLV320AIC3100 aic31xx_hw_params
> > [   47.212032] puneet@TLV320AIC3100 aic31xx_hw_params
> > ##+ SET aic31xx_hw_params
> > [   47.219552] ##+ SET aic31xx_hw_params
> > puneet@TLV320AIC3100 aic31xx_get_divs
> > [   47.226732] puneet@TLV320AIC3100 aic31xx_get_divs
> > ###+ aic31xx_get_divs mclk(5644800) rate(44100)
> > [   47.236080] ###+ aic31xx_get_divs mclk(5644800) 

[linux-sunxi] Need some help to configure ft5x on an A13 tablet.

[l_faillie via linux-sunxi]

Hello,

I'm still playing with my Klipad HC-913 tablet 
(http://linux-sunxi.org/index.php?title=MID-KLIPAD_HC-913) but I'm failing to 
use the touchpad.

I'm using the FEX I took from Android which saying ft5x_ts is used.

The module is correctly loaded :

$ lsmod 
Module  Size  Used by
ft5x_ts40564  0
cdc_ether   5104  0
usbnet 16861  1 cdc_ether

and in dmesg :

[6.787934] ===ft5x_ts_init=
[6.787957] ctp_fetch_sysconfig_para. 
[6.787981] ctp_fetch_sysconfig_para: after: ctp_twi_addr is 0x3f, dirty_addr
_buf: 0x3f. dirty_addr_buf[1]: 0xfffe 
[6.787994] ctp_fetch_sysconfig_para: ctp_twi_id is 1. 
[6.788002] ctp_fetch_sysconfig_para: screen_max_x = 800. 
[6.788011] ctp_fetch_sysconfig_para: screen_max_y = 480. 
[6.788023] ctp_fetch_sysconfig_para: revert_x_flag = 0. 
[6.788032] ctp_fetch_sysconfig_para: revert_y_flag = 0. 
[6.788040] ctp_fetch_sysconfig_para: exchange_x_y_flag = 0. 
[6.788049] ft5x_ts_init: after fetch_sysconfig_para:  normal_i2c: 0x3f. norm
al_i2c[1]: 0xfffe 
[6.788075] ctp_init_platform_resource: tp_reset request gpio fail!
[6.788084] ctp_init_platform_resource: No power port feature present.
[6.788094] ctp_wakeup. 
[6.829440] ctp_detect: Detected chip ft5x_ts at adapter 1, address 0x3f
[6.832848] ft5x_ts_probe begin=.  
[6.835739] input: ft5x_ts as /devices/platform/sunxi-i2c.1/i2c-1/1-003f/inpu
t/input1
[6.836488] ctp_set_irq_mode: config gpio to int mode. 
[6.836519] ctp_set_irq_mode, 225: gpio_int_info, port = 7, port_num = 11. 
[6.836526]  INTERRUPT CONFIG
[6.837899] ==ft5x_ts_probe over =

and it is associated to /dev/input/mouse0 and /dev/input/event1

But
$ cat /dev/input/event1
doesn't display anything when I touch the screen.

As per my readings, I need to patch the source code. 
(https://github.com/linux-sunxi/linux-sunxi/issues/178)

So what I have to do ?
- remove IRQF_TRIGGER_FALLING from ft5x_ts.c line 1765 ?
- what about the "multi-touch" ?
- anything else to do ?

Thanks

Laurent

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[linux-sunxi] [PATCH v5 0/4] ARM: sunxi: Allwinner H3 support

[Jens Kuske]

Hi everyone,

This is v5 of my patch series introducing basic kernel support for Allwinner's
H3 SoC. It mainly adds basic clocks, resets and pinctrl. It also adds
interrupts, timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly
compatible to those in earlier SoCs like A23 and A31, and can simply be reused.

These patches are based on the sunxi-next branch from
git://github.com/linux-sunxi/linux-sunxi.git


Patch 1 adds basic H3 clocks.

Patch 2 adds pin sets for the H3 main PIO.

Patch 3 adds the DTSI for the H3.

Patch 4 adds a DTS for the Orange Pi Plus SBC, which these patches
were developed and tested with.

Changes since v4:
- drop the pll clock cleanup and use dummy clocks instead for now, Maxime
  wants to take care of cleaning up the plls
- split the resets again (as in v1), drop the of_xlate
- fix all reported pinctrl mistakes
- remove memory node and timer frequency from dtsi
- rename the bus gates to bus_*
- clean up the bus gates driver

Changes since v3:
- add a clock driver specific to the bus gates instead of listing parents in
  the DTSI
- skip the holes in the reset controller with of_xlate()

Changes since v2:
- add mbus clock
- add Maxime's suggestion to take the substring up to the first "_" as name
  for the divs base clock
- use A31 pll6 for H3 pll6
- use a clock similar to the new simple gates for H3 bus gates
- drop the pinctrl-as-module patch since pinctrl and gpio don't seem to be
  ready for removable drivers
- documentation and machine support are merged already
  
Changes since v1:
- Update sunxi README in Documentation
- Add the multiple parents gates and use them for bus-gates instead of
  ahb1, ahb2, apb1 and apb2 gates
- Merge the pll8 clock with sun6i pll6
- Merge the ahb12, apb1 and apb2 resets to bus-resets with own compatible
- Add sun6i_timer_init to sun8i machine
- Remove the single SoC names from machine definition, its sun8i family
- Make the pinctrl driver tristate and put its Kconfig entry in the right order
- Rename pinctrl "scr" to "sim" and clock "sim" to "scr" to match user manual
- Remove the address paragraph from GPL in dts and dtsi
- Some style cleanup and line wrapping in dtsi
- Add ARM architected timers
- dmaengine isn't included anymore, it is merged already

Best Regards,
Jens


Jens Kuske (4):
  clk: sunxi: Add H3 clocks support
  pinctrl: sunxi: Add H3 PIO controller support
  ARM: dts: sunxi: Add Allwinner H3 DTSI
  ARM: dts: sun8i: Add Orange Pi Plus support

 Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile |   3 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts   |  77 +++
 arch/arm/boot/dts/sun8i-h3.dtsi| 497 
 drivers/clk/sunxi/Makefile |   1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c| 112 +
 drivers/clk/sunxi/clk-sunxi.c  |   6 +
 drivers/pinctrl/sunxi/Kconfig  |   4 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c   | 515 +
 11 files changed, 1218 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
 create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
 create mode 100644 drivers/clk/sunxi/clk-sun8i-bus-gates.c
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c

-- 
2.6.3

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[linux-sunxi] [PATCH v5 1/4] clk: sunxi: Add H3 clocks support

[Jens Kuske]

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 112 ++
 drivers/clk/sunxi/clk-sunxi.c |   6 ++
 4 files changed, 121 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun8i-bus-gates.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 153ac72..437962d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -29,6 +29,7 @@ Required properties:
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+   "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -56,6 +57,7 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+   "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 103efab..abf4916 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
+obj-y += clk-sun8i-bus-gates.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c 
b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
new file mode 100644
index 000..7ab60c5
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * Based on clk-simple-gates.c, which is:
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sun8i_h3_bus_gates_init(struct device_node *node)
+{
+   static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
+   enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
+   const char *parents[PARENT_MAX];
+   struct clk_onecell_data *clk_data;
+   const char *clk_name;
+   struct property *prop;
+   struct resource res;
+   void __iomem *clk_reg;
+   void __iomem *reg;
+   const __be32 *p;
+   int number, i;
+   u8 clk_bit;
+   u32 index;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg))
+   return;
+
+   for (i = 0; i < ARRAY_SIZE(names); i++) {
+   index = of_property_match_string(node, "clock-names",
+names[i]);
+   if (index < 0)
+   return;
+
+   parents[i] = of_clk_get_parent_name(node, index);
+   }
+
+   clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+   if (!clk_data)
+   goto err_unmap;
+
+   number = of_property_count_u32_elems(node, "clock-indices");
+   of_property_read_u32_index(node, "clock-indices", number - 1, );
+
+   clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+   if (!clk_data->clks)
+  

[linux-sunxi] [PATCH v5 2/4] pinctrl: sunxi: Add H3 PIO controller support

[Jens Kuske]

The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Jens Kuske 
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig  |   4 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c   | 515 +
 4 files changed, 521 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index b321b26..e6ba602 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -18,6 +18,7 @@ Required properties:
   "allwinner,sun8i-a23-r-pinctrl"
   "allwinner,sun8i-a33-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index e68fd95..89ab7f5 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -51,6 +51,10 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_H3
+   def_bool MACH_SUN8I
+   select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index e080290..6bd818e 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,4 +13,5 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)   += 
pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
new file mode 100644
index 000..77d4cf0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
@@ -0,0 +1,515 @@
+/*
+ * Allwinner H3 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai 
+ * Copyright (C) 2014 Maxime Ripard 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_h3_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x3, "jtag"),  /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x3, "pwm0"),
+  

[linux-sunxi] [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jens Kuske]

The Allwinner H3 is a home entertainment system oriented SoC with
four Cortex-A7 cores and a Mali-400MP2 GPU.

Signed-off-by: Jens Kuske 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 497 
 1 file changed, 497 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
new file mode 100644
index 000..1524130e
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -0,0 +1,497 @@
+/*
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include 
+#include 
+
+/ {
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+
+   pll1: clk@01c2 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a23-pll1-clk";
+   reg = <0x01c2 0x4>;
+   clocks = <>;
+   clock-output-names = "pll1";
+   };
+
+   /* dummy clock until actually implemented */
+   pll5: pll5_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <0>;
+   clock-output-names = "pll5";
+   };
+
+   pll6: clk@01c20028 {
+   

[linux-sunxi] [PATCH v5 4/4] ARM: dts: sun8i: Add Orange Pi Plus support

[Jens Kuske]

The Orange Pi Plus is a SBC based on the Allwinner H3 SoC
with 8GB eMMC, multiple USB ports through a USB hub chip, SATA through
a USB-SATA bridge, one uSD slot, a 10/100/1000M ethernet port,
WiFi, HDMI, headphone jack, IR receiver, a microphone, a CSI connector
and a 40-pin GPIO header.

Signed-off-by: Jens Kuske 
---
 arch/arm/boot/dts/Makefile   |  3 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 
 2 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e8f44c7..cc7309b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -661,7 +661,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \
-   sun8i-a33-sinlinx-sina33.dtb
+   sun8i-a33-sinlinx-sina33.dtb \
+   sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
new file mode 100644
index 000..e67df59
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015 Jens Kuske 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+
+/ {
+   model = "Xunlong Orange Pi Plus";
+   compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>, <_cd_pin>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <4>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   cd-inverted;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
-- 
2.6.3

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