[linux-sunxi] [PATCH v2 20/26] drm: sun4i: tv: Add PAL output standard

[Maxime Ripard]

Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 42 
 1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 4f10f8b6b07c..4f369de2a1fc 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -176,7 +176,49 @@ struct sun4i_tv {
struct sun4i_drv*drv;
 };
 
+struct video_levels pal_video_levels = {
+   .black = 252,   .blank = 252,
+};
+
+struct burst_levels pal_burst_levels = {
+   .cb = 40,   .cr = 40,
+};
+
+struct color_gains pal_color_gains = {
+   .cb = 224,  .cr = 224,
+};
+
+struct resync_parameters pal_resync_parameters = {
+   .field = true,  .line = 13, .pixel = 12,
+};
+
 struct tv_mode tv_modes[] = {
+   {
+   .name   = "PAL",
+   .mode   = SUN4I_TVE_CFG0_RES_576i,
+   .chroma_freq= 0x2a098acb,
+
+   .back_porch = 138,
+   .front_porch= 24,
+   .line_number= 625,
+
+   .hdisplay   = 720,
+   .hfront_porch   = 3,
+   .hsync_len  = 2,
+   .hback_porch= 139,
+
+   .vdisplay   = 576,
+   .vfront_porch   = 28,
+   .vsync_len  = 2,
+   .vback_porch= 19,
+
+   .vblank_level   = 252,
+
+   .color_gains= _color_gains,
+   .burst_levels   = _burst_levels,
+   .video_levels   = _video_levels,
+   .resync_params  = _resync_parameters,
+   },
 };
 
 static inline struct sun4i_tv *
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 08/26] clk: sun5i: add DRAM gates

[Maxime Ripard]

The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index fe34fc56e803..2a76cc3718d4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -57,6 +57,7 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
+   "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c 
b/drivers/clk/sunxi/clk-simple-gates.c
index 0214c6548afd..5666c767fa14 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -112,6 +112,8 @@ CLK_OF_DECLARE(sun5i_a13_apb0, 
"allwinner,sun5i-a13-apb0-gates-clk",
   sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
   sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_dram, "allwinner,sun5i-a13-dram-gates-clk",
+  sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
   sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock

[Maxime Ripard]

The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.

It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).

Add a driver for the channel 1 clock.

Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c| 154 ++
 3 files changed, 156 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index bb9fb78dcff8..fe34fc56e803 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -67,6 +67,7 @@ Required properties:
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on 
the A10
+   "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on 
the A10
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 40c32ffd912c..0a20873cd103 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun4i-display.o
 obj-y += clk-sun4i-pll3.o
+obj-y += clk-sun4i-tcon-ch1.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 
b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
new file mode 100644
index ..51ddc38821f7
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SUN4I_TCON_CH1_SCLK_NAME_LEN   32
+
+#define SUN4I_A10_TCON_CH1_SCLK2_PARENTS   4
+
+#define SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT  31
+#define SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK  3
+#define SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT 24
+#define SUN4I_A10_TCON_CH1_SCLK2_DIV_WIDTH 4
+#define SUN4I_A10_TCON_CH1_SCLK2_DIV_SHIFT 0
+
+#define SUN4I_A10_TCON_CH1_SCLK1_GATE_BIT  15
+#define SUN4I_A10_TCON_CH1_SCLK1_DIV_WIDTH 1
+#define SUN4I_A10_TCON_CH1_SCLK1_DIV_SHIFT 11
+
+static DEFINE_SPINLOCK(sun4i_a10_tcon_ch1_lock);
+
+static void __init sun4i_a10_tcon_ch1_setup(struct device_node *node)
+{
+   const char *sclk2_parents[SUN4I_A10_TCON_CH1_SCLK2_PARENTS];
+   const char *sclk1_name = node->name;
+   const char *sclk2_name;
+   struct clk_divider *sclk1_div, *sclk2_div;
+   struct clk_gate *sclk1_gate, *sclk2_gate;
+   struct clk_mux *sclk2_mux;
+   struct clk *sclk1, *sclk2;
+   void __iomem *reg;
+   int i, ret;
+
+   of_property_read_string(node, "clock-output-names",
+   _name);
+
+   sclk2_name = kasprintf(GFP_KERNEL, "%s2", sclk1_name);
+   if (!sclk2_name)
+   return;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n", sclk2_name);
+   return;
+   }
+
+   for (i = 0; i < SUN4I_A10_TCON_CH1_SCLK2_PARENTS; i++)
+   sclk2_parents[i] = of_clk_get_parent_name(node, i);
+
+   sclk2_mux = kzalloc(sizeof(*sclk2_mux), GFP_KERNEL);
+   if (!sclk2_mux)
+   return;
+
+   sclk2_mux->reg = reg;
+   sclk2_mux->shift = SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT;
+   sclk2_mux->mask = SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK;
+   sclk2_mux->lock = _a10_tcon_ch1_lock;
+
+   sclk2_gate = kzalloc(sizeof(*sclk2_gate), GFP_KERNEL);
+   if (!sclk2_gate)
+   goto free_sclk2_mux;
+
+   sclk2_gate->reg = reg;
+   sclk2_gate->bit_idx = SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT;
+   sclk2_gate->lock = _a10_tcon_ch1_lock;
+
+   sclk2_div = kzalloc(sizeof(*sclk2_div), GFP_KERNEL);
+   

[linux-sunxi] [PATCH v2 18/26] drm: sun4i: Add RGB output

[Maxime Ripard]

One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/Makefile |   2 +
 drivers/gpu/drm/sun4i/sun4i_rgb.c  | 229 +
 drivers/gpu/drm/sun4i/sun4i_rgb.h  |  18 +++
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  26 -
 drivers/gpu/drm/sun4i/sun4i_tcon.h |   2 +
 5 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.h

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 7b0e83bae867..a7c9e7fd5a26 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -3,6 +3,8 @@ sun4i-drm-y += sun4i_drv.o
 sun4i-drm-y += sun4i_framebuffer.o
 sun4i-drm-y += sun4i_layer.o
 
+sun4i-drm-y += sun4i_rgb.o
+
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o
 
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c 
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
new file mode 100644
index ..c2b366e39749
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "sun4i_drv.h"
+#include "sun4i_tcon.h"
+
+struct sun4i_rgb {
+   struct drm_connectorconnector;
+   struct drm_encoder  encoder;
+
+   struct sun4i_drv*drv;
+};
+
+static inline struct sun4i_rgb *
+drm_connector_to_sun4i_rgb(struct drm_connector *connector)
+{
+   return container_of(connector, struct sun4i_rgb,
+   connector);
+}
+
+static inline struct sun4i_rgb *
+drm_encoder_to_sun4i_rgb(struct drm_encoder *encoder)
+{
+   return container_of(encoder, struct sun4i_rgb,
+   encoder);
+}
+
+static int sun4i_rgb_get_modes(struct drm_connector *connector)
+{
+   struct sun4i_rgb *rgb =
+   drm_connector_to_sun4i_rgb(connector);
+   struct sun4i_drv *drv = rgb->drv;
+   struct sun4i_tcon *tcon = drv->tcon;
+
+   return drm_panel_get_modes(tcon->panel);
+}
+
+static int sun4i_rgb_mode_valid(struct drm_connector *connector,
+   struct drm_display_mode *mode)
+{
+   u32 hsync = mode->hsync_end - mode->hsync_start;
+   u32 vsync = mode->vsync_end - mode->vsync_start;
+
+   DRM_DEBUG_DRIVER("Validating modes...\n");
+
+   if ((hsync < 1) || (hsync > 0x3ff) ||
+   (mode->htotal < 1) || (mode->htotal > 0xfff))
+   return MODE_H_ILLEGAL;
+
+   DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
+
+   if ((vsync < 1) || (vsync > 0x3ff) ||
+   (mode->vtotal < 1) || (mode->vtotal > 0xfff))
+   return MODE_V_ILLEGAL;
+
+   DRM_DEBUG_DRIVER("Vertical parameters OK\n");
+
+   return MODE_OK;
+}
+
+static struct drm_encoder *
+sun4i_rgb_best_encoder(struct drm_connector *connector)
+{
+   struct sun4i_rgb *rgb =
+   drm_connector_to_sun4i_rgb(connector);
+
+   return >encoder;
+}
+
+static struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
+   .get_modes  = sun4i_rgb_get_modes,
+   .mode_valid = sun4i_rgb_mode_valid,
+   .best_encoder   = sun4i_rgb_best_encoder,
+};
+
+static enum drm_connector_status
+sun4i_rgb_connector_detect(struct drm_connector *connector, bool force)
+{
+   return connector_status_connected;
+}
+
+static void
+sun4i_rgb_connector_destroy(struct drm_connector *connector)
+{
+   struct sun4i_rgb *rgb = drm_connector_to_sun4i_rgb(connector);
+   struct sun4i_drv *drv = rgb->drv;
+   struct sun4i_tcon *tcon = drv->tcon;
+
+   drm_panel_detach(tcon->panel);
+   drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs sun4i_rgb_con_funcs = {
+   .dpms   = drm_atomic_helper_connector_dpms,
+   .detect = sun4i_rgb_connector_detect,
+   .fill_modes = drm_helper_probe_single_connector_modes,
+   .destroy= sun4i_rgb_connector_destroy,
+   .reset  = drm_atomic_helper_connector_reset,
+   .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+   .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
+};
+
+static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
+{
+   struct sun4i_rgb *rgb 

[linux-sunxi] [PATCH v2 11/26] ARM: sun5i: Add DRAM gates

[Maxime Ripard]

The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.

Enable it.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-a10s.dtsi |  7 ---
 arch/arm/boot/dts/sun5i-a13.dtsi  |  2 +-
 arch/arm/boot/dts/sun5i-r8.dtsi   |  2 +-
 arch/arm/boot/dts/sun5i.dtsi  | 19 +++
 4 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi 
b/arch/arm/boot/dts/sun5i-a10s.dtsi
index bddd0de88af6..52d2c79cb37b 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -66,7 +66,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
 
@@ -74,7 +74,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>;
+   clocks = < 1>, <_gates 36>, <_gates 44>,
+<_gates 26>;
status = "disabled";
};
 
@@ -83,7 +84,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 9669b03f20f3..f29163650ca8 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -62,7 +62,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <_gates 36>, <_gates 44>, <_be_clk>,
-<_ch0_clk>;
+<_ch0_clk>, <_gates 26>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index b1e4e0170d51..691d3de75b35 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -53,7 +53,7 @@
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <_gates 34>, <_gates 36>,
 <_gates 44>, <_be_clk>,
-<_ch1_clk>;
+<_ch1_clk>, <_gates 26>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 0840612b5ed6..c72d94228915 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -338,6 +338,25 @@
clock-output-names = "usb_ohci0", "usb_phy";
};
 
+   dram_gates: clk@01c20100 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun5i-a13-dram-gates-clk";
+   reg = <0x01c20100 0x4>;
+   clocks = < 0>;
+   clock-indices = <0>,
+   <1>,
+   <25>,
+   <26>,
+   <29>,
+   <31>;
+   clock-output-names = "dram_ve",
+"dram_csi",
+"dram_de_fe",
+"dram_de_be",
+"dram_ace",
+"dram_iep";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver

[Maxime Ripard]

The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.

Add a driver to support both.

Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-sun4i-display.c | 241 ++
 3 files changed, 244 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 8a47b77abfca..5360554a7d3f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -55,6 +55,7 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+   "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
@@ -64,6 +65,7 @@ Required properties:
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
+   "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on 
the A10
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index cb4c299214ce..a991cd8ca509 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
+obj-y += clk-sun4i-display.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-display.c 
b/drivers/clk/sunxi/clk-sun4i-display.c
new file mode 100644
index ..9dc6894f0934
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-display.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct sun4i_a10_display_clk_data {
+   boolhas_div;
+   boolhas_rst;
+   u8  parents;
+
+   u8  offset_en;
+   u8  offset_div;
+   u8  offset_mux;
+   u8  offset_rst;
+
+   u8  width_div;
+   u8  width_mux;
+};
+
+struct reset_data {
+   void __iomem*reg;
+   spinlock_t  *lock;
+   struct reset_controller_dev rcdev;
+   u8  offset;
+};
+
+static DEFINE_SPINLOCK(sun4i_a10_display_lock);
+
+static inline struct reset_data *rcdev_to_reset_data(struct 
reset_controller_dev *rcdev)
+{
+   return container_of(rcdev, struct reset_data, rcdev);
+};
+
+static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   struct reset_data *data = rcdev_to_reset_data(rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg & ~BIT(data->offset), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct reset_data *data = rcdev_to_reset_data(rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg | BIT(data->offset), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{

[linux-sunxi] [PATCH v2 02/26] reset: Make reset_control_ops const

[Maxime Ripard]

The ops pointer is holding a pointer to a structure that is usually not
modified. Make it const.

Signed-off-by: Maxime Ripard 
---
 include/linux/reset-controller.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index ce6b962ffed4..a3a5bcdb1d02 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -38,7 +38,7 @@ struct of_phandle_args;
  * @nr_resets: number of reset controls in this reset controller device
  */
 struct reset_controller_dev {
-   struct reset_control_ops *ops;
+   const struct reset_control_ops *ops;
struct module *owner;
struct list_head list;
struct device_node *of_node;
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 09/26] ARM: sun5i: dt: Add pll3 and pll7 clocks

[Maxime Ripard]

Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun5i.dtsi | 43 +++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 59a9426e3bd4..0840612b5ed6 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -88,6 +88,15 @@
clock-output-names = "osc24M";
};
 
+   osc3M: osc3M_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <8>;
+   clock-mult = <1>;
+   clocks = <>;
+   clock-output-names = "osc3M";
+   };
+
osc32k: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -112,6 +121,23 @@
 "pll2-4x", "pll2-8x";
};
 
+   pll3: clk@01c20010 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-pll3-clk";
+   reg = <0x01c20010 0x4>;
+   clocks = <>;
+   clock-output-names = "pll3";
+   };
+
+   pll3x2: pll3x2_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <2>;
+   clocks = <>;
+   clock-output-names = "pll3-2x";
+   };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -136,6 +162,23 @@
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
 
+   pll7: clk@01c20030 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-pll3-clk";
+   reg = <0x01c20030 0x4>;
+   clocks = <>;
+   clock-output-names = "pll7";
+   };
+
+   pll7x2: pll7x2_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <2>;
+   clocks = <>;
+   clock-output-names = "pll7-2x";
+   };
+
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 26/26] DO NOT MERGE: ARM: sun5i: chip: Enable the LCD panel

[Maxime Ripard]

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-r8-chip.dts | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts 
b/arch/arm/boot/dts/sun5i-r8-chip.dts
index c26c095b42c6..147c39106f63 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -82,6 +82,10 @@
vin0-supply = <_ldo3>;
vin1-supply = <_ldo4>;
};
+
+   panel: panel {
+   compatible = "olimex,lcd-olinuxino-43-ts";
+   };
 };
 
  {
@@ -236,6 +240,7 @@
 
  {
status = "okay";
+   allwinner,panel = <>;
 };
 
  {
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 23/26] ARM: sun5i: chip: Enable the TV Encoder

[Maxime Ripard]

The CHIP has a composite output available muxed with the microphone in the
micro-jack plug.

Enable the composite output in its DTS.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-r8-chip.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts 
b/arch/arm/boot/dts/sun5i-r8-chip.dts
index c976c7618118..c26c095b42c6 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -84,6 +84,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -230,6 +234,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_b>;
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 25/26] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS

[Maxime Ripard]

Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.

It is a 480x272 panel connected through a 24-bits RGB interface.

Signed-off-by: Maxime Ripard 
---
 .../display/panel/olimex,lcd-olinuxino-43-ts.txt   |  7 ++
 drivers/gpu/drm/panel/panel-simple.c   | 26 ++
 2 files changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
 
b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
new file mode 100644
index ..74540a090669
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
@@ -0,0 +1,7 @@
+Olimex 4.3" TFT LCD panel
+
+Required properties:
+- compatible: should be "olimex,lcd-olinuxino-43-ts"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index f97b73ec4713..3ae22e0a7f38 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1003,6 +1003,29 @@ static const struct panel_desc okaya_rs800480t_7x0gp = {
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };
 
+static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+   .clock = 9000,
+   .hdisplay = 480,
+   .hsync_start = 480 + 5,
+   .hsync_end = 480 + 5 + 30,
+   .htotal = 480 + 5 + 30 + 10,
+   .vdisplay = 272,
+   .vsync_start = 272 + 8,
+   .vsync_end = 272 + 8 + 5,
+   .vtotal = 272 + 8 + 5 + 3,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc olimex_lcd_olinuxino_43ts = {
+   .modes = _lcd_olinuxino_43ts_mode,
+   .num_modes = 1,
+   .size = {
+   .width = 105,
+   .height = 67,
+   },
+   .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
.clock = 25000,
.hdisplay = 480,
@@ -1179,6 +1202,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "okaya,rs800480t-7x0gp",
.data = _rs800480t_7x0gp,
}, {
+   .compatible = "olimex,lcd-olinuxino-43-ts",
+   .data = _lcd_olinuxino_43ts,
+   }, {
.compatible = "ortustech,com43h4m85ulc",
.data = _com43h4m85ulc,
}, {
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 01/26] reset: Move DT cell size check to the core

[Maxime Ripard]

The core currently doesn't check that the DT cell size matches what the
driver declares, which means that every xlate function needs to duplicate
that check.

Make sure that of_reset_control_get checks for this to avoid duplication
and errors.

Signed-off-by: Maxime Ripard 
---
 drivers/reset/core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/reset/core.c b/drivers/reset/core.c
index 7955e00d04d4..d53b2b980bdd 100644
--- a/drivers/reset/core.c
+++ b/drivers/reset/core.c
@@ -46,9 +46,6 @@ struct reset_control {
 static int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
  const struct of_phandle_args *reset_spec)
 {
-   if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
-   return -EINVAL;
-
if (reset_spec->args[0] >= rcdev->nr_resets)
return -EINVAL;
 
@@ -182,6 +179,9 @@ struct reset_control *of_reset_control_get(struct 
device_node *node,
return ERR_PTR(-EPROBE_DEFER);
}
 
+   if (WARN_ON(args.args_count != rcdev->of_reset_n_cells))
+   return ERR_PTR(-EINVAL);
+
rstc_id = rcdev->of_xlate(rcdev, );
if (rstc_id < 0) {
mutex_unlock(_controller_list_mutex);
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 21/26] drm: sun4i: tv: Add NTSC output standard

[Maxime Ripard]

Add the settings to support the NTSC standard.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 45 
 1 file changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 4f369de2a1fc..46331087b0e9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -176,24 +176,69 @@ struct sun4i_tv {
struct sun4i_drv*drv;
 };
 
+struct video_levels ntsc_video_levels = {
+   .black = 282,   .blank = 240,
+};
+
 struct video_levels pal_video_levels = {
.black = 252,   .blank = 252,
 };
 
+struct burst_levels ntsc_burst_levels = {
+   .cb = 79,   .cr = 0,
+};
+
 struct burst_levels pal_burst_levels = {
.cb = 40,   .cr = 40,
 };
 
+struct color_gains ntsc_color_gains = {
+   .cb = 160,  .cr = 160,
+};
+
 struct color_gains pal_color_gains = {
.cb = 224,  .cr = 224,
 };
 
+struct resync_parameters ntsc_resync_parameters = {
+   .field = false, .line = 14, .pixel = 12,
+};
+
 struct resync_parameters pal_resync_parameters = {
.field = true,  .line = 13, .pixel = 12,
 };
 
 struct tv_mode tv_modes[] = {
{
+   .name   = "NTSC",
+   .mode   = SUN4I_TVE_CFG0_RES_480i,
+   .chroma_freq= 0x21f07c1f,
+   .yc_en  = true,
+   .dac3_en= true,
+   .dac_bit25_en   = true,
+
+   .back_porch = 118,
+   .front_porch= 32,
+   .line_number= 525,
+
+   .hdisplay   = 720,
+   .hfront_porch   = 18,
+   .hsync_len  = 2,
+   .hback_porch= 118,
+
+   .vdisplay   = 480,
+   .vfront_porch   = 26,
+   .vsync_len  = 2,
+   .vback_porch= 17,
+
+   .vblank_level   = 240,
+
+   .color_gains= _color_gains,
+   .burst_levels   = _burst_levels,
+   .video_levels   = _video_levels,
+   .resync_params  = _resync_parameters,
+   },
+   {
.name   = "PAL",
.mode   = SUN4I_TVE_CFG0_RES_576i,
.chroma_freq= 0x2a098acb,
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 06/26] clk: sunxi: Add PLL3 clock

[Maxime Ripard]

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile|  1 +
 drivers/clk/sunxi/clk-sun4i-pll3.c| 90 +++
 3 files changed, 92 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 5360554a7d3f..bb9fb78dcff8 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,6 +10,7 @@ Required properties:
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+   "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a991cd8ca509..40c32ffd912c 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun4i-display.o
+obj-y += clk-sun4i-pll3.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-pll3.c 
b/drivers/clk/sunxi/clk-sun4i-pll3.c
new file mode 100644
index ..6c9c2210b6b2
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-pll3.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SUN4I_A10_PLL3_GATE_BIT31
+#define SUN4I_A10_PLL3_DIV_WIDTH   7
+#define SUN4I_A10_PLL3_DIV_SHIFT   0
+
+static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
+
+static void __init sun4i_a10_pll3_setup(struct device_node *node)
+{
+   const char *clk_name = node->name, *parent;
+   struct clk_multiplier *mult;
+   struct clk_gate *gate;
+   void __iomem *reg;
+   struct clk *clk;
+   int ret;
+
+   of_property_read_string(node, "clock-output-names", _name);
+   parent = of_clk_get_parent_name(node, 0);
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n", clk_name);
+   return;
+   }
+
+   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   if (!gate)
+   return;
+
+   gate->reg = reg;
+   gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
+   gate->lock = _a10_pll3_lock;
+
+   mult = kzalloc(sizeof(*mult), GFP_KERNEL);
+   if (!mult)
+   goto err_free_gate;
+
+   mult->reg = reg;
+   mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
+   mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
+   mult->lock = _a10_pll3_lock;
+
+   clk = clk_register_composite(NULL, clk_name,
+, 1,
+NULL, NULL,
+>hw, _multiplier_ops,
+>hw, _gate_ops,
+0);
+   if (IS_ERR(clk)) {
+   pr_err("%s: Couldn't register the clock\n", clk_name);
+   goto err_free_mult;
+   }
+
+   ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+   if (WARN_ON(ret))
+   goto err_clk_unregister;
+
+   return;
+
+err_clk_unregister:
+   clk_unregister_composite(clk);
+err_free_mult:
+   kfree(mult);
+err_free_gate:
+   kfree(gate);
+}
+
+CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
+  sun4i_a10_pll3_setup);
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit 

[linux-sunxi] [PATCH v2 17/26] drm: sun4i: Add DT bindings documentation

[Maxime Ripard]

The display pipeline of the Allwinner A10 is involving several loosely
coupled components.

Add a documentation for the bindings.

Signed-off-by: Maxime Ripard 
---
 .../bindings/display/sunxi/sun4i-drm.txt   | 228 +
 1 file changed, 228 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
new file mode 100644
index ..061bc87147a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -0,0 +1,228 @@
+Allwinner A10 Display Pipeline
+==
+
+The Allwinner A10 Display pipeline is composed of several components
+that are going to be documented below:
+
+TV Encoder
+--
+
+The TV Encoder supports the composite and VGA output. It is one end of
+the pipeline.
+
+Required properties:
+ - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
+ - reg: base address and size of memory-mapped region
+ - clocks: the clocks driving the TV encoder
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoint.
+
+TCON
+
+
+The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
+
+Required properties:
+ - compatible: value should be "allwinner,sun4i-a10-tcon".
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the TCON. Three are needed:
+   - 'ahb': the interface clocks
+   - 'tcon-ch0': The clock driving the TCON channel 0
+   - 'tcon-ch1': The clock driving the TCON channel 1
+
+ - clock-names: the clock names mentioned above
+ - clock-output-names: Name of the pixel clock created
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoint, the second one the output
+
+Optional properties:
+  - allwinner,panel: phandle to the panel used in our RGB interface
+
+
+Display Engine Backend
+--
+
+The display engine backend exposes layers and sprites to the
+system.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a13-display-backend
+  - reg: base address and size of the memory-mapped region.
+  - clocks: phandles to the clocks feeding the frontend and backend
+* ahb: the backend interface clock
+* mod: the backend module clock
+* ram: the backend DRAM clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset controllers driving the backend
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoints, the second one the output
+
+Display Engine Frontend
+---
+
+The display engine frontend does formats conversion, scaling,
+deinterlacing and color space conversion.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a13-display-frontend
+  - reg: base address and size of the memory-mapped region.
+  - interrupts: interrupt associated to this IP
+  - clocks: phandles to the clocks feeding the frontend and backend
+* ahb: the backend interface clock
+* mod: the backend module clock
+* ram: the backend DRAM clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset controllers driving the backend
+
+Display Engine Pipeline
+---
+
+The display engine pipeline (and its entry point, since it can be
+either directly the backend or the frontend) is represented as an
+extra node.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a13-display-engine
+  - allwinner,pipelines: list of phandle to the entry points of the
+pipelines (either to the frontend or backend)
+
+Example:
+
+panel: panel {
+   compatible = "olimex,lcd-olinuxino-43-ts";
+};
+
+tve0: tv-encoder@01c0a000 {
+   compatible = "allwinner,sun4i-a10-tv-encoder";
+   reg = <0x01c0a000 0x1000>;
+   clocks = <_gates 34>;
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tve0_in_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_out_tve0>;
+   };
+   };
+};
+
+tcon0: lcd-controller@01c0c000 {
+   compatible = "allwinner,sun4i-a10-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = <44>;
+   clocks = <_gates 36>,
+<_ch0_clk>,
+<_ch1_clk>;
+   clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+   clock-output-names = 

[linux-sunxi] [PATCH v2 19/26] drm: sun4i: Add composite output

[Maxime Ripard]

Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.

Add support for that TV encoder.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/Makefile   |   1 +
 drivers/gpu/drm/sun4i/sun4i_tv.c | 588 +++
 2 files changed, 589 insertions(+)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.c

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index a7c9e7fd5a26..c458b09181fe 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_SUN4I) += sun4i-drm.o
 
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tcon.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
new file mode 100644
index ..4f10f8b6b07c
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -0,0 +1,588 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "sun4i_backend.h"
+#include "sun4i_drv.h"
+#include "sun4i_tcon.h"
+
+#define SUN4I_TVE_EN_REG   0x000
+#define SUN4I_TVE_EN_DAC_MAP_MASK  GENMASK(19, 4)
+#define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
+#define SUN4I_TVE_EN_ENABLEBIT(0)
+
+#define SUN4I_TVE_CFG0_REG 0x004
+#define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
+#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M   BIT(25)
+#define SUN4I_TVE_CFG0_CORE_CONTROL_54MBIT(24)
+#define SUN4I_TVE_CFG0_YC_EN   BIT(17)
+#define SUN4I_TVE_CFG0_COMP_EN BIT(16)
+#define SUN4I_TVE_CFG0_RES(x)  ((x) & 0xf)
+#define SUN4I_TVE_CFG0_RES_480iSUN4I_TVE_CFG0_RES(0)
+#define SUN4I_TVE_CFG0_RES_576iSUN4I_TVE_CFG0_RES(1)
+
+#define SUN4I_TVE_DAC0_REG 0x008
+#define SUN4I_TVE_DAC0_CLOCK_INVERTBIT(24)
+#define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
+#define SUN4I_TVE_DAC0_LUMA_0_4SUN4I_TVE_DAC0_LUMA(3)
+#define SUN4I_TVE_DAC0_CHROMA(x)   (((x) & 3) << 18)
+#define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
+#define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
+#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS  SUN4I_TVE_DAC0_INTERNAL_DAC(3)
+#define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
+
+#define SUN4I_TVE_NOTCH_REG0x00c
+#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x)((4 - (x)) << (dac * 3))
+
+#define SUN4I_TVE_CHROMA_FREQ_REG  0x010
+
+#define SUN4I_TVE_PORCH_REG0x014
+#define SUN4I_TVE_PORCH_BACK(x)((x) << 16)
+#define SUN4I_TVE_PORCH_FRONT(x)   (x)
+
+#define SUN4I_TVE_LINE_REG 0x01c
+#define SUN4I_TVE_LINE_FIRST(x)((x) << 16)
+#define SUN4I_TVE_LINE_NUMBER(x)   (x)
+
+#define SUN4I_TVE_LEVEL_REG0x020
+#define SUN4I_TVE_LEVEL_BLANK(x)   ((x) << 16)
+#define SUN4I_TVE_LEVEL_BLACK(x)   (x)
+
+#define SUN4I_TVE_DAC1_REG 0x024
+#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x)   ((x) << (dac * 8))
+
+#define SUN4I_TVE_DETECT_STA_REG   0x038
+#define SUN4I_TVE_DETECT_STA_DAC(dac)  BIT((dac * 8))
+#define SUN4I_TVE_DETECT_STA_UNCONNECTED   0
+#define SUN4I_TVE_DETECT_STA_CONNECTED 1
+#define SUN4I_TVE_DETECT_STA_GROUND2
+
+#define SUN4I_TVE_CB_CR_LVL_REG0x10c
+#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x)((x) << 8)
+#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x)(x)
+
+#define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
+#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x)   (x)
+
+#define SUN4I_TVE_BURST_WIDTH_REG  0x114
+#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
+#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x)   ((x) << 8)
+#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x)   (x)
+
+#define SUN4I_TVE_CB_CR_GAIN_REG   0x118
+#define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
+#define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
+
+#define SUN4I_TVE_SYNC_VBI_REG 0x11c
+#define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
+#define SUN4I_TVE_SYNC_VBI_VBLANK(x)   (x)
+
+#define SUN4I_TVE_ACTIVE_LINE_REG

[linux-sunxi] [PATCH v2 22/26] ARM: sun5i: r8: Add display blocks to the DTSI

[Maxime Ripard]

The TCON, tv-encoder and display engine backends and frontends are combined
to create our display pipeline.

Add them to the R8 DTSI. It's supposed to be perfectly compatible with the
A10s and A13, but since we haven't tested it on them yet, it's safer to
just enable it on the R8. Eventually, it should be moved to sun5i.dtsi

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-r8.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 691d3de75b35..b3bf91516a80 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -57,4 +57,138 @@
status = "disabled";
};
};
+
+   soc@01c0 {
+   tve0: tv-encoder@01c0a000 {
+   compatible = "allwinner,sun4i-a10-tv-encoder";
+   reg = <0x01c0a000 0x1000>;
+   clocks = <_gates 34>;
+   status = "disabled";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tve0_in_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_out_tve0>;
+   };
+   };
+   };
+
+   tcon0: lcd-controller@01c0c000 {
+   compatible = "allwinner,sun4i-a10-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = <44>;
+   clocks = <_gates 36>,
+<_ch0_clk>,
+<_ch1_clk>;
+   clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+   clock-output-names = "tcon-pixel-clock";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tcon0_in: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   tcon0_in_be0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_tcon0>;
+   };
+   };
+
+   tcon0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   tcon0_out_tve0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_tcon0>;
+   };
+   };
+   };
+   };
+
+   fe0: display-frontend@01e0 {
+   compatible = "allwinner,sun5i-a13-display-frontend";
+   reg = <0x01e0 0x2>;
+   interrupts = <47>;
+   clocks = <_gates 46>, <_fe_clk>,
+<_gates 25>;
+   clock-names = "ahb", "mod",
+ "ram";
+   resets = <_fe_clk>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   fe0_out: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   fe0_out_be0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_in_fe0>;
+   };
+   };
+   };
+   };
+
+   be0: display-backend@01e6 {
+   compatible = "allwinner,sun5i-a13-display-backend";
+   reg = <0x01e6 0x1>;
+   clocks = <_gates 44>, <_be_clk>,
+<_gates 26>;
+   clock-names = "ahb", "mod",
+ "ram";
+   resets = <_be_clk>;
+   status = "disabled";
+
+   

[linux-sunxi] [PATCH v2 15/26] drm/modes: Support modes names on the command line

[Maxime Ripard]

The drm subsystem also uses the video= kernel parameter, and in the
documentation refers to the fbdev documentation for that parameter.

However, that documentation also says that instead of giving the mode using
its resolution we can also give a name. However, DRM doesn't handle that
case at the moment. Even though in most case it shouldn't make any
difference, it might be useful for analog modes, where different standards
might have the same resolution, but still have a few different parameters
that are not encoded in the modes (NTSC vs NTSC-J vs PAL-M for example).

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/drm_crtc.c  |  3 ++-
 drivers/gpu/drm/drm_fb_helper.c |  4 
 drivers/gpu/drm/drm_modes.c | 49 -
 include/drm/drm_modes.h |  1 +
 4 files changed, 41 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 24c5434abd1c..c3267d695e4e 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -846,8 +846,9 @@ static void drm_connector_get_cmdline_mode(struct 
drm_connector *connector)
connector->force = mode->force;
}
 
-   DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n",
+   DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n",
  connector->name,
+ mode->name ? mode->name : "",
  mode->xres, mode->yres,
  mode->refresh_specified ? mode->refresh : 60,
  mode->rb ? " reduced blanking" : "",
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 69cbab5e5c81..fcb7ba796202 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1649,6 +1649,10 @@ struct drm_display_mode *drm_pick_cmdline_mode(struct 
drm_fb_helper_connector *f
prefer_non_interlace = !cmdline_mode->interlace;
 again:
list_for_each_entry(mode, _helper_conn->connector->modes, head) {
+   /* Check (optional) mode name first */
+   if (!strcmp(mode->name, cmdline_mode->name))
+   return mode;
+
/* check width/height */
if (mode->hdisplay != cmdline_mode->xres ||
mode->vdisplay != cmdline_mode->yres)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 5b1921b22dd6..bbb23000eb5b 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1351,7 +1351,7 @@ bool drm_mode_parse_command_line_for_connector(const char 
*mode_option,
   struct drm_cmdline_mode *mode)
 {
const char *name;
-   bool parse_extras = false;
+   bool named_mode = false, parse_extras = false;
unsigned int bpp_off = 0, refresh_off = 0;
unsigned int mode_end = 0;
char *bpp_ptr = NULL, *refresh_ptr = NULL, *extra_ptr = NULL;
@@ -1370,8 +1370,14 @@ bool drm_mode_parse_command_line_for_connector(const 
char *mode_option,
 
name = mode_option;
 
+   /*
+* If the first character is not a digit, then it means that
+* we have a named mode.
+*/
if (!isdigit(name[0]))
-   return false;
+   named_mode = true;
+   else
+   named_mode = false;
 
/* Try to locate the bpp and refresh specifiers, if any */
bpp_ptr = strchr(name, '-');
@@ -1398,12 +1404,16 @@ bool drm_mode_parse_command_line_for_connector(const 
char *mode_option,
parse_extras = true;
}
 
-   ret = drm_mode_parse_cmdline_res_mode(name, mode_end,
- parse_extras,
- connector,
- mode);
-   if (ret)
-   return false;
+   if (named_mode) {
+   strncpy(mode->name, name, mode_end);
+   } else {
+   ret = drm_mode_parse_cmdline_res_mode(name, mode_end,
+ parse_extras,
+ connector,
+ mode);
+   if (ret)
+   return false;
+   }
mode->specified = true;
 
if (bpp_ptr) {
@@ -1431,14 +1441,23 @@ bool drm_mode_parse_command_line_for_connector(const 
char *mode_option,
extra_ptr = refresh_end_ptr;
 
if (extra_ptr) {
-   int remaining = strlen(name) - (extra_ptr - name);
+   if (!named_mode) {
+   int len = strlen(name) - (extra_ptr - name);
 
-   /*
-* We still have characters to process, while
-* we shouldn't have any
-*/
-   if (remaining > 0)
-   return 

[linux-sunxi] [PATCH v2 00/26] drm: Add Allwinner A10 display engine support

[Maxime Ripard]

Hi everyone,

The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.

Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
example), and the output availables will change too (HDMI, composite,
VGA on the A20, none of them on the A13).

On most featured SoCs, it looks like that:

 ++
 |RAM |
 ++
   ||  ||
   v|  |v
 ++ |  | ++
 |Frontend| |  | |Frontend|
 ++ |  | ++
 |  |  | |
 v  |  | v
 ++ |  | ++
 |Backend |<+  +>|Backend |
 ++  ++
 |   |
 v   v
 ++  ++---> LVDS
 |  TCON  |  |  TCON  |---> RGB
 ++  ++
   |   +---+   +---+  |
   |   |   |  |
   v   v   v  v
 ++  ++  ++---> VGA
 | TV Encoder |  |HDMI|  | TV Encoder |---> Composite
 ++  ++  ++

The current code only assumes that there is a single instance of all
the controllers. It also supports only the RGB and Composite
interfaces.

Let me know what you think,
Maxime

Changes from v1:
  - Rebased on top of 4.4

  - Merged the clock drivers for the display and TCON channel 0 clocks
  - Replaced the container_of calls in the display reset clocks to an
inline function
  - Checked the return code of of_clk_parent_fill in the clocks
drivers
  - Checked the return code of of_clk_add_provider in the tcon-ch1 and
PLL3 clocks
  - Added missing clocks headers
  - Created a composite clock unregister function

  - Moved the binding documentation to
Documentation/devicetree/bindings/display
  - Added the clocks binding documentation
  - Added the Olimex vendor to the list of DT vendors
  - Moved to the OF graph representation and the component framework

  - Moved the reset cells count check into the reset framework to
avoid duplicating the code in every xlate implementation.
  - Made the reset_ops const

  - Reworked the DRM cmdline mode parsing code to allow named mode
  - Fixed the TV mode lookup when the mode name is not present (for
example because it was given by the userspace)

  - Made the driver outputs optional (to avoid crashing when a board
doesn't have either a panel or a composite output enabled)
  - Added multiple plane support with transparency
  - Moved the backend registers writes commit in the CRTC atomic_flush
callback
  - Removed the load / unload functions
  - Removed the enabled booleans in my private structure and removed
the implicit call to disable_unused_functions in the DRM core to
push it in the drivers.
  - Fixed a few bitmasks on some bitfields definition
  - Fixed the RGB connector mode validation that was not testing the
right values

Matthias Brugger (1):
  clk: Add regmap support

Maxime Ripard (25):
  reset: Move DT cell size check to the core
  reset: Make reset_control_ops const
  clk: composite: Add unregister function
  clk: sunxi: Add display and TCON0 clocks driver
  clk: sunxi: Add PLL3 clock
  clk: sunxi: Add TCON channel1 clock
  clk: sun5i: add DRAM gates
  ARM: sun5i: dt: Add pll3 and pll7 clocks
  ARM: sun5i: a13: Add display and TCON clocks
  ARM: sun5i: Add DRAM gates
  ARM: sun5i: Add TV encoder gate to the DTSI
  drm/fb_cma_helper: Remove implicit call to disable_unused_functions
  drm/modes: Rewrite the command line parser
  drm/modes: Support modes names on the command line
  drm: Add Allwinner A10 Display Engine support
  drm: sun4i: Add DT bindings documentation
  drm: sun4i: Add RGB output
  drm: sun4i: Add composite output
  drm: sun4i: tv: Add PAL output standard
  drm: sun4i: tv: Add NTSC output standard
  ARM: sun5i: r8: Add display blocks to the DTSI
  ARM: sun5i: chip: Enable the TV Encoder
  devicetree: Add olimex vendor prefix
  drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS
  DO NOT MERGE: ARM: sun5i: chip: Enable the LCD panel

 Documentation/devicetree/bindings/clock/sunxi.txt  |   5 +
 .../display/panel/olimex,lcd-olinuxino-43-ts.txt   |   7 +
 .../bindings/display/sunxi/sun4i-drm.txt   | 228 +++
 .../devicetree/bindings/vendor-prefixes.txt|   1 +
 arch/arm/boot/dts/sun5i-a10s.dtsi  |   7 +-
 arch/arm/boot/dts/sun5i-a13.dtsi   |  46 +-
 

[linux-sunxi] [PATCH v2 03/26] clk: Add regmap support

[Maxime Ripard]

From: Matthias Brugger 

Some devices like SoCs from Mediatek need to use the clock
through a regmap interface.
This patch adds regmap support for the simple multiplexer clock,
the divider clock and the clock gate code.

Signed-off-by: Matthias Brugger 
Signed-off-by: Maxime Ripard 
---
 drivers/clk/Makefile |  1 +
 drivers/clk/clk-divider.c| 68 +---
 drivers/clk/clk-gate.c   | 54 +++--
 drivers/clk/clk-io.c | 48 ++
 drivers/clk/clk-io.h | 22 +++
 drivers/clk/clk-mux.c| 94 +---
 include/linux/clk-provider.h | 54 +++--
 7 files changed, 298 insertions(+), 43 deletions(-)
 create mode 100644 drivers/clk/clk-io.c
 create mode 100644 drivers/clk/clk-io.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 820714c72d36..31a888c0c182 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_COMMON_CLK)  += clk-mux.o
 obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fractional-divider.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gpio.o
+obj-$(CONFIG_COMMON_CLK)   += clk-io.o
 ifeq ($(CONFIG_OF), y)
 obj-$(CONFIG_COMMON_CLK)   += clk-conf.o
 endif
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3ace102a2a0a..1ddb353b3fff 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -18,6 +18,8 @@
 #include 
 #include 
 
+#include "clk-io.h"
+
 /*
  * DOC: basic adjustable divider clock that cannot gate
  *
@@ -142,7 +144,8 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw 
*hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
 
-   val = clk_readl(divider->reg) >> divider->shift;
+   val = clk_io_readl(hw, divider->reg, divider->regmap, divider->offset);
+   val >>= divider->shift;
val &= div_mask(divider->width);
 
return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -354,7 +357,10 @@ static long clk_divider_round_rate(struct clk_hw *hw, 
unsigned long rate,
 
/* if read only, just return current value */
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
-   bestdiv = readl(divider->reg) >> divider->shift;
+   bestdiv = clk_io_readl(hw, divider->reg, divider->regmap,
+  divider->offset);
+
+   bestdiv >>= divider->shift;
bestdiv &= div_mask(divider->width);
bestdiv = _get_div(divider->table, bestdiv, divider->flags,
divider->width);
@@ -400,12 +406,16 @@ static int clk_divider_set_rate(struct clk_hw *hw, 
unsigned long rate,
 
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider->width) << (divider->shift + 16);
+   val |= value << divider->shift;
+   clk_io_writel(hw, divider->reg, divider->regmap,
+ divider->offset, val);
} else {
-   val = clk_readl(divider->reg);
-   val &= ~(div_mask(divider->width) << divider->shift);
+   u32 mask = div_mask(divider->width) << divider->shift;
+
+   val = value << divider->shift;
+   clk_io_update_bits(hw, divider->reg, divider->regmap,
+  divider->offset, mask, val);
}
-   val |= value << divider->shift;
-   clk_writel(val, divider->reg);
 
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
@@ -424,9 +434,9 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
 
 static struct clk *_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
-   void __iomem *reg, u8 shift, u8 width,
-   u8 clk_divider_flags, const struct clk_div_table *table,
-   spinlock_t *lock)
+   void __iomem *reg, struct regmap *regmap, u32 offset,
+   u8 shift, u8 width, u8 clk_divider_flags,
+   const struct clk_div_table *table, spinlock_t *lock)
 {
struct clk_divider *div;
struct clk *clk;
@@ -451,7 +461,12 @@ static struct clk *_register_divider(struct device *dev, 
const char *name,
init.num_parents = (parent_name ? 1 : 0);
 
/* struct clk_divider assignments */
-   div->reg = reg;
+   if (flags & CLK_USE_REGMAP)
+   div->regmap = regmap;
+   else
+   div->reg = reg;
+
+   div->offset = offset;
div->shift = shift;
div->width = width;
div->flags = clk_divider_flags;
@@ -485,8 +500,8 @@ struct clk *clk_register_divider(struct device *dev, const 
char *name,
void __iomem *reg, u8 shift, u8 width,
u8 

[linux-sunxi] [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions

[Maxime Ripard]

The drm_fbdev_cma_init function always calls the
drm_helper_disable_unused_functions. Since it's part of the usual probe
process, all the drivers using that helper will end up having their encoder
and CRTC disable functions called at probe if their device has not been
reported as enabled.

This could be fixed by reading out from the registers the current state of
the device if it is enabled, but even that will not handle the case where
the device is actually disabled.

Moreover, the drivers using the atomic modesetting expect that their enable
and disable callback to be called when the device is already enabled or
disabled (respectively).

We can however fix this issue by moving the call to
drm_helper_disable_unused_functions out of drm_fbdev_cma_init and make the
drivers needing it (all the drivers calling drm_fbdev_cma_init and not
using the atomic modesetting) explicitly call it.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/drm_fb_cma_helper.c | 3 ---
 drivers/gpu/drm/imx/imx-drm-core.c  | 1 +
 drivers/gpu/drm/sti/sti_drv.c   | 1 +
 drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 +
 4 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c 
b/drivers/gpu/drm/drm_fb_cma_helper.c
index c19a62561183..daa98d881142 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -348,9 +348,6 @@ struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device 
*dev,
 
}
 
-   /* disable all the possible outputs/crtcs before entering KMS mode */
-   drm_helper_disable_unused_functions(dev);
-
ret = drm_fb_helper_initial_config(helper, preferred_bpp);
if (ret < 0) {
dev_err(dev->dev, "Failed to set initial hw configuration.\n");
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c 
b/drivers/gpu/drm/imx/imx-drm-core.c
index 7b990b4e96d2..e1db57791fc9 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -312,6 +312,7 @@ static int imx_drm_driver_load(struct drm_device *drm, 
unsigned long flags)
dev_warn(drm->dev, "Invalid legacyfb_depth.  Defaulting to 
16bpp\n");
legacyfb_depth = 16;
}
+   drm_helper_disable_unused_functions(drm);
imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
drm->mode_config.num_crtc, MAX_CRTC);
if (IS_ERR(imxdrm->fbhelper)) {
diff --git a/drivers/gpu/drm/sti/sti_drv.c b/drivers/gpu/drm/sti/sti_drv.c
index 1469987949d8..506b5626f3ed 100644
--- a/drivers/gpu/drm/sti/sti_drv.c
+++ b/drivers/gpu/drm/sti/sti_drv.c
@@ -160,6 +160,7 @@ static int sti_load(struct drm_device *dev, unsigned long 
flags)
 
drm_mode_config_reset(dev);
 
+   drm_helper_disable_unused_functions(dev);
drm_fbdev_cma_init(dev, 32,
   dev->mode_config.num_crtc,
   dev->mode_config.num_connector);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c 
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 876cad58b1f9..24be31d69701 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -294,6 +294,7 @@ static int tilcdc_load(struct drm_device *dev, unsigned 
long flags)
break;
}
 
+   drm_helper_disable_unused_functions(dev);
priv->fbdev = drm_fbdev_cma_init(dev, bpp,
dev->mode_config.num_crtc,
dev->mode_config.num_connector);
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 24/26] devicetree: Add olimex vendor prefix

[Maxime Ripard]

Olimex is an open source hardware boards vendors based in Bulgaria.

Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 55df1d444e9f..de4eb72b3adc 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -161,6 +161,7 @@ nuvoton Nuvoton Technology Corporation
 nvidia NVIDIA
 nxpNXP Semiconductors
 okaya  Okaya Electric America, Inc.
+olimex Olimex
 onnn   ON Semiconductor Corp.
 opencores  OpenCores.org
 option Option NV
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 10/26] ARM: sun5i: a13: Add display and TCON clocks

[Maxime Ripard]

Enable the display and TCON (channel 0 and channel 1) clocks that are going
to be needed to drive the display engine, tcon and TV encoders.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 38 +-
 arch/arm/boot/dts/sun5i-r8.dtsi  |  5 +++--
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index d910d3a6c41c..9669b03f20f3 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -61,7 +61,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>;
+   clocks = <_gates 36>, <_gates 44>, <_be_clk>,
+<_ch0_clk>;
status = "disabled";
};
};
@@ -149,6 +150,41 @@
 "apb1_i2c2", "apb1_uart1",
 "apb1_uart3";
};
+
+   de_be_clk: clk@01c20104 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20104 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-be";
+   };
+
+   de_fe_clk: clk@01c2010c {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c2010c 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-fe";
+   };
+
+   tcon_ch0_clk: clk@01c20118 {
+   #clock-cells = <0>;
+   #reset-cells = <1>;
+   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+   reg = <0x01c20118 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon-ch0-sclk";
+   };
+
+   tcon_ch1_clk: clk@01c2012c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+   reg = <0x01c2012c 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon-ch1-sclk";
+   };
};
 
soc@01c0 {
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 0ef865601ac9..b1e4e0170d51 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -51,8 +51,9 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
-   clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>;
+   clocks = <_gates 34>, <_gates 36>,
+<_gates 44>, <_be_clk>,
+<_ch1_clk>;
status = "disabled";
};
};
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 04/26] clk: composite: Add unregister function

[Maxime Ripard]

The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.

While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.

Add a clk_unregister_composite function to fix this.

Signed-off-by: Maxime Ripard 
---
 drivers/clk/clk-composite.c  | 15 +++
 include/linux/clk-provider.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 4735de0660cc..f4c38f209594 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -288,3 +288,18 @@ err:
kfree(composite);
return clk;
 }
+
+void clk_unregister_composite(struct clk *clk)
+{
+   struct clk_composite *composite;
+   struct clk_hw *hw;
+
+   hw = __clk_get_hw(clk);
+   if (!hw)
+   return;
+
+   composite = to_clk_composite(hw);
+
+   clk_unregister(clk);
+   kfree(composite);
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 0c55a37cf8f7..76c34a9622db 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -632,6 +632,7 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
unsigned long flags);
+void clk_unregister_composite(struct clk *clk);
 
 /***
  * struct clk_gpio_gate - gpio gated clock
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 14/26] drm/modes: Rewrite the command line parser

[Maxime Ripard]

Rewrite the command line parser in order to get away from the state machine
parsing the video mode lines.

Hopefully, this will allow to extend it more easily to support named modes
and / or properties set directly on the command line.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/drm_modes.c | 308 +++-
 1 file changed, 191 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index cd74a0953f42..5b1921b22dd6 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -30,6 +30,7 @@
  * authorization from the copyright holder(s) and author(s).
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -1199,6 +1200,131 @@ void drm_mode_connector_list_update(struct 
drm_connector *connector,
 }
 EXPORT_SYMBOL(drm_mode_connector_list_update);
 
+static int drm_mode_parse_cmdline_bpp(const char *str, char **end_ptr,
+ struct drm_cmdline_mode *mode)
+{
+   if (str[0] != '-')
+   return -EINVAL;
+
+   mode->bpp = simple_strtol(str + 1, end_ptr, 10);
+   mode->bpp_specified = true;
+
+   return 0;
+}
+
+static int drm_mode_parse_cmdline_refresh(const char *str, char **end_ptr,
+ struct drm_cmdline_mode *mode)
+{
+   if (str[0] != '@')
+   return -EINVAL;
+
+   mode->refresh = simple_strtol(str + 1, end_ptr, 10);
+   mode->refresh_specified = true;
+
+   return 0;
+}
+
+static int drm_mode_parse_cmdline_extra(const char *str, int length,
+   struct drm_connector *connector,
+   struct drm_cmdline_mode *mode)
+{
+   int i;
+
+   for (i = 0; i < length; i++) {
+   switch (str[i]) {
+   case 'i':
+   mode->interlace = true;
+   break;
+   case 'm':
+   mode->margins = true;
+   break;
+   case 'D':
+   if (mode->force != DRM_FORCE_UNSPECIFIED)
+   return -EINVAL;
+
+   if ((connector->connector_type != 
DRM_MODE_CONNECTOR_DVII) &&
+   (connector->connector_type != 
DRM_MODE_CONNECTOR_HDMIB))
+   mode->force = DRM_FORCE_ON;
+   else
+   mode->force = DRM_FORCE_ON_DIGITAL;
+   break;
+   case 'd':
+   if (mode->force != DRM_FORCE_UNSPECIFIED)
+   return -EINVAL;
+
+   mode->force = DRM_FORCE_OFF;
+   break;
+   case 'e':
+   if (mode->force != DRM_FORCE_UNSPECIFIED)
+   return -EINVAL;
+
+   mode->force = DRM_FORCE_ON;
+   break;
+   default:
+   return -EINVAL;
+   }
+   }
+
+   return 0;
+}
+
+static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int 
length,
+  bool extras,
+  struct drm_connector *connector,
+  struct drm_cmdline_mode *mode)
+{
+   bool rb = false, cvt = false;
+   int xres = 0, yres = 0;
+   int remaining, i;
+   char *end_ptr;
+
+   xres = simple_strtol(str, _ptr, 10);
+
+   if (end_ptr[0] != 'x')
+   return -EINVAL;
+   end_ptr++;
+
+   yres = simple_strtol(end_ptr, _ptr, 10);
+
+   remaining = length - (end_ptr - str);
+   if (remaining < 0)
+   return -EINVAL;
+
+   for (i = 0; i < remaining; i++) {
+   switch (end_ptr[i]) {
+   case 'M':
+   cvt = true;
+   break;
+   case 'R':
+   rb = true;
+   break;
+   default:
+   /*
+* Try to pass that to our extras parsing
+* function to handle the case where the
+* extras are directly after the resolution
+*/
+   if (extras) {
+   int ret = drm_mode_parse_cmdline_extra(end_ptr 
+ i,
+  1,
+  
connector,
+  mode);
+   if (ret)
+   return ret;
+   } else {
+   return -EINVAL;
+   }
+   }
+   }
+
+   mode->xres 

[linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support

[Maxime Ripard]

The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.

Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/Kconfig   |   2 +
 drivers/gpu/drm/Makefile  |   3 +-
 drivers/gpu/drm/sun4i/Kconfig |  14 +
 drivers/gpu/drm/sun4i/Makefile|   9 +
 drivers/gpu/drm/sun4i/sun4i_backend.c | 321 +++
 drivers/gpu/drm/sun4i/sun4i_backend.h | 160 ++
 drivers/gpu/drm/sun4i/sun4i_crtc.c| 120 
 drivers/gpu/drm/sun4i/sun4i_crtc.h|  30 ++
 drivers/gpu/drm/sun4i/sun4i_drv.c | 325 +++
 drivers/gpu/drm/sun4i/sun4i_drv.h |  30 ++
 drivers/gpu/drm/sun4i/sun4i_framebuffer.c |  54 
 drivers/gpu/drm/sun4i/sun4i_framebuffer.h |  19 ++
 drivers/gpu/drm/sun4i/sun4i_layer.c   | 160 ++
 drivers/gpu/drm/sun4i/sun4i_layer.h   |  30 ++
 drivers/gpu/drm/sun4i/sun4i_tcon.c| 497 ++
 drivers/gpu/drm/sun4i/sun4i_tcon.h| 175 +++
 16 files changed, 1948 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sun4i/Kconfig
 create mode 100644 drivers/gpu/drm/sun4i/Makefile
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_backend.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_backend.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_crtc.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_crtc.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_drv.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_drv.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_framebuffer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_framebuffer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index c4bf9a1cf4a6..ea029f1534fe 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -239,6 +239,8 @@ source "drivers/gpu/drm/rcar-du/Kconfig"
 
 source "drivers/gpu/drm/shmobile/Kconfig"
 
+source "drivers/gpu/drm/sun4i/Kconfig"
+
 source "drivers/gpu/drm/omapdrm/Kconfig"
 
 source "drivers/gpu/drm/tilcdc/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 1e9ff4c3e3db..d8ea25dabca9 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -1,4 +1,4 @@
-#
+
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
@@ -62,6 +62,7 @@ obj-$(CONFIG_DRM_ARMADA) += armada/
 obj-$(CONFIG_DRM_ATMEL_HLCDC)  += atmel-hlcdc/
 obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
 obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
+obj-$(CONFIG_DRM_SUN4I) += sun4i/
 obj-$(CONFIG_DRM_OMAP) += omapdrm/
 obj-y  += tilcdc/
 obj-$(CONFIG_DRM_QXL) += qxl/
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
new file mode 100644
index ..99510e64e91a
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -0,0 +1,14 @@
+config DRM_SUN4I
+   tristate "DRM Support for Allwinner A10 Display Engine"
+   depends on DRM && ARM
+   depends on ARCH_SUNXI || COMPILE_TEST
+   select DRM_GEM_CMA_HELPER
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_PANEL
+   select REGMAP_MMIO
+   select VIDEOMODE_HELPERS
+   help
+ Choose this option if you have an Allwinner SoC with a
+ Display Engine. If M is selected the module will be called
+ sun4i-drm.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
new file mode 100644
index ..7b0e83bae867
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -0,0 +1,9 @@
+sun4i-drm-y += sun4i_crtc.o
+sun4i-drm-y += sun4i_drv.o
+sun4i-drm-y += sun4i_framebuffer.o
+sun4i-drm-y += sun4i_layer.o
+
+obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o
+
+obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i_tcon.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
new file mode 100644
index ..082fef60dd3e
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */

[linux-sunxi][PATCH v3 3/5] ARM: dts: sun7i: Add Itead Ibox support

[codekipper]

From: Marcus Cooper 

The Itead Ibox is a multi board device based on the Allwinner A20 SoC.
It contains the A20 Itead Core module and a base board for the external
interfaces.

The core module comes with 4GB NAND and 1GB DDR RAM.

The base board to which the core board is connected provides 3 USB 2.0 Host
ports, 1 USB 2.0 OTG, 1 uSD slot, 10/100 Ethernet port, HDMI, IR receiver,
SPDIF and a 32-pin GPIO header. This header expands the features of core
board by exposing the VGA pins, audio In/Out pins, SATA, SPI, I2C, UARTS,
USB-OTG and power.

Signed-off-by: Marcus Cooper 
---
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 124 +
 2 files changed, 125 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun7i-a20-itead-ibox.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index da910b2..5c5e8f4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -638,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
+   sun7i-a20-itead-ibox.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-m3.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts 
b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
new file mode 100644
index 000..66b8dec
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2015 - Marcus Cooper 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20-itead-core.dtsi"
+
+/ {
+   model = "Itead Ibox A20";
+   compatible = "itead,itead_ibox_a20", "allwinner,sun7i-a20";
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_itead_core>;
+
+   green {
+   label = "itead_core:green:usr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   blue {
+   label = "itead_core:blue:usr";
+   gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+   };
+};
+
+ {
+   target-supply = <_ahci_5v>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_mii_a>;
+   phy = <>;
+   phy-mode = "mii";
+   status = "okay";
+
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rx_pins_a>;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>, <_cd_pin_reference_design>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <4>;
+   cd-gpios = < 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+   cd-inverted;
+   status = "okay";

[linux-sunxi][PATCH v3 4/5] ARM: dts: sun4i: Add Itead A10 Core support

[codekipper]

From: Marcus Cooper 

The A10 Itead Core module comes with 4GB NAND and 1GB DDR RAM. All of the
I/O interfaces are exposed via 4 groups of 2*30 1mm pitched female headers.

Signed-off-by: Marcus Cooper 
---
 arch/arm/boot/dts/sun4i-a10-itead-core.dtsi | 86 +
 1 file changed, 86 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun4i-a10-itead-core.dtsi

diff --git a/arch/arm/boot/dts/sun4i-a10-itead-core.dtsi 
b/arch/arm/boot/dts/sun4i-a10-itead-core.dtsi
new file mode 100644
index 000..97f653a
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-itead-core.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 - Marcus Cooper 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun4i-a10.dtsi"
+#include "sunxi-itead-core-common.dtsi"
+
+ {
+   cpu-supply = <_dcdc2>;
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+
+   axp209: pmic@34 {
+   reg = <0x34>;
+   interrupts = <0>;
+   };
+};
+
+#include "axp209.dtsi"
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-int-dll";
+};
+
+_ldo1 {
+   regulator-name = "vdd-rtc";
+};
+
+_ldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "avcc";
+};
-- 
2.7.0

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi][PATCH v3 1/5] ARM: dts: sunxi: Add sunxi-itead-core-common.dtsi

[codekipper]

From: Marcus Cooper 

Itead have a core module board that can be populated with either
an Allwinner A10 or A20 SoC. This patch creates a common dtsi
which these boards can use.

Signed-off-by: Marcus Cooper 
---
 arch/arm/boot/dts/sunxi-itead-core-common.dtsi | 99 ++
 1 file changed, 99 insertions(+)
 create mode 100644 arch/arm/boot/dts/sunxi-itead-core-common.dtsi

diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi 
b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi
new file mode 100644
index 000..0074f7b
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2015 - Marcus Cooper 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+_usb1_vbus {
+   status = "okay";
+};
+
+_usb2_vbus {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
+
+ {
+   usb1_vbus-supply = <_usb1_vbus>;
+   usb2_vbus-supply = <_usb2_vbus>;
+   status = "okay";
+};
-- 
2.7.0

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH] clk: sunxi: Fix mod0 clock calculation to return stable results and check divisor size limits

[Marcus Weseloh]

Hi,

2016-01-13 12:18 GMT+01:00 Maxime Ripard :
> Sorry for the reviewing delay.
No problem at all, thanks for the review!

> On Mon, Dec 28, 2015 at 06:31:32PM +0100, Marcus Weseloh wrote:
>> This patch fixes some problems in the mod0 clock calculation. It has
>> the potential to break stuff, as the issues explained below had the
>> effect that clk_set_rate would always return successfully, sometimes
>> setting a frequency that is higher than the requested value.
>
> That's actually the expected behaviour of clk_set_rate.
>
> clk_set_rate is supposed to adjust the given clock rate to something
> that the clock drivers seems fit. It should only return an error in a
> case where you can't change the rate at all (because you didn't pass a
> valid struct clk pointer, because changing the rate would violate some
> clock flags, etc.). Otherwise, clk_set_rate should succeed.
>
> By returning an error code the clock is higher than the one passed,
> you violate that expectation, especially since that is relative to the
> clock you passed.
>
> It makes sense in your case to never exceed the given rate, it might
> not for a different clock in the tree, or even for a different
> instance of the same clock. For example, you could very well have
> another case in your system where you should not have rates set that
> are below the one given because that would prevent the consumer
> device to be usable.
>
> This is why the adjustment is left to the clock driver, and is not
> enforced by the framework itself, simply because the framework has no
> idea how you want to round your clock rate on that particular clock in
> your system.

I understand now, thanks a lot for the good explanation! So my
thinking is wrong for the general case of the clock framework itself,
and that actually makes a lot of sense.

But the clk_factors_determine_rate function in
drivers/clk/sunxi/clk-factors.c works on the assumption that the
returned rate must be less or equal to the requested rate. At least
that is what the code in that function tries to do. That the mod0
factor calculation doesn't check the m and div variables for overflow
undermines the intended behaviour, as it "lies" about the frequencies
that the hardware can support. And for very low frequencies below
80kHz, clk_set_rate does currently return -EINVAL. There are even
cases when it results in a division by zero error, for example if you
request a rate of 94kHz from a 24Mhz parent (2400 / 94000 =
255,32, rounded up to 256 = 0 on the u8 variable).

Now I'm unsure what to do here... If the clock driver should only
return an error in real error cases and not when the requested
frequency isn't reachable, then clk_factors_determine_rate needs to be
changed as well?

>> Code that "accidentally worked" because of this might fail after
>> applying this patch.
>>
>> The problems in detail:
>>
>> 1. If a very low frequency is requested from a high parent clock, the
>> divisors "div" and "calcm" might be > 255. This patch changes the type
>> of both variables to unsigned int, because the silent cast to u8 will
>> result in invalid frequencies and register values.
>>
>> 2. The width of the "m" divisor in the clock control registers is only
>> 4 bit, but that limitation is not checked when calculating the divisor
>> and the resulting frequency. This patch adds a check that m never
>> exceeds the field width.
>>
>> 3. During a call to clk_set_rate, the sun4i_a10_get_mod0_factors
>> function is called multiple times: first to find the best parent and
>> frequency, then again to calculate the p and m divisors, passing the
>> frequencies returned by the previous call(s). In certain cases
>> those chained calls do not result in the best frequency choice.
>
> You know the drill by now :)
>
> You're fixing three different issues, please send three different
> patches.

Yes, thanks for the reminder :-) I thought about it just as I hit the
"send" button, but it was too late then.

>> An example:
>> parent_rate = 24Mhz, freq = 1.4Mhz results in p=1, m=9, freq=133,
>> (which gets rounded down to 133).
>> Calling the function again with parent_rate = 24Mhz and freq = 133
>> results in p=1, m=10, freq=120.
>>
>> Rounding up the returned frequency removes this problem.
>>
>> Signed-off-by: Marcus Weseloh 
>> ---
>>  drivers/clk/sunxi/clk-mod0.c | 7 +--
>>  1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
>> index d167e1e..d03f099 100644
>> --- a/drivers/clk/sunxi/clk-mod0.c
>> +++ b/drivers/clk/sunxi/clk-mod0.c
>> @@ -31,7 +31,8 @@
>>  static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
>>  u8 *n, u8 *k, u8 *m, u8 *p)
>>  {
>> - u8 div, calcm, calcp;
>> + unsigned int div, calcm;
>> + u8 calcp;
>>
>>   /* These clocks can only divide, so we will never be able to achieve
>>

[linux-sunxi] Re: orangepi mirror

[Benjamin Henrion]

On Thu, Jan 14, 2016 at 8:40 AM, Thomas Kaiser
 wrote:
> Benjamin Henrion wrote:
>
>> The few images I tested were full of bugs and needed a kernel update
>> to get latest Loboris.eu version.
>
>
> Maybe it's a good idea to point out that while loboris' images/settings fix
> many things they're also responsible for worsening the overheating problems
> the H3 is blamed for. Please have a look at:
>
> http://www.cnx-software.com/2015/09/01/getting-started-with-orange-pi-pc-pi-2-and-pi-plus-development-boards/#comment-521235
>
> Maybe you can add this as a readme.txt?

I will add a README.TXT and a wiki page with my findings :-)

I have a OPI-2 (v1.0) and a OPI-PC (v1.2).

The naming convention (OrangePi 2, Plus, Minus, etc...) is just a
nightmare, especially to understand which image is compatible with
which, considering that the SOC is the same for all.

Orangepi.org has also an horrible website with a big rolling banner on
the top of the page, which is confusing even more visitors when you
want to know which board has what.

I went through different states yesterday:

1. Broken USB
2. Broken ethernet
3. Broken wifi support

But I am still stuck at having the 3 properly working, even with
Loboris latest kernel updated with this script:

http://filez.zoobab.com/allwinner/orangepi/mega/update_kernel.sh

which installs this kernel:

$ cat /proc/version
Linux version 3.4.39-01-lobo (boris@UbuntuMate) (gcc version 4.6.3
20120201 (prerelease) (crosstool-NG linaro-1.13.1-2012.02-20120222 -
Linaro GCC 2012.02) ) #1 SMP PREEMPT Sun Oct 25 14:46:41 CET 2015

This kernel has working wifi+ethernet, but the USB is broken.

Most of those images seems to have been generated on the 30st of
August, and with a kernel that had broken USB+Ethernet.

--
Benjamin Henrion 
FFII Brussels - +32-484-566109 - +32-2-3500762
"In July 2005, after several failed attempts to legalise software
patents in Europe, the patent establishment changed its strategy.
Instead of explicitly seeking to sanction the patentability of
software, they are now seeking to create a central European patent
court, which would establish and enforce patentability rules in their
favor, without any possibility of correction by competing courts or
democratically elected legislators."

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi][PATCH v3 0/5] ARM: dt: sunxi: Add Itead Ibox support

[codekipper]

From: Marcus Cooper 

Hi All,

this patch series is an extension of the initial patch delivery for the
Itead Ibox as found here
https://groups.google.com/d/msg/linux-sunxi/GR_co3ObW8s/0BTPQljmAAAJ.

There seems to be a few Itead variants out there based on their A10/A20
core module and this patch series attempts to organise the device tree
files with some consideration that these variants may be added later.

I've also converted the A10 Itead Iteaduino dts to use these common files.
As I don't have this board to verify the changes I simply compared the
output of the fdtdump before and after applying these patches. The only
difference was the addition of codec support and a reduction to the dcdc2
max voltage.

BR,
CK

---
Changes since v2:
- removed duplicate naming
- moved enabling of some peripherals to board level.

Changes since v1:
- Added audio codec.
- Seperated into individual patches
- added Itead A10 core dtsi
- modified sun4i-a10-itead-iteaduino-plus.dts to use itead common core dtsi


Marcus Cooper (5):
  ARM: dts: sunxi: Add sunxi-itead-core-common.dtsi
  ARM: dts: sun7i: Add Itead A20 Core support
  ARM: dts: sun7i: Add Itead Ibox support
  ARM: dts: sun4i: Add Itead A10 Core support
  ARM: dts: sun4i: Itead Iteaduino to use common code

 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/sun4i-a10-itead-core.dtsi|  86 ++
 .../boot/dts/sun4i-a10-itead-iteaduino-plus.dts|  93 +---
 arch/arm/boot/dts/sun7i-a20-itead-core.dtsi|  87 +++
 arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 124 +
 arch/arm/boot/dts/sunxi-itead-core-common.dtsi |  99 
 6 files changed, 399 insertions(+), 91 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun4i-a10-itead-core.dtsi
 create mode 100644 arch/arm/boot/dts/sun7i-a20-itead-core.dtsi
 create mode 100644 arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
 create mode 100644 arch/arm/boot/dts/sunxi-itead-core-common.dtsi

-- 
2.7.0

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi][PATCH v3 5/5] ARM: dts: sun4i: Itead Iteaduino to use common code

[codekipper]

From: Marcus Cooper 

Convert the Itead Iteaduino A10 to use the new common itead core dtsi.

Signed-off-by: Marcus Cooper 
---
 .../boot/dts/sun4i-a10-itead-iteaduino-plus.dts| 93 +-
 1 file changed, 2 insertions(+), 91 deletions(-)

diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts 
b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
index 985e155..b84eca3 100644
--- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright 2015 Josef Gajdusek 
+ * Copyright 2015 - Marcus Cooper 
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -41,23 +42,11 @@
  */
 
 /dts-v1/;
-#include "sun4i-a10.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include 
-#include 
+#include "sun4i-a10-itead-core.dtsi"
 
 / {
model = "Iteaduino Plus A10";
compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10";
-
-   aliases {
-   serial0 = 
-   };
-
-   chosen {
-   stdout-path = "serial0:115200n8";
-   };
 };
 
  {
@@ -65,18 +54,6 @@
status = "okay";
 };
 
- {
-   cpu-supply = <_dcdc2>;
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
@@ -88,17 +65,6 @@
status = "okay";
 };
 
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins_a>;
-   status = "okay";
-
-   axp209: pmic@34 {
-   reg = <0x34>;
-   interrupts = <0>;
-   };
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
@@ -135,68 +101,13 @@
status = "okay";
 };
 
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
 _ahci_5v {
status = "okay";
 };
 
-#include "axp209.dtsi"
-
-_dcdc2 {
-   regulator-always-on;
-   regulator-min-microvolt = <100>;
-   regulator-max-microvolt = <145>;
-   regulator-name = "vdd-cpu";
-};
-
-_dcdc3 {
-   regulator-always-on;
-   regulator-min-microvolt = <100>;
-   regulator-max-microvolt = <140>;
-   regulator-name = "vdd-int-dll";
-};
-
-_ldo1 {
-   regulator-name = "vdd-rtc";
-};
-
-_ldo2 {
-   regulator-always-on;
-   regulator-min-microvolt = <300>;
-   regulator-max-microvolt = <300>;
-   regulator-name = "avcc";
-};
-
-_usb1_vbus {
-   status = "okay";
-};
-
-_usb2_vbus {
-   status = "okay";
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>,
<_cs0_pins_a>;
status = "okay";
 };
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins_a>;
-   status = "okay";
-};
-
- {
-   usb1_vbus-supply = <_usb1_vbus>;
-   usb2_vbus-supply = <_usb2_vbus>;
-   status = "okay";
-};
-- 
2.7.0

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi][PATCH v3 2/5] ARM: dts: sun7i: Add Itead A20 Core support

[codekipper]

From: Marcus Cooper 

The A20 Itead Core module comes with 4GB NAND and 1GB DDR RAM. All of the
I/O interfaces are exposed via 4 groups of 2*30 1mm pitched female headers.

Signed-off-by: Marcus Cooper 
---
 arch/arm/boot/dts/sun7i-a20-itead-core.dtsi | 87 +
 1 file changed, 87 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun7i-a20-itead-core.dtsi

diff --git a/arch/arm/boot/dts/sun7i-a20-itead-core.dtsi 
b/arch/arm/boot/dts/sun7i-a20-itead-core.dtsi
new file mode 100644
index 000..db8c0f9
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-itead-core.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2015 - Marcus Cooper 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun7i-a20.dtsi"
+#include "sunxi-itead-core-common.dtsi"
+
+ {
+   cpu-supply = <_dcdc2>;
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+
+   axp209: pmic@34 {
+   reg = <0x34>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   };
+};
+
+#include "axp209.dtsi"
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-int-dll";
+};
+
+_ldo1 {
+   regulator-name = "vdd-rtc";
+};
+
+_ldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "avcc";
+};
-- 
2.7.0

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: patch for I2S test on 'mripard' A20 wip-i2s branch

[martijn]

On Wednesday, January 13, 2016 at 6:49:03 AM UTC+1, Andrea Venturi wrote:
> hello,
> 
> 
> i've tested the experimental github branch for I2S DAI mainline linux driver 
> on:
>  https://github.com/mripard/linux/tree/sunxi/wip/a20-i2s
> 
> 
> 
> my HW setup actually is:
> an Olimex A20-SOM with EValuation Board: 
> https://www.olimex.com/Products/SOM/A20/A20-SOM-EVB/the Audio DAC is a 
> PCM5102x based low cost device: 
> http://www.aliexpress.com/item/PCM5102-DAC-Decoder-I2S-Player-Assembled-Board-32Bit-384K-Beyond-ES9023-PCM1794/32579339671.html
> let me state in advance i've no economic interest at all in these specific 
> vendors or products! :-)
> 
> 
> BTW the PCM510x DAC is a pretty simple device with no cfg at all on the 
> software side (there's no I2C or SPI bus [*]) and it does need only three 
> wires on the I2S side (BITCLK, LRCLK and DATAIN) as the local system clock is 
> "generated" internally with some kind of PLL.
> 
> 
> so, as technically speaking, the "simple sound card" need two entries for the 
> two "legs" (DAI+CODEC) of an audio connection, i had to put in place a pretty 
> simple "stub" driver of the PCM codec (patch 0001); this PCM510x codec driver 
> needs to be enabled in kernel config for module creation. (also the I2S sunxi 
> DAI has to be enabled there)
> 
> 
> then in patch 0004 there are the DTS entries for the A20-OLIMEX-SOM EVB 
> entries enabling the I2S DAI based audio card (the patched DTS enables also 
> the analog audio codec here)
> 
> 
> at this point, as per my tests,we could alreay have a bitstream when doing a 
> playback with aplay but with wrong clocks (slower) on BITCLK and LRCLK pins. 
> 
> 
> AFAICS this is happening for two reasons:
> the 4 clock (PLL2x1 .. PLL2x8) entries in DTSI about i2s0 on the clk 
> compatible = "allwinner,sun4i-a10-mod1-clk" are reversed , look at others clk 
> entries for spdif/ac97 to see they do not match (patch 0002)
> the mod1_clk clock composite driver was not able to set parent rate for a 
> missing flag (patch 0003), thanx to mripard for the hint on IRC. 
> after these four patches applied, the playback is working "flawlessly" (a 
> part of some "scratching frames" in the playback start.. some kind of audio 
> muting would be useful at start).
> 
> 
> a (not so subtle) issue come to mind if both analog audio codec and I2S DAI 
> try to playback two streams with incompatible sample rate (44100 and 48000 
> for example), i suppose the latest starting would reprogram the PLL2 in a way 
> not compatible with the first one. some kind of locking preventing this issue 
> would be needed in the long run.. 
> 
> 
> i post this mail for further consideration and tests from the linux-sunxi 
> community; as i've been told by Maxime Ripard, we are still far from having a 
> mainlining of this driver because it would need a proper submission to 
> relevant linux group of interests and maintainers (Alsa and ARM i suppose), 
> and that's something i'm actually not really ready to properly tackle! :-)
> 
> 
> me, i'm actually considering to test and implement also the "I2S slave mode" 
> where clocks come from "codec" (with a different HW codec, of course and 
> report if something useful comes out..)
> 
> 
> hope this is useful for someone, anyway. that's all, bye
> 
> 
> Andrea
> 
> 
> [*] technically speaking there's a "jumper" on the DAC board (selecting from 
> "I2S" formatted to LEFT justified I2S data) that is "statically" forced to 
> one level (actually i tested I2S only) and i suppose it could be configured 
> with an additional GPIO line between SOC and DAC board as selectable on the 
> fly at startup or maybe runtime too, but i don't see it a compelling or 
> missing feature at all. who carez! :-)

What would be the best way tot test this for me ?

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: orangepi mirror

[Thomas Kaiser]

Benjamin Henrion wrote:

> The naming convention (OrangePi 2, Plus, Minus, etc...) is just a
> nightmare, especially to understand which image is compatible with
> which, considering that the SOC is the same for all.

And it won't get better with the new H3 based Orange Pi One/Lite ;)

But loboris' images do not differentiate between the different boards
at all. It's necessary to run update_kernel.sh that exchanges kernel
and script.bin (and for the latter you can decide from a few fixed
resolutions and whether you use a HDMI-DVI converter or not ‹ all this
stuff is defined in script.bin)

> I went through different states yesterday:
> 
> 1. Broken USB
> 2. Broken ethernet
> 3. Broken wifi support

Ethernet/USB should work after running update_kernel.sh and choosing
the correct board (if you're using a really old image from him there
might be a few manual steps necessary). Regarding Wi-Fi check whether
the necessary module is loaded and then execute:

sudo nmcli -a d wifi connect

See

http://www.orangepi.org/orangepibbsen/forum.php?mod=viewthread=342

BTW: To use any display resolution (currently no EDID detection in the
H3 3.4 kernel) I relied on fbset in the past: Install the package,
define/choose a resolution in /etc/fb.modes and set this with fbset at
boot.

Regards,

Thomas


-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] ATTN Maxime: ASoC: sun4i-codec: Remove redundant SND_PCM_RATE_KNOT

[Clive Messer]

Maxime,

Can I ask what the real purpose of this patch was?

ASoC: sun4i-codec: Remove redundant SND_PCM_RATE_KNOT 


All it does is stop the codec supporting 88k2 and 176k4 sample rates, both 
of which did and do still work correctly with that patch reverted!

Regards

Clive

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH] fexc: do not abort on a huge version number

[Icenowy Zheng]

Some A33 evb boards have fex files with version = "100", even in the official
SDK. It seems that it's not a error at all. Now only a warning will be printed
in this situation.
---
 script_bin.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/script_bin.c b/script_bin.c
index ce13a2a..2e9f9cf 100644
--- a/script_bin.c
+++ b/script_bin.c
@@ -330,9 +330,8 @@ int script_decompile_bin(void *bin, size_t bin_size,
if ((head->version[0] > SCRIPT_BIN_VERSION_LIMIT) ||
(head->version[1] > SCRIPT_BIN_VERSION_LIMIT) ||
(head->version[2] > SCRIPT_BIN_VERSION_LIMIT)) {
-   pr_err("Malformed data: version %d.%d.%d.\n",
+   pr_info("Possibly malformed data: version %d.%d.%d.\n",
   head->version[0], head->version[1], head->version[2]);
-   return 0;
}
 
/* TODO: SANITY: compare head.sections with bin_size */
-- 
2.6.4

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver

[Rob Herring]

On Thu, Jan 14, 2016 at 04:24:48PM +0100, Maxime Ripard wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
> 
> Add a driver to support both.
> 
> Signed-off-by: Maxime Ripard 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |   2 +

Can't someone read the datasheet and add these compatible strings in one 
pass instead of one at a time?

Acked-by: Rob Herring 

>  drivers/clk/sunxi/Makefile|   1 +
>  drivers/clk/sunxi/clk-sun4i-display.c | 241 
> ++
>  3 files changed, 244 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock

[Rob Herring]

On Thu, Jan 14, 2016 at 04:24:49PM +0100, Maxime Ripard wrote:
> The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> PLL7, clocked from a 3MHz oscillator, that drives the display related
> clocks (GPU, display engine, TCON, etc.)
> 
> Add a driver for it.
> 
> Signed-off-by: Maxime Ripard 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +

Acked-by: Rob Herring 

>  drivers/clk/sunxi/Makefile|  1 +
>  drivers/clk/sunxi/clk-sun4i-pll3.c| 90 
> +++
>  3 files changed, 92 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 17/26] drm: sun4i: Add DT bindings documentation

[Rob Herring]

On Thu, Jan 14, 2016 at 04:25:00PM +0100, Maxime Ripard wrote:
> The display pipeline of the Allwinner A10 is involving several loosely
> coupled components.
> 
> Add a documentation for the bindings.
> 
> Signed-off-by: Maxime Ripard 
> ---
>  .../bindings/display/sunxi/sun4i-drm.txt   | 228 
> +

drm is a linuxism. It shouldn't be used for binding doc.

>  1 file changed, 228 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> new file mode 100644
> index ..061bc87147a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -0,0 +1,228 @@
> +Allwinner A10 Display Pipeline
> +==
> +
> +The Allwinner A10 Display pipeline is composed of several components
> +that are going to be documented below:
> +
> +TV Encoder
> +--
> +
> +The TV Encoder supports the composite and VGA output. It is one end of
> +the pipeline.
> +
> +Required properties:
> + - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
> + - reg: base address and size of memory-mapped region
> + - clocks: the clocks driving the TV encoder
> +
> +- ports: A ports node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt. The
> +  first port should be the input endpoint.
> +
> +TCON
> +
> +
> +The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
> +
> +Required properties:
> + - compatible: value should be "allwinner,sun4i-a10-tcon".
> + - reg: base address and size of memory-mapped region
> + - interrupts: interrupt associated to this IP
> + - clocks: phandles to the clocks feeding the TCON. Three are needed:
> +   - 'ahb': the interface clocks
> +   - 'tcon-ch0': The clock driving the TCON channel 0
> +   - 'tcon-ch1': The clock driving the TCON channel 1
> +
> + - clock-names: the clock names mentioned above
> + - clock-output-names: Name of the pixel clock created
> +
> +- ports: A ports node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt. The
> +  first port should be the input endpoint, the second one the output
> +
> +Optional properties:
> +  - allwinner,panel: phandle to the panel used in our RGB interface
> +
> +
> +Display Engine Backend
> +--
> +
> +The display engine backend exposes layers and sprites to the
> +system.
> +
> +Required properties:
> +  - compatible: value must be one of:
> +* allwinner,sun5i-a13-display-backend
> +  - reg: base address and size of the memory-mapped region.
> +  - clocks: phandles to the clocks feeding the frontend and backend
> +* ahb: the backend interface clock
> +* mod: the backend module clock
> +* ram: the backend DRAM clock
> +  - clock-names: the clock names mentioned above
> +  - resets: phandles to the reset controllers driving the backend
> +
> +- ports: A ports node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt. The
> +  first port should be the input endpoints, the second one the output
> +
> +Display Engine Frontend
> +---
> +
> +The display engine frontend does formats conversion, scaling,
> +deinterlacing and color space conversion.
> +
> +Required properties:
> +  - compatible: value must be one of:
> +* allwinner,sun5i-a13-display-frontend
> +  - reg: base address and size of the memory-mapped region.
> +  - interrupts: interrupt associated to this IP
> +  - clocks: phandles to the clocks feeding the frontend and backend

> +* ahb: the backend interface clock
> +* mod: the backend module clock
> +* ram: the backend DRAM clock

should be frontend?

> +  - clock-names: the clock names mentioned above
> +  - resets: phandles to the reset controllers driving the backend

ditto

> +
> +Display Engine Pipeline
> +---
> +
> +The display engine pipeline (and its entry point, since it can be
> +either directly the backend or the frontend) is represented as an
> +extra node.
> +
> +Required properties:
> +  - compatible: value must be one of:
> +* allwinner,sun5i-a13-display-engine
> +  - allwinner,pipelines: list of phandle to the entry points of the
> +pipelines (either to the frontend or backend)
> +
> +Example:
> +
> +panel: panel {
> + compatible = "olimex,lcd-olinuxino-43-ts";

This should either be a child of what it is attached to or use of-graph.

> +};
> +
> +tve0: tv-encoder@01c0a000 {
> + compatible = "allwinner,sun4i-a10-tv-encoder";
> + reg = <0x01c0a000 0x1000>;
> + clocks = <_gates 34>;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tve0_in_tcon0: endpoint@0 {
> +  

[linux-sunxi] Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix

[Rob Herring]

On Thu, Jan 14, 2016 at 04:25:07PM +0100, Maxime Ripard wrote:
> Olimex is an open source hardware boards vendors based in Bulgaria.
> 
> Signed-off-by: Maxime Ripard 
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring 

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH 1/5] power: axp818: Remove duplicate register definition macros

[Vishnu Patekar]

Hello Wens,

Thanks for correcting it.

Regards,
Vishnu

On Tue, Jan 12, 2016 at 2:42 PM, Chen-Yu Tsai  wrote:
> Some of the register definitions are duplicated. Drop them.
>
> Signed-off-by: Chen-Yu Tsai 
> ---
>  include/axp818.h | 8 
>  1 file changed, 8 deletions(-)
>
> diff --git a/include/axp818.h b/include/axp818.h
> index 1dc6456..46d05ad 100644
> --- a/include/axp818.h
> +++ b/include/axp818.h
> @@ -32,13 +32,6 @@
>  #define AXP818_OUTPUT_CTRL3_ALDO2_EN   (1 << 6)
>  #define AXP818_OUTPUT_CTRL3_ALDO3_EN   (1 << 7)
>
> -#define AXP818_DCDC1_CTRL  0x20
> -#define AXP818_DCDC2_CTRL  0x21
> -#define AXP818_DCDC3_CTRL  0x22
> -#define AXP818_DCDC4_CTRL  0x23
> -#define AXP818_DCDC5_CTRL  0x24
> -#define AXP818_DCDC6_CTRL  0x25
> -
>  #define AXP818_DLDO1_CTRL  0x15
>  #define AXP818_DLDO2_CTRL  0x16
>  #define AXP818_DLDO3_CTRL  0x17
> @@ -46,7 +39,6 @@
>  #define AXP818_ELDO1_CTRL  0x19
>  #define AXP818_ELDO2_CTRL  0x1a
>  #define AXP818_ELDO3_CTRL  0x1b
> -#define AXP818_ELDO3_CTRL  0x1b
>  #define AXP818_FLDO1_CTRL  0x1c
>  #define AXP818_FLDO2_3_CTRL0x1d
>  #define AXP818_DCDC1_CTRL  0x20
> --
> 2.6.4
>

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock

[Rob Herring]

On Thu, Jan 14, 2016 at 04:24:50PM +0100, Maxime Ripard wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
> 
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
> 
> Add a driver for the channel 1 clock.
> 
> Signed-off-by: Maxime Ripard 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +

Acked-by: Rob Herring 

>  drivers/clk/sunxi/Makefile|   1 +
>  drivers/clk/sunxi/clk-sun4i-tcon-ch1.c| 154 
> ++
>  3 files changed, 156 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 08/26] clk: sun5i: add DRAM gates

[Rob Herring]

On Thu, Jan 14, 2016 at 04:24:51PM +0100, Maxime Ripard wrote:
> The Allwinner SoCs have a gate controller to gate the access to the DRAM
> clock to the some devices that need to access the DRAM directly (mostly
> display / image related IPs).
> 
> Use a simple gates driver to support the one found in the A13 / R8 SoCs.
> 
> Signed-off-by: Maxime Ripard 
> Acked-by: Chen-Yu Tsai 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +

Acked-by: Rob Herring 

>  drivers/clk/sunxi/clk-simple-gates.c  | 2 ++
>  2 files changed, 3 insertions(+)

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 25/26] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS

[Rob Herring]

On Thu, Jan 14, 2016 at 04:25:08PM +0100, Maxime Ripard wrote:
> Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
> panel driver.
> 
> It is a 480x272 panel connected through a 24-bits RGB interface.
> 
> Signed-off-by: Maxime Ripard 
> ---
>  .../display/panel/olimex,lcd-olinuxino-43-ts.txt   |  7 ++

Acked-by: Rob Herring 

>  drivers/gpu/drm/panel/panel-simple.c   | 26 
> ++
>  2 files changed, 33 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.