Re: [linux-sunxi] Re: [PATCH 2/3] ARM: dts: sun7i: Add RGB666 pins definition

[Giulio Benetti]

Hi,

Il 12/04/2018 01:09, Paul Kocialkowski ha scritto:

Hi,

Le jeudi 12 avril 2018 à 00:22 +0200, Giulio Benetti a écrit :

Hi,

Il 10/04/2018 23:31, Paul Kocialkowski ha scritto:

This adds the pins definition for RGB666 LCD panels on the A20. It
was
imported from the A33 definition, that concernes the same set of
pins.

Signed-off-by: Paul Kocialkowski 
---
   arch/arm/boot/dts/sun7i-a20.dtsi | 8 
   1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
b/arch/arm/boot/dts/sun7i-a20.dtsi
index e529e4ff2174..f46af8675cfa 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -781,6 +781,14 @@
function = "ir1";
};
   
+			lcd_rgb666_pins: lcd_rgb666@0 {


I point you to this Thread and back:
https://lists.freedesktop.org/archives/dri-devel/2018-March/170688.htm
l

I did the same for rgb888, so good part is discussed.

IMHO I would:
- call lcd0_rgb666_pins, since this is for LCD0 interface
- same as above, call lcd0-rgb666, take care about using "-" instad
of
"_" that can cause DTC warnings.
- remove @0 since only this set can achieve LCD0 RGB666, and I
don't think there will be other combinations.


I even responded to that discussion but overlooked these aspects when
crafting this patch. Thanks for the summary :)


You're welcome, I've forgotten you've been involved discussing
that patch so i've pointed you something yours :)
Anyway it should help.

Best regards

--
Giulio Benetti
CTO

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Kind regards

--
Giulio Benetti
CTO

MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 049/8931563 - Fax 049/8931346
Cod.Fiscale - P.IVA 02663420285
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+   pins = "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7",
+  "PD10", "PD11", "PD12",
"PD13", "PD14", "PD15",
+  "PD18", "PD19", "PD20",
"PD21", "PD22", "PD23",
+  "PD24", "PD25", "PD26",
"PD27";
+   function = "lcd0";
+   };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2",
   "PF3", "PF4", "PF5";






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[linux-sunxi] Re: [PATCH 1/3] drm/panel: Add RGB666 variant of Innolux AT070TN92

[Paul Kocialkowski]

Hi,

Le mercredi 11 avril 2018 à 08:28 +0200, Maxime Ripard a écrit :
> On Tue, Apr 10, 2018 at 11:31:27PM +0200, Paul Kocialkowski wrote:
> > This adds timings for the RGB666 variant of the Innolux AT070TN92
> > panel,
> > as found on the Ainol AW1 tablet.
> > 
> > Signed-off-by: Paul Kocialkowski 
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 26
> > ++
> >  1 file changed, 26 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c
> > b/drivers/gpu/drm/panel/panel-simple.c
> > index 5591984a392b..efeb2f2162bc 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -1063,6 +1063,29 @@ static const struct panel_desc
> > innolux_at070tn92 = {
> > .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> >  };
> >  
> > +static const struct drm_display_mode innolux_at070tn92_rgb666_mode
> > = {
> > +   .clock = 4,
> > +   .hdisplay = 800,
> > +   .hsync_start = 800 + 112,
> > +   .hsync_end = 800 + 112 + 1,
> > +   .htotal = 800 + 112 + 1 + 87,
> > +   .vdisplay = 480,
> > +   .vsync_start = 480 + 141,
> > +   .vsync_end = 480 + 141 + 1,
> > +   .vtotal = 480 + 141 + 1 + 38,
> > +   .vrefresh = 60,
> > +};
> 
> I'm not sure why you'd need different timings if the only difference
> is the bus width.

I'll try with the other timings, although it might be desirable to have
a higher clock speed thanks to the reduced number of wires on the bus.

> > +static const struct panel_desc innolux_at070tn92_rgb666 = {
> > +   .modes = _at070tn92_rgb666_mode,
> > +   .num_modes = 1,
> > +   .size = {
> > +   .width = 154,
> > +   .height = 86,
> > +   },
> > +   .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> > +};
> > +
> >  static const struct display_timing innolux_g101ice_l01_timing = {
> > .pixelclock = { 6040, 7110, 7470 },
> > .hactive = { 1280, 1280, 1280 },
> > @@ -2105,6 +2128,9 @@ static const struct of_device_id
> > platform_of_match[] = {
> > }, {
> > .compatible = "innolux,at070tn92",
> > .data = _at070tn92,
> > +   }, {
> > +   .compatible = "innolux,at070tn92-rgb666",
> > +   .data = _at070tn92_rgb666,
> 
> And this isn't a different device, it's just the integration in the
> board that is different, so you shouldn't have a different compatible
> here, but rather something like the bus-width property documented in
> the Documentation/devicetree/bindings/media/video-interfaces.txt file.

I'll take a look at it and try to craft v2 in this direction then.

Thanks for the review!

-- 
Paul Kocialkowski,

developer of free digital technology and hardware support.

Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Re: [linux-sunxi] Re: [PATCH 2/3] ARM: dts: sun7i: Add RGB666 pins definition

[Paul Kocialkowski]

Hi,

Le jeudi 12 avril 2018 à 00:22 +0200, Giulio Benetti a écrit :
> Hi,
> 
> Il 10/04/2018 23:31, Paul Kocialkowski ha scritto:
> > This adds the pins definition for RGB666 LCD panels on the A20. It
> > was
> > imported from the A33 definition, that concernes the same set of
> > pins.
> > 
> > Signed-off-by: Paul Kocialkowski 
> > ---
> >   arch/arm/boot/dts/sun7i-a20.dtsi | 8 
> >   1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
> > b/arch/arm/boot/dts/sun7i-a20.dtsi
> > index e529e4ff2174..f46af8675cfa 100644
> > --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> > +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> > @@ -781,6 +781,14 @@
> > function = "ir1";
> > };
> >   
> > +   lcd_rgb666_pins: lcd_rgb666@0 {
> 
> I point you to this Thread and back:
> https://lists.freedesktop.org/archives/dri-devel/2018-March/170688.htm
> l
> 
> I did the same for rgb888, so good part is discussed.
> 
> IMHO I would:
> - call lcd0_rgb666_pins, since this is for LCD0 interface
> - same as above, call lcd0-rgb666, take care about using "-" instad
> of 
> "_" that can cause DTC warnings.
> - remove @0 since only this set can achieve LCD0 RGB666, and I
>don't think there will be other combinations.

I even responded to that discussion but overlooked these aspects when
crafting this patch. Thanks for the summary :)

> Kind regards
> 
> -- 
> Giulio Benetti
> CTO
> 
> MICRONOVA SRL
> Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
> Tel. 049/8931563 - Fax 049/8931346
> Cod.Fiscale - P.IVA 02663420285
> Capitale Sociale € 26.000 i.v.
> Iscritta al Reg. Imprese di Padova N. 02663420285
> Numero R.E.A. 258642
> 
> 
> > +   pins = "PD2", "PD3", "PD4", "PD5",
> > "PD6", "PD7",
> > +  "PD10", "PD11", "PD12",
> > "PD13", "PD14", "PD15",
> > +  "PD18", "PD19", "PD20",
> > "PD21", "PD22", "PD23",
> > +  "PD24", "PD25", "PD26",
> > "PD27";
> > +   function = "lcd0";
> > +   };
> > +
> > mmc0_pins_a: mmc0@0 {
> > pins = "PF0", "PF1", "PF2",
> >"PF3", "PF4", "PF5";
> > 
> 
> 
-- 
Paul Kocialkowski,

developer of free digital technology and hardware support.

Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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[linux-sunxi] Re: [PATCH 3/3] ARM: dts: sun7i: Add support for the Ainol AW1 tablet

[Paul Kocialkowski]

Hi and thanks for the review !

Le mercredi 11 avril 2018 à 09:06 +0200, Maxime Ripard a écrit :
> Hi,
> 
> On Tue, Apr 10, 2018 at 11:31:29PM +0200, Paul Kocialkowski wrote:
> > This adds support for the Ainol AW1, an A20-based 7" tablet from
> > Ainol.
> > 
> > The following board-specific features are supported:
> > * LCD panel
> > * Backlight
> > * USB OTG
> > * Buttons
> > * Touchscreen (doesn't work without non-free firmware)
> > * Accelerometer
> > * Battery
> > 
> > The following are untested:
> > * Audio output
> > * Audio speakers
> > * USB via SPCI connector
> > 
> > The following are not supported:
> > * Wi-Fi
> > * Bluetooth
> > * NAND
> > * Audio via SPCI connector
> > 
> > Signed-off-by: Paul Kocialkowski 
> > ---
> >  arch/arm/boot/dts/Makefile|   1 +
> >  arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts | 358
> > ++
> >  2 files changed, 359 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 9f7133b6fba0..03bfacebfdbd 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -929,6 +929,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
> > sun6i-a31s-sinovoip-bpi-m2.dtb \
> > sun6i-a31s-yones-toptech-bs1078-v2.dtb
> >  dtb-$(CONFIG_MACH_SUN7I) += \
> > +   sun7i-a20-ainol-aw1.dtb \
> > sun7i-a20-bananapi.dtb \
> > sun7i-a20-bananapi-m1-plus.dtb \
> > sun7i-a20-bananapro.dtb \
> > diff --git a/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > b/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > new file mode 100644
> > index ..697586991aea
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > @@ -0,0 +1,358 @@
> > +/*
> > + * Copyright 2018 Paul Kocialkowski 
> > + *
> > + * This file is dual-licensed: you can use it either under the
> > terms
> > + * of the GPL or the X11 license, at your option. Note that this
> > dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License
> > as
> > + * published by the Free Software Foundation; either version 2
> > of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This file is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty
> > of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
> > the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated
> > documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom
> > the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall
> > be
> > + * included in all copies or substantial portions of the
> > Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> > WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> > OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> 
> Can you use an SPDX header instead of the whole license text?

Sure, will do in v2.

> > + */
> > +
> > +/dts-v1/;
> > +#include "sun7i-a20.dtsi"
> > +#include "sunxi-common-regulators.dtsi"
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   model = "Ainol AW1";
> > +   compatible = "ainol,ainol-aw1", "allwinner,sun7i-a20";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:115200n8";
> > +   };
> > +
> > +   backlight: backlight {
> > +   compatible = "pwm-backlight";
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <_enable_pin>;
> 
> You don't need any of the pinctrl nodes for the GPIOs

I tried without the pinctrl nodes and got issues on various controllers
(e.g. i2c for the touchscreen) because of the missing pinctrl nodes on
4.16. Maybe I'm missing some patches here?

> > +   pwms = < 0 5 

[linux-sunxi] Re: [PATCH 2/3] ARM: dts: sun7i: Add RGB666 pins definition

[Giulio Benetti]

Hi,

Il 10/04/2018 23:31, Paul Kocialkowski ha scritto:

This adds the pins definition for RGB666 LCD panels on the A20. It was
imported from the A33 definition, that concernes the same set of pins.

Signed-off-by: Paul Kocialkowski 
---
  arch/arm/boot/dts/sun7i-a20.dtsi | 8 
  1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e529e4ff2174..f46af8675cfa 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -781,6 +781,14 @@
function = "ir1";
};
  
+			lcd_rgb666_pins: lcd_rgb666@0 {


I point you to this Thread and back:
https://lists.freedesktop.org/archives/dri-devel/2018-March/170688.html

I did the same for rgb888, so good part is discussed.

IMHO I would:
- call lcd0_rgb666_pins, since this is for LCD0 interface
- same as above, call lcd0-rgb666, take care about using "-" instad of 
"_" that can cause DTC warnings.

- remove @0 since only this set can achieve LCD0 RGB666, and I
  don't think there will be other combinations.

Kind regards

--
Giulio Benetti
CTO

MICRONOVA SRL
Sede: Via A. Niedda 3 - 35010 Vigonza (PD)
Tel. 049/8931563 - Fax 049/8931346
Cod.Fiscale - P.IVA 02663420285
Capitale Sociale € 26.000 i.v.
Iscritta al Reg. Imprese di Padova N. 02663420285
Numero R.E.A. 258642



+   pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+  "PD10", "PD11", "PD12", "PD13", "PD14", 
"PD15",
+  "PD18", "PD19", "PD20", "PD21", "PD22", 
"PD23",
+  "PD24", "PD25", "PD26", "PD27";
+   function = "lcd0";
+   };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2",
   "PF3", "PF4", "PF5";




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Re: [linux-sunxi] [PATCH 1/5] dt-bindings: allow dwmac-sun8i to use other devices' exported regmap

[Brüns , Stefan]

On Mittwoch, 11. April 2018 16:16:37 CEST Icenowy Zheng wrote:
> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i is
> in another device's memory space. In this situation dwmac-sun8i can use
> a regmap exported by the other device with only the EMAC clock register.
> 
> Document this situation in the dwmac-sun8i device tree binding
> documentation.
> 
> Signed-off-by: Icenowy Zheng 
> ---
>  Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index
> 3d6d5fa0c4d5..0c5f63a80617 100644
> --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> @@ -20,8 +20,9 @@ Required properties:
>  - phy-handle: See ethernet.txt
>  - #address-cells: shall be 1
>  - #size-cells: shall be 0
> -- syscon: A phandle to the syscon of the SoC with one of the following
> - compatible string:
> +- syscon: A phandle to a device which exports the EMAC clock register as a
> + regmap or to the syscon of the SoC with one of the following compatible
... regmap, or ...

> + string:
string_s_:

>- allwinner,sun8i-h3-system-controller
>- allwinner,sun8i-v3s-system-controller
>- allwinner,sun50i-a64-system-controller

Kind regards,

Stefan

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[linux-sunxi] [PATCH 5/5] arm64: allwinner: a64: add SRAM controller device tree node

[Icenowy Zheng]

Allwinner A64 has a SRAM controller, and in the device tree currently
we have a syscon node to enable EMAC driver to access the EMAC clock
register. As SRAM controller driver can now export regmap for this
register, replace the syscon node to the SRAM controller device node,
and let EMAC driver to acquire its EMAC clock regmap.

Signed-off-by: Icenowy Zheng 
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1b2ef28c42bd..1c37659d9d41 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -168,10 +168,25 @@
#size-cells = <1>;
ranges;
 
-   syscon: syscon@1c0 {
-   compatible = "allwinner,sun50i-a64-system-controller",
-   "syscon";
+   sram_controller: sram-controller@1c0 {
+   compatible = "allwinner,sun50i-a64-sram-controller";
reg = <0x01c0 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   sram_c: sram@18000 {
+   compatible = "mmio-sram";
+   reg = <0x00018000 0x28000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x00018000 0x28000>;
+
+   de2_sram: sram-section@0 {
+   compatible = 
"allwinner,sun50i-a64-sram-c";
+   reg = <0x 0x28000>;
+   };
+   };
};
 
dma: dma-controller@1c02000 {
@@ -599,7 +614,7 @@
 
emac: ethernet@1c3 {
compatible = "allwinner,sun50i-a64-emac";
-   syscon = <>;
+   syscon = <_controller>;
reg = <0x01c3 0x1>;
interrupts = ;
interrupt-names = "macirq";
-- 
2.15.1

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[linux-sunxi] [PATCH 4/5] drivers: soc: sunxi: export a regmap for EMAC clock reg on A64

[Icenowy Zheng]

The A64 SRAM controller memory zone has a EMAC clock register, which is
needed by the Ethernet MAC driver (dwmac-sun8i).

Export a regmap for this register on A64.

Signed-off-by: Icenowy Zheng 
---
 drivers/soc/sunxi/sunxi_sram.c | 48 --
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index 882be5ed7e84..35ab5f334bb1 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -281,13 +282,41 @@ int sunxi_sram_release(struct device *dev)
 }
 EXPORT_SYMBOL(sunxi_sram_release);
 
+struct sunxi_sramc_variant {
+   bool has_emac_clock;
+};
+
+static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
+   /* Nothing special */
+};
+
+static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
+   .has_emac_clock = true,
+};
+
+static struct regmap_config sunxi_sram_emac_clock_regmap = {
+   .reg_bits   = 32,
+   .val_bits   = 32,
+   .reg_stride = 4,
+   .max_register   = 0x0,  /* only single register */
+   .name   = "emac-clock",
+};
+
+#define SUNXI_SRAM_EMAC_CLOCK_REG  0x30
+
 static int sunxi_sram_probe(struct platform_device *pdev)
 {
struct resource *res;
struct dentry *d;
+   struct regmap *emac_clock;
+   const struct sunxi_sramc_variant *variant;
 
sram_dev = >dev;
 
+   variant = of_device_get_match_data(>dev);
+   if (!variant)
+   return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(>dev, res);
if (IS_ERR(base))
@@ -300,12 +329,27 @@ static int sunxi_sram_probe(struct platform_device *pdev)
if (!d)
return -ENOMEM;
 
+   if (variant->has_emac_clock) {
+   emac_clock = devm_regmap_init_mmio(>dev,
+  base + 
SUNXI_SRAM_EMAC_CLOCK_REG,
+  
_sram_emac_clock_regmap);
+
+   if (IS_ERR(emac_clock))
+   return PTR_ERR(emac_clock);
+   }
+
return 0;
 }
 
 static const struct of_device_id sunxi_sram_dt_match[] = {
-   { .compatible = "allwinner,sun4i-a10-sram-controller" },
-   { .compatible = "allwinner,sun50i-a64-sram-controller" },
+   {
+   .compatible = "allwinner,sun4i-a10-sram-controller",
+   .data = _a10_sramc_variant,
+   },
+   {
+   .compatible = "allwinner,sun50i-a64-sram-controller",
+   .data = _a64_sramc_variant,
+   },
{ },
 };
 MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
-- 
2.15.1

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[linux-sunxi] [PATCH 3/5] net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device

[Icenowy Zheng]

From: Chen-Yu Tsai 

On the Allwinner R40 SoC, the "GMAC clock" register is in the CCU
address space; on the A64 SoC this register is in the SRAM controller
address space, and with a different offset.

To access the register from another device and hide the internal
difference between the device, let it register a regmap named
"emac-clock". We can then get the device from the phandle, and
retrieve the regmap with dev_get_regmap(); in this situation the
regmap_field will be set up to access the only register in the regmap.

Signed-off-by: Chen-Yu Tsai 
[Icenowy: change to use regmaps with single register, change commit
 message]
Signed-off-by: Icenowy Zheng 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 48 ++-
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 1037f6c78bca..b61210c0d415 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -85,6 +85,13 @@ const struct reg_field old_syscon_reg_field = {
.msb = 31,
 };
 
+/* Specially exported regmap which contains only EMAC register */
+const struct reg_field single_reg_field = {
+   .reg = 0,
+   .lsb = 0,
+   .msb = 31,
+};
+
 static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
.soc_has_internal_phy = true,
@@ -979,6 +986,44 @@ static struct mac_device_info *sun8i_dwmac_setup(void 
*ppriv)
return mac;
 }
 
+static struct regmap *sun8i_dwmac_get_emac_regmap(struct sunxi_priv_data *emac,
+ struct device_node *node)
+{
+   struct device_node *syscon_node;
+   struct platform_device *syscon_pdev = NULL;
+   struct regmap *regmap = NULL;
+
+   syscon_node = of_parse_phandle(node, "syscon", 0);
+   if (!syscon_node)
+   return ERR_PTR(-ENODEV);
+
+   if (of_device_is_compatible(syscon_node, "syscon")) {
+   regmap = syscon_regmap_lookup_by_phandle(node, "syscon");
+
+   emac->emac_reg_field = _syscon_reg_field;
+   } else {
+   syscon_pdev = of_find_device_by_node(syscon_node);
+   if (!syscon_pdev) {
+   /* platform device might not be probed yet */
+   regmap = ERR_PTR(-EPROBE_DEFER);
+   goto out_put_node;
+   }
+
+   /* If no regmap is found then trap into error */
+   regmap = dev_get_regmap(_pdev->dev, "emac-clock");
+   if (!regmap)
+   regmap = ERR_PTR(-EINVAL);
+
+   emac->emac_reg_field = _reg_field;
+   }
+
+   if (syscon_pdev)
+   platform_device_put(syscon_pdev);
+out_put_node:
+   of_node_put(syscon_node);
+   return regmap;
+}
+
 static int sun8i_dwmac_probe(struct platform_device *pdev)
 {
struct plat_stmmacenet_data *plat_dat;
@@ -1023,13 +1068,12 @@ static int sun8i_dwmac_probe(struct platform_device 
*pdev)
gmac->regulator = NULL;
}
 
-   regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "syscon");
+   regmap = sun8i_dwmac_get_emac_regmap(gmac, pdev->dev.of_node);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(>dev, "Unable to map syscon: %d\n", ret);
return ret;
}
-   gmac->emac_reg_field = old_syscon_reg_field;
 
gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
 *gmac->emac_reg_field);
-- 
2.15.1

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[linux-sunxi] [PATCH 2/5] net: stmmac: dwmac-sun8i: Use regmap_field for syscon register access

[Icenowy Zheng]

From: Chen-Yu Tsai 

In several SoCs the EMAC register is in the range of another device,
either the SRAM controller (e.g. A64) or the clock controlling unit
(e.g. R40). In this situation we're going to let the device to export a
regmap which contains only the EMAC register, for the dwmac-sun8i driver
to manipulation this register.

This patch converts the use of regmap to regmap_field for mapping and
accessing the EMAC register, so we can have the register address based
on the regmap class, and not in the actual register manipulation code.

This patch only converts regmap_read() and regmap_write() calls to
regmap_field_read() and regmap_field_write() calls. There are some
places where it might make sense to switch to regmap_field_update_bits(),
but this is not done here to keep the patch simple.

Signed-off-by: Chen-Yu Tsai 
[Icenowy: decide reg_field based on regmap type, change commit message]
Signed-off-by: Icenowy Zheng 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 41 ---
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index a3fa65b1ca8e..1037f6c78bca 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -61,9 +61,10 @@ struct emac_variant {
  * @regulator: reference to the optional regulator
  * @rst_ephy:  reference to the optional EPHY reset for the internal PHY
  * @variant:   reference to the current board variant
- * @regmap:regmap for using the syscon
+ * @regmap_field: regmap field for the gmac register
  * @internal_phy_powered: Does the internal PHY is enabled
  * @mux_handle:Internal pointer used by mdio-mux lib
+ * @emac_reg_field: reg_field for the regmap's gmac register
  */
 struct sunxi_priv_data {
struct clk *tx_clk;
@@ -71,9 +72,17 @@ struct sunxi_priv_data {
struct regulator *regulator;
struct reset_control *rst_ephy;
const struct emac_variant *variant;
-   struct regmap *regmap;
+   struct regmap_field *regmap_field;
bool internal_phy_powered;
void *mux_handle;
+   const struct reg_field *emac_reg_field;
+};
+
+/* EMAC clock register @ 0x30 in the "system control" address range */
+const struct reg_field old_syscon_reg_field = {
+   .reg = 0x30,
+   .lsb = 0,
+   .msb = 31,
 };
 
 static const struct emac_variant emac_variant_h3 = {
@@ -216,7 +225,6 @@ static const struct emac_variant emac_variant_a64 = {
 #define SYSCON_ETCS_MII0x0
 #define SYSCON_ETCS_EXT_GMII   0x1
 #define SYSCON_ETCS_INT_GMII   0x2
-#define SYSCON_EMAC_REG0x30
 
 /* sun8i_dwmac_dma_reset() - reset the EMAC
  * Called from stmmac via stmmac_dma_ops->reset
@@ -745,7 +753,7 @@ static int mdio_mux_syscon_switch_fn(int current_child, int 
desired_child,
bool need_power_ephy = false;
 
if (current_child ^ desired_child) {
-   regmap_read(gmac->regmap, SYSCON_EMAC_REG, );
+   regmap_field_read(gmac->regmap_field, );
switch (desired_child) {
case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
dev_info(priv->device, "Switch mux to internal PHY");
@@ -763,7 +771,7 @@ static int mdio_mux_syscon_switch_fn(int current_child, int 
desired_child,
desired_child);
return -EINVAL;
}
-   regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
+   regmap_field_write(gmac->regmap_field, val);
if (need_power_ephy) {
ret = sun8i_dwmac_power_internal_phy(priv);
if (ret)
@@ -801,7 +809,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
int ret;
u32 reg, val;
 
-   regmap_read(gmac->regmap, SYSCON_EMAC_REG, );
+   regmap_field_read(gmac->regmap_field, );
reg = gmac->variant->default_syscon_value;
if (reg != val)
dev_warn(priv->device,
@@ -883,7 +891,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
return -EINVAL;
}
 
-   regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
+   regmap_field_write(gmac->regmap_field, reg);
 
return 0;
 }
@@ -892,7 +900,7 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data 
*gmac)
 {
u32 reg = gmac->variant->default_syscon_value;
 
-   regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
+   regmap_field_write(gmac->regmap_field, reg);
 }
 
 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
@@ -980,6 +988,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
int ret;
struct stmmac_priv *priv;
struct net_device *ndev;
+   struct regmap *regmap;
 
ret = stmmac_get_platform_resources(pdev, 

[linux-sunxi] [PATCH 1/5] dt-bindings: allow dwmac-sun8i to use other devices' exported regmap

[Icenowy Zheng]

On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i is
in another device's memory space. In this situation dwmac-sun8i can use
a regmap exported by the other device with only the EMAC clock register.

Document this situation in the dwmac-sun8i device tree binding
documentation.

Signed-off-by: Icenowy Zheng 
---
 Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt 
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 3d6d5fa0c4d5..0c5f63a80617 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -20,8 +20,9 @@ Required properties:
 - phy-handle: See ethernet.txt
 - #address-cells: shall be 1
 - #size-cells: shall be 0
-- syscon: A phandle to the syscon of the SoC with one of the following
- compatible string:
+- syscon: A phandle to a device which exports the EMAC clock register as a
+ regmap or to the syscon of the SoC with one of the following compatible
+ string:
   - allwinner,sun8i-h3-system-controller
   - allwinner,sun8i-v3s-system-controller
   - allwinner,sun50i-a64-system-controller
-- 
2.15.1

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[linux-sunxi] [PATCH 0/5] Add support in dwmac-sun8i for accessing EMAC clock

[Icenowy Zheng]

On some Allwinner SoCs, the EMAC clock register is in another device's
emory space, e.g. on A64 it's in the memory space of SRAM controller.

This patchset adds the possibility for the device to export the EMAC
clock register as a single-register regmap.

PATCH 1 adds the device tree binding for dwmac-sun8i to use another
device's regmap.

PATCH 2 and 3 are dwmac-sun8i refactors.

PATCH 4 exports the EMAC clock regmap in the SRAM controller driver.

PATCH 5 enable SRAM controller in the A64 device tree (replaces
syscon), and bind dwmac-sun8i to it.

Chen-Yu Tsai (2):
  net: stmmac: dwmac-sun8i: Use regmap_field for syscon register access
  net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device

Icenowy Zheng (3):
  dt-bindings: allow dwmac-sun8i to use other devices' exported regmap
  drivers: soc: sunxi: export a regmap for EMAC clock reg on A64
  arm64: allwinner: a64: add SRAM controller device tree node

 .../devicetree/bindings/net/dwmac-sun8i.txt|  5 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 23 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 85 +++---
 drivers/soc/sunxi/sunxi_sram.c | 48 +++-
 4 files changed, 141 insertions(+), 20 deletions(-)

-- 
2.15.1

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Re: [linux-sunxi] messages from bootlin addresses don't show up on the sunxi list

[Luc Verhaegen]

On Wed, Apr 11, 2018 at 12:15:47PM +0200, Luc Verhaegen wrote:
> 
> In any case, Mike, i just provided Maxime with the email address he 
> registered with, so he can try to fix his account details. I am not able 
> to alter the email address on this account directly, the only other 
> option i have would be to remove this account.

I worded this wrong. It is the only option i or other ml admins have.

Removing this account and creating a new one seems like more work than 
being able to rescue this account and by maxime changing his email 
address (if at all possible).

Luc Verhaegen.

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Re: [linux-sunxi] messages from bootlin addresses don't show up on the sunxi list

[Luc Verhaegen]

On Wed, Apr 11, 2018 at 11:59:06AM +0200, Maxime Ripard wrote:
> On Wed, Apr 11, 2018 at 11:37:10AM +0200, mike.v...@gmail.com wrote:
> > 2018-04-10 10:51 GMT+02:00 Luc Verhaegen :
> > >
> > > This seems like something maxime specific. Mylene seems to manage to
> > > post to the sunxi ml just fine. Quentin schulz is also in the members
> > > list and allowed to post. Same for paulk's bootlin account.
> > >
> > > There are no pending messages, there is no maxime.rip...@bootlin.com in
> > > the banned posters (which is where initial post == spam goes).
> > >
> > > You will have to go ask maxime.
> > 
> > Your messages do not show up on the list. Can you have a look why?
> 
> I haven't been able to unregister my old (@free-electrons.com) mail
> address, and I'm still receiving those mails. And I don't want to
> receive all of them in double either.

Maxime: to be clear: you have not used your bootlin address to email 
linux-sunxi@ either, so the ml admins did not miss this, or drop this 
on the floor. Right?

In any case, Mike, i just provided Maxime with the email address he 
registered with, so he can try to fix his account details. I am not able 
to alter the email address on this account directly, the only other 
option i have would be to remove this account.

Luc Verhaegen.

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Re: [linux-sunxi] Re: [PATCH 3/3] ARM: dts: sun7i: Add support for the Ainol AW1 tablet

[Paul Kocialkowski]

Hi,

Le mardi 10 avril 2018 à 23:35 +0200, Paul Kocialkowski a écrit :
> Le mardi 10 avril 2018 à 23:31 +0200, Paul Kocialkowski a écrit :
> > This adds support for the Ainol AW1, an A20-based 7" tablet from
> > Ainol.
> 
> This version didn't use the dedicated binding for the panel and will
> be
> fixed in v2 and onwards.
> 
> > The following board-specific features are supported:
> > * LCD panel
> > * Backlight
> > * USB OTG
> > * Buttons
> > * Touchscreen (doesn't work without non-free firmware)
> > * Accelerometer
> > * Battery
> > 
> > The following are untested:
> > * Audio output
> > * Audio speakers
> > * USB via SPCI connector
> > 
> > The following are not supported:
> > * Wi-Fi
> > * Bluetooth
> > * NAND
> > * Audio via SPCI connector

The camera is also not supported at this point.

> > Signed-off-by: Paul Kocialkowski 
> > ---
> >  arch/arm/boot/dts/Makefile|   1 +
> >  arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts | 358
> > ++
> >  2 files changed, 359 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 9f7133b6fba0..03bfacebfdbd 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -929,6 +929,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
> > sun6i-a31s-sinovoip-bpi-m2.dtb \
> > sun6i-a31s-yones-toptech-bs1078-v2.dtb
> >  dtb-$(CONFIG_MACH_SUN7I) += \
> > +   sun7i-a20-ainol-aw1.dtb \
> > sun7i-a20-bananapi.dtb \
> > sun7i-a20-bananapi-m1-plus.dtb \
> > sun7i-a20-bananapro.dtb \
> > diff --git a/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > b/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > new file mode 100644
> > index ..697586991aea
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun7i-a20-ainol-aw1.dts
> > @@ -0,0 +1,358 @@
> > +/*
> > + * Copyright 2018 Paul Kocialkowski 
> > + *
> > + * This file is dual-licensed: you can use it either under the
> > terms
> > + * of the GPL or the X11 license, at your option. Note that this
> > dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License
> > as
> > + * published by the Free Software Foundation; either version 2
> > of
> > the
> > + * License, or (at your option) any later version.
> > + *
> > + * This file is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty
> > of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
> > the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated
> > documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom
> > the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall
> > be
> > + * included in all copies or substantial portions of the
> > Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> > WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> > OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +#include "sun7i-a20.dtsi"
> > +#include "sunxi-common-regulators.dtsi"
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   model = "Ainol AW1";
> > +   compatible = "ainol,ainol-aw1", "allwinner,sun7i-a20";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:115200n8";
> > +   };
> > +
> > +   backlight: backlight {
> > +   compatible = "pwm-backlight";
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <_enable_pin>;
> > +   pwms = < 0 5 PWM_POLARITY_INVERTED>;
> > +   brightness-levels = <0 10 20 30 40 50 60 70 80 90
> > 100>;
> > +   default-brightness-level = <5>;
> > +   enable-gpios = < 7 7 GPIO_ACTIVE_HIGH>; /* PH7
> > */
> > +   };
> >