Re: [linux-sunxi] Re: [PATCH v4 3/3] ARM: dts: sun7i: Add support for the Ainol AW1 tablet

[Brüns , Stefan]

On Freitag, 18. Mai 2018 09:14:36 CEST Maxime Ripard wrote:
> On Mon, May 14, 2018 at 10:36:08PM +0200, Paul Kocialkowski wrote:
> > > > +   backlight: backlight {
> > > > +   compatible = "pwm-backlight";
> > > > +   pwms = < 0 5 PWM_POLARITY_INVERTED>;
> > > > +   brightness-levels = <  0   1   1   1   1   2   2   2
> > > > +  2   3   3   3   3   4   4   4
> > > > +  5   5   5   6   6   6   7   7
> > > > +  8   8   8   9   9   9  10  10
> > > > + 10  11  11  12  12  12  13  13
> > > > + 14  14  14  15  15  16  16  17
> > > > + 17  17  18  18  19  19  20  20
> > > > + 21  21  21  22  22  23  23  24
> > > > + 24  25  25  26  26  27  27  28
> > > > + 28  29  30  30  31  31  32  32
> > > > + 33  33  34  35  35  36  36  37
> > > > + 38  38  39  39  40  41  41  42
> > > > + 43  43  44  44  45  46  47  47
> > > > + 48  49  49  50  51  51  52  53
> > > > + 54  54  55  56  57  57  58  59
> > > > + 60  61  61  62  63  64  65  65
> > > > + 66  67  68  69  70  71  71  72
> > > > + 73  74  75  76  77  78  79  80
> > > > + 81  82  83  84  85  86  87  88
> > > > + 89  90  91  92  93  94  95  96
> > > > + 97  98  99 101 102 103 104 105
> > > > +106 108 109 110 111 112 114 115
> > > > +116 117 119 120 121 123 124 125
> > > > +127 128 129 131 132 133 135 136
> > > > +138 139 141 142 144 145 147 148
> > > > +150 151 153 154 156 157 159 161
> > > > +162 164 166 167 169 171 173 174
> > > > +176 178 180 181 183 185 187 189
> > > > +191 192 194 196 198 200 202 204
> > > > +206 208 210 212 214 216 219 221
> > > > +223 225 227 229 232 234 236 238
> > > > +241 242 244 246 248 250 253 255>;
> > > 
> > > You kind of overdid it here :)
> > > 
> > > What I meant to say before was that if you have 10 elements (and you
> > > really should have something in that magnitude) each step should
> > > increase the perceived brightness by 10%.
> > 
> > Mhh I think 10 elements would fall too short to really depict the curve
> > with appropriate precision. Given the usual size for brightness cursors
> > in e.g. gnome-shell, it feels like a bigger number would be more
> > appropriate. Let's make it to 100 with values from 0 to 255!
> > 
> > > In this particular case, I really think having something close to <0 4
> > > 8 16 32 64 128 255> would be enough.
> > > 
> > > And in general, that kind of odd looking table without any more
> > > context is just screaming for a comment :)
> > 
> > Noted, I will explain the idea, but probably without the exact formula
> > that's really a nasty hack written down on a piece of paper sitting in
> > my garbage at this point.
> 
> So no one will ever be able to understand where this sequence comes
> from (yourself-in-two-years included). That sounds like a pretty bad
> idea.
> 
> Maxime

The following formula yields practically the same table:

out = ceil(255 * (0.245 * in/255  +  0.755 * pow(in/255, 2.6) ))

Maximum error: 4, maximum relative error: 0.33 

Kind regards,

Stefan

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

[Jernej Škrabec]

Hi,

Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> > 
> > It is highly unlikely this will be higher than 2, at least for this HDMI
> > PHY, since it has only 1 bit reserved for parent selection. But since I
> > have to fix it, I'll add ">= 2"
> 
> If we're only going to have two parents at most, ever, why don't we
> had just a single other boolean. This would be less intrusive, and we
> wouldn't have to check for those corner cases.

That works for me too. And since it's only the code, it can always be reworked 
if there is the need.

Best regards,
Jernej

> 
> > BTW, I'll resend fixed version of this patch for my R40 HDMI series, since
> > there is nothing to hold it back, unlike for this.
> 
> Awesome, thanks!
> Maxime
> 
> --
> Maxime Ripard, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> https://bootlin.com




-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v7 06/35] musb: sunxi: Add OTG device clkgate and reset for H3/H5

[Maxime Ripard]

On Fri, May 18, 2018 at 01:55:31PM +0200, Marek Vasut wrote:
> On 05/18/2018 01:51 PM, Maxime Ripard wrote:
> > On Mon, May 14, 2018 at 11:13:54AM +0200, Marek Vasut wrote:
> >>> And I don't really know what the constraints are on the SPL side, but
> >>> it's really tight on our end. So maybe I'm exagerating, but you're
> >>> definitely understating it too.
> >>
> >> You can fit into 16k , can you not ?
> > 
> > We have 13k.
> 
> Yuck, in total or for code/data ?
> Seems very similar to CI20.

It's the size of the SRAM, so total.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

[Maxime Ripard]

On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > lookup pll-2 either.
> 
> It is highly unlikely this will be higher than 2, at least for this HDMI PHY, 
> since it has only 1 bit reserved for parent selection. But since I have to 
> fix 
> it, I'll add ">= 2"

If we're only going to have two parents at most, ever, why don't we
had just a single other boolean. This would be less intrusive, and we
wouldn't have to check for those corner cases.

> BTW, I'll resend fixed version of this patch for my R40 HDMI series, since 
> there is nothing to hold it back, unlike for this.

Awesome, thanks!
Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

[Jernej Škrabec]

Hi,

Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
> Hi, guys,
> 
> On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
> > Hi,
> > 
> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> >> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> >>> From: Jernej Skrabec 
> >>> 
> >>> Some SoCs with DW HDMI have multiple possible clock parents, like A64
> >>> and R40.
> >>> 
> >>> Expand HDMI PHY clock driver to support second clock parent.
> >>> 
> >>> Signed-off-by: Jernej Skrabec 
> >>> Signed-off-by: Jagan Teki 
> >>> ---
> >>> Changes for v2:
> >>> - new patch
> >>> 
> >>>   drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |  9 ++-
> >>>   drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 33 ---
> >>>   drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89
> >>>   ++ 3 files changed, 96 insertions(+), 35
> >>>   deletions(-)
> >>> 
> >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> >>> b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..303189d6602c
> >>> 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> >>> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> >>> @@ -98,7 +98,8 @@
> >>> 
> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29)
> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33BIT(27)
> >>> 
> >>> -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL BIT(26)
> >>> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
> >>> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT   26
> >>> 
> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN   BIT(25)
> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x)  ((x) << 20)
> >>> 
> >>> @@ -146,7 +147,7 @@
> >>> 
> >>>   struct sun8i_hdmi_phy;
> >>>   
> >>>   struct sun8i_hdmi_phy_variant {
> >>> 
> >>> - bool has_phy_clk;
> >>> + int  phy_clk_num;
> >>> 
> >>>   void (*phy_init)(struct sun8i_hdmi_phy *phy);
> >>>   void (*phy_disable)(struct dw_hdmi *hdmi,
> >>>   
> >>>   struct sun8i_hdmi_phy *phy);
> >>> 
> >>> @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
> >>> 
> >>>   struct clk  *clk_mod;
> >>>   struct clk  *clk_phy;
> >>>   struct clk  *clk_pll0;
> >>> 
> >>> + struct clk  *clk_pll1;
> >>> 
> >>>   unsigned intrcal;
> >>>   struct regmap   *regs;
> >>>   struct reset_control*rst_phy;
> >>> 
> >>> @@ -188,6 +190,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi
> >>> *hdmi);
> >>> 
> >>>   void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
> >>>   const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
> >>> 
> >>> -int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device
> >>> *dev);
> >>> +int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device
> >>> *dev,
> >>> +  int clk_num);
> >>> 
> >>>   #endif /* _SUN8I_DW_HDMI_H_ */
> >>> 
> >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> >>> b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index
> >>> 5a52fc489a9d..0eadf087fc46
> >>> 100644
> >>> --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> >>> +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> >>> @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi
> >>> *hdmi,>
> >>> 
> >>>   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
> >>>   
> >>>  SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
> >>> 
> >>> - regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
> >>> + /*
> >>> +  * NOTE: We have to be careful not to overwrite PHY parent
> >>> +  * clock selection bit and clock divider.
> >>> +  */
> >>> + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
> >>> +(u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
> >>> +pll_cfg1_init);
> >>> 
> >>>   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
> >>>   
> >>>  (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
> >>>  pll_cfg2_init);
> >>> 
> >>> @@ -232,7 +238,7 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi
> >>> *hdmi,
> >>> void *data,>
> >>> 
> >>>   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
> >>>   
> >>>  SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
> >>> 
> >>> - if (phy->variant->has_phy_clk)
> >>> + if (phy->variant->phy_clk_num)
> >>> 
> >>>   clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
> >>>   
> >>>   return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 
> >>> 1000);
> >>> 
> >>> @@ -393,7 +399,7 @@ static const struct 

[linux-sunxi] Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

[Jernej Škrabec]

Hi,

Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> > From: Jernej Skrabec 
> > 
> > Some SoCs with DW HDMI have multiple possible clock parents, like A64
> > and R40.
> > 
> > Expand HDMI PHY clock driver to support second clock parent.
> > 
> > Signed-off-by: Jernej Skrabec 
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - new patch
> > 
> >  drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |  9 ++-
> >  drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 33 ---
> >  drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89
> >  ++ 3 files changed, 96 insertions(+), 35
> >  deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..303189d6602c
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > @@ -98,7 +98,8 @@
> > 
> >  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_ENBIT(29)
> >  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_ENBIT(28)
> >  #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33   BIT(27)
> > 
> > -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL   BIT(26)
> > +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK   BIT(26)
> > +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
> > 
> >  #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN  BIT(25)
> >  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)((x) << 22)
> >  #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
> > 
> > @@ -146,7 +147,7 @@
> > 
> >  struct sun8i_hdmi_phy;
> >  
> >  struct sun8i_hdmi_phy_variant {
> > 
> > -   bool has_phy_clk;
> > +   int  phy_clk_num;
> > 
> > void (*phy_init)(struct sun8i_hdmi_phy *phy);
> > void (*phy_disable)(struct dw_hdmi *hdmi,
> > 
> > struct sun8i_hdmi_phy *phy);
> > 
> > @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
> > 
> > struct clk  *clk_mod;
> > struct clk  *clk_phy;
> > struct clk  *clk_pll0;
> > 
> > +   struct clk  *clk_pll1;
> > 
> > unsigned intrcal;
> > struct regmap   *regs;
> > struct reset_control*rst_phy;
> > 
> > @@ -188,6 +190,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi
> > *hdmi);
> > 
> >  void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
> >  const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
> > 
> > -int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev);
> > +int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
> > +int clk_num);
> > 
> >  #endif /* _SUN8I_DW_HDMI_H_ */
> > 
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 5a52fc489a9d..0eadf087fc46
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi
> > *hdmi,> 
> > regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
> > 
> >SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
> > 
> > -   regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
> > +   /*
> > +* NOTE: We have to be careful not to overwrite PHY parent
> > +* clock selection bit and clock divider.
> > +*/
> > +   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
> > +  (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
> > +  pll_cfg1_init);
> > 
> > regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
> > 
> >(u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
> >pll_cfg2_init);
> > 
> > @@ -232,7 +238,7 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi,
> > void *data,> 
> > regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
> > 
> >SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
> > 
> > -   if (phy->variant->has_phy_clk)
> > +   if (phy->variant->phy_clk_num)
> > 
> > clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
> > 
> > return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
> > 
> > @@ -393,7 +399,7 @@ static const struct sun8i_hdmi_phy_variant
> > sun8i_a83t_hdmi_phy = {> 
> >  };
> >  
> >  static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
> > 
> > -   .has_phy_clk = true,
> > +   .phy_clk_num = 1,
> > 
> > .phy_init = _hdmi_phy_init_h3,
> > .phy_disable = _hdmi_phy_disable_h3,
> > .phy_config = _hdmi_phy_config_h3,
> > 
> > @@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi,
> > struct device_node *node)> 
> > goto err_put_clk_bus;
> > 
> > }
> > 
> > -   if (phy->variant->has_phy_clk) {
> > 

[linux-sunxi] Re: [PATCH v2 16/26] dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO[0-1] macros

[Rob Herring]

On Fri, May 18, 2018 at 03:15:26PM +0530, Jagan Teki wrote:
> Allwinner A64 has two clock parents PLL_VIDEO0 and PLL_VIDEO1.
> 
> Include these macros on dt-bindings so-that the same can be
> used while defining CCU clock phadles.
> 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - new patch
> 
>  include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Rob Herring 

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [U-Boot] [PATCH v6 0/7] sunxi: sync H3, H5, A64 DTs from mainline Linux

[Andre Przywara]

Hi,

On 18/05/18 11:41, Peter Robinson wrote:
> On Wed, May 16, 2018 at 9:00 AM, Andre Przywara  
> wrote:
>> This is an updated version of the series which brings the exact mainline
>> Linux device tree files for various Allwinner boards into U-Boot.
>> Apart from using the usually more correct reference DT files, this offers
>> the big benefit of being able to use U-Boot's DT copy for directly passing
>> it to the kernel. This avoids to actually load a .dtb file from somewhere,
>> and allows seamless and automatic UEFI booting, so distribution installer
>> images should just work (TM).
>>
>> This cover the ARMv8 SoCs (H5, A64), but also all boards with the H3, as
>> this is somewhat married to the H5 and can only be updated together.
>> The H3 and H5 DT files have diverged quite a bit, but as U-Boot's own
>> usage of the DT is (yet) quite limited, there should be no regressions.
>> The patches are split to first update the SoC .dtsi file, then the board
>> .dts files in a second patch. They are grouped to handle the A64 first,
>> then the H5 and H3. I put the respective kernel commit IDs in the commit
>> messages.
>> Patch 6 brings in the mainline DT for the SoPine baseboard, for which we
>> didn't have a separate .dts in U-Boot so far.
>> Patch 7 adds a separate .dts file for the Pine64-LTS board, which is
>> virtually identical to the SoPine baseboard, but, due to the SoC being
>> named differently, deserves a separate file.
>>
>> This is based on origin/master (ca70cbabdcd1).
>>
>> Maxime, I kept you Acked-by: from the previous posts, as I literally
>> just updated to the latest Linux master, which went through your review
>> anyway. Hope that's OK for you.
>>
>> Cheers,
>> Andre.
>>
>> Changelog v5 .. v6:
>> - bring back DT update patches
>> - update to Linux v4.17-rc5
> 
> Are these based purely on 4.17rc5 because I don't see
> sun50i-a64-pine64-lts.dts in Linus's upstream.

Well, yes, I added this trivial wrapper. I can (and probably will) post
it to Linux, but actually it would be sufficient to have some DT in
U-Boot (and on the SPI flash!), so that one can just use $fdtcontroladdr
and be done.

In case you wonder about (other) differences between mainline and this
series: There is this one path name change in the sun50i-h5.dtsi,
mentioned in the 3/7 commit message, plus I left in the common libretech
.dtsi Chen-Yu created for U-Boot. I guess we will see this sooner or
later in Linux and can then sync this back, if needed.

Cheers,
Andre.

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v7 06/35] musb: sunxi: Add OTG device clkgate and reset for H3/H5

[Marek Vasut]

On 05/18/2018 01:51 PM, Maxime Ripard wrote:
> On Mon, May 14, 2018 at 11:13:54AM +0200, Marek Vasut wrote:
>>> And I don't really know what the constraints are on the SPL side, but
>>> it's really tight on our end. So maybe I'm exagerating, but you're
>>> definitely understating it too.
>>
>> You can fit into 16k , can you not ?
> 
> We have 13k.

Yuck, in total or for code/data ?
Seems very similar to CI20.

> This is no longer a simple request, but some huge spaghetti changes
> that need to be done, mostly by volunteers.

 I am not sure this "volunteers" argument really works in this
 discussion, since this looks like a commercial contribution to me.
>>>
>>> I have no idea to be honest. The maintainance however is volunteering
>>> on my side, and I'm getting a bit tired to see that every one has an
>>> agenda without any consideration about who has the time and resources
>>> to actually do it.
>>
>> My agenda is to make sure upstream doesn't become a swamp.
> 
> And it will become less of a swamp with those patches with the phy
> conversion, so you can tick that on your checklist I guess?

I think so

-- 
Best regards,
Marek Vasut

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v7 06/35] musb: sunxi: Add OTG device clkgate and reset for H3/H5

[Maxime Ripard]

On Mon, May 14, 2018 at 11:13:54AM +0200, Marek Vasut wrote:
> > And I don't really know what the constraints are on the SPL side, but
> > it's really tight on our end. So maybe I'm exagerating, but you're
> > definitely understating it too.
> 
> You can fit into 16k , can you not ?

We have 13k.

> >>> This is no longer a simple request, but some huge spaghetti changes
> >>> that need to be done, mostly by volunteers.
> >>
> >> I am not sure this "volunteers" argument really works in this
> >> discussion, since this looks like a commercial contribution to me.
> > 
> > I have no idea to be honest. The maintainance however is volunteering
> > on my side, and I'm getting a bit tired to see that every one has an
> > agenda without any consideration about who has the time and resources
> > to actually do it.
> 
> My agenda is to make sure upstream doesn't become a swamp.

And it will become less of a swamp with those patches with the phy
conversion, so you can tick that on your checklist I guess?

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: Libva/VA-API integration with freerdp

[Miguel Amez]

Hi again list,

After asking to the freerdp list, this is the answer that they send me:

*Hi Miguel,*

*no, currently there is no (direct) support for libva, but it may be*
*indirectly used with the FFMPEG AVC444 decoder backend.*

*Currently the biggest obstacle there is the custom YUV to RGB filter for*
*the AVC444 mode, which is done CPU only.*

*Accelerating older RGB modes will most likely not be possible though, as*
*they use custom codecs not really supported by hardware.*

*From my point of view libva support will only be half of the work as the*
*main problem currently is the lack of GPU accelerated filter/image*
*manipulation necessary after the video decoding is already complete.*

*But, of course, getting a speedup is always what we're looking for, so*
*maybe we can find some way.*


I think they aren't bad news indeed, but we need to build a use case
scenary with all this characteristics in order to figure out the way we
could "do the miracle". Any idea/suggestion that you have on this?

Thanks for your help,

2018-05-18 10:30 GMT+02:00 Miguel Amez :

> Good morning list,
>
> This is my first post to the list, so I don't know very well the rules that
> you have about posting (if there is anyone).
>
> I've contacted to Paul to know which was the best way of sending you my
> purposal/suggestion, and he told me that sending to this list probably
> would be the best one, so hands on it!
>
> I've been working with Allwinner A20 and freerdp in a production
> environment for 3 years with kernel 3.4+. Our main problem is the video
> acceleration, that makes the experience a litle bit  weird, so that is why
> we decided to test the newest cedrus driver with mainline kernel. Final
> experience is more or less the same and troubles found are again related to
> multimedia and video acceleration.
>
> After taking a look at freerdp's git repository, I realized about one
> commit that talks about the integration in their software of libva/VA-API
> drivers/decoders, so I'm asking them about the posibility of the
> integration of cedrus-libva with their software.
>
> My suggestion: I consider that giving this integration functionality to
> sunxi-cedrus could be great for the comunity as a different use case apart
> from multimedia playing resources, that you are more focused on nowadays.
>
> What do you thing? Would you give me support on this?
>
> Thanks in advance,
>

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Libva/VA-API integration with freerdp

[Miguel Amez]

 Good morning list,

This is my first post to the list, so I don't know very well the rules that
you have about posting (if there is anyone).

I've contacted to Paul to know which was the best way of sending you my
purposal/suggestion, and he told me that sending to this list probably
would be the best one, so hands on it!

I've been working with Allwinner A20 and freerdp in a production
environment for 3 years with kernel 3.4+. Our main problem is the video
acceleration, that makes the experience a litle bit  weird, so that is why
we decided to test the newest cedrus driver with mainline kernel. Final
experience is more or less the same and troubles found are again related to
multimedia and video acceleration.

After taking a look at freerdp's git repository, I realized about one
commit that talks about the integration in their software of libva/VA-API
drivers/decoders, so I'm asking them about the posibility of the
integration of cedrus-libva with their software.

My suggestion: I consider that giving this integration functionality to
sunxi-cedrus could be great for the comunity as a different use case apart
from multimedia playing resources, that you are more focused on nowadays.

What do you thing? Would you give me support on this?

Thanks in advance,

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [U-Boot] [PATCH v6 0/7] sunxi: sync H3, H5, A64 DTs from mainline Linux

[Peter Robinson]

On Wed, May 16, 2018 at 9:00 AM, Andre Przywara  wrote:
> This is an updated version of the series which brings the exact mainline
> Linux device tree files for various Allwinner boards into U-Boot.
> Apart from using the usually more correct reference DT files, this offers
> the big benefit of being able to use U-Boot's DT copy for directly passing
> it to the kernel. This avoids to actually load a .dtb file from somewhere,
> and allows seamless and automatic UEFI booting, so distribution installer
> images should just work (TM).
>
> This cover the ARMv8 SoCs (H5, A64), but also all boards with the H3, as
> this is somewhat married to the H5 and can only be updated together.
> The H3 and H5 DT files have diverged quite a bit, but as U-Boot's own
> usage of the DT is (yet) quite limited, there should be no regressions.
> The patches are split to first update the SoC .dtsi file, then the board
> .dts files in a second patch. They are grouped to handle the A64 first,
> then the H5 and H3. I put the respective kernel commit IDs in the commit
> messages.
> Patch 6 brings in the mainline DT for the SoPine baseboard, for which we
> didn't have a separate .dts in U-Boot so far.
> Patch 7 adds a separate .dts file for the Pine64-LTS board, which is
> virtually identical to the SoPine baseboard, but, due to the SoC being
> named differently, deserves a separate file.
>
> This is based on origin/master (ca70cbabdcd1).
>
> Maxime, I kept you Acked-by: from the previous posts, as I literally
> just updated to the latest Linux master, which went through your review
> anyway. Hope that's OK for you.
>
> Cheers,
> Andre.
>
> Changelog v5 .. v6:
> - bring back DT update patches
> - update to Linux v4.17-rc5

Are these based purely on 4.17rc5 because I don't see
sun50i-a64-pine64-lts.dts in Linus's upstream.

Peter

> Changelog v4 .. v5:
> - drop Linux DT update patches for now
> - fix minor checkpatch complaints
>
> Changelog v3 .. v4:
> - remove MMC environment for all Allwinner boards (including 32 bit ones)
> - keep MMC environment offset to the old values
> - drop DT adjustments to use fixed MMC regulator
>
> Changelog v2 .. v3:
> 01: added, was on the list before
> 02: drop redundant H5 line
> 03-08: unchanged
> 09-20: added
>
> Changelog v1 .. v2:
> 01, 02, 03: unchanged
> 04, 05, 06, 07: added
>
> Andre Przywara (7):
>   sunxi: DT: A64: update device tree file for Allwinner A64 SoC
>   sunxi: DT: A64: update board .dts files from Linux
>   sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs
>   sunxi: DT: H5: update board .dts files from Linux
>   sunxi: DT: H3: update board .dts files from Linux
>   sunxi: DT: A64: add proper SoPine baseboard device tree
>   sunxi: DT: A64: add Pine64-LTS support
>
>  arch/arm/dts/Makefile   |   4 +-
>  arch/arm/dts/axp803.dtsi| 150 +
>  arch/arm/dts/sun50i-a64-bananapi-m64.dts| 200 +-
>  arch/arm/dts/sun50i-a64-nanopi-a64.dts  | 111 +++-
>  arch/arm/dts/sun50i-a64-olinuxino.dts   | 153 -
>  arch/arm/dts/sun50i-a64-orangepi-win.dts| 135 +++-
>  arch/arm/dts/sun50i-a64-pine64-lts.dts  |  13 +
>  arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi |  59 --
>  arch/arm/dts/sun50i-a64-pine64-plus.dts |  17 +-
>  arch/arm/dts/sun50i-a64-pine64.dts  | 186 +-
>  arch/arm/dts/sun50i-a64-sopine-baseboard.dts| 150 +
>  arch/arm/dts/sun50i-a64-sopine.dtsi | 142 
>  arch/arm/dts/sun50i-a64.dtsi| 303 -
>  arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 122 +++-
>  arch/arm/dts/sun50i-h5-nanopi-neo2.dts  |  91 ++-
>  arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 186 +-
>  arch/arm/dts/sun50i-h5-orangepi-prime.dts   | 189 +-
>  arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts  |  64 +-
>  arch/arm/dts/sun50i-h5.dtsi |  36 +-
>  arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts|  55 +-
>  arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts  | 109 ++-
>  arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts|  78 +++
>  arch/arm/dts/sun8i-h3-nanopi-m1.dts |  42 ++
>  arch/arm/dts/sun8i-h3-nanopi-neo-air.dts|  28 +-
>  arch/arm/dts/sun8i-h3-nanopi-neo.dts|  17 +
>  arch/arm/dts/sun8i-h3-nanopi.dtsi   |  13 +-
>  arch/arm/dts/sun8i-h3-orangepi-2.dts|  92 ++-
>  arch/arm/dts/sun8i-h3-orangepi-lite.dts |  57 +-
>  arch/arm/dts/sun8i-h3-orangepi-one.dts  |  94 ++-
>  arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts  |  11 +-
>  arch/arm/dts/sun8i-h3-orangepi-pc.dts   | 113 +++-
>  arch/arm/dts/sun8i-h3-orangepi-plus.dts |  29 +-
>  arch/arm/dts/sun8i-h3-orangepi-plus2e.dts   |  15 +-
>  arch/arm/dts/sun8i-h3.dtsi  | 544 ++-
>  arch/arm/dts/sunxi-h3-h5.dtsi   | 842 
> 
>  

[linux-sunxi] Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

[Maxime Ripard]

On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> From: Jernej Skrabec 
> 
> Some SoCs with DW HDMI have multiple possible clock parents, like A64
> and R40.
> 
> Expand HDMI PHY clock driver to support second clock parent.
> 
> Signed-off-by: Jernej Skrabec 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - new patch
> 
>  drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |  9 ++-
>  drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 33 ---
>  drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89 
> ++
>  3 files changed, 96 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h 
> b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> index 79154f0f674a..303189d6602c 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> @@ -98,7 +98,8 @@
>  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN  BIT(29)
>  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN  BIT(28)
>  #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
> -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL BIT(26)
> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT   26
>  #define SUN8I_HDMI_PHY_PLL_CFG1_PLLENBIT(25)
>  #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)  ((x) << 22)
>  #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x)   ((x) << 20)
> @@ -146,7 +147,7 @@
>  struct sun8i_hdmi_phy;
>  
>  struct sun8i_hdmi_phy_variant {
> - bool has_phy_clk;
> + int  phy_clk_num;
>   void (*phy_init)(struct sun8i_hdmi_phy *phy);
>   void (*phy_disable)(struct dw_hdmi *hdmi,
>   struct sun8i_hdmi_phy *phy);
> @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
>   struct clk  *clk_mod;
>   struct clk  *clk_phy;
>   struct clk  *clk_pll0;
> + struct clk  *clk_pll1;
>   unsigned intrcal;
>   struct regmap   *regs;
>   struct reset_control*rst_phy;
> @@ -188,6 +190,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
>  void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
>  const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
>  
> -int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev);
> +int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
> +  int clk_num);
>  
>  #endif /* _SUN8I_DW_HDMI_H_ */
> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 
> b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> index 5a52fc489a9d..0eadf087fc46 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
>   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
>  SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
>  
> - regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
> + /*
> +  * NOTE: We have to be careful not to overwrite PHY parent
> +  * clock selection bit and clock divider.
> +  */
> + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
> +(u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
> +pll_cfg1_init);
>   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
>  (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
>  pll_cfg2_init);
> @@ -232,7 +238,7 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, 
> void *data,
>   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
>  SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
>  
> - if (phy->variant->has_phy_clk)
> + if (phy->variant->phy_clk_num)
>   clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
>  
>   return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
> @@ -393,7 +399,7 @@ static const struct sun8i_hdmi_phy_variant 
> sun8i_a83t_hdmi_phy = {
>  };
>  
>  static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
> - .has_phy_clk = true,
> + .phy_clk_num = 1,
>   .phy_init = _hdmi_phy_init_h3,
>   .phy_disable = _hdmi_phy_disable_h3,
>   .phy_config = _hdmi_phy_config_h3,
> @@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, 
> struct device_node *node)
>   goto err_put_clk_bus;
>   }
>  
> - if (phy->variant->has_phy_clk) {
> + if (phy->variant->phy_clk_num) {
>   phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
>   if (IS_ERR(phy->clk_pll0)) {
>   dev_err(dev, "Could not get pll-0 clock\n");
> @@ -472,7 +478,16 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, 
> struct device_node *node)
>   goto 

[linux-sunxi] Re: [PATCH v2 00/26] arm64: allwinner: Add A64 DE2 HDMI support

[Maxime Ripard]

On Fri, May 18, 2018 at 03:15:10PM +0530, Jagan Teki wrote:
> Allwinner A64 has display engine pipeline like other Allwinner SOC's 
> A83T/H3/H5.
> 
> A64 behaviour similar to Allwinner A83T where
> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
> Mixer1 => TCON1 => HDMI
> as per Display System Block DiagramAllwinner_A64_User_Manual_V1.1.pdf
> 
> This is second patch-set followed with previous RFC[1] and first series[2]
> and merely concentrated on HDMI pipeline through TCON1 and rest will add 
> eventually.
> 
> This series fixed previous version comments
> - about documenting fallback compatibles
> - adding new compatible for mixer1
> - support for multiple DW HDMI PHY clock parents (thanks, to Jernej)
> 
> Note:
> Pine64 boards are unable to get edid by default like other A64 boards,
> but forcing 'video=HDMI-A-1:1920x1080@60D' kernel command line can
> create edid with display on penel.

There's no point in trying to push this without the SRAM issue being
solved. It is required, and won't be merged unless this is addressed.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] [PATCH v2 26/26] arm64: dts: allwinner: a64: sopine: Enable HDMI output

[Jagan Teki]

Enable HDMI output on sopine board.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 .../dts/allwinner/sun50i-a64-sopine-baseboard.dts  | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index abe179de35d7..72f29b78117c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
 
+   connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
reg_vcc1v8: vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
@@ -69,6 +80,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -86,6 +101,17 @@
status = "okay";
 };
 
+ {
+   hvcc-supply = <_dldo1>;
+   status = "okay";
+};
+
+_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <_con_in>;
+   };
+};
+
  {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 24/26] arm64: dts: allwinner: a64: a64-olinuxino: Enable HDMI output

[Jagan Teki]

Enable HDMI output on a64-olinuxino board.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 .../boot/dts/allwinner/sun50i-a64-olinuxino.dts| 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 3b3081b10ecb..83329c8fec4f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -58,12 +58,38 @@
stdout-path = "serial0:115200n8";
};
 
+   connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   hvcc-supply = <_dldo1>;
+   status = "okay";
+};
+
+_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <_con_in>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 21/26] arm64: dts: allwinner: a64: bananapi-m64: Enable HDMI output

[Jagan Teki]

Enable HDMI output on Bananpi-m64 board.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 0716b1441187..bbbf7b17b70b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
 
+   connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
leds {
compatible = "gpio-leds";
 
@@ -86,6 +97,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -103,6 +118,17 @@
status = "okay";
 };
 
+ {
+   hvcc-supply = <_dldo1>;
+   status = "okay";
+};
+
+_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <_con_in>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 18/26] drm/sun4i: Enable DesignWare HDMI for SUN8I and SUN50I

[Jagan Teki]

Allwinner SoC like SUN8I and SUN50I are now using DesignWare HDMI
so enable them as default.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Enable for SUN8I

 drivers/gpu/drm/sun4i/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index a84120025197..c10617c1f84b 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -52,6 +52,7 @@ config DRM_SUN6I_DSI
 
 config DRM_SUN8I_DW_HDMI
tristate "Support for Allwinner version of DesignWare HDMI"
+   default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
depends on DRM_SUN4I
select DRM_DW_HDMI
help
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 13/26] drm/sun4i: Add support for A64 HDMI PHY

[Jagan Teki]

From: Jernej Skrabec 

PHY is the same as in H3, except it can select between two clock parent.

Signed-off-by: Jernej Skrabec 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 
b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 0eadf087fc46..39fbf7257fce 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -392,6 +392,13 @@ static struct regmap_config sun8i_hdmi_phy_regmap_config = 
{
.name   = "phy"
 };
 
+static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
+   .phy_clk_num = 2,
+   .phy_init = _hdmi_phy_init_h3,
+   .phy_disable = _hdmi_phy_disable_h3,
+   .phy_config = _hdmi_phy_config_h3,
+};
+
 static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
.phy_init = _hdmi_phy_init_a83t,
.phy_disable = _hdmi_phy_disable_a83t,
@@ -406,6 +413,10 @@ static const struct sun8i_hdmi_phy_variant 
sun8i_h3_hdmi_phy = {
 };
 
 static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
+   {
+   .compatible = "allwinner,sun50i-a64-hdmi-phy",
+   .data = _a64_hdmi_phy,
+   },
{
.compatible = "allwinner,sun8i-a83t-hdmi-phy",
.data = _a83t_hdmi_phy,
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

[Jagan Teki]

From: Jernej Skrabec 

Some SoCs with DW HDMI have multiple possible clock parents, like A64
and R40.

Expand HDMI PHY clock driver to support second clock parent.

Signed-off-by: Jernej Skrabec 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- new patch

 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |  9 ++-
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 33 ---
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89 ++
 3 files changed, 96 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h 
b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 79154f0f674a..303189d6602c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -98,7 +98,8 @@
 #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_ENBIT(29)
 #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_ENBIT(28)
 #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33   BIT(27)
-#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL   BIT(26)
+#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK   BIT(26)
+#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
 #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN  BIT(25)
 #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)((x) << 22)
 #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
@@ -146,7 +147,7 @@
 struct sun8i_hdmi_phy;
 
 struct sun8i_hdmi_phy_variant {
-   bool has_phy_clk;
+   int  phy_clk_num;
void (*phy_init)(struct sun8i_hdmi_phy *phy);
void (*phy_disable)(struct dw_hdmi *hdmi,
struct sun8i_hdmi_phy *phy);
@@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
struct clk  *clk_mod;
struct clk  *clk_phy;
struct clk  *clk_pll0;
+   struct clk  *clk_pll1;
unsigned intrcal;
struct regmap   *regs;
struct reset_control*rst_phy;
@@ -188,6 +190,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
 const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
 
-int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev);
+int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
+int clk_num);
 
 #endif /* _SUN8I_DW_HDMI_H_ */
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 
b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 5a52fc489a9d..0eadf087fc46 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
   SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
 
-   regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
+   /*
+* NOTE: We have to be careful not to overwrite PHY parent
+* clock selection bit and clock divider.
+*/
+   regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
+  (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
+  pll_cfg1_init);
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
   (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
   pll_cfg2_init);
@@ -232,7 +238,7 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void 
*data,
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
   SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
 
-   if (phy->variant->has_phy_clk)
+   if (phy->variant->phy_clk_num)
clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
 
return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
@@ -393,7 +399,7 @@ static const struct sun8i_hdmi_phy_variant 
sun8i_a83t_hdmi_phy = {
 };
 
 static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
-   .has_phy_clk = true,
+   .phy_clk_num = 1,
.phy_init = _hdmi_phy_init_h3,
.phy_disable = _hdmi_phy_disable_h3,
.phy_config = _hdmi_phy_config_h3,
@@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct 
device_node *node)
goto err_put_clk_bus;
}
 
-   if (phy->variant->has_phy_clk) {
+   if (phy->variant->phy_clk_num) {
phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
if (IS_ERR(phy->clk_pll0)) {
dev_err(dev, "Could not get pll-0 clock\n");
@@ -472,7 +478,16 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, 
struct device_node *node)
goto err_put_clk_mod;
}
 
-   ret = sun8i_phy_clk_create(phy, dev);
+   if (phy->variant->phy_clk_num) {
+   phy->clk_pll1 = of_clk_get_by_name(node, 

[linux-sunxi] [PATCH v2 15/26] dt-bindings: display: Add compatible for A64 HDMI PHY

[Jagan Teki]

HDMI PHY on Allwinner A64 has similar like H3/H5 but with
two clock parents, so add separate compatible for A64.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Add separate compatible for A64

 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 1a5ff416dea4..4f7b9dca8ca0 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -104,6 +104,7 @@ Required properties:
   - compatible: value must be one of:
 * allwinner,sun8i-a83t-hdmi-phy
 * allwinner,sun8i-h3-hdmi-phy
+* allwinner,sun50i-a64-hdmi-phy
   - reg: base address and size of memory-mapped region
   - clocks: phandles to the clocks feeding the HDMI PHY
 * bus: the HDMI PHY interface clock
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 14/26] dt-bindings: display: Add compatible for A64 HDMI

[Jagan Teki]

HDMI on Allwinner A64 has similar like H3/H5/A83T.

Add compatible a64 and update A83T compatible as fallback.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Add fallback compatible

 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 863afad6a4df..1a5ff416dea4 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -78,6 +78,7 @@ Required properties:
 
   - compatible: value must be one of:
 * "allwinner,sun8i-a83t-dw-hdmi"
+* "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"
   - reg: base address and size of memory-mapped region
   - reg-io-width: See dw_hdmi.txt. Shall be 1.
   - interrupts: HDMI interrupt number
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 11/26] arm64: defconfig: Enable CONFIG_DRM_SUN4I

[Jagan Teki]

Enable DRM Support for Allwinner Display Engine, built as a module.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d25121b087bb..d2db76f296cf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -421,6 +421,7 @@ CONFIG_DRM_EXYNOS_DSI=y
 CONFIG_DRM_EXYNOS_HDMI=y
 CONFIG_DRM_EXYNOS_MIC=y
 CONFIG_DRM_ROCKCHIP=m
+CONFIG_DRM_SUN4I=m
 CONFIG_ROCKCHIP_ANALOGIX_DP=y
 CONFIG_ROCKCHIP_CDN_DP=y
 CONFIG_ROCKCHIP_DW_HDMI=y
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 05/26] drm/sun4i: DE2 mixer: Add index quirk

[Jagan Teki]

From: Jernej Skrabec 

When TCON set up TCON TOP, it needs to know mixer index. Here we do that
by setting engine ID to number provided in mixer index quirk.

Signed-off-by: Jernej Skrabec 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- New patch

 drivers/gpu/drm/sun4i/sun8i_mixer.c | 4 ++--
 drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c 
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 126899d6f0d3..36d90c76317a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -353,13 +353,13 @@ static int sun8i_mixer_bind(struct device *dev, struct 
device *master,
dev_set_drvdata(dev, mixer);
mixer->engine.ops = _engine_ops;
mixer->engine.node = dev->of_node;
-   /* The ID of the mixer currently doesn't matter */
-   mixer->engine.id = -1;
 
mixer->cfg = of_device_get_match_data(dev);
if (!mixer->cfg)
return -EINVAL;
 
+   mixer->engine.id = mixer->cfg->index;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h 
b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index f34e70c42adf..aeda6e9a7627 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -123,6 +123,7 @@ struct de2_fmt_info {
  * are invalid.
  * @mod_rate: module clock rate that needs to be set in order to have
  * a functional block.
+ * @index: mixer index, needed to properly set TCON TOP
  */
 struct sun8i_mixer_cfg {
int vi_num;
@@ -130,6 +131,7 @@ struct sun8i_mixer_cfg {
int scaler_mask;
int ccsc;
unsigned long   mod_rate;
+   int index;
 };
 
 struct sun8i_mixer {
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 09/26] arm64: dts: allwinner: a64: Add DE2 tcon1 pipeline

[Jagan Teki]

The DE2 on the A64 is mainly composed of the mixers and tcons,
plus various encoders.

This patch add second mixer and tcon which eventually useful
for testing HDMI. the other part of DE2 will add in future.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Change compatibles and other based on previous patch changes

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 26c2a9c44727..9c1452ee8027 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -107,6 +107,12 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun50i-a64-display-engine";
+   allwinner,pipelines = <>;
+   status = "disabled";
+   };
+
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -183,6 +189,30 @@
#reset-cells = <1>;
};
 
+   mixer1: mixer@120 {
+   compatible = "allwinner,sun50i-a64-de2-mixer-1";
+   reg = <0x0120 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_WB>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer1_out: port@1 {
+   reg = <1>;
+
+   mixer1_out_tcon1: endpoint {
+   remote-endpoint = 
<_in_mixer1>;
+   };
+   };
+   };
+   };
+
+
syscon: syscon@1c0 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
@@ -200,6 +230,37 @@
#dma-cells = <1>;
};
 
+   tcon1: lcd-controller@1c0d000 {
+   compatible = "allwinner,sun50i-a64-tcon-tv",
+"allwinner,sun8i-a83t-tcon-tv";
+   reg = <0x01c0d000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_BUS_TCON1>, < CLK_TCON1>;
+   clock-names = "ahb", "tcon-ch1";
+   resets = < RST_BUS_TCON1>;
+   reset-names = "lcd";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tcon1_in: port@0 {
+   reg = <0>;
+
+   tcon1_in_mixer1: endpoint {
+   remote-endpoint = 
<_out_tcon1>;
+   };
+   };
+
+   tcon1_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   };
+   };
+   };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 08/26] drm/sun4i: Add support for A64 display engine

[Jagan Teki]

Display Engine(DE2) in Allwinner A64 has two mixers and tcons.

The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.

The routing for mixer1 is through tcon1 and connected to HDMI.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 50d19605c38f..c84102a750f8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -368,6 +368,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ .compatible = "allwinner,sun9i-a80-display-engine" },
+   { .compatible = "allwinner,sun50i-a64-display-engine" },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 10/26] drm/sun4i: Enable DE2 Mixer for SUN8I and SUN50I

[Jagan Teki]

Allwinner SoC like SUN8I and SUN50I are now using DE2 Mixer
so enable them as default.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Enable for SUN8I

 drivers/gpu/drm/sun4i/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 156a865c3e6d..a84120025197 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -61,7 +61,7 @@ config DRM_SUN8I_DW_HDMI
 
 config DRM_SUN8I_MIXER
tristate "Support for Allwinner Display Engine 2.0 Mixer"
-   default MACH_SUN8I
+   default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
help
  Choose this option if you have an Allwinner SoC with the
  Allwinner Display Engine 2.0, which has a mixer to do some
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 04/26] clk: sunxi-ng: a64: Add minimal rate for video PLLs

[Jagan Teki]

According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both A64 video PLLs to 192 MHz.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- New patch

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++-
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c 
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index ee9c12cf3f08..d0e30192f0cf 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, 
"pll-audio-base",
   BIT(28), /* lock */
   CLK_SET_RATE_UNGATE);
 
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
-   "osc24M", 0x010,
-   8, 7,   /* N */
-   0, 4,   /* M */
-   BIT(24),/* frac enable */
-   BIT(25),/* frac select */
-   27000,  /* frac rate 0 */
-   29700,  /* frac rate 1 */
-   BIT(31),/* gate */
-   BIT(28),/* lock */
-   CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+   "osc24M", 0x010,
+   19200,  /* Minimum rate */
+   8, 7,   /* N */
+   0, 4,   /* M */
+   BIT(24),/* frac enable */
+   BIT(25),/* frac select */
+   27000,  /* frac rate 0 */
+   29700,  /* frac rate 1 */
+   BIT(31),/* gate */
+   BIT(28),/* lock */
+   CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
@@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = {
},
 };
 
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
-   "osc24M", 0x030,
-   8, 7,   /* N */
-   0, 4,   /* M */
-   BIT(24),/* frac enable */
-   BIT(25),/* frac select */
-   27000,  /* frac rate 0 */
-   29700,  /* frac rate 1 */
-   BIT(31),/* gate */
-   BIT(28),/* lock */
-   CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+   "osc24M", 0x030,
+   19200,  /* Minimum rate */
+   8, 7,   /* N */
+   0, 4,   /* M */
+   BIT(24),/* frac enable */
+   BIT(25),/* frac select */
+   27000,  /* frac rate 0 */
+   29700,  /* frac rate 1 */
+   BIT(31),/* gate */
+   BIT(28),/* lock */
+   CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 07/26] dt-bindings: display: Add compatible for A64 DE2 tcon1 blocks

[Jagan Teki]

Allwinner A64 has DE2 pipeline with tcon0 and tcon1 block
which is similar Allwinner A83T.

This patch adds dt-binding documentation for A64 DE2 tcon1 blocks.

Mixer1 has different configuration for A64 so use separate compatible
but tcon1 has similar behaviour with A83T so add fallback compatible.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Add fallback compatible for tcon1
- Add separate compatible for mixer1 

 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 3346c1e2a7a0..863afad6a4df 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -148,6 +148,7 @@ Required properties:
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
+   * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the TCON.
@@ -311,6 +312,7 @@ Required properties:
 * allwinner,sun8i-a83t-de2-mixer-1
 * allwinner,sun8i-h3-de2-mixer-0
 * allwinner,sun8i-v3s-de2-mixer
+* allwinner,sun50i-a64-de2-mixer-1"
   - reg: base address and size of the memory-mapped region.
   - clocks: phandles to the clocks feeding the mixer
 * bus: the mixer interface clock
@@ -343,6 +345,7 @@ Required properties:
 * allwinner,sun8i-h3-display-engine
 * allwinner,sun8i-v3s-display-engine
 * allwinner,sun9i-a80-display-engine
+* allwinner,sun50i-a64-display-engine
 
   - allwinner,pipelines: list of phandle to the display engine
 frontends (DE 1.0) or mixers (DE 2.0) available.
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 06/26] drm/sun4i: Add support for A64 mixer1

[Jagan Teki]

Mixers in Allwinner have similar capabilities as others SoCs with DE2.

Mixer1 has 1 VI and 1 UI planes and supports HW scaling on all
planes.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- New patch

 drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c 
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 36d90c76317a..5b02c6ee2be6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -508,6 +508,15 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.mod_rate = 15000,
 };
 
+static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
+   .ccsc   = 1,
+   .index  = 1,
+   .mod_rate   = 29700,
+   .scaler_mask= 0x3,
+   .ui_num = 1,
+   .vi_num = 1,
+};
+
 static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
@@ -525,6 +534,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = _v3s_mixer_cfg,
},
+   {
+   .compatible = "allwinner,sun50i-a64-de2-mixer-1",
+   .data = _a64_mixer1_cfg,
+   },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 03/26] clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I

[Jagan Teki]

Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
as default.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Enable for MACH_SUN8I

 drivers/clk/sunxi-ng/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 826674d090fd..e20182aa9748 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -63,6 +63,8 @@ config SUN8I_V3S_CCU
 
 config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
+   default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+   depends on DRM_SUN4I && (MACH_SUN8I || (ARM64 && ARCH_SUNXI))
 
 config SUN8I_R40_CCU
bool "Support for the Allwinner R40 CCU"
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 02/26] arm64: dts: allwinner: a64: Add DE2 CCU

[Jagan Teki]

DE2 CCU in Allwinner A64 has same like H5, so use the
similar dts details for A64 with fallback compatible.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Add h5 compatible first since A64 came first.

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1b2ef28c42bd..26c2a9c44727 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,9 +43,11 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -168,6 +170,19 @@
#size-cells = <1>;
ranges;
 
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun50i-h5-de2-clk",
+"allwinner,sun50i-a64-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 01/26] dt-bindings: clock: Add compatible for A64 DE2 CCU

[Jagan Teki]

Allwinner A64 has DE2 CCU is similar to H3/H5 SoC.

So add compatible for A64 which is fallback compatible
for H5, so update fallback binding.

Signed-off-by: Jagan Teki 
Reviewed-by: Rob Herring 
---
Changes for v2:
- Add fallback compatible

 Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index f2fa87c4765c..e3ffe0bcd0a0 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -7,6 +7,7 @@ Required properties :
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
+   - "allwinner,sun50i-a64-de2-clk", "allwinner,sun50i-h5-de2-clk"
 
 - reg: Must contain the registers base address and length
 - clocks: phandle to the clocks feeding the display engine subsystem.
-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] [PATCH v2 00/26] arm64: allwinner: Add A64 DE2 HDMI support

[Jagan Teki]

Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.

A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block DiagramAllwinner_A64_User_Manual_V1.1.pdf

This is second patch-set followed with previous RFC[1] and first series[2]
and merely concentrated on HDMI pipeline through TCON1 and rest will add 
eventually.

This series fixed previous version comments
- about documenting fallback compatibles
- adding new compatible for mixer1
- support for multiple DW HDMI PHY clock parents (thanks, to Jernej)

Note:
Pine64 boards are unable to get edid by default like other A64 boards,
but forcing 'video=HDMI-A-1:1920x1080@60D' kernel command line can
create edid with display on penel.

Log:
[1.613196] sun4i-drm display-engine: bound 120.mixer (ops 
sun8i_mixer_ops)
[1.620764] sun4i-drm display-engine: No panel or bridge found... RGB output 
disabled
[1.628612] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops 
sun4i_tcon_ops)
[1.637677] sun8i-dw-hdmi 1ee.hdmi: Detected HDMI TX controller v1.32a 
with HDCP (sun8i_dw_hdmi_ph
y)
[1.647699] sun8i-dw-hdmi 1ee.hdmi: registered DesignWare HDMI I2C bus 
driver
[1.656090] [drm] forcing HDMI-A-1 connector on
[1.660664] sun4i-drm display-engine: bound 1ee.hdmi (ops 
sun8i_dw_hdmi_ops)
[1.668063] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[1.674684] [drm] No driver support for vblank timestamp query.
[2.497502] Console: switching to colour frame buffer device 240x67
[2.551795] sun4i-drm display-engine: fb0:  frame buffer device
[2.558166] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on 
minor 0

[2] https://lkml.org/lkml/2018/4/30/288
[1] https://lkml.org/lkml/2018/4/24/547

Icenowy Zheng (1):
  drm: sun4i: add support for HVCC regulator for DWC HDMI glue

Jagan Teki (22):
  dt-bindings: clock: Add compatible for A64 DE2 CCU
  arm64: dts: allwinner: a64: Add DE2 CCU
  clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
  clk: sunxi-ng: a64: Add minimal rate for video PLLs
  drm/sun4i: Add support for A64 mixer1
  dt-bindings: display: Add compatible for A64 DE2 tcon1 blocks
  drm/sun4i: Add support for A64 display engine
  arm64: dts: allwinner: a64: Add DE2 tcon1 pipeline
  drm/sun4i: Enable DE2 Mixer for SUN8I and SUN50I
  arm64: defconfig: Enable CONFIG_DRM_SUN4I
  dt-bindings: display: Add compatible for A64 HDMI
  dt-bindings: display: Add compatible for A64 HDMI PHY
  dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO[0-1] macros
  arm64: dts: allwinner: a64: Add HDMI support
  drm/sun4i: Enable DesignWare HDMI for SUN8I and SUN50I
  arm64: dts: allwinner: a64: Add HDMI pipeline
  arm64: dts: allwinner: a64: bananapi-m64: Enable HDMI output
  arm64: dts: allwinner: a64: nanopi-a64: Enable HDMI output
  arm64: dts: allwinner: a64: orangepi-win: Enable HDMI output
  arm64: dts: allwinner: a64: a64-olinuxino: Enable HDMI output
  arm64: dts: allwinner: a64: pine64: Enable HDMI output
  arm64: dts: allwinner: a64: sopine: Enable HDMI output

Jernej Skrabec (3):
  drm/sun4i: DE2 mixer: Add index quirk
  drm/sun4i: Add support for multiple DW HDMI PHY clock parents
  drm/sun4i: Add support for A64 HDMI PHY

 .../devicetree/bindings/clock/sun8i-de2.txt|   1 +
 .../bindings/display/sunxi/sun4i-drm.txt   |   5 +
 .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts |  26 +
 .../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts   |  26 +
 .../boot/dts/allwinner/sun50i-a64-olinuxino.dts|  26 +
 .../boot/dts/allwinner/sun50i-a64-orangepi-win.dts |  26 +
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |  26 +
 .../dts/allwinner/sun50i-a64-sopine-baseboard.dts  |  26 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 124 +
 arch/arm64/configs/defconfig   |   1 +
 drivers/clk/sunxi-ng/Kconfig   |   2 +
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c  |  46 
 drivers/gpu/drm/sun4i/Kconfig  |   3 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c  |   1 +
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c  |  14 +++
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |  11 +-
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c |  44 ++--
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c |  89 +++
 drivers/gpu/drm/sun4i/sun8i_mixer.c|  17 ++-
 drivers/gpu/drm/sun4i/sun8i_mixer.h|   2 +
 include/dt-bindings/clock/sun50i-a64-ccu.h |   2 +
 21 files changed, 458 insertions(+), 60 deletions(-)

-- 
2.14.3

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[linux-sunxi] Re: [PATCH v2 4/4] ARM: PWM: add allwinner sun8i pwm support.

[Maxime Ripard]

On Thu, May 17, 2018 at 10:48:58PM +0800, Hao Zhang wrote:
> 2018-05-15 19:17 GMT+08:00 Maxime Ripard :
> > Hi,
> >
> > On Mon, May 14, 2018 at 10:45:44PM +0800, Hao Zhang wrote:
> >> 2018-02-26 17:00 GMT+08:00 Maxime Ripard :
> >> > Thanks for respinning this serie. It looks mostly good, but you still
> >> > have a quite significant number of checkpatch (--strict) warnings that
> >> > you should address.
> >>
> >> Thanks for reviews :) ,i'm sorry for that, it will be fixed next
> >> time.  and, besides, in what situation were the checkpatch warning
> >> can be ignore？
> >
> > The only one that can be reasonably be ignored is the long line
> > warning, and only if complying to the limit would make it less easy to
> > understand.
> >
> >> >
> >> > On Sun, Feb 25, 2018 at 09:53:08PM +0800, hao_zhang wrote:
> >> >> +#define CAPTURE_IRQ_ENABLE_REG   0x0010
> >> >> +#define CFIE(ch) BIT(ch << 1 + 1)
> >> >> +#define CRIE(ch) BIT(ch << 1)
> >> >
> >> > You should also put your argument between parentheses here (and in all
> >> > your other macros).
> >>
> >> Do you mean like this ?
> >> #define CFIE(ch) BIT((ch) << 1 + 1)
> >> #define CRIE(ch) BIT((ch) << 1)
> >
> > Yep, exactly. Otherwise, if you do something like CRIE(1 + 1), the
> > result will be BIT(1 + 1 << 1), which will expand to 3, instead of 4.
> >
> > Also, CFIE looks a bit weird here, is it the offset that is
> > incremented, or the value? You should probably have parentheses to
> > make it explicit.
> 
> The vallue,
> BIT(((ch) << 1) + 1) It seem not very nice...
> 
> uhmm...
> In CAPTURE_IRQ_ENABLE_REG odd number is CFIE, even number is CRIE
> each channel has one CFIE and CRIE.
> 
> we can also describe like this:
> #define CFIE(ch) BIT((ch) * 2 + 1)
> #define CRIE(ch) BIT((ch) * 2)

That works for me.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: [PATCH 1/1] ARM:dts:sunxi: Add Olimex A20-SOM-EVB-eMMC board

[Maxime Ripard]

On Wed, May 16, 2018 at 02:38:08PM +0300, Stefan Mavrodiev wrote:
> With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
> Currently used card is KLMAG2GEND, wired to MMC2 slot.
> 
> Signed-off-by: Stefan Mavrodiev 

Applied, thanks!

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: [PATCH 1/1] ARM:dts:sunxi: Add Olimex A20-SOM-EVB-eMMC board

[Maxime Ripard]

On Thu, May 17, 2018 at 10:34:06AM +0300, Stefan Mavrodiev wrote:
> On 05/17/2018 10:25 AM, Stefan Wahren wrote:
> > Hi Stefan,
> > 
> > > Stefan Mavrodiev  hat am 16. Mai 2018 um 13:38 
> > > geschrieben:
> > > 
> > > 
> > > With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
> > > Currently used card is KLMAG2GEND, wired to MMC2 slot.
> > > 
> > > Signed-off-by: Stefan Mavrodiev 
> > > ---
> > >   arch/arm/boot/dts/Makefile |  1 +
> > >   .../arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts | 37 
> > > ++
> > >   2 files changed, 38 insertions(+)
> > >   create mode 100644 arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
> > > 
> > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > > index 1db91ec..7f1ee65 100644
> > > --- a/arch/arm/boot/dts/Makefile
> > > +++ b/arch/arm/boot/dts/Makefile
> > > @@ -959,6 +959,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
> > >   sun7i-a20-m3.dtb \
> > >   sun7i-a20-mk808c.dtb \
> > >   sun7i-a20-olimex-som-evb.dtb \
> > > + sun7i-a20-olimex-som-evb-emmc.dtb \
> > >   sun7i-a20-olimex-som204-evb.dtb \
> > >   sun7i-a20-olimex-som204-evb-emmc.dtb \
> > >   sun7i-a20-olinuxino-lime.dtb \
> > > diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts 
> > > b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
> > > new file mode 100644
> > > index 000..81ebc97
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
> > > @@ -0,0 +1,37 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
> > > + *
> > > + * Copyright (C) 2018 Olimex Ltd.
> > > + *   Author: Stefan Mavrodiev 
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "sun7i-a20-olimex-som-evb.dts"
> > > +
> > > +/ {
> > > +
> > > + model = "Olimex A20-Olimex-SOM-EVB-eMMC";
> > > + compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
> > the file Documentation/devicetree/bindings/arm/olimex.txt seems to be out 
> > of date. I cannot find any recent board compatible.
> > 
> > Didn't checkpatch complain about it?
>
> Yes it did. I didn't get is seriously because neither Olimex A20 based board
> is documented in the binding.

I guess we should fix that as well, but that can come in a subsequent
patch.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: [PATCH v6 7/7] sunxi: DT: A64: add Pine64-LTS support

[Maxime Ripard]

Hi Andre,

On Wed, May 16, 2018 at 09:00:50AM +0100, Andre Przywara wrote:
> The Pine64-LTS board is a new board version of the Pine64, though
> actually it's a non-SoM version of the SoPine and its baseboard.
> In contrast to the original Pine64 it features LPDDR3 DRAM, an eMMC
> socket and a SPI flash chip for storing firmware (like U-Boot).
> Add it as a variant to the existing SoPine defconfig, since from a
> software point of view they are really not different.
> 
> Signed-off-by: Andre Przywara 

I'm mostly fine with the changes you made, there's just one thing that
worries me a bit: the discoverability of the defconfig is pretty bad.

If you don't know it already, it's very difficult to see that the
defconfig you should use for the Pine64 LTS is the SoPine Baseboard
one.

Maybe we can add a symbolic link from the pine64_lts_defconfig to the
sopine one to make that obvious?

The bonus would be that if we ever need to split them for whatever
reason, we can do that without breaking each and every user setup.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature

[linux-sunxi] Re: [PATCH v4 3/3] ARM: dts: sun7i: Add support for the Ainol AW1 tablet

[Maxime Ripard]

On Mon, May 14, 2018 at 10:36:08PM +0200, Paul Kocialkowski wrote:
> > > + backlight: backlight {
> > > + compatible = "pwm-backlight";
> > > + pwms = < 0 5 PWM_POLARITY_INVERTED>;
> > > + brightness-levels = <  0   1   1   1   1   2   2   2
> > > +2   3   3   3   3   4   4   4
> > > +5   5   5   6   6   6   7   7
> > > +8   8   8   9   9   9  10  10
> > > +   10  11  11  12  12  12  13  13
> > > +   14  14  14  15  15  16  16  17
> > > +   17  17  18  18  19  19  20  20
> > > +   21  21  21  22  22  23  23  24
> > > +   24  25  25  26  26  27  27  28
> > > +   28  29  30  30  31  31  32  32
> > > +   33  33  34  35  35  36  36  37
> > > +   38  38  39  39  40  41  41  42
> > > +   43  43  44  44  45  46  47  47
> > > +   48  49  49  50  51  51  52  53
> > > +   54  54  55  56  57  57  58  59
> > > +   60  61  61  62  63  64  65  65
> > > +   66  67  68  69  70  71  71  72
> > > +   73  74  75  76  77  78  79  80
> > > +   81  82  83  84  85  86  87  88
> > > +   89  90  91  92  93  94  95  96
> > > +   97  98  99 101 102 103 104 105
> > > +  106 108 109 110 111 112 114 115
> > > +  116 117 119 120 121 123 124 125
> > > +  127 128 129 131 132 133 135 136
> > > +  138 139 141 142 144 145 147 148
> > > +  150 151 153 154 156 157 159 161
> > > +  162 164 166 167 169 171 173 174
> > > +  176 178 180 181 183 185 187 189
> > > +  191 192 194 196 198 200 202 204
> > > +  206 208 210 212 214 216 219 221
> > > +  223 225 227 229 232 234 236 238
> > > +  241 242 244 246 248 250 253 255>;
> > 
> > You kind of overdid it here :)
> > 
> > What I meant to say before was that if you have 10 elements (and you
> > really should have something in that magnitude) each step should
> > increase the perceived brightness by 10%.
> 
> Mhh I think 10 elements would fall too short to really depict the curve
> with appropriate precision. Given the usual size for brightness cursors
> in e.g. gnome-shell, it feels like a bigger number would be more
> appropriate. Let's make it to 100 with values from 0 to 255!
> 
> > In this particular case, I really think having something close to <0 4
> > 8 16 32 64 128 255> would be enough.
> > 
> > And in general, that kind of odd looking table without any more
> > context is just screaming for a comment :)
> 
> Noted, I will explain the idea, but probably without the exact formula
> that's really a nasty hack written down on a piece of paper sitting in
> my garbage at this point.

So no one will ever be able to understand where this sequence comes
from (yourself-in-two-years included). That sounds like a pretty bad
idea.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

-- 
You received this message because you are subscribed to the Google Groups 
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.


signature.asc
Description: PGP signature