[linux-sunxi] [PATCH] ARM: dts: sun7i: pcduino3-nano: enable RGMII RX/TX delay on PHY
The RX/TX delays for the Ethernet PHY on the Linksprite pcDuino 3 Nano
are configured in hardware, using resistors that are populated to pull
the RTL8211E's RXDLY/TXDLY pins low or high as needed.
phy-mode should be set to rgmii-id to reflect this. Previously it was
set to rgmii, which used to work but now results in the delays being
disabled again as a result of the bugfix in commit bbc4d71d6354 ("net:
phy: realtek: fix rtl8211e rx/tx delay config").
Tested on two pcDuino 3 Nano boards purchased in 2015. Without this fix,
Ethernet works unreliably on one board and doesn't work at all on the
other.
Fixes: 061035d456c9 ("ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board")
Signed-off-by: Adam Sampson
Reviewed-by: Andrew Lunn
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index fce2f7fcd084..bf38c66c1815 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Adam Sampson
+ * Copyright 2015-2020 Adam Sampson
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -115,7 +115,7 @@ {
pinctrl-names = "default";
pinctrl-0 = <_rgmii_pins>;
phy-handle = <>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
--
2.29.1
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[linux-sunxi] [PATCH] ARM: dts: sun7i: pcduino3-nano: enable RGMII RX/TX delay on PHY
The RX/TX delays for the Ethernet PHY on the Linksprite pcDuino 3 Nano
are configured in hardware, using resistors that are populated to pull
the RTL8211E's RXDLY/TXDLY pins low or high as needed.
phy-mode should be set to rgmii-id to reflect this. Previously it was
set to rgmii, which used to work but now results in the delays being
disabled again as a result of the bugfix in commit bbc4d71d6354 ("net:
phy: realtek: fix rtl8211e rx/tx delay config").
Tested on two pcDuino 3 Nano boards purchased in 2015. Without this fix,
Ethernet works unreliably on one board and doesn't work at all on the
other.
Fixes: 061035d456c9 ("ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board")
Signed-off-by: Adam Sampson
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index fce2f7fcd084..bf38c66c1815 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Adam Sampson
+ * Copyright 2015-2020 Adam Sampson
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -115,7 +115,7 @@ {
pinctrl-names = "default";
pinctrl-0 = <_rgmii_pins>;
phy-handle = <>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
--
2.29.1
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[linux-sunxi] sun4i-emac Ethernet problems with Linux 5.0
Hi all, On an A10 Cubieboard, there seems to be something odd going on with the sun4i-emac driver with 5.0... With 4.20.12, the driver correctly reports the switch's supported modes and negotiates 100baseT full duplex: # ethtool eth0 [...] Link partner advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full Link partner advertised pause frame use: No Link partner advertised auto-negotiation: Yes Speed: 100Mb/s Duplex: Full With 5.0.3, it ends up at 10baseT half duplex: Link partner advertised link modes: 10baseT/Half Link partner advertised pause frame use: No Link partner advertised auto-negotiation: No Speed: 10Mb/s Duplex: Half After it's been running for a while, I'm also getting a report like this (from emac_interrupt) in dmesg every few seconds: [ 571.518667] sun4i-emac 1c0b000.ethernet eth0: ab : 40004 [ 572.318132] sun4i-emac 1c0b000.ethernet eth0: ab : 40004 [ 572.707625] sun4i-emac 1c0b000.ethernet eth0: ab : 40008 [ 573.491298] sun4i-emac 1c0b000.ethernet eth0: ab : 40004 [ 574.399618] sun4i-emac 1c0b000.ethernet eth0: ab : 40004 [ 574.941244] sun4i-emac 1c0b000.ethernet eth0: ab : 40004 I can't see any non-trivial differences to either sun4i-emac or the A10 device trees between 4.20 and 5.0; any ideas what else might be causing this? Cheers, -- Adam Sampson <http://offog.org/> -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2] ASoC: sun4i-codec: use consistent names for PA controls
The power amplifier for the headphone output is called "the PA" and "the
headphone amplifier" in Allwinner's documentation for the A10 and A20.
sun4i-codec calls it "PA" in some places and "Pre-Amplifier" (which
isn't really accurate) in others, leading to user-visible controls with
different names referring to the same device.
When this driver implements audio input, it'll also need to expose
controls for the line and mic input preamps, so just referring to "the
Pre-Amplifier" will be ambiguous.
Change it to use "Power Amplifier" consistently for the power
amplifier's controls.
Signed-off-by: Adam Sampson <a...@offog.org>
---
Changes in v2:
- use "Power Amplifier" rather than "PA"
---
sound/soc/sunxi/sun4i-codec.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index bcbf4da..1bb896d 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -2,6 +2,7 @@
* Copyright 2014 Emilio López <emi...@elopez.com.ar>
* Copyright 2014 Jon Smirl <jonsm...@gmail.com>
* Copyright 2015 Maxime Ripard <maxime.rip...@free-electrons.com>
+ * Copyright 2015 Adam Sampson <a...@offog.org>
*
* Based on the Allwinner SDK driver, released under the GPL.
*
@@ -404,7 +405,7 @@ static const struct snd_kcontrol_new sun4i_codec_pa_mute =
static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
static const struct snd_kcontrol_new sun4i_codec_widgets[] = {
- SOC_SINGLE_TLV("PA Volume", SUN4I_CODEC_DAC_ACTL,
+ SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
sun4i_codec_pa_volume_scale),
};
@@ -452,12 +453,12 @@ static const struct snd_soc_dapm_widget
sun4i_codec_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
- /* Pre-Amplifier */
- SND_SOC_DAPM_MIXER("Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
+ /* Power Amplifier */
+ SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
sun4i_codec_pa_mixer_controls,
ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
- SND_SOC_DAPM_SWITCH("Pre-Amplifier Mute", SND_SOC_NOPM, 0, 0,
+ SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0,
_codec_pa_mute),
SND_SOC_DAPM_OUTPUT("HP Right"),
@@ -480,16 +481,16 @@ static const struct snd_soc_dapm_route
sun4i_codec_dapm_routes[] = {
{ "Left Mixer", NULL, "Mixer Enable" },
{ "Left Mixer", "Left DAC Playback Switch", "Left DAC" },
- /* Pre-Amplifier Mixer Routes */
- { "Pre-Amplifier", "Mixer Playback Switch", "Left Mixer" },
- { "Pre-Amplifier", "Mixer Playback Switch", "Right Mixer" },
- { "Pre-Amplifier", "DAC Playback Switch", "Left DAC" },
- { "Pre-Amplifier", "DAC Playback Switch", "Right DAC" },
+ /* Power Amplifier Routes */
+ { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" },
+ { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" },
+ { "Power Amplifier", "DAC Playback Switch", "Left DAC" },
+ { "Power Amplifier", "DAC Playback Switch", "Right DAC" },
- /* PA -> HP path */
- { "Pre-Amplifier Mute", "Switch", "Pre-Amplifier" },
- { "HP Right", NULL, "Pre-Amplifier Mute" },
- { "HP Left", NULL, "Pre-Amplifier Mute" },
+ /* Headphone Output Routes */
+ { "Power Amplifier Mute", "Switch", "Power Amplifier" },
+ { "HP Right", NULL, "Power Amplifier Mute" },
+ { "HP Left", NULL, "Power Amplifier Mute" },
};
static struct snd_soc_codec_driver sun4i_codec_codec = {
--
2.1.4
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[linux-sunxi] [PATCH] ASoC: sun4i-codec: use consistent names for PA controls
The power amplifier for the headphone output is called "the PA" and "the
headphone amplifier" in Allwinner's documentation for the A10 and A20.
sun4i-codec calls it "PA" in some places and "Pre-Amplifier" (which
isn't really accurate) in others, leading to user-visible controls with
different names referring to the same device.
When this driver implements audio input, it'll also need to expose
controls for the line and mic input preamps, so just referring to "the
Pre-Amplifier" will be ambiguous.
Change it to use "PA" consistently for the power amplifier.
Signed-off-by: Adam Sampson <a...@offog.org>
---
sound/soc/sunxi/sun4i-codec.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index bcbf4da..ff3304d 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -2,6 +2,7 @@
* Copyright 2014 Emilio López <emi...@elopez.com.ar>
* Copyright 2014 Jon Smirl <jonsm...@gmail.com>
* Copyright 2015 Maxime Ripard <maxime.rip...@free-electrons.com>
+ * Copyright 2015 Adam Sampson <a...@offog.org>
*
* Based on the Allwinner SDK driver, released under the GPL.
*
@@ -452,12 +453,12 @@ static const struct snd_soc_dapm_widget
sun4i_codec_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
- /* Pre-Amplifier */
- SND_SOC_DAPM_MIXER("Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
+ /* Headphone output power amplifier */
+ SND_SOC_DAPM_MIXER("PA", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
sun4i_codec_pa_mixer_controls,
ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
- SND_SOC_DAPM_SWITCH("Pre-Amplifier Mute", SND_SOC_NOPM, 0, 0,
+ SND_SOC_DAPM_SWITCH("PA Mute", SND_SOC_NOPM, 0, 0,
_codec_pa_mute),
SND_SOC_DAPM_OUTPUT("HP Right"),
@@ -480,16 +481,16 @@ static const struct snd_soc_dapm_route
sun4i_codec_dapm_routes[] = {
{ "Left Mixer", NULL, "Mixer Enable" },
{ "Left Mixer", "Left DAC Playback Switch", "Left DAC" },
- /* Pre-Amplifier Mixer Routes */
- { "Pre-Amplifier", "Mixer Playback Switch", "Left Mixer" },
- { "Pre-Amplifier", "Mixer Playback Switch", "Right Mixer" },
- { "Pre-Amplifier", "DAC Playback Switch", "Left DAC" },
- { "Pre-Amplifier", "DAC Playback Switch", "Right DAC" },
+ /* PA Mixer Routes */
+ { "PA", "Mixer Playback Switch", "Left Mixer" },
+ { "PA", "Mixer Playback Switch", "Right Mixer" },
+ { "PA", "DAC Playback Switch", "Left DAC" },
+ { "PA", "DAC Playback Switch", "Right DAC" },
/* PA -> HP path */
- { "Pre-Amplifier Mute", "Switch", "Pre-Amplifier" },
- { "HP Right", NULL, "Pre-Amplifier Mute" },
- { "HP Left", NULL, "Pre-Amplifier Mute" },
+ { "PA Mute", "Switch", "PA" },
+ { "HP Right", NULL, "PA Mute" },
+ { "HP Left", NULL, "PA Mute" },
};
static struct snd_soc_codec_driver sun4i_codec_codec = {
--
2.1.4
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[linux-sunxi] [PATCH] ARM: sun7i: dt: Enable audio codec on pcDuino V3 Nano
The pcDuino V3 Nano has a 3.5mm TRRS jack socket for audio, using the
CTIA standard pinout, connected to HPOUTL, HPOUTR, HPCOM/HPCOMFB and
MICIN1/VMIC (via appropriate RC networks) on the A20. The PH00 GPIO is
wired for headphone plug detection: it reads 0 when nothing's plugged
in, and 1 when a plug is inserted.
LINEINL/R and FMINL/R are not connected.
Signed-off-by: Adam Sampson <a...@offog.org>
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index 1757a6a..ddac732 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -82,6 +82,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
cpu-supply = <_dcdc2>;
};
--
2.1.4
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Re: [linux-sunxi] Kernel config for OTG on the A20?
Hi Siarhei, On Wed, Oct 14, 2015 at 12:03:49PM +0300, Siarhei Siamashka wrote: > This is what I used for testing USB OTG on pcDuino2: ... > The important parts were the CONFIG_MUSB_PIO_ONLY=y option (without > it enabled, I had DMA related errors in the kernel log) and the old > 'sunxi: initialize pinctrl before module init, fix "could not find > pctldev for node %s, deferring probe"' patch from willswang (without > it, there were these "deferred probe" errors also making USB OTG fail). A-ha! Yes, it looks like that patch is what I was missing -- with it, my dts patch works fine in both host and device modes. :) Thanks very much, -- Adam Sampson <a...@offog.org> <http://offog.org/> -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH] ARM: dts: sun7i: Enable USB DRC on pcDuino v3 Nano
The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the
pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V
bus (it's not switchable), and the OTG port's ID pin is connected to PH4
on the A20.
Tested successfully in both host and device modes.
Signed-off-by: Adam Sampson <a...@offog.org>
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index beac431..1757a6a 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -142,6 +142,10 @@
status = "okay";
};
+_sram {
+ status = "okay";
+};
+
{
ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
allwinner,pins = "PH2";
@@ -157,6 +161,13 @@
allwinner,pull = ;
};
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
allwinner,pins = "PD2";
allwinner,function = "gpio_out";
@@ -211,7 +222,15 @@
status = "okay";
};
+_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_id_detect_pin>;
+ usb0_id_det-gpio = < 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb1_vbus-supply = <_usb1_vbus>;
usb2_vbus-supply = <_usb1_vbus>;
status = "okay";
--
2.1.4
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[linux-sunxi] Kernel config for OTG on the A20?
Hi all,
What kernel config options do I need to turn on for OTG to work on the
A20? It doesn't appear to be enabled in sunxi_defconfig or
multi_v7_defconfig.
The patch below adds support for OTG for the pcDuino v3 Nano based on
the schematic, and I've verified that PH4 is indeed the ID pin by
reading it as a GPIO (it reads 0 with a host adaptor plugged in and 1
with nothing plugged in), but trying various likely-looking config
options hasn't resulted in it actually detecting devices, so I assume
there's something I'm meant to have enabled that I haven't...
Thanks,
Adam Sampson <a...@offog.org> <http://offog.org/>
---
(Not tested...)
The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the
pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V
bus (it's not switchable), and the OTG port's ID pin is connected to PH4
on the A20.
Signed-off-by: Adam Sampson <a...@offog.org>
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index beac431..1757a6a 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -142,6 +142,10 @@
status = "okay";
};
+_sram {
+ status = "okay";
+};
+
{
ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
allwinner,pins = "PH2";
@@ -157,6 +161,13 @@
allwinner,pull = ;
};
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
allwinner,pins = "PD2";
allwinner,function = "gpio_out";
@@ -211,7 +222,15 @@
status = "okay";
};
+_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_id_detect_pin>;
+ usb0_id_det-gpio = < 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb1_vbus-supply = <_usb1_vbus>;
usb2_vbus-supply = <_usb1_vbus>;
status = "okay";
--
2.1.4
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[linux-sunxi] [PATCH] ARM: dts: sun7i: Add regulator configuration for pcDuino v3 Nano
The power configuration on this board is the same as the pcDuino v3.
This will enable frequency/voltage scaling over the standard A20
operating points from 144 MHz to 960 MHz.
Tested using cpufreq-ljt-stress-test on two pcDuino v3 Nano boards; also
tested successfully with voltages reduced by 0.025 V.
Signed-off-by: Adam Sampson <a...@offog.org>
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 35 ---
1 file changed, 31 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index ee85e07..1757a6a 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -82,6 +82,10 @@
status = "okay";
};
+ {
+ cpu-supply = <_dcdc2>;
+};
+
{
status = "okay";
};
@@ -108,13 +112,9 @@
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
@@ -182,6 +182,33 @@
status = "okay";
};
+#include "axp209.dtsi"
+
+_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "vdd-cpu";
+};
+
+_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <140>;
+ regulator-name = "vdd-int-pll";
+};
+
+_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ regulator-name = "avcc";
+};
+
/* A single regulator (U24) powers both USB host ports. */
_usb1_vbus {
pinctrl-0 = <_vbus_pin_pcduino3_nano>;
--
2.1.4
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Re: [linux-sunxi] [PATCH] ARM: dts: sun7i: Correct USB regulators on pcDuino v3 Nano
Chen-Yu Tsai <w...@csie.org> writes:
> Since Siarhei spotted the issue, maybe add a Reported-by tag where credit
> is due?
Will do.
>> _ahci_5v {
>> + pinctrl-names = "default";
[twice]
>
> This is already in sunxi-common-regulators.dtsi.
> No need to add it again.
OK -- fixed. v2 incoming.
Thanks,
--
Adam Sampson <a...@offog.org> <http://offog.org/>
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[linux-sunxi] [PATCH v2] ARM: dts: sun7i: Correct USB regulators on pcDuino v3 Nano
The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
single RT9701GB regulator, which has its enable input tied to the A20's
PD2 pin, pulled up to 3v3 via a 10k resistor.
However, the script.bin that shipped with the device listed PH11 and PH3
as Vbus control pins for the two USB ports. Neither of these are
actually connected to anything.
Siarhei Siamashka spotted this problem while reviewing the other
LinkSprite boards. This patch fixes it by only defining a single
regulator, controlled by PD2. Testing shows that the USB ports are now
(correctly) only powered up once the USB PHY driver is loaded.
Reported-by: Siarhei Siamashka <siarhei.siamas...@gmail.com>
Signed-off-by: Adam Sampson <a...@offog.org>
---
Changes in v2:
- Add Reported-by line
- Remove redundant pinctrl-names entries
---
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index 5361fce..b304778 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -158,7 +158,7 @@
};
usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
- allwinner,pins = "PH11";
+ allwinner,pins = "PD2";
allwinner,function = "gpio_out";
allwinner,drive = ;
allwinner,pull = ;
@@ -171,13 +171,10 @@
status = "okay";
};
+/* A single regulator (U24) powers both USB host ports. */
_usb1_vbus {
pinctrl-0 = <_vbus_pin_pcduino3_nano>;
- gpio = < 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
- status = "okay";
-};
-
-_usb2_vbus {
+ gpio = < 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
status = "okay";
};
@@ -189,6 +186,6 @@
{
usb1_vbus-supply = <_usb1_vbus>;
- usb2_vbus-supply = <_usb2_vbus>;
+ usb2_vbus-supply = <_usb1_vbus>;
status = "okay";
};
--
2.1.4
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[linux-sunxi] [PATCH] sunxi: Make CONFIG_DRAM_TPR3 apply to sun[57]i
The tpr3 (timing skew) parameter is used in all supported versions of
the sunxi DRAM controller, but it was only enabled for sun4i in
47e3501a76894f4ba08bc61f33774bd5d39ff464.
Signed-off-by: Adam Sampson a...@offog.org
---
board/sunxi/dram_sun5i_auto.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c
index e52d54c..660b18e 100644
--- a/board/sunxi/dram_sun5i_auto.c
+++ b/board/sunxi/dram_sun5i_auto.c
@@ -24,7 +24,7 @@ static struct dram_para dram_para = {
# include dram_timings_sun4i.h
.active_windowing = 1,
#endif
- .tpr3 = 0,
+ .tpr3 = CONFIG_DRAM_TPR3,
.tpr4 = 0,
.tpr5 = 0,
.emr1 = CONFIG_DRAM_EMR1,
--
1.7.10.4
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[linux-sunxi] [PATCH v3] sunxi: Add Linksprite_pcDuino3_Nano board / defconfig
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and another for power in, HDMI, SATA, 5V power for SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector. Like the BananaPi, this board needs GMAC_TX_DELAY set to 3 in order for GMAC to work reliably at gigabit speeds. For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano Changed in v3: - add CONFIG_GMAC_TX_DELAY=3, which corresponds to a patch in LinkSprite's A20 kernel; testing shows the performance is now much better at 1000M Signed-off-by: Adam Sampson a...@offog.org --- board/sunxi/MAINTAINERS| 5 + configs/Linksprite_pcDuino3_Nano_defconfig | 11 +++ 2 files changed, 16 insertions(+) create mode 100644 configs/Linksprite_pcDuino3_Nano_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 9050059..44f57ad 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -81,6 +81,11 @@ M: Zoltan Herpai wigy...@uid0.hu S: Maintained F: configs/Linksprite_pcDuino_defconfig +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson a...@offog.org +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin mamli...@gmail.com S: Maintained diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig new file mode 100644 index 000..4baba14 --- /dev/null +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI +CONFIG_FDTFILE=sun7i-a20-pcduino3-nano.dtb +CONFIG_GMAC_TX_DELAY=3 +CONFIG_USB1_VBUS_PIN=PH11 ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 -- 2.2.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH] ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board
On Tue, Jan 27, 2015 at 06:00:35PM +0100, Maxime Ripard wrote: How about pcduino3-nano:green:usr-led3/4? Or ...:usr1/2, and a comment in the .dts explaining how they're labelled on the board? The latter looks better yes. tx and rx would do too, if you know what tx and what rx we're talking about here. I've changed it to usr1/2 with comments. (I don't know if they were intended to be TX/RX; the documentation doesn't suggest so.) They're multipurpose pins on Arduino-compatible headers: ... So should we [...] None of the above, if there's no hardware default, we won't enforce any default either. This is a case for the DT overlays. OK -- that simplifies it quite a bit, then. v3 of the patch incoming! Thanks very much, -- Adam Sampson a...@offog.org http://offog.org/ -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH] ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board
Hi Maxime, On Mon, Jan 26, 2015 at 11:09:21AM +0100, Maxime Ripard wrote: If you read Documentation/leds/leds-class.txt, the pattern to follow is: devicename:colour:function so it should rather be pcduino3-nano:green:usr1 and usr2, or some other thing. How about pcduino3-nano:green:usr-led3/4? Or ...:usr1/2, and a comment in the .dts explaining how they're labelled on the board? There are a couple of other sunxi boards that have the same problem (multiple user-controllable LEDs of the same colour): sun4i-a10-marsboard.dts: label = marsboard:red1:usr; sun4i-a10-marsboard.dts: label = marsboard:red2:usr; sun4i-a10-marsboard.dts: label = marsboard:red3:usr; sun4i-a10-marsboard.dts: label = marsboard:red4:usr; sun9i-a80-optimus.dts: label = optimus:led2:usr; sun9i-a80-optimus.dts: label = optimus:led4:usr; I can send a patch for those if you'd like as well? Should there be aliases for I2C as well, since the same situation applies (i2c0 and i2c2)? Yep. Added. More generally, is it correct to add nodes like these (uart2, spi0, i2c2) for features that appear on the Arduino GPIO headers? If those pins are specifically dedicated to this feature, then yes. They're multipurpose pins on Arduino-compatible headers: http://learn.linksprite.com/wp-content/uploads/2014/10/pcDuino3-Nano_header-Model.jpg How you want them to be configured will depend on what you have plugged in; for example, some Arduino add-on boards will expect J11 P1/2 to be serial RX/TX and some will expect them to be GPIOs. So should we configure i2c2 etc. by default (and let the user turn them into GPIOs if required), or just provide the GPIOs (and require the user to adjust the .dts)? Cheers, -- Adam Sampson a...@offog.org http://offog.org/ -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2] ARM: dts: sun7i: Add dts file for pcDuino 3 Nano board
Add support for the LinkSprite pcDuino 3 Nano board. This is a low-cost
Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM,
4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and
another for power in, HDMI, SATA, 5V power for SATA devices, gigabit
Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector.
For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano
Signed-off-by: Adam Sampson a...@offog.org
---
arch/arm/boot/dts/Makefile|3 +-
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 212 +
2 files changed, 214 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7df26a2..c025724 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -479,7 +479,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-micro.dtb \
- sun7i-a20-pcduino3.dtb
+ sun7i-a20-pcduino3.dtb \
+ sun7i-a20-pcduino3-nano.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
new file mode 100644
index 000..6055de5
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2015 Adam Sampson a...@offog.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include sun7i-a20.dtsi
+#include sunxi-common-regulators.dtsi
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+/ {
+ model = LinkSprite pcDuino3 Nano;
+ compatible = linksprite,pcduino3-nano, allwinner,sun7i-a20;
+
+ aliases {
+ serial0 = uart0;
+ serial1 = uart2;
+ };
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_pcduino3_nano;
+
+ led3 {
+ label = pcduino3-nano:led3:usr;
+ gpios = pio 7 16 GPIO_ACTIVE_LOW; /* PH16 */
+ };
+
+ led4 {
+ label = pcduino3-nano:led4:usr;
+ gpios = pio 7 15 GPIO_ACTIVE_LOW; /* PH15 */
+ };
+ };
+};
+
+ahci {
+ target-supply = reg_ahci_5v;
+ status = okay;
+};
+
+ehci0 {
+ status = okay;
+};
+
+ehci1 {
+ status = okay;
+};
+
+gmac {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_rgmii_a;
+ phy = phy1;
+ phy-mode = rgmii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1
[linux-sunxi] [PATCH] sunxi: Add Linksprite_pcDuino3_Nano board / defconfig
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and another for power in, HDMI, SATA, 5V power for SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector. For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano Signed-off-by: Adam Sampson a...@offog.org --- board/sunxi/MAINTAINERS|5 + configs/Linksprite_pcDuino3_Nano_defconfig | 11 +++ 2 files changed, 16 insertions(+) create mode 100644 configs/Linksprite_pcDuino3_Nano_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 743e7f5..479d147 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -100,3 +100,8 @@ MELE M5 BOARD M: Ian Campbell i...@hellion.org.uk S: Maintained F: configs/Mele_M5_defconfig + +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson a...@offog.org +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig new file mode 100644 index 000..22435eb --- /dev/null +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI +CONFIG_FDTFILE=sun7i-a20-pcduino3-nano.dtb +CONFIG_USB1_VBUS_PIN=PH11 ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_TARGET_PCDUINO3_NANO=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 -- 1.7.10.4 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH] sunxi: Add Linksprite_pcDuino3_Nano board / defconfig
Hi Christophe, On Mon, Jan 26, 2015 at 07:15:20AM -0800, christophe.le.rou...@gmail.com wrote: +CONFIG_SYS_EXTRA_OPTIONS=AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI What do you think about adding RGMII in the CONFIG_SYS_EXTRA_OPTIONS like other gigabit A20 board ? Good catch -- I'll respin the patch! Thanks very much, -- Adam Sampson a...@offog.org http://offog.org/ -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2] sunxi: Add Linksprite_pcDuino3_Nano board / defconfig
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and another for power in, HDMI, SATA, 5V power for SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector. For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano Signed-off-by: Adam Sampson a...@offog.org --- board/sunxi/MAINTAINERS| 5 + configs/Linksprite_pcDuino3_Nano_defconfig | 11 +++ 2 files changed, 16 insertions(+) create mode 100644 configs/Linksprite_pcDuino3_Nano_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 743e7f5..479d147 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -100,3 +100,8 @@ MELE M5 BOARD M: Ian Campbell i...@hellion.org.uk S: Maintained F: configs/Mele_M5_defconfig + +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson a...@offog.org +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig new file mode 100644 index 000..e3ea713 --- /dev/null +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI +CONFIG_FDTFILE=sun7i-a20-pcduino3-nano.dtb +CONFIG_USB1_VBUS_PIN=PH11 ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_TARGET_PCDUINO3_NANO=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 -- 2.2.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
