[linux-sunxi] MIPI CSI MCK on PE16 of A31
Hi, We have one more query regarding A31's MIPI CSI interface. In datasheet, GPIO PE16 pin is mentioned as MCSI-MCLK i.e. Master clock for MIPI CSI. There is no description about this clock. Is this clock input for MIPI interface? Is it absolutely necessary for functioning of MIPI CSI module? If yes, what should be it's value? Are there any constraints like it should be generated from CMOS sensor i.e synchronous to MIPI input etc.? In HummingBird board, we see that this clock is routed to CMOS sensor's connector. So we cannot make out about how to feed clock to this pin. On our HW, this pin is left floating. Can this be reason for MIPI CSI interface not functioning? We checked in linux code also but didn't find any reference to this clock in clock framework. But if we see config pin of this PE16 IO, it is configured for MIPI CSI clock. Please let us know if you have any clues/information. Thank you in advance. Thanks and regards, Satyajit -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] MIPI CSI Issues on A31 | Trying with TC358743 (HDMI to MIPI CSI2 Bridge IC)
Hi, We are using A31 based board which is derived from Merrii HummingBird. On this board, we want to get HDMI capture up using TC358743 (HDMI to MIPI CSI2 Bridge IC). This IC interfaces to MIPI CSI port of A31. We have added TC358743 sub-dev driver and it behaves as if CMOS sensor is connected to the A31. Calls which are not applicable are just stubs. Presently, we are not able to get any frames on A31 side. When we checked MIPI DPHY registers, we see that clock and data lanes are active and toggling in LP and HS mode as expected. But MIPI interface is not showing any packet reception. We are more or less sure about TC358743 settings as they have come from vendor. We have also checked all MIPI/CSI settings and they appear to be fine. Since data is being received till DPHY but not in MIPI we are not sure if we are missing any other board specific settings required to get MIPI interface working e.g. PRCM, MIPI peripheral PLL clock, On board PMIC settings, MIPI IO pins enabling etc. If you have any inputs/pointers about the same, please let us know. Also, please let us know if any MIPI sensor is validated with A31. Exact CMOS sensor part number would help. Is MIPI driver (/drivers/media/video/sunxi-vfe/) complete? Is new CMOS sensor expected to work just by hooking new MIPI sub-device? Or some more changes in MIPI driver at other places is needed? We see that in 'bsp_mipi_csi_set_dphy_timing' function of drivers/media/video/sunxi-vfe/bsp_mipi_csi.c file, functions like 'dphy_rx_set_entm_to_enrx_dly' and 'dphy_rx_set_lp_ulps_wp' are configured with some default values. Do they need to be changed depending on frequency, lanes, resolution etc? DPHY_CLK is used in vfe.c and it is hardcoded to 150MHz. Should this be hardcoded or matched with input MIPI clock? Please let us know. Apologies for so many questions. We are new to this platform. Any inputs/pointers will be very helpful. Thanks and regards, Satyajit -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] MIPI CSI capture issues on A31
Hi, We are using A31 based board which is derived from Merrii HummingBird. On this board, we want to get HDMI capture up using TC358743 (HDMI to MIPI CSI2 Bridge IC). This IC interfaces to MIPI CSI port of A31. We have added TC358743 sub-dev driver and it behaves as if CMOS sensor is connected to the A31. Calls which are not applicable are just stubs. Presently, we are not able to get any frames on A31 side. When we checked MIPI DPHY registers, we see that clock and data lanes are active and toggling in LP and HS mode as expected. But MIPI interface is not showing any packet reception. We are more or less sure about TC358743 settings as they have come from vendor. We have also checked all MIPI/CSI settings and they appear to be fine. Since data is being received till DPHY but not in MIPI we are not sure if we are missing any other board specific settings required to get MIPI interface working e.g. PRCM, MIPI peripheral PLL clock, On board PMIC settings, MIPI IO pins enabling etc. If you have any inputs/pointers about the same, please let us know. Also, please let us know if any MIPI sensor is validated with A31. Exact CMOS sensor part number would help. Is MIPI driver (/drivers/media/video/sunxi-vfe/) complete? Is new CMOS sensor expected to work just by hooking new MIPI sub-device? Or some more changes in MIPI driver at other places is needed? We see that in 'bsp_mipi_csi_set_dphy_timing' function of drivers/media/video/sunxi-vfe/bsp_mipi_csi.c file, functions like 'dphy_rx_set_entm_to_enrx_dly' and 'dphy_rx_set_lp_ulps_wp' are configured with some default values. Do they need to be changed depending on frequency, lanes, resolution etc? DPHY_CLK is used in vfe.c and it is hardcoded to 150MHz. Should this be hardcoded or matched with input MIPI clock? Please let us know. Apologies for so many questions. We are new to this platform. Any inputs/pointers will be very helpful. Thanks and regards, Satyajit -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
