Re: [linux-sunxi] Re: [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef

[Vishnu Patekar]

Even for the single core cortex-a7, SMP bit should be set before
enabling MMU and cache.

Reference: Cortex A7 r0p5 TRM. section 4.3.31.

On Fri, Jan 13, 2017 at 12:41 PM, Icenowy Zheng  wrote:
>
>
> 13.01.2017, 09:34, "Andre Przywara" :
>> Instead of enumerating all SoC families that need that bit set, let's
>> just express this more clearly: The SMP bits needs to be set on
>> SMP capable ARMv7 CPUs. It's much easier to Kconfig to express it the
>> other way round, so we use ! NO_SMP and ! ARM64.
>
> How about single-core Cortex-A7?
>
>>
>> Signed-off-by: Andre Przywara 
>> ---
>>  arch/arm/mach-sunxi/board.c | 5 +
>>  board/sunxi/Kconfig | 6 ++
>>  2 files changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>> index 58fbacb..5a63124 100644
>> --- a/arch/arm/mach-sunxi/board.c
>> +++ b/arch/arm/mach-sunxi/board.c
>> @@ -180,10 +180,7 @@ void s_init(void)
>>  /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
>>  #endif
>>
>> -#if defined CONFIG_MACH_SUN6I || \
>> - defined CONFIG_MACH_SUN7I || \
>> - defined CONFIG_MACH_SUN8I || \
>> - defined CONFIG_MACH_SUN9I
>> +#if !defined(CONFIG_SUNXI_NO_SMP) && !defined(CONFIG_ARM64)
>>  /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg 
>> */
>>  asm volatile(
>>  "mrc p15, 0, r0, c1, c0, 1\n"
>> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
>> index 37b4252..79b6fa7 100644
>> --- a/board/sunxi/Kconfig
>> +++ b/board/sunxi/Kconfig
>> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT
>>  config SPL_SERIAL_SUPPORT
>>  default y
>>
>> +config SUNXI_NO_SMP
>> + bool
>> + default n
>> +
>>  # Note only one of these may be selected at a time! But hidden choices are
>>  # not supported by Kconfig
>>  config SUNXI_GEN_SUN4I
>> @@ -50,12 +54,14 @@ choice
>>  config MACH_SUN4I
>>  bool "sun4i (Allwinner A10)"
>>  select CPU_V7
>> + select SUNXI_NO_SMP
>>  select SUNXI_GEN_SUN4I
>>  select SUPPORT_SPL
>>
>>  config MACH_SUN5I
>>  bool "sun5i (Allwinner A13)"
>>  select CPU_V7
>> + select SUNXI_NO_SMP
>>  select SUNXI_GEN_SUN4I
>>  select SUPPORT_SPL
>>
>> --
>> 2.8.2
>
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Re: [linux-sunxi] [PATCH v2 0/3] clk: sunxi-ng: Add the A83T clocks

[Vishnu Patekar]

Hello Jean-Francois Moine,

Thanks for followup patches for a83t modern clock.

well, this patch series does not apply on sunxi/for-next.



Regards,
Vishnu Pateakr

On Sun, Jun 12, 2016 at 1:39 AM, Jean-Francois Moine 
wrote:

> This patch series adds the clocks of the sunxi A83T in the "modern"
> clock framework proposed by Maxime Ripard.
> It applies on the V2 of his patch series.
>
> It is currently being tested on a Banana Pi M3 with the legacy u-boot.
> - working:
> mmc0
> mmc2 (eMMC) but slow clock
> ths
> uart0
> usb0
> - not working:
> mmc1 (wifi/bt)
> video (machine freeze on reading/writing the DE I/O memory)
> - not yet tested
> audio
> prcm
>
> Jean-Francois Moine (3):
>   clk: sunxi-ng: Add N-D-M-P-factor clock support
>   clk: sunxi-ng: Add the A83T clocks and resets
>   dt: sun8i: Define the clocks of the A83T
>
>  arch/arm/boot/dts/sun8i-a83t.dtsi  |  18 +-
>  drivers/clk/sunxi-ng/Makefile  |   3 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-a83t.c  | 675
> +
>  drivers/clk/sunxi-ng/ccu_common.h  |   1 +
>  drivers/clk/sunxi-ng/ccu_ndmp.c| 239 
>  drivers/clk/sunxi-ng/ccu_ndmp.h|  96 +
>  include/dt-bindings/clock/sun8i-a83t.h | 150 
>  include/dt-bindings/reset/sun8i-a83t.h |  94 +
>  8 files changed, 1270 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu_ndmp.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu_ndmp.h
>  create mode 100644 include/dt-bindings/clock/sun8i-a83t.h
>  create mode 100644 include/dt-bindings/reset/sun8i-a83t.h
>
> --
> 2.8.4
>
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[linux-sunxi] Re: [PATCH v2] clk: sunxi: predivider handling for factors clock

[Vishnu Patekar]

Hello Maxime,

On 2 May 2016 19:13, "Maxime Ripard" 
wrote:
>
> Hi,
>
> On Wed, Apr 20, 2016 at 12:47:46AM +0800, Vishnu Patekar wrote:
> > For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.
> > To handle this, this patch adds predivider table with parent index,
> > prediv shift and width, parents with predivider will have nonzero width.
> >
> > Rate adjustment is moved from clock specific recalc function to generic
> > factors recalc. Also, adds prediv table for a31.
> >
> > Signed-off-by: Vishnu Patekar 
> > ---
> >  drivers/clk/sunxi/clk-factors.c | 31 +++
> >  drivers/clk/sunxi/clk-factors.h | 10 +-
> >  drivers/clk/sunxi/clk-sunxi.c   | 31 +--
> >  3 files changed, 33 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/clk/sunxi/clk-factors.c
b/drivers/clk/sunxi/clk-factors.c
> > index ddefe96..8f3b637 100644
> > --- a/drivers/clk/sunxi/clk-factors.c
> > +++ b/drivers/clk/sunxi/clk-factors.c
> > @@ -45,10 +45,12 @@ static unsigned long clk_factors_recalc_rate(struct
clk_hw *hw,
> >unsigned long parent_rate)
> >  {
> >   u8 n = 1, k = 0, p = 0, m = 0;
> > + u8 par_index = 0;
> >   u32 reg;
> >   unsigned long rate;
> >   struct clk_factors *factors = to_clk_factors(hw);
> >   const struct clk_factors_config *config = factors->config;
> > + const struct clk_factors_prediv *prediv = factors->prediv_config;
> >
> >   /* Fetch the register value */
> >   reg = readl(factors->reg);
> > @@ -63,24 +65,16 @@ static unsigned long clk_factors_recalc_rate(struct
clk_hw *hw,
> >   if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
> >   p = FACTOR_GET(config->pshift, config->pwidth, reg);
> >
> > - if (factors->recalc) {
> > - struct factors_request factors_req = {
> > - .parent_rate = parent_rate,
> > - .n = n,
> > - .k = k,
> > - .m = m,
> > - .p = p,
> > - };
> > -
> > + if (prediv) {
> >   /* get mux details from mux clk structure */
> >   if (factors->mux)
> > - factors_req.parent_index =
> > - (reg >> factors->mux->shift) &
> > - factors->mux->mask;
> > -
> > - factors->recalc(&factors_req);
> > + par_index = (reg >> factors->mux->shift) &
> > + factors->mux->mask;
> >
> > - return factors_req.rate;
> > + if (prediv[par_index].width !=
SUNXI_FACTORS_NOT_APPLICABLE) {
> > + m = FACTOR_GET(prediv[par_index].shift,
> > + prediv[par_index].width, reg);
> > + }
> >   }
> >
> >   /* Calculate the rate */
> > @@ -102,8 +96,12 @@ static int clk_factors_determine_rate(struct clk_hw
*hw,
> >   for (i = 0; i < num_parents; i++) {
> >   struct factors_request factors_req = {
> >   .rate = req->rate,
> > - .parent_index = i,
> >   };
> > +
> > + if (factors->prediv_config)
> > + factors_req.prediv_width =
> > +
 factors->prediv_config[i].width;
> > +
> >   parent = clk_hw_get_parent_by_index(hw, i);
> >   if (!parent)
> >   continue;
> > @@ -211,6 +209,7 @@ struct clk *sunxi_factors_register(struct
device_node *node,
> >   /* set up factors properties */
> >   factors->reg = reg;
> >   factors->config = data->table;
> > + factors->prediv_config = data->prediv_table;
> >   factors->get_factors = data->getter;
> >   factors->recalc = data->recalc;
> >   factors->lock = lock;
> > diff --git a/drivers/clk/sunxi/clk-factors.h
b/drivers/clk/sunxi/clk-factors.h
> > index 1e63c5b..b1b7745 100644
> > --- a/drivers/clk/sunxi/clk-factors.h
> > +++ b/drivers/clk/sunxi/clk-factors.h
> > @@ -18,10 +18,16 @@ struct clk_factors_config {
> >   u8 n_start;
> >  };
> >
> > +struct clk_factors_prediv {
> > + u8 parent_index;
> > + u8 shift;
> > + u8 width;
> > +};
&

[linux-sunxi] Re: [PATCH v2] clk: sunxi: predivider handling for factors clock

[Vishnu Patekar]

Hello Wens,

On Mon, Apr 25, 2016 at 10:51 PM, Chen-Yu Tsai  wrote:
> Hi,
>
> On Wed, Apr 20, 2016 at 12:47 AM, Vishnu Patekar
>  wrote:
>> For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.
>> To handle this, this patch adds predivider table with parent index,
>> prediv shift and width, parents with predivider will have nonzero width.
>>
>> Rate adjustment is moved from clock specific recalc function to generic
>> factors recalc. Also, adds prediv table for a31.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  drivers/clk/sunxi/clk-factors.c | 31 +++
>>  drivers/clk/sunxi/clk-factors.h | 10 +-
>>  drivers/clk/sunxi/clk-sunxi.c   | 31 +--
>>  3 files changed, 33 insertions(+), 39 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi/clk-factors.c 
>> b/drivers/clk/sunxi/clk-factors.c
>> index ddefe96..8f3b637 100644
>> --- a/drivers/clk/sunxi/clk-factors.c
>> +++ b/drivers/clk/sunxi/clk-factors.c
>> @@ -45,10 +45,12 @@ static unsigned long clk_factors_recalc_rate(struct 
>> clk_hw *hw,
>>  unsigned long parent_rate)
>>  {
>> u8 n = 1, k = 0, p = 0, m = 0;
>> +   u8 par_index = 0;
>> u32 reg;
>> unsigned long rate;
>> struct clk_factors *factors = to_clk_factors(hw);
>> const struct clk_factors_config *config = factors->config;
>> +   const struct clk_factors_prediv *prediv = factors->prediv_config;
>>
>> /* Fetch the register value */
>> reg = readl(factors->reg);
>> @@ -63,24 +65,16 @@ static unsigned long clk_factors_recalc_rate(struct 
>> clk_hw *hw,
>> if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
>> p = FACTOR_GET(config->pshift, config->pwidth, reg);
>>
>> -   if (factors->recalc) {
>> -   struct factors_request factors_req = {
>> -   .parent_rate = parent_rate,
>> -   .n = n,
>> -   .k = k,
>> -   .m = m,
>> -   .p = p,
>> -   };
>> -
>> +   if (prediv) {
>> /* get mux details from mux clk structure */
>> if (factors->mux)
>> -   factors_req.parent_index =
>> -   (reg >> factors->mux->shift) &
>> -   factors->mux->mask;
>> -
>> -   factors->recalc(&factors_req);
>> +   par_index = (reg >> factors->mux->shift) &
>> +   factors->mux->mask;
>>
>> -   return factors_req.rate;
>> +   if (prediv[par_index].width != SUNXI_FACTORS_NOT_APPLICABLE) 
>> {
>> +   m = FACTOR_GET(prediv[par_index].shift,
>> +   prediv[par_index].width, reg);
>> +   }
>> }
>>
>> /* Calculate the rate */
>> @@ -102,8 +96,12 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
>> for (i = 0; i < num_parents; i++) {
>> struct factors_request factors_req = {
>> .rate = req->rate,
>> -   .parent_index = i,
>> };
>> +
>> +   if (factors->prediv_config)
>> +   factors_req.prediv_width =
>> +   
>> factors->prediv_config[i].width;
>> +
>> parent = clk_hw_get_parent_by_index(hw, i);
>> if (!parent)
>> continue;
>> @@ -211,6 +209,7 @@ struct clk *sunxi_factors_register(struct device_node 
>> *node,
>> /* set up factors properties */
>> factors->reg = reg;
>> factors->config = data->table;
>> +   factors->prediv_config = data->prediv_table;
>> factors->get_factors = data->getter;
>> factors->recalc = data->recalc;
>> factors->lock = lock;
>> diff --git a/drivers/clk/sunxi/clk-factors.h 
>> b/drivers/clk/sunxi/clk-factors.h
>> index 1e63c5b..b1b7745 100644
>> --- a/drivers/clk/sunxi/clk-factors.h
>> +++ b/drivers/clk/sunxi/clk-factors.h
>> @@ -18,10 +18,16 @@ struct clk_factors_config {
>> u8 n_start;
>>  };
>>
>> +struct cl

[linux-sunxi] [PATCH v2] sunxi factors clock predivider handling

[Vishnu Patekar]

For allwinner A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.

Currently, it's being handled in clock specific functions. 

A83t ahb1 and a31 ahb1 are similar clocks except a83t parent index 0b10 and 0b11
are pll6/prediv and a31 ahb1 parent index 0x11 is pll6/prediv.
with only this change, code duplication was needed.

To handle this, this patch adds predivider table with parent index, prediv 
shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic factors
recalc. clock specific recalc was currently used only by a31 ahb1.

For getter, it differentiates parents with prediv, with non-zero prediv width.

I've tested this patch on a83t bpi-m3 board. I do not have a31 device.
As there are dependencies on other a83t patches, a83t changes are not included
in this patch, It'll be included in separate patch.


v1->v2 Changes:
1. As 'kbuild test robot' reported build failure due to dependency on patches,
Combined two patches in v1 into single patch.


Vishnu Patekar (1):
  clk: sunxi: predivider handling for factors clock

 drivers/clk/sunxi/clk-factors.c | 31 +++
 drivers/clk/sunxi/clk-factors.h | 10 +-
 drivers/clk/sunxi/clk-sunxi.c   | 31 +--
 3 files changed, 33 insertions(+), 39 deletions(-)

-- 
1.9.1

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[linux-sunxi] [PATCH v2] clk: sunxi: predivider handling for factors clock

[Vishnu Patekar]

For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.
To handle this, this patch adds predivider table with parent index,
prediv shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic
factors recalc. Also, adds prediv table for a31.

Signed-off-by: Vishnu Patekar 
---
 drivers/clk/sunxi/clk-factors.c | 31 +++
 drivers/clk/sunxi/clk-factors.h | 10 +-
 drivers/clk/sunxi/clk-sunxi.c   | 31 +--
 3 files changed, 33 insertions(+), 39 deletions(-)

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index ddefe96..8f3b637 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -45,10 +45,12 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw 
*hw,
 unsigned long parent_rate)
 {
u8 n = 1, k = 0, p = 0, m = 0;
+   u8 par_index = 0;
u32 reg;
unsigned long rate;
struct clk_factors *factors = to_clk_factors(hw);
const struct clk_factors_config *config = factors->config;
+   const struct clk_factors_prediv *prediv = factors->prediv_config;
 
/* Fetch the register value */
reg = readl(factors->reg);
@@ -63,24 +65,16 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw 
*hw,
if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
p = FACTOR_GET(config->pshift, config->pwidth, reg);
 
-   if (factors->recalc) {
-   struct factors_request factors_req = {
-   .parent_rate = parent_rate,
-   .n = n,
-   .k = k,
-   .m = m,
-   .p = p,
-   };
-
+   if (prediv) {
/* get mux details from mux clk structure */
if (factors->mux)
-   factors_req.parent_index =
-   (reg >> factors->mux->shift) &
-   factors->mux->mask;
-
-   factors->recalc(&factors_req);
+   par_index = (reg >> factors->mux->shift) &
+   factors->mux->mask;
 
-   return factors_req.rate;
+   if (prediv[par_index].width != SUNXI_FACTORS_NOT_APPLICABLE) {
+   m = FACTOR_GET(prediv[par_index].shift,
+   prediv[par_index].width, reg);
+   }
}
 
/* Calculate the rate */
@@ -102,8 +96,12 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
for (i = 0; i < num_parents; i++) {
struct factors_request factors_req = {
.rate = req->rate,
-   .parent_index = i,
};
+
+   if (factors->prediv_config)
+   factors_req.prediv_width =
+   factors->prediv_config[i].width;
+
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
@@ -211,6 +209,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
/* set up factors properties */
factors->reg = reg;
factors->config = data->table;
+   factors->prediv_config = data->prediv_table;
factors->get_factors = data->getter;
factors->recalc = data->recalc;
factors->lock = lock;
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 1e63c5b..b1b7745 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -18,10 +18,16 @@ struct clk_factors_config {
u8 n_start;
 };
 
+struct clk_factors_prediv {
+   u8 parent_index;
+   u8 shift;
+   u8 width;
+};
+
 struct factors_request {
unsigned long rate;
unsigned long parent_rate;
-   u8 parent_index;
+   u8 prediv_width;
u8 n;
u8 k;
u8 m;
@@ -33,6 +39,7 @@ struct factors_data {
int mux;
int muxmask;
const struct clk_factors_config *table;
+   const struct clk_factors_prediv *prediv_table;
void (*getter)(struct factors_request *req);
void (*recalc)(struct factors_request *req);
const char *name;
@@ -42,6 +49,7 @@ struct clk_factors {
struct clk_hw hw;
void __iomem *reg;
const struct clk_factors_config *config;
+   const struct clk_factors_prediv *prediv_config;
void (*get_factors)(struct factors_request *req);
void (*recalc)(struct factors_request *req);
spinlock_t *lock;
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 91de0a0..5a5f26b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c

[linux-sunxi] Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Vishnu Patekar]

Hello Wens,

On Tue, Apr 19, 2016 at 10:16 PM, Chen-Yu Tsai  wrote:
> On Tue, Apr 19, 2016 at 6:22 PM, Philip Li  wrote:
>> On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote:
>>> Both of these patches in series has to be applied at the same time.
>>> I think this is the reason, it fails.
>
> You should probably squash the second patch into the first.
Yes, I should have, I'll send v2 by combining both patches into one.
>
> ChenYu
>
>> hi Xiaolong, would you help do a check whether we apply the patches in 
>> correct sequence for this case?
>>
>>
>>> On 17 Apr 2016 09:26, "kbuild test robot"  wrote:
>>>
>>> > Hi Vishnu,
>>> >
>>> > [auto build test ERROR on clk/clk-next]
>>> > [also build test ERROR on v4.6-rc3 next-20160415]
>>> > [if your patch is applied to the wrong git tree, please drop us a note to
>>> > help improving the system]
>>> >
>>> > url:
>>> > https://github.com/0day-ci/linux/commits/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
>>> > base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
>>> > clk-next
>>> > config: arm-sunxi_defconfig (attached as .config)
>>> > reproduce:
>>> > wget
>>> > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>>> > -O ~/bin/make.cross
>>> > chmod +x ~/bin/make.cross
>>> > # save the attached .config to linux build tree
>>> > make.cross ARCH=arm
>>> >
>>> > Note: the
>>> > linux-review/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
>>> > HEAD 19bb5fc952754381d9f4f9b2e57a1fa09f467359 builds fine.
>>> >   It only hurts bisectibility.
>>> >
>>> > All errors (new ones prefixed by >>):
>>> >
>>> >drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_get_ahb1_factors':
>>> > >> drivers/clk/sunxi/clk-sunxi.c:310:9: error: 'struct factors_request'
>>> > has no member named 'parent_index'
>>> >  if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
>>> > ^
>>> >drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_ahb1_recalc':
>>> >drivers/clk/sunxi/clk-sunxi.c:340:9: error: 'struct factors_request'
>>> > has no member named 'parent_index'
>>> >  if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
>>> > ^
>>> >
>>> > vim +310 drivers/clk/sunxi/clk-sunxi.c
>>> >
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  304   if (req->parent_rate && req->rate
>>> > > req->parent_rate)
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  305   req->rate =
>>> > req->parent_rate;
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  306
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  307   div =
>>> > DIV_ROUND_UP(req->parent_rate, req->rate);
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  308
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  309   /* calculate pre-divider if parent
>>> > is pll6 */
>>> > a78bb355 Chen-Yu Tsai 2016-01-25 @310   if (req->parent_index ==
>>> > SUN6I_AHB1_PARENT_PLL6) {
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  311   if (div < 4)
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  312   calcp = 0;
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  313   else if (div / 2 < 4)
>>> >
>>> > :: The code at line 310 was first introduced by commit
>>> > :: a78bb35552a800949b2bf68f372d3d6ccabdd790 clk: sunxi: rewrite
>>> > sun6i-a31-ahb1-clk using factors clk with custom recalc
>>> >
>>> > :: TO: Chen-Yu Tsai 
>>> > :: CC: Maxime Ripard 
>>> >
>>> > ---
>>> > 0-DAY kernel test infrastructureOpen Source Technology
>>> > Center
>>> > https://lists.01.org/pipermail/kbuild-all   Intel
>>> > Corporation
>>> >

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[linux-sunxi] Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Vishnu Patekar]

Both of these patches in series has to be applied at the same time.
I think this is the reason, it fails.
On 17 Apr 2016 09:26, "kbuild test robot"  wrote:

> Hi Vishnu,
>
> [auto build test ERROR on clk/clk-next]
> [also build test ERROR on v4.6-rc3 next-20160415]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improving the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
> clk-next
> config: arm-sunxi_defconfig (attached as .config)
> reproduce:
> wget
> https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
> -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm
>
> Note: the
> linux-review/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
> HEAD 19bb5fc952754381d9f4f9b2e57a1fa09f467359 builds fine.
>   It only hurts bisectibility.
>
> All errors (new ones prefixed by >>):
>
>drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_get_ahb1_factors':
> >> drivers/clk/sunxi/clk-sunxi.c:310:9: error: 'struct factors_request'
> has no member named 'parent_index'
>  if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
> ^
>drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_ahb1_recalc':
>drivers/clk/sunxi/clk-sunxi.c:340:9: error: 'struct factors_request'
> has no member named 'parent_index'
>  if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
> ^
>
> vim +310 drivers/clk/sunxi/clk-sunxi.c
>
> a78bb355 Chen-Yu Tsai 2016-01-25  304   if (req->parent_rate && req->rate
> > req->parent_rate)
> a78bb355 Chen-Yu Tsai 2016-01-25  305   req->rate =
> req->parent_rate;
> a78bb355 Chen-Yu Tsai 2016-01-25  306
> a78bb355 Chen-Yu Tsai 2016-01-25  307   div =
> DIV_ROUND_UP(req->parent_rate, req->rate);
> a78bb355 Chen-Yu Tsai 2016-01-25  308
> a78bb355 Chen-Yu Tsai 2016-01-25  309   /* calculate pre-divider if parent
> is pll6 */
> a78bb355 Chen-Yu Tsai 2016-01-25 @310   if (req->parent_index ==
> SUN6I_AHB1_PARENT_PLL6) {
> a78bb355 Chen-Yu Tsai 2016-01-25  311   if (div < 4)
> a78bb355 Chen-Yu Tsai 2016-01-25  312   calcp = 0;
> a78bb355 Chen-Yu Tsai 2016-01-25  313   else if (div / 2 < 4)
>
> :: The code at line 310 was first introduced by commit
> :: a78bb35552a800949b2bf68f372d3d6ccabdd790 clk: sunxi: rewrite
> sun6i-a31-ahb1-clk using factors clk with custom recalc
>
> :: TO: Chen-Yu Tsai 
> :: CC: Maxime Ripard 
>
> ---
> 0-DAY kernel test infrastructureOpen Source Technology
> Center
> https://lists.01.org/pipermail/kbuild-all   Intel
> Corporation
>

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[linux-sunxi] [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Vishnu Patekar]

For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.
To handle this, this patch adds predivider table with parent index,
prediv shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic
factors recalc.

Signed-off-by: Vishnu Patekar 
---
 drivers/clk/sunxi/clk-factors.c | 31 +++
 drivers/clk/sunxi/clk-factors.h | 10 +-
 2 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index ddefe96..8f3b637 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -45,10 +45,12 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw 
*hw,
 unsigned long parent_rate)
 {
u8 n = 1, k = 0, p = 0, m = 0;
+   u8 par_index = 0;
u32 reg;
unsigned long rate;
struct clk_factors *factors = to_clk_factors(hw);
const struct clk_factors_config *config = factors->config;
+   const struct clk_factors_prediv *prediv = factors->prediv_config;
 
/* Fetch the register value */
reg = readl(factors->reg);
@@ -63,24 +65,16 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw 
*hw,
if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
p = FACTOR_GET(config->pshift, config->pwidth, reg);
 
-   if (factors->recalc) {
-   struct factors_request factors_req = {
-   .parent_rate = parent_rate,
-   .n = n,
-   .k = k,
-   .m = m,
-   .p = p,
-   };
-
+   if (prediv) {
/* get mux details from mux clk structure */
if (factors->mux)
-   factors_req.parent_index =
-   (reg >> factors->mux->shift) &
-   factors->mux->mask;
-
-   factors->recalc(&factors_req);
+   par_index = (reg >> factors->mux->shift) &
+   factors->mux->mask;
 
-   return factors_req.rate;
+   if (prediv[par_index].width != SUNXI_FACTORS_NOT_APPLICABLE) {
+   m = FACTOR_GET(prediv[par_index].shift,
+   prediv[par_index].width, reg);
+   }
}
 
/* Calculate the rate */
@@ -102,8 +96,12 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
for (i = 0; i < num_parents; i++) {
struct factors_request factors_req = {
.rate = req->rate,
-   .parent_index = i,
};
+
+   if (factors->prediv_config)
+   factors_req.prediv_width =
+   factors->prediv_config[i].width;
+
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
@@ -211,6 +209,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
/* set up factors properties */
factors->reg = reg;
factors->config = data->table;
+   factors->prediv_config = data->prediv_table;
factors->get_factors = data->getter;
factors->recalc = data->recalc;
factors->lock = lock;
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 1e63c5b..b1b7745 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -18,10 +18,16 @@ struct clk_factors_config {
u8 n_start;
 };
 
+struct clk_factors_prediv {
+   u8 parent_index;
+   u8 shift;
+   u8 width;
+};
+
 struct factors_request {
unsigned long rate;
unsigned long parent_rate;
-   u8 parent_index;
+   u8 prediv_width;
u8 n;
u8 k;
u8 m;
@@ -33,6 +39,7 @@ struct factors_data {
int mux;
int muxmask;
const struct clk_factors_config *table;
+   const struct clk_factors_prediv *prediv_table;
void (*getter)(struct factors_request *req);
void (*recalc)(struct factors_request *req);
const char *name;
@@ -42,6 +49,7 @@ struct clk_factors {
struct clk_hw hw;
void __iomem *reg;
const struct clk_factors_config *config;
+   const struct clk_factors_prediv *prediv_config;
void (*get_factors)(struct factors_request *req);
void (*recalc)(struct factors_request *req);
spinlock_t *lock;
-- 
1.9.1

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[linux-sunxi] [PATCH 0/2] sunxi factors clock predivider handling

[Vishnu Patekar]

For allwinner A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.

Currently, it's being handled in clock specific functions. 

A83t ahb1 and a31 ahb1 are similar clocks except a83t parent index 0b10 and 0b11
are pll6/prediv and a31 ahb1 parent index 0x11 is pll6/prediv.
with only this change, code duplication was needed.

To handle this, this patch adds predivider table with parent index, prediv 
shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic factors
recalc. clock specific recalc was currently used only by a31 ahb1.

For getter, it differentiates parents with prediv, with non-zero prediv width.

I've tested this patch on a83t bpi-m3 board. I do not have a31 device.
a83t changes are not included in this patch, It'll be included in separate 
patch.

Vishnu Patekar (2):
  clk: sunxi: add predivider handling for factors clock
  clk: sunxi: add prediv table for a31 ahb1 clock

 drivers/clk/sunxi/clk-factors.c | 31 +++
 drivers/clk/sunxi/clk-factors.h | 10 +-
 drivers/clk/sunxi/clk-sunxi.c   | 31 +--
 3 files changed, 33 insertions(+), 39 deletions(-)

-- 
1.9.1

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[linux-sunxi] [PATCH 2/2] clk: sunxi: add prediv table for a31 ahb1 clock

[Vishnu Patekar]

For ahb1 clock, move mshift and mwidth to parent specific width and shift.
getter differentiates parents with prediv, with non-zero prediv width.

Also, removed unused ahb1 recalc function, it's now handled in generic
factors recalc.

Signed-off-by: Vishnu Patekar 
---
 drivers/clk/sunxi/clk-sunxi.c | 31 +--
 1 file changed, 9 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 91de0a0..5a5f26b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -282,8 +282,6 @@ static void sun5i_a13_get_ahb_factors(struct 
factors_request *req)
req->p = div;
 }
 
-#define SUN6I_AHB1_PARENT_PLL6 3
-
 /**
  * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
  * AHB rate is calculated as follows
@@ -307,7 +305,7 @@ static void sun6i_get_ahb1_factors(struct factors_request 
*req)
div = DIV_ROUND_UP(req->parent_rate, req->rate);
 
/* calculate pre-divider if parent is pll6 */
-   if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
+   if (req->prediv_width) {
if (div < 4)
calcp = 0;
else if (div / 2 < 4)
@@ -329,22 +327,6 @@ static void sun6i_get_ahb1_factors(struct factors_request 
*req)
 }
 
 /**
- * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
- *  parent index
- */
-static void sun6i_ahb1_recalc(struct factors_request *req)
-{
-   req->rate = req->parent_rate;
-
-   /* apply pre-divider first if parent is pll6 */
-   if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
-   req->rate /= req->m + 1;
-
-   /* clk divider */
-   req->rate >>= req->p;
-}
-
-/**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
  * rate = (parent_rate >> p) / (m + 1);
@@ -474,12 +456,17 @@ static const struct clk_factors_config 
sun5i_a13_ahb_config = {
 };
 
 static const struct clk_factors_config sun6i_ahb1_config = {
-   .mshift = 6,
-   .mwidth = 2,
.pshift = 4,
.pwidth = 2,
 };
 
+static const struct clk_factors_prediv sun6i_ahb1_prediv[] = {
+   {.parent_index = 0, .shift = 0, .width = 0 },   /* LOSC  */
+   {.parent_index = 1, .shift = 0, .width = 0 },   /* OSC24MHz */
+   {.parent_index = 2, .shift = 0, .width = 0 },   /* AXI */
+   {.parent_index = 3, .shift = 6, .width = 2 }/* PLL6/Pre_div */
+};
+
 static const struct clk_factors_config sun4i_apb1_config = {
.mshift = 0,
.mwidth = 5,
@@ -551,8 +538,8 @@ static const struct factors_data sun6i_ahb1_data 
__initconst = {
.mux = 12,
.muxmask = BIT(1) | BIT(0),
.table = &sun6i_ahb1_config,
+   .prediv_table = sun6i_ahb1_prediv,
.getter = sun6i_get_ahb1_factors,
-   .recalc = sun6i_ahb1_recalc,
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
-- 
1.9.1

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[linux-sunxi] Re: [PATCH v4 02/13] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

Hello Maxime,

On Fri, Apr 15, 2016 at 1:28 AM, Maxime Ripard
 wrote:
> On Mon, Apr 04, 2016 at 11:07:29AM +0800, Vishnu Patekar wrote:
>> Hello Maxime,
>>
>> On Thu, Mar 17, 2016 at 6:40 PM, Maxime Ripard
>>  wrote:
>> > On Thu, Mar 17, 2016 at 12:04:25AM +0800, Vishnu Patekar wrote:
>> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> >> clock index 0b1x is PLL6.
>> >>
>> >> Signed-off-by: Vishnu Patekar 
>> >> Acked-by: Chen-Yu Tsai 
>> >> Acked-by: Rob Herring 
>> >> ---
>> >>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>> >>  drivers/clk/sunxi/clk-sunxi.c | 76 
>> >> +++
>> >>  2 files changed, 77 insertions(+)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
>> >> b/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> index 834436f..cba9fe55 100644
>> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> >> @@ -30,6 +30,7 @@ Required properties:
>> >>   "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>> >>   "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
>> >>   "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> >> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
>> >>   "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>> >>   "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>> >>   "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> >> index 91de0a0..a7aab65 100644
>> >> --- a/drivers/clk/sunxi/clk-sunxi.c
>> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> >> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request 
>> >> *req)
>> >>   req->rate >>= req->p;
>> >>  }
>> >>
>> >> +#define SUN8I_A83T_AHB1_PARENT_PLL6  2
>> >> +/**
>> >> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
>> >> + * AHB rate is calculated as follows
>> >> + * rate = parent_rate >> p
>> >> + *
>> >> + * if parent is pll6, then
>> >> + * parent_rate = pll6 rate / (m + 1)
>> >> + */
>> >> +
>> >> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
>> >> +{
>> >> + u8 div, calcp, calcm = 1;
>> >> +
>> >> + /*
>> >> +  * clock can only divide, so we will never be able to achieve
>> >> +  * frequencies higher than the parent frequency
>> >> +  */
>> >> + if (req->parent_rate && req->rate > req->parent_rate)
>> >> + req->rate = req->parent_rate;
>> >> +
>> >> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
>> >> +
>> >> + /* calculate pre-divider if parent is pll6 */
>> >> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
>> >> + if (div < 4)
>> >> + calcp = 0;
>> >> + else if (div / 2 < 4)
>> >> + calcp = 1;
>> >> + else if (div / 4 < 4)
>> >> + calcp = 2;
>> >> + else
>> >> + calcp = 3;
>> >> +
>> >> + calcm = DIV_ROUND_UP(div, 1 << calcp);
>> >> + } else {
>> >> + calcp = __roundup_pow_of_two(div);
>> >> + calcp = calcp > 3 ? 3 : calcp;
>> >> + }
>> >> +
>> >> + req->rate = (req->parent_rate / calcm) >> calcp;
>> >> + req->p = calcp;
>> >> + req->m = calcm - 1;
>> >> +}
>> >> +
>> >> +/**
>> >> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors 
>> >> and
>> >> +* parent index
>> >> +*/
>> >> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
>> >> +{
>> >> + req->rate = req->parent_rate;
>&g

[linux-sunxi] Re: [PATCH v4 02/13] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

Hello Maxime,

On Thu, Mar 17, 2016 at 6:40 PM, Maxime Ripard
 wrote:
> On Thu, Mar 17, 2016 at 12:04:25AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar 
>> Acked-by: Chen-Yu Tsai 
>> Acked-by: Rob Herring 
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>>  drivers/clk/sunxi/clk-sunxi.c | 76 
>> +++
>>  2 files changed, 77 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
>> b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index 834436f..cba9fe55 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -30,6 +30,7 @@ Required properties:
>>   "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>>   "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
>>   "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>> + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
>>   "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>>   "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>>   "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 91de0a0..a7aab65 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request 
>> *req)
>>   req->rate >>= req->p;
>>  }
>>
>> +#define SUN8I_A83T_AHB1_PARENT_PLL6  2
>> +/**
>> + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
>> + * AHB rate is calculated as follows
>> + * rate = parent_rate >> p
>> + *
>> + * if parent is pll6, then
>> + * parent_rate = pll6 rate / (m + 1)
>> + */
>> +
>> +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
>> +{
>> + u8 div, calcp, calcm = 1;
>> +
>> + /*
>> +  * clock can only divide, so we will never be able to achieve
>> +  * frequencies higher than the parent frequency
>> +  */
>> + if (req->parent_rate && req->rate > req->parent_rate)
>> + req->rate = req->parent_rate;
>> +
>> + div = DIV_ROUND_UP(req->parent_rate, req->rate);
>> +
>> + /* calculate pre-divider if parent is pll6 */
>> + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
>> + if (div < 4)
>> + calcp = 0;
>> + else if (div / 2 < 4)
>> + calcp = 1;
>> + else if (div / 4 < 4)
>> + calcp = 2;
>> + else
>> + calcp = 3;
>> +
>> + calcm = DIV_ROUND_UP(div, 1 << calcp);
>> + } else {
>> + calcp = __roundup_pow_of_two(div);
>> + calcp = calcp > 3 ? 3 : calcp;
>> + }
>> +
>> + req->rate = (req->parent_rate / calcm) >> calcp;
>> + req->p = calcp;
>> + req->m = calcm - 1;
>> +}
>> +
>> +/**
>> +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
>> +* parent index
>> +*/
>> +static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
>> +{
>> + req->rate = req->parent_rate;
>> +
>> +/* apply pre-divider first if parent is pll6 */
>
> The comment indentation is wrong
>
>> + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
>
> And this is not the right define you're using.
>
> I still believe that duplicating the same logic just because of
> different dividers is not the way to go.
>
> You could solve that easily by adding a table for the muxes, and
> associate it with parents and dividers, that you could store in
> clk_factors.

I've similar solution (please ignore a83 specific functions those will
be common for a31 and a83t).
https://github.com/vishnupatekar/linux/commit/f7de5b48d886a672b1f6db112fbfd5d2c9849afa

is it aligned to what you're saying?

Or do you mean we can use mux clock with div clock as composite clock?
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] [PATCH v4 01/13] pinctrl: sunxi: Add A83T R_PIO controller

[Vishnu Patekar]

The A83T has R_PIO pin controller, it's same as A23, execpt A83T
interrupt bit is 6th and A83T has one extra pin PL12.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 117 +
 4 files changed, 124 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..f9ff10b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,6 +20,7 @@ Required properties:
   "allwinner,sun9i-a80-pinctrl"
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun8i-a83t-r-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..eeab50b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -51,6 +51,11 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_A83T_R
+   def_bool MACH_SUN8I
+   depends on RESET_CONTROLLER
+   select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..bfd4fa0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)   += 
pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)  += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
new file mode 100644
index 000..5b88921
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -0,0 +1,117 @@
+/*
+ * Allwinner A83T SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai 
+ * Copyright (C) 2014 Maxime Ripard 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+  

[linux-sunxi] [PATCH v4 09/13] ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi

[Vishnu Patekar]

This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A83T dtsi.

Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5d240b9..7b02d85 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -476,6 +476,27 @@
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+
+   r_rsb_pins: r_rsb {
+   allwinner,pins = "PL0", "PL1";
+   allwinner,function = "s_rsb";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+   };
+
+   r_rsb: i2c@01f03400 {
+   compatible = "allwinner,sun8i-a23-rsb";
+   reg = <0x01f03400 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 3>;
+   clock-frequency = <300>;
+   resets = <&apb0_reset 3>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&r_rsb_pins>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
};
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v4 00/13] Add A83T clk, r_pio, mmc rsb support

[Vishnu Patekar]

Hello,
This is v4 of series which adds further support for A83T, mainly adds clock 
support.Also adds R_PIO, PRCM related clocks, mmc, rsb support.

A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.

These patches are based on Maxime's sunxi/for-next branch.
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/

v3->v4 Changes:
1. Removed MODULE_DEVICE_TABLE, module.h and made A83T R_PIO as 
builtin_platform_driver.
2. Corrected config to  MACH_SUN8I in clk/sunxi/Kconfig.
3. Corrected style related errors.

v2->v3 Changes:
1. Corrected wrong configuration of uart0 and timer in dtsi.
2. corrected clock gate name of "spdif" in dtsi.
3. Added kconfig for sunxi clocks, added sun8i-apb0 and sun9i-cpus clocks to it.

v1->v2 Changes:
1. Patches for apb0 gates clock, bus gates, low speed oscillators are already
   merged, so, not included again in this series.
1. sorted the R_PIO Kconfig options.
2. removed un-necessary a83t apb1 div table.
3. combined the three ahb reset registers into one reset node.
4. Changed the bus gates names to bus_spidf and bus_usb_otg.
5. removed un-necessary #address-cells and #size-cells from R_PIO node.
6. splited rsb pins and rsb controller nodes in different patches.
7. used PF6 as mmc0 CD reference design pin.
8. corrected the style related errors.

Patch 1: adds support for r_pio pin controller.

patch 2: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.

patch 3: adds apb1 clock support, apb1 has different dividers compared to a10 
apb0 clock.

patch 4: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.

patch 5-6: adds mmc and it's clock nodes.

patch 7: adds A83T PRCM related clocks, clock resets.

patch 8: adds r_pio pin controller nodes to dtsi

patch 9: adds RSB controller nodes to dtsi

patch 10: adds common MMC CD detect pin as reference design pin 

patch 11: enables mmc0 support for h8homlet board, tested by LABBE Corentin.

patch 12: This patch adds support for Sinovoip BPI-M3 A83T based board, it has 
2GB LPDDR3, u-boot support is added recently for this board.

patch 13: Adds kconfig for clocks(sun8i-apb0 and sun9i-cpus).

Vishnu Patekar (13):
  pinctrl: sunxi: Add A83T R_PIO controller
  clk: sunxi: add ahb1 clock for A83T
  clk: sunxi: Add APB1 clock for A83T
  ARM: dts: sun8i-a83t: Add basic clocks and resets
  ARM: dts: sun8i-a83t: add mmc clock nodes
  ARM: dts: sun8i-a83t: Add mmc controller nodes
  ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
  ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
  ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi
  ARM: dts: sun8i-a83t: add mmc0 CD pin
  ARM: dts: sun8i: enable mmc for H8Homlet Board.
  ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board
  ARM: sunxi: Add Kconfig for sunxi clocks

 Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  11 +
 ...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} |  21 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 285 -
 drivers/clk/Kconfig|   1 +
 drivers/clk/sunxi/Kconfig  |   5 +
 drivers/clk/sunxi/Makefile |   4 +-
 drivers/clk/sunxi/clk-sunxi.c  |  89 +++
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 117 +
 13 files changed, 536 insertions(+), 7 deletions(-)
 copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => 
sun8i-a83t-sinovoip-bpi-m3.dts} (83%)
 create mode 100644 drivers/clk/sunxi/Kconfig
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

-- 
1.9.1

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[linux-sunxi] [PATCH v4 05/13] ARM: dts: sun8i-a83t: add mmc clock nodes

[Vishnu Patekar]

mmc clocks are compatible with that of earlier sun8i socs.
This adds mmc0, mmc1, and mmc2 clock nodes for A83T.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 2689af4..943d8a8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -237,6 +237,36 @@
 "bus_uart2", "bus_uart3",
 "bus_uart4";
};
+
+   mmc0_clk: clk@01c20088 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20088 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc0",
+"mmc0_output",
+"mmc0_sample";
+   };
+
+   mmc1_clk: clk@01c2008c {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c2008c 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc1",
+"mmc1_output",
+"mmc1_sample";
+   };
+
+   mmc2_clk: clk@01c20090 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20090 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc2",
+"mmc2_output",
+"mmc2_sample";
+   };
};
 
soc {
-- 
1.9.1

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[linux-sunxi] [PATCH v4 12/13] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

This patch adds support for Sinovoip BPI-M3 A83T based board.

It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 79 
 2 files changed, 80 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 309cce5..64ad31f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -695,6 +695,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
+   sun8i-a83t-sinovoip-bpi-m3.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
new file mode 100644
index 000..7744b63
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+   model = "Sinovoip BananaPi M3 v1.2";
+   compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
+&r_rsb {
+   status = "okay";
+};
+
+&uart0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart0_pins_b>;
+   status = "okay";
+};
-- 
1.9.1

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[linux-sunxi] [PATCH v4 03/13] clk: sunxi: Add APB1 clock for A83T

[Vishnu Patekar]

APB1 is similar to sun4i-a10-apb0-clk, except different dividers.

This adds support for apb1 on A83T.

Signed-off-by: Vishnu Patekar 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 13 +
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index cba9fe55..291d366 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -51,6 +51,7 @@ Required properties:
"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
++  "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index a7aab65..171282d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -872,6 +872,12 @@ static const struct div_data sun4i_apb0_data __initconst = 
{
.table  = sun4i_apb0_table,
 };
 
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+   .shift  = 8,
+   .pow= 0,
+   .width  = 2,
+};
+
 static void __init sunxi_divider_clk_setup(struct device_node *node,
   const struct div_data *data)
 {
@@ -938,6 +944,13 @@ static void __init sun4i_apb0_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
   sun4i_apb0_clk_setup);
 
+static void __init sun8i_a83t_apb1_clk_setup(struct device_node *node)
+{
+   sunxi_divider_clk_setup(node, &sun8i_a83t_apb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_apb1, "allwinner,sun8i-a83t-apb1-clk",
+  sun8i_a83t_apb1_clk_setup);
+
 static void __init sun4i_axi_clk_setup(struct device_node *node)
 {
sunxi_divider_clk_setup(node, &sun4i_axi_data);
-- 
1.9.1

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[linux-sunxi] [PATCH v4 10/13] ARM: dts: sun8i-a83t: add mmc0 CD pin

[Vishnu Patekar]

A83T Boards BPI-m3 and Allwinner H8Homletv2 boards use PF6 as
Card Detect pin., so use PF6 as reference design CD pin in dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7b02d85..c64d8d6 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -390,6 +390,13 @@
allwinner,pull = ;
};
 
+   mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+   allwinner,pins = "PF6";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
-- 
1.9.1

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[linux-sunxi] [PATCH v4 08/13] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

[Vishnu Patekar]

Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 691bbf1..5d240b9 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -465,5 +465,17 @@
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
+
+   r_pio: pinctrl@01f02c00 {
+   compatible = "allwinner,sun8i-a83t-r-pinctrl";
+   reg = <0x01f02c00 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 0>;
+   resets = <&apb0_reset 0>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   #gpio-cells = <3>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v4 02/13] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 76 +++
 2 files changed, 77 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 834436f..cba9fe55 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -30,6 +30,7 @@ Required properties:
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+   "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 91de0a0..a7aab65 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
req->rate >>= req->p;
 }
 
+#define SUN8I_A83T_AHB1_PARENT_PLL62
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+   u8 div, calcp, calcm = 1;
+
+   /*
+* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency
+*/
+   if (req->parent_rate && req->rate > req->parent_rate)
+   req->rate = req->parent_rate;
+
+   div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+   /* calculate pre-divider if parent is pll6 */
+   if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+   if (div < 4)
+   calcp = 0;
+   else if (div / 2 < 4)
+   calcp = 1;
+   else if (div / 4 < 4)
+   calcp = 2;
+   else
+   calcp = 3;
+
+   calcm = DIV_ROUND_UP(div, 1 << calcp);
+   } else {
+   calcp = __roundup_pow_of_two(div);
+   calcp = calcp > 3 ? 3 : calcp;
+   }
+
+   req->rate = (req->parent_rate / calcm) >> calcp;
+   req->p = calcp;
+   req->m = calcm - 1;
+}
+
+/**
+* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+*   parent index
+*/
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+   req->rate = req->parent_rate;
+
+/* apply pre-divider first if parent is pll6 */
+   if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+   req->rate /= req->m + 1;
+
+   /* clk divider */
+   req->rate >>= req->p;
+}
+
 /**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data 
__initconst = {
.recalc = sun6i_ahb1_recalc,
 };
 
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+   .mux = 12,
+   .muxmask = BIT(1) | BIT(0),
+   .table = &sun6i_ahb1_config,
+   .getter = sun8i_a83t_get_ahb1_factors,
+   .recalc = sun8i_a83t_ahb1_recalc,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -627,6 +696,13 @@ static void __init sun6i_ahb1_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
   sun6i_ahb1_clk_setup);
 
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+   sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+  sun8i_a83t_ahb1_clk_setup);
+
 static void __init sun4i_apb1_clk_setup(struct device_node *node)
 {
sunxi_factors_clk_setup(node, &sun4i_apb1_data);
-- 
1.9.1

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[linux-sunxi] [PATCH v4 06/13] ARM: dts: sun8i-a83t: Add mmc controller nodes

[Vishnu Patekar]

A83T mmc is compatible with earliers sunxi socs.
This adds mmc0, mmc1, and mmc2 controller nodes for A83T.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 943d8a8..a44d4dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -275,6 +275,63 @@
#size-cells = <1>;
ranges;
 
+   mmc0: mmc@01c0f000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c0f000 0x1000>;
+   clocks = <&bus_gates 8>,
+<&mmc0_clk 0>,
+<&mmc0_clk 1>,
+<&mmc0_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 8>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc1: mmc@01c1 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c1 0x1000>;
+   clocks = <&bus_gates 9>,
+<&mmc1_clk 0>,
+<&mmc1_clk 1>,
+<&mmc1_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 9>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc2: mmc@01c11000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c11000 0x1000>;
+   clocks = <&bus_gates 10>,
+<&mmc2_clk 0>,
+<&mmc2_clk 1>,
+<&mmc2_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 10>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
-- 
1.9.1

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[linux-sunxi] [PATCH v4 11/13] ARM: dts: sun8i: enable mmc for H8Homlet Board.

[Vishnu Patekar]

This enables mmc0.

Signed-off-by: Vishnu Patekar 
Tested-by: LABBE Corentin 
---
 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..3269f39 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,16 @@
};
 };
 
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
-- 
1.9.1

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[linux-sunxi] Re: [PATCH v4 01/13] pinctrl: sunxi: Add A83T R_PIO controller

[Vishnu Patekar]

Hello Linus,

On Thu, Mar 17, 2016 at 10:51 PM, Linus Walleij
 wrote:
> On Wed, Mar 16, 2016 at 5:04 PM, Vishnu Patekar
>  wrote:
>
>> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
>> interrupt bit is 6th and A83T has one extra pin PL12.
>>
>> Signed-off-by: Vishnu Patekar 
>> Acked-by: Chen-Yu Tsai 
>> Acked-by: Rob Herring 
>
> I think I already merged this?
AFAIK, this one is not yet merged. At least, you did not say it's merged. :)
>
> Yours,
> Linus Walleij

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[linux-sunxi] [PATCH v4 07/13] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

This adds A83T PRCM related clocks, clock resets.

As a83t apb0 gates clock support is added earlier, this enables it.
Apart from apb0 gates, other added clocks are compatible with
earlier sun8i socs.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a44d4dc..691bbf1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -267,6 +267,44 @@
 "mmc2_output",
 "mmc2_sample";
};
+
+   cpus_clk: clk@01f01400 {
+   compatible = "allwinner,sun9i-a80-cpus-clk";
+   reg = <0x01f01400 0x4>;
+   #clock-cells = <0>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
+   clock-output-names = "cpus";
+   };
+
+   ahb0: ahb0_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <1>;
+   clocks = <&cpus_clk>;
+   clock-output-names = "ahb0";
+   };
+
+   apb0: clk@01f0140c {
+   compatible = "allwinner,sun8i-a23-apb0-clk";
+   reg = <0x01f0140c 0x4>;
+   #clock-cells = <0>;
+   clocks = <&ahb0>;
+   clock-output-names = "apb0";
+   };
+
+   apb0_gates: clk@01f01428 {
+   compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
+   reg = <0x01f01428 0x4>;
+   #clock-cells = <1>;
+   clocks = <&apb0>;
+   clock-indices = <0>, <1>,
+   <2>, <3>,
+   <4>, <6>, <7>;
+   clock-output-names = "apb0_pio", "apb0_ir",
+   "apb0_timer", "apb0_rsb",
+   "apb0_uart", "apb0_i2c0", "apb0_twd";
+   };
};
 
soc {
@@ -421,5 +459,11 @@
#interrupt-cells = <3>;
interrupts = ;
};
+
+   apb0_reset: reset@01f014b0 {
+   reg = <0x01f014b0 0x4>;
+   compatible = "allwinner,sun6i-a31-clock-reset";
+   #reset-cells = <1>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v4 13/13] ARM: sunxi: Add Kconfig for sunxi clocks

[Vishnu Patekar]

This patch adds Kconfig for sunxi clocks.
Currently, only sun8i-apb0 and sun9i-cpus clocks are added.
It'll help to use common clocks across different SOCs.
We can switch to kconfig for other clocks in future.

Signed-off-by: Vishnu Patekar 
---
 drivers/clk/Kconfig| 1 +
 drivers/clk/sunxi/Kconfig  | 5 +
 drivers/clk/sunxi/Makefile | 4 ++--
 3 files changed, 8 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/sunxi/Kconfig

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eca8e01..f9f42e6 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -210,3 +210,4 @@ source "drivers/clk/mvebu/Kconfig"
 
 source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/sunxi/Kconfig"
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
new file mode 100644
index 000..3e8ede4
--- /dev/null
+++ b/drivers/clk/sunxi/Kconfig
@@ -0,0 +1,5 @@
+config CLK_SUN8I_APB0
+   def_bool MACH_SUN9I || MACH_SUN8I
+
+config CLK_SUN9I_CPUS
+   def_bool MACH_SUN9I || MACH_SUN8I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3fd7901..38dfca8 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -17,8 +17,8 @@ obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
 obj-y += clk-usb.o
 
-obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
-obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
+obj-$(CONFIG_CLK_SUN8I_APB0) += clk-sun8i-apb0.o
+obj-$(CONFIG_CLK_SUN9I_CPUS) += clk-sun9i-cpus.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
-- 
1.9.1

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[linux-sunxi] [PATCH v4 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Vishnu Patekar]

This adds A83T system bus clocks, bus gates, and clock resets.

Three ahb reset registers are combined into one node.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 114 +-
 1 file changed, 112 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d3473f8..2689af4 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -146,6 +146,97 @@
clocks = <&osc16M>;
clock-output-names = "osc16M-d512";
};
+
+   pll6: clk@01c20028 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun9i-a80-pll4-clk";
+   reg = <0x01c20028 0x4>;
+   clocks = <&osc24M>;
+   clock-output-names = "pll6";
+   };
+
+   pll6d2: pll6d2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clock-div = <2>;
+   clock-mult = <1>;
+   clocks = <&pll6>;
+   clock-output-names = "pll6d2";
+   };
+
+   ahb1: clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-ahb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "ahb1";
+   };
+
+   apb1: apb1_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-apb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&ahb1>;
+   clock-output-names = "apb1";
+   };
+
+   apb2: clk@01c20058 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-apb1-clk";
+   reg = <0x01c20058 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "apb2";
+   };
+
+   ahb2: clk@01c2005c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ahb2-clk";
+   reg = <0x01c2005c 0x4>;
+   clocks = <&ahb1>, <&pll6d2>;
+   clock-output-names = "ahb2";
+   };
+
+   bus_gates: clk@01c20060 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun8i-a83t-bus-gates-clk";
+   reg = <0x01c20060 0x10>;
+   clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+   clock-names = "ahb1", "ahb2", "apb1", "apb2";
+   clock-indices = <1>, <5>, <6>,
+   <8>, <9>, <10>,
+   <13>, <14>, <17>,
+   <19>, <20>,
+   <21>, <24>,
+   <26>, <27>,
+   <29>, <32>,
+   <36>, <37>,
+   <40>, <43>,
+   <44>, <52>, <53>,
+   <54>, <65>,
+   <69>, <76>, <77>,
+   <78>, <79>, <96>,
+   <97>, <98>,
+   <112>, <113>,
+   <114>, <115>,
+   <116>;
+   clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
+"bus_mmc0", "bus_mmc1", "bus_mmc2",
+"bus_nand", "bus_sdram", 
"bus_emac",
+"bus_hstimer", "bus_spi0

[linux-sunxi] Re: [PATCH v3 01/13] pinctrl: sunxi: Add A83T R_PIO controller support

[Vishnu Patekar]

Hello Linus,


On Wed, Mar 9, 2016 at 10:55 AM, Linus Walleij  wrote:
> On Sat, Mar 5, 2016 at 10:42 PM, Vishnu Patekar
>  wrote:
>
>> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
>> interrupt bit is 6th and A83T has one extra pin PL12.
>>
>> Signed-off-by: Vishnu Patekar 
>> Acked-by: Chen-Yu Tsai 
>> Acked-by: Rob Herring 
>
> As partly noted by others:
>
>> +config PINCTRL_SUN8I_A83T_R
>> +   def_bool MACH_SUN8I
>
> bool
>
>> +   depends on RESET_CONTROLLER
>
> Should it rather select RESET_CONTROLLER?
I used depends on and def_bool as it is used for other sunxi pinctrl drivers.
Using bool and select will not harm anything.
Should I change it to bool and select ?  or keep it to be uniform with
earlier options?
>
>> +static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = {
>> +   { .compatible = "allwinner,sun8i-a83t-r-pinctrl", },
>> +   {}
>> +};
>> +MODULE_DEVICE_TABLE(of, sun8i_a83t_r_pinctrl_match);
>
> Module talk in bool driver.
I'll remove it.
>
>> +static struct platform_driver sun8i_a83t_r_pinctrl_driver = {
>> +   .probe  = sun8i_a83t_r_pinctrl_probe,
>> +   .driver = {
>> +   .name   = "sun8i-a83t-r-pinctrl",
>> +   .of_match_table = sun8i_a83t_r_pinctrl_match,
>> +   },
>> +};
>> +module_platform_driver(sun8i_a83t_r_pinctrl_driver);
>
> Should be builtin?
Yes, It should be. I missed Maxime's earlier commets.
>
> Yours,
> Linus Walleij

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[linux-sunxi] Re: [PATCH v3 13/13] ARM: sunxi: Add Kconfig for sunxi clocks

[Vishnu Patekar]

Hello,

On Sat, Mar 5, 2016 at 11:43 PM, Vishnu Patekar
 wrote:
> This patch adds Kconfig for sunxi clocks.
> Currently, only sun8i-apb0 and sun9i-cpus clocks are added.
> It'll help to use common clocks across different SOCs.
> We can switch to kconfig for other clocks in future.
>
> Signed-off-by: Vishnu Patekar 
> ---
>  drivers/clk/Kconfig| 1 +
>  drivers/clk/sunxi/Kconfig  | 5 +
>  drivers/clk/sunxi/Makefile | 4 ++--
>  3 files changed, 8 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/clk/sunxi/Kconfig
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index eca8e01..f9f42e6 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -210,3 +210,4 @@ source "drivers/clk/mvebu/Kconfig"
>
>  source "drivers/clk/samsung/Kconfig"
>  source "drivers/clk/tegra/Kconfig"
> +source "drivers/clk/sunxi/Kconfig"
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> new file mode 100644
> index 000..afc55c9
> --- /dev/null
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -0,0 +1,5 @@
> +config CLK_SUN8I_APB0
> +   def_bool MACH_SUN9I || MACH_SUN8I_A83T

This should be MACH_SUN8I and not MACH_SUN8I_A83T.

Self NACK for this patch.
> +
> +config CLK_SUN9I_CPUS
> +   def_bool MACH_SUN9I || MACH_SUN8I_A83T
same here

> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 3fd7901..38dfca8 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -17,8 +17,8 @@ obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
>  obj-y += clk-usb.o
>
> -obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
> -obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
> +obj-$(CONFIG_CLK_SUN8I_APB0) += clk-sun8i-apb0.o
> +obj-$(CONFIG_CLK_SUN9I_CPUS) += clk-sun9i-cpus.o
>
>  obj-$(CONFIG_MFD_SUN6I_PRCM) += \
> clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
> --
> 1.9.1
>

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[linux-sunxi] [PATCH v3 13/13] ARM: sunxi: Add Kconfig for sunxi clocks

[Vishnu Patekar]

This patch adds Kconfig for sunxi clocks.
Currently, only sun8i-apb0 and sun9i-cpus clocks are added.
It'll help to use common clocks across different SOCs.
We can switch to kconfig for other clocks in future.

Signed-off-by: Vishnu Patekar 
---
 drivers/clk/Kconfig| 1 +
 drivers/clk/sunxi/Kconfig  | 5 +
 drivers/clk/sunxi/Makefile | 4 ++--
 3 files changed, 8 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/sunxi/Kconfig

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eca8e01..f9f42e6 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -210,3 +210,4 @@ source "drivers/clk/mvebu/Kconfig"
 
 source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/sunxi/Kconfig"
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
new file mode 100644
index 000..afc55c9
--- /dev/null
+++ b/drivers/clk/sunxi/Kconfig
@@ -0,0 +1,5 @@
+config CLK_SUN8I_APB0
+   def_bool MACH_SUN9I || MACH_SUN8I_A83T
+
+config CLK_SUN9I_CPUS
+   def_bool MACH_SUN9I || MACH_SUN8I_A83T
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3fd7901..38dfca8 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -17,8 +17,8 @@ obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
 obj-y += clk-usb.o
 
-obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
-obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
+obj-$(CONFIG_CLK_SUN8I_APB0) += clk-sun8i-apb0.o
+obj-$(CONFIG_CLK_SUN9I_CPUS) += clk-sun9i-cpus.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
-- 
1.9.1

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[linux-sunxi] [PATCH v3 12/13] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

This patch adds support for Sinovoip BPI-M3 A83T based board.

It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 79 
 2 files changed, 80 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 58e461a..c0dd016 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
+   sun8i-a83t-sinovoip-bpi-m3.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
new file mode 100644
index 000..7744b63
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+   model = "Sinovoip BananaPi M3 v1.2";
+   compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
+&r_rsb {
+   status = "okay";
+};
+
+&uart0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart0_pins_b>;
+   status = "okay";
+};
-- 
1.9.1

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[linux-sunxi] [PATCH v3 11/13] ARM: dts: sun8i: enable mmc for H8Homlet Board.

[Vishnu Patekar]

This enables mmc0.

Signed-off-by: Vishnu Patekar 
Tested-by: LABBE Corentin 
---
 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..3269f39 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,16 @@
};
 };
 
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
-- 
1.9.1

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[linux-sunxi] [PATCH v3 08/13] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

[Vishnu Patekar]

Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 691bbf1..5d240b9 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -465,5 +465,17 @@
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
+
+   r_pio: pinctrl@01f02c00 {
+   compatible = "allwinner,sun8i-a83t-r-pinctrl";
+   reg = <0x01f02c00 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 0>;
+   resets = <&apb0_reset 0>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   #gpio-cells = <3>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v3 09/13] ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi

[Vishnu Patekar]

This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A83T dtsi.

Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5d240b9..7b02d85 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -476,6 +476,27 @@
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+
+   r_rsb_pins: r_rsb {
+   allwinner,pins = "PL0", "PL1";
+   allwinner,function = "s_rsb";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+   };
+
+   r_rsb: i2c@01f03400 {
+   compatible = "allwinner,sun8i-a23-rsb";
+   reg = <0x01f03400 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 3>;
+   clock-frequency = <300>;
+   resets = <&apb0_reset 3>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&r_rsb_pins>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
};
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v3 10/13] ARM: dts: sun8i-a83t: add mmc0 CD pin

[Vishnu Patekar]

A83T Boards BPI-m3 and Allwinner H8Homletv2 boards use PF6 as
Card Detect pin., so use PF6 as reference design CD pin in dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7b02d85..c64d8d6 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -390,6 +390,13 @@
allwinner,pull = ;
};
 
+   mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+   allwinner,pins = "PF6";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
-- 
1.9.1

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[linux-sunxi] [PATCH v3 05/13] ARM: dts: sun8i-a83t: add mmc clock nodes

[Vishnu Patekar]

mmc clocks are compatible with that of earlier sun8i socs.
This adds mmc0, mmc1, and mmc2 clock nodes for A83T.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 2689af4..943d8a8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -237,6 +237,36 @@
 "bus_uart2", "bus_uart3",
 "bus_uart4";
};
+
+   mmc0_clk: clk@01c20088 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20088 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc0",
+"mmc0_output",
+"mmc0_sample";
+   };
+
+   mmc1_clk: clk@01c2008c {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c2008c 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc1",
+"mmc1_output",
+"mmc1_sample";
+   };
+
+   mmc2_clk: clk@01c20090 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20090 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc2",
+"mmc2_output",
+"mmc2_sample";
+   };
};
 
soc {
-- 
1.9.1

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[linux-sunxi] [PATCH v3 03/13] clk: sunxi: Add APB1 clock for A83T

[Vishnu Patekar]

APB1 is similar to sun4i-a10-apb0-clk, except different dividers.

This adds support for apb1 on A83T.

Signed-off-by: Vishnu Patekar 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 13 +
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 2ee7841..dd24772 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -49,6 +49,7 @@ Required properties:
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
+   "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 0ae1f09..987a12d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -863,6 +863,12 @@ static const struct div_data sun4i_apb0_data __initconst = 
{
.table  = sun4i_apb0_table,
 };
 
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+   .shift  = 8,
+   .pow= 0,
+   .width  = 2,
+};
+
 static void __init sunxi_divider_clk_setup(struct device_node *node,
   const struct div_data *data)
 {
@@ -899,6 +905,13 @@ static void __init sun4i_apb0_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
   sun4i_apb0_clk_setup);
 
+static void __init sun8i_a83t_apb1_clk_setup(struct device_node *node)
+{
+   sunxi_divider_clk_setup(node, &sun8i_a83t_apb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_apb1, "allwinner,sun8i-a83t-apb1-clk",
+  sun8i_a83t_apb1_clk_setup);
+
 static void __init sun4i_axi_clk_setup(struct device_node *node)
 {
sunxi_divider_clk_setup(node, &sun4i_axi_data);
-- 
1.9.1

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[linux-sunxi] [PATCH v3 00/13] Add A83T clk, r_pio, mmc rsb support

[Vishnu Patekar]

Hello,
This is v3 of series which adds further support for A83T, mainly adds clock 
support.Also adds R_PIO, PRCM related clocks, mmc, rsb support.

A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.

These patches are based on Maxime's sunxi/for-next branch.
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/

v2->v3 Changes:
1. Corrected wrong configuration of uart0 and timer in dtsi.
2. corrected clock gate name of "spdif" in dtsi.
3. Added kconfig for sunxi clocks, added sun8i-apb0 and sun9i-cpus clocks to it.

v1->v2 Changes:
1. Patches for apb0 gates clock, bus gates, low speed oscillators are already
   merged, so, not included again in this series.
1. sorted the R_PIO Kconfig options.
2. removed un-necessary a83t apb1 div table.
3. combined the three ahb reset registers into one reset node.
4. Changed the bus gates names to bus_spidf and bus_usb_otg.
5. removed un-necessary #address-cells and #size-cells from R_PIO node.
6. splited rsb pins and rsb controller nodes in different patches.
7. used PF6 as mmc0 CD reference design pin.
8. corrected the style related errors.

Patch 1: adds support for r_pio pin controller.

patch 2: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.

patch 3: adds apb1 clock support, apb1 has different dividers compared to a10 
apb0 clock.

patch 4: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.

patch 5-6: adds mmc and it's clock nodes.

patch 7: adds A83T PRCM related clocks, clock resets.

patch 8: adds r_pio pin controller nodes to dtsi

patch 9: adds RSB controller nodes to dtsi

patch 10: adds common MMC CD detect pin as reference design pin 

patch 11: enables mmc0 support for h8homlet board, tested by LABBE Corentin.

patch 12: This patch adds support for Sinovoip BPI-M3 A83T based board, it has 
2GB LPDDR3, u-boot support is added recently for this board.

patch 13: Adds kconfig for clocks(sun8i-apb0 and sun9i-cpus).


Vishnu Patekar (13):
  pinctrl: sunxi: Add A83T R_PIO controller support
  clk: sunxi: add ahb1 clock for A83T
  clk: sunxi: Add APB1 clock for A83T
  ARM: dts: sun8i-a83t: Add basic clocks and resets
  ARM: dts: sun8i-a83t: add mmc clock nodes
  ARM: dts: sun8i-a83t: Add mmc controller nodes
  ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
  ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
  ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi
  ARM: dts: sun8i-a83t: add mmc0 CD pin
  ARM: dts: sun8i: enable mmc for H8Homlet Board.
  ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board
  ARM: sunxi: Add Kconfig for sunxi clocks

 Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  11 +
 ...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} |  21 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 285 -
 drivers/clk/Kconfig|   1 +
 drivers/clk/sunxi/Kconfig  |   5 +
 drivers/clk/sunxi/Makefile |   4 +-
 drivers/clk/sunxi/clk-sunxi.c  |  89 +++
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 +
 13 files changed, 538 insertions(+), 7 deletions(-)
 copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => 
sun8i-a83t-sinovoip-bpi-m3.dts} (83%)
 create mode 100644 drivers/clk/sunxi/Kconfig
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

-- 
1.9.1

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[linux-sunxi] [PATCH v3 06/13] ARM: dts: sun8i-a83t: Add mmc controller nodes

[Vishnu Patekar]

A83T mmc is compatible with earliers sunxi socs.
This adds mmc0, mmc1, and mmc2 controller nodes for A83T.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 943d8a8..a44d4dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -275,6 +275,63 @@
#size-cells = <1>;
ranges;
 
+   mmc0: mmc@01c0f000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c0f000 0x1000>;
+   clocks = <&bus_gates 8>,
+<&mmc0_clk 0>,
+<&mmc0_clk 1>,
+<&mmc0_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 8>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc1: mmc@01c1 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c1 0x1000>;
+   clocks = <&bus_gates 9>,
+<&mmc1_clk 0>,
+<&mmc1_clk 1>,
+<&mmc1_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 9>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc2: mmc@01c11000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c11000 0x1000>;
+   clocks = <&bus_gates 10>,
+<&mmc2_clk 0>,
+<&mmc2_clk 1>,
+<&mmc2_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 10>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
-- 
1.9.1

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[linux-sunxi] [PATCH v3 02/13] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 76 +++
 2 files changed, 77 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index c09f59b..2ee7841 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -29,6 +29,7 @@ Required properties:
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+   "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 99f60ef..0ae1f09 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
req->rate >>= req->p;
 }
 
+#define SUN8I_A83T_AHB1_PARENT_PLL62
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+   u8 div, calcp, calcm = 1;
+
+   /*
+* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency
+*/
+   if (req->parent_rate && req->rate > req->parent_rate)
+   req->rate = req->parent_rate;
+
+   div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+   /* calculate pre-divider if parent is pll6 */
+   if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+   if (div < 4)
+   calcp = 0;
+   else if (div / 2 < 4)
+   calcp = 1;
+   else if (div / 4 < 4)
+   calcp = 2;
+   else
+   calcp = 3;
+
+   calcm = DIV_ROUND_UP(div, 1 << calcp);
+   } else {
+   calcp = __roundup_pow_of_two(div);
+   calcp = calcp > 3 ? 3 : calcp;
+}
+
+   req->rate = (req->parent_rate / calcm) >> calcp;
+   req->p = calcp;
+   req->m = calcm - 1;
+}
+
+/**
+* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+*   parent index
+*/
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+   req->rate = req->parent_rate;
+
+/* apply pre-divider first if parent is pll6 */
+   if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+   req->rate /= req->m + 1;
+
+   /* clk divider */
+   req->rate >>= req->p;
+}
+
 /**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data 
__initconst = {
.recalc = sun6i_ahb1_recalc,
 };
 
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+   .mux = 12,
+   .muxmask = BIT(1) | BIT(0),
+   .table = &sun6i_ahb1_config,
+   .getter = sun8i_a83t_get_ahb1_factors,
+   .recalc = sun8i_a83t_ahb1_recalc,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -627,6 +696,13 @@ static void __init sun6i_ahb1_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
   sun6i_ahb1_clk_setup);
 
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+   sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+  sun8i_a83t_ahb1_clk_setup);
+
 static void __init sun4i_apb1_clk_setup(struct device_node *node)
 {
sunxi_factors_clk_setup(node, &sun4i_apb1_data);
-- 
1.9.1

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[linux-sunxi] [PATCH v3 07/13] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

This adds A83T PRCM related clocks, clock resets.

As a83t apb0 gates clock support is added earlier, this enables it.
Apart from apb0 gates, other added clocks are compatible with
earlier sun8i socs.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a44d4dc..691bbf1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -267,6 +267,44 @@
 "mmc2_output",
 "mmc2_sample";
};
+
+   cpus_clk: clk@01f01400 {
+   compatible = "allwinner,sun9i-a80-cpus-clk";
+   reg = <0x01f01400 0x4>;
+   #clock-cells = <0>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
+   clock-output-names = "cpus";
+   };
+
+   ahb0: ahb0_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <1>;
+   clocks = <&cpus_clk>;
+   clock-output-names = "ahb0";
+   };
+
+   apb0: clk@01f0140c {
+   compatible = "allwinner,sun8i-a23-apb0-clk";
+   reg = <0x01f0140c 0x4>;
+   #clock-cells = <0>;
+   clocks = <&ahb0>;
+   clock-output-names = "apb0";
+   };
+
+   apb0_gates: clk@01f01428 {
+   compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
+   reg = <0x01f01428 0x4>;
+   #clock-cells = <1>;
+   clocks = <&apb0>;
+   clock-indices = <0>, <1>,
+   <2>, <3>,
+   <4>, <6>, <7>;
+   clock-output-names = "apb0_pio", "apb0_ir",
+   "apb0_timer", "apb0_rsb",
+   "apb0_uart", "apb0_i2c0", "apb0_twd";
+   };
};
 
soc {
@@ -421,5 +459,11 @@
#interrupt-cells = <3>;
interrupts = ;
};
+
+   apb0_reset: reset@01f014b0 {
+   reg = <0x01f014b0 0x4>;
+   compatible = "allwinner,sun6i-a31-clock-reset";
+   #reset-cells = <1>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v3 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Vishnu Patekar]

This adds A83T system bus clocks, bus gates, and clock resets.

Three ahb reset registers are combined into one node.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 114 +-
 1 file changed, 112 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d3473f8..2689af4 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -146,6 +146,97 @@
clocks = <&osc16M>;
clock-output-names = "osc16M-d512";
};
+
+   pll6: clk@01c20028 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun9i-a80-pll4-clk";
+   reg = <0x01c20028 0x4>;
+   clocks = <&osc24M>;
+   clock-output-names = "pll6";
+   };
+
+   pll6d2: pll6d2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clock-div = <2>;
+   clock-mult = <1>;
+   clocks = <&pll6>;
+   clock-output-names = "pll6d2";
+   };
+
+   ahb1: clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-ahb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "ahb1";
+   };
+
+   apb1: apb1_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-apb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&ahb1>;
+   clock-output-names = "apb1";
+   };
+
+   apb2: clk@01c20058 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-apb1-clk";
+   reg = <0x01c20058 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "apb2";
+   };
+
+   ahb2: clk@01c2005c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ahb2-clk";
+   reg = <0x01c2005c 0x4>;
+   clocks = <&ahb1>, <&pll6d2>;
+   clock-output-names = "ahb2";
+   };
+
+   bus_gates: clk@01c20060 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun8i-a83t-bus-gates-clk";
+   reg = <0x01c20060 0x10>;
+   clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+   clock-names = "ahb1", "ahb2", "apb1", "apb2";
+   clock-indices = <1>, <5>, <6>,
+   <8>, <9>, <10>,
+   <13>, <14>, <17>,
+   <19>, <20>,
+   <21>, <24>,
+   <26>, <27>,
+   <29>, <32>,
+   <36>, <37>,
+   <40>, <43>,
+   <44>, <52>, <53>,
+   <54>, <65>,
+   <69>, <76>, <77>,
+   <78>, <79>, <96>,
+   <97>, <98>,
+   <112>, <113>,
+   <114>, <115>,
+   <116>;
+   clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
+"bus_mmc0", "bus_mmc1", "bus_mmc2",
+"bus_nand", "bus_sdram", 
"bus_emac",
+"bus_hstimer", "bus_spi0

[linux-sunxi] [PATCH v3 01/13] pinctrl: sunxi: Add A83T R_PIO controller support

[Vishnu Patekar]

The A83T has R_PIO pin controller, it's same as A23, execpt A83T
interrupt bit is 6th and A83T has one extra pin PL12.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..f9ff10b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,6 +20,7 @@ Required properties:
   "allwinner,sun9i-a80-pinctrl"
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun8i-a83t-r-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..eeab50b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -51,6 +51,11 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_A83T_R
+   def_bool MACH_SUN8I
+   depends on RESET_CONTROLLER
+   select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..bfd4fa0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)   += 
pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)  += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
new file mode 100644
index 000..11787894
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -0,0 +1,119 @@
+/*
+ * Allwinner A83T SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai 
+ * Copyright (C) 2014 Maxime Ripard 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+  

[linux-sunxi] Re: [PATCH v2 13/13] ARM: sunxi: Introduce MACH_SUN8I_A83T option

[Vishnu Patekar]

Hello Maxime,

On Tue, Mar 1, 2016 at 3:12 PM, Maxime Ripard
 wrote:
> Hi,
>
> On Sun, Feb 28, 2016 at 11:18:58PM +0800, Vishnu Patekar wrote:
>> A83T has CPUS clock similar to A80's. currently, a80 cpus clock only
>> compiled for A80. So, Introduce MACH_SUN8I_A83T to compile it for
>> A83T as well.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  arch/arm/mach-sunxi/Kconfig | 5 +
>>  drivers/clk/sunxi/Makefile  | 3 +++
>>  2 files changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>> index c124d65..424b76d 100644
>> --- a/arch/arm/mach-sunxi/Kconfig
>> +++ b/arch/arm/mach-sunxi/Kconfig
>> @@ -41,6 +41,11 @@ config MACH_SUN8I
>>   select ARM_GIC
>>   select MFD_SUN6I_PRCM
>>
>> +config MACH_SUN8I_A83T
>> + bool "Allwinner A83T (sun8i) SoCs support"
>> + default ARCH_SUNXI
>> + select ARM_GIC
>> +
>>  config MACH_SUN9I
>>   bool "Allwinner (sun9i) SoCs support"
>>   default ARCH_SUNXI
>> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
>> index 3fd7901..2aabfc4 100644
>> --- a/drivers/clk/sunxi/Makefile
>> +++ b/drivers/clk/sunxi/Makefile
>> @@ -20,6 +20,9 @@ obj-y += clk-usb.o
>>  obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
>>  obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
>>
>> +obj-$(CONFIG_MACH_SUN8I_A83T) += clk-sun8i-apb0.o
>> +obj-$(CONFIG_MACH_SUN8I_A83T) += clk-sun9i-cpus.o
>> +
>
> This is not how it should be done. You should rather create a Kconfig
> option for these clocks, and use def_bool CONFIG_MACH_SUN8I || 
> CONFIG_MACH_SUN9I
>
> Switching to Kconfig for the clocks has been on my todo-list for quite
> some time, I guess these two clocks would be a good start.
Okie, I'll create Kconfig in clk/sunxi as below:
config CLK_SUN8I_APB0
def_bool MACH_SUN9I || MACH_SUN8I_A83T

config CLK_SUN9I_CPUS
def_bool MACH_SUN9I || MACH_SUN8I_A83T

We still need to have MACH_SUN8I_A83T to differentiate between
MFD_SUN6I_PRCM which is used by other sun8i platforms.

>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH v2 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Vishnu Patekar]

Hello Wens,

On Mon, Feb 29, 2016 at 1:29 AM, Chen-Yu Tsai  wrote:
> On Sun, Feb 28, 2016 at 7:18 AM, Vishnu Patekar
>  wrote:
>> This adds A83T system bus clocks, bus gates, and clock resets.
>>
>> Three ahb reset registers are combined into one node.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 114 
>> +-
>>  1 file changed, 112 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> index d3473f8..fa7ded5 100644
>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -146,6 +146,97 @@
>> clocks = <&osc16M>;
>> clock-output-names = "osc16M-d512";
>> };
>> +
>> +   pll6: clk@01c20028 {
>> +   #clock-cells = <0>;
>> +   compatible = "allwinner,sun9i-a80-pll4-clk";
>> +   reg = <0x01c20028 0x4>;
>> +   clocks = <&osc24M>;
>> +   clock-output-names = "pll6";
>> +   };
>> +
>> +   pll6d2: pll6d2_clk {
>> +   #clock-cells = <0>;
>> +   compatible = "fixed-factor-clock";
>> +   clock-div = <2>;
>> +   clock-mult = <1>;
>> +   clocks = <&pll6>;
>> +   clock-output-names = "pll6d2";
>> +   };
>> +
>> +   ahb1: clk@01c20054 {
>> +   #clock-cells = <0>;
>> +   compatible = "allwinner,sun8i-a83t-ahb1-clk";
>> +   reg = <0x01c20054 0x4>;
>> +   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
>> +   clock-output-names = "ahb1";
>> +   };
>> +
>> +   apb1: apb1_clk@01c20054 {
>> +   #clock-cells = <0>;
>> +   compatible = "allwinner,sun8i-a83t-apb1-clk";
>> +   reg = <0x01c20054 0x4>;
>> +   clocks = <&ahb1>;
>> +   clock-output-names = "apb1";
>> +   };
>> +
>> +   apb2: clk@01c20058 {
>> +   #clock-cells = <0>;
>> +   compatible = "allwinner,sun4i-a10-apb1-clk";
>> +   reg = <0x01c20058 0x4>;
>> +   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
>> +   clock-output-names = "apb2";
>> +   };
>> +
>> +   ahb2: clk@01c2005c {
>> +   #clock-cells = <0>;
>> +   compatible = "allwinner,sun8i-h3-ahb2-clk";
>> +   reg = <0x01c2005c 0x4>;
>> +   clocks = <&ahb1>, <&pll6d2>;
>> +   clock-output-names = "ahb2";
>> +   };
>> +
>> +   bus_gates: clk@01c20060 {
>> +   #clock-cells = <1>;
>> +   compatible = "allwinner,sun8i-a83t-bus-gates-clk";
>> +   reg = <0x01c20060 0x10>;
>> +   clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
>> +   clock-names = "ahb1", "ahb2", "apb1", "apb2";
>> +   clock-indices = <1>, <5>, <6>,
>> +   <8>, <9>, <10>,
>> +   <13>, <14>, <17>,
>> +   <19>, <20>,
>> +   <21>, <24>,
>> +   <26>, <27>,
>> +   <29>, <32>,
>> +   <36>, <37>,
>> +   <40>, <43>,
>> +   <44>, <52>

[linux-sunxi] [PATCH v2 11/13] ARM: dts: sun8i: enable mmc for H8Homlet Board.

[Vishnu Patekar]

This enables mmc0.

Signed-off-by: Vishnu Patekar 
Tested-by: LABBE Corentin 
---
 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..3269f39 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,16 @@
};
 };
 
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
-- 
1.9.1

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[linux-sunxi] [PATCH v2 13/13] ARM: sunxi: Introduce MACH_SUN8I_A83T option

[Vishnu Patekar]

A83T has CPUS clock similar to A80's. currently, a80 cpus clock only
compiled for A80. So, Introduce MACH_SUN8I_A83T to compile it for
A83T as well.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/mach-sunxi/Kconfig | 5 +
 drivers/clk/sunxi/Makefile  | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index c124d65..424b76d 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -41,6 +41,11 @@ config MACH_SUN8I
select ARM_GIC
select MFD_SUN6I_PRCM
 
+config MACH_SUN8I_A83T
+   bool "Allwinner A83T (sun8i) SoCs support"
+   default ARCH_SUNXI
+   select ARM_GIC
+
 config MACH_SUN9I
bool "Allwinner (sun9i) SoCs support"
default ARCH_SUNXI
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3fd7901..2aabfc4 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -20,6 +20,9 @@ obj-y += clk-usb.o
 obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
 obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
 
+obj-$(CONFIG_MACH_SUN8I_A83T) += clk-sun8i-apb0.o
+obj-$(CONFIG_MACH_SUN8I_A83T) += clk-sun9i-cpus.o
+
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
clk-sun8i-apb0.o
-- 
1.9.1

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[linux-sunxi] [PATCH v2 10/13] ARM: dts: sun8i-a83t: add mmc0 CD pin

[Vishnu Patekar]

A83T Boards BPI-m3 and Allwinner H8Homletv2 boards use PF6 as
Card Detect pin., so use PF6 as reference design CD pin in dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 675fc01..c336833 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -390,6 +390,13 @@
allwinner,pull = ;
};
 
+   mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+   allwinner,pins = "PF6";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
-- 
1.9.1

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[linux-sunxi] [PATCH v2 12/13] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

This patch adds support for Sinovoip BPI-M3 A83T based board.

It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 79 
 2 files changed, 80 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 58e461a..c0dd016 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
+   sun8i-a83t-sinovoip-bpi-m3.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
new file mode 100644
index 000..7744b63
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+   model = "Sinovoip BananaPi M3 v1.2";
+   compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
+&r_rsb {
+   status = "okay";
+};
+
+&uart0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart0_pins_b>;
+   status = "okay";
+};
-- 
1.9.1

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[linux-sunxi] [PATCH v2 09/13] ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi

[Vishnu Patekar]

This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A83T dtsi.

Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index af961a8..675fc01 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -476,6 +476,27 @@
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+
+   r_rsb_pins: r_rsb {
+   allwinner,pins = "PL0", "PL1";
+   allwinner,function = "s_rsb";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+   };
+
+   r_rsb: i2c@01f03400 {
+   compatible = "allwinner,sun8i-a23-rsb";
+   reg = <0x01f03400 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 3>;
+   clock-frequency = <300>;
+   resets = <&apb0_reset 3>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&r_rsb_pins>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
};
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v2 07/13] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

This adds A83T PRCM related clocks, clock resets.

As a83t apb0 gates clock support is added earlier, this enables it.
Apart from apb0 gates, other added clocks are compatible with
earlier sun8i socs.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index dfb510e..b184ea3 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -267,6 +267,44 @@
 "mmc2_output",
 "mmc2_sample";
};
+
+   cpus_clk: clk@01f01400 {
+   compatible = "allwinner,sun9i-a80-cpus-clk";
+   reg = <0x01f01400 0x4>;
+   #clock-cells = <0>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
+   clock-output-names = "cpus";
+   };
+
+   ahb0: ahb0_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <1>;
+   clocks = <&cpus_clk>;
+   clock-output-names = "ahb0";
+   };
+
+   apb0: clk@01f0140c {
+   compatible = "allwinner,sun8i-a23-apb0-clk";
+   reg = <0x01f0140c 0x4>;
+   #clock-cells = <0>;
+   clocks = <&ahb0>;
+   clock-output-names = "apb0";
+   };
+
+   apb0_gates: clk@01f01428 {
+   compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
+   reg = <0x01f01428 0x4>;
+   #clock-cells = <1>;
+   clocks = <&apb0>;
+   clock-indices = <0>, <1>,
+   <2>, <3>,
+   <4>, <6>, <7>;
+   clock-output-names = "apb0_pio", "apb0_ir",
+   "apb0_timer", "apb0_rsb",
+   "apb0_uart", "apb0_i2c0", "apb0_twd";
+   };
};
 
soc {
@@ -421,5 +459,11 @@
#interrupt-cells = <3>;
interrupts = ;
};
+
+   apb0_reset: reset@01f014b0 {
+   reg = <0x01f014b0 0x4>;
+   compatible = "allwinner,sun6i-a31-clock-reset";
+   #reset-cells = <1>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v2 08/13] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

[Vishnu Patekar]

Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index b184ea3..af961a8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -465,5 +465,17 @@
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
+
+   r_pio: pinctrl@01f02c00 {
+   compatible = "allwinner,sun8i-a83t-r-pinctrl";
+   reg = <0x01f02c00 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 0>;
+   resets = <&apb0_reset 0>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   #gpio-cells = <3>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH v2 03/13] clk: sunxi: Add APB1 clock for A83T

[Vishnu Patekar]

APB1 is similar to sun4i-a10-apb0-clk, except different dividers.

This adds support for apb1 on A83T.

Signed-off-by: Vishnu Patekar 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 13 +
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 2ee7841..dd24772 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -49,6 +49,7 @@ Required properties:
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
+   "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 0ae1f09..987a12d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -863,6 +863,12 @@ static const struct div_data sun4i_apb0_data __initconst = 
{
.table  = sun4i_apb0_table,
 };
 
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+   .shift  = 8,
+   .pow= 0,
+   .width  = 2,
+};
+
 static void __init sunxi_divider_clk_setup(struct device_node *node,
   const struct div_data *data)
 {
@@ -899,6 +905,13 @@ static void __init sun4i_apb0_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
   sun4i_apb0_clk_setup);
 
+static void __init sun8i_a83t_apb1_clk_setup(struct device_node *node)
+{
+   sunxi_divider_clk_setup(node, &sun8i_a83t_apb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_apb1, "allwinner,sun8i-a83t-apb1-clk",
+  sun8i_a83t_apb1_clk_setup);
+
 static void __init sun4i_axi_clk_setup(struct device_node *node)
 {
sunxi_divider_clk_setup(node, &sun4i_axi_data);
-- 
1.9.1

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[linux-sunxi] [PATCH v2 06/13] ARM: dts: sun8i-a83t: Add mmc controller nodes

[Vishnu Patekar]

A83T mmc is compatible with earliers sunxi socs.
This adds mmc0, mmc1, and mmc2 controller nodes for A83T.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d2a9435..dfb510e 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -275,6 +275,63 @@
#size-cells = <1>;
ranges;
 
+   mmc0: mmc@01c0f000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c0f000 0x1000>;
+   clocks = <&bus_gates 8>,
+<&mmc0_clk 0>,
+<&mmc0_clk 1>,
+<&mmc0_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 8>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc1: mmc@01c1 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c1 0x1000>;
+   clocks = <&bus_gates 9>,
+<&mmc1_clk 0>,
+<&mmc1_clk 1>,
+<&mmc1_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 9>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc2: mmc@01c11000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c11000 0x1000>;
+   clocks = <&bus_gates 10>,
+<&mmc2_clk 0>,
+<&mmc2_clk 1>,
+<&mmc2_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset 10>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
-- 
1.9.1

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[linux-sunxi] [PATCH v2 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Vishnu Patekar]

This adds A83T system bus clocks, bus gates, and clock resets.

Three ahb reset registers are combined into one node.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 114 +-
 1 file changed, 112 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d3473f8..fa7ded5 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -146,6 +146,97 @@
clocks = <&osc16M>;
clock-output-names = "osc16M-d512";
};
+
+   pll6: clk@01c20028 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun9i-a80-pll4-clk";
+   reg = <0x01c20028 0x4>;
+   clocks = <&osc24M>;
+   clock-output-names = "pll6";
+   };
+
+   pll6d2: pll6d2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clock-div = <2>;
+   clock-mult = <1>;
+   clocks = <&pll6>;
+   clock-output-names = "pll6d2";
+   };
+
+   ahb1: clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-ahb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "ahb1";
+   };
+
+   apb1: apb1_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-apb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&ahb1>;
+   clock-output-names = "apb1";
+   };
+
+   apb2: clk@01c20058 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-apb1-clk";
+   reg = <0x01c20058 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "apb2";
+   };
+
+   ahb2: clk@01c2005c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ahb2-clk";
+   reg = <0x01c2005c 0x4>;
+   clocks = <&ahb1>, <&pll6d2>;
+   clock-output-names = "ahb2";
+   };
+
+   bus_gates: clk@01c20060 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun8i-a83t-bus-gates-clk";
+   reg = <0x01c20060 0x10>;
+   clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+   clock-names = "ahb1", "ahb2", "apb1", "apb2";
+   clock-indices = <1>, <5>, <6>,
+   <8>, <9>, <10>,
+   <13>, <14>, <17>,
+   <19>, <20>,
+   <21>, <24>,
+   <26>, <27>,
+   <29>, <32>,
+   <36>, <37>,
+   <40>, <43>,
+   <44>, <52>, <53>,
+   <54>, <65>,
+   <69>, <76>, <77>,
+   <78>, <79>, <96>,
+   <97>, <98>,
+   <112>, <113>,
+   <114>, <115>,
+   <116>;
+   clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
+"bus_mmc0", "bus_mmc1", "bus_mmc2",
+"bus_nand", "bus_sdram", 
"bus_emac",
+"bus_hstimer", "bus_spi0

[linux-sunxi] [PATCH v2 05/13] ARM: dts: sun8i-a83t: add mmc clock nodes

[Vishnu Patekar]

mmc clocks are compatible with that of earlier sun8i socs.
This adds mmc0, mmc1, and mmc2 clock nodes for A83T.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index fa7ded5..d2a9435 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -237,6 +237,36 @@
 "bus_uart2", "bus_uart3",
 "bus_uart4";
};
+
+   mmc0_clk: clk@01c20088 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20088 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc0",
+"mmc0_output",
+"mmc0_sample";
+   };
+
+   mmc1_clk: clk@01c2008c {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c2008c 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc1",
+"mmc1_output",
+"mmc1_sample";
+   };
+
+   mmc2_clk: clk@01c20090 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20090 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc2",
+"mmc2_output",
+"mmc2_sample";
+   };
};
 
soc {
-- 
1.9.1

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[linux-sunxi] [PATCH v2 00/13] Add A83T clk, r_pio, mmc rsb support

[Vishnu Patekar]

Hello,
This is v2 of series which adds further support for A83T, mainly adds clock 
support.
Also adds R_PIO, PRCM related clocks, mmc, rsb support.

A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.

These patches are based on Maxime's sunxi/for-next branch.
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/

v1->v2 Changes:
1. Patches for apb0 gates clock, bus gates, low speed oscillators are already
   merged, so, not included again in this series.
1. sorted the R_PIO Kconfig options.
2. removed un-necessary a83t apb1 div table.
3. combined the three ahb reset registers into one reset node.
4. Changed the bus gates names to bus_spidf and bus_usb_otg.
5. removed un-necessary #address-cells and #size-cells from R_PIO node.
6. splited rsb pins and rsb controller nodes in different patches.
7. used PF6 as mmc0 CD reference design pin.
8. corrected the style related errors.

Patch 1: adds support for r_pio pin controller.

patch 2: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.

patch 3: adds apb1 clock support, apb1 has different dividers compared to a10 
apb0 clock.

patch 4: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.

patch 5-6: adds mmc and it's clock nodes.

patch 7: adds A83T PRCM related clocks, clock resets.

patch 8: adds r_pio pin controller nodes to dtsi

patch 9: adds RSB controller nodes to dtsi

patch 10: adds common MMC CD detect pin as reference design pin 

patch 11: enables mmc0 support for h8homlet board, tested by LABBE Corentin.

patch 12: This patch adds support for Sinovoip BPI-M3 A83T based board, it has 
2GB LPDDR3, u-boot support is added recently for this board.

patch 13: Introduce MACH_SUN8I_A83T config option.

Vishnu Patekar (13):
  pinctrl: sunxi: Add A83T R_PIO controller support
  clk: sunxi: add ahb1 clock for A83T
  clk: sunxi: Add APB1 clock for A83T
  ARM: dts: sun8i-a83t: Add basic clocks and resets
  ARM: dts: sun8i-a83t: add mmc clock nodes
  ARM: dts: sun8i-a83t: Add mmc controller nodes
  ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
  ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
  ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi
  ARM: dts: sun8i-a83t: add mmc0 CD pin
  ARM: dts: sun8i: enable mmc for H8Homlet Board.
  ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board
  ARM: sunxi: Introduce MACH_SUN8I_A83T option

 Documentation/devicetree/bindings/clock/sunxi.txt  |   2 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  11 +
 ...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} |  21 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 285 -
 arch/arm/mach-sunxi/Kconfig|   5 +
 drivers/clk/sunxi/Makefile |   3 +
 drivers/clk/sunxi/clk-sunxi.c  |  89 +++
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 +
 12 files changed, 538 insertions(+), 5 deletions(-)
 copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => 
sun8i-a83t-sinovoip-bpi-m3.dts} (83%)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

-- 
1.9.1

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[linux-sunxi] [PATCH v2 01/13] pinctrl: sunxi: Add A83T R_PIO controller support

[Vishnu Patekar]

The A83T has R_PIO pin controller, it's same as A23, execpt A83T
interrupt bit is 6th and A83T has one extra pin PL12.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..f9ff10b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,6 +20,7 @@ Required properties:
   "allwinner,sun9i-a80-pinctrl"
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun8i-a83t-r-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..eeab50b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -51,6 +51,11 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_A83T_R
+   def_bool MACH_SUN8I
+   depends on RESET_CONTROLLER
+   select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..bfd4fa0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)   += 
pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)  += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
new file mode 100644
index 000..11787894
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -0,0 +1,119 @@
+/*
+ * Allwinner A83T SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai 
+ * Copyright (C) 2014 Maxime Ripard 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+  

[linux-sunxi] [PATCH v2 02/13] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 76 +++
 2 files changed, 77 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index c09f59b..2ee7841 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -29,6 +29,7 @@ Required properties:
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+   "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 99f60ef..0ae1f09 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
req->rate >>= req->p;
 }
 
+#define SUN8I_A83T_AHB1_PARENT_PLL62
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+   u8 div, calcp, calcm = 1;
+
+   /*
+* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency
+*/
+   if (req->parent_rate && req->rate > req->parent_rate)
+   req->rate = req->parent_rate;
+
+   div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+   /* calculate pre-divider if parent is pll6 */
+   if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+   if (div < 4)
+   calcp = 0;
+   else if (div / 2 < 4)
+   calcp = 1;
+   else if (div / 4 < 4)
+   calcp = 2;
+   else
+   calcp = 3;
+
+   calcm = DIV_ROUND_UP(div, 1 << calcp);
+   } else {
+   calcp = __roundup_pow_of_two(div);
+   calcp = calcp > 3 ? 3 : calcp;
+}
+
+   req->rate = (req->parent_rate / calcm) >> calcp;
+   req->p = calcp;
+   req->m = calcm - 1;
+}
+
+/**
+* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+*   parent index
+*/
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+   req->rate = req->parent_rate;
+
+/* apply pre-divider first if parent is pll6 */
+   if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+   req->rate /= req->m + 1;
+
+   /* clk divider */
+   req->rate >>= req->p;
+}
+
 /**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data 
__initconst = {
.recalc = sun6i_ahb1_recalc,
 };
 
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+   .mux = 12,
+   .muxmask = BIT(1) | BIT(0),
+   .table = &sun6i_ahb1_config,
+   .getter = sun8i_a83t_get_ahb1_factors,
+   .recalc = sun8i_a83t_ahb1_recalc,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -627,6 +696,13 @@ static void __init sun6i_ahb1_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
   sun6i_ahb1_clk_setup);
 
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+   sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+  sun8i_a83t_ahb1_clk_setup);
+
 static void __init sun4i_apb1_clk_setup(struct device_node *node)
 {
sunxi_factors_clk_setup(node, &sun4i_apb1_data);
-- 
1.9.1

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[linux-sunxi] Re: [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

Hello Wens,


On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai  wrote:
> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>  wrote:
>> This adds A83T PRCM related clocks, clock resets.
>>
>> As a83t apb0 gates clock support is added earlier, this enables it.
>> Apart from apb0 gates, other added clocks are compatible with
>> earlier sun8i socs.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 
>> +++
>>  1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> index ac96aa1..5ea20ff 100644
>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -268,6 +268,44 @@
>>  "mmc2_output",
>>  "mmc2_sample";
>> };
>> +
>> +   cpus_clk: clk@01f01400 {
>> +   compatible = "allwinner,sun9i-a80-cpus-clk";
>> +   reg = <0x01f01400 0x4>;
>> +   #clock-cells = <0>;
>> +   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, 
>> <&osc16M>;
>> +   clock-output-names = "cpus";
>> +   };
>> +
>> +   ahb0: ahb0_clk {
>> +   compatible = "fixed-factor-clock";
>> +   #clock-cells = <0>;
>> +   clock-div = <1>;
>> +   clock-mult = <1>;
>> +   clocks = <&cpus_clk>;
>> +   clock-output-names = "ahb0";
>> +   };
>> +
>> +   apb0: clk@01f0140c {
>> +   compatible = "allwinner,sun8i-a23-apb0-clk";
>
> This is actually wrong, as it is wrong in sun9i-a80.dtsi.
> I've sent a patch series for it.
A83T apb0 is different from A80, and it's same as A23, so this should
be correct.
Please correct me in case I'm missing something.

> Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
> "allwinner,sun9i-a80-apbs-clk"
> are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.
Okie.
>
> Regards
> ChenYu
>
>> +   reg = <0x01f0140c 0x4>;
>> +   #clock-cells = <0>;
>> +   clocks = <&ahb0>;
>> +   clock-output-names = "apb0";
>> +   };
>> +
>> +   apb0_gates: clk@01f01428 {
>> +   compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
>> +   reg = <0x01f01428 0x4>;
>> +   #clock-cells = <1>;
>> +   clocks = <&apb0>;
>> +   clock-indices = <0>, <1>,
>> +   <2>, <3>,
>> +   <4>, <6>, <7>;
>> +   clock-output-names = "apb0_pio", "apb0_ir",
>> +   "apb0_timer", "apb0_rsb",
>> +   "apb0_uart", "apb0_i2c0", "apb0_twd";
>> +   };
>> };
>>
>> soc {
>> @@ -434,5 +472,11 @@
>> #interrupt-cells = <3>;
>> interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
>> };
>> +
>> +   apb0_reset: reset@01f014b0 {
>> +   reg = <0x01f014b0 0x4>;
>> +   compatible = "allwinner,sun6i-a31-clock-reset";
>> +   #reset-cells = <1>;
>> +   };
>> };
>>  };
>> --
>> 1.9.1
>>

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[linux-sunxi] Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

Hello Maxime,

On Thu, Feb 4, 2016 at 4:01 PM, Maxime Ripard
 wrote:
> On Thu, Feb 04, 2016 at 02:06:45PM +0800, Vishnu Patekar wrote:
>> Hello Maxime,
>>
>>
>> On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
>>  wrote:
>> > Hi,
>> >
>> > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> >> clock index 0b1x is PLL6.
>> >>
>> >> Signed-off-by: Vishnu Patekar 
>> >
>> > If the clock is the same but the parents are different, then we don't
>> > need to duplicate all the logic. Simply add the number of parents to
>> > mux_data, and you're all set.
>>
>> Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
>> 0b10 and 0b11 is pll6/pre_div.
>> So, just adding number of parents to mux_data will not solve problem.
>
> Is anyone using 0b11 ? Can't we just ignore it?
Yes, it's used, 0b11 is pll6 parent in case of A31.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Vishnu Patekar]

Hello Maxime,


On Tue, Feb 2, 2016 at 9:19 PM, Maxime Ripard
 wrote:
> On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
>> From: Chen-Yu Tsai 
>>
>> The A83T does not have a 32.768 kHz low speed oscillator, either as
>> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
>> internal oscillator, which is then divided by 512 for a clock close
>> to 32 kHz.
>>
>> Signed-off-by: Chen-Yu Tsai 
>
> You should have your SoB here.
>
> Is it ok to add it?
Yes, please add.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

Hello Maxime,


On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
 wrote:
> Hi,
>
> On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar 
>
> If the clock is the same but the parents are different, then we don't
> need to duplicate all the logic. Simply add the number of parents to
> mux_data, and you're all set.

Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
0b10 and 0b11 is pll6/pre_div.
So, just adding number of parents to mux_data will not solve problem.

Regards,
Vishnu
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

Hello Wens,



On Tue, Feb 2, 2016 at 3:37 PM, Chen-Yu Tsai  wrote:
>
> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>  wrote:
> > This patch adds support for Sinovoip BPI-M3 A83T based board.
> >
> > It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> > mic, AP6212 Wifi, etc on it.
> > It is paired with AXP813 PMIC which is almost same as AXP818.
> >
> > Signed-off-by: Vishnu Patekar 
> > ---
> >  arch/arm/boot/dts/Makefile   |  1 +
> >  arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 88 
> > 
> >  2 files changed, 89 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 58e461a..c0dd016 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> > sun8i-a33-sinlinx-sina33.dtb \
> > sun8i-a83t-allwinner-h8homlet-v2.dtb \
> > sun8i-a83t-cubietruck-plus.dtb \
> > +   sun8i-a83t-sinovoip-bpi-m3.dtb \
> > sun8i-h3-orangepi-plus.dtb
> >  dtb-$(CONFIG_MACH_SUN9I) += \
> > sun9i-a80-optimus.dtb \
> > diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts 
> > b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> > new file mode 100644
> > index 000..fecc7dc
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> > @@ -0,0 +1,88 @@
> > +/*
> > + * Copyright 2015 Vishnu Patekar
>
> 2016?
>
> > + * Vishnu Patekar 
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This file is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > + * included in all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +#include "sun8i-a83t.dtsi"
> > +#include "sunxi-common-regulators.dtsi"
> > +
> > +/ {
> > +   model = "Sinovoip BananaPi M3 v1.2";
> > +   compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
> > +
> > +   aliases {
> > +   serial0 = &uart0;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:115200n8";
> > +   };
> > +};
> > +
> > +&pio {
> > +   mmc0_cd_pin_bpi_m3: mmc0_cd_pin@0 {
> > +   allwinner,pins = "PF6";
> > +   allwinner,function = "gpio_in";
> > +  

[linux-sunxi] [PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

This patch adds support for Sinovoip BPI-M3 A83T based board.

It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/Makefile   |  1 +
 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 88 
 2 files changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 58e461a..c0dd016 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
+   sun8i-a83t-sinovoip-bpi-m3.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
new file mode 100644
index 000..fecc7dc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+   model = "Sinovoip BananaPi M3 v1.2";
+   compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&pio {
+   mmc0_cd_pin_bpi_m3: mmc0_cd_pin@0 {
+   allwinner,pins = "PF6";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m3>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
+&uart0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart0_pins_b>;
+   status = "okay";
+};
+
+&r_rsb {
+   status = "okay";
+};
-- 
1.9.1

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[linux-sunxi] [PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board.

[Vishnu Patekar]

This enables mmc0.

Signed-off-by: Vishnu Patekar 
Tested-by: LABBE Corentin 
---
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts| 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..6c1f598 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,25 @@
};
 };
 
+&pio {
+   mmc0_cd_pin_h8homlet: mmc0_cd_pin@0 {
+   allwinner,pins = "PF6";
+   allwinner,function = "gpio_in";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+};
+
+&mmc0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h8homlet>;
+   vmmc-supply = <®_vcc3v0>;
+   cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
-- 
1.9.1

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[linux-sunxi] [PATCH 08/14] ARM: dts: sun8i-a83t: add mmc clock nodes

[Vishnu Patekar]

mmc clocks are compatible with that of earlier sun8i socs.
This adds mmc0, mmc1, and mmc2 clock nodes for A83T.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 568d6fb..b8c8b60 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -238,6 +238,36 @@
 "bus_uart2", "bus_uart3",
 "bus_uart4";
};
+
+   mmc0_clk: clk@01c20088 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20088 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc0",
+"mmc0_output",
+"mmc0_sample";
+   };
+
+   mmc1_clk: clk@01c2008c {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c2008c 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc1",
+"mmc1_output",
+"mmc1_sample";
+   };
+
+   mmc2_clk: clk@01c20090 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20090 0x4>;
+   clocks = <&osc24M>, <&pll6>;
+   clock-output-names = "mmc2",
+"mmc2_output",
+"mmc2_sample";
+   };
};
 
soc {
-- 
1.9.1

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[linux-sunxi] [PATCH 12/14] ARM: dts: sun8i-a83t: Add RSB nodes to dtsi

[Vishnu Patekar]

This adds support for RSB
A83T RSB is compatible with A23 rsb.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 11be9e1..8c67c85 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -499,5 +499,19 @@
allwinner,pull = ;
};
};
+
+   r_rsb: i2c@01f03400 {
+   compatible = "allwinner,sun8i-a23-rsb";
+   reg = <0x01f03400 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 3>;
+   clock-frequency = <300>;
+   resets = <&apb0_reset 3>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&r_rsb_pins>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH 11/14] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

[Vishnu Patekar]

Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5ea20ff..11be9e1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -478,5 +478,26 @@
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
+
+   r_pio: pinctrl@01f02c00 {
+   compatible = "allwinner,sun8i-a83t-r-pinctrl";
+   reg = <0x01f02c00 0x400>;
+   interrupts = ;
+   clocks = <&apb0_gates 0>;
+   resets = <&apb0_reset 0>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   #gpio-cells = <3>;
+
+   r_rsb_pins: r_rsb {
+   allwinner,pins = "PL0", "PL1";
+   allwinner,function = "s_rsb";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH 09/14] ARM: dts: sun8i-a83t: Add mmc controller nodes

[Vishnu Patekar]

A83T mmc is compatible with earliers sunxi socs.
This adds mmc0, mmc1, and mmc2 controller nodes for A83T.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index b8c8b60..ac96aa1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -276,6 +276,63 @@
#size-cells = <1>;
ranges;
 
+   mmc0: mmc@01c0f000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c0f000 0x1000>;
+   clocks = <&bus_gates 8>,
+<&mmc0_clk 0>,
+<&mmc0_clk 1>,
+<&mmc0_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset0 8>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc1: mmc@01c1 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c1 0x1000>;
+   clocks = <&bus_gates 9>,
+<&mmc1_clk 0>,
+<&mmc1_clk 1>,
+<&mmc1_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset0 9>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc2: mmc@01c11000 {
+   compatible = "allwinner,sun5i-a13-mmc";
+   reg = <0x01c11000 0x1000>;
+   clocks = <&bus_gates 10>,
+<&mmc2_clk 0>,
+<&mmc2_clk 1>,
+<&mmc2_clk 2>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = <&ahb_reset0 10>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = ,
-- 
1.9.1

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[linux-sunxi] [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

[Vishnu Patekar]

APB1 is similar to sun4i-a10-apb0-clk, except different dividers.

This adds support for apb1 on A83T.

Signed-off-by: Vishnu Patekar 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 17 +
 2 files changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index bfd82f1..10637e7 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -49,6 +49,7 @@ Required properties:
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
+   "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 02bbdf6..6510b0e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -772,6 +772,22 @@ static const struct div_data sun4i_apb0_data __initconst = 
{
.table  = sun4i_apb0_table,
 };
 
+
+static const struct clk_div_table sun8i_a83t_apb1_table[] __initconst = {
+   { .val = 0, .div = 1 },
+   { .val = 1, .div = 2 },
+   { .val = 2, .div = 3 },
+   { .val = 3, .div = 4 },
+   { } /* sentinel */
+};
+
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+   .shift  = 8,
+   .pow= 0,
+   .width  = 2,
+   .table  = sun8i_a83t_apb1_table,
+};
+
 static void __init sunxi_divider_clk_setup(struct device_node *node,
   struct div_data *data)
 {
@@ -1027,6 +1043,7 @@ static const struct of_device_id clk_div_match[] 
__initconst = {
{.compatible = "allwinner,sun8i-a23-axi-clk", .data = 
&sun8i_a23_axi_data,},
{.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
{.compatible = "allwinner,sun4i-a10-apb0-clk", .data = 
&sun4i_apb0_data,},
+   {.compatible = "allwinner,sun8i-a83t-apb1-clk", .data = 
&sun8i_a83t_apb1_data,},
{}
 };
 
-- 
1.9.1

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[linux-sunxi] [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

This adds A83T PRCM related clocks, clock resets.

As a83t apb0 gates clock support is added earlier, this enables it.
Apart from apb0 gates, other added clocks are compatible with
earlier sun8i socs.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index ac96aa1..5ea20ff 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -268,6 +268,44 @@
 "mmc2_output",
 "mmc2_sample";
};
+
+   cpus_clk: clk@01f01400 {
+   compatible = "allwinner,sun9i-a80-cpus-clk";
+   reg = <0x01f01400 0x4>;
+   #clock-cells = <0>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
+   clock-output-names = "cpus";
+   };
+
+   ahb0: ahb0_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <1>;
+   clocks = <&cpus_clk>;
+   clock-output-names = "ahb0";
+   };
+
+   apb0: clk@01f0140c {
+   compatible = "allwinner,sun8i-a23-apb0-clk";
+   reg = <0x01f0140c 0x4>;
+   #clock-cells = <0>;
+   clocks = <&ahb0>;
+   clock-output-names = "apb0";
+   };
+
+   apb0_gates: clk@01f01428 {
+   compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
+   reg = <0x01f01428 0x4>;
+   #clock-cells = <1>;
+   clocks = <&apb0>;
+   clock-indices = <0>, <1>,
+   <2>, <3>,
+   <4>, <6>, <7>;
+   clock-output-names = "apb0_pio", "apb0_ir",
+   "apb0_timer", "apb0_rsb",
+   "apb0_uart", "apb0_i2c0", "apb0_twd";
+   };
};
 
soc {
@@ -434,5 +472,11 @@
#interrupt-cells = <3>;
interrupts = ;
};
+
+   apb0_reset: reset@01f014b0 {
+   reg = <0x01f014b0 0x4>;
+   compatible = "allwinner,sun6i-a31-clock-reset";
+   #reset-cells = <1>;
+   };
};
 };
-- 
1.9.1

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[linux-sunxi] [PATCH 02/14] clk: sunxi: Add apb0 gates for A83T

[Vishnu Patekar]

APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.

Signed-off-by: Vishnu Patekar 
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..7f19ef5 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -39,6 +39,7 @@ Required properties:
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
+   "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
diff --git a/drivers/clk/sunxi/clk-simple-gates.c 
b/drivers/clk/sunxi/clk-simple-gates.c
index f4da52b..2cfc5a8 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, 
"allwinner,sun8i-a23-apb2-gates-clk",
   sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
   sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_apb0, "allwinner,sun8i-a83t-apb0-gates-clk",
+  sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
   sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
-- 
1.9.1

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[linux-sunxi] [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Vishnu Patekar]

From: Chen-Yu Tsai 

The A83T does not have a 32.768 kHz low speed oscillator, either as
an external crystal or input. It has a 16 MHz RC-based (inaccurate)
internal oscillator, which is then divided by 512 for a clock close
to 32 kHz.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 8d27b63..45b725c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -118,6 +118,7 @@
#size-cells = <1>;
ranges;
 
+   /* TODO: PRCM block has a mux for this. */
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -125,11 +126,25 @@
clock-output-names = "osc24M";
};
 
-   osc32k: osc32k_clk {
+   /*
+* This is called "internal OSC" in some places.
+* It is an internal RC-based oscillator.
+* TODO: Its controls are in the PRCM block.
+*/
+   osc16M: osc16M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
-   clock-frequency = <32768>;
-   clock-output-names = "osc32k";
+   clock-frequency = <1600>;
+   clock-output-names = "osc16M";
+   };
+
+   osc16Md512: osc16Md512_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clock-div = <512>;
+   clock-mult = <1>;
+   clocks = <&osc16M>;
+   clock-output-names = "osc16Md512";
};
};
 
-- 
1.9.1

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[linux-sunxi] [PATCH 00/14] Add A83T clk, r_pio, mmc rsb support

[Vishnu Patekar]

Hello,
This series adds further support for A83T, mainly adds clock support.
Also adds R_PIO, PRCM related clocks, mmc, rsb support.

A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.

Patch 1: adds support for r_pio pin controller.

patch 2: adds PRCM apb0 clock gates, it controls prcm related clocks.

patch 3: adds bus gates which are similar to h3, it's not clearly known which
clocks belongs to which parent.

patch 4: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.

patch 5: adds apb1 clock support, apb1 has different dividers compared to a10 
apb0 clock.

patch 6: this patch is form wens, a83t has 16M internal oscillator, to get 
aproximately 32k clock, it's divided by 512.

patch 7: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.

patch 8-9: adds mmc and it's clock nodes.

patch 10: adds A83T PRCM related clocks, clock resets.

patch 11: adds r_pio pin controller nodes to dtsi

patch 12: adds RSB nodes to dtsi

patch 13: enables mmc0 support for h8homlet board, tested by LABBE Corentin.

patch 14: This patch adds support for Sinovoip BPI-M3 A83T based board, it has 
2GB LPDDR3, u-boot support is added recently for this board.


Regards,
Vishnu

Chen-Yu Tsai (1):
  ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

Vishnu Patekar (13):
  pinctrl: sunxi: Add A83T R_PIO controller support
  clk: sunxi: Add apb0 gates for A83T
  clk: sunxi: add bus gates for A83T
  clk: sunxi: add ahb1 clock for A83T
  clk: sunxi: Add APB1 clock for A83T
  ARM: dts: sun8i-a83t: Add basic clocks and resets
  ARM: dts: sun8i-a83t: add mmc clock nodes
  ARM: dts: sun8i-a83t: Add mmc controller nodes
  ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
  ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
  ARM: dts: sun8i-a83t: Add RSB nodes to dtsi
  ARM: dts: sun8i: enable mmc for H8Homlet Board.
  ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

 Documentation/devicetree/bindings/clock/sunxi.txt  |   4 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  20 ++
 ...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} |  28 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 314 -
 drivers/clk/sunxi/clk-simple-gates.c   |   2 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c|   2 +
 drivers/clk/sunxi/clk-sunxi.c  |  92 ++
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 
 12 files changed, 582 insertions(+), 7 deletions(-)
 copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => 
sun8i-a83t-sinovoip-bpi-m3.dts} (79%)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

-- 
1.9.1

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[linux-sunxi] [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c | 75 +++
 2 files changed, 76 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 4514d77..bfd82f1 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -29,6 +29,7 @@ Required properties:
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+   "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index e460a6b..02bbdf6 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
req->rate >>= req->p;
 }
 
+
+#define SUN8I_A83T_AHB1_PARENT_PLL62
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+   u8 div, calcp, calcm = 1;
+
+   /*
+* clock can only divide, so we will never be able to achieve
+* frequencies higher than the parent frequency
+*/
+   if (req->parent_rate && req->rate > req->parent_rate)
+   req->rate = req->parent_rate;
+
+   div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+   /* calculate pre-divider if parent is pll6 */
+   if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+   if (div < 4)
+   calcp = 0;
+   else if (div / 2 < 4)
+   calcp = 1;
+   else if (div / 4 < 4)
+   calcp = 2;
+   else
+   calcp = 3;
+
+   calcm = DIV_ROUND_UP(div, 1 << calcp);
+   } else {
+   calcp = __roundup_pow_of_two(div);
+   calcp = calcp > 3 ? 3 : calcp;
+   }
+
+   req->rate = (req->parent_rate / calcm) >> calcp;
+   req->p = calcp;
+   req->m = calcm - 1;
+}
+
+/**
+ * sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+ *  parent index
+ */
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+   req->rate = req->parent_rate;
+
+   /* apply pre-divider first if parent is pll6 */
+   if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+   req->rate /= req->m + 1;
+
+   /* clk divider */
+   req->rate >>= req->p;
+}
 /**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data 
__initconst = {
.recalc = sun6i_ahb1_recalc,
 };
 
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+   .mux = 12,
+   .muxmask = BIT(1) | BIT(0),
+   .table = &sun6i_ahb1_config,
+   .getter = sun8i_a83t_get_ahb1_factors,
+   .recalc = sun8i_a83t_ahb1_recalc,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -592,6 +661,12 @@ static void __init sun6i_ahb1_clk_setup(struct device_node 
*node)
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
   sun6i_ahb1_clk_setup);
 
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+   sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+  sun8i_a83t_ahb1_clk_setup);
 
 /**
  * sunxi_mux_clk_setup() - Setup function for muxes
-- 
1.9.1

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[linux-sunxi] [PATCH 07/14] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Vishnu Patekar]

This adds A83T system bus clocks, bus gates, and clock resets.

For ahb1 and ahb2, it's not clear which reset belongs to ahb1
or ahb2; so named as ahb_reset0, ahb_reset1, ahb_reset2.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 127 +-
 1 file changed, 125 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 45b725c..568d6fb 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -146,6 +146,98 @@
clocks = <&osc16M>;
clock-output-names = "osc16Md512";
};
+
+
+   pll6: clk@01c20028 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun9i-a80-pll4-clk";
+   reg = <0x01c20028 0x4>;
+   clocks = <&osc24M>;
+   clock-output-names = "pll6";
+   };
+
+   pll6d2: pll6d2_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-factor-clock";
+   clock-div = <2>;
+   clock-mult = <1>;
+   clocks = <&pll6>;
+   clock-output-names = "pll6d2";
+   };
+
+   ahb1: ahb1_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-ahb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "ahb1";
+   };
+
+   ahb2: ahb2_clk@01c2005c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ahb2-clk";
+   reg = <0x01c2005c 0x4>;
+   clocks = <&ahb1>, <&pll6d2>;
+   clock-output-names = "ahb2";
+   };
+
+   apb1: apb1_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a83t-apb1-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = <&ahb1>;
+   clock-output-names = "apb1";
+   };
+
+   apb2: clk@01c20058 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-apb1-clk";
+   reg = <0x01c20058 0x4>;
+   clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+   clock-output-names = "apb2";
+   };
+
+   bus_gates: clk@01c20060 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun8i-a83t-bus-gates-clk";
+   reg = <0x01c20060 0x10>;
+   clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+   clock-names = "ahb1", "ahb2", "apb1", "apb2";
+   clock-indices = <1>, <5>, <6>,
+   <8>, <9>, <10>,
+   <13>, <14>, <17>,
+   <19>, <20>,
+   <21>, <24>,
+   <26>, <27>,
+   <29>, <32>,
+   <36>, <37>,
+   <40>, <43>,
+   <44>, <52>, <53>,
+   <54>, <65>,
+   <69>, <76>, <77>,
+   <78>, <79>, <96>,
+   <97>, <98>,
+   <112>, <113>,
+   <114>, <115>,
+   <116>;
+   clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
+"bus_mmc0", "bus_mmc1", "bus_mmc2",
+"bus_nand", "bus_sdram", 
"bus_emac",
+  

[linux-sunxi] [PATCH 03/14] clk: sunxi: add bus gates for A83T

[Vishnu Patekar]

A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar 
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c   | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 7f19ef5..4514d77 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -59,6 +59,7 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
+   "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c 
b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index 1113eb9..63fdb79 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -109,3 +109,5 @@ err_unmap:
 
 CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
   sun8i_h3_bus_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
+  sun8i_h3_bus_gates_init);
-- 
1.9.1

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[linux-sunxi] [PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Vishnu Patekar]

The A83T has R_PIO pin controller, it's same as A23, execpt A83T
interrupt bit is 6th and A83T has one extra pin PL12.

Signed-off-by: Vishnu Patekar 
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c   | 119 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..f9ff10b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,6 +20,7 @@ Required properties:
   "allwinner,sun9i-a80-pinctrl"
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun8i-a83t-r-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..c0e4a8b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -46,6 +46,11 @@ config PINCTRL_SUN8I_A83T
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_A83T_R
+   def_bool MACH_SUN8I
+   depends on RESET_CONTROLLER
+   select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..bfd4fa0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)   += 
pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)  += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
new file mode 100644
index 000..11787894
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -0,0 +1,119 @@
+/*
+ * Allwinner A83T SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2016 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai 
+ * Copyright (C) 2014 Maxime Ripard 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"),/* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+ SUNXI_FUNCTIO

Re: [linux-sunxi] Re: [PATCH] 1-wire sunxi enhancement

[Vishnu Patekar]

Hello Peter,
Thanks for the initiative.

Linux-sunxi community members are very helpful, and active, It would
be great, if you could start working on it, whatever questions, doubt
you encounter while doing this, just ask on  #linux-sunxi IRC channel.

Once you've minimal working driver for this, send patch, you'll be
guided in right direction.


Regards,
Vishnu

On Fri, Jan 22, 2016 at 12:09 AM,   wrote:
> Sorry to digg up this old thread, but I was wondering if someone is working 
> on integrating this with the mainline kernel.
> It is listed on the wiki under one of the easy things, but unfortunately my 
> 1-wire knowledge and kernel development skills are too limited to get this 
> started.
>
> Perhaps someone is interested in having a go as a side project to take the 
> mind off some of the more difficult items in progress and who knows boost 
> creativity? :-)
>
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[linux-sunxi] Re: SDIO WIFI (brcm43430)

[Vishnu Patekar]

Hello Arend,

On Tue, Jan 19, 2016 at 5:20 PM, Arend van Spriel  wrote:
> On 19-1-2016 2:30, Vishnu Patekar wrote:
>> Hello Arend,
>>
>> I've A83T BPI-m3 board, which includes AP6212(brcm43430). I'm trying
>> to make it work for mainline linux and brcm driver.
>>
>> After enabling mmc1, It could read vendor: 0x02d0 device: 0xa9a6. from
>> /sys/bus/mmc/devices/mmc1:0001/mmc1:0001:1
>>
>> BRCM driver loads the firmware files, however, it gives below errors
>> and wlan0 is not available:
>>
>> dmesg | grep brcm
>> [1.187459] brcmfmac: brcmf_of_probe: interrupt could not be mapped
>
> Not sure whether this might cause an issue. Could be a devicetree issue.

Yes, it was a device tree issue, it's now fixed.

still, it's not working,
[2.319200] brcmfmac: brcmf_sdio_firmware_callback failed:
dev=mmc1:0001:1, err=0
.
.
[4.405585] brcmfmac: brcmf_sdio_remove Disconnected

detailed log with brcmfmac.debug=30, :http://pastebin.com/PbJYxFhP

>
> Regards,
> Arend
>
>> [1.194419] brcmfmac: F1 signature read @0x1800=0x1530a9a6
>> [1.197807] brcmfmac: brcmf_sdio_drivestrengthinit: No SDIO Drive
>> strength init done for chip 43430 rev 0 pmurev 24
>> [2.310138] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (100):
>> clkctl 0x50
>> [3.319433] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (100):
>> clkctl 0x50
>> [4.349022] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (100):
>> clkctl 0x50
>>
>>
>> There are no brcm43430 firmware files at
>> http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/brcm
>> So, used firmware:
>> https://github.com/RPi-Distro/firmware-nonfree/tree/master/brcm80211/brcm/brcmfmac43430-sdio.bin
>> and .txt.
>>
>> Could you please help me in this regard ?
>>
>>
>> Regards,
>> Vishnu
>>

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[linux-sunxi] SDIO WIFI (brcm43430)

[Vishnu Patekar]

Hello Arend,

I've A83T BPI-m3 board, which includes AP6212(brcm43430). I'm trying
to make it work for mainline linux and brcm driver.

After enabling mmc1, It could read vendor: 0x02d0 device: 0xa9a6. from
/sys/bus/mmc/devices/mmc1:0001/mmc1:0001:1

BRCM driver loads the firmware files, however, it gives below errors
and wlan0 is not available:

dmesg | grep brcm
[1.187459] brcmfmac: brcmf_of_probe: interrupt could not be mapped
[1.194419] brcmfmac: F1 signature read @0x1800=0x1530a9a6
[1.197807] brcmfmac: brcmf_sdio_drivestrengthinit: No SDIO Drive
strength init done for chip 43430 rev 0 pmurev 24
[2.310138] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (100):
clkctl 0x50
[3.319433] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (100):
clkctl 0x50
[4.349022] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (100):
clkctl 0x50


There are no brcm43430 firmware files at
http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/brcm
So, used firmware:
https://github.com/RPi-Distro/firmware-nonfree/tree/master/brcm80211/brcm/brcmfmac43430-sdio.bin
and .txt.

Could you please help me in this regard ?


Regards,
Vishnu

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[linux-sunxi] Re: [PATCH 1/5] power: axp818: Remove duplicate register definition macros

[Vishnu Patekar]

Hello Wens,

Thanks for correcting it.

Regards,
Vishnu

On Tue, Jan 12, 2016 at 2:42 PM, Chen-Yu Tsai  wrote:
> Some of the register definitions are duplicated. Drop them.
>
> Signed-off-by: Chen-Yu Tsai 
> ---
>  include/axp818.h | 8 
>  1 file changed, 8 deletions(-)
>
> diff --git a/include/axp818.h b/include/axp818.h
> index 1dc6456..46d05ad 100644
> --- a/include/axp818.h
> +++ b/include/axp818.h
> @@ -32,13 +32,6 @@
>  #define AXP818_OUTPUT_CTRL3_ALDO2_EN   (1 << 6)
>  #define AXP818_OUTPUT_CTRL3_ALDO3_EN   (1 << 7)
>
> -#define AXP818_DCDC1_CTRL  0x20
> -#define AXP818_DCDC2_CTRL  0x21
> -#define AXP818_DCDC3_CTRL  0x22
> -#define AXP818_DCDC4_CTRL  0x23
> -#define AXP818_DCDC5_CTRL  0x24
> -#define AXP818_DCDC6_CTRL  0x25
> -
>  #define AXP818_DLDO1_CTRL  0x15
>  #define AXP818_DLDO2_CTRL  0x16
>  #define AXP818_DLDO3_CTRL  0x17
> @@ -46,7 +39,6 @@
>  #define AXP818_ELDO1_CTRL  0x19
>  #define AXP818_ELDO2_CTRL  0x1a
>  #define AXP818_ELDO3_CTRL  0x1b
> -#define AXP818_ELDO3_CTRL  0x1b
>  #define AXP818_FLDO1_CTRL  0x1c
>  #define AXP818_FLDO2_3_CTRL0x1d
>  #define AXP818_DCDC1_CTRL  0x20
> --
> 2.6.4
>

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[linux-sunxi] [PATCH v4 0/3] Add basic support for Allwinner A83T SOC

[Vishnu Patekar]

Hello,

Re-sending after corrections, I've some more patches on top of this will send
them separately to avoid delaying this one with new comments.

This patch series adds very basic support for Allwinner A83T SOC.
Clock, peripherals, smp support will be added later.

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.

Note: A83T pincontroller patch is already applied by Linus, so not added in this
patch.

changes from v3->v4
1. arranged sub nodes in soc as per address.
2. removed memory node.
3. corrected style problem in dtsi.

changes from v2->v3
1. removed "Not Supported" for A83T in sunxi/README
2. removed un-unsed nodes from dtsi.
3. corrected GIC_SPI number for PH_EINT in dtsi.
4. removed address at soc node which was un-necessary.
5. corrected reg<> addresses for cpu nodes.
6. changed cpu mask to 8 in gic and archtimer node.


changes from v1->v2:
1. used UART0 header with PB9, PB10 pins.
2. removed unnecessary includes and comments from dtsi.
3. arranged nodes in alphabatical order.
4. arrnaged compatible in alphabatical order.
5. changed cpu nodes to use cpu@100 -cpu@-103.
6. changed dts filename.

Vishnu Patekar (3):
  ARM: sunxi: Introduce Allwinner for A83T support
  ARM: dts: sun8i: Add Allwinner A83T dtsi
  ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner

 Documentation/arm/sunxi/README |   1 -
 Documentation/devicetree/bindings/arm/sunxi.txt|   1 +
 arch/arm/boot/dts/Makefile |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  64 +++
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 204 +
 arch/arm/mach-sunxi/sunxi.c|   1 +
 drivers/clk/sunxi/clk-sunxi.c  |   6 +
 7 files changed, 277 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
 create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi

-- 
1.9.1

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[linux-sunxi] [PATCH v4 3/3] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner

[Vishnu Patekar]

H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.

A83T patches are tested on this board.
It has UART, ethernet, USB, HDMI, etc ports on it.

For FEL mode it needs USB A-A(Male) cable. I used uart0 which
is multiplexed to microsd pins PF2 and PF4.

Enabled UART0 Header(PB9, PB10 pins).

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/Makefile |  1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 64 ++
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cc7309b..0f81c58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -662,6 +662,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
+   sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
new file mode 100644
index 000..342e1d3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+   model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
+   compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&uart0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart0_pins_b>;
+   status = "okay";
+};
-- 
1.9.1

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[linux-sunxi] [PATCH v4 1/3] ARM: sunxi: Introduce Allwinner for A83T support

[Vishnu Patekar]

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.

Signed-off-by: Vishnu Patekar 
Acked-by: Rob Herring 
Acked-by: Chen-Yu Tsai 
---
 Documentation/arm/sunxi/README  | 1 -
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c | 1 +
 drivers/clk/sunxi/clk-sunxi.c   | 6 ++
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 430d279..e5a115f 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -72,6 +72,5 @@ SunXi family
 
 * Octa ARM Cortex-A7 based SoCs
   - Allwinner A83T
-+ Not Supported
 + Datasheet
   http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index bb9b0faa..7e79fcc 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -11,5 +11,6 @@ using one of the following compatible strings:
   allwinner,sun7i-a20
   allwinner,sun8i-a23
   allwinner,sun8i-a33
+  allwinner,sun8i-a83t
   allwinner,sun8i-h3
   allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index c2be98f..3c15619 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -69,6 +69,7 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
+   "allwinner,sun8i-a83t",
"allwinner,sun8i-h3",
NULL,
 };
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 5ba2188..0d45253 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1219,6 +1219,12 @@ CLK_OF_DECLARE(sun8i_a23_clk_init, 
"allwinner,sun8i-a23", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
 
+static void __init sun8i_a83t_init_clocks(struct device_node *node)
+{
+   sunxi_init_clocks(NULL, 0);
+}
+CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t", 
sun8i_a83t_init_clocks);
+
 static void __init sun9i_init_clocks(struct device_node *node)
 {
sunxi_init_clocks(NULL, 0);
-- 
1.9.1

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[linux-sunxi] [PATCH v4 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi

[Vishnu Patekar]

Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 204 ++
 1 file changed, 204 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
new file mode 100644
index 000..90cc09b
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ *
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+
+ */
+
+#include "skeleton.dtsi"
+
+#include 
+
+#include 
+
+/ {
+   interrupt-parent = <&gic>;
+
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+
+   cpu@100 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x100>;
+   };
+
+   cpu@101 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x101>;
+   };
+
+   cpu@102 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x102>;
+   };
+
+   cpu@103 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x103>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M_clk {
+

Re: [linux-sunxi] Another take on sunxi-tools.

[Vishnu Patekar]

Hello Eddy,

I simply cloned and tried to follow README.
It does not have configure.

When tried, "autoconf" it gave below error:

configure.ac:6: error: possibly undefined macro: AM_INIT_AUTOMAKE
  If this token and others are legitimate, please use m4_pattern_allow.
  See the Autoconf documentation.
configure.ac:19: error: possibly undefined macro: AM_CONDITIONAL


It would be great if README lists dependancies if any.

Note: System: ubuntu 14.04

Regards,
Vishnu Patekar

On Wed, Jan 6, 2016 at 11:55 AM, Eddy Beaupré  wrote:
> A few weeks ago, i kinda got angry at the command line parser of
> sunxi-nand-part and its inability to figure out on what kind of device it is
> running. What started as a simple hack to at least make it figure out the
> current partition scheme of the device became a complete rewrite.
>
> My version can create, delete, and insert partitions, it can create a brand
> new MBR on the device, it can work on image file directly. It can do silly
> things like creating a SUN4I partition on a SUN7I device. It can backup or
> restore MBR, and it can figure out the current type of partition.
>
> Since that went well, i told myself, that i could probably make the build
> process a little bit more user friendly, So i rewrote it to work with
> autoconf/automake (forgetting that i already did that about 3 years ago and
> it was already in another branch of the official sunxi-tools). But did it
> more wisely this time.
>
> Each tool is built by its own set of tools. The main builder just try to
> figure out what tools can be build and chain them, It can cross-compile
> almost everything (the only tool that can't be cross-compiled is sunxi-fel,
> because of its dependency with libusb). It will avoid doing silly things
> (like build an x86 version of sunxi-pio).
>
> The main drawback of the new modular build system is its speed. It take a
> whooping 2m7s on a Cubetruck to configure and build everything (tools and
> bare metal tools).
>
> Another thing that bugged me was the lack of man pages, so i wrote a bunch
> of man pages to document a bit each tools.
>
> To continue on what has been done, i added a sunxi- prefix to all the tools
> that didn't had one. Even fex2bin and bin2fex are now prefixed with sunxi-
> (sunxi-fexc now just check if bin2fex or fex2bin appear in its executable
> name to select its mode, no longer an exact match).
>
> Since theses changes ended up with something very different than the current
> tools, and after a little chat with Siarhei Siamashka, i think the best
> thing to do is just keep all this as a fork of sunxi-tools and not submit
> many many many patches and try to have this merge with the official
> sunxi-tools.
>
> Everything is available on my fork if you want to play with it:
>
> https://github.com/armStrapTools/sunxi-tools
>
>
> --
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Re: [linux-sunxi] reason for Allwinner SoC specific pinctrl drivers?

[Vishnu Patekar]

Hello Andre,
This is something we can do for future SOCs.

On 4 Jan 2016 19:02, "Andre Przywara"  wrote:
>
> Hi,
>
> while looking at the Allwinner A64 SoC support, I was wondering why we
> would actually need a pinctrl driver (file) for each and every Allwinner
> SoC that we support.
> Looking at both the A20 and the A64 doc I don't see any differences in
> the port controller implementation apart from the actual
> muxval <-> subsystem assignment, which is just data, right?
> Comparing the code files in drivers/pinctrl/sunxi seems to support this,
> as those drivers only consist of the table and some boilerplate code.
>
> Now I was wondering whether we could get away with one generic Allwinner
> pinctrl driver and put the SoC specific pin assignments in DT instead.
> It looks like adding an "allwinner,muxval" property in addition to the
> existing "allwinner,function" in the SoC's .dtsi would give us all the
> information we need. This could look like:
>
> uart0_pins_a: uart0@0 {
> allwinner,pins =   "PB22", "PB23";
> +   allwinner,muxval = <0x020x02>;
> allwinner,function = "uart0";
> allwinner,drive = ;
> allwinner,pull = ;
> };
>
> Would it make sense that I sit down and prototype such a driver?
>
> We should keep compatibility with older DTs by keeping the existing
> drivers in (or maybe emulating the current behaviour by providing just
> those tables as a fallback) , but newer SoCs (like the A64?) would not
> need a SoC specific driver, but just go with that generic driver and
> appropriate DT properties.
>
> I appreciate any comments on this, especially if I missed something
> which would render this approach impossible or tedious.
AFAIK, there are lot of holes in pin conf registers.
This will complicate the dtsi configuration.
The current pinctrl driver is best possible solution with respect to time
and availability of limited people working on sunxi with the cost of
increase in code size.

It's better to give it a shot to make it generic driver for future SOCs
atleast. Like A83, A64, etc.

Possible solution will always be examined by experts Linus, Maxine, etc.

Regards,
Vishnu

>
> Cheers,
> Andre.
>
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Re: [linux-sunxi] [RFC PATCH] drivers: pinctrl: add driver for Allwinner A64 SoC

[Vishnu Patekar]

 "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"),  /* D3 */
> + SUNXI_FUNCTION_IRQ(0x6, 5)),  /* EINT5 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart1"), /* TX */
> + SUNXI_FUNCTION_IRQ(0x6, 6)),  /* EINT6 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart1"), /* RX */
> + SUNXI_FUNCTION_IRQ(0x6, 7)),  /* EINT7 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
> + SUNXI_FUNCTION_IRQ(0x6, 8)),  /* EINT8 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
> + SUNXI_FUNCTION_IRQ(0x6, 9)),  /* EINT9 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "aif3"),  /* SYNC */
> + SUNXI_FUNCTION(0x3, "i2s1"),  /* SYNC */
> + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> +         SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "aif3"),  /* BCLK */
> + SUNXI_FUNCTION(0x3, "i2s1"),  /* BCLK */
> + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "aif3"),  /* DOUT */
> + SUNXI_FUNCTION(0x3, "i2s1"),  /* DOUT */
> + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "aif3"),  /* DIN */
> + SUNXI_FUNCTION(0x3, "i2s1"),  /* DIN */
> + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
> +   /* Hole */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0"),  /* SCK */
> + SUNXI_FUNCTION_IRQ(0x6, 0)),  /* EINT0 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0"),  /* SDA */
> + SUNXI_FUNCTION_IRQ(0x6, 1)),  /* EINT1 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1"),  /* SCK */
> + SUNXI_FUNCTION_IRQ(0x6, 2)),  /* EINT2 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1"),  /* SDA */
> + SUNXI_FUNCTION_IRQ(0x6, 3)),  /* EINT3 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> + SUNXI_FUNCTION_IRQ(0x6, 4)),  /* EINT4 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> + SUNXI_FUNCTION_IRQ(0x6, 5)),  /* EINT5 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> + SUNXI_FUNCTION_IRQ(0x6, 6)),  /* EINT6 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> + SUNXI_FUNCTION_IRQ(0x6, 7)),  /* EINT7 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "owa"),   /* OUT */
> + SUNXI_FUNCTION_IRQ(0x6, 8)),  /* EINT8 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION_IRQ(0x6, 9)),  /* EINT9 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mic"),   /* CLK */
> + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
> +   SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mic"),   /* DATA */
> + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
> +};
> +
> +static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
> +   .pins = a64_pins,
> +   .npins = ARRAY_SIZE(a64_pins),
> +   .irq_banks = 1,
> +};
> +
> +static int a64_pinctrl_probe(struct platform_device *pdev)
> +{
> +   return sunxi_pinctrl_init(pdev,
> + &a64_pinctrl_data);
> +}
> +
> +static const struct of_device_id a64_pinctrl_match[] = {
> +   { .compatible = "allwinner,a64-pinctrl", },
> +   {}
> +};
> +MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
> +
> +static struct platform_driver a64_pinctrl_driver = {
> +   .probe  = a64_pinctrl_probe,
> +   .driver = {
> +   .name   = "a64-pinctrl",
> +   .of_match_table = a64_pinctrl_match,
> +   },
> +};
> +module_platform_driver(a64_pinctrl_driver);
> +
> +MODULE_AUTHOR("Andre Przywara ");
> +MODULE_DESCRIPTION("Allwinner A64 pinctrl driver");
> +MODULE_LICENSE("GPL");

I've verified that all the bit configurations are correct as per A64
user manual.

Regards,
Vishnu Patekar
> --
> 1.8.4
>
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Re: [linux-sunxi] Re: [PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi

[Vishnu Patekar]

Hello Wens,

On Tue, Dec 22, 2015 at 11:12 AM, Chen-Yu Tsai  wrote:
> On Sat, Dec 19, 2015 at 5:41 AM, Maxime Ripard
>  wrote:
>> Hi,
>>
>> On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote:
>>> Allwinner A83T is new octa-core cortex-a7 SOC.
>>> This adds the basic dtsi, the clocks differs from
>>> earlier sun8i SOCs.
>>>
>>> Signed-off-by: Vishnu Patekar 
>>> ---
>>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 206 
>>> ++
>>>  1 file changed, 206 insertions(+)
>>>  create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
>>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> new file mode 100644
>>> index 000..e577c64
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> @@ -0,0 +1,206 @@
>>> +/*
>>> + * Copyright 2015 Vishnu Patekar
>>> + *
>>> + * Vishnu Patekar 
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + *  a) This file is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of the
>>> + * License, or (at your option) any later version.
>>> + *
>>> + * This file is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + *  b) Permission is hereby granted, free of charge, to any person
>>> + * obtaining a copy of this software and associated documentation
>>> + * files (the "Software"), to deal in the Software without
>>> + * restriction, including without limitation the rights to use,
>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>> + * sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following
>>> + * conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> + * included in all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> +
>>> + */
>>> +
>>> +#include "skeleton.dtsi"
>>> +
>>> +#include 
>>> +
>>> +#include 
>>> +
>>> +/ {
>>> + interrupt-parent = <&gic>;
>>> +
>>> + chosen {
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu@0 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> + reg = <0>;
>>> + };
>>> +
>>> + cpu@1 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> + reg = <1>;
>>> + };
>>> +
>>> + cpu@2 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> +  

[linux-sunxi] Re: [PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi

[Vishnu Patekar]

Hello Maxime,


On Sat, Dec 19, 2015 at 5:41 AM, Maxime Ripard
 wrote:
> Hi,
>
> On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote:
>> Allwinner A83T is new octa-core cortex-a7 SOC.
>> This adds the basic dtsi, the clocks differs from
>> earlier sun8i SOCs.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 206 
>> ++
>>  1 file changed, 206 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> new file mode 100644
>> index 000..e577c64
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -0,0 +1,206 @@
>> +/*
>> + * Copyright 2015 Vishnu Patekar
>> + *
>> + * Vishnu Patekar 
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> +
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +
>> +#include 
>> +
>> +#include 
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>
> A \n here please
>
>> + cpu@100 {
>> + compatible = "arm,cortex-a7";
>> + device_type = 

[linux-sunxi] [PATCH v3 0/3] Add basic support for Allwinner A83T SOC

[Vishnu Patekar]

This patch series adds very basic support for Allwinner A83T SOC.
Clock, peripherals, smp support will be added later.

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.

Note: A83T pincontroller patch is already applied by Linus, so not added in this
patch.

changes from v2->v3
1. removed "Not Supported" for A83T in sunxi/README
2. removed un-unsed nodes from dtsi.
3. corrected GIC_SPI number for PH_EINT in dtsi.
4. removed address at soc node which was un-necessary.
5. corrected reg<> addresses for cpu nodes.
6. changed cpu mask to 8 in gic and archtimer node.


changes from v1->v2:
1. used UART0 header with PB9, PB10 pins.
2. removed unnecessary includes and comments from dtsi.
3. arranged nodes in alphabatical order.
4. arrnaged compatible in alphabatical order.
5. changed cpu nodes to use cpu@100 -cpu@-103.
6. changed dts filename.

Vishnu Patekar (3):
  ARM: sunxi: Introduce Allwinner for A83T support
  ARM: dts: sun8i: Add Allwinner A83T dtsi
  ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner

 Documentation/arm/sunxi/README |   1 -
 Documentation/devicetree/bindings/arm/sunxi.txt|   1 +
 arch/arm/boot/dts/Makefile |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  64 +++
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 206 +
 arch/arm/mach-sunxi/sunxi.c|   1 +
 drivers/clk/sunxi/clk-sunxi.c  |   6 +
 7 files changed, 279 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
 create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi

-- 
1.9.1

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[linux-sunxi] [PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi

[Vishnu Patekar]

Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 206 ++
 1 file changed, 206 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
new file mode 100644
index 000..e577c64
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ *
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+
+ */
+
+#include "skeleton.dtsi"
+
+#include 
+
+#include 
+
+/ {
+   interrupt-parent = <&gic>;
+
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   cpu@100 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x100>;
+   };
+
+   cpu@101 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x101>;
+   };
+   cpu@102 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x102>;
+   };
+
+   cpu@103 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0x103>;
+   };
+   };
+
+   memory {
+   reg = <0x4000 0x8000>;
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   clocks {
+   #address-cells = <1>;
+ 

[linux-sunxi] [PATCH v3 3/3] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner

[Vishnu Patekar]

H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.

A83T patches are tested on this board.
It has UART, ethernet, USB, HDMI, etc ports on it.

For FEL mode it needs USB A-A(Male) cable. I used uart0 which
is multiplexed to microsd pins PF2 and PF4.

Enabled UART0 Header(PB9, PB10 pins).

Signed-off-by: Vishnu Patekar 
---
 arch/arm/boot/dts/Makefile |  1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 64 ++
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cc7309b..0f81c58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -662,6 +662,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
+   sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
new file mode 100644
index 000..342e1d3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+   model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
+   compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&uart0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&uart0_pins_b>;
+   status = "okay";
+};
-- 
1.9.1

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[linux-sunxi] [PATCH v3 1/3] ARM: sunxi: Introduce Allwinner for A83T support

[Vishnu Patekar]

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.

Signed-off-by: Vishnu Patekar 
---
 Documentation/arm/sunxi/README  | 1 -
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c | 1 +
 drivers/clk/sunxi/clk-sunxi.c   | 6 ++
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 430d279..e5a115f 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -72,6 +72,5 @@ SunXi family
 
 * Octa ARM Cortex-A7 based SoCs
   - Allwinner A83T
-+ Not Supported
 + Datasheet
   http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index bb9b0faa..7e79fcc 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -11,5 +11,6 @@ using one of the following compatible strings:
   allwinner,sun7i-a20
   allwinner,sun8i-a23
   allwinner,sun8i-a33
+  allwinner,sun8i-a83t
   allwinner,sun8i-h3
   allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index c2be98f..3c15619 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -69,6 +69,7 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
+   "allwinner,sun8i-a83t",
"allwinner,sun8i-h3",
NULL,
 };
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 5ba2188..0d45253 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1219,6 +1219,12 @@ CLK_OF_DECLARE(sun8i_a23_clk_init, 
"allwinner,sun8i-a23", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
 
+static void __init sun8i_a83t_init_clocks(struct device_node *node)
+{
+   sunxi_init_clocks(NULL, 0);
+}
+CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t", 
sun8i_a83t_init_clocks);
+
 static void __init sun9i_init_clocks(struct device_node *node)
 {
sunxi_init_clocks(NULL, 0);
-- 
1.9.1

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[linux-sunxi] Re: [PATCH v2 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi

[Vishnu Patekar]

Hello Maxime,
Sorry for delayed response.

On Mon, Oct 26, 2015 at 4:20 AM, Maxime Ripard
 wrote:
> Hi,
>
> On Fri, Oct 23, 2015 at 07:46:16AM +0800, Vishnu Patekar wrote:
>> + memory {
>> + reg = <0x4000 0x8000>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + interrupts = > IRQ_TYPE_LEVEL_LOW)>,
>> +  > IRQ_TYPE_LEVEL_LOW)>,
>> +  > IRQ_TYPE_LEVEL_LOW)>,
>> +  > IRQ_TYPE_LEVEL_LOW)>;
>
> Shouldn't the number of CPUs be 8?
Yes, It should be 8, also need to change in gic node to 8 CPUs.
No, smp support till now, still I'll change it in next patch version.
>
>> + clock-frequency = <2400>;
>> + arm,cpu-registers-not-fw-configured;
>> + };
>
> Is there some u-boot support for this SoC yet?
recently, I've posted the v2 of u-boot patch.
>
> If so, both the memory node and the clock-frequency and
> arm,cpu-registers-not-fw-configured properties are useless (and
> harmful for the latter).
Correct, As, timer support is added in u-boot, I'll remove these two.
>
>> + soc@01c0 {
>
> Please remove the address. It's both wrong and useless.
>
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + gic: interrupt-controller@01c81000 {
>> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> + reg = <0x01c81000 0x1000>,
>> +   <0x01c82000 0x1000>,
>> +   <0x01c84000 0x2000>,
>> +   <0x01c86000 0x2000>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,sun8i-a83t-pinctrl";
>> + interrupts = ,
>> + ,
>> + ;
>
> Please align these lines with the first one, like you did for the
> GIC's reg for example.
Okie.
>
>> + reg = <0x01c20800 0x400>;
>> + clocks = <&osc24M>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #gpio-cells = <3>;
>> +
>> + i2c0_pins_a: i2c0@0 {
>> + allwinner,pins = "PH0", "PH1";
>> + allwinner,function = "i2c0";
>> + allwinner,drive = ;
>> + allwinner,pull = ;
>> + };
>> +
>> + i2c1_pins_a: i2c1@0 {
>> + allwinner,pins = "PH2", "PH3";
>> + allwinner,function = "i2c1";
>> + allwinner,drive = ;
>> + allwinner,pull = ;
>> + };
>> +
>> + i2c2_pins_a: i2c2@0 {
>> + allwinner,pins = "PH4", "PH5";
>> + allwinner,function = "i2c2";
>> + allwinner,drive = ;
>> + allwinner,pull = ;
>> + };
>> +
>> + mmc0_pins_a: mmc0@0 {
>> + allwinner,pins = "PF0", "PF1", "PF2",
>> +  "PF3", "PF4", "PF5";
>> + allwinner,function = "mmc0";
>> + allwinner,drive = ;
>> + allwinner,pull = ;
>> + };
>> +
>> + mmc1_pins_a: mmc1@0 {
>> + allwinner,pins = "PG0", "PG1", "PG2",
>> +  "PG3", "PG4", "PG5";
>> +   

[linux-sunxi] Re: [PATCH v2 1/3] ARM: sunxi: Introduce Allwinner for A83T support

[Vishnu Patekar]

Hello,
Sorry for delayed response.

On Fri, Oct 23, 2015 at 9:37 AM, Chen-Yu Tsai  wrote:
> On Fri, Oct 23, 2015 at 7:46 AM, Vishnu Patekar
>  wrote:
>> Allwinner A83T is octa-core cortex-a7 based SoC.
>> It's clock control unit and prcm, pinmux are different from previous sun8i
>> series.
>> Its processor cores are arragned in two clusters 4 cores each,
>> similar to A80.
>>
>> Signed-off-by: Vishnu Patekar 
>
> Could you also update Documentation/arm/sunxi/README, so it says A83T
> is supported?
I'll update and send next version.
>
> Otherwise,
>
> Acked-by: Chen-Yu Tsai 

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Re: [linux-sunxi] Re: [PATCH sunxi-tools 2/2] fel: Enable MMU on Allwinner-H3

[Vishnu Patekar]

Hello,

On Thu, Nov 12, 2015 at 7:03 PM, Julian Calaby 
wrote:

> Hi Stefan,
>
> On Thu, Nov 12, 2015 at 12:20 AM, Stefan Monnier
>  wrote:
> >> When the CPU clock speed is set to 480 MHz by the U-Boot SPL,
> >^^^
> > You mean MBUS?
> >
> >> the performance improvement for 'sunxi-fel write' transfers
> >> to DRAM is ~95 KB/s -> ~510 KB/s.
> >
> >> When the CPU clock speed is set to 1008 MHz by the U-Boot SPL,
> >> the performance improvement for 'sunxi-fel write' transfers
> >> to DRAM is ~180 KB/s -> ~510 KB/s.
> >
> > I don't understand the relation between the above 2 improvements.
> > What change causes the speed to go from 95KB/s to 180KB/s?
>
> My interpretation of this was that before this change, the transfer
> speed was somehow limited by the clock speed. With the MMU enabled, it
> appears that the clock speed is no-longer the limiting factor.
>
> (I'm _guessing_ that the transfer has to bounce through the CPU and
> this was slow without the MMU for some reason. I'm also guessing that
> enabling the MMU has moved the bottleneck elsewhere - possibly the USB
> hardware.)
>

On A83T board, after enabling MMU, sunxi-fel write speed is similar 510KB/s
(peripheral clock is at  600MHz).

If I increase the PLL6(peripheral clock), performance is improving.

after changing the PLL6 to 1200MHz, transfer speed to DDR3 is : 920.2 KB/s

Though, it is mentioned in datasheet that it's value should be 600.
However, allwinner u-boot code make it to 1200MHz.



>
> Thanks,
>
> --
> Julian Calaby
>
> Email: julian.cal...@gmail.com
> Profile: http://www.google.com/profiles/julian.calaby/
>
> --
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>

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