[linux-sunxi] [PATCH RFC 1/6] net: rfkill: gpio: fix gpio name buffer size off by 1
snprintf should be passed the complete size of the buffer, including the space for '\0'. The previous code resulted in the *_reset and *_shutdown strings being truncated. Signed-off-by: Chen-Yu Tsai w...@csie.org --- net/rfkill/rfkill-gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c index bd2a5b9..97ec12a 100644 --- a/net/rfkill/rfkill-gpio.c +++ b/net/rfkill/rfkill-gpio.c @@ -117,8 +117,8 @@ static int rfkill_gpio_probe(struct platform_device *pdev) if (!rfkill-shutdown_name) return -ENOMEM; - snprintf(rfkill-reset_name, len + 6 , %s_reset, rfkill-name); - snprintf(rfkill-shutdown_name, len + 9, %s_shutdown, rfkill-name); + snprintf(rfkill-reset_name, len + 7 , %s_reset, rfkill-name); + snprintf(rfkill-shutdown_name, len + 10, %s_shutdown, rfkill-name); rfkill-clk = devm_clk_get(pdev-dev, clk_name); -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH RFC 4/6] net: rfkill: gpio: add device tree support
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/rfkill/rfkill-gpio.txt | 26 ++
net/rfkill/rfkill-gpio.c | 23 +++
2 files changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
diff --git a/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
new file mode 100644
index 000..8a07ea4
--- /dev/null
+++ b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
@@ -0,0 +1,26 @@
+GPIO controlled RFKILL devices
+
+Required properties:
+- compatible : Must be rfkill-gpio.
+- rfkill-name : Name of RFKILL device
+- rfkill-type : Type of RFKILL device: 1 for WiFi, 2 for BlueTooth
+- NAME_shutdown-gpios : GPIO phandle to shutdown control
+ (phandle must be the second)
+- NAME_reset-gpios : GPIO phandle to reset control
+
+NAME must match the rfkill-name property. NAME_shutdown-gpios or
+NAME_reset-gpios, or both, must be defined.
+
+Optional properties:
+- clocks : phandle to clock to enable/disable
+
+Example:
+
+ rfkill_bt: rfkill@0 {
+ compatible = rfkill-gpio;
+ rfkill-name = bluetooth;
+ rfkill-type = 2;
+ bluetooth_shutdown-gpios = 0, pio 7 18 0;
+ bluetooth_reset-gpios = pio 7 24 0;
+ clocks = clk_out_a;
+ };
diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c
index 3084fa3..48381a8 100644
--- a/net/rfkill/rfkill-gpio.c
+++ b/net/rfkill/rfkill-gpio.c
@@ -26,6 +26,7 @@
#include linux/slab.h
#include linux/acpi.h
#include linux/gpio/consumer.h
+#include linux/of_gpio.h
#include linux/rfkill-gpio.h
@@ -83,6 +84,18 @@ static int rfkill_gpio_acpi_probe(struct device *dev,
return 0;
}
+static int rfkill_gpio_dt_probe(struct device *dev,
+ struct rfkill_gpio_data *rfkill)
+{
+ struct device_node * np = dev-of_node;
+
+ rfkill-name = np-name;
+ of_property_read_string(np, rfkill-name, rfkill-name);
+ of_property_read_u32(np, rfkill-type, rfkill-type);
+
+ return 0;
+}
+
static int rfkill_gpio_probe(struct platform_device *pdev)
{
struct rfkill_gpio_platform_data *pdata = pdev-dev.platform_data;
@@ -100,6 +113,10 @@ static int rfkill_gpio_probe(struct platform_device *pdev)
ret = rfkill_gpio_acpi_probe(pdev-dev, rfkill);
if (ret)
return ret;
+ } else if (pdev-dev.of_node) {
+ ret = rfkill_gpio_dt_probe(pdev-dev, rfkill);
+ if (ret)
+ return ret;
} else if (pdata) {
clk_name = pdata-power_clk_name;
rfkill-name = pdata-name;
@@ -189,6 +206,11 @@ static const struct acpi_device_id rfkill_acpi_match[] = {
{ },
};
+static const struct of_device_id rfkill_of_match[] = {
+ { .compatible = rfkill-gpio, },
+ {},
+};
+
static struct platform_driver rfkill_gpio_driver = {
.probe = rfkill_gpio_probe,
.remove = rfkill_gpio_remove,
@@ -196,6 +218,7 @@ static struct platform_driver rfkill_gpio_driver = {
.name = rfkill_gpio,
.owner = THIS_MODULE,
.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
+ .of_match_table = of_match_ptr(rfkill_of_match),
},
};
--
1.8.5.2
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[linux-sunxi] [PATCH RFC 6/6] ARM: sun7i: cubietruck: enable bluetooth module
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The
Bluetooth part is a BCM20710 device connected to UART2 in the
A20 SoC.
The IC also requires a 32.768 KHz low power clock input for
proper auto-detection of the main clock, and power enable and
wake signals via GPIO.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 37 ++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index c8b3ea9..f172a8f 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -78,6 +78,20 @@
allwinner,drive = 0;
allwinner,pull = 2;
};
+
+ bt_pwr_pin: bt_pwr_pin@0 {
+ allwinner,pins = PH18;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ bt_wake_pin: bt_wake_pin@0 {
+ allwinner,pins = PH24;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
uart0: serial@01c28000 {
@@ -86,6 +100,12 @@
status = okay;
};
+ uart2: serial@01c28800 {
+ pinctrl-names = default;
+ pinctrl-0 = uart2_pins_a;
+ status = okay;
+ };
+
gmac: ethernet@01c5 {
pinctrl-names = default;
pinctrl-0 = gmac_pins_rgmii;
@@ -157,4 +177,21 @@
gpio = pio 7 3 0;
};
};
+
+ rfkill-switches {
+ compatible = simple-bus;
+ pinctrl-names = default;
+
+ rfkill_bt {
+ compatible = rfkill-gpio;
+ pinctrl-names = default;
+ pinctrl-0 = bt_pwr_pin, clk_out_a_pins;
+ rfkill-name = bt;
+ rfkill-type = 2;
+ bt_shutdown-gpios = 0, pio 7 18 0; /* PH18 */
+ bt_reset-gpios = pio 7 24 0; /* PH24 */
+ clocks = clk_out_a;
+ clock-frequency = 32768;
+ };
+ };
};
--
1.8.5.2
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[linux-sunxi] [PATCH RFC 2/6] net: rfkill: gpio: use clk_prepare_enable/clk_disable_unprepare
rfkill-gpio calls clk_enable() without first calling clk_prepare(),
resulting in a warning and no effect. Switch to clk_prepare_enable()
and clk_disable_unprepare.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
net/rfkill/rfkill-gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c
index 97ec12a..c7081b7 100644
--- a/net/rfkill/rfkill-gpio.c
+++ b/net/rfkill/rfkill-gpio.c
@@ -51,10 +51,10 @@ static int rfkill_gpio_set_power(void *data, bool blocked)
gpiod_set_value(rfkill-shutdown_gpio, 0);
gpiod_set_value(rfkill-reset_gpio, 0);
if (!IS_ERR(rfkill-clk) rfkill-clk_enabled)
- clk_disable(rfkill-clk);
+ clk_disable_unprepare(rfkill-clk);
} else {
if (!IS_ERR(rfkill-clk) !rfkill-clk_enabled)
- clk_enable(rfkill-clk);
+ clk_prepare_enable(rfkill-clk);
gpiod_set_value(rfkill-reset_gpio, 1);
gpiod_set_value(rfkill-shutdown_gpio, 1);
}
--
1.8.5.2
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[linux-sunxi] [PATCH net-next v3 6/8] net: stmmac: Deprecate snps,phy-addr and auto-detect PHY address
The snps,phy-addr device tree property is non-standard, and should be removed in favor of proper phy node support. Remove it from the binding documents and warn if the property is still used. Most PHYs respond to address 0, but a few don't, so auto-detect PHY address by default, to make up for the lack of explicit address selection. Signed-off-by: Chen-Yu Tsai w...@csie.org --- Documentation/devicetree/bindings/net/stmmac.txt | 1 - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 9 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt index d132513..aefb639 100644 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt @@ -12,7 +12,6 @@ Required properties: property - phy-mode: String, operation mode of the PHY interface. Supported values are: mii, rmii, gmii, rgmii. -- snps,phy-addrphy address to connect to. - snps,reset-gpio gpio number for phy reset. - snps,reset-active-low boolean flag to indicate if phy reset is active low. - snps,reset-delays-us is triplet of delays diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 634260e..82110f1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -50,7 +50,14 @@ static int stmmac_probe_config_dt(struct platform_device *pdev, if (plat-bus_id 0) plat-bus_id = 0; - of_property_read_u32(np, snps,phy-addr, plat-phy_addr); + /* Default to phy auto-detection */ + plat-phy_addr = -1; + + /* snps,phy-addr is not a standard property. Mark it as deprecated +* and warn of its use. Remove this when phy node support is added. +*/ + if (of_property_read_u32(np, snps,phy-addr, plat-phy_addr) == 0) + dev_warn(pdev-dev, snps,phy-addr property is deprecated\n); plat-mdio_bus_data = devm_kzalloc(pdev-dev, sizeof(struct stmmac_mdio_bus_data), -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH net-next v3 8/8] net: stmmac: sunxi platform extensions for GMAC in Allwinner A20 SoC's
The Allwinner A20 has an ethernet controller that seems to be
an early version of Synopsys DesignWare MAC 10/100/1000 Universal,
which is supported by the stmmac driver.
Allwinner's GMAC requires setting additional registers in the SoC's
clock control unit.
The exact version of the DWMAC IP that Allwinner uses is unknown,
thus the exact feature set is unknown.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../bindings/net/allwinner,sun7i-a20-gmac.txt | 27
drivers/net/ethernet/stmicro/stmmac/Kconfig| 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 141 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +
6 files changed, 186 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
new file mode 100644
index 000..ea4d752
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
@@ -0,0 +1,27 @@
+* Allwinner GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+ - compatible: Should be allwinner,sun7i-a20-gmac
+ - clocks: Should contain the GMAC main clock, and tx clock
+ The tx clock type should be allwinner,sun7i-a20-gmac-clk
+ - clock-names: Should contain the clock names stmmaceth,
+ and allwinner_gmac_tx
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Examples:
+
+ gmac: ethernet@01c5 {
+ compatible = allwinner,sun7i-a20-gmac;
+ reg = 0x01c5 0x1,
+ 0x01c20164 0x4;
+ interrupts = 0 85 1;
+ interrupt-names = macirq;
+ clocks = ahb_gates 49, gmac_tx;
+ clock-names = stmmaceth, allwinner_gmac_tx;
+ phy-mode = mii;
+ };
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index b59d1ef..e2f202e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -26,6 +26,17 @@ config STMMAC_PLATFORM
If unsure, say N.
+config DWMAC_SUNXI
+ bool Allwinner GMAC support
+ depends on STMMAC_PLATFORM ARCH_SUNXI
+ default y
+ ---help---
+ Support for Allwinner A20/A31 GMAC ethernet controllers.
+
+ This selects Allwinner SoC glue layer support for the
+ stmmac device driver. This driver is used for A20/A31
+ GMACethernet controller.
+
config STMMAC_PCI
bool STMMAC PCI bus support
depends on STMMAC_ETH PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile
b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 356a9dd..ecadece 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
+stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
new file mode 100644
index 000..dc4f8ae
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
@@ -0,0 +1,141 @@
+/**
+ * dwmac-sunxi.c - Allwinner sunxi DWMAC specific glue layer
+ *
+ * Copyright (C) 2013 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/stmmac.h
+#include linux/clk.h
+#include linux/phy.h
+#include linux/of_net.h
+#include linux/regulator/consumer.h
+
+struct sunxi_priv_data {
+ int interface;
+ int clk_enabled;
+ struct clk *tx_clk;
+ struct regulator *regulator;
+};
+
+static void *sun7i_gmac_setup(struct platform_device *pdev)
+{
+ struct sunxi_priv_data *gmac;
+ struct device *dev = pdev-dev;
+
+ gmac
[linux-sunxi] [PATCH net-next v3 1/8] net: stmmac: Enable stmmac main clock when probing hardware
The stmmac driver does not enable the main clock during the probe phase.
If the clock was not enabled by the boot loader or was disabled by the
kernel, hardware features and the MDIO bus would not be probed properly.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 26 +++
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index cddcf76..0d2c4cb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1680,8 +1680,6 @@ static int stmmac_open(struct net_device *dev)
struct stmmac_priv *priv = netdev_priv(dev);
int ret;
- clk_prepare_enable(priv-stmmac_clk);
-
stmmac_check_ether_addr(priv);
if (priv-pcs != STMMAC_PCS_RGMII priv-pcs != STMMAC_PCS_TBI
@@ -1819,7 +1817,6 @@ static int stmmac_release(struct net_device *dev)
#ifdef CONFIG_STMMAC_DEBUG_FS
stmmac_exit_fs();
#endif
- clk_disable_unprepare(priv-stmmac_clk);
stmmac_release_ptp(priv);
@@ -2727,10 +2724,18 @@ struct stmmac_priv *stmmac_dvr_probe(struct device
*device,
if ((phyaddr = 0) (phyaddr = 31))
priv-plat-phy_addr = phyaddr;
+ priv-stmmac_clk = devm_clk_get(priv-device, STMMAC_RESOURCE_NAME);
+ if (IS_ERR(priv-stmmac_clk)) {
+ dev_warn(priv-device, %s: warning: cannot get CSR clock\n,
+__func__);
+ goto error_clk_get;
+ }
+ clk_prepare_enable(priv-stmmac_clk);
+
/* Init MAC and get the capabilities */
ret = stmmac_hw_init(priv);
if (ret)
- goto error_free_netdev;
+ goto error_hw_init;
ndev-netdev_ops = stmmac_netdev_ops;
@@ -2768,12 +2773,6 @@ struct stmmac_priv *stmmac_dvr_probe(struct device
*device,
goto error_netdev_register;
}
- priv-stmmac_clk = clk_get(priv-device, STMMAC_RESOURCE_NAME);
- if (IS_ERR(priv-stmmac_clk)) {
- pr_warn(%s: warning: cannot get CSR clock\n, __func__);
- goto error_clk_get;
- }
-
/* If a specific clk_csr value is passed from the platform
* this means that the CSR Clock Range selection cannot be
* changed at run-time and it is fixed. Viceversa the driver'll try to
@@ -2801,12 +2800,12 @@ struct stmmac_priv *stmmac_dvr_probe(struct device
*device,
return priv;
error_mdio_register:
- clk_put(priv-stmmac_clk);
-error_clk_get:
unregister_netdev(ndev);
error_netdev_register:
netif_napi_del(priv-napi);
-error_free_netdev:
+error_hw_init:
+ clk_disable_unprepare(priv-stmmac_clk);
+error_clk_get:
free_netdev(ndev);
return NULL;
@@ -2833,6 +2832,7 @@ int stmmac_dvr_remove(struct net_device *ndev)
stmmac_mdio_unregister(ndev);
netif_carrier_off(ndev);
unregister_netdev(ndev);
+ clk_disable_unprepare(priv-stmmac_clk);
free_netdev(ndev);
return 0;
--
1.8.5.2
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[linux-sunxi] [PATCH net-next v3 2/8] net: stmmac: Add support for optional reset control
The DWMAC has a reset assert line, which is used on some SoCs. Add an
optional reset control to stmmac driver core.
To support reset control deferred probing, this patch changes the driver
probe function to return the actual error, instead of just -EINVAL.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/net/stmmac.txt | 3 +++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 19 ++-
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 4 ++--
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++--
6 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
b/Documentation/devicetree/bindings/net/stmmac.txt
index eba0e5e..d132513 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -30,6 +30,9 @@ Required properties:
Optional properties:
- mac-address: 6 bytes, mac address
+- resets: Should contain a phandle to the STMMAC reset signal, if any
+- reset-names: Should contain the reset signal name stmmaceth, if a
+ reset phandle is given
Examples:
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 6e52c0f..b59d1ef 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -5,6 +5,7 @@ config STMMAC_ETH
select PHYLIB
select CRC32
select PTP_1588_CLOCK
+ select RESET_CONTROLLER
---help---
This is the driver for the Ethernet IPs are built around a
Synopsys IP Core and only tested on the STMicroelectronics
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index 73709e9..c1c141f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -32,6 +32,7 @@
#include linux/pci.h
#include common.h
#include linux/ptp_clock_kernel.h
+#include linux/reset.h
struct stmmac_priv {
/* Frequently used values are kept adjacent for cache effect */
@@ -91,6 +92,7 @@ struct stmmac_priv {
int wolopts;
int wol_irq;
struct clk *stmmac_clk;
+ struct reset_control *stmmac_rst;
int clk_csr;
struct timer_list eee_ctrl_timer;
int lpi_irq;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 0d2c4cb..0c5c120 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -51,6 +51,7 @@
#include linux/net_tstamp.h
#include stmmac_ptp.h
#include stmmac.h
+#include linux/reset.h
#define STMMAC_ALIGN(x)L1_CACHE_ALIGN(x)
#define JUMBO_LEN 9000
@@ -2728,10 +2729,24 @@ struct stmmac_priv *stmmac_dvr_probe(struct device
*device,
if (IS_ERR(priv-stmmac_clk)) {
dev_warn(priv-device, %s: warning: cannot get CSR clock\n,
__func__);
+ ret = PTR_ERR(priv-stmmac_clk);
goto error_clk_get;
}
clk_prepare_enable(priv-stmmac_clk);
+ priv-stmmac_rst = devm_reset_control_get(priv-device,
+ STMMAC_RESOURCE_NAME);
+ if (IS_ERR(priv-stmmac_rst)) {
+ if (PTR_ERR(priv-stmmac_rst) == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ goto error_hw_init;
+ }
+ dev_info(priv-device, no reset control found\n);
+ priv-stmmac_rst = NULL;
+ }
+ if (priv-stmmac_rst)
+ reset_control_deassert(priv-stmmac_rst);
+
/* Init MAC and get the capabilities */
ret = stmmac_hw_init(priv);
if (ret)
@@ -2808,7 +2823,7 @@ error_hw_init:
error_clk_get:
free_netdev(ndev);
- return NULL;
+ return ERR_PTR(ret);
}
/**
@@ -2832,6 +2847,8 @@ int stmmac_dvr_remove(struct net_device *ndev)
stmmac_mdio_unregister(ndev);
netif_carrier_off(ndev);
unregister_netdev(ndev);
+ if (priv-stmmac_rst)
+ reset_control_assert(priv-stmmac_rst);
clk_disable_unprepare(priv-stmmac_clk);
free_netdev(ndev);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
index 37ba2e0..2916089 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
@@ -100,9 +100,9 @@ static int stmmac_pci_probe(struct pci_dev *pdev,
stmmac_default_data();
priv = stmmac_dvr_probe((pdev-dev), plat_dat, addr);
- if (!priv) {
+ if (IS_ERR(priv)) {
pr_err(%s: main driver probe failed
[linux-sunxi] [PATCH net-next v3 0/8] net: stmmac: Add Allwinner A20 GMAC ethernet
Hi, This is v3 of the Allwinner A20 GMAC glue layer for stmmac. I have split the series into stmmac driver changes for net-next, and clock and DT patches for their respective trees. The Allwinner A20 SoC integrates an early version of dwmac IP from Synopsys. On top of that is a hardware glue layer. This layer needs to be configured before the dwmac can be used. Part of the glue layer is a clock mux, which controls the source and direction of the TX clock used by GMAC. The glue layer is implemented with existing feature flags and callbacks found in stmmac driver core. A new stmmac_of_data structure, which is a subset of the original platform data, has been added to tie these values with compatible strings. The purpose of this is to avoid future glue layers assuming they can pass other data or directly modify values used by the driver core. This is found in patch #7. The callbacks have also been extended to pass board specific data. This is found in patch #3. This version of dwmac IP requires store and forward DMA mode. The relevant device tree property was documented, but not implemented. Patch #6 adds this to stmmac platform driver. Changes since v2: * Dropped non CONFIG_RESET_CONTROLLER routines, make stmmac select CONFIG_RESET_CONTROLLER * Split out Deprecate snps,phy-addr and auto-detect PHY address from Use driver data and callbacks tied with compatible strings * Added comments on how sunxi glue layer uses GMAC clock * Rebased onto net-next * Corrected typo in blackfin commit message Changes since v1: * Added optional reset control to stmmac driver core * Added non CONFIG_RESET_CONROLLER routines for the above change * Extended callback API, as discussed with Srinivas * Used new stmmac_of_data to pass features and callbacks, instead of platform data, as discussed * Seperated clock module glue layer into clock driver Cheers, ChenYu Chen-Yu Tsai (8): net: stmmac: Enable stmmac main clock when probing hardware net: stmmac: Add support for optional reset control net: stmmac: Allocate and pass soc/board specific data to callbacks blackfin: Update stmmac callback signatures net: stmmac: Honor DT parameter to force DMA store and forward mode net: stmmac: Deprecate snps,phy-addr and auto-detect PHY address net: stmmac: Use driver data and callbacks tied with compatible strings net: stmmac: sunxi platform extensions for GMAC in Allwinner A20 SoC's .../bindings/net/allwinner,sun7i-a20-gmac.txt | 27 Documentation/devicetree/bindings/net/stmmac.txt | 4 +- Documentation/networking/stmmac.txt| 12 +- arch/blackfin/mach-bf609/boards/ezkit.c| 2 +- drivers/net/ethernet/stmicro/stmmac/Kconfig| 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 141 + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 5 + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 45 +-- drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 4 +- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 80 +--- include/linux/stmmac.h | 24 +++- 12 files changed, 316 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH net-next v3 3/8] net: stmmac: Allocate and pass soc/board specific data to callbacks
The current .init and .exit callbacks requires access to driver
private data structures. This is not a good seperation and abstraction.
Instead, we add a new .setup callback for allocating private data, and
pass the returned pointer to the other callbacks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/networking/stmmac.txt | 12
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 18 ++
include/linux/stmmac.h| 6 --
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/Documentation/networking/stmmac.txt
b/Documentation/networking/stmmac.txt
index cdd916d..2090895 100644
--- a/Documentation/networking/stmmac.txt
+++ b/Documentation/networking/stmmac.txt
@@ -127,8 +127,9 @@ struct plat_stmmacenet_data {
int riwt_off;
void (*fix_mac_speed)(void *priv, unsigned int speed);
void (*bus_setup)(void __iomem *ioaddr);
- int (*init)(struct platform_device *pdev);
- void (*exit)(struct platform_device *pdev);
+ void *(*setup)(struct platform_device *pdev);
+ int (*init)(struct platform_device *pdev, void *priv);
+ void (*exit)(struct platform_device *pdev, void *priv);
void *custom_cfg;
void *custom_data;
void *bsp_priv;
@@ -169,10 +170,13 @@ Where:
o bus_setup: perform HW setup of the bus. For example, on some ST platforms
this field is used to configure the AMBA bridge to generate more
efficient STBus traffic.
- o init/exit: callbacks used for calling a custom initialization;
+ o setup/init/exit: callbacks used for calling a custom initialization;
this is sometime necessary on some platforms (e.g. ST boxes)
where the HW needs to have set some PIO lines or system cfg
-registers.
+registers. setup should return a pointer to private data,
+which will be stored in bsp_priv, and then passed to init and
+exit callbacks. init/exit callbacks should not use or modify
+platform data.
o custom_cfg/custom_data: this is a custom configuration that can be passed
while initializing the resources.
o bsp_priv: another private pointer.
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index cc6b89a7..704a5e0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -144,9 +144,16 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
}
}
+ /* Custom setup (if needed) */
+ if (plat_dat-setup) {
+ plat_dat-bsp_priv = plat_dat-setup(pdev);
+ if (IS_ERR(plat_dat-bsp_priv))
+ return PTR_ERR(plat_dat-bsp_priv);
+ }
+
/* Custom initialisation (if needed)*/
if (plat_dat-init) {
- ret = plat_dat-init(pdev);
+ ret = plat_dat-init(pdev, plat_dat-bsp_priv);
if (unlikely(ret))
return ret;
}
@@ -203,7 +210,10 @@ static int stmmac_pltfr_remove(struct platform_device
*pdev)
int ret = stmmac_dvr_remove(ndev);
if (priv-plat-exit)
- priv-plat-exit(pdev);
+ priv-plat-exit(pdev, priv-plat-bsp_priv);
+
+ if (priv-plat-free)
+ priv-plat-free(pdev, priv-plat-bsp_priv);
return ret;
}
@@ -218,7 +228,7 @@ static int stmmac_pltfr_suspend(struct device *dev)
ret = stmmac_suspend(ndev);
if (priv-plat-exit)
- priv-plat-exit(pdev);
+ priv-plat-exit(pdev, priv-plat-bsp_priv);
return ret;
}
@@ -230,7 +240,7 @@ static int stmmac_pltfr_resume(struct device *dev)
struct platform_device *pdev = to_platform_device(dev);
if (priv-plat-init)
- priv-plat-init(pdev);
+ priv-plat-init(pdev, priv-plat-bsp_priv);
return stmmac_resume(ndev);
}
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 33ace71..0a5a7ac 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -113,8 +113,10 @@ struct plat_stmmacenet_data {
int max_speed;
void (*fix_mac_speed)(void *priv, unsigned int speed);
void (*bus_setup)(void __iomem *ioaddr);
- int (*init)(struct platform_device *pdev);
- void (*exit)(struct platform_device *pdev);
+ void *(*setup)(struct platform_device *pdev);
+ void (*free)(struct platform_device *pdev, void *priv);
+ int (*init)(struct platform_device *pdev, void *priv);
+ void (*exit)(struct platform_device *pdev, void *priv);
void *custom_cfg;
void *custom_data;
void *bsp_priv;
--
1.8.5.2
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[linux-sunxi] Re: [PATCH RFC 4/6] net: rfkill: gpio: add device tree support
On Sat, Jan 18, 2014 at 7:11 AM, Linus Walleij linus.wall...@linaro.org wrote: On Fri, Jan 17, 2014 at 6:43 PM, Chen-Yu Tsai w...@csie.org wrote: On Sat, Jan 18, 2014 at 12:47 AM, Arnd Bergmann a...@arndb.de wrote: +- NAME_shutdown-gpios : GPIO phandle to shutdown control + (phandle must be the second) +- NAME_reset-gpios : GPIO phandle to reset control + +NAME must match the rfkill-name property. NAME_shutdown-gpios or +NAME_reset-gpios, or both, must be defined. + I don't understand this part. Why do you include the name in the gpios property, rather than just hardcoding the property strings to shutdown-gpios and reset-gpios? This quirk is a result of how gpiod_get_index implements device tree lookup. Why can't it just have a single property gpios, where the first element is the reset GPIO and the second is the shutdown GPIO? rfkill-gpio does this: gpio = devm_gpiod_get_index(pdev-dev, rfkill-reset_name, 0); gpio = devm_gpiod_get_index(pdev-dev, rfkill-shutdown_name, 1); The passed con ID name parameter is only there for the device tree case it seems. (ACPI ignores it.) So what about you just don't pass it at all and patch it to do like this instead: gpio = devm_gpiod_get_index(pdev-dev, NULL, 0); gpio = devm_gpiod_get_index(pdev-dev, NULL, 1); I'd like that. It's much cleaner. Heikki, are you OK with this change? I think this is actually necessary if the ACPI and DT unification pipe dream shall limp forward, we cannot have arguments passed that have a semantic effect on DT but not on ACPI... Drivers that are supposed to use both ACPI and DT will always have to pass NULL as con ID. If con_id is given, it is prepended to gpios as the property string. con_id is also used as the label passed to gpiod_request, which is then shown in /sys/kernel/debug/gpio. If your problem is really what turns up in debugfs, then we need to figure out a way to label gpios outside of the *gpiod_get* calls. Let's add a gpiod_set_label call. Currently there's a desc_set_label in gpiolib, which is static inlined. We can either rename and promote it to non-static, or add a new wrapping function. The string passed in *gpiod_get* is a connection ID not a proper name for the GPIO. I see. Perhaps we should not pass this to gpiod_request as the label, or add a comment stating consumers can use the new gpiod_set_label call to change it. Cheers, ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] [PATCH v5 13/14] ARM: sun4i: dts: Add ahci / sata support
Hi,
On Thu, Jan 23, 2014 at 3:04 AM, Hans de Goede hdego...@redhat.com wrote:
From: Oliver Schinagl oli...@schinagl.nl
This patch adds sunxi sata support to A10 boards that have such a connector.
Some boards also feature a regulator via a GPIO and support for this is also
added.
Signed-off-by: Olliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 4
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 +
arch/arm/boot/dts/sun4i-a10.dtsi | 8 +++
arch/arm/boot/dts/sunxi-ahci-reg.dtsi | 38
++
4 files changed, 56 insertions(+)
create mode 100644 arch/arm/boot/dts/sunxi-ahci-reg.dtsi
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index aef8207..3fb7305 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -48,6 +48,10 @@
status = okay;
};
+ ahci: sata@01c18000 {
+ status = okay;
+ };
+
pinctrl@01c20800 {
mmc0_cd_pin_a1000: mmc0_cd_pin@0 {
allwinner,pins = PH1;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index f50fb2b..6ae1110 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -12,6 +12,7 @@
/dts-v1/;
/include/ sun4i-a10.dtsi
+/include/ sunxi-ahci-reg.dtsi
/ {
model = Cubietech Cubieboard;
@@ -51,6 +52,11 @@
status = okay;
};
+ ahci: sata@01c18000 {
+ target-supply = reg_ahci_5v;
+ status = okay;
+ };
+
pinctrl@01c20800 {
mmc0_cd_pin_cubieboard: mmc0_cd_pin@0 {
allwinner,pins = PH1;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi
b/arch/arm/boot/dts/sun4i-a10.dtsi
index 4736dd2..198dcda 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -331,6 +331,14 @@
status = disabled;
};
+ ahci: sata@01c18000 {
+ compatible = allwinner,sun4i-a10-ahci;
+ reg = 0x01c18000 0x1000;
+ interrupts = 56;
+ clocks = pll6 0, ahb_gates 25;
+ status = disabled;
+ };
+
Consider adding
pinctrl-names = default;
in the ahci node to suppress default pin state not found warnings.
Same goes for sun7i-a20.dtsi.
intc: interrupt-controller@01c20400 {
compatible = allwinner,sun4i-ic;
reg = 0x01c20400 0x400;
diff --git a/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
new file mode 100644
index 000..955b197
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
@@ -0,0 +1,38 @@
+/*
+ * sunxi boards sata target power supply common code
+ *
+ * Copyright 2014 - Hans de Goede hdego...@redhat.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc@01c0 {
This block needs to be under
pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = PB8;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
+ };
+
+ regulators {
+ compatible = simple-bus;
+ pinctrl-names = default;
+
+ reg_ahci_5v: ahci-5v {
+ compatible = regulator-fixed;
+ regulator-name = ahci-5v;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ pinctrl-0 = ahci_pwr_pin_a;
+ gpio = pio 1 8 0;
+ enable-active-high;
+ };
+ };
+};
--
1.8.5.3
Great work! Thanks!
ChenYu
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Re: [linux-sunxi] Firmware for Bluetooth (and wifi)
Hi, On Mon, Jan 27, 2014 at 12:34 AM, Hans de Goede hdego...@redhat.com wrote: Hi, On 01/24/2014 04:38 AM, Chen-Yu Tsai wrote: snip Quick update, I've just tested: https://github.com/wens/linux/commits/wip/sunxi-next-wifi About this, I would like to move WiFi power control to a regulator, and controlled by sunxi-mci via vmmc-supply (not supported ATM) Actually the sunxi-mci.c driver already has support for an optional regulator called vmmc. I like this idea, I've done a version of the dt patch using a regulator instead of rfkill here: https://github.com/jwrdegoede/linux-sunxi/commit/8d200113b573549cdcdc1b2d5a5a1cad15cfbe07 This works as advertised and IMHO is the better solution. I have a version in another branch I haven't pushed. I had it using an always-on regulator. I can adjust it to use vmmc. BTW, I'd like to do a patch for sunxi-mci to use the DT parsing code in mmc core. We should re-use code if possible, wouldn't you agree? About the oob interrupt stuff not working, AFAIK you should set a pinctrl function (not input, but a function like mmc is a function) on the pin in question for it to work as external interrupt, I believe you're not doing so in your dts. The pinctrl driver seems to set the function when the interrupt is enabled. Unfortunately we don't have any documentation/examples on how to use them. I will look into that later. Hmm, but you also have a pinctrl entry in the dts setting it up as gpio-input, maybe that conflicts ? I made a version with pinctrl entry setup as irq, got an interrupt, but then the whole thing hung. Looks like pinctrl irqchip was not properly handling chained interrupts. I have done a simple fix, and I hope to test it tomorrow. Then I'll do some more testing with different configurations and hopefully write some documents. Cheers, ChenYu Off topic but, is the USB PHY driver final? I believe there's an issue in the probe error checking code: https://github.com/wens/linux/commit/349b8903e8909455d6f91fbad046fddc2d9326a5 No, I need to do another revision and send that upstream, I hope to do so one of the coming days. Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
Re: [linux-sunxi] Firmware for Bluetooth (and wifi)
On Mon, Jan 27, 2014 at 3:31 PM, Hans de Goede hdego...@redhat.com wrote: Hi, On 01/26/2014 05:58 PM, Chen-Yu Tsai wrote: Hi, On Mon, Jan 27, 2014 at 12:34 AM, Hans de Goede hdego...@redhat.com wrote: Hi, On 01/24/2014 04:38 AM, Chen-Yu Tsai wrote: snip Quick update, I've just tested: https://github.com/wens/linux/commits/wip/sunxi-next-wifi About this, I would like to move WiFi power control to a regulator, and controlled by sunxi-mci via vmmc-supply (not supported ATM) Actually the sunxi-mci.c driver already has support for an optional regulator called vmmc. I like this idea, I've done a version of the dt patch using a regulator instead of rfkill here: https://github.com/jwrdegoede/linux-sunxi/commit/8d200113b573549cdcdc1b2d5a5a1cad15cfbe07 This works as advertised and IMHO is the better solution. I have a version in another branch I haven't pushed. I had it using an always-on regulator. I can adjust it to use vmmc. BTW, I'd like to do a patch for sunxi-mci to use the DT parsing code in mmc core. We should re-use code if possible, wouldn't you agree? I would agree, except that mmc_regulator_get_supply makes vmmc mandatory, it will log and return an error when it is not there, and it will not set ocr_avail. Almost all Allwinnner boards don't have a separate vmmc, so making vmmc mandatory just leads to devicetree containing unnecessary fixed regulators for this. I suppose we could still reuse all the property parsing bits in mmc_of_parse(). This one handles the GPIOs, bus width and host capabilities. About the oob interrupt stuff not working, AFAIK you should set a pinctrl function (not input, but a function like mmc is a function) on the pin in question for it to work as external interrupt, I believe you're not doing so in your dts. The pinctrl driver seems to set the function when the interrupt is enabled. Unfortunately we don't have any documentation/examples on how to use them. I will look into that later. Hmm, but you also have a pinctrl entry in the dts setting it up as gpio-input, maybe that conflicts ? I made a version with pinctrl entry setup as irq, got an interrupt, but then the whole thing hung. Great, that sounds like progress to me :) I think it was a fluke. Now I'm not getting any interrupts. :( Anyway, I am resuming work on musb. I'll get back to this once 3.14-rc1 is out, and sunxi-devel is rebased. I can probably use OTG ID pin to test external interrupts. Cheers, ChenYu Looks like pinctrl irqchip was not properly handling chained interrupts. I have done a simple fix, and I hope to test it tomorrow. Then I'll do some more testing with different configurations and hopefully write some documents. Thanks for working on this. Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] Re: [PATCH v3 2/8] clk: sunxi: update clock-output-names dt binding documentation
Hi Maxime, On Fri, Jan 17, 2014 at 10:55 AM, Emilio López emi...@elopez.com.ar wrote: Hi, El 09/01/14 05:52, Chen-Yu Tsai escribió: clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples. Signed-off-by: Chen-Yu Tsai w...@csie.org --- Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++ 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 0c127cd..8a9147d 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -44,10 +44,18 @@ Required properties for all clocks: multiplexed clocks, the list order must match the hardware programming order. - #clock-cells : from common clock binding; shall be set to 0 except for - allwinner,*-gates-clk where it shall be set to 1 + allwinner,*-gates-clk, allwinner,sun4i-pll5-clk and + allwinner,sun4i-pll6-clk where it shall be set to 1 -Additionally, allwinner,*-gates-clk clocks require: -- clock-output-names : the corresponding gate names that the clock controls +Additionally, most clocks require clock-output-names: +- allwinner,*-gates-clk : the corresponding gate names that the clock controls +- allwinner,sun4i-pll5-clk : pll5_ddr, pll5_mbus +- allwinner,sun4i-pll6-clk : pll6_sata, pll6_other +- allwinner,sun4i-cpu-clk, allwinner,sun4i-axi-clk, + allwinner,sun4i-ahb-clk, allwinner,sun4i-ahb-clk, + allwinner,sun4i-apb1-mux-clk, allwinner,sun4i-apb1-clk + do not need clock-output-names +- all others clocks : the corresponding module name of that clock As we discussed on IRC, I wonder if such verbosity is actually needed. Maybe we should dictate that all clocks must list their corresponding outputs on clock-output-names (with it being the module name if it only has one output). Maxime, could we get your input on this? Thanks ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH v4 1/8] clk: sunxi: add clock-output-names dt property support
sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk@X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property. Signed-off-by: Chen-Yu Tsai w...@csie.org Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Acked-by: Mike Turquette mturque...@linaro.org --- drivers/clk/sunxi/clk-sunxi.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..0ed9794 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -51,6 +51,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node) if (!gate) goto err_free_fixed; + of_property_read_string(node, clock-output-names, clk_name); + /* set up gate and fixed rate properties */ gate-reg = of_iomap(node, 0); gate-bit_idx = SUNXI_OSC24M_GATE; @@ -601,6 +603,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node, (parents[i] = of_clk_get_parent_name(node, i)) != NULL) i++; + of_property_read_string(node, clock-output-names, clk_name); + clk = clk_register_mux(NULL, clk_name, parents, i, CLK_SET_RATE_NO_REPARENT, reg, data-shift, SUNXI_MUX_GATE_WIDTH, @@ -660,6 +664,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node, clk_parent = of_clk_get_parent_name(node, 0); + of_property_read_string(node, clock-output-names, clk_name); + clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg, data-shift, data-width, data-pow ? CLK_DIVIDER_POWER_OF_TWO : 0, -- 1.9.rc1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH v4 2/8] clk: sunxi: update clock-output-names dt binding documentation
clock-output-names is now required for most of sunxi clock nodes, to
provide the name of the corresponding clock. Add the new requirements,
exceptions, as well as examples.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 32 ++-
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index c2cb762..0cf679b 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -44,10 +44,11 @@ Required properties for all clocks:
multiplexed clocks, the list order must match the hardware
programming order.
- #clock-cells : from common clock binding; shall be set to 0 except for
- allwinner,*-gates-clk where it shall be set to 1
-
-Additionally, allwinner,*-gates-clk clocks require:
-- clock-output-names : the corresponding gate names that the clock controls
+ allwinner,*-gates-clk, allwinner,sun4i-pll5-clk and
+ allwinner,sun4i-pll6-clk where it shall be set to 1
+- clock-output-names : shall be the corresponding names of the outputs.
+ If the clock module only has one output, the name shall be the
+ module name.
Clock consumers should specify the desired clocks they use with a
clocks phandle cell. Consumers that are using a gated clock should
@@ -56,18 +57,28 @@ offset of the bit controlling this particular gate in the
register.
For example:
-osc24M: osc24M@01c20050 {
+osc24M: clk@01c20050 {
#clock-cells = 0;
compatible = allwinner,sun4i-osc-clk;
reg = 0x01c20050 0x4;
clocks = osc24M_fixed;
+ clock-output-names = osc24M;
};
-pll1: pll1@01c2 {
+pll1: clk@01c2 {
#clock-cells = 0;
compatible = allwinner,sun4i-pll1-clk;
reg = 0x01c2 0x4;
clocks = osc24M;
+ clock-output-names = pll1;
+};
+
+pll5: clk@01c20020 {
+ #clock-cells = 1;
+ compatible = allwinner,sun4i-pll5-clk;
+ reg = 0x01c20020 0x4;
+ clocks = osc24M;
+ clock-output-names = pll5_ddr, pll5_other;
};
cpu: cpu@01c20054 {
@@ -75,4 +86,13 @@ cpu: cpu@01c20054 {
compatible = allwinner,sun4i-cpu-clk;
reg = 0x01c20054 0x4;
clocks = osc32k, osc24M, pll1;
+ clock-output-names = cpu;
+};
+
+mmc0_clk: clk@01c20088 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-mod0-clk;
+ reg = 0x01c20088 0x4;
+ clocks = osc24M, pll6 1, pll5 1;
+ clock-output-names = mmc0;
};
--
1.9.rc1
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[linux-sunxi] [PATCH v4 6/8] ARM: dts: sun5i: rename clock node names to clk@N
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 30 --
arch/arm/boot/dts/sun5i-a13.dtsi | 30 --
2 files changed, 40 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi
b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ea16054..0efad0e 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -47,34 +47,38 @@
clock-frequency = 0;
};
- osc24M: osc24M@01c20050 {
+ osc24M: clk@01c20050 {
#clock-cells = 0;
compatible = allwinner,sun4i-osc-clk;
reg = 0x01c20050 0x4;
clock-frequency = 2400;
+ clock-output-names = osc24M;
};
- osc32k: osc32k {
+ osc32k: clk@0 {
#clock-cells = 0;
compatible = fixed-clock;
clock-frequency = 32768;
+ clock-output-names = osc32k;
};
- pll1: pll1@01c2 {
+ pll1: clk@01c2 {
#clock-cells = 0;
compatible = allwinner,sun4i-pll1-clk;
reg = 0x01c2 0x4;
clocks = osc24M;
+ clock-output-names = pll1;
};
- pll4: pll4@01c20018 {
+ pll4: clk@01c20018 {
#clock-cells = 0;
compatible = allwinner,sun4i-pll1-clk;
reg = 0x01c20018 0x4;
clocks = osc24M;
+ clock-output-names = pll4;
};
- pll5: pll5@01c20020 {
+ pll5: clk@01c20020 {
#clock-cells = 1;
compatible = allwinner,sun4i-pll5-clk;
reg = 0x01c20020 0x4;
@@ -82,7 +86,7 @@
clock-output-names = pll5_ddr, pll5_other;
};
- pll6: pll6@01c20028 {
+ pll6: clk@01c20028 {
#clock-cells = 1;
compatible = allwinner,sun4i-pll6-clk;
reg = 0x01c20028 0x4;
@@ -96,6 +100,7 @@
compatible = allwinner,sun4i-cpu-clk;
reg = 0x01c20054 0x4;
clocks = osc32k, osc24M, pll1, dummy;
+ clock-output-names = cpu;
};
axi: axi@01c20054 {
@@ -103,9 +108,10 @@
compatible = allwinner,sun4i-axi-clk;
reg = 0x01c20054 0x4;
clocks = cpu;
+ clock-output-names = axi;
};
- axi_gates: axi_gates@01c2005c {
+ axi_gates: clk@01c2005c {
#clock-cells = 1;
compatible = allwinner,sun4i-axi-gates-clk;
reg = 0x01c2005c 0x4;
@@ -118,9 +124,10 @@
compatible = allwinner,sun4i-ahb-clk;
reg = 0x01c20054 0x4;
clocks = axi;
+ clock-output-names = ahb;
};
- ahb_gates: ahb_gates@01c20060 {
+ ahb_gates: clk@01c20060 {
#clock-cells = 1;
compatible = allwinner,sun5i-a10s-ahb-gates-clk;
reg = 0x01c20060 0x8;
@@ -139,9 +146,10 @@
compatible = allwinner,sun4i-apb0-clk;
reg = 0x01c20054 0x4;
clocks = ahb;
+ clock-output-names = apb0;
};
- apb0_gates: apb0_gates@01c20068 {
+ apb0_gates: clk@01c20068 {
#clock-cells = 1;
compatible = allwinner,sun5i-a10s-apb0-gates-clk;
reg = 0x01c20068 0x4;
@@ -155,6 +163,7 @@
compatible = allwinner,sun4i-apb1-mux-clk;
reg = 0x01c20058 0x4;
clocks = osc24M, pll6 1, osc32k;
+ clock-output-names = apb1_mux;
};
apb1: apb1@01c20058 {
@@ -162,9 +171,10 @@
compatible = allwinner,sun4i-apb1-clk;
reg = 0x01c20058 0x4;
clocks = apb1_mux;
+ clock-output-names = apb1;
};
- apb1_gates: apb1_gates@01c2006c {
+ apb1_gates: clk@01c2006c
[linux-sunxi] [PATCH v4 7/8] ARM: dts: sun6i: rename clock node names to clk@N
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 5256ad9..dbc2d29 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -60,17 +60,19 @@
clock-frequency = 2400;
};
- osc32k: osc32k {
+ osc32k: clk@0 {
#clock-cells = 0;
compatible = fixed-clock;
clock-frequency = 32768;
+ clock-output-names = osc32k;
};
- pll1: pll1@01c2 {
+ pll1: clk@01c2 {
#clock-cells = 0;
compatible = allwinner,sun6i-a31-pll1-clk;
reg = 0x01c2 0x4;
clocks = osc24M;
+ clock-output-names = pll1;
};
/*
@@ -97,6 +99,7 @@
* Allwinner.
*/
clocks = osc32k, osc24M, pll1, pll1;
+ clock-output-names = cpu;
};
axi: axi@01c20050 {
@@ -104,6 +107,7 @@
compatible = allwinner,sun4i-axi-clk;
reg = 0x01c20050 0x4;
clocks = cpu;
+ clock-output-names = axi;
};
ahb1_mux: ahb1_mux@01c20054 {
@@ -111,6 +115,7 @@
compatible = allwinner,sun6i-a31-ahb1-mux-clk;
reg = 0x01c20054 0x4;
clocks = osc32k, osc24M, axi, pll6;
+ clock-output-names = ahb1_mux;
};
ahb1: ahb1@01c20054 {
@@ -118,9 +123,10 @@
compatible = allwinner,sun4i-ahb-clk;
reg = 0x01c20054 0x4;
clocks = ahb1_mux;
+ clock-output-names = ahb1;
};
- ahb1_gates: ahb1_gates@01c20060 {
+ ahb1_gates: clk@01c20060 {
#clock-cells = 1;
compatible = allwinner,sun6i-a31-ahb1-gates-clk;
reg = 0x01c20060 0x8;
@@ -146,9 +152,10 @@
compatible = allwinner,sun4i-apb0-clk;
reg = 0x01c20054 0x4;
clocks = ahb1;
+ clock-output-names = apb1;
};
- apb1_gates: apb1_gates@01c20060 {
+ apb1_gates: clk@01c20068 {
#clock-cells = 1;
compatible = allwinner,sun6i-a31-apb1-gates-clk;
reg = 0x01c20068 0x4;
@@ -163,6 +170,7 @@
compatible = allwinner,sun4i-apb1-mux-clk;
reg = 0x01c20058 0x4;
clocks = osc32k, osc24M, pll6, pll6;
+ clock-output-names = apb2_mux;
};
apb2: apb2@01c20058 {
@@ -170,9 +178,10 @@
compatible = allwinner,sun6i-a31-apb2-div-clk;
reg = 0x01c20058 0x4;
clocks = apb2_mux;
+ clock-output-names = apb2;
};
- apb2_gates: apb2_gates@01c2006c {
+ apb2_gates: clk@01c2006c {
#clock-cells = 1;
compatible = allwinner,sun6i-a31-apb2-gates-clk;
reg = 0x01c2006c 0x4;
--
1.9.rc1
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[linux-sunxi] [PATCH v3 0/8] Add Allwinner A20 GMAC ethernet support
Hi, This is the remaining part of v3 of the Allwinner A20 GMAC glue layer for stmmac. The stmmac driver changes have been merged through net-next. The remaining bits are clock and DT patches. The patches should be applied over my clock renaming patches. The Allwinner A20 SoC integrates an early version of dwmac IP from Synopsys. On top of that is a hardware glue layer. This layer needs to be configured before the dwmac can be used. Part of the glue layer is a clock mux, which controls the source and direction of the TX clock used by GMAC. Changes since v2: * Added more comments on GMAC clock driver * Drop CLK_SET_PARENT_GATE in GMAC clock driver * Use macro for max clock parents * Line wrapping Changes since v1: * Added optional reset control to stmmac driver core * Added non CONFIG_RESET_CONROLLER routines for the above change * Extended callback API, as discussed with Srinivas * Used new stmmac_of_data to pass features and callbacks, instead of platform data, as discussed * Seperated clock module glue layer into clock driver Cheers, ChenYu Chen-Yu Tsai (8): clk: sunxi: Add Allwinner A20/A31 GMAC clock unit ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI ARM: dts: sun7i: Add pin muxing options for the GMAC ARM: dts: sun7i: cubietruck: Enable the GMAC ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC ARM: dts: sun7i: olinuxino-micro: Enable GMAC instead of EMAC ARM: dts: sun7i: Add ethernet alias for GMAC Documentation/devicetree/bindings/clock/sunxi.txt | 26 +++ arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 arch/arm/boot/dts/sun7i-a20-cubietruck.dts| 12 arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 arch/arm/boot/dts/sun7i-a20.dtsi | 71 ++- drivers/clk/sunxi/clk-sunxi.c | 83 +++ 6 files changed, 215 insertions(+), 31 deletions(-) -- 1.9.rc1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH v3 3/8] ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index fc7f470..5fbac23 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -630,6 +630,21 @@
status = disabled;
};
+ gmac: ethernet@01c5 {
+ compatible = allwinner,sun7i-a20-gmac;
+ reg = 0x01c5 0x1;
+ interrupts = 0 85 4;
+ interrupt-names = macirq;
+ clocks = ahb_gates 49, gmac_tx_clk;
+ clock-names = stmmaceth, allwinner_gmac_tx;
+ snps,pbl = 2;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
hstimer@01c6 {
compatible = allwinner,sun7i-a20-hstimer;
reg = 0x01c6 0x1000;
--
1.9.rc1
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[linux-sunxi] [PATCH v3 2/8] ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 1595e9a..fc7f470 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -314,6 +314,34 @@
};
/*
+* The following two are dummy clocks, placeholders used
+* on gmac_tx clock. The actual frequency and availability
+* depends on the external PHY, operation mode and link
+* speed.
+*/
+ mii_phy_tx_clk: clk@2 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = mii_phy_tx;
+ };
+
+ gmac_int_tx_clk: clk@3 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 12500;
+ clock-output-names = gmac_int_tx;
+ };
+
+ gmac_tx_clk: clk@01c20164 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-gmac-clk;
+ reg = 0x01c20164 0x4;
+ clocks = mii_phy_tx_clk, gmac_int_tx_clk;
+ clock-output-names = gmac_tx;
+ };
+
+ /*
* Dummy clock used by output clocks
*/
osc24M_32k: clk@1 {
--
1.9.rc1
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[linux-sunxi] [PATCH v3 8/8] ARM: dts: sun7i: Add ethernet alias for GMAC
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0, as it is the only ethernet controller used.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 65fb8d0..c48fb11 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,7 @@
interrupt-parent = gic;
aliases {
- ethernet0 = emac;
+ ethernet0 = gmac;
};
cpus {
--
1.9.rc1
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[linux-sunxi] [PATCH v3 6/8] ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8..7bf4935 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -19,21 +19,6 @@
compatible = cubietech,cubieboard2, allwinner,sun7i-a20;
soc@01c0 {
- emac: ethernet@01c0b000 {
- pinctrl-names = default;
- pinctrl-0 = emac_pins_a;
- phy = phy1;
- status = okay;
- };
-
- mdio@01c0b080 {
- status = okay;
-
- phy1: ethernet-phy@1 {
- reg = 1;
- };
- };
-
pinctrl@01c20800 {
led_pins_cubieboard2: led_pins@0 {
allwinner,pins = PH20, PH21;
@@ -60,6 +45,18 @@
pinctrl-0 = i2c1_pins_a;
status = okay;
};
+
+ gmac: ethernet@01c5 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_mii_a;
+ phy = phy1;
+ phy-mode = mii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
};
leds {
--
1.9.rc1
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[linux-sunxi] [PATCH v3 7/8] ARM: dts: sun7i: olinuxino-micro: Enable GMAC instead of EMAC
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013..b02a796 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -19,21 +19,6 @@
compatible = olimex,a20-olinuxino-micro, allwinner,sun7i-a20;
soc@01c0 {
- emac: ethernet@01c0b000 {
- pinctrl-names = default;
- pinctrl-0 = emac_pins_a;
- phy = phy1;
- status = okay;
- };
-
- mdio@01c0b080 {
- status = okay;
-
- phy1: ethernet-phy@1 {
- reg = 1;
- };
- };
-
pinctrl@01c20800 {
led_pins_olinuxino: led_pins@0 {
allwinner,pins = PH2;
@@ -78,6 +63,18 @@
pinctrl-0 = i2c2_pins_a;
status = okay;
};
+
+ gmac: ethernet@01c5 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_mii_a;
+ phy = phy1;
+ phy-mode = mii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
};
leds {
--
1.9.rc1
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[linux-sunxi] Re: [PATCH v3 1/8] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
Hi,
On Tue, Feb 4, 2014 at 3:31 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Mon, Feb 03, 2014 at 11:32:19AM +0800, Chen-Yu Tsai wrote:
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 26 +++
drivers/clk/sunxi/clk-sunxi.c | 83
+++
2 files changed, 109 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0cf679b..f43b4c0 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -37,6 +37,7 @@ Required properties:
allwinner,sun6i-a31-apb2-gates-clk - for the APB2 gates on A31
allwinner,sun4i-mod0-clk - for the module 0 family of clocks
allwinner,sun7i-a20-out-clk - for the external output clocks
+ allwinner,sun7i-a20-gmac-clk - for the GMAC clock module on A20/A31
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@@ -50,6 +51,9 @@ Required properties for all clocks:
If the clock module only has one output, the name shall be the
module name.
+For allwinner,sun7i-a20-gmac-clk, the parent clocks shall be fixed rate
+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
+
Clock consumers should specify the desired clocks they use with a
clocks phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
@@ -96,3 +100,25 @@ mmc0_clk: clk@01c20088 {
clocks = osc24M, pll6 1, pll5 1;
clock-output-names = mmc0;
};
+
+mii_phy_tx_clk: clk@2 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = mii_phy_tx;
+};
+
+gmac_int_tx_clk: clk@3 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 12500;
+ clock-output-names = gmac_int_tx;
+};
+
+gmac_clk: clk@01c20164 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-gmac-clk;
+ reg = 0x01c20164 0x4;
+ clocks = mii_phy_tx_clk, gmac_int_tx_clk;
You should also document in which order you expect the parents to
be. Or it will probably be easier to just use clock-names here.
Is it not clear from the Required properties section above?
+ clock-output-names = gmac;
+};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 736fb60..0b361d2 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -379,6 +379,89 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32
parent_rate,
/**
+ * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
+ *
+ * This clock looks something like this
+ *
+ * MII TX clock from PHY -|____| to GMAC core
+ * GMAC Int. RGMII TX clk |___\__/__gate---| to PHY
+ * Ext. 125MHz RGMII TX clk --|__divider__/|
+ * ||
+ *
+ * The external 125 MHz reference is optional, i.e. GMAC can use its
+ * internal TX clock just fine. The A31 GMAC clock module does not have
+ * the divider controls for the external reference.
+ *
+ * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
+ * and its internal TX clock for GMII and RGMII modes. The GMAC driver
should
+ * select the appropriate source and gate/ungate the output to the PHY.
+ *
+ * Only the GMAC should use this clock. Altering the clock so that it
doesn't
+ * match the GMAC's operation parameters will result in the GMAC not being
+ * able to send traffic out. The GMAC driver should set the clock rate and
+ * enable/disable this clock to configure the required state. The clock
+ * driver then responds by auto-reparenting the clock.
+ */
+
+#define SUN7I_A20_GMAC_GPIT 2
+#define SUN7I_A20_GMAC_MASK 0x3
+#define SUN7I_A20_GMAC_MAX_PARENTS 2
+
+static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_mux *mux;
+ struct clk_gate *gate;
+ const char *clk_name = node-name;
+ const char *parents[SUN7I_A20_GMAC_MAX_PARENTS];
+ void *reg;
+ int i = 0;
+
+ /* allocate mux and gate clock structs */
+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
+ if (!mux)
+ return;
Newline.
+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ return;
+ }
+
+ reg = of_iomap(node, 0);
You should check for the return code here
[linux-sunxi] Re: [PATCH v3 8/8] ARM: dts: sun7i: Add ethernet alias for GMAC
On Tue, Feb 4, 2014 at 3:38 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Mon, Feb 03, 2014 at 11:32:26AM +0800, Chen-Yu Tsai wrote:
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0, as it is the only ethernet controller used.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
b/arch/arm/boot/dts/sun7i-a20.dtsi
index 65fb8d0..c48fb11 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,7 @@
interrupt-parent = gic;
aliases {
- ethernet0 = emac;
+ ethernet0 = gmac;
};
I'm not very fond of this patch.
People might rely on the fact that ethernet0 is actually the emac, and
are expecting u-boot to fill the ethaddr variable to the emac, and not
the gmac.
Since u-boot is totally able to deal with several ethernet addresses,
please add it as ethernet1.
Actually I think we should override this in the board dts.
The boards we currently support can only use emac or gmac,
and in our u-boot tree, they have been converted to using
gmac. If any future boards support both emac and gmac, we
can address the ordering then. And the ordering should
match u-boot.
What do you think?
Cheers
ChenYu
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Re: [linux-sunxi] [PATCH v2] ARM: sunxi: Add driver for sunxi usb phy
On Sat, Feb 8, 2014 at 12:33 AM, Hans de Goede hdego...@redhat.com wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need poking, which are per phy, but shared between the
ohci and ehci controllers, so these are also controlled from this new phy
driver.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 28 ++
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-sun4i-usb.c| 326
+
4 files changed, 366 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
create mode 100644 drivers/phy/phy-sun4i-usb.c
[...]
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
new file mode 100644
index 000..bd9cb7fa
--- /dev/null
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -0,0 +1,326 @@
+/*
+ * Allwinner sun4i USB phy driver
+ *
+ * Copyright (C) 2014 Hans de Goede hdego...@redhat.com
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ *
+ * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Sylwester Nawrocki s.nawro...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+
+#define REG_ISCR 0x00
+#define REG_PHYCTL 0x04
+#define REG_PHYBIST0x08
+#define REG_PHYTUNE0x0c
+
+#define SUNXI_AHB_ICHR8_EN BIT(10)
+#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
+#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
+#define SUNXI_ULPI_BYPASS_EN BIT(0)
+
+/* Common Control Bits for Both PHYs */
+#define PHY_PLL_BW 0x03
+#define PHY_RES45_CAL_EN 0x0c
+
+/* Private Control Bits for Each PHY */
+#define PHY_TX_AMPLITUDE_TUNE 0x20
+#define PHY_TX_SLEWRATE_TUNE 0x22
+#define PHY_VBUSVALID_TH_SEL 0x25
+#define PHY_PULLUP_RES_SEL 0x27
+#define PHY_OTG_FUNC_EN0x28
+#define PHY_VBUS_DET_EN0x29
+#define PHY_DISCON_TH_SEL 0x2a
+
+#define MAX_PHYS 3
+
+struct sun4i_usb_phy_data {
+ struct clk *clk;
+ void __iomem *base;
+ struct mutex mutex;
+ int num_phys;
+ u32 disc_thresh;
+ struct sun4i_usb_phy {
+ struct phy *phy;
+ void __iomem *pmu;
+ struct regulator *vbus;
+ struct reset_control *reset;
+ int index;
+ } phys[MAX_PHYS];
+};
+
+#define to_sun4i_usb_phy_data(phy) \
+ container_of((phy), struct sun4i_usb_phy_data, phys[(phy)-index])
+
+static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32
data,
+ int len)
+{
+ struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
+ u32 temp, usbc_bit = BIT(phy-index * 2);
+ int i;
+
+ mutex_lock(phy_data-mutex);
+
+ for (i = 0; i len; i++) {
+ temp = readl(phy_data-base + REG_PHYCTL);
+
+ /* clear the address portion */
+ temp = ~(0xff 8);
+
+ /* set the address */
+ temp |= ((addr + i) 8);
+ writel(temp, phy_data-base + REG_PHYCTL);
+
+ /* set the data bit and clear usbc bit*/
+ temp = readb(phy_data-base + REG_PHYCTL);
+ if (data 0x1)
+ temp |= BIT(7);
+ else
+ temp = ~BIT(7);
+ temp = ~usbc_bit;
+ writeb(temp, phy_data-base + REG_PHYCTL);
+
+ /* pulse usbc_bit */
+ temp = readb(phy_data-base + REG_PHYCTL);
+ temp |= usbc_bit;
+ writeb(temp, phy_data-base + REG_PHYCTL);
+
+ temp = readb(phy_data-base +
[linux-sunxi] [PATCH v4 4/8] ARM: dts: sun7i: Add pin muxing options for the GMAC
The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 8eb4d54..68c889c 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -484,6 +484,32 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = PA0, PA1, PA2,
+ PA3, PA4, PA5, PA6,
+ PA7, PA8, PA9, PA10,
+ PA11, PA12, PA13, PA14,
+ PA15, PA16;
+ allwinner,function = gmac;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = PA0, PA1, PA2,
+ PA3, PA4, PA5, PA6,
+ PA7, PA8, PA10,
+ PA11, PA12, PA13,
+ PA15, PA16;
+ allwinner,function = gmac;
+ /*
+* data lines in RGMII mode use DDR mode
+* and need a higher signal drive strength
+*/
+ allwinner,drive = 3;
+ allwinner,pull = 0;
+ };
};
timer@01c20c00 {
--
1.9.rc1
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[linux-sunxi] [PATCH v4 8/8] ARM: dts: sun7i: Add ethernet alias for GMAC
All Allwinner A20 boards we support can only use either EMAC or GMAC,
as they share the same pins. As we have switched all supported to
GMAC, we should alias GMAC (the active controller) as ethernet0,
so u-boot will insert the MAC address for the correct controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 68c889c..1b5fb88 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,7 @@
interrupt-parent = gic;
aliases {
- ethernet0 = emac;
+ ethernet0 = gmac;
serial0 = uart0;
serial1 = uart1;
serial2 = uart2;
--
1.9.rc1
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[linux-sunxi] [PATCH v4 5/8] ARM: dts: sun7i: cubietruck: Enable the GMAC
The CubieTruck uses the GMAC with an RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61..025ce52 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -51,6 +51,18 @@
pinctrl-0 = i2c2_pins_a;
status = okay;
};
+
+ gmac: ethernet@01c5 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_rgmii_a;
+ phy = phy1;
+ phy-mode = rgmii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
};
leds {
--
1.9.rc1
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[linux-sunxi] [PATCH v4 6/8] ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8..7bf4935 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -19,21 +19,6 @@
compatible = cubietech,cubieboard2, allwinner,sun7i-a20;
soc@01c0 {
- emac: ethernet@01c0b000 {
- pinctrl-names = default;
- pinctrl-0 = emac_pins_a;
- phy = phy1;
- status = okay;
- };
-
- mdio@01c0b080 {
- status = okay;
-
- phy1: ethernet-phy@1 {
- reg = 1;
- };
- };
-
pinctrl@01c20800 {
led_pins_cubieboard2: led_pins@0 {
allwinner,pins = PH20, PH21;
@@ -60,6 +45,18 @@
pinctrl-0 = i2c1_pins_a;
status = okay;
};
+
+ gmac: ethernet@01c5 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_mii_a;
+ phy = phy1;
+ phy-mode = mii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
};
leds {
--
1.9.rc1
--
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[linux-sunxi] [PATCH v4 7/8] ARM: dts: sun7i: a20-olinuxino-micro: Enable GMAC instead of EMAC
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013..b02a796 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -19,21 +19,6 @@
compatible = olimex,a20-olinuxino-micro, allwinner,sun7i-a20;
soc@01c0 {
- emac: ethernet@01c0b000 {
- pinctrl-names = default;
- pinctrl-0 = emac_pins_a;
- phy = phy1;
- status = okay;
- };
-
- mdio@01c0b080 {
- status = okay;
-
- phy1: ethernet-phy@1 {
- reg = 1;
- };
- };
-
pinctrl@01c20800 {
led_pins_olinuxino: led_pins@0 {
allwinner,pins = PH2;
@@ -78,6 +63,18 @@
pinctrl-0 = i2c2_pins_a;
status = okay;
};
+
+ gmac: ethernet@01c5 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_mii_a;
+ phy = phy1;
+ phy-mode = mii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
};
leds {
--
1.9.rc1
--
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[linux-sunxi] [PATCH v4 3/8] ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index dd567ea..8eb4d54 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -645,6 +645,21 @@
status = disabled;
};
+ gmac: ethernet@01c5 {
+ compatible = allwinner,sun7i-a20-gmac;
+ reg = 0x01c5 0x1;
+ interrupts = 0 85 4;
+ interrupt-names = macirq;
+ clocks = ahb_gates 49, gmac_tx_clk;
+ clock-names = stmmaceth, allwinner_gmac_tx;
+ snps,pbl = 2;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
hstimer@01c6 {
compatible = allwinner,sun7i-a20-hstimer;
reg = 0x01c6 0x1000;
--
1.9.rc1
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[linux-sunxi] [PATCH v4 0/8] Add Allwinner A20 GMAC ethernet support
Hi, This is the v4 of the remaining Allwinner A20 GMAC glue layer patches. The stmmac driver changes have been merged through net-next. The remaining bits are clock and DT patches. The patches should be applied over my clock renaming patches. The Allwinner A20 SoC integrates an early version of dwmac IP from Synopsys. On top of that is a hardware glue layer. This layer needs to be configured before the dwmac can be used. Part of the glue layer is a clock mux, which controls the source and direction of the TX clock used by GMAC. Changes since v3: * Rework error checking in GMAC clock driver * Clarify required parent clock order for GMAC clock in DT bindings * Rewrite commit log for ARM: dts: sun7i: Add ethernet alias for GMAC * Corrected a20-olinuxino-micro in commit message * Rewrite comments in sun7i dtsi to clarify purpose of dummy clocks * Rebase onto Maxime's sunxi-next branch Changes since v2: * Added more comments on GMAC clock driver * Drop CLK_SET_PARENT_GATE in GMAC clock driver * Use macro for max clock parents * Line wrapping Changes since v1: * Added optional reset control to stmmac driver core * Added non CONFIG_RESET_CONROLLER routines for the above change * Extended callback API, as discussed with Srinivas * Used new stmmac_of_data to pass features and callbacks, instead of platform data, as discussed * Seperated clock module glue layer into clock driver Cheers, ChenYu Chen-Yu Tsai (8): clk: sunxi: Add Allwinner A20/A31 GMAC clock unit ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI ARM: dts: sun7i: Add pin muxing options for the GMAC ARM: dts: sun7i: cubietruck: Enable the GMAC ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC ARM: dts: sun7i: a20-olinuxino-micro: Enable GMAC instead of EMAC ARM: dts: sun7i: Add ethernet alias for GMAC Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++ arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 +++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts| 12 +++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++ arch/arm/boot/dts/sun7i-a20.dtsi | 71 - drivers/clk/sunxi/clk-sunxi.c | 97 +++ 6 files changed, 233 insertions(+), 31 deletions(-) -- 1.9.rc1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH v4 1/8] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++
drivers/clk/sunxi/clk-sunxi.c | 97 +++
2 files changed, 127 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0cf679b..28421d2 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -37,6 +37,7 @@ Required properties:
allwinner,sun6i-a31-apb2-gates-clk - for the APB2 gates on A31
allwinner,sun4i-mod0-clk - for the module 0 family of clocks
allwinner,sun7i-a20-out-clk - for the external output clocks
+ allwinner,sun7i-a20-gmac-clk - for the GMAC clock module on A20/A31
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@@ -50,6 +51,9 @@ Required properties for all clocks:
If the clock module only has one output, the name shall be the
module name.
+For allwinner,sun7i-a20-gmac-clk, the parent clocks shall be fixed rate
+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
+
Clock consumers should specify the desired clocks they use with a
clocks phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
@@ -96,3 +100,29 @@ mmc0_clk: clk@01c20088 {
clocks = osc24M, pll6 1, pll5 1;
clock-output-names = mmc0;
};
+
+mii_phy_tx_clk: clk@2 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = mii_phy_tx;
+};
+
+gmac_int_tx_clk: clk@3 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 12500;
+ clock-output-names = gmac_int_tx;
+};
+
+gmac_clk: clk@01c20164 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-gmac-clk;
+ reg = 0x01c20164 0x4;
+ /*
+* The first clock must be fixed at 25MHz;
+* the second clock must be fixed at 125MHz
+*/
+ clocks = mii_phy_tx_clk, gmac_int_tx_clk;
+ clock-output-names = gmac;
+};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 736fb60..da1d5cc 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -379,6 +379,103 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32
parent_rate,
/**
+ * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
+ *
+ * This clock looks something like this
+ *
+ * MII TX clock from PHY -|____| to GMAC core
+ * GMAC Int. RGMII TX clk |___\__/__gate---| to PHY
+ * Ext. 125MHz RGMII TX clk --|__divider__/|
+ * ||
+ *
+ * The external 125 MHz reference is optional, i.e. GMAC can use its
+ * internal TX clock just fine. The A31 GMAC clock module does not have
+ * the divider controls for the external reference.
+ *
+ * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
+ * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
+ * select the appropriate source and gate/ungate the output to the PHY.
+ *
+ * Only the GMAC should use this clock. Altering the clock so that it doesn't
+ * match the GMAC's operation parameters will result in the GMAC not being
+ * able to send traffic out. The GMAC driver should set the clock rate and
+ * enable/disable this clock to configure the required state. The clock
+ * driver then responds by auto-reparenting the clock.
+ */
+
+#define SUN7I_A20_GMAC_GPIT2
+#define SUN7I_A20_GMAC_MASK0x3
+#define SUN7I_A20_GMAC_PARENTS 2
+
+static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ struct clk_mux *mux;
+ struct clk_gate *gate;
+ const char *clk_name = node-name;
+ const char *parents[SUN7I_A20_GMAC_PARENTS];
+ void *reg;
+ int i = 0;
+
+ if (of_property_read_string(node, clock-output-names, clk_name))
+ return;
+
+ /* allocate mux and gate clock structs */
+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
+ if (!mux)
+ return;
+
+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+ if (!gate)
+ goto free_mux;
+
+ /* gmac clock requires exactly 2 parents */
+ parents[0] = of_clk_get_parent_name(node, 0);
+ parents[1] = of_clk_get_parent_name(node, 1);
+ if (!parents[0] || !parents[1])
+ goto free_gate;
+
+ reg = of_iomap(node, 0);
+ if (!reg)
+ goto free_gate
[linux-sunxi] [PATCH v5] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi,
This is v5 of the Allwinner A20 GMAC clock patch. Hans noted a
compiler warning: unused variable in the previous version.
The DT bits remain the same, and Maxime has already taken them.
The Allwinner A20 SoC integrates an early version of dwmac
IP from Synopsys. On top of that is a hardware glue layer.
This layer needs to be configured before the dwmac can be
used.
Part of the glue layer is a clock mux, which controls the
source and direction of the TX clock used by GMAC.
Changes since v4:
* Removed unused variable in GMAC clock driver left over from v3
Changes since v3:
* Rework error checking in GMAC clock driver
* Clarify required parent clock order for GMAC clock in DT bindings
* Rewrite commit log for ARM: dts: sun7i: Add ethernet alias for GMAC
* Corrected a20-olinuxino-micro in commit message
* Rewrite comments in sun7i dtsi to clarify purpose of dummy clocks
* Rebase onto Maxime's sunxi-next branch
Changes since v2:
* Added more comments on GMAC clock driver
* Drop CLK_SET_PARENT_GATE in GMAC clock driver
* Use macro for max clock parents
* Line wrapping
Changes since v1:
* Added optional reset control to stmmac driver core
* Added non CONFIG_RESET_CONROLLER routines for the above change
* Extended callback API, as discussed with Srinivas
* Used new stmmac_of_data to pass features and callbacks,
instead of platform data, as discussed
* Seperated clock module glue layer into clock driver
Cheers
ChenYu
---
Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++
drivers/clk/sunxi/clk-sunxi.c | 96 +++
2 files changed, 126 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0cf679b..28421d2 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -37,6 +37,7 @@ Required properties:
allwinner,sun6i-a31-apb2-gates-clk - for the APB2 gates on A31
allwinner,sun4i-mod0-clk - for the module 0 family of clocks
allwinner,sun7i-a20-out-clk - for the external output clocks
+ allwinner,sun7i-a20-gmac-clk - for the GMAC clock module on A20/A31
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@@ -50,6 +51,9 @@ Required properties for all clocks:
If the clock module only has one output, the name shall be the
module name.
+For allwinner,sun7i-a20-gmac-clk, the parent clocks shall be fixed rate
+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
+
Clock consumers should specify the desired clocks they use with a
clocks phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
@@ -96,3 +100,29 @@ mmc0_clk: clk@01c20088 {
clocks = osc24M, pll6 1, pll5 1;
clock-output-names = mmc0;
};
+
+mii_phy_tx_clk: clk@2 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = mii_phy_tx;
+};
+
+gmac_int_tx_clk: clk@3 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 12500;
+ clock-output-names = gmac_int_tx;
+};
+
+gmac_clk: clk@01c20164 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-gmac-clk;
+ reg = 0x01c20164 0x4;
+ /*
+* The first clock must be fixed at 25MHz;
+* the second clock must be fixed at 125MHz
+*/
+ clocks = mii_phy_tx_clk, gmac_int_tx_clk;
+ clock-output-names = gmac;
+};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 736fb60..54a5d55 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -379,6 +379,102 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32
parent_rate,
/**
+ * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
+ *
+ * This clock looks something like this
+ *
+ * MII TX clock from PHY -|____| to GMAC core
+ * GMAC Int. RGMII TX clk |___\__/__gate---| to PHY
+ * Ext. 125MHz RGMII TX clk --|__divider__/|
+ * ||
+ *
+ * The external 125 MHz reference is optional, i.e. GMAC can use its
+ * internal TX clock just fine. The A31 GMAC clock module does not have
+ * the divider controls for the external reference.
+ *
+ * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
+ * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
+ * select the appropriate source
Re: [linux-sunxi] [PATCH v5 4/8] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Hi,
On Wed, Feb 12, 2014 at 3:33 AM, David Lanzendörfer
david.lanzendoer...@o2s.ch wrote:
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzendörfer, additional
fixes and cleanups by Hans de Goede.
It uses dma in bus-master mode using a built-in designware idmac controller,
which is identical to the one found in the mmc-dw hosts.
The rest of the host is not identical to mmc-dw.
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/mmc/host/Kconfig |7
drivers/mmc/host/Makefile|2
drivers/mmc/host/sunxi-mmc.c | 872
++
drivers/mmc/host/sunxi-mmc.h | 239
4 files changed, 1120 insertions(+)
create mode 100644 drivers/mmc/host/sunxi-mmc.c
create mode 100644 drivers/mmc/host/sunxi-mmc.h
[..]
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
new file mode 100644
index 000..5fc4634
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -0,0 +1,872 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2014-2015 Aaron Maoye leafy.m...@reuuimllatech.com
+ * (C) Copyright 2014-2015 O2S GmbH www.o2s.ch
+ * (C) Copyright 2014-2015 David Lanzendörfer david.lanzendoer...@o2s.ch
+ * (C) Copyright 2014-2015 Hans de Goede hdego...@redhat.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/io.h
+#include linux/device.h
+#include linux/interrupt.h
+#include linux/delay.h
+#include linux/err.h
+
+#include linux/clk.h
+#include linux/clk-private.h
+#include linux/clk/sunxi.h
+
+#include linux/gpio.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include linux/scatterlist.h
+#include linux/dma-mapping.h
+#include linux/slab.h
+#include linux/regulator/consumer.h
+
+#include linux/of_address.h
+#include linux/of_gpio.h
+#include linux/of_platform.h
+
+#include linux/mmc/host.h
+#include linux/mmc/sd.h
+#include linux/mmc/sdio.h
+#include linux/mmc/mmc.h
+#include linux/mmc/core.h
+#include linux/mmc/card.h
+#include linux/mmc/slot-gpio.h
+
+#include sunxi-mmc.h
+
+static int sunxi_mmc_init_host(struct mmc_host *mmc)
+{
+ u32 rval;
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ int ret;
+
+ ret = clk_prepare_enable(smc_host-clk_ahb);
+ if (ret) {
+ dev_err(mmc_dev(smc_host-mmc), AHB clk err %d\n, ret);
+ return ret;
+ }
+ ret = clk_prepare_enable(smc_host-clk_mod);
+ if (ret) {
+ dev_err(mmc_dev(smc_host-mmc), MOD clk err %d\n, ret);
+ clk_disable_unprepare(smc_host-clk_ahb);
+ return ret;
+ }
+
+ /* reset controller */
+ rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HARDWARE_RESET;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ mci_writel(smc_host, REG_FTRGL, 0x20070008);
+ mci_writel(smc_host, REG_TMOUT, 0x);
+ mci_writel(smc_host, REG_IMASK, smc_host-sdio_imask);
+ mci_writel(smc_host, REG_RINTR, 0x);
+ mci_writel(smc_host, REG_DBGC, 0xdeb);
+ mci_writel(smc_host, REG_FUNS, 0xceaa);
+ mci_writel(smc_host, REG_DLBA, smc_host-sg_dma);
+ rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTERRUPT_ENABLE_BIT;
+ rval = ~SDXC_ACCESS_DONE_DIRECT;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ return 0;
+}
+
+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
+{
+ mci_writel(smc_host, REG_GCTRL, SDXC_HARDWARE_RESET);
+ clk_disable_unprepare(smc_host-clk_ahb);
+ clk_disable_unprepare(smc_host-clk_mod);
+}
+
+/* /\* UHS-I Operation Modes */
+/* * DS 25MHz 12.5MB/s3.3V */
+/* * HS 50MHz 25MB/s 3.3V */
+/* * SDR1225MHz 12.5MB/s1.8V */
+/* * SDR2550MHz 25MB/s 1.8V */
+/* * SDR50100MHz 50MB/s 1.8V */
+/* * SDR104 208MHz 104MB/s 1.8V */
+/* * DDR5050MHz 50MB/s 1.8V */
+/* * MMC Operation Modes */
+/* * DS 26MHz 26MB/s 3/1.8/1.2V */
+/* * HS 52MHz 52MB/s 3/1.8/1.2V */
+/* * HSDDR52MHz 104MB/s 3/1.8/1.2V */
+/* * HS200200MHz 200MB/s 1.8/1.2V */
+/* * */
+/* * Spec. Timing */
+/* * SD3.0 */
+/* * FcclkTcclk Fsclk Tsclk Tis Tih odly RTis RTih */
+/* * 400K 2.5us 24M 41ns5ns 5ns 1 2209ns
Re: [linux-sunxi] [PATCH 1/2] pinctrl-sunxi: fix external interrupts not working
Hi, On Sat, Feb 15, 2014 at 8:02 PM, Hans de Goede hdego...@redhat.com wrote: Hi All, Here is a patch series fixing external interrupts, tested only on A20 sofar, I'll do a version for upstream once I've tested this more thoroughly, but I wanted to share this right away. I submitted the exact same patch as the second one (chained_irq) last week. See: http://thread.gmane.org/gmane.linux.kernel.stable/79546 With that mmc CD interrupt works on my Cubietruck. Didn't notice the mask offset was wrong. Chen, this should help with using out-of-band interrupts on the cubietruck wifi. I'll test this with David's latest patches. Thanks! ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH 3/5] ARM: sun6i: dt: Add A31 GMAC gigabit ethernet controller node
The A31 has the same GMAC found on the A20 SoC, except it has
an extra reset control.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ee09e4c..e958d5f 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -429,6 +429,22 @@
status = disabled;
};
+ gmac: ethernet@01c3 {
+ compatible = allwinner,sun7i-a20-gmac;
+ reg = 0x01c3 0x1054;
+ interrupts = 0 82 4;
+ interrupt-names = macirq;
+ clocks = ahb1_gates 17, gmac_tx_clk;
+ clock-names = stmmaceth, allwinner_gmac_tx;
+ resets = ahb1_rst 17;
+ snps,pbl = 2;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
spi0: spi@01c68000 {
compatible = allwinner,sun6i-a31-spi;
reg = 0x01c68000 0x1000;
--
1.9.0
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[linux-sunxi] [PATCH 2/5] ARM: sun6i: dt: Add GMAC clock node to the A31 DTSI
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d2a2bf..ee09e4c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -229,6 +229,34 @@
clocks = osc24M, pll6;
clock-output-names = spi3;
};
+
+ /*
+* The following two are dummy clocks, placeholders used in the
gmac_tx
+* clock. The gmac driver will choose one parent depending on
the PHY
+* interface mode, using clk_set_rate auto-reparenting.
+* The actual TX clock rate is not controlled by the gmac_tx
clock.
+*/
+ mii_phy_tx_clk: clk@1 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = mii_phy_tx;
+ };
+
+ gmac_int_tx_clk: clk@2 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 12500;
+ clock-output-names = gmac_int_tx;
+ };
+
+ gmac_tx_clk: clk@01c200d0 {
+ #clock-cells = 0;
+ compatible = allwinner,sun7i-a20-gmac-clk;
+ reg = 0x01c200d0 0x4;
+ clocks = mii_phy_tx_clk, gmac_int_tx_clk;
+ clock-output-names = gmac_tx;
+ };
};
soc@01c0 {
--
1.9.0
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[linux-sunxi] [PATCH 0/5] ARM: sun6i: dt: Add support for GMAC
Hi Maxime, This series add support for the GMAC in A31. The GMAC is the same as in the A20, except it has an extra reset control. The GMAC clock module is mostly the same as in the A20, without the extra dividers, which I left out intentionally from the clock driver. The register offsets and interrupts were copied from A31 SDK in Rhombus Tech's repository. The pin muxes were from the EVB fex file. If you have the A31 datasheet, you could double check them. This series is based on current sunxi-next ( e8176a3b0 ). As I don't have actual A31 hardware, this is only compile tested. Please give it a try, and let me know if it works or not. Cheers, ChenYu Chen-Yu Tsai (5): ARM: sun6i: dt: Add pin muxing options for GMAC ARM: sun6i: dt: Add GMAC clock node to the A31 DTSI ARM: sun6i: dt: Add A31 GMAC gigabit ethernet controller node ARM: sun6i: dt: Add ethernet alias for GMAC ARM: sun6i: columbus: Enable the GMAC arch/arm/boot/dts/sun6i-a31-colombus.dts | 12 + arch/arm/boot/dts/sun6i-a31.dtsi | 87 2 files changed, 99 insertions(+) -- 1.9.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
[linux-sunxi] [PATCH 1/5] ARM: sun6i: dt: Add pin muxing options for GMAC
The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 42
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 42f310a..4d2a2bf 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -257,6 +257,48 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = PA0, PA1, PA2, PA3,
+ PA8, PA9, PA11,
+ PA12, PA13, PA14, PA19,
+ PA20, PA21, PA22, PA23,
+ PA24, PA26, PA27;
+ allwinner,function = gmac;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ gmac_pins_gmii_a: gmac_gmii@0 {
+ allwinner,pins = PA0, PA1, PA2, PA3,
+ PA4, PA5, PA6, PA7,
+ PA8, PA9, PA10, PA11,
+ PA12, PA13, PA14, PA15,
+ PA16, PA17, PA18, PA19,
+ PA20, PA21, PA22, PA23,
+ PA24, PA25, PA26, PA27;
+ allwinner,function = gmac;
+ /*
+* data lines in GMII mode run at 125MHz and
+* might need a higher signal drive strength
+*/
+ allwinner,drive = 2;
+ allwinner,pull = 0;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = PA0, PA1, PA2, PA3,
+ PA9, PA10, PA11,
+ PA12, PA13, PA14, PA19,
+ PA20, PA25, PA26, PA27;
+ allwinner,function = gmac;
+ /*
+* data lines in RGMII mode use DDR mode
+* and need a higher signal drive strength
+*/
+ allwinner,drive = 3;
+ allwinner,pull = 0;
+ };
};
ahb1_rst: reset@01c202c0 {
--
1.9.0
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[linux-sunxi] [PATCH 5/5] ARM: sun6i: columbus: Enable the GMAC
The A31 Colombus board uses the GMAC with a Realtek RTL8211E-VB RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31-colombus.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts
b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index e5adae3..19a0385 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -28,5 +28,17 @@
pinctrl-0 = uart0_pins_a;
status = okay;
};
+
+ gmac: ethernet@01c3 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_rgmii_a;
+ phy = phy1;
+ phy-mode = rgmii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
};
};
--
1.9.0
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[linux-sunxi] [PATCH RFC] hwmon: AXP20x: Add support for hwmon subsystem
AXP202 and AXP209 can report voltages and current readings for its
various power inputs, as well as the LiPo battery. There is also an
internal temperature sensor. This patch adds basic support for them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi everyone,
This is a basic hwmon driver for the AXP209 PMIC. All the internal sensors
are supported. DT support and ADC on GPIO pins, among other things, are
missing. The driver was hastily put together in a couple of hours by copy
and pasting, so feel free to criticize. I just thought I'd get it out there
first. :)
The ACIN/VBUS current sensors are not accurate on the Cubie* boards. These
have bypasses for things like USB VBUS and SATA power.
Cheers
ChenYu
drivers/hwmon/Kconfig| 10 ++
drivers/hwmon/Makefile | 1 +
drivers/hwmon/axp20x-hwmon.c | 242 +++
drivers/mfd/axp20x.c | 3 +
4 files changed, 256 insertions(+)
create mode 100644 drivers/hwmon/axp20x-hwmon.c
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 5ce43d8..dcdf918 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -337,6 +337,16 @@ config SENSORS_ATXP1
This driver can also be built as a module. If so, the module
will be called atxp1.
+config SENSORS_AXP20X
+ tristate X-POWERS AXP20X PMIC
+ depends on MFD_AXP20X
+ help
+ If you say yes here you get support for the hardware
+ monitoring features of the AXP20X series of PMICs.
+
+ This driver can also be built as a module. If so, the module
+ will be called axp20x-hwmon.
+
config SENSORS_DS620
tristate Dallas Semiconductor DS620
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index ec7cde0..410c622 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_SENSORS_ADT7475) += adt7475.o
obj-$(CONFIG_SENSORS_APPLESMC) += applesmc.o
obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o
obj-$(CONFIG_SENSORS_ATXP1)+= atxp1.o
+obj-$(CONFIG_SENSORS_AXP20X) += axp20x-hwmon.o
obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o
obj-$(CONFIG_SENSORS_DA9052_ADC)+= da9052-hwmon.o
obj-$(CONFIG_SENSORS_DA9055)+= da9055-hwmon.o
diff --git a/drivers/hwmon/axp20x-hwmon.c b/drivers/hwmon/axp20x-hwmon.c
new file mode 100644
index 000..9dd78ea
--- /dev/null
+++ b/drivers/hwmon/axp20x-hwmon.c
@@ -0,0 +1,242 @@
+/*
+ * axp20x regulators driver.
+ *
+ * Copyright (C) 2013 Chen-Yu Tsai w...@csie.org
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/err.h
+#include linux/platform_device.h
+#include linux/hwmon.h
+#include linux/hwmon-sysfs.h
+#include linux/regmap.h
+#include linux/i2c.h
+
+#include linux/mfd/axp20x.h
+
+#define AXP20X_ADC_EN1_MASK0xff
+#define AXP20X_ADC_EN2_MASK0x80
+
+/* Use MSB register offset as index */
+static const char * const input_names[] = {
+ [AXP20X_ACIN_V_ADC_H] = ACIN,
+ [AXP20X_ACIN_I_ADC_H] = ACIN,
+ [AXP20X_VBUS_V_ADC_H] = VBUS,
+ [AXP20X_VBUS_I_ADC_H] = VBUS,
+ [AXP20X_TEMP_ADC_H] = CHIP,
+ [AXP20X_TS_IN_H]= TS,
+ [AXP20X_GPIO0_V_ADC_H] = GPIO0,
+ [AXP20X_GPIO1_V_ADC_H] = GPIO1,
+ [AXP20X_PWR_BATT_H] = BATT,
+ [AXP20X_BATT_V_H] = BATT,
+ [AXP20X_BATT_CHRG_I_H] = BATT_CHRG,
+ [AXP20X_BATT_DISCHRG_I_H] = BATT_DISCHRG,
+ [AXP20X_IPSOUT_V_HIGH_H]= IPS_OUT,
+};
+
+static const int input_step[] = {
+ [AXP20X_ACIN_V_ADC_H] = 1700,
+ [AXP20X_ACIN_I_ADC_H] = 625,
+ [AXP20X_VBUS_V_ADC_H] = 1700,
+ [AXP20X_VBUS_I_ADC_H] = 375,
+ [AXP20X_TEMP_ADC_H] = 100,
+ [AXP20X_TS_IN_H] = 800,
+ [AXP20X_GPIO0_V_ADC_H] = 500,
+ [AXP20X_GPIO1_V_ADC_H] = 500,
+ [AXP20X_PWR_BATT_H] = 1100,
+ [AXP20X_BATT_V_H] = 1100,
+ [AXP20X_BATT_CHRG_I_H] = 500,
+ [AXP20X_BATT_DISCHRG_I_H] = 500,
+ [AXP20X_IPSOUT_V_HIGH_H] = 1400,
+};
+
+static int axp20x_adc_read(struct axp20x_dev *axp20x, int channel)
+{
+ unsigned char val[3];
+ int ret;
+
+ if (channel AXP20X_ACIN_V_ADC_H || channel AXP20X_IPSOUT_V_HIGH_H)
+ return -EINVAL;
+
+ /* ADC values are split among at most 3 registers */
+ ret = regmap_bulk_read(axp20x-regmap, channel, val, 3);
+ if (ret) {
+ dev_dbg(axp20x-dev, Read ADC 0x%02x failed: %d\n, channel,
+ ret);
+ return ret
Re: [linux-sunxi] Re: [PATCH v3 1/5] i2c: mv64xxx: Add reset deassert call
On Fri, Mar 7, 2014 at 6:34 PM, Russell King - ARM Linux li...@arm.linux.org.uk wrote: On Fri, Mar 07, 2014 at 11:07:51AM +0100, Maxime Ripard wrote: Hi Russell, On Fri, Mar 07, 2014 at 09:52:23AM +, Russell King - ARM Linux wrote: On Tue, Mar 04, 2014 at 05:28:37PM +0100, Maxime Ripard wrote: The Allwinner A31 SoC using that IP has a reset controller maintaining it reset unless told otherwise. Add some optional reset support to the driver. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com Reviewed-by: Gregory CLEMENT gregory.clem...@free-electrons.com Tested-by: Gregory CLEMENT gregory.clem...@free-electrons.com This appears to be causing some build errors in Olof's next builder for many of the ARM platforms which make use of this: drivers/i2c/busses/i2c-mv64xxx.c:924: undefined reference to `reset_control_assert' drivers/i2c/busses/i2c-mv64xxx.c:904: undefined reference to `reset_control_assert' drivers/i2c/busses/i2c-mv64xxx.c:771: undefined reference to `devm_reset_control_get' drivers/i2c/busses/i2c-mv64xxx.c:778: undefined reference to `reset_control_deassert' The reset framework doesn't define its functions when its not selected, and somehow I think it was not here. What's odd is that there is an explicit select on RESET_CONTROLLER in the Kconfig. Maybe it's the circular dependency issue that has been reported that cause this and Wolfram sent a patch for: http://patchwork.ozlabs.org/patch/327573/ If that patch has been taken, then yes, it will have caused the above - because now we have Dove and Kirkwood platforms trying to build this driver without RESET_CONTROLLER being set. The problem with depending on RESET_CONTROLLER is that then these platforms end up without their I2C controller - because there's nothing which enables RESET_CONTROLLER in their configuration. Since RESET_CONTROLLER is not required for those platforms, it really should be optional - and I think the real fix is for the reset controller support to provide stub functions. Philipp Zabel suggested that adding a _optional variant that provides stubs and doesn't depend on RESET_CONTROLLER is probably better. This keeps the compile time checks for drivers requiring it. See: https://lkml.org/lkml/2014/1/10/220 I ended up dropping my patch though. Cheers, ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH v1 9/9] sunxi: add gmac Ethernet support
On Fri, Mar 14, 2014 at 6:33 PM, Ian Campbell i...@hellion.org.uk wrote:
Based linux-sunxi#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section in
ldscripts vs v2014.01.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Jens Kuske jensku...@gmail.com
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/board.c | 15 +
boards.cfg | 4 +--
drivers/net/Makefile | 1 +
drivers/net/sunxi_gmac.c | 34
include/configs/sunxi-common.h | 68
5 files changed, 120 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/sunxi_gmac.c
[..]
diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
new file mode 100644
index 000..432d7b2
--- /dev/null
+++ b/drivers/net/sunxi_gmac.c
@@ -0,0 +1,34 @@
+#include common.h
+#include netdev.h
+#include miiphy.h
+#include asm/gpio.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+
+int sunxi_gmac_initialize(bd_t *bis)
+{
+ int pin;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set up clock gating */
+ setbits_le32(ccm-ahb_gate1, 0x1 AHB_GATE_OFFSET_GMAC);
+
+ /* Set MII clock */
+ setbits_le32(ccm-gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII);
+
+ /* Configure pin mux settings for GMAC */
+ for (pin = SUNXI_GPA(0); pin = SUNXI_GPA(16); pin++) {
+ /* skip unused pins in RGMII mode */
+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+ continue;
+ sunxi_gpio_set_cfgpin(pin, 5);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+
+ designware_initialize(0, SUNXI_GMAC_BASE, 0x1,
PHY_INTERFACE_MODE_RGMII);
Hi,
Thanks for working on this!
I see you left out all the CONFIG_RGMII ifdefs from this file. Not
sure if it's because you're aiming to support only the Cubietruck
first. I think you should keep them in the same patch. You can then
just add the appropriate config options when support of other A20
boards roll in.
There are 3 changes to the designware driver since u-boot-sunxi's
last merge (2014.1-rc1):
50b0df8 net/designware: make driver compatible with data cache
92a190a net/designware - switch driver to phylib usage
74cb708 net/designware: add explicit reset of {tx|rx}_currdescnum
The move to phylib will likely break the current code. Maybe we could
merge 2014.4-rc1 in to fix it first.
Also, GMAC support depends on
5a51af3 net/designware: Reduce DMA burst length
by Jens Kuske (jemk). Neither of us bothered to send this upstream yet.
Cheers
ChenYu
+
+ return 0;
+}
[..]
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Re: [linux-sunxi] Re: [U-Boot] [PATCH v1 7/9] sunxi: mmc support
On Mon, Mar 17, 2014 at 4:38 AM, Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-03-14 at 17:36 +0200, Pantelis Antoniou wrote:
[...]
Thanks for your review. It seems there are still quite a few issues
dating back to the original allwinner dumps here.
@linux-sunxi: if anyone wants to volunteer to help cleanup this
particular driver I'd be very happy -- there's a lot of it!
+
+static void dumpmmcreg(struct sunxi_mmc *reg)
+{
+ debug(dump mmc registers:\n);
+ debug(gctrl 0x%08x\n, reg-gctrl);
+ debug(clkcr 0x%08x\n, reg-clkcr);
+ debug(timeout 0x%08x\n, reg-timeout);
+ debug(width 0x%08x\n, reg-width);
+ debug(blksz 0x%08x\n, reg-blksz);
[...] lots more debug(foo)
+}
^^^ #ifdef DEBUG here?
I can if you prefer but debug() itself effectively includes the same
ifdef so the end result is already the same.
[...]
+/* support 4 mmc hosts */
+struct mmc mmc_dev[4];
+struct sunxi_mmc_host mmc_host[4];
+
^ hosts mmc structs can be allocated even for SPL now
Can be or must be?
+ struct sunxi_mmc_host *mmchost = mmc_host[sdc_no];
+ static struct sunxi_gpio *gpio_c =
+ ((struct sunxi_gpio_reg
*)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_C];
+ static struct sunxi_gpio *gpio_f =
+ ((struct sunxi_gpio_reg
*)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_F];
+#if CONFIG_MMC1_PG
+ static struct sunxi_gpio *gpio_g =
+ ((struct sunxi_gpio_reg
*)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_G];
+#endif
+ static struct sunxi_gpio *gpio_h =
+ ((struct sunxi_gpio_reg
*)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_H];
+ static struct sunxi_gpio *gpio_i =
+ ((struct sunxi_gpio_reg
*)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_I];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
^ Castings are ugly; rework with a temporary variable.
Ack.
The static's here are odd too and date back to the original alwinner
code dumps. I'll get rid of them too.
You can drop the gpio ones in favor of using the sunxi gpio driver.
[...]
+ case 3:
+ /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
+ writel(0x 16, gpio_i-cfg[0]);
+ writel(0x22, gpio_i-cfg[1]);
+ writel(0x555 8, gpio_i-pull[0]);
+ writel(0x555 8, gpio_i-drv[0]);
+ break;
+
+ default:
+ return -1;
+ }
+
Lots of magic constants. I have no idea what's going on here.
Use a few defines.
Right. These came from the original allwinner dumps so I was worried
that they might be undocumented magic, but actually since the are gpio
frobbing I reckon I can figure them out.
Should be something like this:
for (pin = SUNXI_GPI(4); pin = SUNXI_GPI(9); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
sunxi_gpio_set_drv(pin, 1);
sunxi_gpio_set_pull(pin, SUNXI_PULL_UP);
}
Note that SUNXI_GPI_* and SUNXI_PULL_* have not been defined.
I will send a patch for both the macros and MMC pinmux setting.
[..]
Thanks for working on this!
Cheers
ChenYu
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[linux-sunxi] [PATCH u-boot sunxi 5/5] mmc: sunxi: Use sunxi gpio functions to configure pins
Use the sunxi gpio driver to configure pins, instead of directly
writing magic numbers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/mmc/sunxi_mmc.c | 56 +++--
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index eae1f7c..248d669 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -138,22 +138,11 @@ static int mmc_resource_init(int sdc_no)
static int mmc_clk_io_on(int sdc_no)
{
+ unsigned int pin;
unsigned int rval;
unsigned int pll5_clk;
unsigned int divider;
struct sunxi_mmc_host *mmchost = mmc_host[sdc_no];
- static struct sunxi_gpio *gpio_c =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_C];
- static struct sunxi_gpio *gpio_f =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_F];
-#if CONFIG_MMC1_PG
- static struct sunxi_gpio *gpio_g =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_G];
-#endif
- static struct sunxi_gpio *gpio_h =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_H];
- static struct sunxi_gpio *gpio_i =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_I];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
debug(init mmc %d clock and io\n, sdc_no);
@@ -162,40 +151,47 @@ static int mmc_clk_io_on(int sdc_no)
switch (sdc_no) {
case 0:
/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
- writel(0x22, gpio_f-cfg[0]);
- writel(0x555, gpio_f-pull[0]);
- writel(0xaaa, gpio_f-drv[0]);
+ for (pin = SUNXI_GPF(0); pin = SUNXI_GPF(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0_CMD);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
break;
case 1:
#if CONFIG_MMC1_PG
/* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
- writel(0x44, gpio_g-cfg[0]);
- writel(0x555, gpio_g-pull[0]);
- writel(0xaaa, gpio_g-drv[0]);
+ for (pin = SUNXI_GPG(0); pin = SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPG0_SDC1_CMD;
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#else
/* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
- writel(0x55 24, gpio_h-cfg[2]);
- writel(0x, gpio_h-cfg[3]);
- writel(0x555 12, gpio_h-pull[1]);
- writel(0xaaa 12, gpio_h-drv[1]);
+ for (pin = SUNXI_GPH(22); pin = SUNXI_GPH(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1_CMD);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#endif
break;
case 2:
/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
- writel(0x33 24, gpio_c-cfg[0]);
- writel(0x, gpio_c-cfg[1]);
- writel(0x555 12, gpio_c-pull[0]);
- writel(0xaaa 12, gpio_c-drv[0]);
+ for (pin = SUNXI_GPC(6); pin = SUNXI_GPC(11); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2_CMD);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
break;
case 3:
/* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
- writel(0x 16, gpio_i-cfg[0]);
- writel(0x22, gpio_i-cfg[1]);
- writel(0x555 8, gpio_i-pull[0]);
- writel(0x555 8, gpio_i-drv[0]);
+ for (pin = SUNXI_GPI(4); pin = SUNXI_GPI(9); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3_CMD);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
break;
default:
--
1.9.0
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[linux-sunxi] [PATCH u-boot sunxi 4/5] net: sunxi_gmac: Use sunxi gpio pin function macros
Signed-off-by: Chen-Yu Tsai w...@csie.org --- drivers/net/sunxi_gmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c index b8b9016..98a78c4 100644 --- a/drivers/net/sunxi_gmac.c +++ b/drivers/net/sunxi_gmac.c @@ -31,7 +31,7 @@ int sunxi_gmac_initialize(bd_t *bis) if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) continue; #endif - sunxi_gpio_set_cfgpin(pin, 5); + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GRXD3); sunxi_gpio_set_drv(pin, 3); } -- 1.9.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot sunxi 2/5] i2c: sunxi: Use sunxi gpio pin function macros
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/i2c/sunxi_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/sunxi_i2c.c b/drivers/i2c/sunxi_i2c.c
index 5fe790a..5babf06 100644
--- a/drivers/i2c/sunxi_i2c.c
+++ b/drivers/i2c/sunxi_i2c.c
@@ -19,8 +19,8 @@ void i2c_init(int speed, int slaveaddr)
{
int timeout = 0x2ff;
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0_SCK);
clock_twi_onoff(0, 1);
/* Enable the i2c bus */
--
1.9.0
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[linux-sunxi] Re: [PATCH u-boot sunxi 5/5] mmc: sunxi: Use sunxi gpio functions to configure pins
On Mon, Mar 17, 2014 at 4:28 PM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-03-17 at 12:05 +0800, Chen-Yu Tsai wrote:
@@ -162,40 +151,47 @@ static int mmc_clk_io_on(int sdc_no)
switch (sdc_no) {
case 0:
/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
- writel(0x22, gpio_f-cfg[0]);
- writel(0x555, gpio_f-pull[0]);
- writel(0xaaa, gpio_f-drv[0]);
+ for (pin = SUNXI_GPF(0); pin = SUNXI_GPF(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0_CMD);
I appreciate that the function is the same for each pin but this still
looks odd. Perhaps just #define SUNXI_GPFx_SDC0 and use that?
I was matching what was already defined, but yeah, that looks better.
Maybe we should change the other existing one as well?
I'm referring to the whole patch series, and the ones already in gpio.h.
I did something similar yesterday and just opencoded the calls.
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
I was wondering about these -- do these matter even when the PIN is
configured for a specific function and not as a GPIO?
The pull-up/downs and drive strength are valid regardless whether the
PIN is used for GPIO (input/output). IIRC, most boards have external
pull-ups for MMC, so sunxi_gpio_set_pull can be dropped. Drive strength
must be set for MMC to work reliably. This was tested by Hans for the
kernel DTs.
Cheers,
ChenYu
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[linux-sunxi] [PATCH u-boot sunxi v2 2/6] i2c: sunxi: Use sunxi gpio pin function macros
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/i2c/sunxi_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/sunxi_i2c.c b/drivers/i2c/sunxi_i2c.c
index 5fe790a..9a542f6 100644
--- a/drivers/i2c/sunxi_i2c.c
+++ b/drivers/i2c/sunxi_i2c.c
@@ -19,8 +19,8 @@ void i2c_init(int speed, int slaveaddr)
{
int timeout = 0x2ff;
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
clock_twi_onoff(0, 1);
/* Enable the i2c bus */
--
1.9.0
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[linux-sunxi] [PATCH u-boot sunxi v2 5/6] mmc: sunxi: Use sunxi gpio functions to configure pins
Use the sunxi gpio driver to configure pins, instead of directly
writing magic numbers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/mmc/sunxi_mmc.c | 56 +++--
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index eae1f7c..80e4369 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -138,22 +138,11 @@ static int mmc_resource_init(int sdc_no)
static int mmc_clk_io_on(int sdc_no)
{
+ unsigned int pin;
unsigned int rval;
unsigned int pll5_clk;
unsigned int divider;
struct sunxi_mmc_host *mmchost = mmc_host[sdc_no];
- static struct sunxi_gpio *gpio_c =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_C];
- static struct sunxi_gpio *gpio_f =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_F];
-#if CONFIG_MMC1_PG
- static struct sunxi_gpio *gpio_g =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_G];
-#endif
- static struct sunxi_gpio *gpio_h =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_H];
- static struct sunxi_gpio *gpio_i =
- ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_I];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
debug(init mmc %d clock and io\n, sdc_no);
@@ -162,40 +151,47 @@ static int mmc_clk_io_on(int sdc_no)
switch (sdc_no) {
case 0:
/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
- writel(0x22, gpio_f-cfg[0]);
- writel(0x555, gpio_f-pull[0]);
- writel(0xaaa, gpio_f-drv[0]);
+ for (pin = SUNXI_GPF(0); pin = SUNXI_GPF(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
break;
case 1:
#if CONFIG_MMC1_PG
/* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
- writel(0x44, gpio_g-cfg[0]);
- writel(0x555, gpio_g-pull[0]);
- writel(0xaaa, gpio_g-drv[0]);
+ for (pin = SUNXI_GPG(0); pin = SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPG0_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#else
/* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
- writel(0x55 24, gpio_h-cfg[2]);
- writel(0x, gpio_h-cfg[3]);
- writel(0x555 12, gpio_h-pull[1]);
- writel(0xaaa 12, gpio_h-drv[1]);
+ for (pin = SUNXI_GPH(22); pin = SUNXI_GPH(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#endif
break;
case 2:
/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
- writel(0x33 24, gpio_c-cfg[0]);
- writel(0x, gpio_c-cfg[1]);
- writel(0x555 12, gpio_c-pull[0]);
- writel(0xaaa 12, gpio_c-drv[0]);
+ for (pin = SUNXI_GPC(6); pin = SUNXI_GPC(11); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
break;
case 3:
/* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
- writel(0x 16, gpio_i-cfg[0]);
- writel(0x22, gpio_i-cfg[1]);
- writel(0x555 8, gpio_i-pull[0]);
- writel(0x555 8, gpio_i-drv[0]);
+ for (pin = SUNXI_GPI(4); pin = SUNXI_GPI(9); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
break;
default:
--
1.9.0
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[linux-sunxi] [PATCH u-boot sunxi v2 1/6] ARM: sunxi: Add gpio pull-up/down and cleanup pin function definitions
Add definitions for pull-up/downs, and several pin functions used
by various drivers, such as gmac, i2c, and mmc.
Also remove any pin functions not currently used by drivers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/gpio.h | 48 +++---
1 file changed, 15 insertions(+), 33 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index d5a01d8..9509ed7 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -102,20 +102,10 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
-#define SUNXI_GPA0_ERXD3 2
-#define SUNXI_GPA0_SPI1_CS03
-#define SUNXI_GPA0_UART2_RTS 4
+#define SUNXI_GPA0_EMAC2
+#define SUN7I_GPA0_GMAC5
-#define SUNXI_GPA1_ERXD2 2
-#define SUNXI_GPA1_SPI1_CLK3
-#define SUNXI_GPA1_UART2_CTS 4
-
-#define SUNXI_GPA2_ERXD1 2
-#define SUNXI_GPA2_SPI1_MOSI 3
-#define SUNXI_GPA2_UART2_TX4
-
-#define SUNXI_GPA10_UART1_TX 4
-#define SUNXI_GPA11_UART1_RX 4
+#define SUNXI_GPB0_TWI02
#define SUN4I_GPB22_UART0_TX 2
#define SUN4I_GPB23_UART0_RX 2
@@ -126,32 +116,24 @@ enum sunxi_gpio_number {
#define SUN5I_GPG3_UART0_TX4
#define SUN5I_GPG4_UART0_RX4
-#define SUNXI_GPC2_NCLE2
-#define SUNXI_GPC2_SPI0_CLK3
-
-#define SUNXI_GPC6_NRB02
-#define SUNXI_GPC6_SDC2_CMD3
-
-#define SUNXI_GPC7_NRB12
-#define SUNXI_GPC7_SDC2_CLK3
+#define SUNXI_GPC6_SDC23
-#define SUNXI_GPC8_NDQ02
-#define SUNXI_GPC8_SDC2_D0 3
+#define SUNXI_GPF0_SDC02
-#define SUNXI_GPC9_NDQ12
-#define SUNXI_GPC9_SDC2_D1 3
+#define SUNXI_GPF2_SDC02
+#define SUNXI_GPF2_UART0_TX4
+#define SUNXI_GPF4_UART0_RX4
-#define SUNXI_GPC10_NDQ2 2
-#define SUNXI_GPC10_SDC2_D23
+#define SUN4I_GPG0_SDC14
-#define SUNXI_GPC11_NDQ3 2
-#define SUNXI_GPC11_SDC2_D33
+#define SUN4I_GPH22_SDC1 5
-#define SUNXI_GPF2_SDC0_CLK2
-#define SUNXI_GPF2_UART0_TX4
+#define SUN4I_GPI4_SDC32
-#define SUNXI_GPF4_SDC0_D3 2
-#define SUNXI_GPF4_UART0_RX4
+/* GPIO pin pull-up/down config */
+#define SUNXI_GPIO_PULL_DISABLE0
+#define SUNXI_GPIO_PULL_UP 1
+#define SUNXI_GPIO_PULL_DOWN 2
int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_gpio_get_cfgpin(u32 pin);
--
1.9.0
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[linux-sunxi] [PATCH u-boot sunxi v2 0/6] sunxi: Clean up magic numbers for gpio config
Hi, This series cleans up the gpio config definitions. Unused ones are removed, and new ones are added for i2c, mmc, emac and gmac. Also fixed uart1 name for sun5i. Changes since v1: * Renamed macros to SUNXI_GPXNN_FUNCTION (ex: SUNXI_GPA0_EMAC), where NN identifies the start of the function group. Macros for UARTs were left as-is, as one of them is not consecutive. Also pull-ups are only enabled on the RX pin, leaving RX/TX in the name helps reading the code. * Fixed sun5i UART1 name. * Fixed a compile error introduced in v1. Cheers ChenYu Chen-Yu Tsai (6): ARM: sunxi: Add gpio pull-up/down and cleanup pin function definitions i2c: sunxi: Use sunxi gpio pin function macros net: sunxi_emac: Use sunxi gpio pin function macros net: sunxi_gmac: Use sunxi gpio pin function macros mmc: sunxi: Use sunxi gpio functions to configure pins ARM: sunxi: fix sun5i uart1 pin definition name arch/arm/cpu/armv7/sunxi/board.c | 4 +-- arch/arm/include/asm/arch-sunxi/gpio.h | 52 +++ drivers/i2c/sunxi_i2c.c| 4 +-- drivers/mmc/sunxi_mmc.c| 56 -- drivers/net/sunxi_emac.c | 2 +- drivers/net/sunxi_gmac.c | 2 +- 6 files changed, 49 insertions(+), 71 deletions(-) -- 1.9.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot sunxi v2 4/6] net: sunxi_gmac: Use sunxi gpio pin function macros
Signed-off-by: Chen-Yu Tsai w...@csie.org --- drivers/net/sunxi_gmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c index b8b9016..7a36581 100644 --- a/drivers/net/sunxi_gmac.c +++ b/drivers/net/sunxi_gmac.c @@ -31,7 +31,7 @@ int sunxi_gmac_initialize(bd_t *bis) if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) continue; #endif - sunxi_gpio_set_cfgpin(pin, 5); + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); sunxi_gpio_set_drv(pin, 3); } -- 1.9.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot sunxi v2 3/6] net: sunxi_emac: Use sunxi gpio pin function macros
Signed-off-by: Chen-Yu Tsai w...@csie.org --- drivers/net/sunxi_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 0cadf89..5a06d68 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -497,7 +497,7 @@ int sunxi_emac_initialize(void) /* Configure pin mux settings for MII Ethernet */ for (pin = SUNXI_GPA(0); pin = SUNXI_GPA(17); pin++) - sunxi_gpio_set_cfgpin(pin, 2); + sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC); /* Set up clock gating */ setbits_le32(ccm-ahb_gate0, 0x1 AHB_GATE_OFFSET_EMAC); -- 1.9.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot sunxi v2 6/6] ARM: sunxi: fix sun5i uart1 pin definition name
The pin definition for uart1 was mis-named as uart0.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4 ++--
arch/arm/include/asm/arch-sunxi/gpio.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 5c2ce3f..0abf27e 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -67,8 +67,8 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
#elif CONFIG_CONS_INDEX == 2 defined(CONFIG_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART0_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 9509ed7..802f347 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -113,8 +113,8 @@ enum sunxi_gpio_number {
#define SUN5I_GPB19_UART0_TX 2
#define SUN5I_GPB20_UART0_RX 2
-#define SUN5I_GPG3_UART0_TX4
-#define SUN5I_GPG4_UART0_RX4
+#define SUN5I_GPG3_UART1_TX4
+#define SUN5I_GPG4_UART1_RX4
#define SUNXI_GPC6_SDC23
--
1.9.0
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[linux-sunxi] [PATCH] Add Ippo Q8H-v5
Signed-off-by: Chen-Yu Tsai w...@csie.org --- sys_config/a23/ippo-q8h-v5.fex | 844 + 1 file changed, 844 insertions(+) create mode 100644 sys_config/a23/ippo-q8h-v5.fex diff --git a/sys_config/a23/ippo-q8h-v5.fex b/sys_config/a23/ippo-q8h-v5.fex new file mode 100644 index 000..be31310 --- /dev/null +++ b/sys_config/a23/ippo-q8h-v5.fex @@ -0,0 +1,844 @@ +[product] +version = 100 +machine = a23-a70H + +[platform] +eraseflag = 1 +next_work = 2 + +[target] +boot_clock = 1008 +storage_type = -1 + +[power_sply] +dcdc1_vol = 3000 +dcdc2_vol = 1100 +dcdc3_vol = 1260 +dcdc4_vol = 0 +dcdc5_vol = 1500 +aldo2_vol = 2500 +aldo3_vol = 3000 + +[card_boot] +logical_start = 40960 +sprite_gpio0 = + +[card0_boot_para] +card_ctrl = 0 +card_high_speed = 1 +card_line = 4 +sdc_d1 = port:PF00212default +sdc_d0 = port:PF01212default +sdc_clk = port:PF02212default +sdc_cmd = port:PF03212default +sdc_d3 = port:PF04212default +sdc_d2 = port:PF05212default + +[card2_boot_para] +card_ctrl = 2 +card_high_speed = 1 +card_line = 4 +sdc_clk = port:PC05312default +sdc_cmd = port:PC06312default +sdc_d0 = port:PC08312default +sdc_d1 = port:PC09312default +sdc_d2 = port:PC10312default +sdc_d3 = port:PC11312default + +[twi_para] +twi_port = 0 +twi_scl = port:PH022defaultdefaultdefault +twi_sda = port:PH032defaultdefaultdefault + +[uart_para] +uart_debug_port = 0 +uart_debug_tx = port:PF0231defaultdefault +uart_debug_rx = port:PF0431defaultdefault + +[jtag_para] +jtag_enable = 0 +jtag_ms = port:PF003defaultdefaultdefault +jtag_ck = port:PF053defaultdefaultdefault +jtag_do = port:PF033defaultdefaultdefault +jtag_di = port:PF013defaultdefaultdefault + +[clock] +pll3 = 297 +pll4 = 300 +pll6 = 600 +pll8 = 408 +pll9 = 480 +pll10 = 468 + +[pm_para] +standby_mode = 1 + +[dram_para] +dram_clk = 480 +dram_type = 3 +dram_zq = 0xf777 +dram_odt_en = 1 +dram_para1 = 17835008 +dram_para2 = 0 +dram_mr0 = 6736 +dram_mr1 = 4 +dram_mr2 = 16 +dram_mr3 = 0 +dram_tpr0 = 0x2ab83def +dram_tpr1 = 0x18082356 +dram_tpr2 = 0x34156 +dram_tpr3 = 0x448c5533 +dram_tpr4 = 0x8010d00 +dram_tpr5 = 0x340b20f +dram_tpr6 = 0x20d118cc +dram_tpr7 = 0x14062485 +dram_tpr8 = 0x220d1d52 +dram_tpr9 = 0x1e078c22 +dram_tpr10 = 0x3c +dram_tpr11 = 0x0 +dram_tpr12 = 0x96 +dram_tpr13 = 0x3 + +[wakeup_src_para] +cpu_en = 0 +cpu_freq = 48 +pll_ratio = 273 +dram_selfresh_en = 1 +dram_freq = 36 + +[twi0] +twi_used = 1 +twi_scl = port:PH022defaultdefaultdefault +twi_sda = port:PH032defaultdefaultdefault + +[twi1] +twi_used = 1 +twi_scl = port:PH042defaultdefaultdefault +twi_sda = port:PH052defaultdefaultdefault + +[twi2] +twi_used = 1 +twi_scl = port:PE123defaultdefaultdefault +twi_sda = port:PE133defaultdefaultdefault + +[uart0] +uart_used = 0 +uart_port = 0 +uart_type = 2 +uart_tx = port:PF0231defaultdefault +uart_rx = port:PF0431defaultdefault + +[uart1] +uart_used = 0 +uart_type = 4 +uart_tx = port:PG0621defaultdefault +uart_rx = port:PG0721defaultdefault +uart_rts = port:PG0821defaultdefault +uart_cts = port:PG0921defaultdefault + +[uart2] +uart_used = 0 +uart_type = 4 +uart_tx = port:PB0021defaultdefault +uart_rx = port:PB0121defaultdefault +uart_rts = port:PB0221defaultdefault +uart_cts = port:PB0321defaultdefault + +[uart3] +uart_used = 0 +uart_type = 4 +uart_tx = port:PH0631defaultdefault +uart_rx = port:PH0731defaultdefault +uart_rts = port:PH0831defaultdefault +uart_cts = port:PH0931defaultdefault + +[uart4] +uart_used = 0 +uart_port = 4 +uart_type = 2 +uart_tx = port:PA0421defaultdefault +uart_rx = port:PA0521defaultdefault +uart_rts = port:PA0621defaultdefault +uart_cts = port:PA0721defaultdefault + +[spi0] +spi_used = 0 +spi_cs_bitmap = 1 +spi_mosi = port:PC003defaultdefaultdefault +spi_miso = port:PC013defaultdefaultdefault +spi_sclk = port:PC023defaultdefaultdefault +spi_cs0 = port:PC0331defaultdefault + +[spi1] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA0021defaultdefault +spi_sclk = port:PA012defaultdefaultdefault +spi_mosi = port:PA022defaultdefaultdefault +spi_miso = port:PA032defaultdefaultdefault + +[spi_devices] +spi_dev_num = 0 + +[spi_board0] +modalias = at25df641 +max_speed_hz = 5000 +bus_num = 0 +chip_select = 0 +mode = 0 + +[ctp_para] +ctp_used = 1 +ctp_name = gsl1688_a70 +ctp_twi_id = 0 +ctp_twi_addr = 0x40 +ctp_screen_max_x = 800 +ctp_screen_max_y = 480 +ctp_revert_x_flag = 0 +ctp_revert_y_flag = 0 +ctp_exchange_x_y_flag = 1 +ctp_int_port = port:PB054defaultdefaultdefault +ctp_wakeup = port:PH011defaultdefault1 + +[ctp_list_para] +ctp_det_used = 1 +ft5x_ts = 1 +gt82x = 1 +gslX680 = 1 +gslX680new = 0 +gt9xx_ts = 1 +gt9xxf_ts = 0 +gt811 = 1 +gt818 = 1 +zet622x = 1 +aw5306_ts = 1 + +[tkey_para] +tkey_used = 0 +tkey_twi_id = +tkey_twi_addr = +tkey_int = + +[motor_para] +motor_used = 0 +motor_shake = +motor_ldo = axp22_dldo4 +motor_ldo_voltage = 3300 + +[ths_para] +ths_used = 1 + +[nand0_para] +nand_support_2ch = 0 +nand0_used = 0 +nand0_we = port:PC002defaultdefaultdefault +nand0_ale
Re: [linux-sunxi] [PATCH u-boot-sunxi.git] sunxi: dram: checkpatch.pl cleanups
Hi, On Mon, Mar 24, 2014 at 4:21 AM, Hans de Goede hdego...@redhat.com wrote: Hi, On 03/23/2014 04:13 PM, Ian Campbell wrote: On Sat, 2014-03-22 at 20:22 +0100, Hans de Goede wrote: One thing that stands out when doing a diff against sunxi-merge-v2014.04-rc2 is this: --- u-boot/drivers/net/designware.c 2014-03-21 16:26:42.229522420 +0100 +++ u-boot-sunxi/drivers/net/designware.c 2014-03-22 17:21:51.907879720 + @@ -249,10 +249,10 @@ rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, dma_p-busmode); + writel(FIXEDBURST | PRIORXTX_41 | BURST_8, dma_p-busmode); This is required. The GMAC IP does not support DMA burst lengths above 8. - writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD, - dma_p-opmode); + writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, dma_p-opmode); This is a performance improvement change, as seen in the Linux kernel: csr6 |= DMA_CONTROL_TSF; /* Operating on second frame increase the performance * especially when transmit store-and-forward is used. */ csr6 |= DMA_CONTROL_OSF; Though AFAIK we never changed this. Maybe it was changed upstream. writel(readl(dma_p-opmode) | RXSTART | TXSTART, dma_p-opmode); Which we should probably fix given that you've enabled gmac support. Things work for me without. IIRC the BURST_8 is necessary to get certain traffic patterns to not cause corruption. Don't know about the rest. Wens probably knows best. See above. I was under the impression that Wens (or someone else) had this under control WRT upstreaming so I was leaving it for now, I'm not sure wens, or anyone for that matter is actively working on gmac u-boot support. Sorry, no one is actively working on this ATM. If you could do it, that would be nice. Only a oneliner to change the burst length is required. it can easily go in as an independent fix AFAICT. It can and it should, but first we need some more info I guess, wens ? See inline comments above. I regret that my attention is focused elsewhere ATM, with all that's happened in the last week (and still ongoing) in my country. Feel free to run any GMAC related patches by me, though. I will try to look at it. Cheers ChenYu I also noticed that in include/configs/sunxi-common.h you've a formatting fix for the CONFIG_PHY_ADDR #define which is not yet in u-boot-sunxi. CONFIG_PHY_ADDR arrived as part of the merge of v2014.04-rc2, so the fix got folded into the merge when I redid it. Ah, ok. I might manage a v3, which will be a couple of cleanups and a lot of clarifications about licensing, today, or I might watch game of thrones and do v3 later in the week, lets see how it goes... Sounds good. I hope that your license clarification will be good enough for upstream, and thanks for working on this. Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH u-boot-sunxi.git] sunxi: dram: checkpatch.pl cleanups
On Mon, Mar 24, 2014 at 4:39 PM, Ian Campbell i...@hellion.org.uk wrote: On Mon, 2014-03-24 at 12:55 +0800, Chen-Yu Tsai wrote: Hi, On Mon, Mar 24, 2014 at 4:21 AM, Hans de Goede hdego...@redhat.com wrote: Hi, On 03/23/2014 04:13 PM, Ian Campbell wrote: On Sat, 2014-03-22 at 20:22 +0100, Hans de Goede wrote: One thing that stands out when doing a diff against sunxi-merge-v2014.04-rc2 is this: --- u-boot/drivers/net/designware.c 2014-03-21 16:26:42.229522420 +0100 +++ u-boot-sunxi/drivers/net/designware.c 2014-03-22 17:21:51.907879720 + @@ -249,10 +249,10 @@ rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, dma_p-busmode); + writel(FIXEDBURST | PRIORXTX_41 | BURST_8, dma_p-busmode); This is required. The GMAC IP does not support DMA burst lengths above 8. Should this be a per-platform option or should it be reduced for everyone? Having to make that call is one of the main reasons I've been leaving it alone since I just don't have the necessary context. Reducing it for everyone shouldn't break anything. As for the performance decrease, does anyone actually use U-boot to transfer loads of data? - writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD, - dma_p-opmode); + writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, dma_p-opmode); This is a performance improvement change, What sort of magnitude is it? e.g. I'm not sure how important a few percent would be in a bootloader, but if it were a 200% improvement then well. In any case I think I won't tackle this bit as part of the initial upstreaming attempt. A quick blame shows this was removed in 92a190a net/designware - switch driver to phylib usage The whole section was reworked. I don't know if it was purposely left out, or it was just an error. The commit log doesn't mention it. As for the performance improvement, I don't think it would be up to 200%, but I haven't tested it. Cheers, ChenYu I was under the impression that Wens (or someone else) had this under control WRT upstreaming so I was leaving it for now, I'm not sure wens, or anyone for that matter is actively working on gmac u-boot support. Sorry, no one is actively working on this ATM. If you could do it, that would be nice. Only a oneliner to change the burst length is required. I'll add it (the burst setting) to my list, but I may not do it until after the initial effort has gone upstream. Ian. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v3 08/10] ARM: sun7i/sun4i: dt: Add AXP209 support to various boards
On Fri, Mar 28, 2014 at 5:29 AM, Carlo Caione ca...@caione.org wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 13 +
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 13 +
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 19 +++
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 13 +
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 19 +++
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 19 +++
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 13 +
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 14 ++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 15 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 14 ++
10 files changed, 152 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index fa746aea..cf18c4d 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -88,6 +88,19 @@
pinctrl-names = default;
pinctrl-0 = i2c0_pins_a;
status = okay;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ axp: axp20x@34 {
Hi,
Sorry for spotting this just now. I suggest you change it to
axp209: pmic@34 {
or
axp209_pmic@34 {
to match the ePAPR policy that node names should be generic and
describe functionality. The latter is what some DTs use.
+ reg = 0x34;
+ interrupts = 0;
+
+ compatible = x-powers,axp209;
+ interrupt-controller;
+ #interrupt-cells = 1;
+
+ /include/ x-powers-axp209.dtsi
+ };
};
};
[...]
Same for all the other files.
Thanks for working on this!
ChenYu
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Re: [linux-sunxi] [PATCH u-boot-sunxi 00/11] Initial sun6i support
Hi, On Fri, Mar 28, 2014 at 6:16 PM, Hans de Goede hdego...@redhat.com wrote: Hi All, Here is a u-boot-sunxi patch series adding initial sun6i support, it is based on Maxime's bring up work for sun6i, to which I've added mmc support. Note that this makes some changes to how we handle the mmc module clock in general, which brings the u-boot code in line with what the kernel does for the mmc mod clock. This series does not add full sun6i support, we don't have an SPL / dram setup code yet. What this series does is generate a u-boot.bin which can be used to replace the u-boot used on sdcard images generated by the allwinner tools. IOW boot0 and boot1 are still needed. Has anyone tried the dram setup code here: http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;h=9275ca21ac99592c7d520a41c0914b359c27b913;hb=refs/heads/lichee/jb-4.2.2-a31 What else is needed for SPL? Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] sun6i SPL support status update
Hi Hans, On Sun, Mar 30, 2014 at 8:04 PM, Hans de Goede hdego...@redhat.com wrote: Hi, After wens pointed me to: http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;h=9275ca21ac99592c7d520a41c0914b359c27b913;hb=refs/heads/lichee/jb-4.2.2-a31 I've tried to get a full SPL going on sun6i. No luck sofar, dropping in dram_sun6i.[c,h] +pll5 config seems to get the dram going, at least get_ram_size() likes it. But I cannot get the mmc to work in the SPL. I've narrowed this down to 2 problems, which I believe are related: 1) The mmc controller will simply not work with pll6 as source, after adding a test for the pll6 lock bit I believe this is caused by pll6 never locking. 2) When switching the mmc controller clocksource to OSC24M, then it does work, but gets stuck reading the first sector from the card. I believe this happens because the card is only being supplied 3.0V' rather then 3.3V. Note that the same code works fine in the no SPL u-boot when loaded through boot0 + boot1. Likely wrong power supply voltages are the culprit in both cases (the A31 also has a vdd-pll power pin. So it looks like the next step is to first get the pmic going in u-boot (which will be useful even if booted through boot0 + 1, to enable the nic-phy if nothing else). The A23 lichee u-boot has drivers for P2WI (used in sun6i) and RSB (reduced serial bus, used on A23): https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/p2wi https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/rsb And also PMIC drivers: https://github.com/wens/u-boot-sunxi/tree/lichee-dev-a23/drivers/power Judging from the code, my guess is AXP221 and AXP223 or differ in the type of interface supported. Hope this helps. :) And then see from there. Maybe I'll take a shot at this tonight, for now I'm going to spend some time with my family. Cheers, ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 7/7] ARM: sun7i: cubietruck: enable bluetooth module
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The Bluetooth
part is a BCM20710 device connected to UART2 in the A20 SoC.
The IC requires a 32.768 KHz low power clock input for proper
auto-detection of the main clock, and an enable signal via GPIO.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index cb25d3c..767c8e1 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -61,6 +61,13 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ bt_pwr_pin_cubietruck: bt_pwr_pin@0 {
+ allwinner,pins = PH18;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
uart0: serial@01c28000 {
@@ -69,6 +76,12 @@
status = okay;
};
+ uart2: serial@01c28800 {
+ pinctrl-names = default;
+ pinctrl-0 = uart2_pins_a;
+ status = okay;
+ };
+
i2c0: i2c@01c2ac00 {
pinctrl-names = default;
pinctrl-0 = i2c0_pins_a;
@@ -139,4 +152,16 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ rfkill_bt {
+ compatible = rfkill-gpio;
+ pinctrl-names = default;
+ pinctrl-0 = bt_pwr_pin_cubietruck, clk_out_a_pins_a;
+ clocks = clk_out_a;
+ clock-frequency = 32768;
+ gpios = pio 7 18 0; /* PH18 */
+ gpio-names = reset;
+ rfkill-name = bt;
+ rfkill-type = 2;
+ };
};
--
1.9.1
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[linux-sunxi] [PATCH 4/7] net: rfkill: gpio: fix reversed clock enable state
rfkill-gpio has clk_enabled = blocked, which is true when rfkill blocks the device. This results in calling clock enable/disable at the wrong time. Reversing the value fixes this. Signed-off-by: Chen-Yu Tsai w...@csie.org --- net/rfkill/rfkill-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c index 29ff07c..f46ddf7 100644 --- a/net/rfkill/rfkill-gpio.c +++ b/net/rfkill/rfkill-gpio.c @@ -57,7 +57,7 @@ static int rfkill_gpio_set_power(void *data, bool blocked) gpiod_set_value(rfkill-shutdown_gpio, 1); } - rfkill-clk_enabled = blocked; + rfkill-clk_enabled = !blocked; return 0; } -- 1.9.1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 6/7] net: rfkill: gpio: add clock-frequency device tree property
Some devices, such as Broadcom Bluetooth devices, require a specific
clock rate for the clock tied to the rfkill device. Add a clock-frequency
property so we can specify this from the device tree.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt | 2 ++
net/rfkill/rfkill-gpio.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
index a23da65..67b5edb 100644
--- a/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
+++ b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
@@ -11,6 +11,7 @@ Required properties:
Optional properties:
- clocks : phandle to clock to enable/disable
+- clock-frequency : desired clock rate for the given clock
Example:
@@ -21,4 +22,5 @@ Example:
gpios = pio 7 18 0;
gpio-names = reset;
clocks = clk_out_a;
+ clock-frequency = 32678;
};
diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c
index a174359..14ac8c1 100644
--- a/net/rfkill/rfkill-gpio.c
+++ b/net/rfkill/rfkill-gpio.c
@@ -38,6 +38,7 @@ struct rfkill_gpio_data {
struct rfkill *rfkill_dev;
struct clk *clk;
+ uint32_tclk_frequency;
boolclk_enabled;
};
@@ -90,6 +91,7 @@ static int rfkill_gpio_dt_probe(struct device *dev,
rfkill-name = np-name;
of_property_read_string(np, rfkill-name, rfkill-name);
of_property_read_u32(np, rfkill-type, rfkill-type);
+ of_property_read_u32(np, clock-frequency, rfkill-clk_frequency);
return 0;
}
@@ -122,6 +124,9 @@ static int rfkill_gpio_probe(struct platform_device *pdev)
rfkill-clk = devm_clk_get(pdev-dev, NULL);
+ if (!IS_ERR(rfkill-clk) rfkill-clk_frequency 0)
+ clk_set_rate(rfkill-clk, rfkill-clk_frequency);
+
gpio = devm_gpiod_get_index(pdev-dev, reset, 0);
if (!IS_ERR(gpio)) {
ret = gpiod_direction_output(gpio, 0);
--
1.9.1
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[linux-sunxi] [PATCH 5/7] net: rfkill: gpio: add device tree support
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/rfkill/rfkill-gpio.txt | 24 ++
net/rfkill/rfkill-gpio.c | 23 +
2 files changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
diff --git a/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
new file mode 100644
index 000..a23da65
--- /dev/null
+++ b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
@@ -0,0 +1,24 @@
+GPIO controlled RFKILL devices
+
+Required properties:
+- compatible : Must be rfkill-gpio.
+- rfkill-name : Name of RFKILL device
+- rfkill-type : Type of RFKILL device: 1 for WiFi, 2 for BlueTooth, etc.
+ See include/uapi/linux/rfkill.h for all valid values
+- gpios: At most two GPIO phandles
+- gpio-names : Shall be reset or shutdown, matching gpios.
+ If both are provided, the reset GPIO is toggled first.
+
+Optional properties:
+- clocks : phandle to clock to enable/disable
+
+Example:
+
+ rfkill_bt {
+ compatible = rfkill-gpio;
+ rfkill-name = bluetooth;
+ rfkill-type = 2;
+ gpios = pio 7 18 0;
+ gpio-names = reset;
+ clocks = clk_out_a;
+ };
diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c
index f46ddf7..a174359 100644
--- a/net/rfkill/rfkill-gpio.c
+++ b/net/rfkill/rfkill-gpio.c
@@ -26,6 +26,7 @@
#include linux/slab.h
#include linux/acpi.h
#include linux/gpio/consumer.h
+#include linux/of_gpio.h
#include linux/rfkill-gpio.h
@@ -81,6 +82,18 @@ static int rfkill_gpio_acpi_probe(struct device *dev,
return 0;
}
+static int rfkill_gpio_dt_probe(struct device *dev,
+ struct rfkill_gpio_data *rfkill)
+{
+ struct device_node * np = dev-of_node;
+
+ rfkill-name = np-name;
+ of_property_read_string(np, rfkill-name, rfkill-name);
+ of_property_read_u32(np, rfkill-type, rfkill-type);
+
+ return 0;
+}
+
static int rfkill_gpio_probe(struct platform_device *pdev)
{
struct rfkill_gpio_platform_data *pdata = pdev-dev.platform_data;
@@ -96,6 +109,10 @@ static int rfkill_gpio_probe(struct platform_device *pdev)
ret = rfkill_gpio_acpi_probe(pdev-dev, rfkill);
if (ret)
return ret;
+ } else if (pdev-dev.of_node) {
+ ret = rfkill_gpio_dt_probe(pdev-dev, rfkill);
+ if (ret)
+ return ret;
} else if (pdata) {
rfkill-name = pdata-name;
rfkill-type = pdata-type;
@@ -167,6 +184,11 @@ static const struct acpi_device_id rfkill_acpi_match[] = {
};
#endif
+static const struct of_device_id rfkill_of_match[] = {
+ { .compatible = rfkill-gpio, },
+ {},
+};
+
static struct platform_driver rfkill_gpio_driver = {
.probe = rfkill_gpio_probe,
.remove = rfkill_gpio_remove,
@@ -174,6 +196,7 @@ static struct platform_driver rfkill_gpio_driver = {
.name = rfkill_gpio,
.owner = THIS_MODULE,
.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
+ .of_match_table = of_match_ptr(rfkill_of_match),
},
};
--
1.9.1
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[linux-sunxi] [PATCH 1/7] gpiolib: gpiolib-of: Implement device tree gpio-names based lookup
This patch provides of_get_gpiod_flags_by_name(), which looks up GPIO
phandles by name only, through gpios/gpio-names, and not by index.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/gpio/gpiolib-of.c | 48 +++
include/linux/of_gpio.h | 3 +++
2 files changed, 51 insertions(+)
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 2024d45..5c586fa 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -97,6 +97,54 @@ struct gpio_desc *of_get_named_gpiod_flags(struct
device_node *np,
EXPORT_SYMBOL(of_get_named_gpiod_flags);
/**
+ * of_get_gpiod_flags_by_name() - Get a GPIO descriptor and flags by name
+ * @np:device node to get GPIO from
+ * @name: matching name of gpio phandle
+ * @flags: a flags pointer to fill in
+ *
+ * Returns GPIO descriptor to use with Linux GPIO API, or one of the errno
+ * value on the error condition. If @flags is not NULL the function also fills
+ * in flags for the GPIO.
+ */
+struct gpio_desc *of_get_gpiod_flags_by_name(struct device_node *np,
+ const char *name, enum of_gpio_flags *flags)
+{
+ /* Return -EPROBE_DEFER to support probe() functions to be called
+* later when the GPIO actually becomes available
+*/
+ struct gg_data gg_data = {
+ .flags = flags,
+ .out_gpio = ERR_PTR(-EPROBE_DEFER)
+ };
+ int index = 0;
+ int ret;
+
+ /* exit if no name given */
+ if (!name)
+ return ERR_PTR(-EINVAL);
+
+ /* .of_xlate might decide to not fill in the flags, so clear it. */
+ if (flags)
+ *flags = 0;
+
+ if (name)
+ index = of_property_match_string(np, gpio-names, name);
+
+ ret = of_parse_phandle_with_args(np, gpios, #gpio-cells, index,
+gg_data.gpiospec);
+
+ if (ret)
+ return ERR_PTR(ret);
+
+ gpiochip_find(gg_data, of_gpiochip_find_and_xlate);
+
+ of_node_put(gg_data.gpiospec.np);
+
+ return gg_data.out_gpio;
+}
+EXPORT_SYMBOL(of_get_gpiod_flags_by_names);
+
+/**
* of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
* @gc:pointer to the gpio_chip structure
* @np:device node of the GPIO chip
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index f14123a..134331f 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -51,6 +51,9 @@ static inline struct of_mm_gpio_chip
*to_of_mm_gpio_chip(struct gpio_chip *gc)
extern struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
const char *list_name, int index, enum of_gpio_flags *flags);
+extern struct gpio_desc *of_get_gpiod_flags_by_name(struct device_node *np,
+ const char *name, enum of_gpio_flags *flags);
+
extern int of_mm_gpiochip_add(struct device_node *np,
struct of_mm_gpio_chip *mm_gc);
--
1.9.1
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[linux-sunxi] [PATCH 0/7] net: rfkill: gpio: Add device tree support
Hi everyone, This patch series adds device tree support to rfkill-gpio, and fixes some issues I ran into. This is so we can define and control RF devices through the device tree, such as the Broadcom BCM20710 UART-based Bluetooth device found on the CubieTruck. The series is based on Heikki's rfkill-gpio cleanup patches [1], applied on 3.15-rc1. Kudos to Heikki for paving the way. [1] https://lkml.org/lkml/2014/4/1/451 The device tree bindings are much better than was defined in the RFC series I sent a few months earlier [2], due to cleanups by Heikki, and named gpios (via gpio-names) implemented in the first two patches. Hopefully this will satisfy everyone. [2] https://lkml.org/lkml/2014/1/17/31 The CubieTruck uses a non-default clock rate oscillator for the BCM20710 device. As the datasheet states, a precise 32.768 KHz low power clock must be provided at power on for the device to detect the correct clock rate of the main oscillator. Hence the need for the clock-frequency property. The first 2 patches should go through the gpio tree. The 4 rfkill-gpio patches should go through the same tree that Heikki's patches are in. Maxime, can you take the last one? A big thanks to everyone who gave reviews and suggestions. Changes since RFC: - Dropped gpio name buffer fix patch (not needed after cleanup patches) - New gpios/gpio-names support for device trees - Simplify device tree bindings due to name cleanup and gpio-names support Cheers ChenYu Chen-Yu Tsai (7): gpiolib: gpiolib-of: Implement device tree gpio-names based lookup gpiolib: Support purely name based gpiod lookup in device trees net: rfkill: gpio: use clk_prepare_enable/clk_disable_unprepare net: rfkill: gpio: fix reversed clock enable state net: rfkill: gpio: add device tree support net: rfkill: gpio: add clock-frequency device tree property ARM: sun7i: cubietruck: enable bluetooth module .../devicetree/bindings/rfkill/rfkill-gpio.txt | 26 arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 25 +++ drivers/gpio/gpiolib-of.c | 48 ++ drivers/gpio/gpiolib.c | 9 +++- include/linux/of_gpio.h| 3 ++ net/rfkill/rfkill-gpio.c | 34 +-- 6 files changed, 140 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt -- 1.9.1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: brcmfmac device tree support
On Mon, Apr 14, 2014 at 11:15 PM, Hans de Goede hdego...@redhat.com wrote: Hi Arend, On 04/11/2014 12:31 PM, Arend van Spriel wrote: Hi Hans, I have put some effort in adding device tree support in brcmfmac. Unfortunately, I had no luck getting MMC up and running on pandaboard extension header. So no way to test the patches. Would/could you be willing to do so. Unfortunately since 3.14 using brcmfmac with the wifi chip on the cubietruck is broken for me. I've spend some time debugging this this weekend, but no luck sofar. I'll keep trying and let you know when I've it working again. Maybe it's a timing issue? Try adding a start delay to the regulator? Once it works, I would be happy to try out device tree support and oob interrupts. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] sunxi-devel branch updated to 3.15-rc1
Hi Hans, On Mon, Apr 14, 2014 at 11:23 PM, Hans de Goede hdego...@redhat.com wrote: Hi All, I've just updated: https://github.com/linux-sunxi/linux-sunxi/commits/sunxi-devel to 3.15-rc1 This means that a whole lot of patches have been dropped as they have all been merged, hurray! The big next item on the to get merged list is the mmc code. I've posted new patches for rfkill-gpio and bluetooth on the Cubietruck. If you want to integrate them, you can find them here: https://github.com/wens/linux/tree/rfkill-gpio-dt My Cubieboard has some issues with mmc card detect since 3.14-rc6 sunxi-devel. That was when I got my hands on one, so it could have been there all along. See stack trace: https://gist.github.com/wens/10718744 Wonder if anyone else ran into this? Cheers ChenYu Note for this to work with more then 1 cpu core on sun7i you also need my sunxi-next u-boot branch: https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 7/7] ARM: sun7i: cubietruck: enable bluetooth module
On Tue, Apr 15, 2014 at 10:42 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Apr 15, 2014 at 02:41:41PM +0800, Chen-Yu Tsai wrote:
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The Bluetooth
part is a BCM20710 device connected to UART2 in the A20 SoC.
The IC requires a 32.768 KHz low power clock input for proper
auto-detection of the main clock, and an enable signal via GPIO.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index cb25d3c..767c8e1 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -61,6 +61,13 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ bt_pwr_pin_cubietruck: bt_pwr_pin@0 {
+ allwinner,pins = PH18;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
uart0: serial@01c28000 {
@@ -69,6 +76,12 @@
status = okay;
};
+ uart2: serial@01c28800 {
+ pinctrl-names = default;
+ pinctrl-0 = uart2_pins_a;
+ status = okay;
+ };
+
Please make this a separate patch.
Will do.
i2c0: i2c@01c2ac00 {
pinctrl-names = default;
pinctrl-0 = i2c0_pins_a;
@@ -139,4 +152,16 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ rfkill_bt {
+ compatible = rfkill-gpio;
+ pinctrl-names = default;
+ pinctrl-0 = bt_pwr_pin_cubietruck, clk_out_a_pins_a;
+ clocks = clk_out_a;
+ clock-frequency = 32768;
+ gpios = pio 7 18 0; /* PH18 */
+ gpio-names = reset;
+ rfkill-name = bt;
+ rfkill-type = 2;
+ };
Hmmm, I don't think that's actually right.
If you have such a device, then I'd expect it to be represented as a
full device in the DT, probably with one part for the WiFi, one part
for the Bluetooth, and here the definition of the rfkill device that
controls it.
The AP6210 is not one device, but 2 separate chips in one module. Each
chip has its own controls and interface. They just so happen to share
the same enclosure. Even 2-in-1 chips by Broadcom have separate controls
and interfaces. The WiFi side is most likely connected via SDIO, while
the Bluetooth side is connected to a UART, and optionally I2S for sound.
But tying parts of the device to the rfkill that controls it, such as
the clocks, or the frequency it runs at seems just wrong.
I understand where you're coming from. For devices on buses that require
drivers (such as USB, SDIO) these properties probably should be tied to
the device node.
For our use case here, which is a bluetooth chip connected on the UART,
there is no in kernel representation or driver to tie them to. Same goes
for UART based GPS chips. They just so happen to require toggling a GPIO,
and maybe enabling a specific clock, to get it running. Afterwards,
accessing it is done solely from userspace. For our Broadcom chips, the
user has to upload its firmware first, then designate the tty as a Bluetooth
HCI using hciattach.
We are using the rfkill device as a on-off switch.
Hope this explains the situation.
Cheers
ChenYu
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[linux-sunxi] Re: [PATCH 1/7] gpiolib: gpiolib-of: Implement device tree gpio-names based lookup
Hi, On Wed, Apr 16, 2014 at 3:06 PM, Alexandre Courbot gnu...@gmail.com wrote: On Wed, Apr 16, 2014 at 3:12 PM, Alexandre Courbot gnu...@gmail.com wrote: On Tue, Apr 15, 2014 at 11:20 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: Hi Chen-Yu, On Tue, Apr 15, 2014 at 02:41:35PM +0800, Chen-Yu Tsai wrote: This patch provides of_get_gpiod_flags_by_name(), which looks up GPIO phandles by name only, through gpios/gpio-names, and not by index. IIRC, gpios only uses the *-gpios properties, and not gpios/gpio-names pattern seen on various other things. Is it some new property you introduce? If so, please add it to the documentation. Now, I'm not sure that having two distinct representations of GPIOs in the DT is a good thing. Yes, it's looking odd compared to other similar bindings, but it's what we have to deal with. Mmmm I *think* I somehow remember a discussion about this topic recently, but I cannot find it. Maybe Chen-yu could point us to the conclusion of this discussion and the rationale for (re)implementing named GPIOs this way? Aha, here maybe: https://lkml.org/lkml/2014/1/21/164 They're also mentioned in: https://lkml.org/lkml/2014/2/25/581 However I don't see a clear conclusion that we should implement that scheme. Not that I am strongly against it, but I'd like to see a practical purpose for it. Again no clear conclusion on this. I wrote this as it was one possible way out of the index-based GPIO stuff. Hopefully others will chime in and we can decide whether this is what we want or not. Cheers ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 7/7] ARM: sun7i: cubietruck: enable bluetooth module
Hi,
On Wed, Apr 16, 2014 at 5:44 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
Please try to keep me in CC, even though the ML doesn't make it easy..
Sorry about that.
On Wed, Apr 16, 2014 at 12:06:59AM +0800, Chen-Yu Tsai wrote:
@@ -139,4 +152,16 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ rfkill_bt {
+ compatible = rfkill-gpio;
+ pinctrl-names = default;
+ pinctrl-0 = bt_pwr_pin_cubietruck, clk_out_a_pins_a;
+ clocks = clk_out_a;
+ clock-frequency = 32768;
+ gpios = pio 7 18 0; /* PH18 */
+ gpio-names = reset;
+ rfkill-name = bt;
+ rfkill-type = 2;
+ };
Hmmm, I don't think that's actually right.
If you have such a device, then I'd expect it to be represented as a
full device in the DT, probably with one part for the WiFi, one part
for the Bluetooth, and here the definition of the rfkill device that
controls it.
The AP6210 is not one device, but 2 separate chips in one module. Each
chip has its own controls and interface. They just so happen to share
the same enclosure. Even 2-in-1 chips by Broadcom have separate controls
and interfaces. The WiFi side is most likely connected via SDIO, while
the Bluetooth side is connected to a UART, and optionally I2S for sound.
It's even easier to represent then.
But tying parts of the device to the rfkill that controls it, such as
the clocks, or the frequency it runs at seems just wrong.
I understand where you're coming from. For devices on buses that require
drivers (such as USB, SDIO) these properties probably should be tied to
the device node.
For our use case here, which is a bluetooth chip connected on the UART,
there is no in kernel representation or driver to tie them to. Same goes
for UART based GPS chips. They just so happen to require toggling a GPIO,
and maybe enabling a specific clock, to get it running. Afterwards,
accessing it is done solely from userspace. For our Broadcom chips, the
user has to upload its firmware first, then designate the tty as a Bluetooth
HCI using hciattach.
We are using the rfkill device as a on-off switch.
I understand your point, but the fact that it's implemented in
user-space, or that UART is not a bus (which probably should be), is
only a Linux specific story, and how it's implemented in Linux (even
if the whole rfkill node is another one, but let's stay on topic).
I gave it some thought last night. You are right. My whole approach
is wrong. But let's try to make it right.
So considering the fact that it's primarily connected to a UART,
maybe I should make it a sub-node to the UART node it's actually
connected to? Something like:
uart2: serial@01c28800 {
pinctrl-names = default;
pinctrl-0 = uart2_pins_a;
status = okay;
bt: bt_hci {
compatible = brcm,bcm20710;
/* maybe add some generic compatible */
pinctrl-names = default;
pinctrl-0 = clk_out_a_pins_a,
bt_pwr_pin_cubietruck;
clocks = clk_out_a;
clock-frequency = 32768;
gpios = pio 7 18 0; /* PH18 */
};
};
And let the uart core handle power sequencing for sub-nodes.
The rfkill node would still have the gpios and clocks, but not the
clock-frequency property. It's sole purpose would be to toggle the
controls. But I think the placement is still odd. Perhaps these
virtual devices shouldn't live in the DT at all.
This is a huge abstraction leak.
Let's say you need the I2S stream you mentionned for some
reason. Would you tie the audio stream to the rfkill node as well?
I'm sorry, but from an hardware description perspective, it makes no
sense.
The above revision should be better, from a hardware perspective. I'm
not sure how to tie in the I2S stream, and there I haven't found any
examples in the DT tree.
What's the feeling of the DT maintainers?
Cheers
ChenYu
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Re: [linux-sunxi] [PATCH] sunxi: remove magic numbers from clock_get_pll{5,6}
Hi,
On Tue, Apr 15, 2014 at 3:46 AM, Ian Campbell i...@hellion.org.uk wrote:
For clock_get_pll5 just remove it since it is unused.
For clock_get_pll6 introduce the necessary #defines.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock.c | 18 ++
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 5 +
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +
3 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c
b/arch/arm/cpu/armv7/sunxi/clock.c
index c07a975..94ba6e0 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -24,26 +24,12 @@ int clock_init(void)
return 0;
}
-/* Return PLL5 frequency in Hz
- * Note: Assumes PLL5 reference is 24MHz clock
- */
-unsigned int clock_get_pll5(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(ccm-pll5_cfg);
- int n = (rval 8) 0x1f;
- int k = ((rval 4) 3) + 1;
- int p = 1 ((rval 16) 3);
- return 2400 * n * k / p;
-}
-
You should remove the declaration for clock_get_pll5 from
arch/arm/include/asm/arch-sunxi/clock.h
as well, to be complete.
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
uint32_t rval = readl(ccm-pll6_cfg);
- int n = (rval 8) 0x1f;
- int k = ((rval 4) 3) + 1;
+ int n = (rval CCM_PLL6_CTRL_N_MASK) CCM_PLL6_CTRL_N_SHIFT;
+ int k = ((rval CCM_PLL6_CTRL_K_MASK) CCM_PLL6_CTRL_K_SHIFT) + 1;
return 2400 * n * k / 2;
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 85ae8d7..8e37075 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -209,6 +209,11 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_BYPASS (0x1 30)
#define CCM_PLL5_CTRL_EN (0x1 31)
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1fCCM_PLL6_CTRL_N_SHIFT)
Maybe a space separation between the operands for readability?
Same for the other places.
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3CCM_PLL6_CTRL_K_SHIFT)
+
#define CCM_GPS_CTRL_RESET (0x1 0)
#define CCM_GPS_CTRL_GATE (0x1 1)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d4ddd1f..382f296 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -174,6 +174,11 @@ struct sunxi_ccm_reg {
#define PLL6_CFG_DEFAULT 0x90041911
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1fCCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3CCM_PLL6_CTRL_K_SHIFT)
+
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
Looks good otherwise.
Cheers
ChenYu
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[linux-sunxi] [PATCH] fel: Add A23 SoC ID
Signed-off-by: Chen-Yu Tsai w...@csie.org --- fel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fel.c b/fel.c index ba4212c..97f265e 100644 --- a/fel.c +++ b/fel.c @@ -166,6 +166,7 @@ void aw_fel_get_version(libusb_device_handle *usb) case 0x1625: soc_name=A13;break; case 0x1633: soc_name=A31;break; case 0x1651: soc_name=A20;break; + case 0x1650: soc_name=A23;break; } printf(%.8s soc=%08x(%s) %08x ver=%04x %02x %02x scratchpad=%08x %08x %08x\n, buf.signature, buf.soc_id, soc_name, buf.unknown_0a, buf.protocol, buf.unknown_12, buf.unknown_13, buf.scratchpad, buf.pad[0], buf.pad[1]); -- 1.9.1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot-sunxi 4/7] ARM: sunxi: Allow specifying module in prcm apb0 init function
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/p2wi.c| 2 +-
arch/arm/cpu/armv7/sunxi/prcm.c| 14 ++
arch/arm/include/asm/arch-sunxi/prcm.h | 2 +-
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
index 343fa0b..469c7e0 100644
--- a/arch/arm/cpu/armv7/sunxi/p2wi.c
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -29,7 +29,7 @@ void p2wi_init(void)
struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
/* Enable p2wi and PIO clk, and de-assert their resets */
- prcm_init_apb0();
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
index 8f9bea9..783d4b6 100644
--- a/arch/arm/cpu/armv7/sunxi/prcm.c
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -21,17 +21,15 @@
#include asm/arch/prcm.h
#include asm/arch/sys_proto.h
-void prcm_init_apb0(void)
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
{
struct sunxi_prcm_reg *prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- u32 reg_val;
- reg_val = readl(prcm-apb0_gate);
- reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
- writel(reg_val, prcm-apb0_gate);
+ /* open the clock for module */
+ setbits_le32(prcm-apb0_gate, flags);
- reg_val = readl(prcm-apb0_reset);
- reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
- writel(reg_val, prcm-apb0_reset);
+ /* deassert reset for module */
+ setbits_le32(prcm-apb0_reset, flags);
}
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h
b/arch/arm/include/asm/arch-sunxi/prcm.h
index 85af1f8..df833d7 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -233,6 +233,6 @@ struct sunxi_prcm_reg {
u32 dram_tst; /* 0x190 */
};
-void prcm_init_apb0(void);
+void prcm_apb0_enable(u32 flags);
#endif /* __ASSEMBLY__ */
#endif /* _PRCM_H */
--
2.0.0.rc0
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[linux-sunxi] [PATCH u-boot-sunxi 1/7] ARM: sunxi: Fix sun6i PLL6 default to 600MHz
The original default may have been miscalculated as it was for 624MHz.
The A23 user manual states that PLL6 should be fixed to 600MHz, and
not any other rate.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index c524c29..1861673 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -172,7 +172,7 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0x90011b21
-#define PLL6_CFG_DEFAULT 0x90041911
+#define PLL6_CFG_DEFAULT 0x90041811
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f CCM_PLL6_CTRL_N_SHIFT)
--
2.0.0.rc0
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[linux-sunxi] [PATCH u-boot-sunxi 0/7] ARM: sunxi: Add basic A23 support
Hi everyone, This series adds basic support for A23 based devices. Most of the code is shared with sun6i. DRAM initialization and RSB (reduced serial bus) for the AXP223 found on these devices are still missing, so no SPL. The first patch fixes the default PLL6 clock rate for sun6i. Hans, this might make MMC on sun6i work. The second and third patches cleanup some of the sun6i clock code. The fourth patch adds a function parameter to prcm apb0 enabling code, so we can reuse it for R_UART. The fifth patch actually adds A23 support, which will work over FEL mode, using a micro-SD breakout for the console. The six patch adds support for the R_UART, which is the unused UART found on Ippo-q8h, as the console. The last patch adds build settings for Ippo-q8h. The series can also be found here: https://github.com/wens/u-boot-sunxi/tree/sunxi-a23 I have tested this over FEL mode. To do so, you must get boot0 for FEL mode from the A23 SDK, and update the blob with the correct DRAM settings using Allwinner's tools. MMC works when I insert a card in. In theory boot0 for MMC should work, though I have been unable to get any response out of my device. I have not tried booting anything, as there is nothing to boot at the moment. Cheers ChenYu Chen-Yu Tsai (7): ARM: sunxi: Fix sun6i PLL6 default to 600MHz ARM: sunxi: Fix macro names for mmc and uart reset offsets ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions ARM: sunxi: Allow specifying module in prcm apb0 init function ARM: sunxi: Add basic A23 support ARM: sunxi: Add support for using R_UART as console ARM: sunxi: Add A23 based tablet Ippo-q8h arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 6 +- arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 9 +++-- arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/cpu/armv7/sunxi/early_print.c| 6 ++ arch/arm/cpu/armv7/sunxi/p2wi.c | 2 +- arch/arm/cpu/armv7/sunxi/prcm.c | 14 ++ arch/arm/include/asm/arch-sunxi/clock.h | 2 +- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 21 +++- arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h| 9 + arch/arm/include/asm/arch-sunxi/prcm.h| 2 +- board/sunxi/board.c | 6 +++--- boards.cfg| 1 + drivers/mmc/sunxi_mmc.c | 13 + include/configs/sun8i.h | 28 +++ include/configs/sunxi-common.h| 1 + 17 files changed, 91 insertions(+), 34 deletions(-) create mode 100644 include/configs/sun8i.h -- 2.0.0.rc0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot-sunxi 3/7] ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 88b1d1f..1397b35 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -86,7 +86,7 @@ struct sunxi_ccm_reg {
u32 ps_clk_cfg; /* 0x154 PS module clock */
u32 mtc_clk_cfg;/* 0x158 MTC module clock */
u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
- u32 mbus1_clk_cfg; /* 0x160 MBUS0 module clock */
+ u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
u32 reserved16;
u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
--
2.0.0.rc0
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[linux-sunxi] [PATCH u-boot-sunxi 7/7] ARM: sunxi: Add A23 based tablet Ippo-q8h
The Ippo-q8h is the first A23 based device spotted in the wild. This was used to bring basic support to u-boot. Add build options for it Signed-off-by: Chen-Yu Tsai w...@csie.org --- boards.cfg | 1 + 1 file changed, 1 insertion(+) diff --git a/boards.cfg b/boards.cfg index b3a1494..d3a1e50 100644 --- a/boards.cfg +++ b/boards.cfg @@ -392,6 +392,7 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Iteaduino_Plus_A10 sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi Iteaduino_Plus_A20 sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi Colombus sun6i:COLOMBUS,AXP221_POWER,ENABLE_DLDO1_POWER - +Active arm armv7 sunxi - sunxi Ippo_q8h sun8i:IPPO_Q8H,NO_AXP,CONS_INDEX=5 - Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS - Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS - -- 2.0.0.rc0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot-sunxi 6/7] ARM: sunxi: Add support for using R_UART as console
The R_UART is the only uart other than UART0 on port F which has
usable pads for attaching a console. Support it so we can still
have a console when using MMC on port F.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 5 +
arch/arm/cpu/armv7/sunxi/early_print.c | 6 ++
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
include/configs/sunxi-common.h | 1 +
6 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 4090d3d..88191a4 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -74,6 +74,10 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+#elif CONFIG_CONS_INDEX == 5 defined(CONFIG_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), 1);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index c27d1ff..61a38bf 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -57,6 +57,7 @@ void clock_init_uart(void)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if CONFIG_CONS_INDEX 5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
@@ -70,6 +71,10 @@ void clock_init_uart(void)
/* deassert uart reset */
setbits_le32(ccm-apb2_reset_cfg,
1 (APB2_RESET_UART_SHIFT+CONFIG_CONS_INDEX-1));
+#else
+ /* enable R_PIO and R_UART clocks, and de-assert resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg);
diff --git a/arch/arm/cpu/armv7/sunxi/early_print.c
b/arch/arm/cpu/armv7/sunxi/early_print.c
index da9aa09..d92b780 100644
--- a/arch/arm/cpu/armv7/sunxi/early_print.c
+++ b/arch/arm/cpu/armv7/sunxi/early_print.c
@@ -17,7 +17,13 @@
static int uart_initialized = 0;
+#if CONFIG_CONS_INDEX 5
#define UART CONFIG_CONS_INDEX-1
+#else
+/* SUNXI_R_UART_BASE */
+#define UART 2922
+#endif
+
void uart_init(void) {
/* select dll dlh */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index c14cf8e..9285181 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -111,6 +111,7 @@
#define SUNXI_AVG_BASE 0x01ea
#define SUNXI_PRCM_BASE0x01f01400
+#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUNXI_P2WI_BASE0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 1d0c6cb..46a111e 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -161,6 +161,9 @@ enum sunxi_gpio_number {
#define SUNXI_GPL0_R_P2WI_SCK 3
#define SUNXI_GPL1_R_P2WI_SDA 3
+#define SUN8I_GPL2_R_UART_TX 2
+#define SUN8I_GPL3_R_UART_RX 2
+
int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 397070a..2adaec0 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -43,6 +43,7 @@
#define CONFIG_SYS_NS16550_COM2SUNXI_UART1_BASE
#define CONFIG_SYS_NS16550_COM3SUNXI_UART2_BASE
#define CONFIG_SYS_NS16550_COM4SUNXI_UART3_BASE
+#define CONFIG_SYS_NS16550_COM5SUNXI_R_UART_BASE
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x4000
--
2.0.0.rc0
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[linux-sunxi] Re: [U-Boot] [PATCH v3 9/9] net/designware: Reduce DMA burst length
On Sun, Apr 27, 2014 at 11:25 PM, Ian Campbell i...@hellion.org.uk wrote: On Sat, 2014-04-26 at 20:28 +0200, Marek Vasut wrote: On Friday, April 18, 2014 at 08:05:50 PM, Ian Campbell wrote: From: Jens Kuske jensku...@gmail.com The GMAC module in Allwinner sunxi SoCs seems to have problems with burst lengths 8. Is there any explanation for the problems please ? Jens or Wens, can you answer this? IIRC, with burst lengths 8, GMAC doesn't work, no ping, no DHCP. I don't remember if it was TX or RX that suffered, or even both. Hope this clarifies things a bit. ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [U-Boot] [PATCH v3 9/9] net/designware: Reduce DMA burst length
On Mon, Apr 28, 2014 at 2:08 AM, Marek Vasut ma...@denx.de wrote: On Sunday, April 27, 2014 at 05:29:29 PM, Chen-Yu Tsai wrote: On Sun, Apr 27, 2014 at 11:25 PM, Ian Campbell i...@hellion.org.uk wrote: On Sat, 2014-04-26 at 20:28 +0200, Marek Vasut wrote: On Friday, April 18, 2014 at 08:05:50 PM, Ian Campbell wrote: From: Jens Kuske jensku...@gmail.com The GMAC module in Allwinner sunxi SoCs seems to have problems with burst lengths 8. Is there any explanation for the problems please ? Jens or Wens, can you answer this? IIRC, with burst lengths 8, GMAC doesn't work, no ping, no DHCP. I don't remember if it was TX or RX that suffered, or even both. Hope this clarifies things a bit. No, it does not at all, sorry. What you describe are symptoms, but what I want to know is what is the root cause of those symptoms. You did not explain that. I can not offer much more explanation. The value was hardcoded in Allwinner's code. The datasheets don't offer much, except this line might be related: (DMA) Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each descriptor can transfer up to 4 KB data. Also probably related: 4KB TX FIFO for transmission packets and 16KB RX FIFO for reception packets. I'm not an expert in hardware. We could ask Allwinner, but given past inquiries from the linux-sunxi community, I'd say getting a reply on hardware specifics is unlikely to happen. So my guess is that this is limited by the DWMAC IP Allwinner licensed from Synopsys. Cheers ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 5/7] clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
Hi,
On Mon, Apr 28, 2014 at 10:58 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0 clk and gates: used to clk
Add support for these clks in a separate driver so that they can be probed
as platform devices instead of registered during early init.
We need this to be able to probe PRCM MFD subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/clk/sunxi/Makefile | 2 +
drivers/clk/sunxi/clk-sun6i-prcm.c | 253
+
2 files changed, 255 insertions(+)
create mode 100644 drivers/clk/sunxi/clk-sun6i-prcm.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index b5bac91..ef8cdc9 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -3,3 +3,5 @@
#
obj-y += clk-sunxi.o clk-factors.o
+
+obj-$(CONFIG_MFD_SUN6I_PRCM) += clk-sun6i-prcm.o
diff --git a/drivers/clk/sunxi/clk-sun6i-prcm.c
b/drivers/clk/sunxi/clk-sun6i-prcm.c
new file mode 100644
index 000..bb7b25a
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun6i-prcm.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2014 Free Electrons
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Boris BREZILLON boris.brezil...@free-electrons.com
+ *
+ * Allwinner PRCM (Power/Reset/Clock Management) driver
+ *
+ */
+
+#include linux/clk-provider.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+
+#define SUN6I_APB0_GATES_MAX_SIZE 32
+#define SUN6I_AR100_MAX_PARENTS4
+
+static int sun6i_a31_ar100_mux_clk_register(struct platform_device *pdev)
+{
+ const char *parents[SUN6I_AR100_MAX_PARENTS];
+ struct device_node *np = pdev-dev.of_node;
+ const char *clk_name = np-name;
+ struct resource *r;
+ void __iomem *reg;
+ struct clk *clk;
+ int nparents;
+ int i;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap(pdev-dev, r-start, resource_size(r));
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ nparents = of_clk_get_parent_count(np);
+ if (nparents SUN6I_AR100_MAX_PARENTS)
+ nparents = SUN6I_AR100_MAX_PARENTS;
+
+ for (i = 0; i nparents; i++)
+ parents[i] = of_clk_get_parent_name(np, i);
+
+ of_property_read_string(np, clock-output-names, clk_name);
+
+ clk = clk_register_mux(pdev-dev, clk_name, parents, nparents,
+ CLK_SET_RATE_NO_REPARENT, reg,
+ 16, 2, 0, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static int sun6i_a31_ar100_clk_register(struct platform_device *pdev)
+{
+ struct device_node *np = pdev-dev.of_node;
+ const char *clk_name = np-name;
+ const char *clk_parent;
+ struct resource *r;
+ void __iomem *reg;
+ struct clk *clk;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap(pdev-dev, r-start, resource_size(r));
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ clk_parent = of_clk_get_parent_name(np, 0);
+ if (!clk_parent)
+ return -EINVAL;
+
+ of_property_read_string(np, clock-output-names, clk_name);
+
+ clk = clk_register_divider(pdev-dev, clk_name, clk_parent,
+ 0, reg, 4, 2, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static int sun6i_a31_ar100_div_clk_register(struct platform_device *pdev)
+{
+ struct device_node *np = pdev-dev.of_node;
+ const char *clk_name = np-name;
+ const char *clk_parent;
+ struct resource *r;
+ void __iomem *reg;
+ struct clk *clk;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap(pdev-dev, r-start, resource_size(r));
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ clk_parent = of_clk_get_parent_name(np, 0);
+ if (!clk_parent)
+ return -EINVAL;
+
+ of_property_read_string(np, clock-output-names, clk_name);
+
+ clk = clk_register_divider(pdev-dev, clk_name, clk_parent,
+ 0, reg, 8, 5, 0, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
Would it be possible to merge the 3 ar100 clocks into 1 composite clock?
They do share the same register, and
[linux-sunxi] Re: [PATCH 7/7] ARM: sunxi: dt: add PRCM clk and reset controller subdevices
Hi,
On Mon, Apr 28, 2014 at 10:58 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 49
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
b/arch/arm/boot/dts/sun6i-a31.dtsi
index ec3253a..83a1634 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -501,6 +501,55 @@
prcm@01f01c00 {
Seems the address here was wrong to start with.
compatible = allwinner,sun6i-a31-prcm;
reg = 0x01f01400 0x200;
+
+ ar100_mux: ar100_mux {
Might we use clk@01f01XXX for the names of the clock nodes?
+ compatible =
allwinner,sun6i-a31-ar100-mux-clk;
+ #clock-cells = 0;
+ clocks = osc32k, osc24M, pll6,
pll6;
+ };
+
+ ar100: ar100 {
+ compatible = allwinner,sun6i-a31-ar100-clk;
+ #clock-cells = 0;
+ clocks = ar100_mux;
+ };
+
+ ar100_div: ar100_div {
+ compatible =
allwinner,sun6i-a31-ar100-div-clk;
+ #clock-cells = 0;
+ clocks = ar100;
+ };
+
+ ahb0: ahb0 {
+ compatible = fixed-factor-clock;
+ #clock-cells = 0;
+ clock-div = 1;
+ clock-mult = 1;
+ clocks = ar100_div;
+ clock-output-names = ahb0;
+ };
+
+ apb0: apb0 {
+ compatible = allwinner,sun6i-a31-apb0-clk;
+ #clock-cells = 0;
+ clocks = ahb0;
+ clock-output-names = apb0;
+ };
+
+ apb0_gates: apb0_gates {
+ compatible =
allwinner,sun6i-a31-apb0-gates-clk;
+ #clock-cells = 1;
+ clocks = apb0;
+ clock-output-names = apb0_pio, apb0_ir,
+ apb0_timer01, apb0_p2wi,
+ apb0_uart, apb0_1wire,
+ apb0_i2c;
+ };
+
+ apb0_rst: apb0_rst {
Also use reset@01f01XXX here?
+ compatible =
allwinner,sun6i-a31-clock-reset;
+ #reset-cells = 1;
+ };
};
};
};
Thanks!
ChenYu
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[linux-sunxi] Re: [PATCH u-boot-sunxi 1/7] ARM: sunxi: Fix sun6i PLL6 default to 600MHz
On Sun, Apr 27, 2014 at 1:54 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 04/24/2014 06:39 PM, Chen-Yu Tsai wrote:
The original default may have been miscalculated as it was for 624MHz.
The A23 user manual states that PLL6 should be fixed to 600MHz, and
not any other rate.
Good catch, the problem is that the N factor on sun4i / sun5i / sun7i is 0-31,
where as on sun6i it is 1-32. This means that clock_get_pll6() also need to
be adjusted.
I've added an updated patch to my local tree which also fixes
clock_get_pll6().
Looks good. Nice of you to align the n and k lines as well.
Thanks
ChenYu
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index c524c29..1861673 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -172,7 +172,7 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0x90011b21
-#define PLL6_CFG_DEFAULT 0x90041911
+#define PLL6_CFG_DEFAULT 0x90041811
#define CCM_PLL6_CTRL_N_SHIFT8
#define CCM_PLL6_CTRL_N_MASK (0x1f CCM_PLL6_CTRL_N_SHIFT)
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[linux-sunxi] Re: [PATCH 7/7] ARM: sunxi: dt: add PRCM clk and reset controller subdevices
On Tue, Apr 29, 2014 at 1:27 AM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
On 28/04/2014 18:02, Chen-Yu Tsai wrote:
Hi,
On Mon, Apr 28, 2014 at 10:58 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 49
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
b/arch/arm/boot/dts/sun6i-a31.dtsi
index ec3253a..83a1634 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -501,6 +501,55 @@
prcm@01f01c00 {
Seems the address here was wrong to start with.
Absolutely, I'll fix it.
compatible = allwinner,sun6i-a31-prcm;
reg = 0x01f01400 0x200;
+
+ ar100_mux: ar100_mux {
Might we use clk@01f01XXX for the names of the clock nodes?
Actually, I had a discussion with Maxime, and we decided to remove the
address suffix because the PRCM block is not a bus, and thus should not
have child node with addresses.
But I'm not a DT binding expert (it might be acceptable to define child
nodes with addresses even when the parent is not a bus :-)).
Advices from DT maintainers on that specific point would be great.
Then I would suggest using a _clk suffix in the name, so at least we can
tell what type of device it is. That might be enough to satisfy ePAPR.
At least socfpga, omap54xx, omap44xx are doing it this way.
+ compatible =
allwinner,sun6i-a31-ar100-mux-clk;
+ #clock-cells = 0;
+ clocks = osc32k, osc24M, pll6,
pll6;
+ };
+
+ ar100: ar100 {
+ compatible =
allwinner,sun6i-a31-ar100-clk;
+ #clock-cells = 0;
+ clocks = ar100_mux;
+ };
+
+ ar100_div: ar100_div {
+ compatible =
allwinner,sun6i-a31-ar100-div-clk;
+ #clock-cells = 0;
+ clocks = ar100;
+ };
+
+ ahb0: ahb0 {
+ compatible = fixed-factor-clock;
+ #clock-cells = 0;
+ clock-div = 1;
+ clock-mult = 1;
+ clocks = ar100_div;
+ clock-output-names = ahb0;
+ };
+
+ apb0: apb0 {
+ compatible = allwinner,sun6i-a31-apb0-clk;
+ #clock-cells = 0;
+ clocks = ahb0;
+ clock-output-names = apb0;
+ };
+
+ apb0_gates: apb0_gates {
+ compatible =
allwinner,sun6i-a31-apb0-gates-clk;
+ #clock-cells = 1;
+ clocks = apb0;
+ clock-output-names = apb0_pio, apb0_ir,
+ apb0_timer01, apb0_p2wi,
+ apb0_uart, apb0_1wire,
+ apb0_i2c;
+ };
+
+ apb0_rst: apb0_rst {
Also use reset@01f01XXX here?
+ compatible =
allwinner,sun6i-a31-clock-reset;
+ #reset-cells = 1;
+ };
};
};
};
Thanks!
ChenYu
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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[linux-sunxi] Re: [PATCH v10 15/15] ARM: dts: sun7i: Add basic support for the Cubietruck WiFi module
On Mon, May 5, 2014 at 12:02 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: On Fri, May 02, 2014 at 05:57:29PM +0200, Hans de Goede wrote: From: Chen-Yu Tsai w...@csie.org The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The WiFi part is a BCM43362 IC connected to MMC3 in the A20 SoC via SDIO. The IC also takes a power enable signal via GPIO. The WiFi module supports out-of-band interrupt signaling via GPIO, but this is not supported in this patch. Signed-off-by: Hans de Goede hdego...@redhat.com It doesn't have Chen-Yu SoB. Chen-Yu, are you fine with adding it? My apologies, I didn't notice this patch still had my name on it. Looks good. Signed-off-by: Chen-Yu Tsai w...@csie.org (or Acked-by, not sure which applies in this situation.) No need to respin the set, I'll add it when applying if it's ok. Thanks! Cheers, ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 0/2] ARM: sunxi: Enable syscon for the system controller
Hi, On Tue, May 6, 2014 at 6:55 AM, Maxime Ripard maxime.rip...@free-electrons.com wrote: On Sun, May 04, 2014 at 04:02:38PM +0200, Carlo Caione wrote: The so called system controller in Allwinner A20 and A31 SoCs is multi-purpose controller that tries to add misc functionality to one memory region. In these SoCs it controls the internal SRAM partitioning but it also includes registers for chip versioning and NMI control. This patch adds the proper nodes in the DTS files and enable the syscon in the defconfig files. Even though the system controller includes also register for managing the NMI controller, these register are not mapped in the syscon since they are directly used and mapped by the NMI controller itself. Hmmm, what exactly do you want to achieve with this? The NMI controller won't be able to use it, since it's initialized much earlier than syscon and regmap. I believe this will be used for toggling the SRAM mappings. (Am I right?) The second register toggles mappings for MUSB FIFO, EMAC, and a few of the other IP blocks we currently don't support. Moreover, the A31 doesn't seem to have this system controller, or at least this overlap. There should be something similar, as does the A23. There is no overlap AFAIK. And since on the A20, registers seem to have one usage only, so I guess we can just split this IP into several nodes, just like we did with the NMI. As stated above, the second register toggles SRAM mappings for at most 4 SRAM blocks (for EMAC, MUSB, ACE, ISP). syscon would be a good way to share this register among the various drivers. We do not toggle it in the current EMAC driver. The driver seems to assume it is setup by the bootloader, and on the A20, it seems to be mapped to EMAC by default. The MUSB glue layer driver must toggle this. I think this approach is better than all the individual drivers mapping the registers and toggling a single bit. In fact I did something similar when working on preliminary musb support. Cheers ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v2 7/7] ARM: sunxi: dt: add PRCM clk and reset controller subdevices
On Thu, May 8, 2014 at 11:17 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, May 07, 2014 at 07:25:54PM +0200, Boris BREZILLON wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 39
++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
b/arch/arm/boot/dts/sun6i-a31.dtsi
index ec3253a..b69be0b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -498,9 +498,46 @@
reg = 0x01f01c00 0x300;
};
- prcm@01f01c00 {
+ prcm@01f01400 {
This has already been fixed by Hans.
compatible = allwinner,sun6i-a31-prcm;
reg = 0x01f01400 0x200;
+
+ ar100: ar100_clk {
+ compatible = allwinner,sun6i-a31-ar100-clk;
+ #clock-cells = 0;
+ clocks = osc32k, osc24M, pll6,
pll6;
+ };
+
+ ahb0: ahb0_clk {
+ compatible = fixed-factor-clock;
+ #clock-cells = 0;
+ clock-div = 1;
+ clock-mult = 1;
+ clocks = ar100;
+ clock-output-names = ahb0;
+ };
+
+ apb0: apb0_clk {
+ compatible = allwinner,sun6i-a31-apb0-clk;
+ #clock-cells = 0;
+ clocks = ahb0;
+ clock-output-names = apb0;
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible =
allwinner,sun6i-a31-apb0-gates-clk;
+ #clock-cells = 1;
+ clocks = apb0;
+ clock-output-names = apb0_pio, apb0_ir,
+ apb0_timer01, apb0_p2wi,
timer01 ? is this a typo?
A23 manual lists the clock gate as r_timer0_1, so I put the name on the wiki.
Allwinner sun6i code uses r_tmr or just tmr. I see no problem naming this
clock output as apb0_timer though.
+ apb0_uart, apb0_1wire,
+ apb0_i2c;
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = allwinner,sun6i-a31-clock-reset;
+ #reset-cells = 1;
+ };
};
};
};
--
1.8.3.2
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Re: [linux-sunxi] [PATCH 1/1] a20: add LinkSprite pcDuino3 FEX file
On Sun, May 11, 2014 at 9:48 PM, Zoltan HERPAI wigy...@uid0.hu wrote: File taken from vendor site, original comments cleaned up. Signed-off-by: Zoltan HERPAI wigy...@uid0.hu --- sys_config/a20/linksprite_pcduino3.fex | 1066 1 file changed, 1066 insertions(+) create mode 100644 sys_config/a20/linksprite_pcduino3.fex diff --git a/sys_config/a20/linksprite_pcduino3.fex b/sys_config/a20/linksprite_pcduino3.fex new file mode 100644 index 000..f0f3f13 --- /dev/null +++ b/sys_config/a20/linksprite_pcduino3.fex @@ -0,0 +1,1066 @@ +[product] +version = 100 +machine = pcduino3-v10 + +[platform] +eraseflag = 1 + +[target] +boot_clock = 912 +dcdc2_vol = 1400 +dcdc3_vol = 1250 +ldo2_vol = 3000 +ldo3_vol = 2800 +ldo4_vol = 2800 +power_start = 3 +storage_type = -1 + +[clock] +pll3 = 297 +pll4 = 300 +pll6 = 600 +pll7 = 297 +pll8 = 336 + +[card_boot] +logical_start = 40960 +sprite_gpio0 = port:PH151defaultdefault0 +sprite_work_delay = 1000 +sprite_err_delay = 100 + +[card0_boot_para] +card_ctrl = 0 +card_high_speed = 1 +card_line = 4 +sdc_d1 = port:PF0021defaultdefault +sdc_d0 = port:PF0121defaultdefault +sdc_clk = port:PF0221defaultdefault +sdc_cmd = port:PF0321defaultdefault +sdc_d3 = port:PF0421defaultdefault +sdc_d2 = port:PF0521defaultdefault + +[card2_boot_para] +card_ctrl = 2 +card_high_speed = 1 +card_line = 4 +sdc_cmd = port:PC0631defaultdefault +sdc_clk = port:PC0731defaultdefault +sdc_d0 = port:PC0831defaultdefault +sdc_d1 = port:PC0931defaultdefault +sdc_d2 = port:PC1031defaultdefault +sdc_d3 = port:PC1131defaultdefault + +[twi_para] +twi_port = 0 +twi_scl = port:PB002defaultdefaultdefault +twi_sda = port:PB012defaultdefaultdefault + +[uart_para] +uart_debug_port = 0 +uart_debug_tx = port:PB2221defaultdefault +uart_debug_rx = port:PB2321defaultdefault + +[uart_force_debug] +uart_debug_port = 0 +uart_debug_tx = port:PF0241defaultdefault +uart_debug_rx = port:PF0441defaultdefault + +[jtag_para] +jtag_enable = 0 +jtag_ms = port:PB143defaultdefaultdefault +jtag_ck = port:PB153defaultdefaultdefault +jtag_do = port:PB163defaultdefaultdefault +jtag_di = port:PB173defaultdefaultdefault + +[pm_para] +standby_mode = 0 + +[dram_para] +dram_baseaddr = 0x4000 +dram_clk = 480 +dram_type = 3 +dram_rank_num = -1 +dram_chip_density = -1 +dram_io_width = -1 +dram_bus_width = -1 +dram_cas = 9 +dram_zq = 0x7a +dram_odt_en = 0 +dram_size = -1 +dram_tpr0 = 0x42d899b7 +dram_tpr1 = 0xa090 +dram_tpr2 = 0x22a00 +dram_tpr3 = 0x0 +dram_tpr4 = 0x0 +dram_tpr5 = 0x0 +dram_emr1 = 0x4 +dram_emr2 = 0x10 +dram_emr3 = 0x0 + +[mali_para] +mali_used = 1 +mali_clkdiv = 1 + +[emac_para] +emac_used = 1 +emac_rxd3 = port:PA002defaultdefaultdefault +emac_rxd2 = port:PA012defaultdefaultdefault +emac_rxd1 = port:PA022defaultdefaultdefault +emac_rxd0 = port:PA032defaultdefaultdefault +emac_txd3 = port:PA042defaultdefaultdefault +emac_txd2 = port:PA052defaultdefaultdefault +emac_txd1 = port:PA062defaultdefaultdefault +emac_txd0 = port:PA072defaultdefaultdefault +emac_rxclk = port:PA082defaultdefaultdefault +emac_rxerr = port:PA092defaultdefaultdefault +emac_rxdV = port:PA102defaultdefaultdefault +emac_mdc = port:PA112defaultdefaultdefault +emac_mdio = port:PA122defaultdefaultdefault +emac_txen = port:PA132defaultdefaultdefault +emac_txclk = port:PA142defaultdefaultdefault +emac_crs = port:PA152defaultdefaultdefault +emac_col = port:PA162defaultdefaultdefault +emac_reset = port:PA171defaultdefaultdefault + +[gmac_para] +gmac_used = 1 +gmac_rxd3 = port:PA005defaultdefaultdefault +gmac_rxd2 = port:PA015defaultdefaultdefault +gmac_rxd1 = port:PA025defaultdefaultdefault +gmac_rxd0 = port:PA035defaultdefaultdefault +gmac_txd3 = port:PA045defaultdefaultdefault +gmac_txd2 = port:PA055defaultdefaultdefault +gmac_txd1 = port:PA065defaultdefaultdefault +gmac_txd0 = port:PA075defaultdefaultdefault +gmac_rxclk = port:PA085defaultdefaultdefault +gmac_rxerr = port:PA090defaultdefaultdefault +gmac_rxctl = port:PA105defaultdefaultdefault +gmac_mdc = port:PA115defaultdefaultdefault +gmac_mdio = port:PA125defaultdefaultdefault +gmac_txctl = port:PA135defaultdefaultdefault +gmac_txclk = port:PA140defaultdefaultdefault +gmac_txck = port:PA155defaultdefaultdefault +gmac_clkin = port:PA165defaultdefaultdefault +gmac_txerr = port:PA170defaultdefaultdefault emac and gmac both enabled on the same pins? That doesn't look right. + +[twi0_para] +twi0_used = 1 +twi0_scl = port:PB002defaultdefaultdefault +twi0_sda = port:PB012defaultdefaultdefault + +[twi1_para] +twi1_used = 1 +twi1_scl = port:PB182defaultdefaultdefault +twi1_sda = port:PB192defaultdefaultdefault + +[twi2_para] +twi2_used = 1 +twi2_scl = port:PB202defaultdefaultdefault +twi2_sda = port:PB212defaultdefaultdefault + +[uart_para0] +uart_used = 1 +uart_port = 0 +uart_type = 2 +uart_tx =
Re: [linux-sunxi] [PATCH v4 2/2] input: sun4i-ts: Add support for temperature sensor
Hi,
On Sun, May 11, 2014 at 4:06 PM, Hans de Goede hdego...@redhat.com wrote:
The sun4i resisitive touchscreen controller also comes with a built-in
temperature sensor. This commit adds support for it.
This commit also introduces a new ts-attached device-tree property,
when this is not set, the input part of the driver won't register. This way
the internal temperature sensor can be used to measure the SoC temperature
independent of there actually being a touchscreen attached to the controller.
Signed-off-by: Hans de Goede hdego...@redhat.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
---
.../bindings/input/touchscreen/sun4i.txt | 5 +
drivers/input/touchscreen/sun4i-ts.c | 140
-
2 files changed, 114 insertions(+), 31 deletions(-)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
index 881aea7..aef5779 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
@@ -6,10 +6,15 @@ Required properties:
- reg: mmio address range of the chip
- interrupts: interrupt to which the chip is connected
+Optional properties:
+ - allwinner,ts-attached: boolean indicating that an actual touchscreen is
+ attached to the controller
+
Example:
rtp: rtp@01c25000 {
compatible = allwinner,sun4i-a10-ts;
reg = 0x01c25000 0x100;
interrupts = 29;
+ allwinner,ts-attached;
};
diff --git a/drivers/input/touchscreen/sun4i-ts.c
b/drivers/input/touchscreen/sun4i-ts.c
index c5acdfb..f366221 100644
--- a/drivers/input/touchscreen/sun4i-ts.c
+++ b/drivers/input/touchscreen/sun4i-ts.c
@@ -3,6 +3,9 @@
*
* Copyright (C) 2013 - 2014 Hans de Goede hdego...@redhat.com
*
+ * The hwmon parts are based on work by Corentin LABBE which is:
+ * Copyright (C) 2013 Corentin LABBE clabbe.montj...@gmail.com
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -30,6 +33,7 @@
*/
#include linux/err.h
+#include linux/hwmon.h
#include linux/init.h
#include linux/input.h
#include linux/interrupt.h
@@ -106,14 +110,12 @@ struct sun4i_ts_data {
void __iomem *base;
unsigned int irq;
bool ignore_fifo_data;
+ int temp_data;
};
-static irqreturn_t sun4i_ts_irq(int irq, void *dev_id)
+static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val)
{
- struct sun4i_ts_data *ts = dev_id;
- u32 reg_val, x, y;
-
- reg_val = readl(ts-base + TP_INT_FIFOS);
+ u32 x, y;
if (reg_val FIFO_DATA_PENDING) {
x = readl(ts-base + TP_DATA);
@@ -139,6 +141,20 @@ static irqreturn_t sun4i_ts_irq(int irq, void *dev_id)
input_report_key(ts-input, BTN_TOUCH, 0);
input_sync(ts-input);
}
+}
+
+static irqreturn_t sun4i_ts_irq(int irq, void *dev_id)
+{
+ struct sun4i_ts_data *ts = dev_id;
+ u32 reg_val;
+
+ reg_val = readl(ts-base + TP_INT_FIFOS);
+
+ if (reg_val TEMP_DATA_PENDING)
+ ts-temp_data = readl(ts-base + TEMP_DATA);
+
+ if (ts-input)
+ sun4i_ts_irq_handle_input(ts, reg_val);
writel(reg_val, ts-base + TP_INT_FIFOS);
@@ -149,9 +165,9 @@ static int sun4i_ts_open(struct input_dev *dev)
{
struct sun4i_ts_data *ts = input_get_drvdata(dev);
- /* Flush, set trig level to 1, enable data and up irqs */
- writel(DATA_IRQ_EN(1) | FIFO_TRIG(1) | FIFO_FLUSH(1) |
TP_UP_IRQ_EN(1),
- ts-base + TP_INT_FIFOC);
+ /* Flush, set trig level to 1, enable temp, data and up irqs */
+ writel(TEMP_IRQ_EN(1) | DATA_IRQ_EN(1) | FIFO_TRIG(1) | FIFO_FLUSH(1)
|
+ TP_UP_IRQ_EN(1), ts-base + TP_INT_FIFOC);
return 0;
}
@@ -160,15 +176,48 @@ static void sun4i_ts_close(struct input_dev *dev)
{
struct sun4i_ts_data *ts = input_get_drvdata(dev);
- /* Deactivate all IRQs */
- writel(0, ts-base + TP_INT_FIFOC);
+ /* Deactivate all input IRQs */
+ writel(TEMP_IRQ_EN(1), ts-base + TP_INT_FIFOC);
+}
+
+static ssize_t show_temp(struct device *dev, struct device_attribute
*devattr,
+char *buf)
+{
+ struct sun4i_ts_data *ts = dev_get_drvdata(dev);
+
+ /* No temp_data until the first irq */
+ if (ts-temp_data == -1)
+ return -EAGAIN;
+
+ return sprintf(buf, %d\n, (ts-temp_data - 1447) * 100);
+}
+
+static ssize_t show_temp_label(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+
Re: [linux-sunxi] Re: [PATCH v4 01/03] ARM: sunxi: Add documentation for sunxi consumer infrared devices
Hi,
On Wed, Apr 30, 2014 at 6:54 PM, Александр Берсенев b...@hackerdom.ru wrote:
[PATCH v4 01/03] ARM: sunxi: Add documentation for sunxi consumer infrared
devices
This patch adds documentation for Device-Tree bindings for sunxi IR
controller.
Signed-off-by: Alexander Bersenev b...@hackerdom.ru
Signed-off-by: Alexsey Shestacov wingr...@linux-sunxi.org
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
new file mode 100644
index 000..d502cf4
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -0,0 +1,23 @@
+Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
+
+Required properties:
+- compatible: should be allwinner,sun7i-a20-ir;
+- clocks: list of clock specifiers, corresponding to
+ entries in clock-names property;
+- clock-names: should contain apb0_ir0 and ir0 entries;
+- interrupts: should contain IR IRQ number;
+- reg: should contain IO map address for IR.
+
+Optional properties:
+- linux,rc-map-name : Remote control map name.
+
+Example:
+
+ir0: ir@01c21800 {
+ compatible = allwinner,sun7i-a20-ir;
+ clocks = apb0_gates 6, ir0_clk;
+ clock-names = apb0_ir0, ir0;
+ interrupts = 0 5 1;
+ reg = 0x01C21800 0x40;
+ linux,rc-map-name = rc-rc6-mce;
You seem to be mixing spaces and tabs here, with spaces in front.
(Gmail messed this up. See the original post.)
Please stick to using tabs first, and spaces for alignment.
ChenYu
+};
среда, 30 апреля 2014 г., 16:51:12 UTC+6 пользователь Александр Берсенев
написал:
This patch introduces Consumer IR(CIR) support for sunxi boards.
This is based on Alexsey Shestacov's work based on the original driver
supplied by Allwinner.
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Re: [linux-sunxi] [PATCH v2 3/7] phy: usb: sunxi: Introduce Allwinner A31 USB PHY support
Hi,
On Sat, May 10, 2014 at 8:56 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were
having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
drivers/phy/phy-sun4i-usb.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index e6e6c4ba7145..8bd89430d945 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -61,7 +61,6 @@
#define MAX_PHYS 3
struct sun4i_usb_phy_data {
- struct clk *clk;
void __iomem *base;
struct mutex mutex;
int num_phys;
@@ -71,6 +70,7 @@ struct sun4i_usb_phy_data {
void __iomem *pmu;
struct regulator *vbus;
struct reset_control *reset;
+ struct clk *clk;
int index;
} phys[MAX_PHYS];
};
@@ -146,13 +146,13 @@ static int sun4i_usb_phy_init(struct phy *_phy)
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
int ret;
- ret = clk_prepare_enable(data-clk);
+ ret = clk_prepare_enable(phy-clk);
if (ret)
return ret;
ret = reset_control_deassert(phy-reset);
if (ret) {
- clk_disable_unprepare(data-clk);
+ clk_disable_unprepare(phy-clk);
return ret;
}
@@ -170,11 +170,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
static int sun4i_usb_phy_exit(struct phy *_phy)
{
struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
- struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy-reset);
- clk_disable_unprepare(data-clk);
+ clk_disable_unprepare(phy-clk);
return 0;
}
@@ -228,8 +227,10 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
struct phy_provider *phy_provider;
struct reset_control *reset;
struct regulator *vbus;
+ bool dedicated_clocks;
No default?
struct resource *res;
struct phy *phy;
+ struct clk *clk;
char name[16];
int i;
@@ -249,15 +250,20 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
else
data-disc_thresh = 2;
+ if (of_device_is_compatible(np, allwinner,sun6i-a31-usb-phy))
+ dedicated_clocks = true;
+
dedicated_clocks is more than likely to be true from leftover data
on the stack. This results in the usb phy driver probe failing, and
the usb host drivers left in perpetual probe deferral on my Cubietruck.
Adding an else section fixes this.
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, phy_ctrl);
data-base = devm_ioremap_resource(dev, res);
if (IS_ERR(data-base))
return PTR_ERR(data-base);
- data-clk = devm_clk_get(dev, usb_phy);
- if (IS_ERR(data-clk)) {
- dev_err(dev, could not get usb_phy clock\n);
- return PTR_ERR(data-clk);
+ if (!dedicated_clocks) {
+ clk = devm_clk_get(dev, usb_phy);
+ if (IS_ERR(clk)) {
+ dev_err(dev, could not get usb_phy clock\n);
+ return PTR_ERR(clk);
+ }
}
/* Skip 0, 0 is the phy for otg which is not yet supported. */
@@ -270,6 +276,15 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
vbus = NULL;
}
+ if (dedicated_clocks) {
+ snprintf(name, sizeof(name), usb%d_phy, i);
+ clk = devm_clk_get(dev, name);
+ if (IS_ERR(clk)) {
+ dev_err(dev, failed to get clock %s\n,
name);
+ return PTR_ERR(clk);
+ }
+ }
+
snprintf(name, sizeof(name), usb%d_reset, i);
reset = devm_reset_control_get(dev, name);
if (IS_ERR(reset)) {
@@ -296,6 +311,7 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
data-phys[i].pmu = pmu;
data-phys[i].vbus = vbus;
data-phys[i].reset = reset;
+ data-phys[i].clk = clk;
data-phys[i].index = i;
phy_set_drvdata(phy, data-phys[i]);
}
@@ -311,6 +327,7 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = allwinner,sun4i-a10-usb-phy },
Re: [linux-sunxi] Does AXP209 have some non-volatile memory?
Hi, On Tue, May 13, 2014 at 9:09 PM, Siarhei Siamashka siarhei.siamas...@gmail.com wrote: Hi, There is the following page on the cubieboard.org website: http://cubieboard.org/2014/01/13/upgrade-new-android-for-cubietruckv1-01/ It provides an SD card image, with the following description We don’t need it bootup, just clean some register value on PMU. So I wonder if there is some storage space there to save the information about the CPU and DRAM speed grade? Or if the space is too small, then just some sort of a board type identifier might be also enough. This identifier could be used as a key for a table look-up in the u-boot bootloader to find the necessary information about the hardware. The AXP209 has 12 bytes of general purpose memory (register address 0x04 - 0x0f). Though it seems Allwinner code may be using some of it? Also if the AXP209 is no good, then maybe some other non-volatile memory in the A10/A13/A20 SoC exists? I have read about EFUSE, but it looks like the EFUSE power pin is typically grounded and nobody can write anything there. Any other commonly used and easy/safe to autodetect storage option in the sunxi hardware? The A20 Timer block has 16 general purpose registers for storing data, powered by RTC. Something similar should be available on the other SoCs. It looks like TWI1 is used for connecting EEPROM in the A10-Lime. And TWI2 is used for VGA DDC in the Cubietruck. Are we up to having some sort of a common standard at least for the development boards, so that the same u-boot build could be used for all of them? Cheers ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] GMAC on cubieboard2 with 100MB hub
Hi, On Sun, May 18, 2014 at 10:14 PM, Ian Campbell i...@hellion.org.uk wrote: My cubieboard2 (which uses the designware GMAC driver) doesn't seem to work with my 100MB netgear hub. From both Linux (3.14.4) and u-boot IIRC the associated DT and clock drivers were merged in 3.15. 3.14 only had stmmac glue layer merged. Without them, either the driver won't probe, or you're at the mercy of whatever u-boot setup. (either mainline + sunxi upstreaming patches + cb2 bits, or sunxi repo, doesn't matter) it doesn't seem to be able to generate traffic, despite it thinking there is a link. What is the link speed it thinks it has? Is it correct? Also is the GMAC clock set to the correct setting for MII mode? A cubietruck plugged into the same hub works fine (as do various other bits of non-sunxi kit) and the cubieboard works fine if I plug it directly into the uplink cable which goes to a gigabit cisco switch. Sounds like an auto-negotiation problem. IIRC we've encountered this while working on GMAC support. You must always select PHY_GIGE, even if the link/phy can only do 100M. This is to make U-boot's miiphy interface be aware of the 1000M flags, and correctly mask them out. TBH this hub is probably due an upgrade, but I wondered if anyone had any ideas of things I should try first. Hope this helps. I didn't leave any notes around. Cheers, ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH] pinctrl: sunxi: fix pin numbers passed to register offset helpers
The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses. This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers. Signed-off-by: Chen-Yu Tsai w...@csie.org --- Hi, This patch fixes the pinctrl driver failing to set pinmuxes for the R_PIO block found on the A31 and A23. The problem was found while working on bringing up the A23 SoC. The R_UART pins weren't properly muxed when the bootloader didn't use them. A thank you to Boris who also verified the issue. Cheers, ChenYu --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 26 ++ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index f6522b5..59962fa 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -280,6 +280,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sunxi_pinctrl_group *g = pctl-groups[group]; unsigned long flags; + unsigned pin = g-pin - pctl-desc-pin_base; u32 val, mask; u16 strength; u8 dlevel; @@ -303,23 +304,23 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, * 3: 40mA */ dlevel = strength / 10 - 1; - val = readl(pctl-membase + sunxi_dlevel_reg(g-pin)); - mask = DLEVEL_PINS_MASK sunxi_dlevel_offset(g-pin); + val = readl(pctl-membase + sunxi_dlevel_reg(pin)); + mask = DLEVEL_PINS_MASK sunxi_dlevel_offset(pin); writel((val ~mask) - | dlevel sunxi_dlevel_offset(g-pin), - pctl-membase + sunxi_dlevel_reg(g-pin)); + | dlevel sunxi_dlevel_offset(pin), + pctl-membase + sunxi_dlevel_reg(pin)); break; case PIN_CONFIG_BIAS_PULL_UP: - val = readl(pctl-membase + sunxi_pull_reg(g-pin)); - mask = PULL_PINS_MASK sunxi_pull_offset(g-pin); - writel((val ~mask) | 1 sunxi_pull_offset(g-pin), - pctl-membase + sunxi_pull_reg(g-pin)); + val = readl(pctl-membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK sunxi_pull_offset(pin); + writel((val ~mask) | 1 sunxi_pull_offset(pin), + pctl-membase + sunxi_pull_reg(pin)); break; case PIN_CONFIG_BIAS_PULL_DOWN: - val = readl(pctl-membase + sunxi_pull_reg(g-pin)); - mask = PULL_PINS_MASK sunxi_pull_offset(g-pin); - writel((val ~mask) | 2 sunxi_pull_offset(g-pin), - pctl-membase + sunxi_pull_reg(g-pin)); + val = readl(pctl-membase + sunxi_pull_reg(pin)); + mask = PULL_PINS_MASK sunxi_pull_offset(pin); + writel((val ~mask) | 2 sunxi_pull_offset(pin), + pctl-membase + sunxi_pull_reg(pin)); break; default: break; @@ -376,6 +377,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, spin_lock_irqsave(pctl-lock, flags); + pin -= pctl-desc-pin_base; val = readl(pctl-membase + sunxi_mux_reg(pin)); mask = MUX_PINS_MASK sunxi_mux_offset(pin); writel((val ~mask) | config sunxi_mux_offset(pin), -- 2.0.0.rc2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
