[linux-yocto] [yocto-4.12][PATCH 36/36] ALSA: hda/realtek - Fix ALC700 family no sound issue

[Liwei Song]

From: Kailang Yang 

commit 2d7fe6185722b0817bb345f62ab06b76a7b26542 upstream.

It maybe the typo for ALC700 support patch.
To fix the bit value on this patch.

Fixes: 6fbae35a3170 ("ALSA: hda/realtek - Add support for new codecs 
ALC700/ALC701/ALC703")
Signed-off-by: Kailang Yang 
Cc: 
Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 sound/pci/hda/patch_realtek.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 3f1feb362ffc..5bca33ead28b 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -6541,7 +6541,7 @@ static int patch_alc269(struct hda_codec *codec)
case 0x10ec0703:
spec->codec_variant = ALC269_TYPE_ALC700;
spec->gen.mixer_nid = 0; /* ALC700 does not have any loopback 
mixer path */
-   alc_update_coef_idx(codec, 0x4a, 0, 1 << 15); /* Combo jack 
auto trigger control */
+   alc_update_coef_idx(codec, 0x4a, 1 << 15, 0); /* Combo jack 
auto trigger control */
break;
 
}
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 35/36] ALSA: hda - Add model string for Intel reference board quirk

[Liwei Song]

From: Takashi Iwai 

commit 28d1d6d2f314ff395ff67565d1145742614b21c8 upstream.

For allowing user to apply the existing quirk on a machine with a
different SSID, add a new model string entry, alc700-ref.
The quirk itself was introduced in the commit b84e843644f2: "ALSA:
hda/realtek - Enable jack detection function for Intel ALC700")

Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 Documentation/sound/hd-audio/models.rst | 2 ++
 sound/pci/hda/patch_realtek.c   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/Documentation/sound/hd-audio/models.rst 
b/Documentation/sound/hd-audio/models.rst
index 773d2bfacc6c..1fee5a4f6660 100644
--- a/Documentation/sound/hd-audio/models.rst
+++ b/Documentation/sound/hd-audio/models.rst
@@ -82,6 +82,8 @@ tpt460
 Lenovo Thinkpad T460/560 setup
 dual-codecs
 Lenovo laptops with dual codecs
+alc700-ref
+Intel reference board with ALC700 codec
 
 ALC66x/67x/892
 ==
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 1e9a5797a5a2..3f1feb362ffc 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -6059,6 +6059,7 @@ static const struct hda_model_fixup alc269_fixup_models[] 
= {
{.id = ALC292_FIXUP_TPT440, .name = "tpt440"},
{.id = ALC292_FIXUP_TPT460, .name = "tpt460"},
{.id = ALC233_FIXUP_LENOVO_MULTI_CODECS, .name = "dual-codecs"},
+   {.id = ALC700_FIXUP_INTEL_REFERENCE, .name = "alc700-ref"},
{}
 };
 #define ALC225_STANDARD_PINS \
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 33/36] ALSA: hda: Add Cannonlake PCI ID

[Liwei Song]

From: Guneshwor Singh 

commit 2357f6f00098a437f9de084c3c34254d20dea789 upstream.

Cannonlake is next generation Intel platform. This commit adds PCI ID for
it.

Signed-off-by: Guneshwor Singh 
Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 sound/pci/hda/hda_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 5ae8ddab6412..f958d8d54d15 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -2389,6 +2389,9 @@ static const struct pci_device_id azx_ids[] = {
/* Coffelake */
{ PCI_DEVICE(0x8086, 0xa348),
  .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
+   /* Cannonlake */
+   { PCI_DEVICE(0x8086, 0x9dc8),
+ .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
/* Broxton-P(Apollolake) */
{ PCI_DEVICE(0x8086, 0x5a98),
  .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 34/36] ALSA: hda/realtek - Enable jack detection function for Intel ALC700

[Liwei Song]

From: PeiSen Hou 

commit b84e843644f211dbddcd65ba80732bdc3acf5380 upstream.

Intel ALC 700 needs this patch for jack detection function.
Because ALC700's jack detect function defaults is disable.
So alc700 needs pathc to enable jack detection function.

Signed-off-by: PeiSen Hou 
Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 sound/pci/hda/patch_realtek.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index a8815e6bf400..1e9a5797a5a2 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -4975,6 +4975,7 @@ enum {
ALC233_FIXUP_EAPD_COEF_AND_MIC_NO_PRESENCE,
ALC233_FIXUP_LENOVO_MULTI_CODECS,
ALC294_FIXUP_LENOVO_MIC_LOCATION,
+   ALC700_FIXUP_INTEL_REFERENCE,
 };
 
 static const struct hda_fixup alc269_fixups[] = {
@@ -5760,6 +5761,21 @@ static const struct hda_fixup alc269_fixups[] = {
{ }
},
},
+   [ALC700_FIXUP_INTEL_REFERENCE] = {
+   .type = HDA_FIXUP_VERBS,
+   .v.verbs = (const struct hda_verb[]) {
+   /* Enables internal speaker */
+   {0x20, AC_VERB_SET_COEF_INDEX, 0x45},
+   {0x20, AC_VERB_SET_PROC_COEF, 0x5289},
+   {0x20, AC_VERB_SET_COEF_INDEX, 0x4A},
+   {0x20, AC_VERB_SET_PROC_COEF, 0x001b},
+   {0x58, AC_VERB_SET_COEF_INDEX, 0x00},
+   {0x58, AC_VERB_SET_PROC_COEF, 0x3888},
+   {0x20, AC_VERB_SET_COEF_INDEX, 0x6f},
+   {0x20, AC_VERB_SET_PROC_COEF, 0x2c0b},
+   {}
+   }
+   },
 };
 
 static const struct snd_pci_quirk alc269_fixup_tbl[] = {
@@ -5911,6 +5927,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
SND_PCI_QUIRK(0x10cf, 0x15dc, "Lifebook T731", 
ALC269_FIXUP_LIFEBOOK_HP_PIN),
SND_PCI_QUIRK(0x10cf, 0x1757, "Lifebook E752", 
ALC269_FIXUP_LIFEBOOK_HP_PIN),
SND_PCI_QUIRK(0x10cf, 0x1845, "Lifebook U904", 
ALC269_FIXUP_LIFEBOOK_EXTMIC),
+   SND_PCI_QUIRK(0x10ec, 0x10f2, "Intel Reference board", 
ALC700_FIXUP_INTEL_REFERENCE),
SND_PCI_QUIRK(0x144d, 0xc109, "Samsung Ativ book 9 (NP900X3G)", 
ALC269_FIXUP_INV_DMIC),
SND_PCI_QUIRK(0x144d, 0xc740, "Samsung Ativ book 8 (NP870Z5G)", 
ALC269_FIXUP_ATIV_BOOK_8),
SND_PCI_QUIRK(0x1458, 0xfa53, "Gigabyte BXBT-2807", 
ALC283_FIXUP_HEADSET_MIC),
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 32/36] ALSA: hda - Fix unbalance of i915 module refcount

[Liwei Song]

From: Takashi Iwai 

commit fc18282cdcba984ab89c74d7e844c10114ae0795 upstream.

The commit dba9b7b6ca1a ("ALSA: hda - Fix doubly initialization of
i915 component") contained a typo that leads to the unbalance of i915
module reference.  The value to be checked is not chip->driver_type
but chip->driver_caps.

Fixes: dba9b7b6ca1a ("ALSA: hda - Fix doubly initialization of i915 component")
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=196219
Reported-by: Martin Peres 
Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 sound/pci/hda/hda_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 03e34edc8f24..5ae8ddab6412 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1385,7 +1385,7 @@ static int azx_free(struct azx *chip)
if (hda->need_i915_power)
snd_hdac_display_power(bus, false);
}
-   if (chip->driver_type & AZX_DCAPS_I915_COMPONENT)
+   if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
snd_hdac_i915_exit(bus);
kfree(hda);
 
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 31/36] ALSA: hda - Fix doubly initialization of i915 component

[Liwei Song]

From: Takashi Iwai 

commit dba9b7b6ca1af60fd21137c18795a81a5652c5ae upstream.

In the commit fcc88d91cd36 ("ALSA: hda - Bind with i915 component
before codec binding"), the binding with i915 audio component is moved
to be performed always at probing the controller.  This fixed the
potential problems on IVB, but now it brought another issue on HSW and
BDW.  These two platforms give two individual HD-audio controllers,
one for the analog codec on PCH and another for HDMI over gfx.  Since
I decided to take a lazy path to check only AZX_DRIVER_PCH type in the
commit above, now both controllers try to bind with i915, and you see
a kernel WARNING.

This patch tries to address it again properly.  Now a new DCAPS bit,
AZX_DCAPS_I915_COMPONENT, is introduced for indicating the binding
with i915 component in addition to the existing I915_POWERWELL bit
flag.  Each PCI entry has to give this new flag if it requires the
binding with i915 component.  For HSW/BDW PCH (i.e. the ones defined
by AZX_DCAPS_INTEL_PCH) doesn't contain AZX_DCAPS_I915_COMPONENT bit
while others have it.

While we're at it, add parentheses around the bit flag check for
avoiding possible compiler warnings, too.

The bug was spotted by Intel CI tests.

Fixes: fcc88d91cd36 ("ALSA: hda - Bind with i915 component before codec 
binding")
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=196219
Reported-by: Martin Peres 
Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 sound/pci/hda/hda_controller.h |  6 +-
 sound/pci/hda/hda_intel.c  | 40 ++--
 2 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h
index 35a9ab2cac46..a68e75b00ea3 100644
--- a/sound/pci/hda/hda_controller.h
+++ b/sound/pci/hda/hda_controller.h
@@ -32,7 +32,11 @@
 #define AZX_DCAPS_NO_MSI   (1 << 9)/* No MSI support */
 #define AZX_DCAPS_SNOOP_MASK   (3 << 10)   /* snoop type mask */
 #define AZX_DCAPS_SNOOP_OFF(1 << 12)   /* snoop default off */
-/* 13 unused */
+#ifdef CONFIG_SND_HDA_I915
+#define AZX_DCAPS_I915_COMPONENT (1 << 13) /* bind with i915 gfx */
+#else
+#define AZX_DCAPS_I915_COMPONENT 0 /* NOP */
+#endif
 /* 14 unused */
 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
 #define AZX_DCAPS_POSFIX_LPIB  (1 << 16)   /* Use LPIB as default */
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index a157582b8f2c..03e34edc8f24 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -293,38 +293,43 @@ enum {
(AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 AZX_DCAPS_SNOOP_TYPE(SCH))
 
-/* PCH up to IVB; no runtime PM */
+/* PCH up to IVB; no runtime PM; bind with i915 gfx */
 #define AZX_DCAPS_INTEL_PCH_NOPM \
-   (AZX_DCAPS_INTEL_PCH_BASE)
+   (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 
 /* PCH for HSW/BDW; with runtime PM */
+/* no i915 binding for this as HSW/BDW has another controller for HDMI */
 #define AZX_DCAPS_INTEL_PCH \
(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 
 /* HSW HDMI */
 #define AZX_DCAPS_INTEL_HASWELL \
(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
-AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
-AZX_DCAPS_SNOOP_TYPE(SCH))
+AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
+AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 
 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 #define AZX_DCAPS_INTEL_BROADWELL \
(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
-AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
-AZX_DCAPS_SNOOP_TYPE(SCH))
+AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
+AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 
 #define AZX_DCAPS_INTEL_BAYTRAIL \
-   (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
+   (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
+AZX_DCAPS_I915_POWERWELL)
 
 #define AZX_DCAPS_INTEL_BRASWELL \
-   (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
+   (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
+AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 
 #define AZX_DCAPS_INTEL_SKYLAKE \
-   (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
+   (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
+AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 AZX_DCAPS_I915_POWERWELL)
 
 #define AZX_DCAPS_INTEL_BROXTON \
-   (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
+   (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
+AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 AZX_DCAPS_I915_POWERWELL)
 
 /* quirks for ATI SB / AMD Hudson */
@@ -1008,7 +1013,7 @@ static int 

[linux-yocto] [yocto-4.12][PATCH 28/36] drm/i915/cnl: Implement CNL display init/unit sequence

[Liwei Song]

From: Ville Syrjälä 

commit d8d4a512a6ffa97bde442023e87b9c87a37d8838 upstream.

Implement the CNL display init/uninit sequence as outlined in Bspec.

Quite similar to SKL/BXT. The main complicaiton is probably the extra
procmon setup we must do based on the process/voltage information we
can read out from some register.

v2: s/skl_dbuf/gen9_dbuf/ to follow upstream
bxt needed a cdclk sanitize step, so let's add it for cnl too
v3: s/CHICKEN_MISC_1/CHICKEN_MISC_2/ (Ander)
v4: Rebased by Rodrigo after Ville's cdclk rework
v5: Removed unecessary Aux IO forced enable/disable, Fix DW10 setup
Fix procpon Mask. (Credits-to Paulo and Clint)
Remove A0 workaround.
v6: Rebased on top of recent code (Rodrigo).
v7: Respect the order of sanitize_ after set_
(Done by Rodrigo, Requested by Ville)
v8: Commit message updated to matvh v5 changes besides
Remove unused DW8 and an extra blank line. (all noticed
by Imre).
v9: Remove __attribute__((unused)) added on latest version
of drm/i915/cnl: Implement .set_cdclk() for CNL.

Cc: Paulo Zanoni 
Cc: Clint Taylor 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Imre Deak 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-3-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_reg.h |  23 +++
 drivers/gpu/drm/i915/intel_cdclk.c  | 108 +-
 drivers/gpu/drm/i915/intel_drv.h|   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 113 +++-
 4 files changed, 243 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9268a4aff20..aae97e6aabf4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1655,6 +1655,9 @@ enum skl_disp_power_wells {
 #define   PHY_RESERVED (1 << 7)
 #define BXT_PORT_CL1CM_DW0(phy)_BXT_PHY((phy), 
_PORT_CL1CM_DW0_BC)
 
+#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
+#define   CL_POWER_DOWN_ENABLE (1 << 4)
+
 #define _PORT_CL1CM_DW9_A  0x162024
 #define _PORT_CL1CM_DW9_BC 0x6C024
 #define   IREF0RC_OFFSET_SHIFT 8
@@ -1687,6 +1690,23 @@ enum skl_disp_power_wells {
 #define BXT_PORT_CL2CM_DW6(phy)_BXT_PHY((phy), 
_PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
 
+#define CNL_PORT_COMP_DW0  _MMIO(0x162100)
+#define   COMP_INIT(1 << 31)
+#define CNL_PORT_COMP_DW1  _MMIO(0x162104)
+#define CNL_PORT_COMP_DW3  _MMIO(0x16210c)
+#define   PROCESS_INFO_DOT_0   (0 << 26)
+#define   PROCESS_INFO_DOT_1   (1 << 26)
+#define   PROCESS_INFO_DOT_4   (2 << 26)
+#define   PROCESS_INFO_MASK(7 << 26)
+#define   PROCESS_INFO_SHIFT   26
+#define   VOLTAGE_INFO_0_85V   (0 << 24)
+#define   VOLTAGE_INFO_0_95V   (1 << 24)
+#define   VOLTAGE_INFO_1_05V   (2 << 24)
+#define   VOLTAGE_INFO_MASK(3 << 24)
+#define   VOLTAGE_INFO_SHIFT   24
+#define CNL_PORT_COMP_DW9  _MMIO(0x162124)
+#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A0x16218C
 #define _PORT_REF_DW3_BC   0x6C18C
@@ -6514,6 +6534,9 @@ enum {
 #define  GLK_CL1_PWR_DOWN  (1 << 11)
 #define  GLK_CL2_PWR_DOWN  (1 << 12)
 
+#define CHICKEN_MISC_2 _MMIO(0x42084)
+#define  COMP_PWR_DOWN (1 << 23)
+
 #define _CHICKEN_PIPESL_1_A0x420b0
 #define _CHICKEN_PIPESL_1_B0x420b4
 #define  HSW_FBCQ_DIS  (1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index fea06f38b435..4032cc66082a 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1499,7 +1499,6 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private 
*dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
 }
 
-__attribute__((unused))
 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_state *cdclk_state)
 {
@@ -1572,6 +1571,113 @@ static void cnl_set_cdclk(struct drm_i915_private 
*dev_priv,
intel_update_cdclk(dev_priv);
 }
 
+static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+   int ratio;
+
+   if (cdclk == dev_priv->cdclk.hw.ref)
+   return 0;
+
+   switch (cdclk) {
+   default:
+   MISSING_CASE(cdclk);
+   case 168000:
+   case 336000:
+   ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
+   break;
+   case 528000:
+   ratio = 

[linux-yocto] [yocto-4.12][PATCH 29/36] ALSA: hda - Add AZX_DRIVER_SKL for simplification

[Liwei Song]

From: Takashi Iwai 

commit a4b4793f640b72af3e2bb2a1ad79725c103d5e40 upstream.

We checked the quirks specific to the recent Intel chips by checking
the PCI IDs manually, but it's becoming messy with lots of IS_SKL()
and other macros, as the amount accumulated.

For simplification, here the new AZX_DRIVER_SKL type is introduced,
and check chip->driver_type instead of the manual PCI ID.  The short
name for this is still "HDA Intel PCH", so that it doesn't break the
existing user-space unnecessarily.

Suggested-by: Vinod Koul 
Signed-off-by: Takashi Iwai 
Signed-off-by: Liwei Song 
---
 sound/pci/hda/hda_intel.c | 47 +--
 1 file changed, 21 insertions(+), 26 deletions(-)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 01eb1dc7b5b3..07ea7f48aa01 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -263,6 +263,7 @@ enum {
AZX_DRIVER_ICH,
AZX_DRIVER_PCH,
AZX_DRIVER_SCH,
+   AZX_DRIVER_SKL,
AZX_DRIVER_HDMI,
AZX_DRIVER_ATI,
AZX_DRIVER_ATIHDMI,
@@ -364,23 +365,13 @@ enum {
((pci)->device == 0x0d0c) || \
((pci)->device == 0x160c))
 
-#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
-#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
-#define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
-#define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
-#define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
-#define IS_BXT_T(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x1a98)
-#define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
-#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
-#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci) || \
- IS_BXT_T(pci) || IS_KBL(pci) || IS_KBL_LP(pci) || \
- IS_KBL_H(pci) || IS_GLK(pci) || IS_CFL(pci))
 
 static char *driver_short_names[] = {
[AZX_DRIVER_ICH] = "HDA Intel",
[AZX_DRIVER_PCH] = "HDA Intel PCH",
[AZX_DRIVER_SCH] = "HDA Intel MID",
+   [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility 
*/
[AZX_DRIVER_HDMI] = "HDA Intel HDMI",
[AZX_DRIVER_ATI] = "HDA ATI SB",
[AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
@@ -644,13 +635,13 @@ static void hda_intel_init_chip(struct azx *chip, bool 
full_reset)
 
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
snd_hdac_set_codec_wakeup(bus, true);
-   if (IS_SKL_PLUS(pci)) {
+   if (chip->driver_type == AZX_DRIVER_SKL) {
pci_read_config_dword(pci, INTEL_HDA_CGCTL, );
val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
}
azx_init_chip(chip, full_reset);
-   if (IS_SKL_PLUS(pci)) {
+   if (chip->driver_type == AZX_DRIVER_SKL) {
pci_read_config_dword(pci, INTEL_HDA_CGCTL, );
val = val | INTEL_HDA_CGCTL_MISCBDCGE;
pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
@@ -1075,9 +1066,11 @@ static int azx_resume(struct device *dev)
  */
 static int azx_freeze_noirq(struct device *dev)
 {
+   struct snd_card *card = dev_get_drvdata(dev);
+   struct azx *chip = card->private_data;
struct pci_dev *pci = to_pci_dev(dev);
 
-   if (IS_SKL_PLUS(pci))
+   if (chip->driver_type == AZX_DRIVER_SKL)
pci_set_power_state(pci, PCI_D3hot);
 
return 0;
@@ -1085,9 +1078,11 @@ static int azx_freeze_noirq(struct device *dev)
 
 static int azx_thaw_noirq(struct device *dev)
 {
+   struct snd_card *card = dev_get_drvdata(dev);
+   struct azx *chip = card->private_data;
struct pci_dev *pci = to_pci_dev(dev);
 
-   if (IS_SKL_PLUS(pci))
+   if (chip->driver_type == AZX_DRIVER_SKL)
pci_set_power_state(pci, PCI_D0);
 
return 0;
@@ -1497,7 +1492,7 @@ static int check_position_fix(struct azx *chip, int fix)
dev_dbg(chip->card->dev, "Using LPIB position fix\n");
return POS_FIX_LPIB;
}
-   if (IS_SKL_PLUS(chip->pci)) {
+   if (chip->driver_type == AZX_DRIVER_SKL) {
dev_dbg(chip->card->dev, "Using SKL position fix\n");
return POS_FIX_SKL;
}
@@ -1798,7 +1793,7 @@ static int azx_first_init(struct azx *chip)
return -ENXIO;
}
 
-   if (IS_SKL_PLUS(pci))
+   if (chip->driver_type == AZX_DRIVER_SKL)
snd_hdac_bus_parse_capabilities(bus);
 
/*
@@ -2367,31 +2362,31 @@ static const struct pci_device_id azx_ids[] = {
 

[linux-yocto] [yocto-4.12][PATCH 26/36] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Liwei Song]

From: Ville Syrjälä 

commit 945f2672ccbb5c92a8a7bf23cba3a68a6b0885e7 upstream.

Add support for reading out the cdclk frequency from the hardware on
CNL. Very similar to BXT, with a few new twists and turns:
* the PLL is now called CDCLK PLL, not DE PLL
* reference clock can be 24 MHz in addition to the 19.2 MHz BXT had
* the ratio now lives in the PLL enable register
* Only 1x and 2x CD2X dividers are supported

v2: Deal with PLL lock bit the same way as BXT/SKL do now
v3: DSSM refclk indicator is bit 31 not 24 (Ander)
v4: Rebased by Rodrigo after Ville's cdclk rework.
v5: Set cdclk to the ref clock as previous platforms. (Imre)

Signed-off-by: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Imre Deak 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-1-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_reg.h|  5 
 drivers/gpu/drm/i915/intel_cdclk.c | 56 +-
 2 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19ffc58c8b64..f9268a4aff20 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6554,6 +6554,9 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
 
+#define SKL_DSSM   _MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
+
 #define GEN7_FF_SLICE_CS_CHICKEN1  _MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL(1<<14)
 
@@ -8127,6 +8130,8 @@ enum {
 #define BXT_DE_PLL_ENABLE  _MMIO(0x46070)
 #define   BXT_DE_PLL_PLL_ENABLE(1 << 31)
 #define   BXT_DE_PLL_LOCK  (1 << 30)
+#define   CNL_CDCLK_PLL_RATIO(x)   (x)
+#define   CNL_CDCLK_PLL_RATIO_MASK 0xff
 
 /* GEN9 DC */
 #define DC_STATE_EN_MMIO(0x45504)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index 6b681dc3abd3..dcedc2c7615b 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1414,6 +1414,58 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
bxt_set_cdclk(dev_priv, _state);
 }
 
+static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
+struct intel_cdclk_state *cdclk_state)
+{
+   u32 val;
+
+   if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
+   cdclk_state->ref = 24000;
+   else
+   cdclk_state->ref = 19200;
+
+   cdclk_state->vco = 0;
+
+   val = I915_READ(BXT_DE_PLL_ENABLE);
+   if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
+   return;
+
+   if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
+   return;
+
+   cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
+}
+
+static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
+struct intel_cdclk_state *cdclk_state)
+{
+   u32 divider;
+   int div;
+
+   cnl_cdclk_pll_update(dev_priv, cdclk_state);
+
+   cdclk_state->cdclk = cdclk_state->ref;
+
+   if (cdclk_state->vco == 0)
+   return;
+
+   divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
+
+   switch (divider) {
+   case BXT_CDCLK_CD2X_DIV_SEL_1:
+   div = 2;
+   break;
+   case BXT_CDCLK_CD2X_DIV_SEL_2:
+   div = 4;
+   break;
+   default:
+   MISSING_CASE(divider);
+   return;
+   }
+
+   cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
+}
+
 /**
  * intel_cdclk_state_compare - Determine if two CDCLK states differ
  * @a: first CDCLK state
@@ -1905,7 +1957,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
skl_modeset_calc_cdclk;
}
 
-   if (IS_GEN9_BC(dev_priv))
+   if (IS_CANNONLAKE(dev_priv))
+   dev_priv->display.get_cdclk = cnl_get_cdclk;
+   else if (IS_GEN9_BC(dev_priv))
dev_priv->display.get_cdclk = skl_get_cdclk;
else if (IS_GEN9_LP(dev_priv))
dev_priv->display.get_cdclk = bxt_get_cdclk;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 27/36] drm/i915/cnl: Implement .set_cdclk() for CNL

[Liwei Song]

From: Ville Syrjälä 

commit ef4f7a689ac5f61e36ac9ae77ac967b6469ae68b upstream.

Add support for changing the cdclk frequency on CNL. Again, quite
similar to BXT, but there are some annoying differences which means
trying to share more code might not be feasible:
* PLL ratio now lives in the PLL enable register
* pcode came from SKL, not from BXT

We support three cdclk frequencies: 168,336,528 Mhz. The first two
use the same PLL frequency, the last one uses a different one meaning
we once again may need to toggle the PLL off and on when changing
cdclk.

v2: Rebased by Rodrigo on top of Ville's cdclk rework.
v3: Respect order of set_ bellow get_ (Ville)
v4: Added __attribute__((unused)) to avoid broken compilation with Werror.

Signed-off-by: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Imre Deak 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-2-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 106 +
 1 file changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index dcedc2c7615b..fea06f38b435 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1466,6 +1466,112 @@ static void cnl_get_cdclk(struct drm_i915_private 
*dev_priv,
cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
 }
 
+static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   val = I915_READ(BXT_DE_PLL_ENABLE);
+   val &= ~BXT_DE_PLL_PLL_ENABLE;
+   I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+   /* Timeout 200us */
+   if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
+   DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
+
+   dev_priv->cdclk.hw.vco = 0;
+}
+
+static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+{
+   int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+   u32 val;
+
+   val = CNL_CDCLK_PLL_RATIO(ratio);
+   I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+   val |= BXT_DE_PLL_PLL_ENABLE;
+   I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+   /* Timeout 200us */
+   if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
+   DRM_ERROR("timout waiting for CDCLK PLL lock\n");
+
+   dev_priv->cdclk.hw.vco = vco;
+}
+
+__attribute__((unused))
+static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *cdclk_state)
+{
+   int cdclk = cdclk_state->cdclk;
+   int vco = cdclk_state->vco;
+   u32 val, divider, pcu_ack;
+   int ret;
+
+   mutex_lock(_priv->rps.hw_lock);
+   ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+   SKL_CDCLK_PREPARE_FOR_CHANGE,
+   SKL_CDCLK_READY_FOR_CHANGE,
+   SKL_CDCLK_READY_FOR_CHANGE, 3);
+   mutex_unlock(_priv->rps.hw_lock);
+   if (ret) {
+   DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+ ret);
+   return;
+   }
+
+   /* cdclk = vco / 2 / div{1,2} */
+   switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
+   case 4:
+   divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+   break;
+   case 2:
+   divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+   break;
+   default:
+   WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+   WARN_ON(vco != 0);
+
+   divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+   break;
+   }
+
+   switch (cdclk) {
+   case 528000:
+   pcu_ack = 2;
+   break;
+   case 336000:
+   pcu_ack = 1;
+   break;
+   case 168000:
+   default:
+   pcu_ack = 0;
+   break;
+   }
+
+   if (dev_priv->cdclk.hw.vco != 0 &&
+   dev_priv->cdclk.hw.vco != vco)
+   cnl_cdclk_pll_disable(dev_priv);
+
+   if (dev_priv->cdclk.hw.vco != vco)
+   cnl_cdclk_pll_enable(dev_priv, vco);
+
+   val = divider | skl_cdclk_decimal(cdclk);
+   /*
+* FIXME if only the cd2x divider needs changing, it could be done
+* without shutting off the pipe (if only one pipe is active).
+*/
+   val |= BXT_CDCLK_CD2X_PIPE_NONE;
+   I915_WRITE(CDCLK_CTL, val);
+
+   /* inform PCU of the change */
+   mutex_lock(_priv->rps.hw_lock);
+   sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
+   mutex_unlock(_priv->rps.hw_lock);
+
+   intel_update_cdclk(dev_priv);
+}
+
 /**
  * intel_cdclk_state_compare - Determine if two CDCLK states differ
  * @a: first CDCLK state
-- 

[linux-yocto] [yocto-4.12][PATCH 21/36] drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.

[Liwei Song]

From: Anusha Srivatsa 

commit ccfd13215fd25a0e8c28221f3acc0dcaec11cd15 upstream.

Add PCI Ids for H Sku by following the BSpec.

v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
v3: Add missing IDs(Rodrigo)

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496965267-21725-2-git-send-email-anusha.sriva...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 include/drm/i915_pciids.h   | 5 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 892336a51fb8..29a8eebd24fb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -499,6 +499,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_KBL_GT3_IDS(_kabylake_gt3_info),
INTEL_KBL_GT4_IDS(_kabylake_gt3_info),
INTEL_CFL_S_IDS(_coffeelake_info),
+   INTEL_CFL_H_IDS(_coffeelake_info),
INTEL_CNL_IDS(_cannonlake_info),
{0, 0, 0}
 };
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4858debd4b58..8f25316013ba 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -342,6 +342,11 @@
INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */
 
+/* CFL H */
+#define INTEL_CFL_H_IDS(info) \
+   INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+   INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
+
 /* CNL U 2+2 */
 #define INTEL_CNL_U_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 25/36] drm/i915/cfl: Coffee Lake reuses Kabylake DMC.

[Liwei Song]

From: Rodrigo Vivi 

commit 84cd843e715298bbfb17ed40c7d61d7db6854a70 upstream.

both platforms. We haven't recieved any separated release
specifically for Coffee Lake so let's just re-use what
is already there for Kabylake.

Signed-off-by: Rodrigo Vivi 
Reviewed-by: Dhinakaran Pandiyan 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1497038550-30910-1-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_csr.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c28e11e2deb2..9e225aaf9902 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -435,6 +435,7 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
BDW_FEATURES, \
.gen = 9, \
.platform = INTEL_COFFEELAKE, \
+   .has_csr = 1, \
.has_guc = 1, \
.ddb_size = 896
 
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1575bde0cf90..fb6af0bcdf8f 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -291,7 +291,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private 
*dev_priv,
 
if (IS_GEMINILAKE(dev_priv)) {
required_version = GLK_CSR_VERSION_REQUIRED;
-   } else if (IS_KABYLAKE(dev_priv)) {
+   } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
required_version = KBL_CSR_VERSION_REQUIRED;
} else if (IS_SKYLAKE(dev_priv)) {
required_version = SKL_CSR_VERSION_REQUIRED;
@@ -440,7 +440,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 
if (IS_GEMINILAKE(dev_priv))
csr->fw_path = I915_CSR_GLK;
-   else if (IS_KABYLAKE(dev_priv))
+   else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
csr->fw_path = I915_CSR_KBL;
else if (IS_SKYLAKE(dev_priv))
csr->fw_path = I915_CSR_SKL;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 24/36] drm/i915/huc: Load HuC on Coffee Lake

[Liwei Song]

From: Anusha Srivatsa 

commit 5e5d8b664effe57dc459e082fc37b1aec23f184a upstream.

Coffee Lake reuses Kabylake's HUC firmware.

v2: Change Coffeelake to Coffee Lake

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Lukasz Fiedorowicz 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496965704-23610-2-git-send-email-anusha.sriva...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_huc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 9ee819666a4c..8a5a57fbe5b4 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -165,7 +165,7 @@ void intel_huc_select_fw(struct intel_huc *huc)
huc->fw.path = I915_BXT_HUC_UCODE;
huc->fw.major_ver_wanted = BXT_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = BXT_HUC_FW_MINOR;
-   } else if (IS_KABYLAKE(dev_priv)) {
+   } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
huc->fw.path = I915_KBL_HUC_UCODE;
huc->fw.major_ver_wanted = KBL_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = KBL_HUC_FW_MINOR;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 19/36] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

[Liwei Song]

From: Rodrigo Vivi 

commit 82525c17dedca6316b07c20c62627c83800caa31 upstream.

The whole Display engine for Coffee Lake is pretty much
identical to the Kabylake. For this reason let's reuse
all display related production workardounds here even though
CFL is not explicit listed at Display workarounds page at Spec.

v2: moved intel_pm.c chunck to this patch in order to address
all display related w/a in a single place.

Cc: Arthur Runyan 
Cc: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Dhinakaran Pandiyan 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496937000-8450-3-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_pm.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8aa29202a641..84998240f480 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -58,24 +58,24 @@
 
 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
+   /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
I915_WRITE(CHICKEN_PAR1_1,
   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
I915_WRITE(GEN8_CONFIG0,
   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
 
-   /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
+   /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
I915_WRITE(GEN8_CHICKEN_DCPR_1,
   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
-   /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-   /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
+   /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
+   /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
   DISP_FBC_WM_DIS |
   DISP_FBC_MEMORY_WAKE);
 
-   /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
+   /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
   ILK_DPFC_DISABLE_DUMMY0);
 }
@@ -3073,7 +3073,7 @@ static bool skl_needs_memory_bw_wa(struct 
intel_atomic_state *state)
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-   if (IS_KABYLAKE(dev_priv))
+   if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
return true;
 
if (IS_SKYLAKE(dev_priv) &&
@@ -3784,8 +3784,9 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
  fb->modifier == I915_FORMAT_MOD_Yf_TILED;
x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 
-   /* Display WA #1141: kbl. */
-   if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
+   /* Display WA #1141: kbl,cfl */
+   if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
+   dev_priv->ipc_enabled)
latency += 4;
 
if (apply_memory_bw_wa && x_tiled)
@@ -7500,7 +7501,7 @@ static void kabylake_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-   /* WaFbcNukeOnHostModify:kbl */
+   /* WaFbcNukeOnHostModify:kbl,cfl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
@@ -7968,7 +7969,7 @@ void intel_init_clock_gating_hooks(struct 
drm_i915_private *dev_priv)
 {
if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
-   else if (IS_KABYLAKE(dev_priv))
+   else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = 
kabylake_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 18/36] drm/i915/cfl: Coffee Lake uses CNP PCH.

[Liwei Song]

From: Rodrigo Vivi 

commit 809378196bb449fe30d0ca15a990965fc553f9f5 upstream.

So let's force it on the virtual detection.

Also it is still the only silicon for now on this PCH,
so WARN otherwise.

v2: Rebased on top of Cannonlake and added the missed
debug message as pointed by DK.

Cc: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496937000-8450-2-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f79b1b4ea853..19ffb3439fa9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -139,8 +139,9 @@ static enum intel_pch intel_virt_detect_pch(struct 
drm_i915_private *dev_priv)
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
ret = PCH_SPT;
DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
-   } else if (IS_CANNONLAKE(dev_priv)) {
+   } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
ret = PCH_CNP;
+   DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
}
 
return ret;
@@ -224,11 +225,13 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
-   WARN_ON(!IS_CANNONLAKE(dev_priv));
+   WARN_ON(!IS_CANNONLAKE(dev_priv) &&
+   !IS_COFFEELAKE(dev_priv));
} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
-   WARN_ON(!IS_CANNONLAKE(dev_priv));
+   WARN_ON(!IS_CANNONLAKE(dev_priv) &&
+   !IS_COFFEELAKE(dev_priv));
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 22/36] drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.

[Liwei Song]

From: Anusha Srivatsa 

commit d29fe702c9cb682df99146d24d06e5455f043101 upstream.

Add PCI Ids for U Skus of Coffeelake.

v2: Use intel_coffeelake_gt3_info, in accordance to-
Rodrigo's patch:

v3: rebased

v3: Remove unused INTEL_CFL_IDS(Rodrigo).

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496965267-21725-3-git-send-email-anusha.sriva...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 include/drm/i915_pciids.h   | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 29a8eebd24fb..64336130b27b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -500,6 +500,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_KBL_GT4_IDS(_kabylake_gt3_info),
INTEL_CFL_S_IDS(_coffeelake_info),
INTEL_CFL_H_IDS(_coffeelake_info),
+   INTEL_CFL_U_IDS(_coffeelake_gt3_info),
INTEL_CNL_IDS(_cannonlake_info),
{0, 0, 0}
 };
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 8f25316013ba..34c8f5600ce0 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -347,6 +347,13 @@
INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
 
+/* CFL U */
+#define INTEL_CFL_U_IDS(info) \
+   INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
+   INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
+   INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
+   INTEL_VGA_DEVICE(0x3EA5, info)  /* ULT GT3 */
+
 /* CNL U 2+2 */
 #define INTEL_CNL_U_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 20/36] drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.

[Liwei Song]

From: Anusha Srivatsa 

commit b056f8f3d6b900e8afd19f312719160346d263b4 upstream.

Add PCI Ids for S Sku following the BSpec.

v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
v3: Add missing IDs(Rodrigo)

Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496965267-21725-1-git-send-email-anusha.sriva...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 include/drm/i915_pciids.h   | 8 
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2ebe80f45293..892336a51fb8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -498,6 +498,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_KBL_GT2_IDS(_kabylake_info),
INTEL_KBL_GT3_IDS(_kabylake_gt3_info),
INTEL_KBL_GT4_IDS(_kabylake_gt3_info),
+   INTEL_CFL_S_IDS(_coffeelake_info),
INTEL_CNL_IDS(_cannonlake_info),
{0, 0, 0}
 };
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7d2696a6588e..4858debd4b58 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -334,6 +334,14 @@
INTEL_KBL_GT3_IDS(info), \
INTEL_KBL_GT4_IDS(info)
 
+/* CFL S */
+#define INTEL_CFL_S_IDS(info) \
+   INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
+   INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
+   INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
+   INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
+   INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */
+
 /* CNL U 2+2 */
 #define INTEL_CNL_U_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 17/36] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Liwei Song]

From: Rodrigo Vivi 

commit 71851fa82f4d644f947dd60cfcf81b47640c1b51 upstream.

Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.

It is Gen9 graphics based platform on top of CNP PCH.

Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.

On following patches we will start adding PCI IDs and the
platform specific changes.

v2: Also add BS2 ring that is present on GT3. As on KBL, according
spec: "GT3 also has additional media blocks with second instance
of VEBox and VDBox each", i.e. BSD2 ring in our case. Noticed
when reviewing PCI ID patches.

v3: CFL_PLATFORM instead for CFL_FEATURES because it contains
Platform information and no new features when compared to
BDW_FEATURES definition.

v4: Rebased on top of Cannonlake patches.

Cc: Anusha Srivatsa 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496937000-8450-1-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_pci.c  | 16 
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f298b39d019..45286cb870f2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -888,6 +888,7 @@ enum intel_platform {
INTEL_BROXTON,
INTEL_KABYLAKE,
INTEL_GEMINILAKE,
+   INTEL_COFFEELAKE,
INTEL_CANNONLAKE,
INTEL_MAX_PLATFORMS
 };
@@ -2753,6 +2754,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BROXTON(dev_priv)   ((dev_priv)->info.platform == INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)  ((dev_priv)->info.platform == INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)((dev_priv)->info.platform == 
INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)((dev_priv)->info.platform == 
INTEL_COFFEELAKE)
 #define IS_CANNONLAKE(dev_priv)((dev_priv)->info.platform == 
INTEL_CANNONLAKE)
 #define IS_MOBILE(dev_priv)((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1b043ed871c3..2ebe80f45293 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -430,6 +430,22 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+#define CFL_PLATFORM \
+   .is_alpha_support = 1, \
+   BDW_FEATURES, \
+   .gen = 9, \
+   .platform = INTEL_COFFEELAKE, \
+   .ddb_size = 896
+
+static const struct intel_device_info intel_coffeelake_info = {
+   CFL_PLATFORM,
+};
+
+static const struct intel_device_info intel_coffeelake_gt3_info = {
+   CFL_PLATFORM,
+   .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+};
+
 static const struct intel_device_info intel_cannonlake_info = {
BDW_FEATURES,
.is_alpha_support = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 5ae9a8084d1a..1b9b03ee948d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -51,6 +51,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(BROXTON),
PLATFORM_NAME(KABYLAKE),
PLATFORM_NAME(GEMINILAKE),
+   PLATFORM_NAME(COFFEELAKE),
PLATFORM_NAME(CANNONLAKE),
 };
 #undef PLATFORM_NAME
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 15/36] drm/i915/cnl: Add power wells for CNL

[Liwei Song]

From: Ville Syrjälä 

commit 8bcd3dd417660dce8cf38a731a888f09e8028190 upstream.

CNL power wells are very similar to SKL, with the exception that the
misc IO well has been split into separate AUX IO wells.

Not sure if DMC is supposed to manage the AUX wells for us or not.
Let's assume so for now.

v2: DDI A power well wants DDI A domains, not DDI B domains
v3: s/BIT/BIT_ULL and add proper Aux IO domains. (Rodrigo)
v4: Remove PW_DDI_E. Not supported on Current CNL SKUs. (Rodrigo).
v5: Removed DDI_E_IO_DOMAINS and moved PORT_DDI_E_IO to DDI_A_IO
for the same reasons as v4 when we found out that current CNL
SKUs don't have the full port E split.

Signed-off-by: Ville Syrjälä 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Imre Deak 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-10-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_reg.h |   5 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 136 +++-
 2 files changed, 137 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8a9a6ba32076..19ffc58c8b64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1057,6 +1057,7 @@ enum skl_disp_power_wells {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_DDI_A_E,
GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
+   CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
SKL_DISP_PW_DDI_B,
SKL_DISP_PW_DDI_C,
SKL_DISP_PW_DDI_D,
@@ -1064,6 +1065,10 @@ enum skl_disp_power_wells {
GLK_DISP_PW_AUX_A = 8,
GLK_DISP_PW_AUX_B,
GLK_DISP_PW_AUX_C,
+   CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
+   CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
+   CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
+   CNL_DISP_PW_AUX_D,
 
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f8a375f8dde6..0b3cacd29bac 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -494,6 +494,55 @@ static void hsw_set_power_well(struct drm_i915_private 
*dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_A) |   \
BIT_ULL(POWER_DOMAIN_INIT))
 
+#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (\
+   BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |\
+   BIT_ULL(POWER_DOMAIN_PIPE_B) |  \
+   BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
+   BIT_ULL(POWER_DOMAIN_PIPE_C) |  \
+   BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+   BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+   BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
+   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
+   BIT_ULL(POWER_DOMAIN_AUX_D) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_VGA) | \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (   \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |   \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (   \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (   \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (   \
+   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (  \
+   BIT_ULL(POWER_DOMAIN_AUX_A) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (  \
+   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (  \
+   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (  \
+   BIT_ULL(POWER_DOMAIN_AUX_D) |   \
+   BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+   CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+   BIT_ULL(POWER_DOMAIN_MODESET) | \
+  

[linux-yocto] [yocto-4.12][PATCH 11/36] drm/i915/cnl: add IS_CNL_REVID macro

[Liwei Song]

From: Paulo Zanoni 

commit 3c2e0fd92c194f495aaa8a8a1c86ea1b8c4bd304 upstream.

We're going to use it in the next commits.

Signed-off-by: Paulo Zanoni 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Jim Bride 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-5-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index da76f2823922..6f298b39d019 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2831,6 +2831,12 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GLK_REVID(dev_priv, since, until) \
(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
 
+#define CNL_REVID_A0   0x0
+#define CNL_REVID_B0   0x1
+
+#define IS_CNL_REVID(p, since, until) \
+   (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 14/36] drm/i915/cnl: Cannonlake has same MOCS table than Skylake.

[Liwei Song]

From: Rodrigo Vivi 

commit 1dc0766c33473d61fd85caa5031daf34f719cd3f upstream.

All registers and default configuration are the same for Skylake
and Cannonlake.

v2: Don't apply Wa for platforms without MOCS. (Paulo)

v3: Removed WaDisableSkipCaching that Joonas noticed that
according to spec it is not applicable to CNL.

Cc: Paulo Zanoni 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Joonas Lahtinen 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-8-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_mocs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index 92e461c68385..f4c46b0b8f0a 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -178,7 +178,7 @@ static bool get_mocs_settings(struct drm_i915_private 
*dev_priv,
 {
bool result = false;
 
-   if (IS_GEN9_BC(dev_priv)) {
+   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
table->size  = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 16/36] drm/i915/cnl: Also need power well sanitize.

[Liwei Song]

From: Rodrigo Vivi 

commit bf9a496a1fa434670285bd592c75d009cbb99720 upstream.

The workaround added in
commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
equests left on by DMC/KVMR")
needs to be applied on Cannonlake as well.

So let's assume any platform using this power well setup
will also need and let's just go ahead and remove if condition.

Cc: Imre Deak 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Imre Deak 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-11-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0b3cacd29bac..8a6f287d225b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -853,8 +853,7 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
}
 
-   if (IS_GEN9(dev_priv))
-   gen9_sanitize_power_well_requests(dev_priv, power_well);
+   gen9_sanitize_power_well_requests(dev_priv, power_well);
}
 
if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 07/36] drm/i915/cnl: Introduce Cannonlake platform defition.

[Liwei Song]

From: Rodrigo Vivi 

commit 413f3c19f8ecefd29067897db9c414a29d86685f upstream.

Cannonlake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.

It is Gen10.

Let's start by adding the platform definition based on previous
platforms but yet as alpha_support.

On following patches we will start adding PCI IDs and the
platform specific changes.

CNL has an increased DDB size as Damien had previously
noticed and provided a separated patch that got squashed here.

v2: Squash DDB size here per Ander request.

Credits-to: Damien Lespiau 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Ander Conselvan de Oliveira 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-1-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 +++
 drivers/gpu/drm/i915/i915_pci.c  | 8 
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3db50391679e..da76f2823922 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -888,6 +888,7 @@ enum intel_platform {
INTEL_BROXTON,
INTEL_KABYLAKE,
INTEL_GEMINILAKE,
+   INTEL_CANNONLAKE,
INTEL_MAX_PLATFORMS
 };
 
@@ -2752,6 +2753,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BROXTON(dev_priv)   ((dev_priv)->info.platform == INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)  ((dev_priv)->info.platform == INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)((dev_priv)->info.platform == 
INTEL_GEMINILAKE)
+#define IS_CANNONLAKE(dev_priv)((dev_priv)->info.platform == 
INTEL_CANNONLAKE)
 #define IS_MOBILE(dev_priv)((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2843,6 +2845,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN7(dev_priv)  (!!((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)  (!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)  (!!((dev_priv)->info.gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
 
 #define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)   (IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1a78363c7f4a..d8777276142a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -430,6 +430,14 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+static const struct intel_device_info intel_cannonlake_info = {
+   BDW_FEATURES,
+   .is_alpha_support = 1,
+   .platform = INTEL_CANNONLAKE,
+   .gen = 10,
+   .ddb_size = 1024,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 7d01dfe7faac..6b09a82468ef 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -51,6 +51,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(BROXTON),
PLATFORM_NAME(KABYLAKE),
PLATFORM_NAME(GEMINILAKE),
+   PLATFORM_NAME(CANNONLAKE),
 };
 #undef PLATFORM_NAME
 
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 13/36] drm/i915/cnl: Configure EU slice power gating.

[Liwei Song]

From: Rodrigo Vivi 

commit c7ae7e9ab2078ed987903bc6c308abe57d575a59 upstream.

Cannonlake also supports slice power gating on devices with more
than one slice as SKL. Let's assume that this is the same for SKL+
and exclude BXT only.

v2: Also remove KBL.

Signed-off-by: Rodrigo Vivi 
Reviewed-by: Joonas Lahtinen 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-7-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_device_info.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 3cc8cdbc54ff..5ae9a8084d1a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -184,16 +184,15 @@ static void gen9_sseu_info_init(struct drm_i915_private 
*dev_priv)
DIV_ROUND_UP(sseu->eu_total,
 sseu_subslice_total(sseu)) : 0;
/*
-* SKL supports slice power gating on devices with more than
+* SKL+ supports slice power gating on devices with more than
 * one slice, and supports EU power gating on devices with
-* more than one EU pair per subslice. BXT supports subslice
+* more than one EU pair per subslice. BXT+ supports subslice
 * power gating on devices with more than one subslice, and
 * supports EU power gating on devices with more than one EU
 * pair per subslice.
*/
sseu->has_slice_pg =
-   (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
-   hweight8(sseu->slice_mask) > 1;
+   !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
sseu->has_subslice_pg =
IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 10/36] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.

[Liwei Song]

From: Rodrigo Vivi 

commit 95578277cbdb60e3c68cb92c843cafc1f77c4f55 upstream.

By the Spec all CNL Y skus are 2+2, i.e. GT2.

v2: Really include the PCI IDs to the picidlist[];

Reviewed-by: Anusha Srivatsa 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-4-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 include/drm/i915_pciids.h | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7f1bb3b0ce5b..7d2696a6588e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -341,7 +341,17 @@
INTEL_VGA_DEVICE(0x5A42, info), \
INTEL_VGA_DEVICE(0x5A4A, info)
 
+/* CNL Y 2+2 */
+#define INTEL_CNL_Y_GT2_IDS(info) \
+   INTEL_VGA_DEVICE(0x5A51, info), \
+   INTEL_VGA_DEVICE(0x5A59, info), \
+   INTEL_VGA_DEVICE(0x5A41, info), \
+   INTEL_VGA_DEVICE(0x5A49, info), \
+   INTEL_VGA_DEVICE(0x5A71, info), \
+   INTEL_VGA_DEVICE(0x5A79, info)
+
 #define INTEL_CNL_IDS(info) \
-   INTEL_CNL_U_GT2_IDS(info)
+   INTEL_CNL_U_GT2_IDS(info), \
+   INTEL_CNL_Y_GT2_IDS(info)
 
 #endif /* _I915_PCIIDS_H */
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 12/36] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

[Liwei Song]

From: James Irwin 

commit 8366be98f6792419ac2e19648391988edec7a7fe upstream.

Issue: VIZ-4525

Reviewed-by: Damien Lespiau 
Signed-off-by: James Irwin 
Signed-off-by: Damien Lespiau 
Reviewed-by: Ander Conselvan de Oliveira 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-6-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 6b09a82468ef..3cc8cdbc54ff 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -328,7 +328,7 @@ void intel_device_info_runtime_init(struct drm_i915_private 
*dev_priv)
 * we don't expose the topmost plane at all to prevent ABI breakage
 * down the line.
 */
-   if (IS_GEMINILAKE(dev_priv))
+   if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
for_each_pipe(dev_priv, pipe)
info->num_sprites[pipe] = 3;
else if (IS_BROXTON(dev_priv)) {
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 09/36] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

[Liwei Song]

From: Rodrigo Vivi 

commit e918d79a5d0a1b431e2cac0e6e6ac9452fd9ab32 upstream.

Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is also the new Spec style what makes the review much
more easy and straightforward.

v2: Really include the PCI IDs to the picidlist[];
v3: Remove PCI IDs not present in spec.
v4: Rebase.

Signed-off-by: Anusha Srivatsa 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Clinton Taylor 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-3-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_pci.c |  1 +
 include/drm/i915_pciids.h   | 10 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8777276142a..1b043ed871c3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -482,6 +482,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_KBL_GT2_IDS(_kabylake_info),
INTEL_KBL_GT3_IDS(_kabylake_gt3_info),
INTEL_KBL_GT4_IDS(_kabylake_gt3_info),
+   INTEL_CNL_IDS(_cannonlake_info),
{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 27e0dbaa6c0e..7f1bb3b0ce5b 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -334,4 +334,14 @@
INTEL_KBL_GT3_IDS(info), \
INTEL_KBL_GT4_IDS(info)
 
+/* CNL U 2+2 */
+#define INTEL_CNL_U_GT2_IDS(info) \
+   INTEL_VGA_DEVICE(0x5A52, info), \
+   INTEL_VGA_DEVICE(0x5A5A, info), \
+   INTEL_VGA_DEVICE(0x5A42, info), \
+   INTEL_VGA_DEVICE(0x5A4A, info)
+
+#define INTEL_CNL_IDS(info) \
+   INTEL_CNL_U_GT2_IDS(info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 08/36] drm/i915/cnl: Cannonlake uses CNP PCH.

[Liwei Song]

From: Rodrigo Vivi 

commit acf1dba661e908e923320b4226bad4d8fc23c6f5 upstream.

Avoid warning when CNP is detected with CNL.

Also let's force it on the virtual detection.

Signed-off-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-2-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1501bf7471b6..f79b1b4ea853 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct 
drm_i915_private *dev_priv)
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
ret = PCH_SPT;
DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
+   } else if (IS_CANNONLAKE(dev_priv)) {
+   ret = PCH_CNP;
}
 
return ret;
@@ -222,9 +224,11 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+   WARN_ON(!IS_CANNONLAKE(dev_priv));
} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
+   WARN_ON(!IS_CANNONLAKE(dev_priv));
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 03/36] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.

[Liwei Song]

From: Rodrigo Vivi 

commit 9d81a99713bc29b2f96403b8f7c1720e1b277b35 upstream.

RAWCLK_FREQ register has changed for platforms with CNP+.

[29:26] This field provides the denominator for the fractional
part of the microsecond counter divider.  The numerator
is fixed at 1. Program this field to the denominator of
the fractional portion of reference frequency minus one.
If the fraction is 0, program to 0.
0100b = Fraction .2 MHz = Fraction 1/5.
b = Fraction .0 MHz.

[25:16] This field provides the integer part of the microsecond
counter divider. Program this field to the integer portion
of the reference frequenct minus one.

Also this register tells us that proper raw clock should be read
from SFUSE_STRAP and programmed to this register. Up to this point
on other platforms we are reading instead of programming it so
probably relying on whatever BIOS had configured here.

Now on let's follow the spec and also program this register
fetching the right value from SFUSE_STRAP as Spec tells us to do.

v2: Read from SFUSE_STRAP and Program RAWCLK_FREQ instead of
reading the value relying someone else will program that
for us.
v3: Add missing else. (Jani)
v4: Addressing all Ville's catches:
Use macro for shift bits instead of defining shift.
Remove shift from the cleaning bits with mask that already
has it.
Add missing I915_WRITE to actually write the reg.
Stop using useless DIV_ROUND_* on divider that is exact
dividion and use DIV_ROUND_CLOSEST for the fraction part.
v5: Remove useless Read-Modify-Write on raclk_freq reg. (Ville).
v6: Change is per PCH instead of per platform.

Cc: Ville Syrjälä 
Cc: Jani Nikula 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Ville Syrjälä 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-3-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_reg.h|  5 +
 drivers/gpu/drm/i915/intel_cdclk.c | 29 -
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65b837e96fe6..fed73c543d0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6840,6 +6840,10 @@ enum {
 #define  FDL_TP2_TIMER_SHIFT10
 #define  FDL_TP2_TIMER_MASK (3<<10)
 #define  RAWCLK_FREQ_MASK   0x3ff
+#define  CNP_RAWCLK_DIV_MASK   (0x3ff << 16)
+#define  CNP_RAWCLK_DIV(div)   ((div) << 16)
+#define  CNP_RAWCLK_FRAC_MASK  (0xf << 26)
+#define  CNP_RAWCLK_FRAC(frac) ((frac) << 26)
 
 #define PCH_DPLL_TMR_CFG_MMIO(0xc6208)
 
@@ -8150,6 +8154,7 @@ enum {
 /* SFUSE_STRAP */
 #define SFUSE_STRAP_MMIO(0xc2014)
 #define  SFUSE_STRAP_FUSE_LOCK (1<<13)
+#define  SFUSE_STRAP_RAW_FREQUENCY (1<<8)
 #define  SFUSE_STRAP_DISPLAY_DISABLED  (1<<7)
 #define  SFUSE_STRAP_CRT_DISABLED  (1<<6)
 #define  SFUSE_STRAP_DDIB_DETECTED (1<<2)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index 6808f82ffb5d..6b681dc3abd3 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1790,6 +1790,30 @@ void intel_update_cdclk(struct drm_i915_private 
*dev_priv)
   DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
 }
 
+static int cnp_rawclk(struct drm_i915_private *dev_priv)
+{
+   u32 rawclk;
+   int divider, fraction;
+
+   if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
+   /* 24 MHz */
+   divider = 24000;
+   fraction = 0;
+   } else {
+   /* 19.2 MHz */
+   divider = 19000;
+   fraction = 200;
+   }
+
+   rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
+   if (fraction)
+   rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
+   fraction) - 1);
+
+   I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
+   return divider + fraction;
+}
+
 static int pch_rawclk(struct drm_i915_private *dev_priv)
 {
return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
@@ -1837,7 +1861,10 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 {
-   if (HAS_PCH_SPLIT(dev_priv))
+
+   if (HAS_PCH_CNP(dev_priv))
+   dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
+   else if (HAS_PCH_SPLIT(dev_priv))
dev_priv->rawclk_freq = pch_rawclk(dev_priv);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
-- 
2.7.4

-- 
___
linux-yocto mailing list

[linux-yocto] [yocto-4.12][PATCH 05/36] drm/i915/cnp: add CNP gmbus support

[Liwei Song]

From: Rodrigo Vivi 

commit 3d02352cd9e8b43805bf68e50e395fda2e218791 upstream.

On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.

v2: Don't drop "_BXT" as the indicator of the first platform
supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
Re-add pin 4 for port D. Lost during some rebase.
v5: Use table as spec. If VBT is wrong it should be ignored.

Cc: Daniel Vetter 
Cc: Jani Nikula 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-5-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
 drivers/gpu/drm/i915/intel_hdmi.c |  8 +---
 drivers/gpu/drm/i915/intel_i2c.c  | 15 +--
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fed73c543d0c..8a9a6ba32076 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_DPB5 /* SDVO, HDMIB */
 #define   GMBUS_PIN_DPD6 /* HDMID */
 #define   GMBUS_PIN_RESERVED   7 /* 7 reserved */
-#define   GMBUS_PIN_1_BXT  1
+#define   GMBUS_PIN_1_BXT  1 /* BXT+ (atom) and CNP+ (big core) */
 #define   GMBUS_PIN_2_BXT  2
 #define   GMBUS_PIN_3_BXT  3
+#define   GMBUS_PIN_4_CNP  4
 #define   GMBUS_NUM_PINS   7 /* including 0 */
 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* 
command/status */
 #define   GMBUS_SW_CLR_INT (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 1d623b5e09d6..94241c84ede7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private 
*dev_priv,
 
switch (port) {
case PORT_B:
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT;
else
ddc_pin = GMBUS_PIN_DPB;
break;
case PORT_C:
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT;
else
ddc_pin = GMBUS_PIN_DPC;
break;
case PORT_D:
-   if (IS_CHERRYVIEW(dev_priv))
+   if (HAS_PCH_CNP(dev_priv))
+   ddc_pin = GMBUS_PIN_4_CNP;
+   else if (IS_CHERRYVIEW(dev_priv))
ddc_pin = GMBUS_PIN_DPD_CHV;
else
ddc_pin = GMBUS_PIN_DPD;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b6401e8f1bd6..3c9e00d4ba5a 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,20 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 };
 
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+   [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+   [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+   [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
+   [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 unsigned int pin)
 {
-   if (IS_GEN9_LP(dev_priv))
+   if (HAS_PCH_CNP(dev_priv))
+   return _pins_cnp[pin];
+   else if (IS_GEN9_LP(dev_priv))
return _pins_bxt[pin];
else if (IS_GEN9_BC(dev_priv))
return _pins_skl[pin];
@@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private 
*dev_priv,
 {
unsigned int size;
 
-   if (IS_GEN9_LP(dev_priv))
+   if (HAS_PCH_CNP(dev_priv))
+   size = ARRAY_SIZE(gmbus_pins_cnp);
+   else if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_GEN9_BC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 04/36] drm/i915/cnp: Backlight support for CNP.

[Liwei Song]

From: Rodrigo Vivi 

commit 4c9f7086ac6d069d5b79ba37ef4f1ed4fa3dc3f7 upstream.

Split out BXT and CNP's setup_backlight(),enable_backlight(),
disable_backlight() and hz_to_pwm() into
two separate functions instead of reusing BXT function.

Reuse set_backlight() and get_backlight() since they have
no reference to the utility pin.

v2: Reuse BXT functions with controller 0 instead of
redefining it. (Jani).
Use dev_priv->rawclk_freq instead of getting the value
from SFUSE_STRAP.
v3: Avoid setup backligh controller along with hooks and
fully reuse hooks setup as suggested by Jani.
v4: Clean up commit message.
v5: Implement per PCH instead per platform.

v6: Introduce a new function for CNP.(Jani and Ville)

v7: Squash the all CNP Backlight support patches into a
single patch. (Jani)

v8: Correct indentation, remove unneeded blank lines and
correct mail address (Jani).

v9: Remove unused enum pipe. (by CI)

v10: Remove comment mentioning SFUSE_STRAP in a part of
 the code that we don't use it. (Jani)
 Make controller = 0 since current CNP has only one
 controller and put a comment mentioning why we
 reuse the BXT definitions and are keeping the
 controller = 0. (DK)
v11: Remove spurious line. (DK)

Reviewed-by: Dhinakaran Pandiyan 
Reviewed-by: Jani Nikula 
Suggested-by: Jani Nikula 
Suggested-by: Ville Syrjala 
Cc: Ville Syrjala 
Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Rodrigo Vivi 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-4-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_panel.c | 96 ++
 1 file changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index cb50c527401f..a51acf17ac86 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector 
*connector)
}
 }
 
+static void cnp_disable_backlight(struct intel_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   struct intel_panel *panel = >panel;
+   u32 tmp;
+
+   intel_panel_actually_set_backlight(connector, 0);
+
+   tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+   I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+  tmp & ~BXT_BLC_PWM_ENABLE);
+}
+
 static void pwm_disable_backlight(struct intel_connector *connector)
 {
struct intel_panel *panel = >panel;
@@ -1076,6 +1089,35 @@ static void bxt_enable_backlight(struct intel_connector 
*connector)
pwm_ctl | BXT_BLC_PWM_ENABLE);
 }
 
+static void cnp_enable_backlight(struct intel_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   struct intel_panel *panel = >panel;
+   u32 pwm_ctl;
+
+   pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+   if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
+   DRM_DEBUG_KMS("backlight already enabled\n");
+   pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
+   I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+  pwm_ctl);
+   }
+
+   I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+  panel->backlight.max);
+
+   intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+   pwm_ctl = 0;
+   if (panel->backlight.active_low_pwm)
+   pwm_ctl |= BXT_BLC_PWM_POLARITY;
+
+   I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+   POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+   I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+  pwm_ctl | BXT_BLC_PWM_ENABLE);
+}
+
 static void pwm_enable_backlight(struct intel_connector *connector)
 {
struct intel_panel *panel = >panel;
@@ -1239,6 +1281,17 @@ void intel_backlight_device_unregister(struct 
intel_connector *connector)
 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
 
 /*
+ * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
+ *  PWM increment = 1
+ */
+static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+
+   return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
+}
+
+/*
  * BXT: PWM clock frequency = 19.2 MHz.
  */
 static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
@@ -1633,6 +1686,42 @@ bxt_setup_backlight(struct intel_connector *connector, 
enum pipe unused)
return 0;
 }
 
+static int

[linux-yocto] [yocto-4.12][PATCH 06/36] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Liwei Song]

From: Rodrigo Vivi 

commit 938361e7a50619b76a1415c86438eaee41397220 upstream.

Panel Power sequences for CNP is similar to Broxton,
but with only one sequencer.

Main difference from SPT is that PP_DIVISOR was removed
and power cycle delay has been moved to PP_CONTROL.

v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
as on Broxton. (Found by DK)

v3: Improve commit message. (By DK)

Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Clinton Taylor 
Reviewed-by: Dhinakaran Pandiyan 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-6-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8a883e9abedd..93075873bb2f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -754,7 +754,7 @@ static void intel_pps_get_registers(struct drm_i915_private 
*dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
-   if (!IS_GEN9_LP(dev_priv))
+   if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
 }
 
@@ -5150,7 +5150,7 @@ intel_pps_readout_hw_state(struct drm_i915_private 
*dev_priv,
 
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
-   if (!IS_GEN9_LP(dev_priv)) {
+   if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -5168,7 +5168,7 @@ intel_pps_readout_hw_state(struct drm_i915_private 
*dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5325,7 +5325,7 @@ intel_dp_init_panel_power_sequencer_registers(struct 
drm_device *dev,
 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
 * formula. */
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5351,7 +5351,7 @@ intel_dp_init_panel_power_sequencer_registers(struct 
drm_device *dev,
 
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5359,7 +5359,7 @@ intel_dp_init_panel_power_sequencer_registers(struct 
drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, 
PP_OFF %#x, PP_DIV %#x\n",
  I915_READ(regs.pp_on),
  I915_READ(regs.pp_off),
- IS_GEN9_LP(dev_priv) ?
+ (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
  (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
  I915_READ(regs.pp_div));
 }
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 02/36] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

[Liwei Song]

From: Dhinakaran Pandiyan 

commit ec7e0bb35f8d339b51b440b5fc525618784f11f4 upstream.

The first two bytes of PCI ID for CNP_LP PCH are the same as that of
SPT_LP. We should really be looking at the first 9 bits instead of the
first 8 to identify platforms, although this seems to have not caused any
problems on earlier platforms. Introduce a 9 bit extended mask for SPT and
CNP while not touching the code for any of the other platforms.

v2: (Rodrigo) Make platform agnostic and fix commit message.

Signed-off-by: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-2-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.c | 8 +++-
 drivers/gpu/drm/i915/i915_drv.h | 4 
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5dbb430f3f6f..1501bf7471b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -170,6 +170,9 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
unsigned short id = pch->device & 
INTEL_PCH_DEVICE_ID_MASK;
+   unsigned short id_ext = pch->device &
+   INTEL_PCH_DEVICE_ID_MASK_EXT;
+
dev_priv->pch_id = id;
 
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
@@ -206,7 +209,7 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
-   } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
+   } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
@@ -219,6 +222,9 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+   } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
+   dev_priv->pch_type = PCH_CNP;
+   DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b06d3c269d78..3db50391679e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2942,6 +2942,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_POOLED_EU(dev_priv)((dev_priv)->info.has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK   0xff00
+#define INTEL_PCH_DEVICE_ID_MASK_EXT   0xff80
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE   0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE   0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE   0x1e00
@@ -2951,12 +2952,15 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE0x9D00
 #define INTEL_PCH_KBP_DEVICE_ID_TYPE   0xA200
 #define INTEL_PCH_CNP_DEVICE_ID_TYPE   0xA300
+#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE0x9D80
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE   0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE   0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE  0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
+#define HAS_PCH_CNP_LP(dev_priv) \
+   ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 01/36] drm/i915/cnp: Introduce Cannonpoint PCH.

[Liwei Song]

From: Rodrigo Vivi 

commit 7b22b8c402c8ee26dd4dc1474887a2a91961e766 upstream.

Most of south engine display that is in PCH is still the
same as SPT and KBP, except for this key differences:

- Backlight: Backlight programming changed in CNP PCH.
- Panel Power: Sligh programming changed in CNP PCH.
- GMBUS and GPIO: The pin mapping has changed in CNP PCH.

All of these changes follow more the BXT style.

v2: Update definition to use dev_priv isntead of dev (Tvrtko).

Cc: Tvrtko Ursulin 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-1-git-send-email-rodrigo.v...@intel.com
Signed-off-by: Liwei Song 
---
 drivers/gpu/drm/i915/i915_drv.c | 3 +++
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 drivers/gpu/drm/i915/i915_irq.c | 6 --
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6ac8d37e7ab8..5dbb430f3f6f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -216,6 +216,9 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
+   } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
+   dev_priv->pch_type = PCH_CNP;
+   DRM_DEBUG_KMS("Found CannonPoint PCH\n");
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c453a4e97d5..b06d3c269d78 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1210,6 +1210,7 @@ enum intel_pch {
PCH_LPT,/* Lynxpoint PCH */
PCH_SPT,/* Sunrisepoint PCH */
PCH_KBP,/* Kabypoint PCH */
+   PCH_CNP,/* Cannonpoint PCH */
PCH_NOP,
 };
 
@@ -2949,11 +2950,13 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define INTEL_PCH_SPT_DEVICE_ID_TYPE   0xA100
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE0x9D00
 #define INTEL_PCH_KBP_DEVICE_ID_TYPE   0xA200
+#define INTEL_PCH_CNP_DEVICE_ID_TYPE   0xA300
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE   0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE   0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE  0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
+#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 190f6aa5d15e..6316bb2096f6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2582,7 +2582,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
I915_WRITE(SDEIIR, iir);
ret = IRQ_HANDLED;
 
-   if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+   if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+   HAS_PCH_CNP(dev_priv))
spt_irq_handler(dev_priv, iir);
else
cpt_irq_handler(dev_priv, iir);
@@ -4319,7 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->disable_vblank = gen8_disable_vblank;
if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
-   else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+   else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+HAS_PCH_CNP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

[linux-yocto] [yocto-4.12][PATCH 00/36] add graphic and audio support for CFL-S

[Liwei Song]

These 36 upstream patches use to enable graphic and
audio support for CoffeeLake-s board.
Some cnl patches were backported due to dependency.


Anusha Srivatsa (5):
  drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.
  drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.
  drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.
  drm/i915/guc: Load GuC on Coffee Lake
  drm/i915/huc: Load HuC on Coffee Lake

Dhinakaran Pandiyan (1):
  drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

Guneshwor Singh (1):
  ALSA: hda: Add Cannonlake PCI ID

James Irwin (1):
  drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

Kailang Yang (1):
  ALSA: hda/realtek - Fix ALC700 family no sound issue

Paulo Zanoni (1):
  drm/i915/cnl: add IS_CNL_REVID macro

PeiSen Hou (1):
  ALSA: hda/realtek - Enable jack detection function for Intel ALC700

Rodrigo Vivi (16):
  drm/i915/cnp: Introduce Cannonpoint PCH.
  drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
  drm/i915/cnp: Backlight support for CNP.
  drm/i915/cnp: add CNP gmbus support
  drm/i915/cnp: Panel Power sequence changes for CNP PCH.
  drm/i915/cnl: Introduce Cannonlake platform defition.
  drm/i915/cnl: Cannonlake uses CNP PCH.
  drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
  drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
  drm/i915/cnl: Configure EU slice power gating.
  drm/i915/cnl: Cannonlake has same MOCS table than Skylake.
  drm/i915/cnl: Also need power well sanitize.
  drm/i915/cfl: Introduce Coffee Lake platform definition.
  drm/i915/cfl: Coffee Lake uses CNP PCH.
  drm/i915/cfl: Introduce Display workarounds for Coffee Lake.
  drm/i915/cfl: Coffee Lake reuses Kabylake DMC.

Takashi Iwai (5):
  ALSA: hda - Add AZX_DRIVER_SKL for simplification
  ALSA: hda - Bind with i915 component before codec binding
  ALSA: hda - Fix doubly initialization of i915 component
  ALSA: hda - Fix unbalance of i915 module refcount
  ALSA: hda - Add model string for Intel reference board quirk

Ville Syrjälä (4):
  drm/i915/cnl: Add power wells for CNL
  drm/i915/cnl: Implement .get_display_clock_speed() for CNL
  drm/i915/cnl: Implement .set_cdclk() for CNL
  drm/i915/cnl: Implement CNL display init/unit sequence

 Documentation/sound/hd-audio/models.rst  |   2 +
 drivers/gpu/drm/i915/i915_drv.c  |  18 +-
 drivers/gpu/drm/i915/i915_drv.h  |  18 ++
 drivers/gpu/drm/i915/i915_irq.c  |   6 +-
 drivers/gpu/drm/i915/i915_pci.c  |  30 
 drivers/gpu/drm/i915/i915_reg.h  |  41 -
 drivers/gpu/drm/i915/intel_cdclk.c   | 297 ++-
 drivers/gpu/drm/i915/intel_csr.c |   4 +-
 drivers/gpu/drm/i915/intel_device_info.c |  11 +-
 drivers/gpu/drm/i915/intel_dp.c  |  12 +-
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 drivers/gpu/drm/i915/intel_guc_loader.c  |   2 +-
 drivers/gpu/drm/i915/intel_hdmi.c|   8 +-
 drivers/gpu/drm/i915/intel_huc.c |   2 +-
 drivers/gpu/drm/i915/intel_i2c.c |  15 +-
 drivers/gpu/drm/i915/intel_mocs.c|   2 +-
 drivers/gpu/drm/i915/intel_panel.c   |  96 ++
 drivers/gpu/drm/i915/intel_pm.c  |  21 +--
 drivers/gpu/drm/i915/intel_runtime_pm.c  | 252 +-
 include/drm/i915_pciids.h|  40 +
 sound/pci/hda/hda_controller.h   |   6 +-
 sound/pci/hda/hda_intel.c| 115 ++--
 sound/pci/hda/patch_hdmi.c   |  17 +-
 sound/pci/hda/patch_realtek.c|  20 ++-
 24 files changed, 925 insertions(+), 112 deletions(-)

-- 
2.7.4

-- 
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[qwang2]

On 2018年01月10日 11:11, Bruce Ashfield wrote:

On 2018-01-09 9:07 PM, qwang2 wrote:

Hi Bruce,

This commit is based on the patches at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html.


It seems that those patches hasn't been merged, would you please help 
to check it?


Send them all in a completes series.

Hi Bruce,

I made all these patches in a completes series, and they are at the 
git-tree as below.


Thanks,
Quanyang

The following changes since commit 4226b065fca4f630901d99b99d18c395ae3866fb:

  ipv4: net namespace does not inherit network configurations 
(2017-12-05 17:17:05 -0500)


are available in the git repository at:

  https://github.com/wangquanyang/linux-yocto-4.12.git standard/base

for you to fetch changes up to 1d07c0cde181b7746c6091dc276ff6a205d5ca23:

  x86/intel_rdt: Turn off most RDT features on Skylake (2018-01-10 
13:13:22 +0800)



Alexei Starovoitov (1):
  perf, bpf: Add BPF support to all perf_event types

Arnaldo Carvalho de Melo (5):
  tools: Adopt __noreturn from kernel sources
  perf event-parse: Use pr_warning()
  tools: Adopt __printf from kernel sources
  perf tools: Remove warning()
  perf test: Add 'struct test *' to the test functions

Colin Ian King (2):
  x86/intel_rdt: Remove redundant ternary operator on return
  x86/intel_rdt/cqm: Make integer rmid_limbo_count static

Fenghua Yu (1):
  x86/intel_rdt: Show bitmask of shareable resource with other 
executing units


Jithu Joseph (1):
  x86/intel_rdt: Remove redundant assignment

Reinette Chatre (2):
  x86/intel_rdt: Mark rdt_root and closid_alloc as static
  x86/intel_rdt: Initialize bitmask of shareable resource if CDP 
enabled


Sebastian Andrzej Siewior (1):
  perf/x86/intel/cqm: Use cpuhp_setup_state_cpuslocked()

Tony Luck (10):
  x86/intel_rdt: Simplify info and base file lists
  x86/intel_rdt/mbm: Basic counting of MBM events (total and local)
  x86/intel_rdt: Add framework for better RDT UI diagnostics
  x86/intel_rdt: Add diagnostics when writing the schemata file
  x86/intel_rdt: Add diagnostics when writing the tasks file
  x86/intel_rdt: Add diagnostics when writing the cpus file
  x86/intel_rdt: Add diagnostics when making directories
  x86/intel_rdt: Move special case code for Haswell to a quirk function
  x86/intel_rdt: Add command line options for resource director 
technology

  x86/intel_rdt: Turn off most RDT features on Skylake

Vikas Shivappa (29):
  x86/perf/cqm: Wipe out perf based cqm
  x86/intel_rdt/cqm: Documentation for resctrl based RDT Monitoring
  x86/intel_rdt: Introduce a common compile option for RDT
  x86/intel_rdt: Change file names to accommodate RDT monitor code
  x86/intel_rdt: Cleanup namespace to support RDT monitoring
  x86/intel_rdt: Make rdt_resources_all more readable
  x86/intel_rdt/cqm: Add RDT monitoring initialization
  x86/intel_rdt/cqm: Add RMID (Resource monitoring ID) management
  x86/intel_rdt/cqm: Add info files for RDT monitoring
  x86/intel_rdt: Prepare for RDT monitoring mkdir support
  x86/intel_rdt/cqm: Add mkdir support for RDT monitoring
  x86/intel_rdt: Change closid type from int to u32
  x86/intel_rdt/cqm: Add tasks file support
  x86/intel_rdt: Prepare to add RDT monitor cpus file support
  x86/intel_rdt/cqm: Add cpus file support
  x86/intel_rdt: Prepare for RDT monitor data support
  x86/intel_rdt/cqm: Add mon_data
  x86/intel_rdt: Separate the ctrl bits from rmdir
  x86/intel_rdt/cqm: Add rmdir support
  x86/intel_rdt/cqm: Add mount,umount support
  x86/intel_rdt: Introduce rdt_enable_key for scheduling
  x86/intel_rdt/cqm: Add sched_in support
  x86/intel_rdt/cqm: Add CPU hotplug support
  x86/intel_rdt/mbm: Add mbm counter initialization
  x86/intel_rdt/mbm: Handle counter overflow
  x86/intel_rdt/mbm: Fix MBM overflow handler during CPU hotplug
  x86/intel_rdt/cqm: Improve limbo list processing
  x86/intel_rdt/cqm: Clear the default RMID during hotcpu
  x86/intel_rdt: Modify the intel_pqr_state for better performance

Xiaochen Shen (2):
  x86/intel_rdt: Fix a silent failure when writing zero value schemata
  perf tests: Remove Intel CQM perf test

 Documentation/admin-guide/kernel-parameters.rst |1 +
 Documentation/admin-guide/kernel-parameters.txt |6 +
 Documentation/x86/intel_rdt_ui.txt |  323 --
 MAINTAINERS |2 +-
 arch/x86/Kconfig |   12 +-
 arch/x86/events/intel/Makefile |2 +-
 arch/x86/events/intel/cqm.c   
| 1766 
-

 arch/x86/include/asm/intel_rdt.h |  286 
 arch/x86/include/asm/intel_rdt_common.h |   27 --
 arch/x86/include/asm/intel_rdt_sched.h |   92 
 

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[Bruce Ashfield]

On 2018-01-09 9:07 PM, qwang2 wrote:

Hi Bruce,

This commit is based on the patches at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html.


It seems that those patches hasn't been merged, would you please help to 
check it?


Send them all in a completes series.

What I have in the tree, is what I have merged. If you have
dependencies that aren't in my tree, send them as part of a
combined series.

Bruce



Thanks,

Quanyang


On 2018年01月10日 02:19, Bruce Ashfield wrote:

This series doesn't apply to the current 4.12:

-
Applying: x86/intel_rdt: Move special case code for Haswell to a quirk 
function

error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172
error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply
Patch failed at 0001 x86/intel_rdt: Move special case code for Haswell 
to a quirk function

The copy of the patch that failed is found in:
/home/bruce/poky-kernel/linux-yocto-4.12.git/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---

Can you double check that the 4.12 you used to generate this series
matches what I have staged on git.yoctoproject.org.

Bruce

On 01/08/2018 10:20 PM, quanyang.w...@windriver.com wrote:

From: Tony Luck 

commit 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 upstream

No functional change, but lay the ground work for other per-model
quirks.

Signed-off-by: Tony Luck 
Signed-off-by: Thomas Gleixner 
Cc: Fenghua" 
Cc: Ravi V" 
Cc: "Peter Zijlstra" 
Cc: "Stephane Eranian" 
Cc: "Andi Kleen" 
Cc: "David Carrillo-Cisneros" 
Cc: Vikas Shivappa 
Link: 
http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.l...@intel.com 


---
  arch/x86/kernel/cpu/intel_rdt.c | 52 
++---

  1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_rdt.c 
b/arch/x86/kernel/cpu/intel_rdt.c

index dfc7c48..5af2f8f 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource 
*r, unsigned int closid)

   * is always 20 on hsw server parts. The minimum cache bitmask length
   * allowed for HSW server is always 2 bits. Hardcode all of them.
   */
-static inline bool cache_alloc_hsw_probe(void)
+static inline void cache_alloc_hsw_probe(void)
  {
-    if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-    boot_cpu_data.x86 == 6 &&
-    boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
-    struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
-    u32 l, h, max_cbm = BIT_MASK(20) - 1;
+    struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
+    u32 l, h, max_cbm = BIT_MASK(20) - 1;
  -    if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
-    return false;
-    rdmsr(IA32_L3_CBM_BASE, l, h);
-
-    /* If all the bits were set in MSR, return success */
-    if (l != max_cbm)
-    return false;
+    if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+    return;
+    rdmsr(IA32_L3_CBM_BASE, l, h);
  -    r->num_closid = 4;
-    r->default_ctrl = max_cbm;
-    r->cache.cbm_len = 20;
-    r->cache.shareable_bits = 0xc;
-    r->cache.min_cbm_bits = 2;
-    r->alloc_capable = true;
-    r->alloc_enabled = true;
+    /* If all the bits were set in MSR, return success */
+    if (l != max_cbm)
+    return;
  -    return true;
-    }
+    r->num_closid = 4;
+    r->default_ctrl = max_cbm;
+    r->cache.cbm_len = 20;
+    r->cache.shareable_bits = 0xc;
+    r->cache.min_cbm_bits = 2;
+    r->alloc_capable = true;
+    r->alloc_enabled = true;
  -    return false;
+    rdt_alloc_capable = true;
  }
    /*
@@ -648,7 +642,7 @@ static __init bool get_rdt_alloc_resources(void)
  {
  bool ret = false;
  -    if (cache_alloc_hsw_probe())
+    if (rdt_alloc_capable)
  return true;
    if (!boot_cpu_has(X86_FEATURE_RDT_A))
@@ -690,8 +684,18 @@ static __init bool get_rdt_mon_resources(void)
  return 
!rdt_get_mon_l3_config(_resources_all[RDT_RESOURCE_L3]);

  }
  +static __init void rdt_quirks(void)
+{
+    switch (boot_cpu_data.x86_model) {
+    case INTEL_FAM6_HASWELL_X:
+    cache_alloc_hsw_probe();
+    break;
+    }
+}
+
  static __init bool get_rdt_resources(void)
  {
+    rdt_quirks();
  rdt_alloc_capable = get_rdt_alloc_resources();
  rdt_mon_capable = get_rdt_mon_resources();








--
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[qwang2]

Hi Bruce,

This commit is based on the patches at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html.


It seems that those patches hasn't been merged, would you please help to 
check it?


Thanks,

Quanyang


On 2018年01月10日 02:19, Bruce Ashfield wrote:

This series doesn't apply to the current 4.12:

-
Applying: x86/intel_rdt: Move special case code for Haswell to a quirk 
function

error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172
error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply
Patch failed at 0001 x86/intel_rdt: Move special case code for Haswell 
to a quirk function

The copy of the patch that failed is found in:
/home/bruce/poky-kernel/linux-yocto-4.12.git/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---

Can you double check that the 4.12 you used to generate this series
matches what I have staged on git.yoctoproject.org.

Bruce

On 01/08/2018 10:20 PM, quanyang.w...@windriver.com wrote:

From: Tony Luck 

commit 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 upstream

No functional change, but lay the ground work for other per-model
quirks.

Signed-off-by: Tony Luck 
Signed-off-by: Thomas Gleixner 
Cc: Fenghua" 
Cc: Ravi V" 
Cc: "Peter Zijlstra" 
Cc: "Stephane Eranian" 
Cc: "Andi Kleen" 
Cc: "David Carrillo-Cisneros" 
Cc: Vikas Shivappa 
Link: 
http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.l...@intel.com

---
  arch/x86/kernel/cpu/intel_rdt.c | 52 
++---

  1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_rdt.c 
b/arch/x86/kernel/cpu/intel_rdt.c

index dfc7c48..5af2f8f 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource 
*r, unsigned int closid)

   * is always 20 on hsw server parts. The minimum cache bitmask length
   * allowed for HSW server is always 2 bits. Hardcode all of them.
   */
-static inline bool cache_alloc_hsw_probe(void)
+static inline void cache_alloc_hsw_probe(void)
  {
-if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-boot_cpu_data.x86 == 6 &&
-boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
-struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
-u32 l, h, max_cbm = BIT_MASK(20) - 1;
+struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
+u32 l, h, max_cbm = BIT_MASK(20) - 1;
  -if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
-return false;
-rdmsr(IA32_L3_CBM_BASE, l, h);
-
-/* If all the bits were set in MSR, return success */
-if (l != max_cbm)
-return false;
+if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+return;
+rdmsr(IA32_L3_CBM_BASE, l, h);
  -r->num_closid = 4;
-r->default_ctrl = max_cbm;
-r->cache.cbm_len = 20;
-r->cache.shareable_bits = 0xc;
-r->cache.min_cbm_bits = 2;
-r->alloc_capable = true;
-r->alloc_enabled = true;
+/* If all the bits were set in MSR, return success */
+if (l != max_cbm)
+return;
  -return true;
-}
+r->num_closid = 4;
+r->default_ctrl = max_cbm;
+r->cache.cbm_len = 20;
+r->cache.shareable_bits = 0xc;
+r->cache.min_cbm_bits = 2;
+r->alloc_capable = true;
+r->alloc_enabled = true;
  -return false;
+rdt_alloc_capable = true;
  }
/*
@@ -648,7 +642,7 @@ static __init bool get_rdt_alloc_resources(void)
  {
  bool ret = false;
  -if (cache_alloc_hsw_probe())
+if (rdt_alloc_capable)
  return true;
if (!boot_cpu_has(X86_FEATURE_RDT_A))
@@ -690,8 +684,18 @@ static __init bool get_rdt_mon_resources(void)
  return 
!rdt_get_mon_l3_config(_resources_all[RDT_RESOURCE_L3]);

  }
  +static __init void rdt_quirks(void)
+{
+switch (boot_cpu_data.x86_model) {
+case INTEL_FAM6_HASWELL_X:
+cache_alloc_hsw_probe();
+break;
+}
+}
+
  static __init bool get_rdt_resources(void)
  {
+rdt_quirks();
  rdt_alloc_capable = get_rdt_alloc_resources();
  rdt_mon_capable = get_rdt_mon_resources();






--
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[Bruce Ashfield]

This series doesn't apply to the current 4.12:

-
Applying: x86/intel_rdt: Move special case code for Haswell to a quirk 
function

error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172
error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply
Patch failed at 0001 x86/intel_rdt: Move special case code for Haswell 
to a quirk function

The copy of the patch that failed is found in:
   /home/bruce/poky-kernel/linux-yocto-4.12.git/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---

Can you double check that the 4.12 you used to generate this series
matches what I have staged on git.yoctoproject.org.

Bruce

On 01/08/2018 10:20 PM, quanyang.w...@windriver.com wrote:

From: Tony Luck 

commit 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 upstream

No functional change, but lay the ground work for other per-model
quirks.

Signed-off-by: Tony Luck 
Signed-off-by: Thomas Gleixner 
Cc: Fenghua" 
Cc: Ravi V" 
Cc: "Peter Zijlstra" 
Cc: "Stephane Eranian" 
Cc: "Andi Kleen" 
Cc: "David Carrillo-Cisneros" 
Cc: Vikas Shivappa 
Link: 
http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.l...@intel.com
---
  arch/x86/kernel/cpu/intel_rdt.c | 52 ++---
  1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index dfc7c48..5af2f8f 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource *r, 
unsigned int closid)
   * is always 20 on hsw server parts. The minimum cache bitmask length
   * allowed for HSW server is always 2 bits. Hardcode all of them.
   */
-static inline bool cache_alloc_hsw_probe(void)
+static inline void cache_alloc_hsw_probe(void)
  {
-   if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-   boot_cpu_data.x86 == 6 &&
-   boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
-   struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
-   u32 l, h, max_cbm = BIT_MASK(20) - 1;
+   struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
+   u32 l, h, max_cbm = BIT_MASK(20) - 1;
  
-		if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))

-   return false;
-   rdmsr(IA32_L3_CBM_BASE, l, h);
-
-   /* If all the bits were set in MSR, return success */
-   if (l != max_cbm)
-   return false;
+   if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+   return;
+   rdmsr(IA32_L3_CBM_BASE, l, h);
  
-		r->num_closid = 4;

-   r->default_ctrl = max_cbm;
-   r->cache.cbm_len = 20;
-   r->cache.shareable_bits = 0xc;
-   r->cache.min_cbm_bits = 2;
-   r->alloc_capable = true;
-   r->alloc_enabled = true;
+   /* If all the bits were set in MSR, return success */
+   if (l != max_cbm)
+   return;
  
-		return true;

-   }
+   r->num_closid = 4;
+   r->default_ctrl = max_cbm;
+   r->cache.cbm_len = 20;
+   r->cache.shareable_bits = 0xc;
+   r->cache.min_cbm_bits = 2;
+   r->alloc_capable = true;
+   r->alloc_enabled = true;
  
-	return false;

+   rdt_alloc_capable = true;
  }
  
  /*

@@ -648,7 +642,7 @@ static __init bool get_rdt_alloc_resources(void)
  {
bool ret = false;
  
-	if (cache_alloc_hsw_probe())

+   if (rdt_alloc_capable)
return true;
  
  	if (!boot_cpu_has(X86_FEATURE_RDT_A))

@@ -690,8 +684,18 @@ static __init bool get_rdt_mon_resources(void)
return !rdt_get_mon_l3_config(_resources_all[RDT_RESOURCE_L3]);
  }
  
+static __init void rdt_quirks(void)

+{
+   switch (boot_cpu_data.x86_model) {
+   case INTEL_FAM6_HASWELL_X:
+   cache_alloc_hsw_probe();
+   break;
+   }
+}
+
  static __init bool get_rdt_resources(void)
  {
+   rdt_quirks();
rdt_alloc_capable = get_rdt_alloc_resources();
rdt_mon_capable = get_rdt_mon_resources();
  



--
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto

Re: [linux-yocto] [yocto-4.12] [PATCH] kvm : enable VHOST of host for qemu running guest

[Bruce Ashfield]

this has now been staged and pushed to the yocto kernel
cache repo.

Bruce

On 01/04/2018 04:53 AM, Hongzhi.Song wrote:

Signed-off-by: Hongzhi.Song 
---
  features/kvm/qemu-kvm.cfg | 9 +
  1 file changed, 9 insertions(+)

diff --git a/features/kvm/qemu-kvm.cfg b/features/kvm/qemu-kvm.cfg
index 30b0b8e..3e9a5d4 100644
--- a/features/kvm/qemu-kvm.cfg
+++ b/features/kvm/qemu-kvm.cfg
@@ -2,3 +2,12 @@ CONFIG_KVM=m
  CONFIG_KVM_INTEL=m
  CONFIG_KVM_AMD=m
  CONFIG_TUN=y
+
+# Macvtap
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+
+# VhostNet
+CONFIG_VHOST_NET=m
+CONFIG_VHOST=m
+



--
___
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto