[linux-yocto] [PATCH 14/17] arch/powerpc: Updated Device Trees for Axxia (3400/3500)
From: John Jacques
Also added the 6th Core to the Default 3500 Device Tree
Signed-off-by: John Jacques
---
arch/powerpc/boot/dts/acp342x.dts | 347 +++--
arch/powerpc/boot/dts/acp344x.dts | 164 --
arch/powerpc/boot/dts/acp35xx.dts | 73
3 files changed, 323 insertions(+), 261 deletions(-)
diff --git a/arch/powerpc/boot/dts/acp342x.dts
b/arch/powerpc/boot/dts/acp342x.dts
index 6e02a8c..28a0a13 100644
--- a/arch/powerpc/boot/dts/acp342x.dts
+++ b/arch/powerpc/boot/dts/acp342x.dts
@@ -1,10 +1,10 @@
/*
- * Device Tree Source for IBM Embedded PPC 476 Platform
+ * Device Tree Source for LSI Axxia ACP342x.
*
- * Copyright 2009 Torez Smith, IBM Corporation.
+ * Copyright 2013, LSI Corporation.
*
* Based on earlier code:
- * Copyright (c) 2006, 2007 IBM Corp.
+ * Copyright (c) 2009, 2006, 2007 IBM Corp.
* Josh Boyer , David Gibson
*
* This file is licensed under the terms of the GNU General Public
@@ -17,165 +17,187 @@
/memreserve/ 0x 0x0040;
/ {
-#address-cells = <2>;
-#size-cells = <1>;
-model = "ibm,acpx1-4xx";
-compatible = "ibm,acpx1-4xx","ibm,47x-AMP";
-dcr-parent = <&{/cpus/cpu@0}>;
-
-aliases {
-serial0 = &UART0;
-serial1 = &UART1;
-rapidio0 = &rio0;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "ibm,acpx1-4xx";
+ compatible = "lsi,acp3420", "lsi,acp", "ibm,acpx1-4xx";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ serial0 = &UART0;
+ serial1 = &UART1;
ethernet0 = &FEMAC;
-};
+ rapidio0 = &SRIO0;
+ };
-cpus {
-#address-cells = <1>;
-#size-cells = <0>;
-
-cpu@0 {
-device_type = "cpu";
-model = "PowerPC,4xx"; // real CPU changed in sim
-reg = <0>;
-clock-frequency = <0x5f5e1000>;
-timebase-frequency = <0x5f5e1000>;
-i-cache-line-size = <32>;
-d-cache-line-size = <32>;
-i-cache-size = <32768>;
-d-cache-size = <32768>;
-dcr-controller;
-dcr-access-method = "native";
-status = "ok";
-reset-type = <3>; // 1=core, 2=chip, 3=system (default)
-};
-};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <0>;
+ clock-frequency = <0>; // filled in by U-Boot
+ timebase-frequency = <0>; // filled in by U-Boot
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "ok";
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <1>;
+ clock-frequency = <0>; // filled in by U-Boot
+ timebase-frequency = <0>; // filled in by U-Boot
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "disabled";
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; // filled in by U-Boot
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ };
memory@0 {
device_type = "memory";
-reg = <0x 0x 0x8000>; // filled in by
U-Boot
+reg = <0 0 0>; // filled in by U-Boot
};
memory@8000 {
device_type = "memory";
-reg = <0x 0x8000 0x8000>; // filled in by
U-Boot
+reg = <0 0 0>; // filled in by U-Boot
};
-MPIC: interrupt-controller {
-compatible = "chrp,open-pic";
-interrupt-controller;
-dcr-reg = <0xffc0 0x0003>;
-#address-cells = <0>;
-
[linux-yocto] [PATCH 14/17] arch/powerpc: Updated Device Trees for Axxia (3400/3500)
From: John Jacques
Also added the 6th Core to the Default 3500 Device Tree
Signed-off-by: John Jacques
---
arch/powerpc/boot/dts/acp342x.dts | 347 +++--
arch/powerpc/boot/dts/acp344x.dts | 164 --
arch/powerpc/boot/dts/acp35xx.dts | 73
3 files changed, 323 insertions(+), 261 deletions(-)
diff --git a/arch/powerpc/boot/dts/acp342x.dts
b/arch/powerpc/boot/dts/acp342x.dts
index 6e02a8c..28a0a13 100644
--- a/arch/powerpc/boot/dts/acp342x.dts
+++ b/arch/powerpc/boot/dts/acp342x.dts
@@ -1,10 +1,10 @@
/*
- * Device Tree Source for IBM Embedded PPC 476 Platform
+ * Device Tree Source for LSI Axxia ACP342x.
*
- * Copyright 2009 Torez Smith, IBM Corporation.
+ * Copyright 2013, LSI Corporation.
*
* Based on earlier code:
- * Copyright (c) 2006, 2007 IBM Corp.
+ * Copyright (c) 2009, 2006, 2007 IBM Corp.
* Josh Boyer , David Gibson
*
* This file is licensed under the terms of the GNU General Public
@@ -17,165 +17,187 @@
/memreserve/ 0x 0x0040;
/ {
-#address-cells = <2>;
-#size-cells = <1>;
-model = "ibm,acpx1-4xx";
-compatible = "ibm,acpx1-4xx","ibm,47x-AMP";
-dcr-parent = <&{/cpus/cpu@0}>;
-
-aliases {
-serial0 = &UART0;
-serial1 = &UART1;
-rapidio0 = &rio0;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "ibm,acpx1-4xx";
+ compatible = "lsi,acp3420", "lsi,acp", "ibm,acpx1-4xx";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ serial0 = &UART0;
+ serial1 = &UART1;
ethernet0 = &FEMAC;
-};
+ rapidio0 = &SRIO0;
+ };
-cpus {
-#address-cells = <1>;
-#size-cells = <0>;
-
-cpu@0 {
-device_type = "cpu";
-model = "PowerPC,4xx"; // real CPU changed in sim
-reg = <0>;
-clock-frequency = <0x5f5e1000>;
-timebase-frequency = <0x5f5e1000>;
-i-cache-line-size = <32>;
-d-cache-line-size = <32>;
-i-cache-size = <32768>;
-d-cache-size = <32768>;
-dcr-controller;
-dcr-access-method = "native";
-status = "ok";
-reset-type = <3>; // 1=core, 2=chip, 3=system (default)
-};
-};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <0>;
+ clock-frequency = <0>; // filled in by U-Boot
+ timebase-frequency = <0>; // filled in by U-Boot
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "ok";
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <1>;
+ clock-frequency = <0>; // filled in by U-Boot
+ timebase-frequency = <0>; // filled in by U-Boot
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "disabled";
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; // filled in by U-Boot
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ };
memory@0 {
device_type = "memory";
-reg = <0x 0x 0x8000>; // filled in by
U-Boot
+reg = <0 0 0>; // filled in by U-Boot
};
memory@8000 {
device_type = "memory";
-reg = <0x 0x8000 0x8000>; // filled in by
U-Boot
+reg = <0 0 0>; // filled in by U-Boot
};
-MPIC: interrupt-controller {
-compatible = "chrp,open-pic";
-interrupt-controller;
-dcr-reg = <0xffc0 0x0003>;
-#address-cells = <0>;
-
