Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Peter Stuge wrote: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. Sorry more dumb questions. Do I want SLTSST25LF040A-33-4C-S2AE ---5.4mm Body or SLTSST25LF040A-33-4C-S2E --4mm Body My BIOS chip appears over 5mm Also flashrom does not detect the BIOS chip, there is no code for this type. So how will flashrom be able to write to the BIOS? Chris Lingard -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Montag, 22. Oktober 2007 21:56:32 schrieb Chris Lingard: Peter Stuge wrote: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. Sorry more dumb questions. Do I want SLTSST25LF040A-33-4C-S2AE ---5.4mm Body or SLTSST25LF040A-33-4C-S2E --4mm Body My BIOS chip appears over 5mm Also flashrom does not detect the BIOS chip, there is no code for this type. So how will flashrom be able to write to the BIOS? without a modification in the flashrom source code it will not be possible to write to this chip. Chris Lingard Harald -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 22.10.2007 22:31, Harald Gutmann wrote: Am Montag, 22. Oktober 2007 21:56:32 schrieb Chris Lingard: Also flashrom does not detect the BIOS chip, there is no code for this type. So how will flashrom be able to write to the BIOS? without a modification in the flashrom source code it will not be possible to write to this chip. The problem is that this specific chip does not appear to support the RDID instruction (at least the data sheet is silent about it). If it supports RDID, adding support for it is easy once somebody has run flashrom -V on that chip. Ask your seller/distributor about JEDEC-RDID instruction support before you buy. I have no idea about the correct form factor, though. Regards, Carl-Daniel -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Harald Gutmann wrote: Am Montag, 22. Oktober 2007 21:56:32 schrieb Chris Lingard: without a modification in the flashrom source code it will not be possible to write to this chip. Is there an idiots guide to writing sst25lf040a.c, like modifying one of the other sst*.c files. I have a data sheet :-) -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 18.10.2007 22:58, Carl-Daniel Hailfinger wrote: On 18.10.2007 17:13, Harald Gutmann wrote: Am Donnerstag, 18. Oktober 2007 17:05:30 schrieb Ward Vandewege: On Thu, Oct 18, 2007 at 04:59:36PM +0200, Harald Gutmann wrote: Am Donnerstag, 18. Oktober 2007 01:10:03 schrieb Peter Stuge: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. the chips go up to 32mbit with 50mhz to 75/85mhz and 8 pins, but i wasn't able to find them in europe until now. 64mbit are only available with 16 pins. farnell has an sst chip with right pin position, speed (50mhz) and 16mb in its store. which cost's about 3€. 16Mbit Chip: SST25VF016B-50-4I-S2AF Do not order a lot of SST chips, they are much more difficult to support with the current flashrom architecture. You could order one and check if they support the RDID instruction (data sheet is silent about RDID), but I have no idea if they do. I now found a SST data sheet (not easily found on the official web site) that talks about RDID, so adding support for it should be possible. Regards, Carl-Daniel -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Donnerstag, 18. Oktober 2007 01:10:03 schrieb Peter Stuge: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. the chips go up to 32mbit with 50mhz to 75/85mhz and 8 pins, but i wasn't able to find them in europe until now. 64mbit are only available with 16 pins. farnell has an sst chip with right pin position, speed (50mhz) and 16mb in its store. which cost's about 3€. farnell has also sockels for that chips in his store, but they cost much more. (about 22€). i've an second MX25L4005 here, if someone would like to have it, i can send it. (the chip will be for free, and shipping costs maybe to, depends on how much this will be.) regards, harald -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Donnerstag, 18. Oktober 2007 17:05:30 schrieb Ward Vandewege: On Thu, Oct 18, 2007 at 04:59:36PM +0200, Harald Gutmann wrote: Am Donnerstag, 18. Oktober 2007 01:10:03 schrieb Peter Stuge: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. the chips go up to 32mbit with 50mhz to 75/85mhz and 8 pins, but i wasn't able to find them in europe until now. 64mbit are only available with 16 pins. farnell has an sst chip with right pin position, speed (50mhz) and 16mb in its store. which cost's about 3€. 16Mbit Chip: SST25VF016B-50-4I-S2AF SOIC 8Pin Sockel: 652B0082215-002 What type number is that? Thanks, Ward. -- Ward Vandewege [EMAIL PROTECTED] Free Software Foundation - Senior System Administrator -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On Thu, Oct 18, 2007 at 04:59:36PM +0200, Harald Gutmann wrote: Am Donnerstag, 18. Oktober 2007 01:10:03 schrieb Peter Stuge: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. the chips go up to 32mbit with 50mhz to 75/85mhz and 8 pins, but i wasn't able to find them in europe until now. 64mbit are only available with 16 pins. farnell has an sst chip with right pin position, speed (50mhz) and 16mb in its store. which cost's about 3€. What type number is that? Thanks, Ward. -- Ward Vandewege [EMAIL PROTECTED] Free Software Foundation - Senior System Administrator -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 18.10.2007 17:13, Harald Gutmann wrote: Am Donnerstag, 18. Oktober 2007 17:05:30 schrieb Ward Vandewege: On Thu, Oct 18, 2007 at 04:59:36PM +0200, Harald Gutmann wrote: Am Donnerstag, 18. Oktober 2007 01:10:03 schrieb Peter Stuge: On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. the chips go up to 32mbit with 50mhz to 75/85mhz and 8 pins, but i wasn't able to find them in europe until now. 64mbit are only available with 16 pins. farnell has an sst chip with right pin position, speed (50mhz) and 16mb in its store. which cost's about 3€. 16Mbit Chip: SST25VF016B-50-4I-S2AF Do not order a lot of SST chips, they are much more difficult to support with the current flashrom architecture. You could order one and check if they support the RDID instruction (data sheet is silent about RDID), but I have no idea if they do. EON chips have other pitfalls, but they should theoretically still be easier to support. Regards, Carl-Daniel -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On Wed, Oct 17, 2007 at 08:47:41PM +0100, Chris Lingard wrote: I'll get in touch with the distributors here. Will get back when I know more. I have been trying to get my M57SLI Rev2.0 SPI running LinuxBios for a while, but could not get the chip Sorry, no news from me yet, I hardly have time to check my email this week. I have been offered a batch of SST25LF040A brand new unprogrammed for US $3 each. If this a good price and a way to go? Fairly good price, depending on how many a batch is? 30-or so pieces could go for $3, but you probably want to look for 25LF080A instead then to get more room. Maybe there's a 16Mbit version too. Smaller quantities like 3 or 4 come pre-programmed here That's not a problem per se, you can always erase and reprogram, but usually there is a rather high cost for the service. :\ //Peter -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On Mon, Oct 15, 2007 at 02:57:00AM +0200, Stefan Reinauer wrote: i think some parts here could be done easyer with outb. This implementation of the MX25L4005 relies heavily on the chip being attached to an IT8716F SuperIO. I think we should create an abstraction layer (spi_command()? read_spi_status()?) that can be implemented by a SuperIO or southbridge that has an SPI bus attached. Yes. //Peter -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Montag, 15. Oktober 2007 02:57:00 schrieb Stefan Reinauer:
* Harald Gutmann [EMAIL PROTECTED] [071015 02:16]:
+static void check_n_write_enable() {
+ uint8_t result[3] = {0, 0, 0};
+ uint8_t command[5] = {0x06, 0, 0, 0, 0};
+ // Send WREN (Write Enable)
+ it8716f_spi_command(it8716f_flashport, 1, 0, command, result);
+ uint8_t reg=regval(it8716f_flashport,0x24);
+ reg|=(14);
+ regwrite(it8716f_flashport,0x24,reg);
+}
i think some parts here could be done easyer with outb.
This implementation of the MX25L4005 relies heavily on the chip being
attached to an IT8716F SuperIO.
yes, it does!
I think we should create an abstraction
would be good.
layer (spi_command()? read_spi_status()?) that can be implemented by a
SuperIO or southbridge that has an SPI bus attached. This way we could
have fairly generic SPI flash chip drivers (most SPI chips are pretty
similar too, I think), and they could be used on a new system by just
implementing the southbridge/SuperIO specific part in some other place.
i also think that the spi programming is fairly generic on SPI flash devices.
Stefan
regards,
Harald
--
linuxbios mailing list
linuxbios@linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On Mon, Oct 15, 2007 at 02:57:00AM +0200, Stefan Reinauer wrote:
* Harald Gutmann [EMAIL PROTECTED] [071015 02:16]:
+static void check_n_write_enable() {
+ uint8_t result[3] = {0, 0, 0};
+ uint8_t command[5] = {0x06, 0, 0, 0, 0};
+ // Send WREN (Write Enable)
+ it8716f_spi_command(it8716f_flashport, 1, 0, command, result);
+ uint8_t reg=regval(it8716f_flashport,0x24);
+ reg|=(14);
+ regwrite(it8716f_flashport,0x24,reg);
+}
i think some parts here could be done easyer with outb.
This implementation of the MX25L4005 relies heavily on the chip being
attached to an IT8716F SuperIO. I think we should create an abstraction
layer (spi_command()? read_spi_status()?) that can be implemented by a
SuperIO or southbridge that has an SPI bus attached. This way we could
have fairly generic SPI flash chip drivers (most SPI chips are pretty
similar too, I think), and they could be used on a new system by just
implementing the southbridge/SuperIO specific part in some other place.
Full ack.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
signature.asc
Description: Digital signature
--
linuxbios mailing list
linuxbios@linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Peter Stuge wrote: getting these chips is quite hard, here in europe, I have a couple of 8Mbit SST25VF080B sample chips that I can pass on. I can't sell them but if you pay for postage I'll send you one or two. They are in WSON package which is footprint compatible with SOIC but not quite as easy to work with because no pins are exposed. I can probably also get hold of chips for resale if there is need. Yes please, I got a M57SLI months ago, but it is series 2. I got the wrong series 1 chips, and have not made any progress since. I have tried to order the needed BIOS chip, but will no success. I have a local computer shop who will do the soldering, (I am a programmer and would not have a clue on engineering). Please contact me if you can get the chip required to modify a recent series 2 mother board. Chris Lingard -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Sonntag, 14. Oktober 2007 03:45:10 schrieb Peter Stuge: I have a couple of 8Mbit SST25VF080B sample chips that I can pass on. I can't sell them but if you pay for postage I'll send you one or two. They are in WSON package which is footprint compatible with SOIC but not quite as easy to work with because no pins are exposed. i think to do that circuit with wson packaged chips will be quite hard, because you can't lift the CS# pin that easy like with the sop packaged chips. and i contacted a few people i know, which maybe can get these chips a little easyer than me, over ther company/employers. //Peter regards, harald -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
after a friend of mine (wolfgang illmeyer) implemented the code to write to the spi chip, i can finally give you the following output: % benchvice flashrom # ./flashrom -m gigabyte:m57sli -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios_onchip.rom Calibrating delay loop... ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. RDID returned c2 20 13 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) benchvice flashrom # ./flashrom -m gigabyte:m57sli -v /home/hg87/src/linuxbios/buildrom-devel/linuxbios_onchip.rom Calibrating delay loop... ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. RDID returned c2 20 13 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) Verifying flash - VERIFIED benchvice flashrom # %-- i didn't try to boot the linuxbios until now, and the code is quite ugly and not cleaned up these times. i'll try to get the code cleaned up in the next few days, and poste the code to the list. but now, i try to boot the linuxbios. regards, harald -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 12.10.2007 20:40, Harald Gutmann wrote: i always read about SST25LF040A and MX25L4005A chips which are used for bios on that mainboard. my mainboard which is also revision 2.0 has a different bios chip, which a device from winbond called 25X40VSIG. here's the link to the datasheet of this chip: www.winbond-usa.com/products/Nexflash/pdfs/datasheets/W25X10_20_40_80g.pdf this is just a statement, that there are also boards with that bios-chips out there. original bios chip: %- benchvice flashrom # ./flashrom --mainboard gigabyte:m57sli Calibrating delay loop... ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. RDID returned ef 30 13 No EEPROM/flash device found. Yes, limitation of the current code, I have patches pending and will send once I'm healthy again. benchvice flashrom # % after changing the position of the spdt switch: % benchvice flashrom # ./flashrom --mainboard gigabyte:m57sli Calibrating delay loop... ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0 xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. RDID returned c2 20 13 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) No operations were specified Expected output. Carl-Daniel -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 13.10.2007 15:59, Harald Gutmann wrote: just talking to myselv, but here are some more detailed informations including a backtrace of flashrom: i removed stripping and optimisation, but added the debug flag in makefile. benchvice flashrom # file flashrom flashrom: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), for GNU/Linux 2.6.9, statically linked, not stripped benchvice flashrom # gdb ./flashrom GNU gdb 6.6 Copyright (C) 2006 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type show copying to see the conditions. There is absolutely no warranty for GDB. Type show warranty for details. This GDB was configured as x86_64-pc-linux-gnu... Using host libthread_db library /lib/libthread_db.so.1. (gdb) run --mainboard gigabyte:m57sli -V -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom Starting program: /home/hg87/src/linuxbios/LinuxBIOSv3/util/flashrom/flashrom --mainboard gigabyte:m57sli -V -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom Calibrating delay loop... 348M loops per second. ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for Mx29f002, 256 KB probe_29f002: id1 0xff, id2 0xff Probing for MX25L4005, 512 KB RDID returned c2 20 13 probe_spi: id1 0xc2, id2 0x2013 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) LinuxBIOS last image size (not rom size) is 4096 bytes. MANUFACTURER: GIGABYTE MAINBOARD ID: m57sli This firmware image matches this motherboard. Program received signal SIGSEGV, Segmentation fault. 0x in ?? () (gdb) bt #0 0x in ?? () #1 0x004068f4 in main (argc=6, argv=0x7fff7540a148) at flashrom.c:460 (gdb) c Continuing. Program terminated with signal SIGSEGV, Segmentation fault. The program no longer exists. (gdb) quit benchvice flashrom # That's a NULL pointer dereference because SPI erase/write suppport is not enabled yet. I have patches pending. Carl-Daniel -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 15.10.2007 00:41, Harald Gutmann wrote: after a friend of mine (wolfgang illmeyer) implemented the code to write to the spi chip, i can finally give you the following output: Great! % benchvice flashrom # ./flashrom -m gigabyte:m57sli -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios_onchip.rom Calibrating delay loop... ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. RDID returned c2 20 13 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) benchvice flashrom # ./flashrom -m gigabyte:m57sli -v /home/hg87/src/linuxbios/buildrom-devel/linuxbios_onchip.rom Calibrating delay loop... ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. RDID returned c2 20 13 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) Verifying flash - VERIFIED benchvice flashrom # %-- i didn't try to boot the linuxbios until now, and the code is quite ugly and not cleaned up these times. i'll try to get the code cleaned up in the next few days, and poste the code to the list. Great, thanks! The code I have also is not polished, so even if your code is ugly, it is better than no code. We can clean up that stuff together. I have a few patches pending to flashrom which restructure the SPI code, but they don't change function prototypes, so your code is likely to work fine even after my changes. but now, i try to boot the linuxbios. Good luck! Regards, Carl-Daniel -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Montag, 15. Oktober 2007 01:06:00 schrieb Carl-Daniel Hailfinger:
Great, thanks! The code I have also is not polished, so even if your
code is ugly, it is better than no code. We can clean up that stuff
together.
yes, that's right!
here it is.
the patch is done with:
[EMAIL PROTECTED] ~/src/linuxbios/LinuxBIOSv3/util/flashrom $ svn info
Pfad: .
URL: svn://linuxbios.org/repos/trunk/util/flashrom
Basis des Projektarchivs: svn://linuxbios.org/repos
UUID des Projektarchivs: 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Revision: 2850
Knotentyp: Verzeichnis
Plan: normal
Letzter Autor: rminnich
Letzte geänderte Rev: 2850
Letztes Änderungsdatum: 2007-10-12 23:22:40 +0200 (Fr, 12 Okt 2007)
[EMAIL PROTECTED] ~/src/linuxbios/LinuxBIOSv3/util/flashrom $
have fun with it, or just shrug because of the dirty hacks. ;)
regards, harald
diff -ubrN ../../flashrom.original/board_enable.c flashrom.new/board_enable.c
--- ../../flashrom.original/board_enable.c 2007-10-15 01:14:29.0 +0200
+++ flashrom.new/board_enable.c 2007-10-14 20:28:41.0 +0200
@@ -37,7 +37,7 @@
#define JEDEC_RDID_OUTSIZE 0x01
#define JEDEC_RDID_INSIZE 0x03
-static uint16_t it8716f_flashport = 0;
+uint16_t it8716f_flashport = 0;
/* Generic Super I/O helper functions */
uint8_t regval(uint16_t port, uint8_t reg)
@@ -111,7 +111,7 @@
whereas the IT8716F splits commands internally into address and non-address
commands with the address in inverse wire order. That's why the register
ordering in case 4 and 5 may seem strange. */
-static int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr)
+int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr)
{
uint8_t busy, writeenc;
do {
diff -ubrN ../../flashrom.original/board_enable.h flashrom.new/board_enable.h
--- ../../flashrom.original/board_enable.h 1970-01-01 01:00:00.0 +0100
+++ flashrom.new/board_enable.h 2007-10-14 21:09:18.0 +0200
@@ -0,0 +1,7 @@
+#ifndef boardenableh
+#define boardenableh
+uint16_t it8716f_flashport;
+uint8_t regval(uint16_t port, uint8_t reg);
+void regwrite(uint16_t port, uint8_t reg, uint8_t val);
+int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr);
+#endif
diff -ubrN ../../flashrom.original/flashchips.c flashrom.new/flashchips.c
--- ../../flashrom.original/flashchips.c 2007-10-15 01:14:28.0 +0200
+++ flashrom.new/flashchips.c 2007-10-15 01:24:58.0 +0200
@@ -39,7 +39,7 @@
{Mx29f002, MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
{MX25L4005, MX_ID, MX_25L4005, 512, 4 * 1024,
- probe_spi, NULL, NULL},
+ probe_spi, erase_25l4005, write_25l4005},
{SST29EE020A, SST_ID, SST_29EE020A, 256, 128,
probe_jedec, erase_chip_jedec, write_jedec},
{SST28SF040A, SST_ID, SST_28SF040, 512, 256,
diff -ubrN ../../flashrom.original/flash.h flashrom.new/flash.h
--- ../../flashrom.original/flash.h 2007-10-15 01:14:28.0 +0200
+++ flashrom.new/flash.h 2007-10-14 19:13:52.0 +0200
@@ -294,4 +294,10 @@
/* w49f002u.c */
int write_49f002(struct flashchip *flash, uint8_t *buf);
+/* mx25l4005.c */
+// probe
+int write_25l4005(struct flashchip *flash, uint8_t *buf);
+int erase_25l4005(struct flashchip *flash);
+int read_25l4005(struct flashchip *flash, uint8_t *buf);
+
#endif/* !__FLASH_H__ */
diff -ubrN ../../flashrom.original/Makefile flashrom.new/Makefile
--- ../../flashrom.original/Makefile 2007-10-15 01:14:29.0 +0200
+++ flashrom.new/Makefile 2007-10-15 01:20:16.0 +0200
@@ -24,7 +24,7 @@
am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \
82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \
sst_fwhub.o layout.o lbtable.o flashchips.o flashrom.o \
- sharplhf00l04.o w29ee011.o
+ sharplhf00l04.o w29ee011.o mx25l4005.o
all: pciutils dep $(PROGRAM)
@@ -33,7 +33,7 @@
$(STRIP) $(STRIP_ARGS) $(PROGRAM)
clean:
- rm -f *.o *~
+ rm -f *.o *~ flashrom
distclean: clean
rm -f $(PROGRAM) .dependencies
diff -ubrN ../../flashrom.original/mx25l4005.c flashrom.new/mx25l4005.c
--- ../../flashrom.original/mx25l4005.c 1970-01-01 01:00:00.0 +0100
+++ flashrom.new/mx25l4005.c 2007-10-15 01:17:56.0 +0200
@@ -0,0 +1,57 @@
+#include stdint.h
+#include stdlib.h
+#include stdio.h
+#include flash.h
+#include board_enable.h
+
+static void check_n_write_enable() {
+ uint8_t result[3] = {0, 0, 0};
+ uint8_t command[5] = {0x06, 0, 0, 0, 0};
+ // Send WREN (Write Enable)
+ it8716f_spi_command(it8716f_flashport, 1, 0, command, result);
+ uint8_t reg=regval(it8716f_flashport,0x24);
+ reg|=(14);
+ regwrite(it8716f_flashport,0x24,reg);
+
+}
+
+static void write_disable() {
+ uint8_t result[3] = {0, 0, 0};
+ uint8_t command[5] = {0x04, 0, 0, 0, 0};
+ // Send WRDI (Write Disable)
+
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On 15.10.2007 01:28, Harald Gutmann wrote:
Am Montag, 15. Oktober 2007 01:06:00 schrieb Carl-Daniel Hailfinger:
Great, thanks! The code I have also is not polished, so even if your
code is ugly, it is better than no code. We can clean up that stuff
together.
yes, that's right!
here it is.
Nice!
the patch is done with:
[EMAIL PROTECTED] ~/src/linuxbios/LinuxBIOSv3/util/flashrom $ svn info
Pfad: .
URL: svn://linuxbios.org/repos/trunk/util/flashrom
Basis des Projektarchivs: svn://linuxbios.org/repos
UUID des Projektarchivs: 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Revision: 2850
Knotentyp: Verzeichnis
Plan: normal
Letzter Autor: rminnich
Letzte geänderte Rev: 2850
Letztes Änderungsdatum: 2007-10-12 23:22:40 +0200 (Fr, 12 Okt 2007)
[EMAIL PROTECTED] ~/src/linuxbios/LinuxBIOSv3/util/flashrom $
have fun with it, or just shrug because of the dirty hacks. ;)
I'll review later this week, but from a first glance at the code it
looks nice.
regards, harald
Regards,
Carl-Daniel
diff -ubrN ../../flashrom.original/board_enable.c flashrom.new/board_enable.c
--- ../../flashrom.original/board_enable.c2007-10-15 01:14:29.0
+0200
+++ flashrom.new/board_enable.c 2007-10-14 20:28:41.0 +0200
@@ -37,7 +37,7 @@
#define JEDEC_RDID_OUTSIZE 0x01
#define JEDEC_RDID_INSIZE0x03
-static uint16_t it8716f_flashport = 0;
+uint16_t it8716f_flashport = 0;
/* Generic Super I/O helper functions */
uint8_t regval(uint16_t port, uint8_t reg)
@@ -111,7 +111,7 @@
whereas the IT8716F splits commands internally into address and
non-address
commands with the address in inverse wire order. That's why the register
ordering in case 4 and 5 may seem strange. */
-static int it8716f_spi_command(uint16_t port, unsigned char writecnt,
unsigned char readcnt, const unsigned char *writearr, unsigned char *readarr)
+int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned char
readcnt, const unsigned char *writearr, unsigned char *readarr)
{
uint8_t busy, writeenc;
do {
diff -ubrN ../../flashrom.original/board_enable.h flashrom.new/board_enable.h
--- ../../flashrom.original/board_enable.h1970-01-01 01:00:00.0
+0100
+++ flashrom.new/board_enable.h 2007-10-14 21:09:18.0 +0200
@@ -0,0 +1,7 @@
+#ifndef boardenableh
+#define boardenableh
+uint16_t it8716f_flashport;
+uint8_t regval(uint16_t port, uint8_t reg);
+void regwrite(uint16_t port, uint8_t reg, uint8_t val);
+int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned char
readcnt, const unsigned char *writearr, unsigned char *readarr);
+#endif
diff -ubrN ../../flashrom.original/flashchips.c flashrom.new/flashchips.c
--- ../../flashrom.original/flashchips.c 2007-10-15 01:14:28.0
+0200
+++ flashrom.new/flashchips.c 2007-10-15 01:24:58.0 +0200
@@ -39,7 +39,7 @@
{Mx29f002,MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
{MX25L4005, MX_ID, MX_25L4005, 512, 4 * 1024,
- probe_spi, NULL, NULL},
+ probe_spi, erase_25l4005, write_25l4005},
{SST29EE020A, SST_ID, SST_29EE020A, 256, 128,
probe_jedec, erase_chip_jedec, write_jedec},
{SST28SF040A, SST_ID, SST_28SF040,512, 256,
diff -ubrN ../../flashrom.original/flash.h flashrom.new/flash.h
--- ../../flashrom.original/flash.h 2007-10-15 01:14:28.0 +0200
+++ flashrom.new/flash.h 2007-10-14 19:13:52.0 +0200
@@ -294,4 +294,10 @@
/* w49f002u.c */
int write_49f002(struct flashchip *flash, uint8_t *buf);
+/* mx25l4005.c */
+// probe
+int write_25l4005(struct flashchip *flash, uint8_t *buf);
+int erase_25l4005(struct flashchip *flash);
+int read_25l4005(struct flashchip *flash, uint8_t *buf);
+
#endif /* !__FLASH_H__ */
diff -ubrN ../../flashrom.original/Makefile flashrom.new/Makefile
--- ../../flashrom.original/Makefile 2007-10-15 01:14:29.0 +0200
+++ flashrom.new/Makefile 2007-10-15 01:20:16.0 +0200
@@ -24,7 +24,7 @@
am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \
82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \
sst_fwhub.o layout.o lbtable.o flashchips.o flashrom.o \
- sharplhf00l04.o w29ee011.o
+ sharplhf00l04.o w29ee011.o mx25l4005.o
all: pciutils dep $(PROGRAM)
@@ -33,7 +33,7 @@
$(STRIP) $(STRIP_ARGS) $(PROGRAM)
clean:
- rm -f *.o *~
+ rm -f *.o *~ flashrom
distclean: clean
rm -f $(PROGRAM) .dependencies
diff -ubrN ../../flashrom.original/mx25l4005.c flashrom.new/mx25l4005.c
--- ../../flashrom.original/mx25l4005.c 1970-01-01 01:00:00.0
+0100
+++ flashrom.new/mx25l4005.c 2007-10-15 01:17:56.0
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Montag, 15. Oktober 2007 01:45:51 schrieb Carl-Daniel Hailfinger:
Nice!
it works, and that's the main thing! :)
I'll review later this week, but from a first glance at the code it
looks nice.
some dirty hacks are in the code, but how i told it works.
and now writing from a booted linuxbios!
the bootup time is only great. - but i've to correct someting in filo because
the sleep until the kernel is loaded is just too much. (here about 10
seconds, but i'll try to correct it in the Config of file first.)
just a few comment's on the code:
diff -ubrN ../../flashrom.original/board_enable.c
flashrom.new/board_enable.c ---
../../flashrom.original/board_enable.c 2007-10-15 01:14:29.0
+0200 +++ flashrom.new/board_enable.c 2007-10-14 20:28:41.0
+0200
@@ -37,7 +37,7 @@
#define JEDEC_RDID_OUTSIZE 0x01
#define JEDEC_RDID_INSIZE 0x03
-static uint16_t it8716f_flashport = 0;
+uint16_t it8716f_flashport = 0;
/* Generic Super I/O helper functions */
uint8_t regval(uint16_t port, uint8_t reg)
sould be fine.
@@ -111,7 +111,7 @@
whereas the IT8716F splits commands internally into address and
non-address commands with the address in inverse wire order. That's why
the register ordering in case 4 and 5 may seem strange. */
-static int it8716f_spi_command(uint16_t port, unsigned char writecnt,
unsigned char readcnt, const unsigned char *writearr, unsigned char
*readarr) +int it8716f_spi_command(uint16_t port, unsigned char writecnt,
unsigned char readcnt, const unsigned char *writearr, unsigned char
*readarr) {
uint8_t busy, writeenc;
do {
same here.
diff -ubrN ../../flashrom.original/board_enable.h
flashrom.new/board_enable.h ---
../../flashrom.original/board_enable.h 1970-01-01 01:00:00.0
+0100 +++ flashrom.new/board_enable.h 2007-10-14 21:09:18.0
+0200
@@ -0,0 +1,7 @@
+#ifndef boardenableh
+#define boardenableh
+uint16_t it8716f_flashport;
+uint8_t regval(uint16_t port, uint8_t reg);
+void regwrite(uint16_t port, uint8_t reg, uint8_t val);
+int it8716f_spi_command(uint16_t port, unsigned char writecnt, unsigned
char readcnt, const unsigned char *writearr, unsigned char *readarr);
+#endif
here too.
diff -ubrN ../../flashrom.original/flashchips.c flashrom.new/flashchips.c
--- ../../flashrom.original/flashchips.c2007-10-15 01:14:28.0
+0200 +++ flashrom.new/flashchips.c 2007-10-15 01:24:58.0 +0200
@@ -39,7 +39,7 @@
{Mx29f002,MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
{MX25L4005, MX_ID, MX_25L4005, 512, 4 * 1024,
-probe_spi, NULL, NULL},
+probe_spi, erase_25l4005, write_25l4005},
{SST29EE020A, SST_ID, SST_29EE020A, 256, 128,
probe_jedec, erase_chip_jedec, write_jedec},
{SST28SF040A, SST_ID, SST_28SF040,512, 256,
diff -ubrN ../../flashrom.original/flash.h flashrom.new/flash.h
--- ../../flashrom.original/flash.h 2007-10-15 01:14:28.0 +0200
+++ flashrom.new/flash.h2007-10-14 19:13:52.0 +0200
also okay.
@@ -294,4 +294,10 @@
/* w49f002u.c */
int write_49f002(struct flashchip *flash, uint8_t *buf);
+/* mx25l4005.c */
+// probe
maybe remove that comment.
+int write_25l4005(struct flashchip *flash, uint8_t *buf);
+int erase_25l4005(struct flashchip *flash);
+int read_25l4005(struct flashchip *flash, uint8_t *buf);
+
#endif /* !__FLASH_H__ */
diff -ubrN ../../flashrom.original/Makefile flashrom.new/Makefile
--- ../../flashrom.original/Makefile2007-10-15 01:14:29.0
+0200
+++ flashrom.new/Makefile 2007-10-15 01:20:16.0 +0200
@@ -24,7 +24,7 @@
am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \
82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \
sst_fwhub.o layout.o lbtable.o flashchips.o flashrom.o \
- sharplhf00l04.o w29ee011.o
+ sharplhf00l04.o w29ee011.o mx25l4005.o
all: pciutils dep $(PROGRAM)
@@ -33,7 +33,7 @@
$(STRIP) $(STRIP_ARGS) $(PROGRAM)
clean:
- rm -f *.o *~
+ rm -f *.o *~ flashrom
is in distclean, not necessary.
distclean: clean
rm -f $(PROGRAM) .dependencies
diff -ubrN ../../flashrom.original/mx25l4005.c flashrom.new/mx25l4005.c
--- ../../flashrom.original/mx25l4005.c 1970-01-01 01:00:00.0
+0100 +++ flashrom.new/mx25l4005.c 2007-10-15 01:17:56.0 +0200 @@
-0,0 +1,57 @@
+#include stdint.h
+#include stdlib.h
+#include stdio.h
+#include flash.h
+#include board_enable.h
+
+static void check_n_write_enable() {
+ uint8_t result[3] = {0, 0, 0};
+ uint8_t command[5] = {0x06, 0, 0, 0, 0};
+ // Send WREN (Write Enable)
+ it8716f_spi_command(it8716f_flashport,
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
* Harald Gutmann [EMAIL PROTECTED] [071015 02:16]:
+static void check_n_write_enable() {
+ uint8_t result[3] = {0, 0, 0};
+ uint8_t command[5] = {0x06, 0, 0, 0, 0};
+ // Send WREN (Write Enable)
+ it8716f_spi_command(it8716f_flashport, 1, 0, command, result);
+ uint8_t reg=regval(it8716f_flashport,0x24);
+ reg|=(14);
+ regwrite(it8716f_flashport,0x24,reg);
+}
i think some parts here could be done easyer with outb.
This implementation of the MX25L4005 relies heavily on the chip being
attached to an IT8716F SuperIO. I think we should create an abstraction
layer (spi_command()? read_spi_status()?) that can be implemented by a
SuperIO or southbridge that has an SPI bus attached. This way we could
have fairly generic SPI flash chip drivers (most SPI chips are pretty
similar too, I think), and they could be used on a new system by just
implementing the southbridge/SuperIO specific part in some other place.
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
linuxbios mailing list
linuxbios@linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
just talking to myselv, but here are some more detailed informations including a backtrace of flashrom: i removed stripping and optimisation, but added the debug flag in makefile. benchvice flashrom # file flashrom flashrom: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), for GNU/Linux 2.6.9, statically linked, not stripped benchvice flashrom # gdb ./flashrom GNU gdb 6.6 Copyright (C) 2006 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type show copying to see the conditions. There is absolutely no warranty for GDB. Type show warranty for details. This GDB was configured as x86_64-pc-linux-gnu... Using host libthread_db library /lib/libthread_db.so.1. (gdb) run --mainboard gigabyte:m57sli -V -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom Starting program: /home/hg87/src/linuxbios/LinuxBIOSv3/util/flashrom/flashrom --mainboard gigabyte:m57sli -V -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom Calibrating delay loop... 348M loops per second. ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for Mx29f002, 256 KB probe_29f002: id1 0xff, id2 0xff Probing for MX25L4005, 512 KB RDID returned c2 20 13 probe_spi: id1 0xc2, id2 0x2013 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) LinuxBIOS last image size (not rom size) is 4096 bytes. MANUFACTURER: GIGABYTE MAINBOARD ID: m57sli This firmware image matches this motherboard. Program received signal SIGSEGV, Segmentation fault. 0x in ?? () (gdb) bt #0 0x in ?? () #1 0x004068f4 in main (argc=6, argv=0x7fff7540a148) at flashrom.c:460 (gdb) c Continuing. Program terminated with signal SIGSEGV, Segmentation fault. The program no longer exists. (gdb) quit benchvice flashrom # -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Samstag, 13. Oktober 2007 17:17:15 schrieb Peter Stuge: Excellent job! The soldering looks great - very impressive if this was the first time you soldered electronics. :) no, it wasn't the first time that i soldered, but i don't often solder. Also great to have confirmation that the hardware hack works! according to the flashrom probing output, it works. also the response of the computer on trying to boot with the emtpy bios-chip is a good sign, that it works how it should. Thank you very much. no prob. after booting the machine, i made a svn co of the linuxbios flashrom util, compiled it and had a look if it will work. I'm not sure if flashrom actually works with the SPI chips yet. Carl-Daniel was working on it but I don't remember what the status is. according to Uwe Hermann the write function in current svn version is a NULL function, and not implemented right now. i've to less knowledge in programming and c, to implement that function, but if testers were needed, i'll do it, because i can switch back to the original bios chip easily. //Peter -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On Sat, Oct 13, 2007 at 05:39:51PM +0200, Harald Gutmann wrote: according to Uwe Hermann the write function in current svn version is a NULL function, and not implemented right now. Correct - Carl-Daniel did the SPI detection work, but we don't have read/write support yet. I have updated the M57SLI build tutorial to indicate that the SOIC hardware hack has been confirmed. I really need to get the components so I can do it too on my board. Thanks! Ward. -- Ward Vandewege [EMAIL PROTECTED] Free Software Foundation - Senior System Administrator -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
Am Samstag, 13. Oktober 2007 18:32:28 schrieb Ward Vandewege: I have updated the M57SLI build tutorial to indicate that the SOIC hardware hack has been confirmed. I really need to get the components so I can do it too on my board. thanks for adding it to the wiki, because i've no account right now. getting these chips is quite hard, here in europe, but i'd recommend you, to try to get a serial eeprom, with more capacity, because with the mx25l4005 you just have 512kb space, and linuxbios with LAB as payload would require 1024kb. as reported here (http://linuxbios.org/pipermail/linuxbios/2007-September/024494.html), it is no problem to use an eeprom with more capacity. also documented (here http://linuxbios.org/pipermail/linuxbios/2007-September/024189.html and here http://linuxbios.org/pipermail/linuxbios/2007-September/024196.html) is, that the clock signal is either 16mhz or 25mhz, but not the 85mhz wich are documented in the 85mhz wich the MX25L4005A has. so i think, that it should be no problem to add an s.eeprom with more capacity and lower clock rate. (and also the manufacturer shouldn't mind. when the technical specifications are the same/nearly the same). Thanks! Ward. regards, harald -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
On Sat, Oct 13, 2007 at 07:30:29PM +0200, Harald Gutmann wrote: thanks for adding it to the wiki, because i've no account right now. I would've put my description on the wiki but haven't had time. If anyone wants to use my text or pictures please go ahead. getting these chips is quite hard, here in europe, I have a couple of 8Mbit SST25VF080B sample chips that I can pass on. I can't sell them but if you pay for postage I'll send you one or two. They are in WSON package which is footprint compatible with SOIC but not quite as easy to work with because no pins are exposed. I can probably also get hold of chips for resale if there is need. but i'd recommend you, to try to get a serial eeprom, An important clarification here. If you buy a serial EEPROM you'll get something quite different from the SPI flash that is needed for the Gigabyte board. (They also come in SOIC but have an I2C interface and sizes are rarely in the megabits, usually they're only a few kbytes.) Please don't confuse the two since they are not compatible. with more capacity, because with the mx25l4005 you just have 512kb space, and linuxbios with LAB as payload would require 1024kb. Indeed - 8Mbit or more is the way to go. no problem to use an eeprom with more capacity. Again important to note that none of the suitable chips will be EEPROM, only flash ROM. Depending on who you purchase your chips from, confusing the two terms may cause a big problem. (Ie. you getting unusable chips.) //Peter -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Re: [LinuxBIOS] M57SLI Rev2.0 SPI - how to add the second bios chip (incl. pictures)
trying to flash the new chip with flashrom fails right now, but i don't know why. here is the output from flashrom, when i try to flash the linuxbios.rom file: ./flashrom -V --mainboard gigabyte:m57sli -w /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom Calibrating delay loop... 291M loops per second. ok No LinuxBIOS table found. Found chipset NVIDIA MCP55: Enabling flash write... OK. Found board GIGABYTE GA-M57SLI: Enabling flash write... Serial flash segment 0xfffe-0x enabled Serial flash segment 0x000e-0x000f enabled Serial flash segment 0xffee-0xffef disabled Serial flash segment 0xfff8-0xfffe enabled LPC write to serial flash enabled serial flash pin 29 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for Mx29f002, 256 KB probe_29f002: id1 0xff, id2 0xff Probing for MX25L4005, 512 KB RDID returned c2 20 13 probe_spi: id1 0xc2, id2 0x2013 MX25L4005 found at physical address: 0xfff8 Flash part is MX25L4005 (512 KB) LinuxBIOS last image size (not rom size) is 4096 bytes. MANUFACTURER: GIGABYTE MAINBOARD ID: m57sli This firmware image matches this motherboard. Segmentation fault. benchvice flashrom # ls -lh /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom -rw-r--r-- 1 hg87 hg87 512K 12. Okt 22:59 /home/hg87/src/linuxbios/buildrom-devel/linuxbios.rom benchvice flashrom # tomorrow i'll have a more detailed look on that problem, because i've to leave now. regards, harald -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
