Re: [RFC: PATCH 08/13] powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote: On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp sha...@linux.vnet.ibm.com wrote: powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores From: Benjamin Herrenschmidt b...@kernel.crashing.org There are still some unstable bits on the DD1 and DD1.1 cores. Don't use the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1 for additional workarounds in later patches. The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 defined. Isn't the policy generally not to commit workarounds for early/errataful hardware which will not be seen in the real world? Otherwise, every new half-broken core could burn a bunch of feature bits... -Hollis I'm with Hollis. Cluttering the code with non-production errata could get very ugly as well as burning feature bits up like made. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Strange OOPS in 2.6.33
Got this OOPS a few times after coldstarting out
board a few times:
Unable to handle kernel paging request for unknown fault
Faulting instruction address: 0xc020e2b4
Oops: Kernel access of bad area, sig: 11 [#1]
TMCUTU
Modules linked in:
NIP: c020e2b4 LR: c020e274 CTR:
REGS: c7a41b40 TRAP: 0600 Not tainted (2.6.33)
MSR: 9032 EE,ME,IR,DR CR: 28002424 XER:
DAR: 09f52312, DSISR: 0120
TASK = c7889940[420] 'syslogd' THREAD: c7a4
GPR00: 09f52312 c7a41bf0 c7889940 0002 c7a41c40 c02734ac c78acc68
GPR08: c7a41c00 c78acc00 09f5214b c796e3d4 1001f444 bfe78700
GPR16: bfe77400 bfe77ee0 bfe773f8 0021 0ffef130 c7a41df0
GPR24: c7a41cf0 c7a41c70 0011 7f01 09f5214a c034a5cc c7a41c00
NIP [c020e2b4] ip_dev_find+0x90/0xf0
LR [c020e274] ip_dev_find+0x50/0xf0
Call Trace:
[c7a41bf0] [c020e274] ip_dev_find+0x50/0xf0 (unreliable)
[c7a41c60] [c01dd86c] __ip_route_output_key+0x8d4/0xb00
[c7a41d50] [c01ddab8] ip_route_output_flow+0x1c/0xa0
[c7a41d60] [c01ff8a0] ip4_datagram_connect+0x17c/0x2b8
[c7a41e30] [c020a75c] inet_dgram_connect+0x5c/0xa8
[c7a41e50] [c01a5030] sys_connect+0x7c/0xcc
[c7a41f00] [c01a6008] sys_socketcall+0x128/0x214
[c7a41f40] [c0011800] ret_from_syscall+0x0/0x38
--- Exception: c01 at 0xff6e004
LR = 0xfe2dac0
Instruction dump:
bb810060 38210070 7c0803a6 4e800020 88010052 2f82 409e0028 81210054
83a90068 2f9d 419e0018 381d01c8 7d200028 31290001 7d20012d 40a2fff4
---[ end trace 0824e85bac28e7e4 ]---
gdb says:
(gdb) list *0xc020e2b4
0xc020e2b4 is in ip_dev_find (/usr/local/src/BUILD/trunk/os2kernel/arch/
powerpc/include/asm/atomic.h:106).
101
102 static __inline__ void atomic_inc(atomic_t *v)
103 {
104 int t;
105
106 __asm__ __volatile__(
107 1: lwarx %0,0,%2 # atomic_inc\n\
108 addic %0,%0,1\n
109 PPC405_ERR77(0,%2)
110 stwcx. %0,0,%2 \n\
gdb) disass 0xc020e2b4 0xc020e2c4
Dump of assembler code from 0xc020e2b4 to 0xc020e2c4:
0xc020e2b4 ip_dev_find+144: lwarx r9,0,r0
0xc020e2b8 ip_dev_find+148: addic r9,r9,1
0xc020e2bc ip_dev_find+152: stwcx. r9,0,r0
0xc020e2c0 ip_dev_find+156: bne-0xc020e2b4 ip_dev_find+144
This is on a MPC8321 CPU
gcc 3.4.6
Any ideas?
Got a bit further, turn out that the dev ptr returned from
dev = FIB_RES_DEV(res) is bogus in ip_dev_find:
struct net_device * ip_dev_find(struct net *net, __be32 addr)
{
struct flowi fl = { .nl_u = { .ip4_u = { .daddr = addr } } };
struct fib_result res;
struct net_device *dev = NULL;
struct fib_table *local_table;
#ifdef CONFIG_IP_MULTIPLE_TABLES
res.r = NULL;
#endif
local_table = fib_get_table(net, RT_TABLE_LOCAL);
if (!local_table || fib_table_lookup(local_table, fl, res))
return NULL;
if (res.type != RTN_LOCAL)
goto out;
dev = FIB_RES_DEV(res);
if (dev)
dev_hold(dev);
out:
fib_res_put(res);
return dev;
}
I have no idea how to proceed from here. Problem happens when user space
makes its first access to eth0, in this case ntpdate. It is very hard to repeat
the problem so it feels like a race somewhere in interface bringup
Jocke
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[PATCH V2] powerpc/mpc512x: Add gpio driver
This patch adds a gpio driver for MPC512X PowerPCs.
It has been tested on our CAN-CBX-CPU5201 module that
uses a MPC5121 CPU. This platform comes with a couple of
LEDs and configuration switches that have been used for testing.
Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu
---
v2: - move driver to arch/powerpc/platforms/512x directory
- Kconfig changes are now in arch/powerpc/platform/512x/Kconfig
- put struct mpc512x_gpio_regs in driver's .c file
- rename GPIO_MASK into MPC512x_GPIO_MASK
- use shadow registers instead of r/m/w-operations
- don't use arch_initcall but call mpc512x_add_gpiochips()
from mpc512x platform setup code.
arch/powerpc/platforms/512x/Kconfig |9 ++
arch/powerpc/platforms/512x/Makefile |1 +
arch/powerpc/platforms/512x/mpc512x.h|3 +
arch/powerpc/platforms/512x/mpc512x_gpio.c | 198 ++
arch/powerpc/platforms/512x/mpc512x_shared.c |3 +
5 files changed, 214 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/512x/mpc512x_gpio.c
diff --git a/arch/powerpc/platforms/512x/Kconfig
b/arch/powerpc/platforms/512x/Kconfig
index 4dac9b0..840c6b4 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -10,6 +10,15 @@ config PPC_MPC5121
bool
select PPC_MPC512x
+config MPC512x_GPIO
+ bool MPC512x GPIO support
+ depends on PPC_MPC512x
+ select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ help
+ Say Y here if you're going to use hardware that connects to the
+ MPC512x GPIOs.
+
config MPC5121_ADS
bool Freescale MPC5121E ADS
depends on 6xx
diff --git a/arch/powerpc/platforms/512x/Makefile
b/arch/powerpc/platforms/512x/Makefile
index 90be2f5..12518e3 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -4,3 +4,4 @@
obj-y += clock.o mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC5121_GENERIC) += mpc5121_generic.o
+obj-$(CONFIG_MPC512x_GPIO) += mpc512x_gpio.o
diff --git a/arch/powerpc/platforms/512x/mpc512x.h
b/arch/powerpc/platforms/512x/mpc512x.h
index b2daca0..4c67990 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -16,4 +16,7 @@ extern void __init mpc512x_init(void);
extern int __init mpc5121_clk_init(void);
void __init mpc512x_declare_of_platform_devices(void);
extern void mpc512x_restart(char *cmd);
+#ifdef CONFIG_MPC512x_GPIO
+extern int __init mpc512x_add_gpiochips(void);
+#endif
#endif /* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_gpio.c
b/arch/powerpc/platforms/512x/mpc512x_gpio.c
new file mode 100644
index 000..fc6ad82
--- /dev/null
+++ b/arch/powerpc/platforms/512x/mpc512x_gpio.c
@@ -0,0 +1,198 @@
+/*
+ * MPC512x gpio driver
+ *
+ * Copyright (c) 2010 Matthias Fuchs matthias.fu...@esd.eu, esd gmbh
+ *
+ * derived from ppc4xx gpio driver
+ *
+ * Copyright (c) 2008 Harris Corporation
+ * Copyright (c) 2008 Sascha Hauer s.ha...@pengutronix.de, Pengutronix
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *
+ * Author: Steve Falco sfa...@harris.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/spinlock.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/gpio.h
+#include linux/types.h
+
+#define MPC512x_GPIO_MASK(gpio) (0x8000 (gpio))
+
+struct mpc512x_gpio_regs {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr1;
+ u32 gpicr2;
+};
+
+struct mpc512x_chip {
+ struct of_mm_gpio_chip mm_gc;
+ spinlock_t lock;
+
+ /* shadow registers */
+ u32 dat;
+ u32 odr;
+ u32 dir;
+};
+
+/*
+ * GPIO LIB API implementation for GPIOs
+ *
+ * There are a maximum of 32 gpios in each gpio controller.
+ */
+static inline struct mpc512x_chip *
+to_mpc512x_gpiochip(struct of_mm_gpio_chip *mm_gc)
+{
+ return container_of(mm_gc, struct mpc512x_chip, mm_gc);
+}
+
+static int mpc512x_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct
Re: JFFS2 warnings
Hello, I too facing the same problems. I too have mpc8313 based customized board. Would you please let me know, if you know how to resolve these messages. Kindly please acknowledge, thank you Kind Regards, Vijay Nikam On Tue, Mar 2, 2010 at 12:13 AM, Ron Madrid ron_mad...@sbcglobal.netwrote: I'm getting a bunch of these after I 'reboot' or 'poweroff' several times. Empty flash at 0x0056205c ends at 0x00562800 Empty flash at 0x00565334 ends at 0x00565800 Empty flash at 0x00576104 ends at 0x00576800 JFFS2 notice: (848) check_node_data: wrong data CRC in data node at 0x00577034: read 0xe6adad18, calculated 0x202a305c. JFFS2 notice: (848) check_node_data: wrong data CRC in data node at 0x00575768: read 0xe6adad18, calculated 0xfc64f8a3. I'm not too sure why I'm getting these, but recently they seem to have caused a few problems with parts of my filesystem (i.e. programs not running correctly). Can someone tell me what these are or what could be causing them? I'm using 2.6.33rc1 and this is on an mpc8313 based board. Not sure what other info would be useful. Thanks, Ron ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/4] 8xx: Optimize TLB Miss code.
Heiko Schocher h...@denx.de wrote on 2010/03/04 17:30:07: Hello Joakim, Joakim Tjernlund wrote: Wolfgang Denk w...@denx.de wrote on 2010/03/04 13:16:56: From: Wolfgang Denk w...@denx.de To: h...@denx.de Cc: Joakim Tjernlund joakim.tjernl...@transmode.se, Klaus-Jürgen heyd...@kieback-peter.de, linuxppc-...@ozlabs.org, Scott Wood scottw...@freescale.com Date: 2010/03/04 13:17 Subject: Re: [PATCH 0/4] 8xx: Optimize TLB Miss code. Dear Heiko, thanks for running the tests. In message 4b8f8bb4.6070...@denx.de you wrote: here the results: run version 1-4 2.6.33-rc6 without your patches 5-8 2.6.33-rc6 with all your patches 9-12 2.6.33-rc6 with patches 1,2 and 4 (without 8xx: Don't touch ACCESSED when no SWAP) 13-16 2.6.33-rc6 with all your patches and CONFIG_PIN_TLB=y So CONFIG_PIN_TLB imroves the performance as expected, while the other patches don;t show any measurable improvememt - or am I reading the results incorrectly? Close but not quite. What stands out most is: Memory latencies in nanoseconds - smaller is better (WARNING - may not be correct, check graphs) -- Host OS Mhz L1 $ L2 $Main memRand mem Guesses - - --- --- tqm8xxLinux 2.6.33-66 31.8 141.0 184.0 1165.7 tqm8xxLinux 2.6.33-66 31.8 141.2 184.2 1165.3 tqm8xxLinux 2.6.33-66 31.8 141.3 184.3 1165.6 tqm8xxLinux 2.6.33-66 31.8 141.3 184.2 1166.2 tqm8xxLinux 2.6.33-66 31.8 141.0 171.8 1100.5No L2 cache? tqm8xxLinux 2.6.33-66 31.8 141.0 171.8 1102.5No L2 cache? tqm8xxLinux 2.6.33-66 31.8 141.0 171.8 1101.7No L2 cache? tqm8xxLinux 2.6.33-66 31.8 141.0 171.8 1101.6No L2 cache? tqm8xxLinux 2.6.33-66 31.8 141.1 173.4 1149.1No L2 cache? tqm8xxLinux 2.6.33-66 31.8 141.1 173.4 1149.0No L2 cache? tqm8xxLinux 2.6.33-66 31.7 141.1 173.4 1148.7No L2 cache? tqm8xxLinux 2.6.33-66 31.7 141.1 173.4 1148.2No L2 cache? tqm8xxLinux 2.6.33-66 31.8 171.1 171.7 1099.8No L2 cache? tqm8xxLinux 2.6.33-66 31.8 171.1 171.6 1100.5No L2 cache? tqm8xxLinux 2.6.33-66 31.7 171.0 171.7 1101.0No L2 cache? tqm8xxLinux 2.6.33-66 31.8 171.0 171.6 1101.3No L2 cache? Besides the numbers, note how the first group doesn't have a Guesses entry. Is there something odd with the results for the first group? Hmm.. just to be safe, I made this test again, but it shows also no entry in Guesses ... Hardware, Linux Source, rootFS, lmbench sources, all the same ... OK Also, since you are using MODULES, patch 2 is nullified. Patch 1 is very minor and should not show I think. This leaves patches 3 4. There appears to be something funny with patch 3,Don't touch ACCESSED when no SWAP, as it yields bad numbers for Prot Fault so perhaps I am missing something that needs ACCESSED even if NO_SWAP. Perhaps a someone that knows MM in Linux knows? Is there any messages in the kernel log(dmesg)? I couldn;t find something in the output with dmesg ... but if you want this output, I can send it to you. No, if you can't find anything in there, I won't either. What would be interesting is to skip patch 3 and turn off MODULES add PIN_TLB and compare that against your unpatched .33 but with MODULES off and PIN_TLB on Jocke ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC: PATCH 08/13] powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
On Fri, 2010-03-05 at 03:15 -0600, Kumar Gala wrote: On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote: On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp sha...@linux.vnet.ibm.com wrote: powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores From: Benjamin Herrenschmidt b...@kernel.crashing.org There are still some unstable bits on the DD1 and DD1.1 cores. Don't use the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1 for additional workarounds in later patches. The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 defined. Isn't the policy generally not to commit workarounds for early/errataful hardware which will not be seen in the real world? Otherwise, every new half-broken core could burn a bunch of feature bits... -Hollis I'm with Hollis. Cluttering the code with non-production errata could get very ugly as well as burning feature bits up like made. Ben's going to make the decision on whether or not these patches should be included into mainline. I'd be happy maintaining them separately if not. I'm separating out the DD1 workaround from the others, since it's less likely that one will be needed long-term. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] powerpc: add support for new hcall H_BEST_ENERGY
On Wed, Mar 03, 2010 at 11:48:22PM +0530, Vaidyanathan Srinivasan wrote:
static void __init cpu_init_thread_core_maps(int tpc)
diff --git a/arch/powerpc/platforms/pseries/Kconfig
b/arch/powerpc/platforms/pseries/Kconfig
index c667f0f..b3dd108 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -33,6 +33,16 @@ config PSERIES_MSI
depends on PCI_MSI EEH
default y
+config PSERIES_ENERGY
+ tristate pseries energy management capabilities driver
+ depends on PPC_PSERIES
+ default y
+ help
+ Provides interface to platform energy management capabilities
+ on supported PSERIES platforms.
+ Provides: /sys/devices/system/cpu/pseries_(de)activation_hint_list
+ and /sys/devices/system/cpu/cpuN/pseries_(de)activation_hint
+
config SCANLOG
tristate Scanlog dump interface
depends on RTAS_PROC PPC_PSERIES
.
+static int __init pseries_energy_init(void)
+{
+ int cpu, err;
+ struct sys_device *cpu_sys_dev;
+
+ /* Create the sysfs files */
+ err = sysfs_create_file(cpu_sysdev_class.kset.kobj,
+ attr_cpu_activate_hint_list.attr);
+ if (!err)
+ err = sysfs_create_file(cpu_sysdev_class.kset.kobj,
+ attr_cpu_deactivate_hint_list.attr);
+
+ for_each_possible_cpu(cpu) {
+ cpu_sys_dev = get_cpu_sysdev(cpu);
+ err = sysfs_create_file(cpu_sys_dev-kobj,
+ attr_percpu_activate_hint.attr);
+ if (err)
+ break;
+ err = sysfs_create_file(cpu_sys_dev-kobj,
+ attr_percpu_deactivate_hint.attr);
+ if (err)
+ break;
+ }
+ return err;
+
+}
Shouldn't we create this only for supported platforms ?
Thanks
Dipankar
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Re: [PATCH 1/4] gpiolib: Introduce chip addition/removal notifier
On Tue, 9 Feb 2010 10:16:44 -0700 Grant Likely grant.lik...@secretlab.ca wrote: On Fri, Feb 5, 2010 at 1:32 PM, Anton Vorontsov avoront...@ru.mvista.com wrote: Some platforms (e.g. OpenFirmware) want to know when a particular chip added or removed, so that the platforms could add their specifics for non-platform devices, like I2C or SPI GPIO chips. This patch implements the notifier for chip addition and removal events. Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com --- drivers/gpio/gpiolib.c | 14 ++ include/asm-generic/gpio.h | 8 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 350842a..375c03a 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -9,6 +9,7 @@ #include linux/seq_file.h #include linux/gpio.h #include linux/idr.h +#include linux/notifier.h /* Optional implementation infrastructure for GPIO interfaces. @@ -1029,6 +1030,9 @@ static inline void gpiochip_unexport(struct gpio_chip *chip) #endif /* CONFIG_GPIO_SYSFS */ +BLOCKING_NOTIFIER_HEAD(gpio_notifier); +EXPORT_SYMBOL_GPL(gpio_notifier); + /** * gpiochip_add() - register a gpio_chip * @chip: the chip to register, with chip-base initialized @@ -1103,6 +1107,9 @@ fail: pr_err(gpiochip_add: gpios %d..%d (%s) not registered\n, chip-base, chip-base + chip-ngpio - 1, chip-label ? : generic); +else +blocking_notifier_call_chain(gpio_notifier, + GPIO_NOTIFY_CHIP_ADDED, chip); Rather than doing an else block which will need to be reworked if/when any additional code is added to the bottom of this routine, please rework the if() block to bail on failure instead of implicitly falling through to the return statement. This still hasn't happened. Otherwise, this patch looks okay to me, so you can go ahead and add my: Acked-by: Grant Likely grant.lik...@secretlab.ca I'll merge it anyway and will ask you guys to keep track of this issue, thanks. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/4] gpiolib: Introduce chip addition/removal notifier
On Fri, Mar 05, 2010 at 11:59:18AM -0800, Andrew Morton wrote: [...] /** * gpiochip_add() - register a gpio_chip * @chip: the chip to register, with chip-base initialized @@ -1103,6 +1107,9 @@ fail: pr_err(gpiochip_add: gpios %d..%d (%s) not registered\n, chip-base, chip-base + chip-ngpio - 1, chip-label ? : generic); +else +blocking_notifier_call_chain(gpio_notifier, + GPIO_NOTIFY_CHIP_ADDED, chip); Rather than doing an else block which will need to be reworked if/when any additional code is added to the bottom of this routine, please rework the if() block to bail on failure instead of implicitly falling through to the return statement. This still hasn't happened. It's in your tree already :-) gpiolib-cosmetic-improvements-for-error-handling-in-gpiochip_add.patch -- Anton Vorontsov email: cbouatmai...@gmail.com irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 02/13] powerpc/44x: break out cpu init code into stand-alone function
powerpc/44x: break out cpu init code into stand-alone function From: Dave Kleikamp sha...@linux.vnet.ibm.com The 47x platform supports multiple cores and shares code with 44x. Break out code that is common for initializing the primary and secondary cpus into a function which can be called for both. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_44x.S | 330 +--- 1 files changed, 171 insertions(+), 159 deletions(-) diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 711368b..39be049 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -69,165 +69,7 @@ _ENTRY(_start); mr r27,r7 li r24,0 /* CPU number */ -/* - * In case the firmware didn't do it, we apply some workarounds - * that are good for all 440 core variants here - */ - mfspr r3,SPRN_CCR0 - rlwinm r3,r3,0,0,27/* disable icache prefetch */ - isync - mtspr SPRN_CCR0,r3 - isync - sync - -/* - * Set up the initial MMU state - * - * We are still executing code at the virtual address - * mappings set by the firmware for the base of RAM. - * - * We first invalidate all TLB entries but the one - * we are running from. We then load the KERNELBASE - * mappings so we can begin to use kernel addresses - * natively and so the interrupt vector locations are - * permanently pinned (necessary since Book E - * implementations always have translation enabled). - * - * TODO: Use the known TLB entry we are running from to - * determine which physical region we are located - * in. This can be used to determine where in RAM - * (on a shared CPU system) or PCI memory space - * (on a DRAMless system) we are located. - * For now, we assume a perfect world which means - * we are located at the base of DRAM (physical 0). - */ - -/* - * Search TLB for entry that we are currently using. - * Invalidate all entries but the one we are using. - */ - /* Load our current PID-MMUCR TID and MSR IS-MMUCR STS */ - mfspr r3,SPRN_PID /* Get PID */ - mfmsr r4 /* Get MSR */ - andi. r4,r4,msr...@l /* TS=1? */ - beq wmmucr /* If not, leave STS=0 */ - orisr3,r3,ppc44x_mmucr_...@h/* Set STS=1 */ -wmmucr:mtspr SPRN_MMUCR,r3 /* Put MMUCR */ - sync - - bl invstr /* Find our address */ -invstr:mflrr5 /* Make it accessible */ - tlbsx r23,0,r5/* Find entry we are in */ - li r4,0/* Start at TLB entry 0 */ - li r3,0/* Set PAGEID inval value */ -1: cmpwr23,r4 /* Is this our entry? */ - beq skpinv /* If so, skip the inval */ - tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ -skpinv:addir4,r4,1 /* Increment */ - cmpwi r4,64 /* Are we done? */ - bne 1b /* If not, repeat */ - isync /* If so, context change */ - -/* - * Configure and load pinned entry into TLB slot 63. - */ - - lis r3,page_off...@h - ori r3,r3,page_off...@l - - /* Kernel is at the base of RAM */ - li r4, 0/* Load the kernel physical address */ - - /* Load the kernel PID = 0 */ - li r0,0 - mtspr SPRN_PID,r0 - sync - - /* Initialize MMUCR */ - li r5,0 - mtspr SPRN_MMUCR,r5 - sync - - /* pageid fields */ - clrrwi r3,r3,10/* Mask off the effective page number */ - ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M - - /* xlat fields */ - clrrwi r4,r4,10/* Mask off the real page number */ - /* ERPN is 0 for first 4GB page */ - - /* attrib fields */ - /* Added guarded bit to protect against speculative loads/stores */ - li r5,0 - ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) - -li r0,63/* TLB slot 63 */ - - tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ - tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ - tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ - - /* Force context change */ - mfmsr r0 - mtspr SPRN_SRR1, r0 - lis r0,3...@h - ori r0,r0,3...@l - mtspr SPRN_SRR0,r0 - sync - rfi - - /* If necessary, invalidate original entry we used */ -3: cmpwi
[PATCH 03/13] powerpc/47x: Base ppc476 support
powerpc/47x: Base ppc476 support
From: Dave Kleikamp sha...@linux.vnet.ibm.com
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out. The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cache.h |6
arch/powerpc/include/asm/cputable.h|4
arch/powerpc/include/asm/mmu-44x.h | 51 +++
arch/powerpc/include/asm/mmu.h |1
arch/powerpc/include/asm/reg.h |1
arch/powerpc/include/asm/reg_booke.h | 26 ++
arch/powerpc/kernel/cputable.c | 13 +
arch/powerpc/kernel/entry_32.S |5
arch/powerpc/kernel/head_44x.S | 502 +++-
arch/powerpc/kernel/misc_32.S |9 -
arch/powerpc/kernel/smp.c |8 +
arch/powerpc/mm/44x_mmu.c | 144 +
arch/powerpc/mm/mmu_context_nohash.c |8 +
arch/powerpc/mm/mmu_decl.h |7
arch/powerpc/mm/tlb_nohash_low.S | 118 +++-
arch/powerpc/platforms/44x/Kconfig |9 +
arch/powerpc/platforms/Kconfig.cputype |5
17 files changed, 873 insertions(+), 44 deletions(-)
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 81de6eb..725634f 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -12,8 +12,12 @@
#define L1_CACHE_SHIFT 6
#define MAX_COPY_PREFETCH 4
#elif defined(CONFIG_PPC32)
-#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
+#if defined(CONFIG_PPC_47x)
+#define L1_CACHE_SHIFT 7
+#else
+#define L1_CACHE_SHIFT 5
+#endif
#else /* CONFIG_PPC64 */
#define L1_CACHE_SHIFT 7
#endif
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 80f315e..75b774e 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -365,6 +365,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |
CPU_FTR_NOEXECUTE)
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |
CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
+#define CPU_FTRS_47X (CPU_FTRS_440x6)
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
@@ -453,6 +454,9 @@ enum {
#ifdef CONFIG_44x
CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif
+#ifdef CONFIG_PPC_47x
+ CPU_FTRS_47X |
+#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 |
#endif
diff --git a/arch/powerpc/include/asm/mmu-44x.h
b/arch/powerpc/include/asm/mmu-44x.h
index 0372669..bf52d70 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -40,7 +40,7 @@
#define PPC44x_TLB_I 0x0400 /* Caching is inhibited */
#define PPC44x_TLB_M 0x0200 /* Memory is coherent */
#define PPC44x_TLB_G 0x0100 /* Memory is guarded */
-#define PPC44x_TLB_E 0x0080 /* Memory is guarded */
+#define PPC44x_TLB_E 0x0080 /* Memory is little endian */
#define PPC44x_TLB_PERM_MASK 0x003f
#define PPC44x_TLB_UX 0x0020 /* User execution */
@@ -53,6 +53,52 @@
/* Number of TLB entries */
#define PPC44x_TLB_SIZE64
+/* 47x bits */
+#define PPC47x_MMUCR_TID 0x
+#define PPC47x_MMUCR_STS 0x0001
+
+/* Page identification fields */
+#define PPC47x_TLB0_EPN_MASK 0xf000 /* Effective Page Number */
+#define PPC47x_TLB0_VALID 0x0800 /* Valid flag */
+#define PPC47x_TLB0_TS 0x0400 /* Translation address space */
+#define PPC47x_TLB0_4K 0x
+#define PPC47x_TLB0_16K0x0010
+#define PPC47x_TLB0_64K0x0030
+#define PPC47x_TLB0_1M 0x0070
+#define PPC47x_TLB0_16M0x00f0
+#define PPC47x_TLB0_256M 0x01f0
+#define PPC47x_TLB0_1G 0x03f0
+#define PPC47x_TLB0_BOLTED_R 0x0008 /* tlbre only */
+
+/* Translation fields */
+#define PPC47x_TLB1_RPN_MASK 0xf000 /* Real Page Number */
+#define PPC47x_TLB1_ERPN_MASK 0x03ff
+
+/* Storage attribute and access control fields */
+#define PPC47x_TLB2_ATTR_MASK 0x0003ff80
+#define PPC47x_TLB2_IL1I 0x0002 /* Memory is guarded */
+#define PPC47x_TLB2_IL1D 0x0001 /* Memory is guarded */
+#define PPC47x_TLB2_U0
[PATCH 01/13] powerpc/booke: Add Stack Marking support to Booke Exception Prolog
powerpc/booke: Add Stack Marking support to Booke Exception Prolog From: Torez Smith lnxto...@linux.vnet.ibm.com This patch adds a marker to the exception stack frame to aid in debugging. It's already inserted on other platforms and xmon recognizes it and identifies exception frames when showing stack traces. Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_booke.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 50504ae..a0bf158 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -1,6 +1,7 @@ #ifndef __HEAD_BOOKE_H__ #define __HEAD_BOOKE_H__ +#include asm/ptrace.h/* for STACK_FRAME_REGS_MARKER */ /* * Macros used for common Book-e exception handling */ @@ -48,6 +49,9 @@ stw r10,0(r11); \ rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ stw r0,GPR0(r11);\ + lis r10, stack_frame_regs_mar...@ha;/* exception frame marker */ \ + addir10, r10, stack_frame_regs_mar...@l; \ + stw r10, 8(r11); \ SAVE_4GPRS(3, r11); \ SAVE_2GPRS(7, r11) -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 05/13] powerpc/476: Add isync after loading mmu and debug spr's
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp sha...@linux.vnet.ibm.com
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/head_44x.S |8
arch/powerpc/kernel/kprobes.c|3 +++
arch/powerpc/kernel/process.c|3 +++
arch/powerpc/kernel/traps.c |6 ++
arch/powerpc/mm/44x_mmu.c|1 +
arch/powerpc/mm/tlb_nohash_low.S |3 +++
6 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 1acd175..992e9d5 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -464,6 +464,9 @@ finish_tlb_load_44x:
lwz r11,PGDIR(r11)
mfspr r12,SPRN_PID/* Get PID */
4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
/* Mask of required permission bits. Note that while we
* do copy ESR:ST to _PAGE_RW position as trying to write
@@ -561,6 +564,9 @@ finish_tlb_load_44x:
lwz r11,PGDIR(r11)
mfspr r12,SPRN_PID/* Get PID */
4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
/* Make up the required permissions */
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
@@ -1031,6 +1037,7 @@ clear_utlb_entry:
mtspr SPRN_USPCR,r3
LOAD_REG_IMMEDIATE(r3, 0x12345670)
mtspr SPRN_ISPCR,r3
+ isync /* 476 needs this */
/* Force context change */
mfmsr r0
@@ -1116,6 +1123,7 @@ head_start_common:
/* Establish the interrupt vector base */
lis r4,interrupt_b...@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
+ isync /* 476 needs this */
addis r22,r22,kernelb...@h
mtlrr22
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index c932978..7fec5db 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -113,6 +113,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p,
struct pt_regs *regs)
#ifdef CONFIG_BOOKE
regs-msr = ~MSR_CE;
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
#endif
/*
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7b816da..15ee756 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -286,6 +286,9 @@ int set_dabr(unsigned long dabr)
/* XXX should we have a CPU_FTR_HAS_DABR ? */
#if defined(CONFIG_BOOKE)
mtspr(SPRN_DAC1, dabr);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
#elif defined(CONFIG_PPC_BOOK3S)
mtspr(SPRN_DABR, dabr);
#endif
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 21ed77b..9957c44 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1080,6 +1080,9 @@ void __kprobes DebugException(struct pt_regs *regs,
unsigned long debug_status)
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~DBCR0_BT);
/* Clear the BT event */
mtspr(SPRN_DBSR, DBSR_BT);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
/* Do the single step trick only when coming from userspace */
if (user_mode(regs)) {
@@ -1102,6 +1105,9 @@ void __kprobes DebugException(struct pt_regs *regs,
unsigned long debug_status)
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~DBCR0_IC);
/* Clear the instruction completion event */
mtspr(SPRN_DBSR, DBSR_IC);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
if (notify_die(DIE_SSTEP, single_step, regs, 5,
5, SIGTRAP) == NOTIFY_STOP) {
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index d8c6efb..a5f082a 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -156,6 +156,7 @@ static void __cpuinit ppc47x_pin_tlb(unsigned int virt,
unsigned int phys)
virt, phys, bolted);
mtspr(SPRN_MMUCR, 0);
+ isync();
__asm__ __volatile__(
tlbwe %2,%3,0\n
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index e925cb5..7c890f7 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -92,6 +92,9 @@ _GLOBAL(__tlbil_va)
*/
wrteei 0
mtspr SPRN_MMUCR,r5
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
tlbsx. r6,0,r3
bne 10f
sync
--
Dave Kleikamp
IBM Linux Technology Center
[PATCH 07/13] powerpc/47x: defconfig for 476 on the iss 4xx simulator
powerpc/47x: defconfig for 476 on the iss 4xx simulator From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/configs/44x/iss476-smp_defconfig | 1026 + 1 files changed, 1026 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/configs/44x/iss476-smp_defconfig diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig new file mode 100644 index 000..8683cbc --- /dev/null +++ b/arch/powerpc/configs/44x/iss476-smp_defconfig @@ -0,0 +1,1026 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33 +# Thu Mar 4 11:50:12 2010 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +CONFIG_EVENT_PROFILE=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set
[PATCH 08/13] powerpc/476: define specific cpu table entry DD1.1 core
powerpc/476: define specific cpu table entry DD1.1 core
From: Benjamin Herrenschmidt b...@kernel.crashing.org
There are still some unstable bits in the DD1.1 cores. Don't use
the FPU or the tlbivax operation. Define CPU_FTR_476_DD1_1 for additional
workarounds in later patches.
The DD1 core requires an additional workaround that will be addressed
in a separate patch, which may not need to be picked up into the
mainline kernel.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c | 26 --
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 9fff628..7c5d490 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -153,6 +153,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x2000)
#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x4000)
#define CPU_FTR_NO_DPM ASM_CONST(0x8000)
+#define CPU_FTR_476_DD1_1 ASM_CONST(0x0001)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0002)
#define CPU_FTR_NO_BTICASM_CONST(0x0004)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0010)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index a06e6d3..cb9e6b7 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1701,15 +1701,15 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
- { /* 476 core */
+ { /* 476 DD1.1 core */
.pvr_mask = 0x,
- .pvr_value = 0x11a5,
+ .pvr_value = 0x11a52040,
.cpu_name = 476,
- .cpu_features = CPU_FTRS_47X,
- .cpu_user_features = COMMON_USER_BOOKE |
- PPC_FEATURE_HAS_FPU,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1_1 |
+ CPU_FTR_FPU_UNAVAILABLE,
+ .cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
- MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+ MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
.machine_check = machine_check_47x,
@@ -1724,6 +1724,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
PPC_FEATURE_HAS_FPU,
.cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
+ { /* 476 others */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a52000,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X,
+ .cpu_user_features = COMMON_USER_BOOKE |
+ PPC_FEATURE_HAS_FPU,
+ .mmu_features = MMU_FTR_TYPE_47x |
MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
--
Dave Kleikamp
IBM Linux Technology Center
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[PATCH 06/13] powerpc/4xx: Simple platform for the ISS 4xx simulator
powerpc/4xx: Simple platform for the ISS 4xx simulator
From: Torez Smith lnxto...@linux.vnet.ibm.com
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/boot/Makefile|5 +
arch/powerpc/boot/dts/iss4xx-mpic.dts | 155 +++
arch/powerpc/boot/dts/iss4xx.dts | 116 +++
arch/powerpc/boot/treeboot-iss4xx.c | 56 +++
arch/powerpc/boot/wrapper |3 +
arch/powerpc/include/asm/reg.h|3 +
arch/powerpc/kernel/cputable.c| 15 +++
arch/powerpc/kernel/head_44x.S|2
arch/powerpc/platforms/44x/Kconfig| 11 ++
arch/powerpc/platforms/44x/Makefile |1
arch/powerpc/platforms/44x/iss4xx.c | 165 +
11 files changed, 531 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/iss4xx-mpic.dts
create mode 100644 arch/powerpc/boot/dts/iss4xx.dts
create mode 100644 arch/powerpc/boot/treeboot-iss4xx.c
create mode 100644 arch/powerpc/platforms/44x/iss4xx.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index bb2465b..997196e 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -77,7 +78,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c
cuboot-85xx.c holly.c
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c
\
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
- gamecube-head.S gamecube.c wii-head.S wii.c
+ gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -206,6 +207,8 @@ image-$(CONFIG_TAISHAN) +=
cuImage.taishan
image-$(CONFIG_KATMAI) += cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
+image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
+ treeImage.iss4xx-mpic
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss4xx-mpic.dts
b/arch/powerpc/boot/dts/iss4xx-mpic.dts
new file mode 100644
index 000..23e9d9b
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss4xx-mpic.dts
@@ -0,0 +1,155 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2010 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer jwbo...@linux.vnet.ibm.com, David Gibson d...@au1.ibm.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x01f0 0x0010;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx;
+ dcr-parent = {/cpus/c...@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ c...@0 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = ok;
+ };
+ c...@1 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 1;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
[PATCH 09/13] powerpc/476: Workaround for dcbf/dcbz workaround on DD1
powerpc/476: Workaround for dcbf/dcbz workaround on DD1 From: Benjamin Herrenschmidt b...@kernel.crashing.org On the DD1.1 core, the dcbf and dcbz instructions need to be preceded and followed by an lwsync. We must trap user-space to ensure that this occurs there too. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h | 10 +++ arch/powerpc/include/asm/ppc-opcode.h |4 +++ arch/powerpc/include/asm/reg_booke.h |9 +++ arch/powerpc/kernel/entry_32.S| 35 +++--- arch/powerpc/kernel/head_44x.S|9 +++ arch/powerpc/kernel/misc_32.S | 32 ++- arch/powerpc/kernel/traps.c | 45 + arch/powerpc/lib/copy_32.S|7 - 8 files changed, 145 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index 8f0fe79..bee05ec 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -64,6 +64,16 @@ #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif + +#ifdef CONFIG_PPC_47x +#define PPC476_ERR_DCBx() \ + BEGIN_FTR_SECTION; \ + lwsync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else +#define PPC476_ERR_DCBx() +#endif /* CONFIG_PPC_47x */ + #endif #endif /* _ASM_POWERPC_ASM_COMPAT_H */ diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ef9aa84..629b1fe 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -19,6 +19,10 @@ #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe #define PPC_INST_DCBAL 0x7c2005ec +#define PPC_INST_DCBF 0x7cac +#define PPC_INST_DCBF_MASK 0xfc0007fe +#define PPC_INST_DCBZ 0x7c0007ec +#define PPC_INST_DCBZ_MASK 0xfc0007fe #define PPC_INST_DCBZL 0x7c2007ec #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ee61a9d..8153093 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -276,6 +276,8 @@ #define ESR_IMCN 0x4000 /* Instr. Machine Check - Non-config */ #define ESR_IMCB 0x2000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x1000 /* Instr. Machine Check - Timeout */ +#define ESR_POT1 0x2000 /* 476 - IOCR1 trap */ +#define ESR_POT2 0x1000 /* 476 - IOCR2 trap */ #define ESR_PIL0x0800 /* Program Exception - Illegal */ #define ESR_PPR0x0400 /* Program Exception - Privileged */ #define ESR_PTR0x0200 /* Program Exception - Trap */ @@ -535,6 +537,13 @@ #define MMUBE1_VBE30x0004 #define MMUBE1_VBE40x0002 #define MMUBE1_VBE50x0001 +#define SPRN_IOCCR 860 +#defineIOCCR_IOCR1EN 0x8000 +#defineIOCCR_IOCR1M0x4000 +#defineIOCCR_IOCR2EN 0x2000 +#defineIOCCR_IOCR2M0x1000 +#define SPRN_IOCR1 861 +#define SPRN_IOCR2 862 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ed4aeb9..57b7893 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -142,6 +142,12 @@ transfer_to_handler: addir2,r12,-THREAD tovirt(r2,r2) /* set r2 to current */ beq 2f /* if from user, fix up THREAD.regs */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ addir11,r1,STACK_FRAME_OVERHEAD stw r11,PT_REGS(r12) #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) @@ -280,6 +286,12 @@ stack_ovf: 0: _GLOBAL(DoSyscall) +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ stw r3,ORIG_GPR3(r1) li r12,0 stw r12,RESULT(r1) @@ -381,6 +393,16 @@ BEGIN_MMU_FTR_SECTION 1: END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x) #endif /* CONFIG_44x */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + lwz r7,_MSR(r1) + andi. r5,r7,MSR_PR + beq 11f + lis r4,(IOCCR_IOCR1EN|IOCCR_IOCR2EN)@h + mtspr
[PATCH 10/13] powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |7 ++- arch/powerpc/kernel/head_booke.h |3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index bee05ec..1890fbf 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -70,8 +70,13 @@ BEGIN_FTR_SECTION; \ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) -#else +#define PPC476_ERR_ISYNC() \ + BEGIN_FTR_SECTION; \ + isync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() +#define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ #endif diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index a0bf158..c6f5dcd 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -164,7 +164,8 @@ */ #defineSTART_EXCEPTION(label) \ .align 5; \ -label: +label: \ + PPC476_ERR_ISYNC() #define FINISH_EXCEPTION(func) \ bl transfer_to_handler_full; \ -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 11/13] powerpc/476: Software workaround to fix dcr read/write sequencing.
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only otherwise used by critical interrupts,
and we don't care if what we write is overwritten.
Ideally, would only do this when CPU_FTR_476_DD1_1 is set, but I'm not
getting the feature macros working in inlined assembler. The dummy store
is pretty cheap though, so I'm doing it unconditionally for 47x.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/dcr-native.h | 24 ++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/dcr-native.h
b/arch/powerpc/include/asm/dcr-native.h
index 7d2e623..768ce50 100644
--- a/arch/powerpc/include/asm/dcr-native.h
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -50,14 +50,34 @@ extern unsigned int __mfdcr(unsigned int reg);
static inline unsigned int mfdcrx(unsigned int reg)
{
unsigned int ret;
- asm volatile(.long 0x7c000206 | (%0 21) | (%1 16)
+ asm volatile(
+#ifdef CONFIG_PPC_47x
+ /*
+* Workaround: move reg to an spr prior to mfdcrx instruction
+*/
+/* __stringify(BEGIN_FTR_SECTION) */
+mtspr __stringify(SPRN_SPRG_WSCRATCH_CRIT),%1;
+/* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */
+#endif
+.long 0x7c000206 | (%0 21) | (%1 16)
: =r (ret) : r (reg));
return ret;
}
static inline void mtdcrx(unsigned int reg, unsigned int val)
{
- asm volatile(.long 0x7c000306 | (%0 21) | (%1 16)
+ asm volatile(
+#ifdef CONFIG_PPC_47x
+ /*
+* Workaround: move reg to an spr prior to mtdcrx instruction.
+* (Would love to get the FTR_SECTION macros working for
+* inlined assembler -- shaggy)
+*/
+/* __stringify(BEGIN_FTR_SECTION) */
+mtspr __stringify(SPRN_SPRG_WSCRATCH_CRIT),%1;
+/* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */
+#endif
+.long 0x7c000306 | (%0 21) | (%1 16)
: : r (val), r (reg));
}
--
Dave Kleikamp
IBM Linux Technology Center
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[PATCH 12/13] powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |2 ++ arch/powerpc/kernel/head_44x.S|1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index 1890fbf..fd16e3a 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -70,12 +70,14 @@ BEGIN_FTR_SECTION; \ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#define PPC476_ERR_MTPID PPC476_ERR_DCBx #define PPC476_ERR_ISYNC() \ BEGIN_FTR_SECTION; \ isync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) #else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() +#define PPC476_ERR_MTPID() #define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index a96796d..c27b0cd 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -705,6 +705,7 @@ _GLOBAL(set_context) stw r4, 0x4(r5) #endif mtspr SPRN_PID,r3 + PPC476_ERR_MTPID() isync /* Force context change */ blr -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 13/13] powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/asm-compat.h |5 +
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c| 14 ++
arch/powerpc/kernel/head_booke.h |3 +++
4 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/asm-compat.h
b/arch/powerpc/include/asm/asm-compat.h
index fd16e3a..43e9d1b 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -71,6 +71,10 @@
lwsync; \
END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)
#define PPC476_ERR_MTPID PPC476_ERR_DCBx
+#define PPC476_ERR_DCI() \
+ BEGIN_FTR_SECTION; \
+ dci;\
+ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1)
#define PPC476_ERR_ISYNC() \
BEGIN_FTR_SECTION; \
isync; \
@@ -78,6 +82,7 @@
#else /* ! CONFIG_PPC_47x */
#define PPC476_ERR_DCBx()
#define PPC476_ERR_MTPID()
+#define PPC476_ERR_DCI()
#define PPC476_ERR_ISYNC()
#endif /* CONFIG_PPC_47x */
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 7c5d490..1cf38fb 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -156,6 +156,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_476_DD1_1 ASM_CONST(0x0001)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0002)
#define CPU_FTR_NO_BTICASM_CONST(0x0004)
+#define CPU_FTR_476_DD1ASM_CONST(0x0008)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0010)
#define CPU_FTR_PPC_LE ASM_CONST(0x0020)
#define CPU_FTR_REAL_LEASM_CONST(0x0040)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index cb9e6b7..e91bb2e 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1701,6 +1701,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
+ { /* 476 DD1 core - needs DD1.1 feature as well */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a5,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1 |
+ CPU_FTR_476_DD1_1 | CPU_FTR_FPU_UNAVAILABLE,
+ .cpu_user_features = COMMON_USER_BOOKE,
+ .mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
{ /* 476 DD1.1 core */
.pvr_mask = 0x,
.pvr_value = 0x11a52040,
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index c6f5dcd..c8e38c8 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -174,12 +174,14 @@ label:
\
#define EXCEPTION(n, label, hdlr, xfer)\
START_EXCEPTION(label); \
+ PPC476_ERR_DCI(); \
NORMAL_EXCEPTION_PROLOG;\
addir3,r1,STACK_FRAME_OVERHEAD; \
xfer(n, hdlr)
#define CRITICAL_EXCEPTION(n, label, hdlr) \
START_EXCEPTION(label); \
+ PPC476_ERR_DCI(); \
CRITICAL_EXCEPTION_PROLOG; \
addir3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL ~(MSR_ME|MSR_DE|MSR_CE)), \
@@ -379,6 +381,7 @@ label:
\
#define DECREMENTER_EXCEPTION\
START_EXCEPTION(Decrementer) \
+ PPC476_ERR_DCI(); \
NORMAL_EXCEPTION_PROLOG; \
lis r0,tsr_...@h; /* Setup the DEC interrupt mask */\
mtspr SPRN_TSR,r0;
Re: [PATCH 3/4] of/gpio: Implement GPIOLIB notifier hooks
On Fri, Mar 5, 2010 at 1:35 PM, Andrew Morton a...@linux-foundation.org wrote:
On Fri, 5 Mar 2010 13:28:32 -0700
Grant Likely grant.lik...@secretlab.ca wrote:
On Fri, Mar 5, 2010 at 1:00 PM, Andrew Morton a...@linux-foundation.org
wrote:
On Tue, 9 Feb 2010 22:16:20 +0300
Anton Vorontsov avoront...@ru.mvista.com wrote:
On Tue, Feb 09, 2010 at 10:13:11AM -0700, Grant Likely wrote:
[...]
+static int __init of_gpio_notifier_init(void)
+{
+ __ __ __ return blocking_notifier_chain_register(gpio_notifier,
of_gpio_nb);
+}
+arch_initcall(of_gpio_notifier_init);
Another concern; __if any gpio chips get registered before this
arch_initcall (not sure if it is possible or not), then those chips
won't get registered with the of gpio infrastructure.
Technically, it is possible, but registering usual GPIO controllers
in arch_initcall feels not quite right approach in the first place
(and, btw, it won't work most of the time, because even early drivers
do not register itself earlier than subsys_initcall).
And arch gpio controllers (like QE GPIO) are usually device-less,
and they use of_mm_gpiochip_add(), so we fully control them.
Plus I don't see any reason why we couldn't move
of_gpio_notifier_init() into, say, postcore_initcall, if we ever
need it.
I'll assume that you're OK with that response.
No, not really,
You left me dangling :(
Sorry, got caught up with other things.
I'm not really very comfortable with the whole
approach being taken. And, while I acked the first patch in the
series, that patch isn't needed by anything except patches 2, 3 4.
Also, the OF stuff is a moving target at the moment with all the
rework is being undertaken. I'd rather let this series sit out for
another merge cycle so that the underlying OF stuff can settle down.
OK, please take it up on-list?
Okay. I'm making this reply on list.
Anton, as I've stated before, I'm not thrilled with the approach.
Combine that with the changes being made to drivers/of right now and
the addition device tree to ARM and other architectures, my preference
is to let this patch series lie fallow for one more merge cycle so
that things can settle out in the OF infrastructure code.
g.
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Re: [PATCH 3/4] of/gpio: Implement GPIOLIB notifier hooks
On Fri, Mar 05, 2010 at 04:47:06PM -0700, Grant Likely wrote: [...] I'm not really very comfortable with the whole approach being taken. And, while I acked the first patch in the series, that patch isn't needed by anything except patches 2, 3 4. But you didn't answer my replies, ie were sitting silent like for a month? So you didn't give my any chance to make them comfortable to you. Is there any punishment ready for that? ;-) I see one: apply these patches, and rework this stuff as you like when you have some time? Or tell me your idea, and I'll do the rework for you, in 2.6.35. But in the meantime, these patches can be nicely used to support I2C/SPI GPIO controllers. Also, the OF stuff is a moving target at the moment with all the rework is being undertaken. I'd rather let this series sit out for another merge cycle so that the underlying OF stuff can settle down. OK, please take it up on-list? Okay. I'm making this reply on list. Anton, as I've stated before, I'm not thrilled with the approach. Again, great timing for telling that, I must say. Yes, you said it once with some minor arguments (doubts and questions), to which I replied long ago. Then nothing. Combine that with the changes being made to drivers/of right now and the addition device tree to ARM and other architectures, my preference is to let this patch series lie fallow for one more merge cycle so that things can settle out in the OF infrastructure code. How exactly OF rework affects these patches? And why some rework should be used as an excuse for not adding a hardware support? -- Anton Vorontsov email: cbouatmai...@gmail.com irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/4] of/gpio: Implement GPIOLIB notifier hooks
On Fri, Mar 5, 2010 at 5:28 PM, Anton Vorontsov avoront...@ru.mvista.com wrote: On Fri, Mar 05, 2010 at 04:47:06PM -0700, Grant Likely wrote: [...] I'm not really very comfortable with the whole approach being taken. And, while I acked the first patch in the series, that patch isn't needed by anything except patches 2, 3 4. But you didn't answer my replies, ie were sitting silent like for a month? So you didn't give my any chance to make them comfortable to you. The last version of the patches were posted on Feb 8. -rc8 was released on Feb 12. For changes to common code, that is a little late for getting queued up for the merge window. If it was a subsystem that I maintain, say SPI, then I doubt I would have picked it up for 2.6.34. But I am not the GPIO maintainer. I've stated my case, I'm not fond of the approach, and I'd rather have another merge cycle before committing to the method of making OF gpio bindings more generic. I missed your request to merge this via the powerpc tree and I had higher priority concerns, so I really didn't think much of it. I assumed that David would look at the arguments and make his own decision. For the record, my main concerns are: - Now that I see the implementation, I think that it is too complex. The bus notifiers really aren't needed and it can be done with much lower impact on the core gpiolib code. - Using notifiers adds an unnecessary race condition, however unlikely. Is there any punishment ready for that? ;-) I see one: apply these patches, and rework this stuff as you like when you have some time? Changes to common code don't work that way. Sometimes things just don't get enough attention and they wait another cycle, get reworked, or get dropped entirely. Or tell me your idea, and I'll do the rework for you, in 2.6.35. But in the meantime, these patches can be nicely used to support I2C/SPI GPIO controllers. ...and anyone who need it immediately is welcome to pull your changes into their private tree. Skipping a cycle is not the end of the world. Combine that with the changes being made to drivers/of right now and the addition device tree to ARM and other architectures, my preference is to let this patch series lie fallow for one more merge cycle so that things can settle out in the OF infrastructure code. How exactly OF rework affects these patches? For one, the device node pointer is moving out of archdata into 'struct device' proper and I've got patches adding OF hooks into the core of the platform bus. If those patches look good to GregKH, then I'll be pursing the same pattern for the other bus types (i2c, spi, etc), and it will be further argument for putting the OF hooks directly into gpiolib instead of using a notifier. I'll be posting the patches as soon as the merge window closes. And why some rework should be used as an excuse for not adding a hardware support? If this was a standalone device driver then I'd agree. However, this is an infrastructure change. Infrastructure changes get more scrutiny and are always harder to merge. Especially just before the merge window opens with very little linux-next exposure. g. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/4] of/gpio: Implement GPIOLIB notifier hooks
On Fri, Mar 05, 2010 at 08:54:56PM -0700, Grant Likely wrote: [...] The last version of the patches were posted on Feb 8. -rc8 was released on Feb 12. For changes to common code, that is a little late for getting queued up for the merge window. If it was a subsystem that I maintain, say SPI, then I doubt I would have picked it up for 2.6.34. And of course the part of the OF rework, which was first posted for *review* on Feb 03, is a completely different story? 48 files changed, 317 insertions(+), 575 deletions(-) It's in Linus' tree now. And the other part of the OF rework that was posted for review on Feb 13 is another story too? It's in Linus' tree as well. Your patches touch 3 architectures, and a lot of the code that is used by all the OF drivers, still 03 and 13 Feb was OK for them. But I am not the GPIO maintainer. David is. And I heard only positive feedback on the patches last time. For the record, my main concerns are: - Now that I see the implementation, I think that it is too complex. The bus notifiers really aren't needed and it can be done with much lower impact on the core gpiolib code. That's a non-argument, what is lower impact? Do I touch any hot paths? And if nothing has changed, David (again, the gpiolib maintainer) is happy with the notifiers approach, why would you care? Anyhow, changing the notifier to a direct call is a matter of a trivial patch that we can queue anytime in 2.6.35. - Using notifiers adds an unnecessary race condition, however unlikely. Where? Is it a real one? I see a lot of race conditions, but none of them because of the notifiers approach. Is there any punishment ready for that? ;-) I see one: apply these patches, and rework this stuff as you like when you have some time? Changes to common code don't work that way. Sometimes things just don't get enough attention and they wait another cycle, get reworked, or get dropped entirely. See above wrt OF rework patches. Or tell me your idea, and I'll do the rework for you, in 2.6.35. But in the meantime, these patches can be nicely used to support I2C/SPI GPIO controllers. ...and anyone who need it immediately is welcome to pull your changes into their private tree. Skipping a cycle is not the end of the world. Using notifiers is not the end of the world either. Combine that with the changes being made to drivers/of right now and the addition device tree to ARM and other architectures, my preference is to let this patch series lie fallow for one more merge cycle so that things can settle out in the OF infrastructure code. How exactly OF rework affects these patches? For one, the device node pointer is moving out of archdata into 'struct device' proper and I've got patches adding OF hooks into the core of the platform bus. If those patches look good to GregKH, then I'll be pursing the same pattern for the other bus types (i2c, spi, etc), and it will be further argument for putting the OF hooks directly into gpiolib instead of using a notifier. I'll be posting the patches as soon as the merge window closes. I don't get it. Why is it a problem to change your patches that ought to be queued for 2.6.*35*? And why some rework should be used as an excuse for not adding a hardware support? If this was a standalone device driver then I'd agree. However, this is an infrastructure change. Infrastructure changes get more scrutiny and are always harder to merge. Especially just before the merge window opens with very little linux-next exposure. See above wrt OF rework patches. -- Anton Vorontsov email: cbouatmai...@gmail.com irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
