Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
On Oct 20, 2010, at 12:12 AM, Zang Roy-R61911 wrote: -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Tuesday, October 19, 2010 21:19 PM To: Zang Roy-R61911 Cc: linux-...@lists.infradead.org; Wood Scott-B07421; dedeki...@gmail.com; Lan Chunhe-B25806; linuxppc-...@ozlabs.org; a...@linux-foundation.org; dw...@infradead.org; Gala Kumar-B11780 Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices On Oct 18, 2010, at 2:22 AM, Roy Zang wrote: Move Freescale elbc interrupt from nand dirver to elbc driver. Then all elbc devices can use the interrupt instead of ONLY nand. For former nand driver, it had the two functions: 1. detecting nand flash partitions; 2. registering elbc interrupt. Now, second function is removed to fsl_lbc.c. Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com Signed-off-by: Roy Zang tie-fei.z...@freescale.com Reviewed-by: Anton Vorontsov cbouatmai...@gmail.com Cc: Wood Scott-B07421 b07...@freescale.com --- Roy, this is a nit, but are these really p4080 specific? just wondering why the subject is P4080/eLBC:... We start these code in P4080 project. Some customer want to track eLBC error on P4080, but some of the code is limited in nand driver only ... That is why P4080/eLBC ... Roy sure, but is anything about these patches p4080 specific? - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: CONFIG_FEC is not good for mpc8xx ethernet?
On MPC8xx you want drivers/net/fs_enet/mii-fec.c. This is just the
MDIO driver; it doesn't handle any particular PHY. I don't know if
there is a driver specifically for AM79C874, though the generic PHY
support may be good enough.
Maybe.
I can found one related patch for supporting PHY AM79C874 on 2.6.15,
--
http://lists.ozlabs.org/pipermail/linuxppc-embedded/2005-November/021043.html
But I don't see that on the latest kernel, and also I don't know the history
completely for that. Maybe its already merged into one generic PHY driver but
I'm not sure.
Thank Scott Tiejun for valuable information.
The problem for me is that the PHY failed to be probed. The related
error messages are shown below. I even tried the patch Tiejun pointed
out. But that doesn't help. The phy ID read from the bus was all Fs.
FEC MII Bus: probed
mdio_bus fa200e00: error probing PHY at address 0
I don't know if AM79C874 requires any special handling. But from the
comment in mdiobb_cmd() there seems to be something special.
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good
* measure. The IEEE spec says this is a PHY optional
* requirement. The AMD 79C874 requires one after power up and
* one after a MII communications error. This means that we are
* doing more preambles than we need, but it is safer and will be
* much more robust.
*/
If there is any network action in u-boot, e.g., tftp or ping, the PHY
can be successfully probed after that. Any hints what went wrong with
the PHY?
Thanks,
-Shawn.
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Re: CONFIG_FEC is not good for mpc8xx ethernet?
Shawn Jin wrote:
On MPC8xx you want drivers/net/fs_enet/mii-fec.c. �This is just the
MDIO driver; it doesn't handle any particular PHY. �I don't know if
there is a driver specifically for AM79C874, though the generic PHY
support may be good enough.
Maybe.
I can found one related patch for supporting PHY AM79C874 on 2.6.15,
--
http://lists.ozlabs.org/pipermail/linuxppc-embedded/2005-November/021043.html
But I don't see that on the latest kernel, and also I don't know the history
completely for that. Maybe its already merged into one generic PHY driver but
I'm not sure.
Thank Scott Tiejun for valuable information.
The problem for me is that the PHY failed to be probed. The related
error messages are shown below. I even tried the patch Tiejun pointed
out. But that doesn't help. The phy ID read from the bus was all Fs.
FEC MII Bus: probed
mdio_bus fa200e00: error probing PHY at address 0
Is this is all log related to PHY? And are you sure your PHY Address is zero?
Often there are at most 32 PHY devices resided one MDIO bus. So you can dump PHY
ID to check if there is a PHY firstly. A ID value of 0x indicates that the
address is invalid if I recalled properly.
But I think PHY driver already do the above process on Linux.
So looks MDIO driver cannot compatible for your platform. I recommend you try
debug mdio driver to access valid PHY ID firstly. Especially where/why this stop
at address '0'? When you can get a valid PHY ID you can go phy driver.
I don't know if AM79C874 requires any special handling. But from the
comment in mdiobb_cmd() there seems to be something special.
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good
* measure. The IEEE spec says this is a PHY optional
* requirement. The AMD 79C874 requires one after power up and
* one after a MII communications error. This means that we are
* doing more preambles than we need, but it is safer and will be
* much more robust.
*/
If there is any network action in u-boot, e.g., tftp or ping, the PHY
can be successfully probed after that. Any hints what went wrong with
On bootstrap the driver should reset MDIO bus/PHY before probing PHY again.
Tiejun
the PHY?
Thanks,
-Shawn.
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RE: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Wednesday, October 20, 2010 14:55 PM To: Zang Roy-R61911 Cc: linux-...@lists.infradead.org; Wood Scott-B07421; dedeki...@gmail.com; Lan Chunhe-B25806; linuxppc-...@ozlabs.org; a...@linux-foundation.org; dw...@infradead.org; Gala Kumar-B11780 Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices On Oct 20, 2010, at 12:12 AM, Zang Roy-R61911 wrote: -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Tuesday, October 19, 2010 21:19 PM To: Zang Roy-R61911 Cc: linux-...@lists.infradead.org; Wood Scott-B07421; dedeki...@gmail.com; Lan Chunhe-B25806; linuxppc-...@ozlabs.org; a...@linux-foundation.org; dw...@infradead.org; Gala Kumar-B11780 Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices On Oct 18, 2010, at 2:22 AM, Roy Zang wrote: Move Freescale elbc interrupt from nand dirver to elbc driver. Then all elbc devices can use the interrupt instead of ONLY nand. For former nand driver, it had the two functions: 1. detecting nand flash partitions; 2. registering elbc interrupt. Now, second function is removed to fsl_lbc.c. Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com Signed-off-by: Roy Zang tie-fei.z...@freescale.com Reviewed-by: Anton Vorontsov cbouatmai...@gmail.com Cc: Wood Scott-B07421 b07...@freescale.com --- Roy, this is a nit, but are these really p4080 specific? just wondering why the subject is P4080/eLBC:... We start these code in P4080 project. Some customer want to track eLBC error on P4080, but some of the code is limited in nand driver only ... That is why P4080/eLBC ... Roy sure, but is anything about these patches p4080 specific? No. Should I update the subject by a new version. Thanks. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: CONFIG_FEC is not good for mpc8xx ethernet?
The problem for me is that the PHY failed to be probed. The related error messages are shown below. I even tried the patch Tiejun pointed out. But that doesn't help. The phy ID read from the bus was all Fs. FEC MII Bus: probed mdio_bus fa200e00: error probing PHY at address 0 I think I figured out the probing failure. My board uses PortD bit8 as an input pin from phy's MDC. I didn't set up this pin assignment. When probing the PHY the fs_enet_fec_mii_read() is called to get phy id. The correct phy id was returned. However when I tried to set up the ip address using the command ifconfig eth0 192.168.0.4. The same function was called again. But this time the fecp-fec_r_cntrl mysteriously became 0 so the kernel reported bug for that. # ifconfig eth0 192.168.0.4 [ cut here ] kernel BUG at drivers/net/fs_enet/mii-fec.c:58! Oops: Exception in kernel mode, sig: 5 [#1] MyMPC870 NIP: c012b79c LR: c012963c CTR: c012b77c REGS: c7457c60 TRAP: 0700 Not tainted (2.6.33.5) MSR: 00029032 EE,ME,CE,IR,DR CR: 24020042 XER: 2000 TASK = c784[236] 'ifconfig' THREAD: c7456000 GPR00: 0001 c7457d10 c784 c7845400 0001 GPR08: c77c44fc c906ce00 c784806c 0b9f 84020042 100b986c 10096042 1009604f GPR16: 1009603b 10096030 10096001 100b188e c7457e18 8914 c742430c c740b000 GPR24: c7424300 c78443c0 0001 c7845428 c7845400 c7845600 c7845600 NIP [c012b79c] fs_enet_fec_mii_read+0x20/0x90 LR [c012963c] mdiobus_read+0x50/0x74 Call Trace: [c7457d10] [c0115744] driver_bound+0x60/0xa0 (unreliable) [c7457d30] [c0129094] genphy_config_init+0x24/0xd4 [c7457d40] [c0128920] phy_init_hw+0x4c/0x78 [c7457d50] [c0128a40] phy_connect_direct+0x24/0x88 [c7457d70] [c0133e50] of_phy_connect+0x48/0x6c [c7457d90] [c012ae10] fs_enet_open+0xf0/0x2cc [c7457db0] [c0148a54] dev_open+0x100/0x138 [c7457dd0] [c0146ca0] dev_change_flags+0x80/0x1a8 [c7457df0] [c018e104] devinet_ioctl+0x630/0x750 [c7457e60] [c018eb5c] inet_ioctl+0xcc/0xf8 [c7457e70] [c01370d8] sock_ioctl+0x60/0x28c [c7457e90] [c007dbcc] vfs_ioctl+0x38/0x9c [c7457ea0] [c007ddf0] do_vfs_ioctl+0x84/0x708 [c7457f10] [c007e4b4] sys_ioctl+0x40/0x74 [c7457f40] [c000de60] ret_from_syscall+0x0/0x38 Instruction dump: 80010014 7c0803a6 38210010 4e800020 81230018 8129 7c0004ac 80090144 0c00 4c00012c 6804 5400f7fe 0f00 5484b810 64846002 54a5925a ---[ end trace 41bf95259a68372e ]--- Trace/breakpoint trap I cannot find where the fec_r_cntrl would be reset to 0 after fs_enet_mdio_probe() sets it to FEC_RCNTRL_MII_MODE. Odd? Thanks, -Shawn. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
On Tue, 2010-10-19 at 22:23 -0500, pac...@kosh.dhis.org wrote: The diff fragment above applied inside prom_close_stdin, but there are some prom_printf calls after prom_close_stdin. Calling prom_printf after closing stdout sounds like it could be bad. If I moved it down below all the prom_printf's, it would be after the quiesce call. Would that be acceptable (or even interesting as an experiment)? Does a close need a quiesce after it? Just try :-) quiesce is something that afaik only apple ever implemented anyways. It uses hooks inside their OF to shut down all drivers that do bus master (among other HW sanitization tasks). Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Freescale P2020/ 85xx PCIe: DMA low throughtput
Hi, I'm working on bring up for a new board based on Freescales p2020. I have a programmable FPGA as a PCIe device with a buffer I can write to and from. I want to test performence for the PCIe bus. I encountered a problem while doing a DMA between the FPGA DDR. The whole buffer moves to and from the device with out mismatches but with low throughtput. The thing is that the buffer divided to many transactions of byte size instead of transferring it in a burst. I must mention that even a buffer of word size, divided in to byte transactions by the DMA (the core can read a word so it seems like the DMA fault. I tried to change the latency timer, max latency, min latency and cache line in the configuration space of both sides of the pcie bus. It didn't help. Do you have an idea what can it be? Thanks, Natalie. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: Freescale P2020/ 85xx PCIe: DMA low throughtput
Hi, I'm working on bring up for a new board based on Freescales p2020. I have a programmable FPGA as a PCIe device with a buffer I can write to and from. I want to test performence for the PCIe bus. I encountered a problem while doing a DMA between the FPGA DDR. The whole buffer moves to and from the device with out mismatches but with low throughtput. The thing is that the buffer divided to many transactions of byte size instead of transferring it in a burst. I must mention that even a buffer of word size, divided in to byte transactions by the DMA (the core can read a word so it seems like the DMA fault. I tried to change the latency timer, max latency, min latency and cache line in the configuration space of both sides of the pcie bus. It didn't help. Do you have an idea what can it be? Thanks, Natalie. Assuming the P2020 has the usual 85xx-style DMA engine, you may have the Band Width Control cleared to 0. This 4-bit field (BWC) restricts the transfer size to 2^BWC bytes, for BWC=0,1,..0xa. 0xb-0xe are reserved. 0xf disables bandwidth sharing to allow uninterrupted transfers from each channel, so if you are using several channels one channel can completely lock out other channels. BWC=0x8 at reset (2^8 = 256 bytes). See the P2020 manual for more details. BWC is the field with mask 0x0f00 in the MR (Master Reset) register for the channel (0, 1, 2, 3), at offset 0x100, 0x180, 0x200, 0x280 relative to the base of the DMA controller. Clive ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
Benjamin Herrenschmidt writes: On Tue, 2010-10-19 at 22:23 -0500, pac...@kosh.dhis.org wrote: The diff fragment above applied inside prom_close_stdin, but there are some prom_printf calls after prom_close_stdin. Calling prom_printf after closing stdout sounds like it could be bad. If I moved it down below all the prom_printf's, it would be after the quiesce call. Would that be acceptable (or even interesting as an experiment)? Does a close need a quiesce after it? Just try :-) quiesce is something that afaik only apple ever implemented anyways. It uses hooks inside their OF to shut down all drivers that do bus master (among other HW sanitization tasks). I booted a version with a prom_close_stdout after the last prom_debug. It didn't have any effect. That 1000Hz clock was still ticking. -- Alan Curry ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [QUESTION] MPC8343 'internal only' DMA support
On Tue, Oct 19, 2010 at 3:15 AM, KRONSTORFER Horst horst.kronstor...@frequentis.com wrote: i assume the mpc8343 dma controllers ability to do internally controlled operations (csb/csb) is _not_ affected by deactivating externally controlled operations via pinmultiplexing in sicrl. am I correct? Hmmm... maybe. In general, if you want an external master for the DMA controller, I think you need to enable that via various registers. So if you don't enable external master, you won't have one. Does that answer your question? -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
On Wed, 2010-10-20 at 13:33 -0500, pac...@kosh.dhis.org wrote: Just try :-) quiesce is something that afaik only apple ever implemented anyways. It uses hooks inside their OF to shut down all drivers that do bus master (among other HW sanitization tasks). I booted a version with a prom_close_stdout after the last prom_debug. It didn't have any effect. That 1000Hz clock was still ticking. Ok so you'll have to make up a workaround in prom_init that looks for OHCI's in the device-tree and disable them. Check if the OHCI node has some existing f-code words you can use for that with dev /path-to-ohci words in OF for example. If not, you may need to use the low level register accessors. Use OF client interface interpret to run forth code from C. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[patch 1/1] powerpc: enable ARCH_DMA_ADDR_T_64BIT with ARCH_PHYS_ADDR_T_64BIT
From: FUJITA Tomonori fujita.tomon...@lab.ntt.co.jp Signed-off-by: FUJITA Tomonori fujita.tomon...@lab.ntt.co.jp Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Andrew Morton a...@linux-foundation.org --- arch/powerpc/Kconfig |3 +++ 1 file changed, 3 insertions(+) diff -puN arch/powerpc/Kconfig~powerpc-enable-arch_dma_addr_t_64bit-with-arch_phys_addr_t_64bit arch/powerpc/Kconfig --- a/arch/powerpc/Kconfig~powerpc-enable-arch_dma_addr_t_64bit-with-arch_phys_addr_t_64bit +++ a/arch/powerpc/Kconfig @@ -16,6 +16,9 @@ config WORD_SIZE config ARCH_PHYS_ADDR_T_64BIT def_bool PPC64 || PHYS_64BIT +config ARCH_DMA_ADDR_T_64BIT + def_bool ARCH_PHYS_ADDR_T_64BIT + config MMU bool default y _ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V5 0/9] *** Add Synopsys DesignWare HS USB OTG driver ***
This patch series add Synopsys DesignWare HS USB OTG driver support. PATCH V5 has a new license header from Synopsys and APM Previous versions: 1. Addressed comment from Wolfgang Denk to sync with git://git.denx.de/linux-2.6-denx.git. 2. Added bug fixes and features from Stefan Roese and Chuck Meade. 3. Removed dts file from this pathch per Sergei Shtylyov suggestion. We'll submit a separate patch to PowerPC tree. 4. Modified driver to use generic USB OTG enumeration state. 5. Move Makefiles to the last patch per David Daney suggestion. Fushen Chen (9): Add Synopsys DesignWare HS USB OTG Control and Status Register (CSR). Add Synopsys DesignWare HS USB OTG driver framework. Add Synopsys DesignWare HS USB OTG Core Interface Layer (CIL). Add Synopsys DesignWare HS USB OTG HCD function. Add Synopsys DesignWare HS USB OTG HCD interrupt function. Add Synopsys DesignWare HS USB OTG HCD queue function. Add Synopsys DesignWare HS USB OTG PCD function. Add Synopsys DesignWare HS USB OTG PCD interrupt function. Add Synopsys DesignWare HS USB OTG driver kernel configuration and Makefile. drivers/Makefile|1 + drivers/usb/Kconfig |2 + drivers/usb/dwc_otg/Kconfig | 99 + drivers/usb/dwc_otg/Makefile| 19 + drivers/usb/dwc_otg/dwc_otg_apmppc.c| 394 drivers/usb/dwc_otg/dwc_otg_cil.c | 892 + drivers/usb/dwc_otg/dwc_otg_cil.h | 1181 +++ drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 618 ++ drivers/usb/dwc_otg/dwc_otg_driver.h| 78 + drivers/usb/dwc_otg/dwc_otg_hcd.c | 2400 +++ drivers/usb/dwc_otg/dwc_otg_hcd.h | 413 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1465 ++ drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 +++ drivers/usb/dwc_otg/dwc_otg_param.c | 730 +++ drivers/usb/dwc_otg/dwc_otg_pcd.c | 1733 drivers/usb/dwc_otg/dwc_otg_pcd.h | 137 ++ drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 2262 + drivers/usb/dwc_otg/dwc_otg_regs.h | 3269 +++ 18 files changed, 16390 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc_otg/Kconfig create mode 100644 drivers/usb/dwc_otg/Makefile create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h -- 1.7.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V5 9/9] Add Synopsys DesignWare HS USB OTG driver kernel configuration and Makefile.
Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc_otg/Kconfig | 99 ++ drivers/usb/dwc_otg/Makefile | 19 4 files changed, 121 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc_otg/Kconfig create mode 100644 drivers/usb/dwc_otg/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index a2aea53..36cb201 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc_otg/ obj-$(CONFIG_PCI) += usb/ obj-$(CONFIG_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SERIO)+= input/serio/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 4aa00e6..bbb8b2c 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -114,6 +114,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc_otg/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 000..174141d --- /dev/null +++ b/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,99 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + depends on 405EZ || 405EX || 460EX + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode if 405EX || 460EX + +config DWC_OTG_MODE + bool DWC OTG Mode if 405EX || 460EX + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode if 405EX || 460EX + +config DWC_DMA_MODE + bool DWC DMA Mode if 405EX || (460EX \ + (!USB_EHCI_HCD || !USB_OHCI_HCD)) + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register if 405EX || 460EX + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian if 405EZ + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size if 405EZ || 405EX || 460EX + default n if 460EX || 405EX + default y if 405EZ + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile new file mode 100644 index 000..31dd5e8 --- /dev/null +++ b/drivers/usb/dwc_otg/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc_otg.o + +dwc_otg-objs := dwc_otg_cil.o dwc_otg_cil_intr.o dwc_otg_param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc_otg-objs += dwc_otg_apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o \ + dwc_otg_hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o +endif -- 1.7.3
[PATCH V5 6/9] Add Synopsys DesignWare HS USB OTG HCD queue function.
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 +++
1 files changed, 697 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 000..b1d67fe
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,697 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include dwc_otg_hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ union hprt0_data hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type == USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+ qh-sched_frame = dwc_frame_num_inc(hcd-frame_number,
+ SCHEDULE_SLOP);
+
[PATCH V5 2/9] Add Synopsys DesignWare HS USB OTG driver framework.
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 394 ++
drivers/usb/dwc_otg/dwc_otg_driver.h | 78
drivers/usb/dwc_otg/dwc_otg_param.c | 730 ++
3 files changed, 1202 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c
diff --git a/drivers/usb/dwc_otg/dwc_otg_apmppc.c
b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
new file mode 100644
index 000..a5c75c4
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
@@ -0,0 +1,394 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include dwc_otg_driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval = IRQ_NONE;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ union hprt0_data hprt0 = {.d32 = 0};
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0.b.prtpwr = 0;
+ dwc_write_reg32(dwc_dev-core_if-host_if-hprt0,
+ hprt0.d32);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+
[PATCH V5 5/9] Add Synopsys DesignWare HS USB OTG HCD interrupt function.
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1465
1 files changed, 1465 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 000..c4c8e10
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1465 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include dwc_otg_hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ union hfnum_data hfnum;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ union gintsts_data gintsts = {.d32 = 0};
+
+ hfnum.d32 =
+ dwc_read_reg32(hcd-core_if-host_if-host_global_regs-hfnum);
+
+ hcd-frame_number = hfnum.b.frnum;
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts.b.sofintr = 1;
+ dwc_write_reg32(gintsts_reg(hcd), gintsts.d32);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ union host_grxsts_data grxsts;
+ struct dwc_hc *hc = NULL;
+
+ grxsts.d32 = dwc_read_reg32(hcd-core_if-core_global_regs-grxstsp);
+ hc = hcd-hc_ptr_array[grxsts.b.chnum];
+
+ /* Packet Status */
+ switch (grxsts.b.pktsts) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if (grxsts.b.bcnt 0) {
+
[PATCH V5 7/9] Add Synopsys DesignWare HS USB OTG PCD function.
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_pcd.c | 1733 +
drivers/usb/dwc_otg/dwc_otg_pcd.h | 137 +++
2 files changed, 1870 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h
diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c
b/drivers/usb/dwc_otg/dwc_otg_pcd.c
new file mode 100644
index 000..9e226d7
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
@@ -0,0 +1,1733 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include dwc_otg_pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (core_if-hwcfg2.b.hs_phy_type == 2
+ core_if-hwcfg2.b.fs_phy_type == 1
+ core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (core_if-hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ core_if-hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ core_if-hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+
[PATCH V5 0/9] Add Synopsys DesignWare HS USB OTG driver
This patch series add Synopsys DesignWare HS USB OTG driver support. PATCH V5 has a new license header from Synopsys and APM Previous versions: 1. Addressed comment from Wolfgang Denk to sync with git://git.denx.de/linux-2.6-denx.git. 2. Added bug fixes and features from Stefan Roese and Chuck Meade. 3. Removed dts file from this pathch per Sergei Shtylyov suggestion. We'll submit a separate patch to PowerPC tree. 4. Modified driver to use generic USB OTG enumeration state. 5. Move Makefiles to the last patch per David Daney suggestion. Fushen Chen (9): Add Synopsys DesignWare HS USB OTG Control and Status Register (CSR). Add Synopsys DesignWare HS USB OTG driver framework. Add Synopsys DesignWare HS USB OTG Core Interface Layer (CIL). Add Synopsys DesignWare HS USB OTG HCD function. Add Synopsys DesignWare HS USB OTG HCD interrupt function. Add Synopsys DesignWare HS USB OTG HCD queue function. Add Synopsys DesignWare HS USB OTG PCD function. Add Synopsys DesignWare HS USB OTG PCD interrupt function. Add Synopsys DesignWare HS USB OTG driver kernel configuration and Makefile. drivers/Makefile|1 + drivers/usb/Kconfig |2 + drivers/usb/dwc_otg/Kconfig | 99 + drivers/usb/dwc_otg/Makefile| 19 + drivers/usb/dwc_otg/dwc_otg_apmppc.c| 394 drivers/usb/dwc_otg/dwc_otg_cil.c | 892 + drivers/usb/dwc_otg/dwc_otg_cil.h | 1181 +++ drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 618 ++ drivers/usb/dwc_otg/dwc_otg_driver.h| 78 + drivers/usb/dwc_otg/dwc_otg_hcd.c | 2400 +++ drivers/usb/dwc_otg/dwc_otg_hcd.h | 413 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1465 ++ drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 +++ drivers/usb/dwc_otg/dwc_otg_param.c | 730 +++ drivers/usb/dwc_otg/dwc_otg_pcd.c | 1733 drivers/usb/dwc_otg/dwc_otg_pcd.h | 137 ++ drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 2262 + drivers/usb/dwc_otg/dwc_otg_regs.h | 3269 +++ 18 files changed, 16390 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc_otg/Kconfig create mode 100644 drivers/usb/dwc_otg/Makefile create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h -- 1.7.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V5 0/9] Add Synopsys DesignWare HS USB OTG driver
On Wed, Oct 20, 2010 at 06:06:34PM -0700, Fushen Chen wrote: This patch series add Synopsys DesignWare HS USB OTG driver support. Unfortunatly this is right at the start of the merge window for me, which means it is past the window for anything new to go into .37. Can you resend this after .37-rc1 comes out and I can review it at that point in time? thanks, greg k-h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
NFS boot problems
Anybody else seeing this with 2.6.36? [ 431.260895] Unable to handle kernel paging request for data at address 0x24002082 [ 431.268407] Faulting instruction address: 0xc000f6c0 [ 431.273321] Oops: Kernel access of bad area, sig: 11 [#1] [ 431.278670] Warp [ 431.280494] last sysfs file: [ 431.283447] Modules linked in: [ 431.286486] NIP: c000f6c0 LR: c02d2338 CTR: [ 431.291436] REGS: cf831ea0 TRAP: 0300 Not tainted (2.6.36-pika+) [ 431.297680] MSR: 00029000 EE,ME,CE CR: 24084048 XER: [ 431.303758] DEAR: 24002082, ESR: [ 431.307753] TASK = cf82c000[1] 'swapper' THREAD: cf83 [ 431.312958] GPR00: cf831f50 cf82c000 24002082 363a2f74 24002081 cf81f128 0120 [ 431.321291] GPR08: 00029000 c03e cf8001a0 c03e1f30 15e6a17f 0ffa9700 007fff97 [ 431.329624] GPR16: 00400450 0080 007fff00 0ffa9d3c c020 0001 [ 431.337957] GPR24: c03f c03bcd8c c03e2390 c03e1ef4 c03e1ee8 c03e2390 [ 431.346487] NIP [c000f6c0] strcmp+0x8/0x24 [ 431.350558] LR [c02d2338] svc_reg_xprt_class+0x50/0xd0 [ 431.355665] Call Trace: [ 431.358115] [cf831f50] [c00ecbd8] proc_create_data+0x6c/0xcc (unreliable) [ 431.364883] [cf831f70] [c02c6ce8] svc_init_xprt_sock+0x24/0x34 [ 431.370702] [cf831f80] [c03bce20] init_sunrpc+0x94/0xb0 [ 431.375899] [cf831f90] [c00015d8] do_one_initcall+0x15c/0x1a0 [ 431.381635] [cf831fd0] [c03a0874] kernel_init+0xd8/0x178 [ 431.386921] [cf831ff0] [c000c31c] kernel_thread+0x50/0x6c [ 431.392296] Instruction dump: [ 431.395248] 3884 8c050001 2c00 4082fff8 38a5 8c040001 2c00 9c050001 [ 431.402973] 4082fff4 4e800020 38a3 3884 8c650001 2c83 8c040001 7c601851 [ 431.411405] ---[ end trace 5e5d343531be722e ]--- It looks like both xcl-xcl_name and cl-xcl_name are bogus addresses. Cheers, Sean ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
