[PATCH V6 4/9] powerpc, ptrace: Enable vr_(get/set) for transactional memory
This patch enables the vr_get which gets the running value of all
the VMX registers and the vr_set which sets the running value of
of all the VMX registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/kernel/ptrace.c | 104 +--
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 2de3b2c..5398c6e 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -530,10 +530,35 @@ static int vr_active(struct task_struct *target,
return target-thread.used_vr ? regset-n : 0;
}
+/**
+ * vr_get - get VR registers
+ * @target:The target task.
+ * @regset:The user regset structure.
+ * @pos: The buffer position.
+ * @count: Number of bytes to copy.
+ * @kbuf: Kernel buffer to copy from.
+ * @ubuf: User buffer to copy into.
+ *
+ * When the transaction is active, 'transact_vr' holds the current running
+ * value of all the VMX registers and 'vr_state' holds the last checkpointed
+ * value of all the VMX registers for the current transaction to fall back
+ * on in case it aborts. When transaction is not active 'vr_state' holds
+ * the current running state of all the VMX registers. So this function which
+ * gets the current running values of all the VMX registers, needs to know
+ * whether any transaction is active or not. The userspace interface buffer
+ * layout is as follows.
+ *
+ * struct data {
+ * vector128 vr[32];
+ * vector128 vscr;
+ * vector128 vrsave;
+ * };
+ */
static int vr_get(struct task_struct *target, const struct user_regset *regset,
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
+ struct thread_vr_state *addr;
int ret;
flush_altivec_to_thread(target);
@@ -541,8 +566,19 @@ static int vr_get(struct task_struct *target, const struct
user_regset *regset,
BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
offsetof(struct thread_vr_state, vr[32]));
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ if (MSR_TM_ACTIVE(target-thread.regs-msr)) {
+ flush_fp_to_thread(target);
+ flush_tmregs_to_thread(target);
+ addr = target-thread.transact_vr;
+ } else {
+ addr = target-thread.vr_state;
+ }
+#else
+ addr = target-thread.vr_state;
+#endif
ret = user_regset_copyout(pos, count, kbuf, ubuf,
- target-thread.vr_state, 0,
+ addr, 0,
33 * sizeof(vector128));
if (!ret) {
/*
@@ -553,7 +589,16 @@ static int vr_get(struct task_struct *target, const struct
user_regset *regset,
u32 word;
} vrsave;
memset(vrsave, 0, sizeof(vrsave));
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ if (MSR_TM_ACTIVE(target-thread.regs-msr))
+ vrsave.word = target-thread.transact_vrsave;
+ else
+ vrsave.word = target-thread.vrsave;
+#else
vrsave.word = target-thread.vrsave;
+#endif
+
ret = user_regset_copyout(pos, count, kbuf, ubuf, vrsave,
33 * sizeof(vector128), -1);
}
@@ -561,10 +606,35 @@ static int vr_get(struct task_struct *target, const
struct user_regset *regset,
return ret;
}
+/**
+ * vr_set - set VR registers
+ * @target:The target task.
+ * @regset:The user regset structure.
+ * @pos: The buffer position.
+ * @count: Number of bytes to copy.
+ * @kbuf: Kernel buffer to copy into.
+ * @ubuf: User buffer to copy from.
+ *
+ * When the transaction is active, 'transact_vr' holds the current running
+ * value of all the VMX registers and 'vr_state' holds the last checkpointed
+ * value of all the VMX registers for the current transaction to fall back
+ * on in case it aborts. When transaction is not active 'vr_state' holds
+ * the current running state of all the VMX registers. So this function which
+ * sets the current running values of all the VMX registers, needs to know
+ * whether any transaction is active or not. The userspace interface buffer
+ * layout is as follows.
+ *
+ * struct data {
+ * vector128 vr[32];
+ * vector128 vscr;
+ * vector128 vrsave;
+ * };
+ */
static int vr_set(struct task_struct *target, const struct user_regset *regset,
unsigned int pos, unsigned int count,
const void *kbuf, const void __user *ubuf)
{
+ struct thread_vr_state *addr;
int ret;
flush_altivec_to_thread(target);
@@ -572,8 +642,19 @@ static int vr_set(struct task_struct *target, const struct
[PATCH V6 5/9] powerpc, ptrace: Enable support for transactional memory register sets
This patch enables get and set of transactional memory related register
sets through PTRACE_GETREGSET-PTRACE_SETREGSET interface by implementing
four new powerpc specific register sets i.e REGSET_TM_SPR, REGSET_TM_CGPR,
REGSET_TM_CFPR, REGSET_CVMX support corresponding to these following new
ELF core note types added previously in this regard.
(1) NT_PPC_TM_SPR
(2) NT_PPC_TM_CGPR
(3) NT_PPC_TM_CFPR
(4) NT_PPC_TM_CVMX
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 2 +
arch/powerpc/kernel/ptrace.c| 714 +++-
2 files changed, 701 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/elf.h
b/arch/powerpc/include/uapi/asm/elf.h
index 59dad11..fdc8e2f 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -91,6 +91,8 @@
#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
#define ELF_NFPREG 33 /* includes fpscr */
+#define ELF_NVMX 34 /* includes all vector registers */
+#define ELF_NTMSPRREG 7 /* includes TM sprs, org_msr, dscr, tar, ppr */
typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 5398c6e..fe22740 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -63,6 +63,11 @@ struct pt_regs_offset {
{.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
#define REG_OFFSET_END {.name = NULL, .offset = 0}
+/* Some common structure offsets */
+#define TSO(f) (offsetof(struct thread_struct, f))
+#define TVSO(f)(offsetof(struct thread_vr_state, f))
+#define TFSO(f)(offsetof(struct thread_fp_state, f))
+
static const struct pt_regs_offset regoffset_table[] = {
GPR_OFFSET_NAME(0),
GPR_OFFSET_NAME(1),
@@ -809,6 +814,579 @@ static int evr_set(struct task_struct *target, const
struct user_regset *regset,
}
#endif /* CONFIG_SPE */
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+/**
+ * tm_spr_active - get active number of registers in TM SPR
+ * @target:The target task.
+ * @regset:The user regset structure.
+ *
+ * This function checks the active number of available
+ * regisers in the transactional memory SPR category.
+ */
+static int tm_spr_active(struct task_struct *target,
+const struct user_regset *regset)
+{
+ if (!cpu_has_feature(CPU_FTR_TM))
+ return -ENODEV;
+
+ if (!MSR_TM_ACTIVE(target-thread.regs-msr))
+ return 0;
+
+ return regset-n;
+}
+
+/**
+ * tm_spr_get - get the TM related SPR registers
+ * @target:The target task.
+ * @regset:The user regset structure.
+ * @pos: The buffer position.
+ * @count: Number of bytes to copy.
+ * @kbuf: Kernel buffer to copy from.
+ * @ubuf: User buffer to copy into.
+ *
+ * This function gets transactional memory related SPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct {
+ * u64 tm_tfhar;
+ * u64 tm_texasr;
+ * u64 tm_tfiar;
+ * unsigned long tm_orig_msr;
+ * unsigned long tm_tar;
+ * unsigned long tm_ppr;
+ * unsigned long tm_dscr;
+ * };
+ */
+static int tm_spr_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user *ubuf)
+{
+ int ret;
+
+ /* Build tests */
+ BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
+ BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
+ BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(tm_orig_msr));
+ BUILD_BUG_ON(TSO(ckpt_regs) + sizeof(struct pt_regs) != TSO(tm_tar));
+ BUILD_BUG_ON(TSO(tm_tar) + sizeof(unsigned long) != TSO(tm_ppr));
+ BUILD_BUG_ON(TSO(tm_ppr) + sizeof(unsigned long) != TSO(tm_dscr));
+
+ if (!cpu_has_feature(CPU_FTR_TM))
+ return -ENODEV;
+
+ if (!MSR_TM_ACTIVE(target-thread.regs-msr))
+ return -ENODATA;
+
+ /* Flush the states */
+ flush_fp_to_thread(target);
+ flush_altivec_to_thread(target);
+ flush_tmregs_to_thread(target);
+
+ /* TFHAR register */
+ ret = user_regset_copyout(pos, count, kbuf, ubuf,
+ target-thread.tm_tfhar, 0, sizeof(u64));
+
+ /* TEXASR register */
+ if (!ret)
+ ret = user_regset_copyout(pos, count, kbuf, ubuf,
+ target-thread.tm_texasr, sizeof(u64),
+ 2 * sizeof(u64));
+
+ /* TFIAR register */
+ if (!ret)
+ ret = user_regset_copyout(pos, count, kbuf, ubuf,
+ target-thread.tm_tfiar,
+ 2
[PATCH V6 6/9] powerpc, ptrace: Enable support for miscellaneous debug registers
This patch enables get and set of miscellaneous debug registers through
ptrace PTRACE_GETREGSET-PTRACE_SETREGSET interface by implementing new
powerpc specific register set REGSET_MISC support corresponding to the
new ELF core note NT_PPC_MISC added previously in this regard.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 1 +
arch/powerpc/kernel/ptrace.c| 131
2 files changed, 132 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/elf.h
b/arch/powerpc/include/uapi/asm/elf.h
index fdc8e2f..a41bd98 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -93,6 +93,7 @@
#define ELF_NFPREG 33 /* includes fpscr */
#define ELF_NVMX 34 /* includes all vector registers */
#define ELF_NTMSPRREG 7 /* includes TM sprs, org_msr, dscr, tar, ppr */
+#define ELF_NMISCREG 3 /* includes dscr, tar, ppr */
typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index fe22740..eddf7df 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1388,6 +1388,122 @@ static int tm_cvmx_set(struct task_struct *target,
}
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+#ifdef CONFIG_PPC64
+/**
+ * get_misc_dbg() - get MISC debug registers
+ * @target:The target task.
+ * @regset:The user regset structure.
+ * @pos: The buffer position.
+ * @count: Number of bytes to copy.
+ * @kbuf: Kernel buffer to copy from.
+ * @ubuf: User buffer to copy into.
+ *
+ * This function gets various miscellaneous debug registers which includes
+ * DSCR, PPR and TAR. The userspace intarface buffer layout is as follows.
+ *
+ * struct {
+ * unsigned long dscr;
+ * unsigned long ppr;
+ * unsigned long tar;
+ * };
+ *
+ * The data element 'tar' in the structure will be valid only if the kernel
+ * has CONFIG_PPC_BOOK3S_64 config option enabled.
+ */
+static int get_misc_dbg(struct task_struct *target,
+ const struct user_regset *regset, unsigned int pos,
+ unsigned int count, void *kbuf, void __user *ubuf)
+{
+ int ret;
+
+ /* Build test */
+ BUILD_BUG_ON(TSO(dscr) + 2 * sizeof(unsigned long) != TSO(ppr));
+
+#ifdef CONFIG_PPC_BOOK3S_64
+ BUILD_BUG_ON(TSO(ppr) + sizeof(unsigned long) != TSO(tar));
+#endif
+
+ /* DSCR register */
+ ret = user_regset_copyout(pos, count, kbuf, ubuf,
+ target-thread.dscr, 0,
+ sizeof(unsigned long));
+
+ /* PPR register */
+ if (!ret)
+ ret = user_regset_copyout(pos, count, kbuf, ubuf,
+ target-thread.ppr,
+ sizeof(unsigned long),
+ 2 * sizeof(unsigned long));
+
+#ifdef CONFIG_PPC_BOOK3S_64
+ /* TAR register */
+ if (!ret)
+ ret = user_regset_copyout(pos, count, kbuf, ubuf,
+ target-thread.tar,
+ 2 * sizeof(unsigned long),
+ 3 * sizeof(unsigned long));
+#endif
+ return ret;
+}
+
+/**
+ * set_misc_dbg() - set MISC debug registers
+ * @target:The target task.
+ * @regset:The user regset structure.
+ * @pos: The buffer position.
+ * @count: Number of bytes to copy.
+ * @kbuf: Kernel buffer to copy into.
+ * @ubuf: User buffer to copy from.
+ *
+ * This function sets various miscellaneous debug registers which includes
+ * DSCR, PPR and TAR. The userspace intarface buffer layout is as follows.
+ *
+ * struct {
+ * unsigned long dscr;
+ * unsigned long ppr;
+ * unsigned long tar;
+ * };
+ *
+ * The data element 'tar' in the structure will be valid only if the kernel
+ * has CONFIG_PPC_BOOK3S_64 config option enabled.
+ */
+static int set_misc_dbg(struct task_struct *target,
+ const struct user_regset *regset, unsigned int pos,
+ unsigned int count, const void *kbuf,
+ const void __user *ubuf)
+{
+ int ret;
+
+ /* Build test */
+ BUILD_BUG_ON(TSO(dscr) + 2 * sizeof(unsigned long) != TSO(ppr));
+
+#ifdef CONFIG_PPC_BOOK3S_64
+ BUILD_BUG_ON(TSO(ppr) + sizeof(unsigned long) != TSO(tar));
+#endif
+
+ /* DSCR register */
+ ret = user_regset_copyin(pos, count, kbuf, ubuf,
+ target-thread.dscr, 0,
+ sizeof(unsigned long));
+
+ /* PPR register */
+ if (!ret)
+ ret = user_regset_copyin(pos, count, kbuf, ubuf,
+
[PATCH V6 7/9] selftests, powerpc: Add test case for TM related ptrace interface
This patch adds one more test case called 'tm-ptrace' targeting TM
related ptrace interface. This test creates one child process to
run some basic TM transactions and the parent process attaches the
child to do some ptrace probing using the recently added regset
interfaces. The parent process then compares the received values
against the expected values to verify whether it has passed the
given test or not.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
tools/testing/selftests/powerpc/tm/Makefile| 2 +-
tools/testing/selftests/powerpc/tm/tm-ptrace.c | 542 +
2 files changed, 543 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/powerpc/tm/tm-ptrace.c
diff --git a/tools/testing/selftests/powerpc/tm/Makefile
b/tools/testing/selftests/powerpc/tm/Makefile
index 2cede23..71d400a 100644
--- a/tools/testing/selftests/powerpc/tm/Makefile
+++ b/tools/testing/selftests/powerpc/tm/Makefile
@@ -1,4 +1,4 @@
-PROGS := tm-resched-dscr
+PROGS := tm-resched-dscr tm-ptrace
all: $(PROGS)
diff --git a/tools/testing/selftests/powerpc/tm/tm-ptrace.c
b/tools/testing/selftests/powerpc/tm/tm-ptrace.c
new file mode 100644
index 000..7a6c7d3
--- /dev/null
+++ b/tools/testing/selftests/powerpc/tm/tm-ptrace.c
@@ -0,0 +1,542 @@
+/*
+ * Test program for TM ptrace interface
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Copyright 2014 IBM Corporation
+ *
+ * Author: Anshuman Khandual khand...@linux.vnet.ibm.com
+ */
+#include inttypes.h
+#include unistd.h
+#include stdlib.h
+#include string.h
+#include malloc.h
+#include errno.h
+#include sys/ptrace.h
+#include sys/uio.h
+#include sys/types.h
+#include sys/wait.h
+#include sys/signal.h
+#include sys/user.h
+#include linux/elf.h
+#include linux/types.h
+
+#include utils.h
+
+#define TEST_PASS 0
+#define TEST_FAIL 1
+
+#define MAX_STR_LENGTH 100
+
+/* ELF core notes */
+#define NT_PPC_TM_SPR 0x103 /* PowerPC TM special registers */
+#define NT_PPC_TM_CGPR 0x104 /* PowerpC TM checkpointed GPR */
+#define NT_PPC_TM_CFPR 0x105 /* PowerPC TM checkpointed FPR */
+#define NT_PPC_TM_CVMX 0x106 /* PowerPC TM checkpointed VMX */
+#define NT_PPC_MISC0x107 /* PowerPC miscellaneous registers */
+
+/* TM instructions */
+#define TBEGIN .long 0x7C00051D ;
+#define TEND .long 0x7C00055D ;
+
+/* SPR number */
+#define SPRN_DSCR 3
+#define SPRN_TAR 815
+#define SPRN_PPR 896
+
+#define C_DSCR 10 /* TM checkpointed DSCR */
+#define C_TAR 20 /* TM checkpointed TAR */
+#define C_PPR 0x8 /* TM checkpointed PPR */
+
+#define DSCR 50 /* TM running DSCR */
+#define TAR60 /* TM running TAR */
+#define PPR0x4 /* TM running PPR */
+
+/* Values for GPR-FPR[0..31] */
+#define VAL0 0
+#define VAL1 1
+#define VAL2 2
+#define VAL3 3
+#define VAL4 4
+#define VAL5 5
+#define VAL6 6
+#define VAL7 7
+#define VAL8 8
+#define VAL9 9
+#define VAL10 10
+#define VAL11 11
+#define VAL12 12
+#define VAL13 13
+#define VAL14 14
+#define VAL15 15
+#define VAL_MAX16
+
+/* Standard data types */
+typedef unsigned int u32;
+typedef __vector128 vector128;
+
+/* NT_PPC_TM_SPR buffer layout */
+struct tm_spr_regs {
+ u64 tm_tfhar;
+ u64 tm_texasr;
+ u64 tm_tfiar;
+ u64 tm_orig_msr;
+ u64 tm_tar;
+ u64 tm_ppr;
+ u64 tm_dscr;
+};
+
+/*
+ * NT_PPC_TM_CGPR buffer layout
+ *
+ * Same as that of struct pt_regs
+ */
+
+/* NT_PPC_TM_CFPR buffer layout */
+struct tm_cfpr {
+ u64 fpr[32];
+ u64 fpscr;
+};
+
+/* NT_PPC_TM_CVMX buffer layout */
+struct tm_cvmx {
+ vector128 vr[32] __attribute__((aligned(16)));
+ vector128 vscr __attribute__((aligned(16)));
+ u32 vrsave;
+};
+
+/* NT_PPC_MISC buffer layout */
+struct misc_regs {
+ u64 dscr;
+ u64 ppr;
+ u64 tar;
+};
+
+/*
+ * do_tm_transaction
+ *
+ * This functions sets the values for TAR, DSCR, PPR, GPR[0..31],
+ * FPR[0..31] registers before starting the trasanction which will
+ * enable the kernel to save them as checkpointed values. Then it
+ * starts the transaction where it loads a different set of values
+ * into the same registers again thus enabling the kernel to save
+ * them off as running values for this transaction. Then the function
+ * gets stuck forcing the process to loop at one single instruction.
+ * The transaction never finishes, thus giving the parent process
+ * the opportunity to trace the running and checkpointed values of
+ * various registers.
+ */
+void do_tm_transaction(void)
+{
+ asm __volatile__(
+ /* TM checkpointed values
[PATCH V6 8/9] selftests, powerpc: Make GIT ignore all binaries related to TM
This patch includes all the TM test binaries into the .gitignore file listing in the same directory. This will make sure that GIT ignores all of them while displaying status. Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- tools/testing/selftests/powerpc/tm/.gitignore | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 tools/testing/selftests/powerpc/tm/.gitignore diff --git a/tools/testing/selftests/powerpc/tm/.gitignore b/tools/testing/selftests/powerpc/tm/.gitignore new file mode 100644 index 000..71f9f9d --- /dev/null +++ b/tools/testing/selftests/powerpc/tm/.gitignore @@ -0,0 +1,2 @@ +tm-ptrace +tm-resched-dscr -- 1.9.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 9/9] selftests: Make GIT ignore all binaries in powerpc test suite
This patch includes all of the powerpc test binaries into the .gitignore file listing in their respective directories. This will make sure that GIT ignores all of these test binaries while displaying status. Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- .../testing/selftests/powerpc/copyloops/.gitignore | 4 tools/testing/selftests/powerpc/mm/.gitignore | 1 + tools/testing/selftests/powerpc/pmu/.gitignore | 3 +++ tools/testing/selftests/powerpc/pmu/ebb/.gitignore | 22 ++ .../selftests/powerpc/primitives/.gitignore| 1 + 5 files changed, 31 insertions(+) create mode 100644 tools/testing/selftests/powerpc/copyloops/.gitignore create mode 100644 tools/testing/selftests/powerpc/mm/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/.gitignore create mode 100644 tools/testing/selftests/powerpc/primitives/.gitignore diff --git a/tools/testing/selftests/powerpc/copyloops/.gitignore b/tools/testing/selftests/powerpc/copyloops/.gitignore new file mode 100644 index 000..25a192f --- /dev/null +++ b/tools/testing/selftests/powerpc/copyloops/.gitignore @@ -0,0 +1,4 @@ +copyuser_64 +copyuser_power7 +memcpy_64 +memcpy_power7 diff --git a/tools/testing/selftests/powerpc/mm/.gitignore b/tools/testing/selftests/powerpc/mm/.gitignore new file mode 100644 index 000..156f4e8 --- /dev/null +++ b/tools/testing/selftests/powerpc/mm/.gitignore @@ -0,0 +1 @@ +hugetlb_vs_thp_test diff --git a/tools/testing/selftests/powerpc/pmu/.gitignore b/tools/testing/selftests/powerpc/pmu/.gitignore new file mode 100644 index 000..e748f33 --- /dev/null +++ b/tools/testing/selftests/powerpc/pmu/.gitignore @@ -0,0 +1,3 @@ +count_instructions +l3_bank_test +per_event_excludes diff --git a/tools/testing/selftests/powerpc/pmu/ebb/.gitignore b/tools/testing/selftests/powerpc/pmu/ebb/.gitignore new file mode 100644 index 000..42bddbe --- /dev/null +++ b/tools/testing/selftests/powerpc/pmu/ebb/.gitignore @@ -0,0 +1,22 @@ +reg_access_test +event_attributes_test +cycles_test +cycles_with_freeze_test +pmc56_overflow_test +ebb_vs_cpu_event_test +cpu_event_vs_ebb_test +cpu_event_pinned_vs_ebb_test +task_event_vs_ebb_test +task_event_pinned_vs_ebb_test +multi_ebb_procs_test +multi_counter_test +pmae_handling_test +close_clears_pmcc_test +instruction_count_test +fork_cleanup_test +ebb_on_child_test +ebb_on_willing_child_test +back_to_back_ebbs_test +lost_exception_test +no_handler_test +cycles_with_mmcr2_test diff --git a/tools/testing/selftests/powerpc/primitives/.gitignore b/tools/testing/selftests/powerpc/primitives/.gitignore new file mode 100644 index 000..4cc4e31 --- /dev/null +++ b/tools/testing/selftests/powerpc/primitives/.gitignore @@ -0,0 +1 @@ +load_unaligned_zeropad -- 1.9.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V3] powerpc, powernv: Add OPAL platform event driver
On 11/25/2014 06:51 PM, Anshuman Khandual wrote: This patch creates a new OPAL platform event character driver which will give userspace clients the access to these events and process them effectively. Following platforms events are currently supported with this platform driver. (1) Environmental and Power Warning (EPOW) (2) Delayed Power Off (DPO) The user interface for this driver is /dev/opal_event character device file where the user space clients can poll and read for new opal platform events. The expected sequence of events driven from user space should be like the following. (1) Open the character device file (2) Poll on the file for POLLIN event (3) When unblocked, must attempt to read PLAT_EVENT_MAX_SIZE size (4) Kernel driver will pass at most one opal_plat_event structure (5) Poll again for more new events The driver registers for OPAL messages notifications corresponding to individual OPAL events. When any of those event messages arrive in the kernel, the callbacks are called to process them which in turn unblocks the polling thread on the character device file. The driver also registers a timer function which will be called after a threshold amount of time to shutdown the system. The user space client receives the timeout value for all individual OPAL platform events and hence must prepare the system and eventually shutdown. In case the user client does not shutdown the system, the timer function will be called after the threshold and shutdown the system explicitly. Reviewed-by: Neelesh Gupta neele...@linux.vnet.ibm.com Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- Changes in V3: - Rebased the patch against the mainline Changes in V2: - Changed the function fetch_dpo_timeout - Export opal_platform_events.h for user space consumption - Posted here https://patchwork.ozlabs.org/patch/396725/ Original V1: - Original patch - Posted here http://patchwork.ozlabs.org/patch/394340/ Hey Michael, Do you have any updates on this patch yet ? Thanks ! ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 1/9] elf: Add new powerpc specifc core note sections
This patch adds four new ELF core note sections for powerpc
transactional memory and one new ELF core note section for
powerpc general miscellaneous debug registers. These addition
of new ELF core note sections extends the existing ELF ABI
without affecting it in any manner.
Acked-by: Andrew Morton a...@linux-foundation.org
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
include/uapi/linux/elf.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ea9bf25..2260fc0 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -379,6 +379,11 @@ typedef struct elf64_shdr {
#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
+#define NT_PPC_TM_SPR 0x103 /* PowerPC TM special registers */
+#define NT_PPC_TM_CGPR 0x104 /* PowerpC TM checkpointed GPR */
+#define NT_PPC_TM_CFPR 0x105 /* PowerPC TM checkpointed FPR */
+#define NT_PPC_TM_CVMX 0x106 /* PowerPC TM checkpointed VMX */
+#define NT_PPC_MISC0x107 /* PowerPC miscellaneous registers */
#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */
#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */
--
1.9.3
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Re: powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument.
On 11/29/2014 04:08 AM, Michael Ellerman wrote:
On Tue, 2014-23-09 at 03:53:54 UTC, Mahesh Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
The flush_tlb hook in cpu_spec was introduced as a generic function hook
to invalidate TLBs. But the current implementation of flush_tlb hook
takes IS (invalidation selector) as an argument which is architecture
dependent. Hence, It is not right to have a generic routine where caller
has to pass non-generic argument.
This patch fixes this and makes flush_tlb hook as high level API.
The old code used to call flush_tlb hook with IS=0 (single page) resulting
partial invalidation of TLBs which is not right. This fix now makes
sure that whole TLB is invalidated to be able to successfully recover from
TLB and ERAT errors.
Which old code? You mean the MCE code I think. That's a bug fix, so it should
be a separate patch.
Yes. MCE code. Since this patch re-factors the code that takes IS as
direct argument, having a separate fix patch does not make any sense and
would get overwritten by this patch anyway.
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index daa5af9..ae3e74f 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -100,7 +100,7 @@ struct cpu_spec {
/*
* Processor specific routine to flush tlbs.
*/
-void(*flush_tlb)(unsigned long inval_selector);
+void(*flush_tlb)(unsigned int action);
};
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index d765144..068ac8b 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -112,6 +112,11 @@
#define TLBIEL_INVAL_SET_SHIFT 12
#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
+#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
+
+/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
+#define FLUSH_TLB_ALL 0 /* invalidate all TLBs */
+#define FLUSH_TLB_LPID 1 /* invalidate TLBs for current
LPID */
Now that these are generic actions then they should go in cputable.h with the
flush hook.
Sure, I will move them.
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index 4673353..9c9b741 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -137,15 +137,11 @@ __init_HFSCR:
/*
* Clear the TLB using the specified IS form of tlbiel instruction
* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
- *
- * r3 = IS field
*/
__init_tlb_power7:
-li r3,0xc00/* IS field = 0b11 */
-_GLOBAL(__flush_tlb_power7)
li r6,128
mtctr r6
-mr r7,r3 /* IS field */
+li r7,0xc00/* IS field = 0b11 */
ptesync
2: tlbiel r7
addir7,r7,0x1000
So the current version is:
_GLOBAL(__flush_tlb_power7)
li r6,128
mtctr r6
mr r7,r3 /* IS field */
ptesync
2:tlbiel r7
addir7,r7,0x1000
bdnz2b
ptesync
1:blr
ie. a loop preceeded and followed by ptesync.
Your new version is:
+static void _flush_tlb(uint32_t tlb_set, unsigned long inval_selector)
+{
+unsigned long i, rb;
+
+rb = inval_selector;
+for (i = 0; i tlb_set; i++) {
+asm volatile(tlbiel %0 : : r (rb));
+rb += 1 TLBIEL_INVAL_SET_SHIFT;
+}
+}
ie. no ptesyncs at all.
But there's no mention of that in the changelog. You need to explain why it is
OK to drop the ptesyncs.
You are right. I should put ptesyncs in _flush_tlb(). Will make this
change in v2. Thanks for catching this.
+/*
+ * Generic routine to flush TLB on power7. This routine is used as
+ * flush_tlb hook in cpu_spec for Power7 processor.
+ *
+ * action = FLUSH_TLB_ALL: Invalidate all TLBs.
+ * FLUSH_TLB_LPID: Invalidate TLB for current LPID.
+ */
+void __flush_tlb_power7(unsigned int action)
+{
+switch (action) {
+case FLUSH_TLB_ALL:
+_flush_tlb(POWER7_TLB_SETS, TLBIEL_INVAL_SET);
+break;
+case FLUSH_TLB_LPID:
+_flush_tlb(POWER7_TLB_SETS, TLBIEL_INVAL_SET_LPID);
+break;
+default:
+break;
+}
+}
+
+/*
+ * Generic routine to flush TLB on power8. This routine is used as
+ * flush_tlb hook in cpu_spec for power8 processor.
+ *
+ * action = FLUSH_TLB_ALL: Invalidate all TLBs.
+ * FLUSH_TLB_LPID: Invalidate TLB for current LPID.
+ */
+void __flush_tlb_power8(unsigned int action)
+{
+switch (action) {
+case FLUSH_TLB_ALL:
+_flush_tlb(POWER8_TLB_SETS, TLBIEL_INVAL_SET);
+break;
+case FLUSH_TLB_LPID:
+
Re: [PATCH 02/10] mm: Add p[te|md] protnone helpers for use by NUMA balancing
On Tue, Dec 02, 2014 at 09:38:39AM +1100, Benjamin Herrenschmidt wrote:
On Fri, 2014-11-21 at 13:57 +, Mel Gorman wrote:
#ifdef CONFIG_NUMA_BALANCING
+/*
+ * These work without NUMA balancing but the kernel does not care. See the
+ * comment in include/asm-generic/pgtable.h
+ */
+static inline int pte_protnone(pte_t pte)
+{
+ return (pte_val(pte)
+ (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
+}
I would add a comment clarifying that this only works for user pages,
ie, this accessor will always return true for a kernel page on ppc.
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/powerpc/include/asm/pgtable.h
index 490bd6d..7b889a3 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -41,7 +41,8 @@ static inline pgprot_t pte_pgprot(pte_t pte) { return
__pgprot(pte_val(pte) PA
#ifdef CONFIG_NUMA_BALANCING
/*
* These work without NUMA balancing but the kernel does not care. See the
- * comment in include/asm-generic/pgtable.h
+ * comment in include/asm-generic/pgtable.h . On powerpc, this will only
+ * work for user pages and always return true for kernel pages.
*/
static inline int pte_protnone(pte_t pte)
{
--
Mel Gorman
SUSE Labs
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Re: Disabled LocalPlus Controller (LPC) clock on MPC512x
On 26/11/2014 12:49, Alexander Popov wrote: Hello. Hi. My Freescale TWR-MPC5125 board instantly reboots if I touch any physical address on the LocalPlus Bus (LPB) for the first time when Linux has already booted. This effect is reproduced by using /dev/mem or loading a kernel module which works with any peripherals on LPB. It took me some time to find out that such crash is caused by clk_disable_unused() in drivers/clk/clk.c, which disables LocalPlus Controller (LPC) clock if I don't touch LPB addresses in the previous initcalls. So starting Linux with clk_ignore_unused bootparam or inserting dummy LPB reading to some initcall is a temporary fix. Is it correct to gate LPC clock? For me yes, because it's physically present on SoC and could not be muxed. If yes, how to avoid the mentioned crashes properly? There's a piece of code in arch/powerpc/platforms/512x/clock-commonclk.c which is doubtful for me: /* * pre-enable those internal clock items which never get * claimed by any peripheral driver, to not have the clock * subsystem disable them late at startup */ clk_prepare_enable(clks[MPC512x_CLK_DUMMY]); clk_prepare_enable(clks[MPC512x_CLK_E300]);/* PowerPC CPU */ clk_prepare_enable(clks[MPC512x_CLK_DDR]);/* DRAM */ clk_prepare_enable(clks[MPC512x_CLK_MEM]);/* SRAM */ clk_prepare_enable(clks[MPC512x_CLK_IPS]);/* SoC periph */ clk_prepare_enable(clks[MPC512x_CLK_LPC]);/* boot media */ Does it mean that these clocks should be registered with CLK_IGNORE_UNUSED flag? Yes, in my opinion this groups of clocks may be considered as always on, but I don't think that MPC512x_CLK_LPC is an internal clock and then It could be enable if really used only. In detail: - may be good to enable MPC512x_CLK_LPC only when localbus is enabled by the dts - if enabled, MPC512x_CLK_LPC have to setup with CLK_IGNORE_UNUSED flag because never get claimed by any driver. I put in CC Gerhard Sittig also beacuse it might be interesting to know his point of view as the author of mpc512x common clock driver. Regards, Matteo Thanks a lot. Best regards, Alexander ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] Documentation: bindings: net: DPAA corenet binding document
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, December 02, 2014 6:40 AM
On Fri, 2014-11-28 at 12:10 +0200, Madalin Bucur wrote:
Add the device tree binding document for the DPAA corenet node
and DPAA Ethernet nodes.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
Documentation/devicetree/bindings/net/fsl-dpaa.txt | 31
++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/fsl-dpaa.txt
diff --git a/Documentation/devicetree/bindings/net/fsl-dpaa.txt
b/Documentation/devicetree/bindings/net/fsl-dpaa.txt
new file mode 100644
index 000..822c668
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/fsl-dpaa.txt
@@ -0,0 +1,31 @@
+*DPAA corenet
+
+The corenet bus containing all DPAA Ethernet nodes.
What does this have to do with corenet?
The corenet-generic platform code uses this compatible. Here are some excerpts
from the platform code found in SDK
arch/powerpc/platforms/85xx/corenet_generic.c
...
* Corenet based SoC DS Setup
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
* Copyright 2009-2011 Freescale Semiconductor Inc.
...
static const struct of_device_id of_device_ids[] = {
{
.compatible = simple-bus
},
{
.compatible = fsl,dpaa
},
...
int __init corenet_gen_publish_devices(void)
{
return of_platform_bus_probe(NULL, of_device_ids, NULL);
}
...
+Required property
+ - compatible: string property. Must include fsl,dpaa. Can include
+ also fsl,SoC-dpaa.
No need for the SoC part. As we previously discussed, the only
purpose of this node is backwards compatibility with the U-Boot MAC
address fixup -- if U-Boot doesn't look for the SoC version, then
don't complicate things.
Though, I can't find where U-Boot references this node. Are you sure
it's not using the ethernet%d aliases like everything else, in which
case why do we need this node at all?
-Scott
The initial (Freescale SDK) binding document contained those compatibles,
not sure what the initial intent was for the SoC variants.
The fsl,dpaa node is of interest to the DPAA Ethernet because it is
the parent of the fsl,dpa-ethernet nodes.
Madalin
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Re: [RFC PATCH v1 1/1] powerpc/85xx: Add support for Emerson/Artesyn MVME2500.
Hi Scott,
On 2 December 2014 at 06:03, Scott Wood scottw...@freescale.com wrote:
[...]
I was referring to the final ranges entry:
+ 0x5 0x0 0x0 0xffdf 0x1000;
The localbus ranges should reflect what was programmed into BRn/ORn.
The smallest size that can be programmed into ORn is 32 KiB.
Sorry I'll use 0x8000 instead of 0x1000.
The pq3-gpio-0.dtsi defines an gpio controller in this way:
gpio-controller@f000 {
reg = 0xf000 0x100;
[...]
But MVME2500 board requires a slightly different definition:
reg = 0xfc00 0x100;
The GPIO CCSR registers on a P2010 don't change based on what board you
put it on. It looks like pq3-gpio-0.dtsi is just wrong, for all chips
that use it. It should be fixed there.
I have to admit that I'm not using GPIO at the moment so a typo into
board's manufacturer manual is more probable.
Better still would be if we could have address map tweaks be kconfig
fragments that get mixed in by the user, with merge_config.sh.
Personally I would prefer see something more simple like this:
%_defconfig: scripts/kconfig/conf
# Grab the platform generic config file (for a SoC family)
$(Q)$ --defconfig=arch/$(SRCARCH)/configs/mpc$(shell dirname
$@)_defconfig Kconfig
What is the dirname here trying to do?
Extract string 85xx from make 85xx/mvme2500_defconfig command.
So the above mentioned Makefile snip grabs
arch/powerpc/configs/mpc85xx_defconfig and applies (using
merge_config.sh) options present in
arch/powerpc/configs/85xx/mvme2500_defconfig.
It should reduces the size of the board specific defconfig without
using any other fragments and without change anything in user habits.
In my humble opinion that hardware is so rigid that flexibility given
by config fragments don't seem very useful.
Using this approach the mvme2500_defconfig file could looks like this:
CONFIG_MVME2500=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
# CONFIG_PCIEASPM is not set
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_BROADCOM_PHY=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_M25P80=y
CONFIG_HWMON=m
CONFIG_SENSORS_LM90=m
CONFIG_EDAC_MPC85XX=y
CONFIG_ADVANCED_OPTIONS=y
CONFIG_LOWMEM_SIZE_BOOL=y
CONFIG_LOWMEM_SIZE=0x4000
CONFIG_PAGE_OFFSET_BOOL=y
CONFIG_PAGE_OFFSET=0x8000
CONFIG_KERNEL_START_BOOL=y
CONFIG_TASK_SIZE_BOOL=y
CONFIG_TASK_SIZE=0x8000
CONFIG_STAGING=y
CONFIG_VME_BUS=y
CONFIG_VME_TSI148=y
CONFIG_VME_USER=y
I know it is a very stupid idea so feel free to ignore me on this point :)
I gues the point here is to avoid using highmem just for the last 256
MiB?
Yes. Can you suggest me a better solution, please?
Not if the performance benefit from getting rid of highmem is worth
carrying this around... But it would still be good if the board support
were build in the standard defconfig as well. It's unlikely to get much
build coverage (by people who don't use this board) in a board-specific
defconfig.
Ok I changed mpc85xx_defconfig and it works with few addiction. So we
have two possibilities: use mpc85xx_defconfig (but without VME_USER
and Highmem tweak) or add mvme2500_defconfig: Which do you prefer? I
would prefer the mvme2500_defconfig but I think that my vote doesn't
count (rightly).
What do you think about move board setup code from
platform/85xx/mvme2500.c to platform/platforms/85xx/mpc85xx_ds.c?
Thank you very much.
Ciao,
Alessio
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Re: [PATCH V6 9/9] selftests: Make GIT ignore all binaries in powerpc test suite
On 12/02/2014 12:56 AM, Anshuman Khandual wrote: This patch includes all of the powerpc test binaries into the .gitignore file listing in their respective directories. This will make sure that GIT ignores all of these test binaries while displaying status. Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- .../testing/selftests/powerpc/copyloops/.gitignore | 4 tools/testing/selftests/powerpc/mm/.gitignore | 1 + tools/testing/selftests/powerpc/pmu/.gitignore | 3 +++ tools/testing/selftests/powerpc/pmu/ebb/.gitignore | 22 ++ .../selftests/powerpc/primitives/.gitignore| 1 + 5 files changed, 31 insertions(+) create mode 100644 tools/testing/selftests/powerpc/copyloops/.gitignore create mode 100644 tools/testing/selftests/powerpc/mm/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/.gitignore create mode 100644 tools/testing/selftests/powerpc/primitives/.gitignore Creating a single .gitignore at tools/testing/selftests/powerpc will make this simpler without having to add one .gitignore for each directory underneath. Thanks for taking on the task to add .gitignore for all powerpc binaries. -- Shuah -- Shuah Khan Sr. Linux Kernel Developer Samsung Research America (Silicon Valley) shua...@osg.samsung.com | (970) 217-8978 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 03/10] mm: Convert p[te|md]_numa users to p[te|md]_protnone_numa
On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote: Now, hash_preload can possibly insert an hpte in hash page table even if the access is not allowed by the pte permissions. But i guess even that is ok. because we will fault again, end-up calling hash_page_mm where we handle that part correctly. I think we need a test case... Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 03/10] mm: Convert p[te|md]_numa users to p[te|md]_protnone_numa
On Tue, 2014-12-02 at 13:01 +0530, Aneesh Kumar K.V wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Fri, 2014-11-21 at 13:57 +, Mel Gorman wrote:
void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
pte_t pte)
{
-#ifdef CONFIG_DEBUG_VM
- WARN_ON(pte_val(*ptep) _PAGE_PRESENT);
-#endif
+ /*
+* When handling numa faults, we already have the pte marked
+* _PAGE_PRESENT, but we can be sure that it is not in hpte.
+* Hence we can use set_pte_at for them.
+*/
+ VM_WARN_ON((pte_val(*ptep) (_PAGE_PRESENT | _PAGE_USER)) ==
+ (_PAGE_PRESENT | _PAGE_USER));
+
His is that going to fare with set_pte_at() called for kernel pages ?
Yes, we won't capture those errors now. But is there any other debug
check i could use to capture the wrong usage of set_pte_at ?
Actually the above is fine, for some reason I mis-read the test as
blowing on kernel pages, it doesn't.
We probably do need to make sure however that protnone isn't used for
kernel pages.
Cheers,
Ben.
-aneesh
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[PATCH] powerpc: add little endian flag to syscall_get_arch()
Since both ppc and ppc64 have LE variants which are now reported by uname, add
that flag (__AUDIT_ARCH_LE) to syscall_get_arch() and add AUDIT_ARCH_PPC*LE
variants.
Without this, perf trace and auditctl fail.
Mainline kernel reports ppc64le (per a058801) but there is no matching
AUDIT_ARCH_PPC64LE.
See:
https://www.redhat.com/archives/linux-audit/2014-August/msg00082.html
https://www.redhat.com/archives/linux-audit/2014-December/msg4.html
Signed-off-by: Richard Guy Briggs r...@redhat.com
---
arch/powerpc/include/asm/syscall.h |6 +-
include/uapi/linux/audit.h |2 ++
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/syscall.h
b/arch/powerpc/include/asm/syscall.h
index 6fa2708..a58acab 100644
--- a/arch/powerpc/include/asm/syscall.h
+++ b/arch/powerpc/include/asm/syscall.h
@@ -90,6 +90,10 @@ static inline void syscall_set_arguments(struct task_struct
*task,
static inline int syscall_get_arch(void)
{
- return is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
+ int arch = is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
+#ifdef __LITTLE_ENDIAN__
+ arch |= __AUDIT_ARCH_LE
+#endif
+ return arch;
}
#endif /* _ASM_SYSCALL_H */
diff --git a/include/uapi/linux/audit.h b/include/uapi/linux/audit.h
index 4d100c8..fe29a99 100644
--- a/include/uapi/linux/audit.h
+++ b/include/uapi/linux/audit.h
@@ -364,7 +364,9 @@ enum {
#define AUDIT_ARCH_PARISC (EM_PARISC)
#define AUDIT_ARCH_PARISC64(EM_PARISC|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_PPC (EM_PPC)
+#define AUDIT_ARCH_PPCLE (EM_PPC|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_PPC64 (EM_PPC64|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_PPC64LE (EM_PPC64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_S390(EM_S390)
#define AUDIT_ARCH_S390X (EM_S390|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_SH (EM_SH)
--
1.7.1
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[PATCH] ALSA: i2sbus: Deletion of unnecessary checks before the function call release_and_free_resource
From: Markus Elfring elfr...@users.sourceforge.net Date: Tue, 2 Dec 2014 22:50:24 +0100 The release_and_free_resource() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring elfr...@users.sourceforge.net --- sound/aoa/soundbus/i2sbus/core.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/sound/aoa/soundbus/i2sbus/core.c b/sound/aoa/soundbus/i2sbus/core.c index a80d5ea..4e2b4fb 100644 --- a/sound/aoa/soundbus/i2sbus/core.c +++ b/sound/aoa/soundbus/i2sbus/core.c @@ -79,8 +79,7 @@ static void i2sbus_release_dev(struct device *dev) if (i2sdev-out.dbdma) iounmap(i2sdev-out.dbdma); if (i2sdev-in.dbdma) iounmap(i2sdev-in.dbdma); for (i = aoa_resource_i2smmio; i = aoa_resource_rxdbdma; i++) - if (i2sdev-allocated_resource[i]) - release_and_free_resource(i2sdev-allocated_resource[i]); + release_and_free_resource(i2sdev-allocated_resource[i]); free_dbdma_descriptor_ring(i2sdev, i2sdev-out.dbdma_ring); free_dbdma_descriptor_ring(i2sdev, i2sdev-in.dbdma_ring); for (i = aoa_resource_i2smmio; i = aoa_resource_rxdbdma; i++) @@ -323,8 +322,7 @@ static int i2sbus_add_dev(struct macio_dev *macio, if (dev-out.dbdma) iounmap(dev-out.dbdma); if (dev-in.dbdma) iounmap(dev-in.dbdma); for (i=0;i3;i++) - if (dev-allocated_resource[i]) - release_and_free_resource(dev-allocated_resource[i]); + release_and_free_resource(dev-allocated_resource[i]); mutex_destroy(dev-lock); kfree(dev); return 0; -- 2.1.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: add little endian flag to syscall_get_arch()
On 12/02/2014 01:27 PM, Richard Guy Briggs wrote:
Since both ppc and ppc64 have LE variants which are now reported by uname, add
that flag (__AUDIT_ARCH_LE) to syscall_get_arch() and add AUDIT_ARCH_PPC*LE
variants.
Without this, perf trace and auditctl fail.
Mainline kernel reports ppc64le (per a058801) but there is no matching
AUDIT_ARCH_PPC64LE.
See:
https://www.redhat.com/archives/linux-audit/2014-August/msg00082.html
https://www.redhat.com/archives/linux-audit/2014-December/msg4.html
Signed-off-by: Richard Guy Briggs r...@redhat.com
---
arch/powerpc/include/asm/syscall.h |6 +-
include/uapi/linux/audit.h |2 ++
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/syscall.h
b/arch/powerpc/include/asm/syscall.h
index 6fa2708..a58acab 100644
--- a/arch/powerpc/include/asm/syscall.h
+++ b/arch/powerpc/include/asm/syscall.h
@@ -90,6 +90,10 @@ static inline void syscall_set_arguments(struct
task_struct *task,
static inline int syscall_get_arch(void)
{
- return is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
+ int arch = is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
+#ifdef __LITTLE_ENDIAN__
+ arch |= __AUDIT_ARCH_LE
+#endif
+ return arch;
}
#endif /* _ASM_SYSCALL_H */
diff --git a/include/uapi/linux/audit.h b/include/uapi/linux/audit.h
index 4d100c8..fe29a99 100644
--- a/include/uapi/linux/audit.h
+++ b/include/uapi/linux/audit.h
@@ -364,7 +364,9 @@ enum {
#define AUDIT_ARCH_PARISC(EM_PARISC)
#define AUDIT_ARCH_PARISC64 (EM_PARISC|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_PPC (EM_PPC)
+#define AUDIT_ARCH_PPCLE (EM_PPC|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_PPC64 (EM_PPC64|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_PPC64LE (EM_PPC64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_S390 (EM_S390)
#define AUDIT_ARCH_S390X (EM_S390|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_SH(EM_SH)
IBM would know for certain but I wasn't aware there was a PPCLE (32bit compat).
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Re: [PATCH] powerpc: add little endian flag to syscall_get_arch()
On Tue, Dec 2, 2014 at 1:27 PM, Richard Guy Briggs r...@redhat.com wrote:
Since both ppc and ppc64 have LE variants which are now reported by uname, add
that flag (__AUDIT_ARCH_LE) to syscall_get_arch() and add AUDIT_ARCH_PPC*LE
variants.
Without this, perf trace and auditctl fail.
Mainline kernel reports ppc64le (per a058801) but there is no matching
AUDIT_ARCH_PPC64LE.
There's no seccomp filter support for powerpc, so there's no risk that
this breaks it.
--Andy
See:
https://www.redhat.com/archives/linux-audit/2014-August/msg00082.html
https://www.redhat.com/archives/linux-audit/2014-December/msg4.html
Signed-off-by: Richard Guy Briggs r...@redhat.com
---
arch/powerpc/include/asm/syscall.h |6 +-
include/uapi/linux/audit.h |2 ++
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/syscall.h
b/arch/powerpc/include/asm/syscall.h
index 6fa2708..a58acab 100644
--- a/arch/powerpc/include/asm/syscall.h
+++ b/arch/powerpc/include/asm/syscall.h
@@ -90,6 +90,10 @@ static inline void syscall_set_arguments(struct
task_struct *task,
static inline int syscall_get_arch(void)
{
- return is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
+ int arch = is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
+#ifdef __LITTLE_ENDIAN__
+ arch |= __AUDIT_ARCH_LE
+#endif
+ return arch;
}
#endif /* _ASM_SYSCALL_H */
diff --git a/include/uapi/linux/audit.h b/include/uapi/linux/audit.h
index 4d100c8..fe29a99 100644
--- a/include/uapi/linux/audit.h
+++ b/include/uapi/linux/audit.h
@@ -364,7 +364,9 @@ enum {
#define AUDIT_ARCH_PARISC (EM_PARISC)
#define AUDIT_ARCH_PARISC64(EM_PARISC|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_PPC (EM_PPC)
+#define AUDIT_ARCH_PPCLE (EM_PPC|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_PPC64 (EM_PPC64|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_PPC64LE (EM_PPC64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_S390(EM_S390)
#define AUDIT_ARCH_S390X (EM_S390|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_SH (EM_SH)
--
1.7.1
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Re: [RFC PATCH v1 1/1] powerpc/85xx: Add support for Emerson/Artesyn MVME2500.
On Tue, 2014-12-02 at 15:55 +0100, Alessio Igor Bogani wrote:
Hi Scott,
On 2 December 2014 at 06:03, Scott Wood scottw...@freescale.com wrote:
[...]
The pq3-gpio-0.dtsi defines an gpio controller in this way:
gpio-controller@f000 {
reg = 0xf000 0x100;
[...]
But MVME2500 board requires a slightly different definition:
reg = 0xfc00 0x100;
The GPIO CCSR registers on a P2010 don't change based on what board you
put it on. It looks like pq3-gpio-0.dtsi is just wrong, for all chips
that use it. It should be fixed there.
I have to admit that I'm not using GPIO at the moment so a typo into
board's manufacturer manual is more probable.
The various chip manuals also say that the registers start at offset
0xc00 in the gpio block. Testing suggests that the registers actually
repeat every 0x100 bytes within the 4K page, but it would be good to fix
the device tree to match the documented location.
Better still would be if we could have address map tweaks be kconfig
fragments that get mixed in by the user, with merge_config.sh.
Personally I would prefer see something more simple like this:
%_defconfig: scripts/kconfig/conf
# Grab the platform generic config file (for a SoC family)
$(Q)$ --defconfig=arch/$(SRCARCH)/configs/mpc$(shell dirname
$@)_defconfig Kconfig
What is the dirname here trying to do?
Extract string 85xx from make 85xx/mvme2500_defconfig command.
So the above mentioned Makefile snip grabs
arch/powerpc/configs/mpc85xx_defconfig and applies (using
merge_config.sh) options present in
arch/powerpc/configs/85xx/mvme2500_defconfig.
But mpc85xx_defconfig isn't a suitable base for all 85xx (SMP, corenet,
etc). Plus, hardcoding mpc in front of it in generic infrastructure
would not be appropriate (even on PPC you have the 40x and 44x
directories).
The right way to do this would be to have a metaconfig file that lists
the base config and a set of fragments to apply, which the user can use
like an ordinary defconfig.
It should reduces the size of the board specific defconfig without
using any other fragments and without change anything in user habits.
In my humble opinion that hardware is so rigid that flexibility given
by config fragments don't seem very useful.
Which hardware? The MVME2500? It looked like you were proposing a more
general solution. Note that many config options have nothing to do with
the hardware (filesystems, debug options, network protocols,
virtualization, etc).
In any case, we don't want a defconfig for every board. We want a small
set of defconfigs that provide wide build coverage and the ability to
run on a wide variety of boards. Nothing stops users or board vendors
from maintaining more targeted configs out of tree.
I gues the point here is to avoid using highmem just for the last 256
MiB?
Yes. Can you suggest me a better solution, please?
Not if the performance benefit from getting rid of highmem is worth
carrying this around... But it would still be good if the board support
were build in the standard defconfig as well. It's unlikely to get much
build coverage (by people who don't use this board) in a board-specific
defconfig.
Ok I changed mpc85xx_defconfig and it works with few addiction. So we
have two possibilities: use mpc85xx_defconfig (but without VME_USER
and Highmem tweak) or add mvme2500_defconfig: Which do you prefer? I
would prefer the mvme2500_defconfig but I think that my vote doesn't
count (rightly).
If it were just the highmem tweak I'd say that falls into the realm of
user config -- it's no different from any other board with 1 GiB of RAM.
I don't want to turn on staging drivers in the main defconfigs (unless
it's for something needed by most boards covered by the defconfig),
since it makes it easier for users to enable other staging drivers
without realizing it.
So, put everything but VME and the highmem tweak in mpc85xx_defconfig.
If you want, add an 85xx/mvme2500.config fragment that adds VME and the
highmem tweak (separate config fragments for each would be better, but
without a metaconfig mechanism it's less friendly to users who won't
know what the best starting point is for this board).
What do you think about move board setup code from
platform/85xx/mvme2500.c to platform/platforms/85xx/mpc85xx_ds.c?
It's not a DS board, but it'd be good to have a
platforms/85xx/mpc85xx_generic.c (similar to
platforms/85xx/corenet_generic.c) for platforms that don't need anything
special in the board file.
-Scott
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Re: [PATCH] Documentation: bindings: net: DPAA corenet binding document
On Tue, 2014-12-02 at 06:12 -0600, Bucur Madalin-Cristian-B32716 wrote: -Original Message- From: Wood Scott-B07421 Sent: Tuesday, December 02, 2014 6:40 AM On Fri, 2014-11-28 at 12:10 +0200, Madalin Bucur wrote: Add the device tree binding document for the DPAA corenet node and DPAA Ethernet nodes. Signed-off-by: Madalin Bucur madalin.bu...@freescale.com --- Documentation/devicetree/bindings/net/fsl-dpaa.txt | 31 ++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/fsl-dpaa.txt diff --git a/Documentation/devicetree/bindings/net/fsl-dpaa.txt b/Documentation/devicetree/bindings/net/fsl-dpaa.txt new file mode 100644 index 000..822c668 --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl-dpaa.txt @@ -0,0 +1,31 @@ +*DPAA corenet + +The corenet bus containing all DPAA Ethernet nodes. What does this have to do with corenet? The corenet-generic platform code uses this compatible. That doesn't make it a corenet bus. It's not a bus at all. +Required property + - compatible: string property. Must include fsl,dpaa. Can include + also fsl,SoC-dpaa. No need for the SoC part. As we previously discussed, the only purpose of this node is backwards compatibility with the U-Boot MAC address fixup -- if U-Boot doesn't look for the SoC version, then don't complicate things. Though, I can't find where U-Boot references this node. Are you sure it's not using the ethernet%d aliases like everything else, in which case why do we need this node at all? -Scott The initial (Freescale SDK) binding document contained those compatibles, not sure what the initial intent was for the SoC variants. The fsl,dpaa node is of interest to the DPAA Ethernet because it is the parent of the fsl,dpa-ethernet nodes. I'm not interested in what the SDK binding says, or what the SDK kernel does. I'm interested in whether there's a U-Boot compatibility issue, as was previously alleged. If there isn't, then there's no need for fsl,dpaa *or* fsl,dpa-ethernet. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc: Remove more traces of bootmem
On Thu, 2014-11-20 at 13:33 +1100, Tony Breeds wrote:
On Thu, Nov 20, 2014 at 11:07:38AM +1100, Michael Ellerman wrote:
--- a/arch/powerpc/lib/alloc.c
+++ b/arch/powerpc/lib/alloc.c
@@ -13,9 +13,7 @@ void * __init_refok zalloc_maybe_bootmem(size_t size,
gfp_t mask)
if (mem_init_done)
p = kzalloc(size, mask);
else {
- p = alloc_bootmem(size);
- if (p)
- memset(p, 0, size);
+ p = memblock_virt_alloc(size, 0);
}
You knew someone would ask but ...
Do you want to remove the {} form the else clause so that the style matches
the if()
Actually I was going to do a follow-up that just returns directly without p at
all, thanks for the reminder :)
cheers
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Re: [PATCH v3 1/4] powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA BMan
On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
+bman: bman@31a000 {
+ compatible = fsl,bman;
+ reg = 0x31a000 0x1000;
+ interrupts = 16 2 1 2;
+ fsl,bman-portals = bportals;
+ memory-region = bman_fbpr;
Shouldn't it be bportals?
And I don't see fsl,bman-portals in the binding...
-Scott
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Re: [PATCH v3 3/4] powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)
On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
diff --git a/arch/powerpc/boot/dts/t4240rdb.dts
b/arch/powerpc/boot/dts/t4240rdb.dts
index 53761d4..431bf4e 100644
--- a/arch/powerpc/boot/dts/t4240rdb.dts
+++ b/arch/powerpc/boot/dts/t4240rdb.dts
@@ -69,10 +69,27 @@
device_type = memory;
};
+ reserved-memory {
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ compatible = fsl,bman-fbpr;
+ alloc-ranges = 0 0 0x 0x;
+ size = 0 0x100;
+ alignment = 0 0x100;
+ };
+ };
Can't this be done at the SoC level rather than board level?
-Scott
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Re: [PATCH v2 0/3] fix a kernel panic on fsl corenet board when CONFIG_CLK_PPC_CORENET is enabled
If the current code panics as of commit da788acb2838, then the revert (but not the other patches) should go to stable as well. -Scott On Wed, 2014-11-26 at 21:30 -0600, Tang Yuantian-B29983 wrote: Hello Mike, Could you please apply this patch? This patch has been acked for a while. Thanks, Yuantian -Original Message- From: Linuxppc-dev [mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Scott Wood Sent: Friday, November 07, 2014 12:08 PM To: Kevin Hao Cc: Mike Turquette; Gerhard Sittig; Lu Jingchang-B35083; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v2 0/3] fix a kernel panic on fsl corenet board when CONFIG_CLK_PPC_CORENET is enabled On Sun, 2014-10-19 at 14:11 +0800, Kevin Hao wrote: Hi, I have done a boot test on p2014rdb and t4240qds boards. I don't have an access to mpc512x board, so only build test for that. v2: - Revert the commit da788acb2838 first. - Invoke of_clk_init() from a common place. v1 This tries to fix a kernel panic introduced by commit da788acb2838 (clk: ppc-corenet: Fix Section mismatch warning). Kevin Hao (3): Revert clk: ppc-corenet: Fix Section mismatch warning powerpc: call of_clk_init() from time_init() clk: ppc-corenet: fix section mismatch warning arch/powerpc/kernel/time.c| 5 arch/powerpc/platforms/512x/clock-commonclk.c | 11 --- drivers/clk/clk-ppc-corenet.c | 43 --- 3 files changed, 16 insertions(+), 43 deletions(-) Acked-by: Scott Wood scottw...@freescale.com Whose tree should this go through? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 0/6]: Make 24x7 and GPCI events available in sysfs
The current support for the 24x7 and GPCI counters in the kernel requires
users to specify the domain and offset of the event numerically, which is
obviously hard to use:
perf stat -C 0 -e \
'hv_24x7/domain=2,offset=0xd58,starting_index=0,lpar=0x/' \
sleep 1
This patchset exports the 24x7 and GPCI counters info in sysfs so users can
specify the events by name:
$ cd /sys/bus/event_source/devices/hv_24x7/events
$ cat HPM_CS_FROM_L4_LDATA__PHYS_CORE
domain=0x2,offset=0xd58,starting_index=$core,lpar=0x0
$ cat HPM_TLBIE__VCPU_HOME_CHIP
domain=0x4,offset=0x358,starting_index=$vcpu,lpar=$sibling_guest_id
perf stat -C 0 -e \
'hv_24x7/HPM_CS_FROM_L4_LDATA__PHYS_CORE,starting_index=0'
sleep 1
This patchset adds the kernel support to export events in sysfs. A follow-on
patchset will add support to the perf tool to parse the event parameters like
'lpar=$sibling_guest_id' and display them via 'perf list'.
Changelog[v5]
- [Jiri Olsa, Peter Zijlstra] Use '$arg' notation rather than ?
to indicate event parameters.
- [Michael Ellerman] Separate the kernel and tool patches in the
patchset into different patchsets.
Changelog[v4]
- [Jiri Olsa Rebase to perf/core tree to fix small merge conflict.
Changelog[v3]
- [Jiri Olsa] Changed the event parameters are specified. If
event file specifes 'param=val' make the usage 'param=123'
rather than 'val=123'. (patch 1,2/10)
- Shortened event names using PHYS and VCPU (patch 4/10)
- Print help message if invalid parameter is specified or required
parameter is missing.
- Moved 3 patches that are unrelated to parametrized events into
a separate patchset.
- Reordered patches so code changes come first.
Changelog[v2]
- [Joe Perches, David Laight] Use beNN_to_cpu() instead of guessing
the size from type.
- Use kmem_cache_free() to free page allocated with kmem_cache_alloc().
- Rebase to recent kernel
Cody P Schafer (6):
perf: provide sysfs_show for struct perf_pmu_events_attr
perf: add PMU_EVENT_ATTR_STRING() helper
powerpc/perf/hv-24x7: parse catalog and populate sysfs with events
powerpc/perf/{hv-gpci, hv-common}: generate requests with counters
annotated
powerpc/perf/hv-gpci: add the remaining gpci requests
powerpc/perf/hv-24x7: Document sysfs event description entries
.../testing/sysfs-bus-event_source-devices-hv_24x7 | 22 +
arch/powerpc/perf/hv-24x7-catalog.h| 25 +
arch/powerpc/perf/hv-24x7-domains.h| 28 +
arch/powerpc/perf/hv-24x7.c| 787 -
arch/powerpc/perf/hv-24x7.h| 12 +-
arch/powerpc/perf/hv-common.c | 10 +-
arch/powerpc/perf/hv-gpci-requests.h | 262 +++
arch/powerpc/perf/hv-gpci.c| 8 +
arch/powerpc/perf/hv-gpci.h| 37 +-
arch/powerpc/perf/req-gen/_begin.h | 13 +
arch/powerpc/perf/req-gen/_clear.h | 5 +
arch/powerpc/perf/req-gen/_end.h | 4 +
arch/powerpc/perf/req-gen/_request-begin.h | 15 +
arch/powerpc/perf/req-gen/_request-end.h | 8 +
arch/powerpc/perf/req-gen/perf.h | 155
include/linux/perf_event.h | 10 +
kernel/events/core.c | 8 +
17 files changed, 1365 insertions(+), 44 deletions(-)
create mode 100644 arch/powerpc/perf/hv-24x7-domains.h
create mode 100644 arch/powerpc/perf/hv-gpci-requests.h
create mode 100644 arch/powerpc/perf/req-gen/_begin.h
create mode 100644 arch/powerpc/perf/req-gen/_clear.h
create mode 100644 arch/powerpc/perf/req-gen/_end.h
create mode 100644 arch/powerpc/perf/req-gen/_request-begin.h
create mode 100644 arch/powerpc/perf/req-gen/_request-end.h
create mode 100644 arch/powerpc/perf/req-gen/perf.h
--
1.8.3.1
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[PATCH v5 1/6] perf: provide sysfs_show for struct perf_pmu_events_attr
From: Cody P Schafer c...@linux.vnet.ibm.com
(struct perf_pmu_events_attr) is defined in include/linux/perf_event.h,
but the only show for it is in x86 and contains x86 specific stuff.
Make a generic one for those of us who are just using the event_str.
CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
CC: Haren Myneni hb...@us.ibm.com
CC: Cody P Schafer d...@codyps.com
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
---
include/linux/perf_event.h | 3 +++
kernel/events/core.c | 8
2 files changed, 11 insertions(+)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 486e84c..58f59bd 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -897,6 +897,9 @@ struct perf_pmu_events_attr {
const char *event_str;
};
+ssize_t perf_event_sysfs_show(struct device *dev, struct device_attribute
*attr,
+ char *page);
+
#define PMU_EVENT_ATTR(_name, _var, _id, _show)
\
static struct perf_pmu_events_attr _var = {\
.attr = __ATTR(_name, 0444, _show, NULL), \
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 3e19d3e..1e92387 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -8276,6 +8276,14 @@ void __init perf_event_init(void)
!= 1024);
}
+ssize_t perf_event_sysfs_show(struct device *dev, struct device_attribute
*attr,
+ char *page)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+ return sprintf(page, %s\n, pmu_attr-event_str);
+}
+
static int __init perf_event_sysfs_init(void)
{
struct pmu *pmu;
--
1.8.3.1
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[PATCH v5 3/6] powerpc/perf/hv-24x7: parse catalog and populate sysfs with events
From: Cody P Schafer c...@linux.vnet.ibm.com
Retrieves and parses the 24x7 catalog on POWER systems that supply it
(right now, only POWER 8). Events are exposed via sysfs in the standard
fashion, and are all parameterized.
$ cd /sys/bus/event_source/devices/hv_24x7/events
$ cat HPM_CS_FROM_L4_LDATA__PHYS_CORE
domain=0x2,offset=0xd58,starting_index=$core,lpar=0x0
$ cat HPM_TLBIE__VCPU_HOME_CHIP
domain=0x4,offset=0x358,starting_index=$vcpu,lpar=$sibling_guest_id
where user has to specify values for $core when specifying the first event
and $vcpu and $sibling_guest_id when specifying the second event with the
perf tool.
Catalog is (at the moment) only parsed on boot. It needs re-parsing
when a some hypervisor events occur. At that point we'll also need to
prevent old events from continuing to function (counter that is passed
in via spare space in the config values?).
Changelog[v5]
[Jiri Olsa, Peter Zijlstra] Prefix required parameters with '$'
to make it easy for user to recognize.
Changelog[v4]
[Sukadev Bhattiprolu] Use PHYS and VCPU in place of PHYSICAL and
VIRTUAL_PROCESSOR to shorten the names of the domains and hence,
events;
Changelog[v2]
[Joe Perches, David Laight] Use beNN_to_cpu() instead of guessing
the size from type.
Use kmem_cache_free() to free page allocated with kmem_cache_alloc().
CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
CC: Haren Myneni hb...@us.ibm.com
CC: Cody P Schafer d...@codyps.com
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
---
arch/powerpc/perf/hv-24x7-catalog.h | 25 ++
arch/powerpc/perf/hv-24x7-domains.h | 28 ++
arch/powerpc/perf/hv-24x7.c | 787 +++-
arch/powerpc/perf/hv-24x7.h | 12 +-
4 files changed, 838 insertions(+), 14 deletions(-)
create mode 100644 arch/powerpc/perf/hv-24x7-domains.h
diff --git a/arch/powerpc/perf/hv-24x7-catalog.h
b/arch/powerpc/perf/hv-24x7-catalog.h
index 21b19dd..69e2e1f 100644
--- a/arch/powerpc/perf/hv-24x7-catalog.h
+++ b/arch/powerpc/perf/hv-24x7-catalog.h
@@ -30,4 +30,29 @@ struct hv_24x7_catalog_page_0 {
__u8 reserved6[2];
} __packed;
+struct hv_24x7_event_data {
+ __be16 length; /* in bytes, must be a multiple of 16 */
+ __u8 reserved1[2];
+ __u8 domain; /* Chip = 1, Core = 2 */
+ __u8 reserved2[1];
+ __be16 event_group_record_offs; /* in bytes, must be 8 byte aligned */
+ __be16 event_group_record_len; /* in bytes */
+
+ /* in bytes, offset from event_group_record */
+ __be16 event_counter_offs;
+
+ /* verified_state, unverified_state, caveat_state, broken_state, ... */
+ __be32 flags;
+
+ __be16 primary_group_ix;
+ __be16 group_count;
+ __be16 event_name_len;
+ __u8 remainder[];
+ /* __u8 event_name[event_name_len - 2]; */
+ /* __be16 event_description_len; */
+ /* __u8 event_desc[event_description_len - 2]; */
+ /* __be16 detailed_desc_len; */
+ /* __u8 detailed_desc[detailed_desc_len - 2]; */
+} __packed;
+
#endif
diff --git a/arch/powerpc/perf/hv-24x7-domains.h
b/arch/powerpc/perf/hv-24x7-domains.h
new file mode 100644
index 000..49c1efd
--- /dev/null
+++ b/arch/powerpc/perf/hv-24x7-domains.h
@@ -0,0 +1,28 @@
+
+/*
+ * DOMAIN(name, num, index_kind, is_physical)
+ *
+ * @name: An all caps token, suitable for use in generating an enum
+ * member and appending to an event name in sysfs.
+ *
+ * @num: The number corresponding to the domain as given in
+ * documentation. We assume the catalog domain and the hcall
+ * domain have the same numbering (so far they do), but this
+ * may need to be changed in the future.
+ *
+ * @index_kind: A stringifiable token describing the meaning of the index
+ * within the given domain. Must fit the parsing rules of the
+ * perf sysfs api.
+ *
+ * @is_physical: True if the domain is physical, false otherwise (if virtual).
+ *
+ * Note: The terms PHYS_CHIP, PHYS_CORE, VCPU correspond to physical chip,
+ * physical core and virtual processor in 24x7 Counters specifications.
+ */
+
+DOMAIN(PHYS_CHIP, 0x01, chip, true)
+DOMAIN(PHYS_CORE, 0x02, core, true)
+DOMAIN(VCPU_HOME_CORE, 0x03, vcpu, false)
+DOMAIN(VCPU_HOME_CHIP, 0x04, vcpu, false)
+DOMAIN(VCPU_HOME_NODE, 0x05, vcpu, false)
+DOMAIN(VCPU_REMOTE_NODE, 0x06, vcpu, false)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index dba3408..73d5bfc 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -13,16 +13,80 @@
#define pr_fmt(fmt) hv-24x7: fmt
#include linux/perf_event.h
+#include linux/rbtree.h
#include linux/module.h
#include linux/slab.h
+#include linux/vmalloc.h
+
#include asm/firmware.h
#include asm/hvcall.h
#include asm/io.h
+#include linux/byteorder/generic.h
#include hv-24x7.h
[PATCH v5 4/6] powerpc/perf/{hv-gpci, hv-common}: generate requests with counters annotated
From: Cody P Schafer c...@linux.vnet.ibm.com
This adds (in req-gen/) a framework for defining gpci counter requests.
It uses macro magic similar to ftrace.
Also convert the existing hv-gpci request structures and enum values to
use the new framework (and adjust old users of the structs and enum
values to cope with changes in naming).
In exchange for this macro disaster, we get autogenerated event listing
for GPCI in sysfs, build time field offset checking, and zero
duplication of information about GPCI requests.
CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
CC: Haren Myneni hb...@us.ibm.com
CC: Cody P Schafer d...@codyps.com
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
---
arch/powerpc/perf/hv-common.c | 10 +-
arch/powerpc/perf/hv-gpci-requests.h | 79 +++
arch/powerpc/perf/hv-gpci.c| 8 ++
arch/powerpc/perf/hv-gpci.h| 37 +++
arch/powerpc/perf/req-gen/_begin.h | 13 +++
arch/powerpc/perf/req-gen/_clear.h | 5 +
arch/powerpc/perf/req-gen/_end.h | 4 +
arch/powerpc/perf/req-gen/_request-begin.h | 15 +++
arch/powerpc/perf/req-gen/_request-end.h | 8 ++
arch/powerpc/perf/req-gen/perf.h | 155 +
10 files changed, 304 insertions(+), 30 deletions(-)
create mode 100644 arch/powerpc/perf/hv-gpci-requests.h
create mode 100644 arch/powerpc/perf/req-gen/_begin.h
create mode 100644 arch/powerpc/perf/req-gen/_clear.h
create mode 100644 arch/powerpc/perf/req-gen/_end.h
create mode 100644 arch/powerpc/perf/req-gen/_request-begin.h
create mode 100644 arch/powerpc/perf/req-gen/_request-end.h
create mode 100644 arch/powerpc/perf/req-gen/perf.h
diff --git a/arch/powerpc/perf/hv-common.c b/arch/powerpc/perf/hv-common.c
index 47e02b3..7dce8f10 100644
--- a/arch/powerpc/perf/hv-common.c
+++ b/arch/powerpc/perf/hv-common.c
@@ -9,13 +9,13 @@ unsigned long hv_perf_caps_get(struct hv_perf_caps *caps)
unsigned long r;
struct p {
struct hv_get_perf_counter_info_params params;
- struct cv_system_performance_capabilities caps;
+ struct hv_gpci_system_performance_capabilities caps;
} __packed __aligned(sizeof(uint64_t));
struct p arg = {
.params = {
.counter_request = cpu_to_be32(
- CIR_SYSTEM_PERFORMANCE_CAPABILITIES),
+ HV_GPCI_system_performance_capabilities),
.starting_index = cpu_to_be32(-1),
.counter_info_version_in = 0,
}
@@ -31,9 +31,9 @@ unsigned long hv_perf_caps_get(struct hv_perf_caps *caps)
caps-version = arg.params.counter_info_version_out;
caps-collect_privileged = !!arg.caps.perf_collect_privileged;
- caps-ga = !!(arg.caps.capability_mask CV_CM_GA);
- caps-expanded = !!(arg.caps.capability_mask CV_CM_EXPANDED);
- caps-lab = !!(arg.caps.capability_mask CV_CM_LAB);
+ caps-ga = !!(arg.caps.capability_mask HV_GPCI_CM_GA);
+ caps-expanded = !!(arg.caps.capability_mask HV_GPCI_CM_EXPANDED);
+ caps-lab = !!(arg.caps.capability_mask HV_GPCI_CM_LAB);
return r;
}
diff --git a/arch/powerpc/perf/hv-gpci-requests.h
b/arch/powerpc/perf/hv-gpci-requests.h
new file mode 100644
index 000..0dfc4d9
--- /dev/null
+++ b/arch/powerpc/perf/hv-gpci-requests.h
@@ -0,0 +1,79 @@
+
+#include req-gen/_begin.h
+
+/*
+ * Based on the document getPerfCountInfo v1.07
+ */
+
+/* this needs to be -1 encoded in hex suitable for parsing by tools/perf. */
+#define M1 0x
+
+/*
+ * #define REQUEST_NAME counter_request_name
+ * #define REQUEST_NUM r_num
+ * #define REQUEST_IDX_KIND starting_index_kind
+ * #include I(REQUEST_BEGIN)
+ * REQUEST(
+ * __field(...)
+ * __field(...)
+ * __array(...)
+ * __count(...)
+ * )
+ * #include I(REQUEST_END)
+ *
+ * - starting_index_kind is one of:
+ * M1: must be -1
+ * chip_id: hardware chip id or -1 for current hw chip
+ * phys_processor_idx:
+ *
+ * __count(offset, bytes, name):
+ * a counter that should be exposed via perf
+ * __field(offset, bytes, name)
+ * a normal field
+ * __array(offset, bytes, name)
+ * an array of bytes
+ *
+ *
+ * @bytes for __count, and __field _must_ be a numeral token
+ * in decimal, not an expression and not in hex.
+ *
+ *
+ * TODO:
+ * - expose secondary index (if any counter ever uses it, only 0xA0
+ * appears to use it right now, and it doesn't have any counters)
+ * - embed versioning info
+ * - include counter descriptions
+ */
+#define REQUEST_NAME dispatch_timebase_by_processor
+#define REQUEST_NUM 0x10
+#define REQUEST_IDX_KIND phys_processor_idx
+#include I(REQUEST_BEGIN)
+REQUEST(__count(0, 8, processor_time_in_timebase_cycles)
+ __field(0x8,4, hw_processor_id)
+ __field(0xC,2,
[PATCH v5 2/6] perf: add PMU_EVENT_ATTR_STRING() helper
From: Cody P Schafer c...@linux.vnet.ibm.com
Helper for constructing static struct perf_pmu_events_attr s.
CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
CC: Haren Myneni hb...@us.ibm.com
CC: Cody P Schafer d...@codyps.com
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
---
include/linux/perf_event.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 58f59bd..4038299 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -906,6 +906,13 @@ static struct perf_pmu_events_attr _var = {
\
.id = _id, \
};
+#define PMU_EVENT_ATTR_STRING(_name, _var, _value) \
+static struct perf_pmu_events_attr _var = {\
+ .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \
+ .event_str = _value,\
+};
+
+
#define PMU_FORMAT_ATTR(_name, _format)
\
static ssize_t \
_name##_show(struct device *dev, \
--
1.8.3.1
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[PATCH v5 5/6] powerpc/perf/hv-gpci: add the remaining gpci requests
From: Cody P Schafer c...@linux.vnet.ibm.com Add the remaining gpci requests that contain counters suitable for use by perf. Omit those that don't contain any counters (but note their ommision). CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com CC: Haren Myneni hb...@us.ibm.com CC: Cody P Schafer d...@codyps.com Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com --- arch/powerpc/perf/hv-gpci-requests.h | 183 +++ 1 file changed, 183 insertions(+) diff --git a/arch/powerpc/perf/hv-gpci-requests.h b/arch/powerpc/perf/hv-gpci-requests.h index 0dfc4d9..bf70fdf 100644 --- a/arch/powerpc/perf/hv-gpci-requests.h +++ b/arch/powerpc/perf/hv-gpci-requests.h @@ -65,6 +65,33 @@ REQUEST(__count(0, 8, processor_time_in_timebase_cycles) ) #include I(REQUEST_END) +#define REQUEST_NAME entitled_capped_uncapped_donated_idle_timebase_by_partition +#define REQUEST_NUM 0x20 +#define REQUEST_IDX_KIND sibling_part_id +#include I(REQUEST_BEGIN) +REQUEST(__field(0, 8, partition_id) + __count(0x8,8, entitled_cycles) + __count(0x10, 8, consumed_capped_cycles) + __count(0x18, 8, consumed_uncapped_cycles) + __count(0x20, 8, cycles_donated) + __count(0x28, 8, purr_idle_cycles) +) +#include I(REQUEST_END) + +/* + * Not available for counter_info_version = 0x8, use + * run_instruction_cycles_by_partition(0x100) instead. + */ +#define REQUEST_NAME run_instructions_run_cycles_by_partition +#define REQUEST_NUM 0x30 +#define REQUEST_IDX_KIND sibling_part_id +#include I(REQUEST_BEGIN) +REQUEST(__field(0, 8, partition_id) + __count(0x8,8, instructions_completed) + __count(0x10, 8, cycles) +) +#include I(REQUEST_END) + #define REQUEST_NAME system_performance_capabilities #define REQUEST_NUM 0x40 #define REQUEST_IDX_KIND M1 @@ -75,5 +102,161 @@ REQUEST(__field(0, 1, perf_collect_privileged) ) #include I(REQUEST_END) +#define REQUEST_NAME processor_bus_utilization_abc_links +#define REQUEST_NUM 0x50 +#define REQUEST_IDX_KIND hw_chip_id +#include I(REQUEST_BEGIN) +REQUEST(__field(0, 4, hw_chip_id) + __array(0x4,0xC,reserved1) + __count(0x10, 8, total_link_cycles) + __count(0x18, 8, idle_cycles_for_a_link) + __count(0x20, 8, idle_cycles_for_b_link) + __count(0x28, 8, idle_cycles_for_c_link) + __array(0x30, 0x20, reserved2) +) +#include I(REQUEST_END) + +#define REQUEST_NAME processor_bus_utilization_wxyz_links +#define REQUEST_NUM 0x60 +#define REQUEST_IDX_KIND hw_chip_id +#include I(REQUEST_BEGIN) +REQUEST(__field(0, 4, hw_chip_id) + __array(0x4,0xC,reserved1) + __count(0x10, 8, total_link_cycles) + __count(0x18, 8, idle_cycles_for_w_link) + __count(0x20, 8, idle_cycles_for_x_link) + __count(0x28, 8, idle_cycles_for_y_link) + __count(0x30, 8, idle_cycles_for_z_link) + __array(0x38, 0x28, reserved2) +) +#include I(REQUEST_END) + +#define REQUEST_NAME processor_bus_utilization_gx_links +#define REQUEST_NUM 0x70 +#define REQUEST_IDX_KIND hw_chip_id +#include I(REQUEST_BEGIN) +REQUEST(__field(0, 4, hw_chip_id) + __array(0x4,0xC,reserved1) + __count(0x10, 8, gx0_in_address_cycles) + __count(0x18, 8, gx0_in_data_cycles) + __count(0x20, 8, gx0_in_retries) + __count(0x28, 8, gx0_in_bus_cycles) + __count(0x30, 8, gx0_in_cycles_total) + __count(0x38, 8, gx0_out_address_cycles) + __count(0x40, 8, gx0_out_data_cycles) + __count(0x48, 8, gx0_out_retries) + __count(0x50, 8, gx0_out_bus_cycles) + __count(0x58, 8, gx0_out_cycles_total) + __count(0x60, 8, gx1_in_address_cycles) + __count(0x68, 8, gx1_in_data_cycles) + __count(0x70, 8, gx1_in_retries) + __count(0x78, 8, gx1_in_bus_cycles) + __count(0x80, 8, gx1_in_cycles_total) + __count(0x88, 8, gx1_out_address_cycles) + __count(0x90, 8, gx1_out_data_cycles) + __count(0x98, 8, gx1_out_retries) + __count(0xA0, 8, gx1_out_bus_cycles) + __count(0xA8, 8, gx1_out_cycles_total) +) +#include I(REQUEST_END) + +#define REQUEST_NAME processor_bus_utilization_mc_links +#define REQUEST_NUM 0x80 +#define REQUEST_IDX_KIND hw_chip_id +#include I(REQUEST_BEGIN) +REQUEST(__field(0, 4, hw_chip_id) + __array(0x4,0xC,reserved1) + __count(0x10, 8, mc0_frames) + __count(0x18, 8, mc0_reads) + __count(0x20, 8, mc0_write) + __count(0x28, 8, mc0_total_cycles) + __count(0x30, 8, mc1_frames) + __count(0x38, 8, mc1_reads) + __count(0x40, 8, mc1_writes) + __count(0x48, 8,
[PATCH v5 6/6] powerpc/perf/hv-24x7: Document sysfs event description entries
From: Cody P Schafer c...@linux.vnet.ibm.com CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com CC: Haren Myneni hb...@us.ibm.com CC: Cody P Schafer d...@codyps.com Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com --- .../testing/sysfs-bus-event_source-devices-hv_24x7 | 22 ++ 1 file changed, 22 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 index 32f3f5f..cf70084 100644 --- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 @@ -21,3 +21,25 @@ Contact: Linux on PowerPC Developer List linuxppc-dev@lists.ozlabs.org Description: Exposes the version field of the 24x7 catalog. This is also extractable from the provided binary catalog sysfs entry. + +What: /sys/bus/event_source/devices/hv_24x7/event_descs/event-name +Date: February 2014 +Contact: Cody P Schafer c...@linux.vnet.ibm.com +Description: + Provides the description of a particular event as provided by + the firmware. If firmware does not provide a description, no + file will be created. + + Note that the event-name lacks the domain suffix appended for + events in the events/ dir. + +What: /sys/bus/event_source/devices/hv_24x7/event_long_descs/event-name +Date: February 2014 +Contact: Cody P Schafer c...@linux.vnet.ibm.com +Description: + Provides the long description of a particular event as + provided by the firmware. If firmware does not provide a + description, no file will be created. + + Note that the event-name lacks the domain suffix appended for + events in the events/ dir. -- 1.8.3.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 0/4] Add support for parametrized events
Description of event parameters from the documentation patch: Event parameters are a basic way for partial events to be specified in sysfs with per-event names given to the fields that need to be filled in when using a particular event. It is intended for supporting cases where the single 'cpu' parameter is insufficient. For example, POWER 8 has events for physical sockets/cores/cpus that are accessible from with virtual machines. To keep using the single 'cpu' parameter we'd need to perform a mapping between Linux's cpus and the physical machine's cpus (in this case Linux is running under a hypervisor). This isn't possible because bindings between our cpus and physical cpus may not be fixed, and we probably won't have a cpu on each physical cpu. Description of the sysfs contents when events are parameterized (copied from an included patch): Examples: domain=0x1,offset=0x8,starting_index=$core In the case of the last example, a value replacing $core would need to be provided by the user selecting the particular event. This is refered to as event parameterization. All non-numerical values indicate an event parameter. Notes on how perf-list displays parameterized events PARAMETERIZED EVENTS Some pmu events listed by 'perf list' will be displayed with '$xyz' in them. For example: hv_24x7/HPM_THREAD_NAP_CCYC__PHYS_CORE,starting_index=$core/ This means that when provided as an event, a value for $core must also be supplied. For example: perf stat -e \ 'hv_24x7/HPM_THREAD_NAP_CCYC__PHYS_CORE,starting_index=2' ... Changelog[v5] - [Jiri Olsa, Peter Zijlstra] Use '$arg' notation rather than ? to indicate event parameters. - [Michael Ellerman] Separate the kernel and tool patches in the patchset into different patchsets. Changelog[v4] - [Jiri Olsa] Rebase to perf/core tree (fix small merge conflict) Changelog[v3] - [Jiri Olsa] Changed the event parameters are specified. If event file specifes 'param=val' make the usage 'param=123' rather than 'val=123'. (patch 1,2/10) - Shortened event names using PHYS and VCPU (patch 4/10) - Print help message if invalid parameter is specified or required parameter is missing. - Moved 3 patches that are unrelated to parametrized events into a separate patchset. - Reordered patches so code changes come first. Changelog[v2] - [Joe Perches, David Laight] Use beNN_to_cpu() instead of guessing the size from type. - Use kmem_cache_free() to free page allocated with kmem_cache_alloc(). - Rebase to recent kernel Cody P Schafer (4): tools/perf: support parsing parameterized events tools/perf: extend format_alias() to include event parameters perf Documentation: add event parameters tools/perf: Document parameterized and symbolic events .../testing/sysfs-bus-event_source-devices-events | 6 ++ tools/perf/Documentation/perf-list.txt | 13 +++ tools/perf/Documentation/perf-record.txt | 12 +++ tools/perf/Documentation/perf-stat.txt | 20 - tools/perf/util/parse-events.h | 1 + tools/perf/util/pmu.c | 92 +++--- 6 files changed, 128 insertions(+), 16 deletions(-) -- 1.8.3.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 2/4] tools/perf: extend format_alias() to include event parameters
From: Cody P Schafer c...@linux.vnet.ibm.com
This causes `perf list pmu` to show parameters for parameterized events
like:
pmu/event_name,param1=$param1,param2=$param2/ [Kernel PMU event]
Example:
hv_24x7/HPM_TLBIE__PHYS_CORE,starting_index=$core/ [Kernel PMU event]
Changelog[v5]
[Jiri Olsa, Peter Zijlstra] Use '$' to prefix parameterized events.
Changelog[v4]
[Jiri Olsa] If the parameter for an event in sysfs is 'param=val',
have perf-list show the event as 'param=?' rather than 'val=?'.
CC: Haren Myneni hb...@us.ibm.com
CC: Cody P Schafer d...@codyps.com
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
---
tools/perf/util/pmu.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index cb516dd..f8674c1 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -810,10 +810,35 @@ void perf_pmu__set_format(unsigned long *bits, long from,
long to)
set_bit(b, bits);
}
+static int sub_non_neg(int a, int b)
+{
+ if (b a)
+ return 0;
+ return a - b;
+}
+
static char *format_alias(char *buf, int len, struct perf_pmu *pmu,
struct perf_pmu_alias *alias)
{
- snprintf(buf, len, %s/%s/, pmu-name, alias-name);
+ struct parse_events_term *term;
+ int used = snprintf(buf, len, %s/%s, pmu-name, alias-name);
+
+ list_for_each_entry(term, alias-terms, list)
+ if (term-type_val == PARSE_EVENTS__TERM_TYPE_STR)
+ used += snprintf(buf + used, sub_non_neg(len, used),
+ ,%s=$%s, term-config,
+ term-val.str);
+
+ if (sub_non_neg(len, used) 0) {
+ buf[used] = '/';
+ used++;
+ }
+ if (sub_non_neg(len, used) 0) {
+ buf[used] = '\0';
+ used++;
+ } else
+ buf[len - 1] = '\0';
+
return buf;
}
--
1.8.3.1
___
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[PATCH v5 1/4] tools/perf: support parsing parameterized events
From: Cody P Schafer c...@linux.vnet.ibm.com
Enable event specification like:
pmu/event_name,param1=0x1,param2=0x4/
Assuming that
/sys/bus/event_source/devices/pmu/events/event_name
Contains something like
param2=$foo,bar=1,param1=$baz
Changelog[v4]:
[Jiri Olsa] Merge to recent perf-core and fix a small conflict.
Changelog[v3]:
[Jiri Olsa] If the sysfs event file specifies 'param=val', make the
usage 'hv_24x7/event,param=123/' rather than 'hv_24x7/event,val=123/'.
CC: Haren Myneni hb...@us.ibm.com
CC: Cody P Schafer d...@codyps.com
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
Conflicts:
tools/perf/util/pmu.c
---
tools/perf/util/parse-events.h | 1 +
tools/perf/util/pmu.c | 65 +++---
2 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h
index db2cf78..ca226ce 100644
--- a/tools/perf/util/parse-events.h
+++ b/tools/perf/util/parse-events.h
@@ -71,6 +71,7 @@ struct parse_events_term {
int type_val;
int type_term;
struct list_head list;
+ bool used;
};
struct parse_events_evlist {
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 5c9c494..cb516dd 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -551,31 +551,68 @@ static void pmu_format_value(unsigned long *format, __u64
value, __u64 *v,
}
/*
+ * Term is a string term, and might be a param-term. Try to look up it's value
+ * in the remaining terms.
+ * - We have a term like base-or-format-term=param-term,
+ * - We need to find the value supplied for param-term (with param-term named
+ * in a config string) later on in the term list.
+ */
+static int pmu_resolve_param_term(struct parse_events_term *term,
+ struct list_head *head_terms,
+ __u64 *value)
+{
+ struct parse_events_term *t;
+
+ list_for_each_entry(t, head_terms, list) {
+ if (t-type_val == PARSE_EVENTS__TERM_TYPE_NUM) {
+ if (!strcmp(t-config, term-config)) {
+ t-used = true;
+ *value = t-val.num;
+ return 0;
+ }
+ }
+ }
+
+ if (verbose)
+ printf(Required parameter '%s' not specified\n, term-config);
+
+ return -1;
+}
+
+/*
* Setup one of config[12] attr members based on the
* user input data - term parameter.
*/
static int pmu_config_term(struct list_head *formats,
struct perf_event_attr *attr,
struct parse_events_term *term,
+ struct list_head *head_terms,
bool zero)
{
struct perf_pmu_format *format;
__u64 *vp;
+ __u64 val;
+
+ /*
+* If this is a parameter we've already used for parameterized-eval,
+* skip it in normal eval.
+*/
+ if (term-used)
+ return 0;
/*
-* Support only for hardcoded and numnerial terms.
* Hardcoded terms should be already in, so nothing
* to be done for them.
*/
if (parse_events__is_hardcoded_term(term))
return 0;
- if (term-type_val != PARSE_EVENTS__TERM_TYPE_NUM)
- return -EINVAL;
-
format = pmu_find_format(formats, term-config);
- if (!format)
+ if (!format) {
+ if (verbose)
+ printf(Invalid event/parameter '%s'\n, term-config);
return -EINVAL;
+ }
switch (format-value) {
case PERF_PMU_FORMAT_VALUE_CONFIG:
@@ -592,11 +629,16 @@ static int pmu_config_term(struct list_head *formats,
}
/*
-* XXX If we ever decide to go with string values for
-* non-hardcoded terms, here's the place to translate
-* them into value.
+* Either directly use a numeric term, or try to translate string terms
+* using event parameters.
*/
- pmu_format_value(format-bits, term-val.num, vp, zero);
+ if (term-type_val == PARSE_EVENTS__TERM_TYPE_NUM)
+ val = term-val.num;
+ else
+ if (pmu_resolve_param_term(term, head_terms, val))
+ return -EINVAL;
+
+ pmu_format_value(format-bits, val, vp, zero);
return 0;
}
@@ -607,9 +649,10 @@ int perf_pmu__config_terms(struct list_head *formats,
{
struct parse_events_term *term;
- list_for_each_entry(term, head_terms, list)
- if (pmu_config_term(formats, attr, term, zero))
+ list_for_each_entry(term, head_terms, list) {
+ if (pmu_config_term(formats, attr, term, head_terms, zero))
return
[PATCH v5 3/4] perf Documentation: add event parameters
From: Cody P Schafer c...@linux.vnet.ibm.com Event parameters are a basic way for partial events to be specified in sysfs with per-event names given to the fields that need to be filled in when using a particular event. It is intended for supporting cases where the single 'cpu' parameter is insufficient. For example, POWER 8 has events for physical sockets/cores/cpus that are accessible from with virtual machines. To keep using the single 'cpu' parameter we'd need to perform a mapping between Linux's cpus and the physical machine's cpus (in this case Linux is running under a hypervisor). This isn't possible because bindings between our cpus and physical cpus may not be fixed, and we probably won't have a cpu on each physical cpu. CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com CC: Haren Myneni hb...@us.ibm.com CC: Cody P Schafer d...@codyps.com Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com --- Documentation/ABI/testing/sysfs-bus-event_source-devices-events | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events index 20979f8..f584b16 100644 --- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events @@ -52,12 +52,18 @@ Description:Per-pmu performance monitoring events specific to the running syste event=0x2abc event=0x423,inv,cmask=0x3 domain=0x1,offset=0x8,starting_index=0x + domain=0x1,offset=0x8,starting_index=$phys_cpu Each of the assignments indicates a value to be assigned to a particular set of bits (as defined by the format file corresponding to the term) in the perf_event structure passed to the perf_open syscall. + In the case of the last example, a value replacing $phys_cpu + would need to be provided by the user selecting the particular + event. This is referred to as event parameterization. All + non-numerical values indicate an event parameter. + What: /sys/bus/event_source/devices/pmu/events/event.unit Date: 2014/02/24 Contact: Linux kernel mailing list linux-ker...@vger.kernel.org -- 1.8.3.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 4/4] tools/perf: Document parameterized and symbolic events
From: Cody P Schafer c...@linux.vnet.ibm.com Changelog[v6]: - [Sukadev Bhattiprolu]: Update documentation of perf-list and perf-record; Added documentation for perf-stat. CC: Haren Myneni hb...@us.ibm.com CC: Cody P Schafer d...@codyps.com Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com --- tools/perf/Documentation/perf-list.txt | 13 + tools/perf/Documentation/perf-record.txt | 12 tools/perf/Documentation/perf-stat.txt | 20 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index cbb4f74..8e9a1121 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -89,6 +89,19 @@ raw encoding of 0x1A8 can be used: You should refer to the processor specific documentation for getting these details. Some of them are referenced in the SEE ALSO section below. +PARAMETERIZED EVENTS + + +Some pmu events listed by 'perf-list' will be displayed with '$x' in them. For +example: + + hv_gpci/dtbp_ptitc,starting_index=$core/ + +This means that when provided as an event, a value for '$core' must +also be supplied. For example: + + perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,starting_index=0x2/' ... + OPTIONS --- diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index af9a54e..acdcf3b 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -33,6 +33,18 @@ OPTIONS - a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a hexadecimal event descriptor. + - a symbolically formed PMU event like 'pmu/param1=0x3,param2/' where + 'param1', 'param2', etc are defined as formats for the PMU in + /sys/bus/event_sources/devices/pmu/format/*. + + - a symbolically formed event like 'pmu/config=M,config1=N,config3=K/' + + where M, N, K are numbers (in decimal, hex, octal format). Acceptable + values for each of 'config', 'config1' and 'config2' are defined by + corresponding entries in /sys/bus/event_sources/devices/pmu/format/* + param1 and param2 are defined as formats for the PMU in: + /sys/bus/event_sources/devices/pmu/format/* + - a hardware breakpoint event in the form of '\mem:addr[:access]' where addr is the address in memory you want to break in. Access is the memory access type (read, write, execute) it can diff --git a/tools/perf/Documentation/perf-stat.txt b/tools/perf/Documentation/perf-stat.txt index 29ee857..04e150d 100644 --- a/tools/perf/Documentation/perf-stat.txt +++ b/tools/perf/Documentation/perf-stat.txt @@ -25,10 +25,22 @@ OPTIONS -e:: --event=:: - Select the PMU event. Selection can be a symbolic event name - (use 'perf list' to list all events) or a raw PMU - event (eventsel+umask) in the form of rNNN where NNN is a -hexadecimal event descriptor. + Select the PMU event. Selection can be: + + - a symbolic event name (use 'perf list' to list all events) + + - a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a + hexadecimal event descriptor. + + - a symbolically formed event like 'pmu/param1=0x3,param2/' where + param1 and param2 are defined as formats for the PMU in + /sys/bus/event_sources/devices/pmu/format/* + + - a symbolically formed event like 'pmu/config=M,config1=N,config2=K/' + where M, N, K are numbers (in decimal, hex, octal format). + Acceptable values for each of 'config', 'config1' and 'config2' + parameters are defined by corresponding entries in + /sys/bus/event_sources/devices/pmu/format/* -i:: --no-inherit:: -- 1.8.3.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V2] powerpc/mm: don't do tlbie for updatepp request with NO HPTE fault
On Tue, 2014-12-02 at 12:20 +0530, Aneesh Kumar K.V wrote: upatepp get called for a nohpte fault, when we find from the linux page table that the translation was hashed before. In that case we are sure that there is no existing translation, hence we could avoid doing tlbie. Same comments as last time. http://patchwork.ozlabs.org/patch/406219/ cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: powernv: Return to cpu offline loop when finished in KVM guest
When a secondary hardware thread has finished running a KVM guest, we
currently put that thread into nap mode using a nap instruction in
the KVM code. This changes the code so that instead of doing a nap
instruction directly, we instead cause the call to power7_nap() that
put the thread into nap mode to return. The reason for doing this is
to avoid having the KVM code having to know what low-power mode to
put the thread into.
In the case of a secondary thread used to run a KVM guest, the thread
will be offline from the point of view of the host kernel, and the
relevant power7_nap() call is the one in pnv_smp_cpu_disable().
In this case we don't want to clear pending IPIs in the offline loop
in that function, since that might cause us to miss the wakeup for
the next time the thread needs to run a guest. To tell whether or
not to clear the interrupt, we use the SRR1 value returned from
power7_nap(), and check if it indicates an external interrupt. We
arrange that the return from power7_nap() when we have finished running
a guest returns 0, so pending interrupts don't get flushed in that
case.
Note that it is important a secondary thread that has finished
executing in the guest, or that didn't have a guest to run, should
not return to power7_nap's caller while the kvm_hstate.hwthread_req
flag in the PACA is non-zero, because the return from power7_nap
will reenable the MMU, and the MMU might still be in guest context.
In this situation we spin at low priority in real mode waiting for
hwthread_req to become zero.
Signed-off-by: Paul Mackerras pau...@samba.org
---
I think this would be best going through the powerpc tree. Alex,
if you can give me an acked-by for this that would be appreciated.
arch/powerpc/include/asm/processor.h| 2 +-
arch/powerpc/kernel/exceptions-64s.S| 2 ++
arch/powerpc/kernel/idle_power7.S | 12 ++--
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 54 ++---
arch/powerpc/platforms/powernv/smp.c| 23 +++---
5 files changed, 68 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index dda7ac4..29c3798 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -451,7 +451,7 @@ extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
extern int powersave_nap; /* set if nap mode can be used in idle loop */
-extern void power7_nap(int check_irq);
+extern unsigned long power7_nap(int check_irq);
extern void power7_sleep(void);
extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index a1d45c1..7f29c5f 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -131,6 +131,8 @@ BEGIN_FTR_SECTION
1:
#endif
+ /* Return SRR1 from power7_nap() */
+ mfspr r3,SPRN_SRR1
beq cr1,2f
b power7_wakeup_noloss
2: b power7_wakeup_loss
diff --git a/arch/powerpc/kernel/idle_power7.S
b/arch/powerpc/kernel/idle_power7.S
index c0754bb..18c0687 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -212,6 +212,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
mtspr SPRN_SRR0,r5
rfid
+/*
+ * R3 here contains the value that will be returned to the caller
+ * of power7_nap.
+ */
_GLOBAL(power7_wakeup_loss)
ld r1,PACAR1(r13)
BEGIN_FTR_SECTION
@@ -219,15 +223,19 @@ BEGIN_FTR_SECTION
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
REST_NVGPRS(r1)
REST_GPR(2, r1)
- ld r3,_CCR(r1)
+ ld r6,_CCR(r1)
ld r4,_MSR(r1)
ld r5,_NIP(r1)
addir1,r1,INT_FRAME_SIZE
- mtcrr3
+ mtcrr6
mtspr SPRN_SRR1,r4
mtspr SPRN_SRR0,r5
rfid
+/*
+ * R3 here contains the value that will be returned to the caller
+ * of power7_nap.
+ */
_GLOBAL(power7_wakeup_noloss)
lbz r0,PACA_NAPSTATELOST(r13)
cmpwi r0,0
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index edb2ccd..65c105b 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -201,8 +201,6 @@ kvmppc_primary_no_guest:
bge kvm_novcpu_exit /* another thread already exiting */
li r3, NAPPING_NOVCPU
stb r3, HSTATE_NAPPING(r13)
- li r3, 1
- stb r3, HSTATE_HWTHREAD_REQ(r13)
b kvm_do_nap
@@ -293,6 +291,8 @@ kvm_start_guest:
/* if we have no vcpu to run, go back to sleep */
beq kvm_no_guest
+kvm_secondary_got_guest:
+
/* Set HSTATE_DSCR(r13) to something sensible */
ld r6, PACA_DSCR(r13)
std r6, HSTATE_DSCR(r13)
@@ -318,27 +318,46 @@ kvm_start_guest:
[PATCH v2] powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument.
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
The flush_tlb hook in cpu_spec was introduced as a generic function hook
to invalidate TLBs. But the current implementation of flush_tlb hook
takes IS (invalidation selector) as an argument which is architecture
dependent. Hence, It is not right to have a generic routine where caller
has to pass non-generic argument.
This patch fixes this and makes flush_tlb hook as high level API.
The existing MCE code calls flush_tlb hook with IS=0 (single page) resulting
partial invalidation of TLBs which is not right. This rework now makes
sure that whole TLB is invalidated to be able to successfully recover from
TLB and ERAT errors.
Reported-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
Changes in V2:
- Moved TLB flush action #defines to cputable.h
- Added missing ptesyncs to before and after TLB flush.
- Moved switch case to flush_tlb_206() function as suggested by
Michael Ellerman.
arch/powerpc/include/asm/cputable.h |6 +++-
arch/powerpc/include/asm/mmu-hash64.h |1 +
arch/powerpc/kernel/cpu_setup_power.S | 10 +-
arch/powerpc/kernel/cputable.c|4 +-
arch/powerpc/kernel/mce_power.c | 53 -
arch/powerpc/kvm/book3s_hv_ras.c |4 +-
6 files changed, 63 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index daa5af9..d053301 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -100,7 +100,7 @@ struct cpu_spec {
/*
* Processor specific routine to flush tlbs.
*/
- void(*flush_tlb)(unsigned long inval_selector);
+ void(*flush_tlb)(unsigned int action);
};
@@ -114,6 +114,10 @@ extern void do_feature_fixups(unsigned long value, void
*fixup_start,
extern const char *powerpc_base_platform;
+/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
+#define FLUSH_TLB_ALL 0 /* invalidate all TLBs */
+#define FLUSH_TLB_LPID 1 /* invalidate TLBs for current LPID */
+
#endif /* __ASSEMBLY__ */
/* CPU kernel features */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index aeebc94..4f50db7 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -112,6 +112,7 @@
#define TLBIEL_INVAL_SET_SHIFT 12
#define POWER7_TLB_SETS128 /* # sets in POWER7 TLB */
+#define POWER8_TLB_SETS512 /* # sets in POWER8 TLB */
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index 4673353..9c9b741 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -137,15 +137,11 @@ __init_HFSCR:
/*
* Clear the TLB using the specified IS form of tlbiel instruction
* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
- *
- * r3 = IS field
*/
__init_tlb_power7:
- li r3,0xc00/* IS field = 0b11 */
-_GLOBAL(__flush_tlb_power7)
li r6,128
mtctr r6
- mr r7,r3 /* IS field */
+ li r7,0xc00/* IS field = 0b11 */
ptesync
2: tlbiel r7
addir7,r7,0x1000
@@ -154,11 +150,9 @@ _GLOBAL(__flush_tlb_power7)
1: blr
__init_tlb_power8:
- li r3,0xc00/* IS field = 0b11 */
-_GLOBAL(__flush_tlb_power8)
li r6,512
mtctr r6
- mr r7,r3 /* IS field */
+ li r7,0xc00/* IS field = 0b11 */
ptesync
2: tlbiel r7
addir7,r7,0x1000
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 8084059..81c1ba5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -71,8 +71,8 @@ extern void __restore_cpu_power7(void);
extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_power8(void);
extern void __restore_cpu_a2(void);
-extern void __flush_tlb_power7(unsigned long inval_selector);
-extern void __flush_tlb_power8(unsigned long inval_selector);
+extern void __flush_tlb_power7(unsigned int action);
+extern void __flush_tlb_power8(unsigned int action);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index aa9aff3..65f6043 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -28,6 +28,55 @@
#include asm/mce.h
#include asm/machdep.h
+static void flush_tlb_206(unsigned int num_sets, unsigned int action)
+{
+ unsigned long rb;
+
Re: [V6,1/9] elf: Add new powerpc specifc core note sections
On Tue, 2014-02-12 at 07:56:45 UTC, Anshuman Khandual wrote:
This patch adds four new ELF core note sections for powerpc
transactional memory and one new ELF core note section for
powerpc general miscellaneous debug registers. These addition
of new ELF core note sections extends the existing ELF ABI
without affecting it in any manner.
Acked-by: Andrew Morton a...@linux-foundation.org
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
include/uapi/linux/elf.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ea9bf25..2260fc0 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -379,6 +379,11 @@ typedef struct elf64_shdr {
#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
+#define NT_PPC_TM_SPR0x103 /* PowerPC TM special registers
*/
+#define NT_PPC_TM_CGPR 0x104 /* PowerpC TM checkpointed GPR
*/
+#define NT_PPC_TM_CFPR 0x105 /* PowerPC TM checkpointed FPR
*/
+#define NT_PPC_TM_CVMX 0x106 /* PowerPC TM checkpointed VMX
*/
+#define NT_PPC_MISC 0x107 /* PowerPC miscellaneous registers */
This is a really terrible name, MISC.
Having said that, I guess it's accurate. We have a whole bunch of regs that
have accrued over recent years that aren't accessible via ptrace.
It seems to me if we're adding a misc regset we should be adding everything we
might want to it that is currenty architected.
But currently you only include the PPR, TAR DSCR.
Looking at Power ISA v2.07, I see the following that could be included:
MMCR2
MMCRA
PMC1
PMC2
PMC3
PMC4
PMC5
PMC6
MMCR0
EBBHR
EBBRR
BESCR
SIAR
SDAR
CFAR?
Those are all new in 2.07 except for CFAR.
There might be more I missed, that was just a quick scan.
Some are only accessible when EBB is in use, maybe those could be a separate
regset.
cheers
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Re: [PATCH V6 9/9] selftests: Make GIT ignore all binaries in powerpc test suite
On 12/02/2014 11:53 PM, Shuah Khan wrote: On 12/02/2014 12:56 AM, Anshuman Khandual wrote: This patch includes all of the powerpc test binaries into the .gitignore file listing in their respective directories. This will make sure that GIT ignores all of these test binaries while displaying status. Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- .../testing/selftests/powerpc/copyloops/.gitignore | 4 tools/testing/selftests/powerpc/mm/.gitignore | 1 + tools/testing/selftests/powerpc/pmu/.gitignore | 3 +++ tools/testing/selftests/powerpc/pmu/ebb/.gitignore | 22 ++ .../selftests/powerpc/primitives/.gitignore| 1 + 5 files changed, 31 insertions(+) create mode 100644 tools/testing/selftests/powerpc/copyloops/.gitignore create mode 100644 tools/testing/selftests/powerpc/mm/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/.gitignore create mode 100644 tools/testing/selftests/powerpc/primitives/.gitignore Creating a single .gitignore at tools/testing/selftests/powerpc will make this simpler without having to add one .gitignore for each directory underneath. Sure, will do. Thanks for taking on the task to add .gitignore for all powerpc binaries. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v5 1/6] perf: provide sysfs_show for struct perf_pmu_events_attr
On Tue, 2014-12-02 at 18:03 -0800, Sukadev Bhattiprolu wrote: From: Cody P Schafer c...@linux.vnet.ibm.com (struct perf_pmu_events_attr) is defined in include/linux/perf_event.h, but the only show for it is in x86 and contains x86 specific stuff. Make a generic one for those of us who are just using the event_str. CC: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com CC: Haren Myneni hb...@us.ibm.com CC: Cody P Schafer d...@codyps.com Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com --- include/linux/perf_event.h | 3 +++ kernel/events/core.c | 8 2 files changed, 11 insertions(+) Acme/Peterz, are you happy for us to take this series through the powerpc tree? Do you want to give us an ack for patches 1 2? cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 0/3] fix a kernel panic on fsl corenet board when CONFIG_CLK_PPC_CORENET is enabled
On Tue, Dec 02, 2014 at 06:38:57PM -0600, Scott Wood wrote: If the current code panics as of commit da788acb2838, then the revert (but not the other patches) should go to stable as well. OK, I will make a respin to cc stable and add yours and Michael's ack. Thanks, Kevin pgpVjwceGF3KP.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [V6,1/9] elf: Add new powerpc specifc core note sections
On 12/03/2014 10:52 AM, Michael Ellerman wrote:
On Tue, 2014-02-12 at 07:56:45 UTC, Anshuman Khandual wrote:
This patch adds four new ELF core note sections for powerpc
transactional memory and one new ELF core note section for
powerpc general miscellaneous debug registers. These addition
of new ELF core note sections extends the existing ELF ABI
without affecting it in any manner.
Acked-by: Andrew Morton a...@linux-foundation.org
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
include/uapi/linux/elf.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ea9bf25..2260fc0 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -379,6 +379,11 @@ typedef struct elf64_shdr {
#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
+#define NT_PPC_TM_SPR 0x103 /* PowerPC TM special registers
*/
+#define NT_PPC_TM_CGPR 0x104 /* PowerpC TM checkpointed GPR
*/
+#define NT_PPC_TM_CFPR 0x105 /* PowerPC TM checkpointed FPR
*/
+#define NT_PPC_TM_CVMX 0x106 /* PowerPC TM checkpointed VMX
*/
+#define NT_PPC_MISC 0x107 /* PowerPC miscellaneous registers */
This is a really terrible name, MISC.
Having said that, I guess it's accurate. We have a whole bunch of regs that
have accrued over recent years that aren't accessible via ptrace.
It seems to me if we're adding a misc regset we should be adding everything we
might want to it that is currenty architected.
But I believe they also need to be part of the thread_struct structure to be
accessible from ptrace.
But currently you only include the PPR, TAR DSCR.
Yeah, thats what we started with.
Looking at Power ISA v2.07, I see the following that could be included:
MMCR2
MMCRA
PMC1
PMC2
PMC3
PMC4
PMC5
PMC6
MMCR0
EBBHR
EBBRR
BESCR
SIAR
SDAR
CFAR?
MMCRA, PMC[1..6], EBBHR, BESCR, EBBRR, CFAR are not part of the thread struct.
Those are all new in 2.07 except for CFAR.
There might be more I missed, that was just a quick scan.
Some are only accessible when EBB is in use, maybe those could be a separate
regset.
Yeah we can have one more regset for EBB specific registers.
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Re: [PATCH] ALSA: i2sbus: Deletion of unnecessary checks before the function call release_and_free_resource
At Tue, 02 Dec 2014 22:55:57 +0100, SF Markus Elfring wrote: From: Markus Elfring elfr...@users.sourceforge.net Date: Tue, 2 Dec 2014 22:50:24 +0100 The release_and_free_resource() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring elfr...@users.sourceforge.net Thanks, applied. Takashi --- sound/aoa/soundbus/i2sbus/core.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/sound/aoa/soundbus/i2sbus/core.c b/sound/aoa/soundbus/i2sbus/core.c index a80d5ea..4e2b4fb 100644 --- a/sound/aoa/soundbus/i2sbus/core.c +++ b/sound/aoa/soundbus/i2sbus/core.c @@ -79,8 +79,7 @@ static void i2sbus_release_dev(struct device *dev) if (i2sdev-out.dbdma) iounmap(i2sdev-out.dbdma); if (i2sdev-in.dbdma) iounmap(i2sdev-in.dbdma); for (i = aoa_resource_i2smmio; i = aoa_resource_rxdbdma; i++) - if (i2sdev-allocated_resource[i]) - release_and_free_resource(i2sdev-allocated_resource[i]); + release_and_free_resource(i2sdev-allocated_resource[i]); free_dbdma_descriptor_ring(i2sdev, i2sdev-out.dbdma_ring); free_dbdma_descriptor_ring(i2sdev, i2sdev-in.dbdma_ring); for (i = aoa_resource_i2smmio; i = aoa_resource_rxdbdma; i++) @@ -323,8 +322,7 @@ static int i2sbus_add_dev(struct macio_dev *macio, if (dev-out.dbdma) iounmap(dev-out.dbdma); if (dev-in.dbdma) iounmap(dev-in.dbdma); for (i=0;i3;i++) - if (dev-allocated_resource[i]) - release_and_free_resource(dev-allocated_resource[i]); + release_and_free_resource(dev-allocated_resource[i]); mutex_destroy(dev-lock); kfree(dev); return 0; -- 2.1.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 3/4] powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)
Hello Scott,
On 12/02/2014 06:32 PM, Scott Wood wrote:
On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
diff --git a/arch/powerpc/boot/dts/t4240rdb.dts
b/arch/powerpc/boot/dts/t4240rdb.dts
index 53761d4..431bf4e 100644
--- a/arch/powerpc/boot/dts/t4240rdb.dts
+++ b/arch/powerpc/boot/dts/t4240rdb.dts
@@ -69,10 +69,27 @@
device_type = memory;
};
+reserved-memory {
+#address-cells = 2;
+#size-cells = 2;
+ranges;
+
+bman_fbpr: bman-fbpr {
+compatible = fsl,bman-fbpr;
+alloc-ranges = 0 0 0x 0x;
+size = 0 0x100;
+alignment = 0 0x100;
+};
+};
Can't this be done at the SoC level rather than board level?
The size of the memory is not SoC specific. Among other things is
determined by the number of MACs that are pinned-out on the board
Cheers,
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