[PATCH v4 36/45] powerpc/mm: Don't be too strict with _etext alignment on PPC32
Similar to PPC64, accept to map RO data as ROX as a trade off between between security and memory usage. Having RO data executable is not a high risk as RO data can't be modified to forge an exploit. Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig | 26 -- arch/powerpc/kernel/vmlinux.lds.S | 3 +-- 2 files changed, 1 insertion(+), 28 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 1d4ef4f27dec..d147d379b1b9 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -778,32 +778,6 @@ config THREAD_SHIFT Used to define the stack size. The default is almost always what you want. Only change this if you know what you are doing. -config ETEXT_SHIFT_BOOL - bool "Set custom etext alignment" if STRICT_KERNEL_RWX && \ -(PPC_BOOK3S_32 || PPC_8xx) - depends on ADVANCED_OPTIONS - help - This option allows you to set the kernel end of text alignment. When - RAM is mapped by blocks, the alignment needs to fit the size and - number of possible blocks. The default should be OK for most configs. - - Say N here unless you know what you are doing. - -config ETEXT_SHIFT - int "_etext shift" if ETEXT_SHIFT_BOOL - range 17 28 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 - range 19 23 if STRICT_KERNEL_RWX && PPC_8xx - default 17 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 - default 19 if STRICT_KERNEL_RWX && PPC_8xx - default PPC_PAGE_SHIFT - help - On Book3S 32 (603+), IBATs are used to map kernel text. - Smaller is the alignment, greater is the number of necessary IBATs. - - On 8xx, large pages (512kb or 8M) are used to map kernel linear - memory. Aligning to 8M reduces TLB misses as only 8M pages are used - in that case. - config DATA_SHIFT_BOOL bool "Set custom data alignment" if STRICT_KERNEL_RWX && \ (PPC_BOOK3S_32 || PPC_8xx) diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 31a0f201fb6f..54f23205c2b9 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -15,7 +15,6 @@ #include #define STRICT_ALIGN_SIZE (1 << CONFIG_DATA_SHIFT) -#define ETEXT_ALIGN_SIZE (1 << CONFIG_ETEXT_SHIFT) ENTRY(_stext) @@ -116,7 +115,7 @@ SECTIONS } :text - . = ALIGN(ETEXT_ALIGN_SIZE); + . = ALIGN(PAGE_SIZE); _etext = .; PROVIDE32 (etext = .); -- 2.25.0
[PATCH v4 35/45] powerpc/8xx: Move DTLB perf handling closer.
Now that space have been freed next to the DTLB miss handler, it's associated DTLB perf handling can be brought back in the same place. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index fb5d17187772..9f3f7f3d03a7 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -344,6 +344,17 @@ DataStoreTLBMiss: rfi patch_site 0b, patch__dtlbmiss_exit_1 +#ifdef CONFIG_PERF_EVENTS + patch_site 0f, patch__dtlbmiss_perf +0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) + addir10, r10, 1 + stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) + mfspr r10, SPRN_DAR + mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r11, SPRN_M_TW + rfi +#endif + /* This is an instruction TLB error on the MPC8xx. This could be due * to many reasons, such as executing guarded memory or illegal instruction * addresses. There is nothing to do but handle a big time error fault. @@ -390,18 +401,6 @@ DARFixed:/* Return from dcbx instruction bug workaround */ /* 0x300 is DataAccess exception, needed by bad_page_fault() */ EXC_XFER_LITE(0x300, handle_page_fault) -/* Called from DataStoreTLBMiss when perf TLB misses events are activated */ -#ifdef CONFIG_PERF_EVENTS - patch_site 0f, patch__dtlbmiss_perf -0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) - addir10, r10, 1 - stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) - mfspr r10, SPRN_DAR - mtspr SPRN_DAR, r11 /* Tag DAR */ - mfspr r11, SPRN_M_TW - rfi -#endif - stack_overflow: vmap_stack_overflow_exception -- 2.25.0
[PATCH v4 34/45] powerpc/8xx: Remove now unused TLB miss functions
The code to setup linear and IMMR mapping via huge TLB entries is not called anymore. Remove it. Also remove the handling of removed code exits in the perf driver. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 8 +- arch/powerpc/kernel/head_8xx.S | 83 arch/powerpc/perf/8xx-pmu.c | 10 --- 3 files changed, 1 insertion(+), 100 deletions(-) diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h index 4d3ef3841b00..e82368838416 100644 --- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h @@ -240,13 +240,7 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) } /* patch sites */ -extern s32 patch__itlbmiss_linmem_top, patch__itlbmiss_linmem_top8; -extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp; -extern s32 patch__fixupdar_linmem_top; -extern s32 patch__dtlbmiss_romem_top, patch__dtlbmiss_romem_top8; - -extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2; -extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3; +extern s32 patch__itlbmiss_exit_1, patch__dtlbmiss_exit_1; extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf; #endif /* !__ASSEMBLY__ */ diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index d1546f379757..fb5d17187772 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -278,33 +278,6 @@ InstructionTLBMiss: rfi #endif -#ifndef CONFIG_PIN_TLB_TEXT -ITLBMissLinear: - mtcrr11 -#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23 - patch_site 0f, patch__itlbmiss_linmem_top8 - - mfspr r10, SPRN_SRR0 -0: subis r11, r10, (PAGE_OFFSET - 0x8000)@ha - rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K - ori r11, r11, MI_PS512K | MI_SVALID - rlwinm r10, r10, 0, 0x0ff8 /* 8xx supports max 256Mb RAM */ -#else - /* Set 8M byte page and mark it valid */ - li r11, MI_PS8MEG | MI_SVALID - rlwinm r10, r10, 20, 0x0f80/* 8xx supports max 256Mb RAM */ -#endif - mtspr SPRN_MI_TWC, r11 - ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ - _PAGE_PRESENT - mtspr SPRN_MI_RPN, r10/* Update TLB entry */ - -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 - rfi - patch_site 0b, patch__itlbmiss_exit_2 -#endif - . = 0x1200 DataStoreTLBMiss: mtspr SPRN_DAR, r10 @@ -371,62 +344,6 @@ DataStoreTLBMiss: rfi patch_site 0b, patch__dtlbmiss_exit_1 -DTLBMissIMMR: - mtcrr11 - /* Set 512k byte guarded page and mark it valid */ - li r10, MD_PS512K | MD_GUARDED | MD_SVALID - mtspr SPRN_MD_TWC, r10 - mfspr r10, SPRN_IMMR /* Get current IMMR */ - rlwinm r10, r10, 0, 0xfff8 /* Get 512 kbytes boundary */ - ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ - _PAGE_PRESENT | _PAGE_NO_CACHE - mtspr SPRN_MD_RPN, r10/* Update TLB entry */ - - li r11, RPN_PATTERN - -0: mfspr r10, SPRN_DAR - mtspr SPRN_DAR, r11 /* Tag DAR */ - mfspr r11, SPRN_M_TW - rfi - patch_site 0b, patch__dtlbmiss_exit_2 - -DTLBMissLinear: - mtcrr11 - rlwinm r10, r10, 20, 0x0f80/* 8xx supports max 256Mb RAM */ -#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23 - patch_site 0f, patch__dtlbmiss_romem_top8 - -0: subis r11, r10, (PAGE_OFFSET - 0x8000)@ha - rlwinm r11, r11, 0, 0xff80 - neg r10, r11 - or r11, r11, r10 - rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K - ori r11, r11, MI_PS512K | MI_SVALID - mfspr r10, SPRN_MD_EPN - rlwinm r10, r10, 0, 0x0ff8 /* 8xx supports max 256Mb RAM */ -#else - /* Set 8M byte page and mark it valid */ - li r11, MD_PS8MEG | MD_SVALID -#endif - mtspr SPRN_MD_TWC, r11 -#ifdef CONFIG_STRICT_KERNEL_RWX - patch_site 0f, patch__dtlbmiss_romem_top - -0: subis r11, r10, 0 - rlwimi r10, r11, 11, _PAGE_RO -#endif - ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ - _PAGE_PRESENT - mtspr SPRN_MD_RPN, r10/* Update TLB entry */ - - li r11, RPN_PATTERN - -0: mfspr r10, SPRN_DAR - mtspr SPRN_DAR, r11 /* Tag DAR */ - mfspr r11, SPRN_M_TW - rfi - patch_site 0b, patch__dtlbmiss_exit_3 - /* This is an instruction TLB error on the MPC8xx. This could be due * to many reasons, such as executing guarded memory or illegal instruction * addresses. There is nothing to do but handle a big time error fault.
[PATCH v4 32/45] powerpc/8xx: Always pin TLBs at startup.
At startup, map 32 Mbytes of memory through 4 pages of 8M,
and PIN them inconditionnaly. They need to be pinned because
KASAN is using page tables early and the TLBs might be
dynamically replaced otherwise.
Remove RSV4I flag after installing mappings unless
CONFIG_PIN_TLB_ is selected.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 31 +--
arch/powerpc/mm/nohash/8xx.c | 19 +--
2 files changed, 18 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index d607f4b53e0f..b0cceee6405c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -765,6 +765,14 @@ start_here:
mtspr SPRN_MD_RPN, r0
lis r0, (MD_TWAM | MD_RSV4I)@h
mtspr SPRN_MD_CTR, r0
+#endif
+#ifndef CONFIG_PIN_TLB_TEXT
+ li r0, 0
+ mtspr SPRN_MI_CTR, r0
+#endif
+#if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR)
+ lis r0, MD_TWAM@h
+ mtspr SPRN_MD_CTR, r0
#endif
tlbia /* Clear all TLB entries */
sync/* wait for tlbia/tlbie to finish */
@@ -802,10 +810,6 @@ initial_mmu:
mtspr SPRN_MD_CTR, r10/* remove PINNED DTLB entries */
tlbia /* Invalidate all TLB entries */
-#ifdef CONFIG_PIN_TLB_DATA
- orisr10, r10, MD_RSV4I@h
- mtspr SPRN_MD_CTR, r10/* Set data TLB control */
-#endif
lis r8, MI_APG_INIT@h /* Set protection modes */
ori r8, r8, MI_APG_INIT@l
@@ -814,33 +818,32 @@ initial_mmu:
ori r8, r8, MD_APG_INIT@l
mtspr SPRN_MD_AP, r8
- /* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
-#ifdef CONFIG_PIN_TLB_TEXT
+ /* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */
lis r8, MI_RSV4I@h
ori r8, r8, 0x1c00
-#endif
+ orisr12, r10, MD_RSV4I@h
+ ori r12, r12, 0x1c00
li r9, 4 /* up to 4 pages of 8M */
mtctr r9
lis r9, KERNELBASE@h/* Create vaddr for TLB */
li r10, MI_PS8MEG | MI_SVALID /* Set 8M byte page */
li r11, MI_BOOTINIT/* Create RPN for address 0 */
- lis r12, _einittext@h
- ori r12, r12, _einittext@l
1:
-#ifdef CONFIG_PIN_TLB_TEXT
mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
addir8, r8, 0x100
-#endif
-
ori r0, r9, MI_EVALID /* Mark it valid */
mtspr SPRN_MI_EPN, r0
mtspr SPRN_MI_TWC, r10
mtspr SPRN_MI_RPN, r11/* Store TLB entry */
+ mtspr SPRN_MD_CTR, r12
+ addir12, r12, 0x100
+ mtspr SPRN_MD_EPN, r0
+ mtspr SPRN_MD_TWC, r10
+ mtspr SPRN_MD_RPN, r11
addis r9, r9, 0x80
addis r11, r11, 0x80
- cmplcr0, r9, r12
- bdnzf gt, 1b
+ bdnz1b
/* Since the cache is enabled according to the information we
* just loaded into the TLB, invalidate and enable the caches here.
diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
index a9313aa6f1cd..2c480e35b426 100644
--- a/arch/powerpc/mm/nohash/8xx.c
+++ b/arch/powerpc/mm/nohash/8xx.c
@@ -62,23 +62,6 @@ unsigned long p_block_mapped(phys_addr_t pa)
*/
void __init MMU_init_hw(void)
{
- /* PIN up to the 3 first 8Mb after IMMR in DTLB table */
- if (IS_ENABLED(CONFIG_PIN_TLB_DATA)) {
- unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe00;
- unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY;
- int i = 28;
- unsigned long addr = 0;
- unsigned long mem = total_lowmem;
-
- for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) {
- mtspr(SPRN_MD_CTR, ctr | (i << 8));
- mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) |
MD_EVALID);
- mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID);
- mtspr(SPRN_MD_RPN, addr | flags | _PAGE_PRESENT);
- addr += LARGE_PAGE_SIZE_8M;
- mem -= LARGE_PAGE_SIZE_8M;
- }
- }
}
static bool immr_is_mapped __initdata;
@@ -226,7 +209,7 @@ void __init setup_initial_memory_limit(phys_addr_t
first_memblock_base,
BUG_ON(first_memblock_base != 0);
/* 8xx can only access 32MB at the moment */
- memblock_set_current_limit(min_t(u64, first_memblock_size, 0x0200));
+ memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M));
}
/*
--
2.25.0
[PATCH v4 33/45] powerpc/8xx: Drop special handling of Linear and IMMR mappings in I/D TLB handlers
Up to now, linear and IMMR mappings are managed via huge TLB entries
through specific code directly in TLB miss handlers. This implies
some patching of the TLB miss handlers at startup, and a lot of
dedicated code.
Remove all this specific dedicated code.
For now we are back to normal handling via standard 4k pages. In the
next patches, linear memory mapping and IMMR mapping will be managed
through huge pages.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 +
arch/powerpc/mm/nohash/8xx.c | 106 +
2 files changed, 3 insertions(+), 132 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b0cceee6405c..d1546f379757 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -207,31 +207,21 @@ InstructionTLBMiss:
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
INVALIDATE_ADJACENT_PAGES_CPU15(r10)
mtspr SPRN_MD_EPN, r10
- /* Only modules will cause ITLB Misses as we always
-* pin the first 8MB of kernel memory */
#ifdef ITLB_MISS_KERNEL
mfcrr11
-#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
+#if defined(SIMPLE_KERNEL_ADDRESS)
cmpicr0, r10, 0 /* Address >= 0x8000 */
#else
rlwinm r10, r10, 16, 0xfff8
cmpli cr0, r10, PAGE_OFFSET@h
-#ifndef CONFIG_PIN_TLB_TEXT
- /* It is assumed that kernel code fits into the first 32M */
-0: cmpli cr7, r10, (PAGE_OFFSET + 0x200)@h
- patch_site 0b, patch__itlbmiss_linmem_top
-#endif
#endif
#endif
mfspr r10, SPRN_M_TWB /* Get level 1 table */
#ifdef ITLB_MISS_KERNEL
-#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
+#if defined(SIMPLE_KERNEL_ADDRESS)
bge+3f
#else
blt+3f
-#endif
-#ifndef CONFIG_PIN_TLB_TEXT
- blt cr7, ITLBMissLinear
#endif
rlwinm r10, r10, 0, 20, 31
orisr10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
@@ -327,19 +317,9 @@ DataStoreTLBMiss:
mfspr r10, SPRN_MD_EPN
rlwinm r10, r10, 16, 0xfff8
cmpli cr0, r10, PAGE_OFFSET@h
-#ifndef CONFIG_PIN_TLB_IMMR
- cmpli cr6, r10, VIRT_IMMR_BASE@h
-#endif
-0: cmpli cr7, r10, (PAGE_OFFSET + 0x200)@h
- patch_site 0b, patch__dtlbmiss_linmem_top
mfspr r10, SPRN_M_TWB /* Get level 1 table */
blt+3f
-#ifndef CONFIG_PIN_TLB_IMMR
-0: beq-cr6, DTLBMissIMMR
- patch_site 0b, patch__dtlbmiss_immr_jmp
-#endif
- blt cr7, DTLBMissLinear
rlwinm r10, r10, 0, 20, 31
orisr10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
3:
@@ -571,14 +551,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
cmpli cr1, r11, PAGE_OFFSET@h
mfspr r11, SPRN_M_TWB /* Get level 1 table */
blt+cr1, 3f
- rlwinm r11, r10, 16, 0xfff8
-
-0: cmpli cr7, r11, (PAGE_OFFSET + 0x180)@h
- patch_site 0b, patch__fixupdar_linmem_top
/* create physical page address from effective address */
tophys(r11, r10)
- blt-cr7, 201f
mfspr r11, SPRN_M_TWB /* Get level 1 table */
rlwinm r11, r11, 0, 20, 31
orisr11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
index 2c480e35b426..b735482e1529 100644
--- a/arch/powerpc/mm/nohash/8xx.c
+++ b/arch/powerpc/mm/nohash/8xx.c
@@ -55,8 +55,6 @@ unsigned long p_block_mapped(phys_addr_t pa)
return 0;
}
-#define LARGE_PAGE_SIZE_8M (1<<23)
-
/*
* MMU_init_hw does the chip-specific initialization of the MMU hardware.
*/
@@ -81,122 +79,20 @@ void __init mmu_mapin_immr(void)
map_kernel_page(v + offset, p + offset, PAGE_KERNEL_NCG);
}
-static void mmu_patch_cmp_limit(s32 *site, unsigned long mapped)
-{
- modify_instruction_site(site, 0x, (unsigned long)__va(mapped) >>
16);
-}
-
-static void mmu_patch_addis(s32 *site, long simm)
-{
- unsigned int instr = *(unsigned int *)patch_site_addr(site);
-
- instr &= 0x;
- instr |= ((unsigned long)simm) >> 16;
- patch_instruction_site(site, ppc_inst(instr));
-}
-
-static void mmu_mapin_ram_chunk(unsigned long offset, unsigned long top,
pgprot_t prot)
-{
- unsigned long s = offset;
- unsigned long v = PAGE_OFFSET + s;
- phys_addr_t p = memstart_addr + s;
-
- for (; s < top; s += PAGE_SIZE) {
- map_kernel_page(v, p, prot);
- v += PAGE_SIZE;
- p += PAGE_SIZE;
- }
-}
-
unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
{
- unsigned long mapped;
-
mmu_mapin_immr();
- if (__map_without_ltlbs) {
- mapped = 0;
- if (!IS_ENABLED(CONFIG_PIN_TLB_IMMR))
- patch_instruction_site(&patch__dtlbmiss_immr_jmp,
ppc_inst(PPC_
[PATCH v4 31/45] powerpc/8xx: Don't set IMMR map anymore at boot
Only early debug requires IMMR to be mapped early.
No need to set it up and pin it in assembly. Map it
through page tables at udbg init when necessary.
If CONFIG_PIN_TLB_IMMR is selected, pin it once we
don't need the 32 Mb pinned RAM anymore.
Signed-off-by: Christophe Leroy
---
v2: Disable TLB reservation to modify entry 31
---
arch/powerpc/kernel/head_8xx.S | 39 +-
arch/powerpc/mm/mmu_decl.h | 4 +++
arch/powerpc/mm/nohash/8xx.c | 15 +---
arch/powerpc/platforms/8xx/Kconfig | 2 +-
arch/powerpc/sysdev/cpm_common.c | 2 ++
5 files changed, 35 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index c9e3d54e6a6f..d607f4b53e0f 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -749,6 +749,23 @@ start_here:
rfi
/* Load up the kernel context */
2:
+#ifdef CONFIG_PIN_TLB_IMMR
+ lis r0, MD_TWAM@h
+ orisr0, r0, 0x1f00
+ mtspr SPRN_MD_CTR, r0
+ LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
+ tlbie r0
+ mtspr SPRN_MD_EPN, r0
+ LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_PS512K | MD_GUARDED)
+ mtspr SPRN_MD_TWC, r0
+ mfspr r0, SPRN_IMMR
+ rlwinm r0, r0, 0, 0xfff8
+ ori r0, r0, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
+ _PAGE_NO_CACHE | _PAGE_PRESENT
+ mtspr SPRN_MD_RPN, r0
+ lis r0, (MD_TWAM | MD_RSV4I)@h
+ mtspr SPRN_MD_CTR, r0
+#endif
tlbia /* Clear all TLB entries */
sync/* wait for tlbia/tlbie to finish */
@@ -797,28 +814,6 @@ initial_mmu:
ori r8, r8, MD_APG_INIT@l
mtspr SPRN_MD_AP, r8
- /* Map a 512k page for the IMMR to get the processor
-* internal registers (among other things).
-*/
-#ifdef CONFIG_PIN_TLB_IMMR
- orisr10, r10, MD_RSV4I@h
- ori r10, r10, 0x1c00
- mtspr SPRN_MD_CTR, r10
-
- mfspr r9, 638 /* Get current IMMR */
- andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
-
- lis r8, VIRT_IMMR_BASE@h/* Create vaddr for TLB */
- ori r8, r8, MD_EVALID /* Mark it valid */
- mtspr SPRN_MD_EPN, r8
- li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
- ori r8, r8, MD_SVALID /* Make it valid */
- mtspr SPRN_MD_TWC, r8
- mr r8, r9 /* Create paddr for TLB */
- ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
- mtspr SPRN_MD_RPN, r8
-#endif
-
/* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
#ifdef CONFIG_PIN_TLB_TEXT
lis r8, MI_RSV4I@h
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 7097e07a209a..1b6d39e9baed 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -182,6 +182,10 @@ static inline void mmu_mark_initmem_nx(void) { }
static inline void mmu_mark_rodata_ro(void) { }
#endif
+#ifdef CONFIG_PPC_8xx
+void __init mmu_mapin_immr(void);
+#endif
+
#ifdef CONFIG_PPC_DEBUG_WX
void ptdump_check_wx(void);
#else
diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
index bda5290af751..a9313aa6f1cd 100644
--- a/arch/powerpc/mm/nohash/8xx.c
+++ b/arch/powerpc/mm/nohash/8xx.c
@@ -66,7 +66,7 @@ void __init MMU_init_hw(void)
if (IS_ENABLED(CONFIG_PIN_TLB_DATA)) {
unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe00;
unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY;
- int i = IS_ENABLED(CONFIG_PIN_TLB_IMMR) ? 29 : 28;
+ int i = 28;
unsigned long addr = 0;
unsigned long mem = total_lowmem;
@@ -81,12 +81,19 @@ void __init MMU_init_hw(void)
}
}
-static void __init mmu_mapin_immr(void)
+static bool immr_is_mapped __initdata;
+
+void __init mmu_mapin_immr(void)
{
unsigned long p = PHYS_IMMR_BASE;
unsigned long v = VIRT_IMMR_BASE;
int offset;
+ if (immr_is_mapped)
+ return;
+
+ immr_is_mapped = true;
+
for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE)
map_kernel_page(v + offset, p + offset, PAGE_KERNEL_NCG);
}
@@ -122,9 +129,10 @@ unsigned long __init mmu_mapin_ram(unsigned long base,
unsigned long top)
{
unsigned long mapped;
+ mmu_mapin_immr();
+
if (__map_without_ltlbs) {
mapped = 0;
- mmu_mapin_immr();
if (!IS_ENABLED(CONFIG_PIN_TLB_IMMR))
patch_instruction_site(&patch__dtlbmiss_immr_jmp,
ppc_inst(PPC_INST_NOP));
if (!IS_ENABLED(CONFIG_PIN_TLB_TEXT))
@@ -143,7 +151,6 @@ unsigned long __init mmu_mapin_ram(unsigned long base,
unsigned long top)
*/
mmu_mapin_ram_c
[PATCH v4 30/45] powerpc/8xx: Add function to set pinned TLBs
Pinned TLBs cannot be modified when the MMU is enabled.
Create a function to rewrite the pinned TLB entries with MMU off.
To set pinned TLB, we have to turn off MMU, disable pinning,
do a TLB flush (Either with tlbie and tlbia) then reprogam
the TLB entries, enable pinning and turn on MMU.
If using tlbie, it cleared entries in both instruction and data
TLB regardless whether pinning is disabled or not.
If using tlbia, it clears all entries of the TLB which has
disabled pinning.
To make it easy, just clear all entries in both TLBs, and
reprogram them.
The function takes two arguments, the top of the memory to
consider and whether data is RO under _sinittext.
When DEBUG_PAGEALLOC is set, the top is the end of kernel rodata.
Otherwise, that's the top of physical RAM.
Everything below _sinittext is set RX, over _sinittext that's RW.
Signed-off-by: Christophe Leroy
---
v2: Function rewritten to manage all entries at once.
---
arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 2 +
arch/powerpc/kernel/head_8xx.S | 103 +++
2 files changed, 105 insertions(+)
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index a092e6434bda..4d3ef3841b00 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -193,6 +193,8 @@
#include
+void mmu_pin_tlb(unsigned long top, bool readonly);
+
typedef struct {
unsigned int id;
unsigned int active;
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 423465b10c82..c9e3d54e6a6f 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -16,6 +16,7 @@
#include
#include
+#include
#include
#include
#include
@@ -866,6 +867,108 @@ initial_mmu:
mtspr SPRN_DER, r8
blr
+#ifdef CONFIG_PIN_TLB
+_GLOBAL(mmu_pin_tlb)
+ lis r9, (1f - PAGE_OFFSET)@h
+ ori r9, r9, (1f - PAGE_OFFSET)@l
+ mfmsr r10
+ mflrr11
+ li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
+ rlwinm r0, r10, 0, ~MSR_RI
+ rlwinm r0, r0, 0, ~MSR_EE
+ mtmsr r0
+ isync
+ .align 4
+ mtspr SPRN_SRR0, r9
+ mtspr SPRN_SRR1, r12
+ rfi
+1:
+ li r5, 0
+ lis r6, MD_TWAM@h
+ mtspr SPRN_MI_CTR, r5
+ mtspr SPRN_MD_CTR, r6
+ tlbia
+
+#ifdef CONFIG_PIN_TLB_TEXT
+ LOAD_REG_IMMEDIATE(r5, 28 << 8)
+ LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
+ LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG)
+ LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH |
_PAGE_PRESENT)
+ LOAD_REG_ADDR(r9, _sinittext)
+ li r0, 4
+ mtctr r0
+
+2: ori r0, r6, MI_EVALID
+ mtspr SPRN_MI_CTR, r5
+ mtspr SPRN_MI_EPN, r0
+ mtspr SPRN_MI_TWC, r7
+ mtspr SPRN_MI_RPN, r8
+ addir5, r5, 0x100
+ addis r6, r6, SZ_8M@h
+ addis r8, r8, SZ_8M@h
+ cmplw r6, r9
+ bdnzt lt, 2b
+ lis r0, MI_RSV4I@h
+ mtspr SPRN_MI_CTR, r0
+#endif
+ LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM)
+#ifdef CONFIG_PIN_TLB_DATA
+ LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
+ LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG)
+#ifdef CONFIG_PIN_TLB_IMMR
+ li r0, 3
+#else
+ li r0, 4
+#endif
+ mtctr r0
+ cmpwi r4, 0
+ beq 4f
+ LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH |
_PAGE_PRESENT)
+ LOAD_REG_ADDR(r9, _sinittext)
+
+2: ori r0, r6, MD_EVALID
+ mtspr SPRN_MD_CTR, r5
+ mtspr SPRN_MD_EPN, r0
+ mtspr SPRN_MD_TWC, r7
+ mtspr SPRN_MD_RPN, r8
+ addir5, r5, 0x100
+ addis r6, r6, SZ_8M@h
+ addis r8, r8, SZ_8M@h
+ cmplw r6, r9
+ bdnzt lt, 2b
+
+4: LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT)
+2: ori r0, r6, MD_EVALID
+ mtspr SPRN_MD_CTR, r5
+ mtspr SPRN_MD_EPN, r0
+ mtspr SPRN_MD_TWC, r7
+ mtspr SPRN_MD_RPN, r8
+ addir5, r5, 0x100
+ addis r6, r6, SZ_8M@h
+ addis r8, r8, SZ_8M@h
+ cmplw r6, r3
+ bdnzt lt, 2b
+#endif
+#ifdef CONFIG_PIN_TLB_IMMR
+ LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
+ LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED)
+ mfspr r8, SPRN_IMMR
+ rlwinm r8, r8, 0, 0xfff8
+ ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
+ _PAGE_NO_CACHE | _PAGE_PRESENT
+ mtspr SPRN_MD_CTR, r5
+ mtspr SPRN_MD_EPN, r0
+ mtspr SPRN_MD_TWC, r7
+ mtspr SPRN_MD_RPN, r8
+#endif
+#if defined(CONFIG_PIN_TLB_IMMR) || defined(CONFIG_PIN_TLB_DATA)
+ lis r0, (MD_RSV4I | MD_TWAM)@h
+ mtspr SPRN_MI_CTR, r0
+#endif
+ mtspr SPRN_SRR1, r10
+ mtspr SPRN_SRR0, r11
+ rfi
+#endif /
[PATCH v4 29/45] powerpc/8xx: Move PPC_PIN_TLB options into 8xx Kconfig
PPC_PIN_TLB options are dedicated to the 8xx, move them into the 8xx Kconfig. While we are at it, add some text to explain what it does. Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig | 20 --- arch/powerpc/platforms/8xx/Kconfig | 41 ++ 2 files changed, 41 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 30e2111ca15d..1d4ef4f27dec 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -1227,26 +1227,6 @@ config TASK_SIZE hex "Size of user task space" if TASK_SIZE_BOOL default "0x8000" if PPC_8xx default "0xc000" - -config PIN_TLB - bool "Pinned Kernel TLBs (860 ONLY)" - depends on ADVANCED_OPTIONS && PPC_8xx && \ - !DEBUG_PAGEALLOC && !STRICT_KERNEL_RWX - -config PIN_TLB_DATA - bool "Pinned TLB for DATA" - depends on PIN_TLB - default y - -config PIN_TLB_IMMR - bool "Pinned TLB for IMMR" - depends on PIN_TLB || PPC_EARLY_DEBUG_CPM - default y - -config PIN_TLB_TEXT - bool "Pinned TLB for TEXT" - depends on PIN_TLB - default y endmenu if PPC64 diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig index b37de62d7e7f..0d036cd868ef 100644 --- a/arch/powerpc/platforms/8xx/Kconfig +++ b/arch/powerpc/platforms/8xx/Kconfig @@ -162,4 +162,45 @@ config UCODE_PATCH default y depends on !NO_UCODE_PATCH +menu "8xx advanced setup" + depends on PPC_8xx + +config PIN_TLB + bool "Pinned Kernel TLBs" + depends on ADVANCED_OPTIONS && !DEBUG_PAGEALLOC && !STRICT_KERNEL_RWX + help + On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each + table 4 TLBs can be pinned. + + It reduces the amount of usable TLBs to 28 (ie by 12%). That's the + reason why we make it selectable. + + This option does nothing, it just activate the selection of what + to pin. + +config PIN_TLB_DATA + bool "Pinned TLB for DATA" + depends on PIN_TLB + default y + help + This pins the first 32 Mbytes of memory with 8M pages. + +config PIN_TLB_IMMR + bool "Pinned TLB for IMMR" + depends on PIN_TLB || PPC_EARLY_DEBUG_CPM + default y + help + This pins the IMMR area with a 512kbytes page. In case + CONFIG_PIN_TLB_DATA is also selected, it will reduce + CONFIG_PIN_TLB_DATA to 24 Mbytes. + +config PIN_TLB_TEXT + bool "Pinned TLB for TEXT" + depends on PIN_TLB + default y + help + This pins kernel text with 8M pages. + +endmenu + endmenu -- 2.25.0
[PATCH v4 28/45] powerpc/8xx: MM_SLICE is not needed anymore
As the 8xx now manages 512k pages in standard page tables,
it doesn't need CONFIG_PPC_MM_SLICES anymore.
Don't select it anymore and remove all related code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 64
arch/powerpc/include/asm/nohash/32/slice.h | 20 --
arch/powerpc/include/asm/slice.h | 2 -
arch/powerpc/platforms/Kconfig.cputype | 1 -
4 files changed, 87 deletions(-)
delete mode 100644 arch/powerpc/include/asm/nohash/32/slice.h
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index 26b7cee34dfe..a092e6434bda 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -176,12 +176,6 @@
*/
#define SPRN_M_TW 799
-#ifdef CONFIG_PPC_MM_SLICES
-#include
-#define SLICE_ARRAY_SIZE (1 << (32 - SLICE_LOW_SHIFT - 1))
-#define LOW_SLICE_ARRAY_SZ SLICE_ARRAY_SIZE
-#endif
-
#if defined(CONFIG_PPC_4K_PAGES)
#define mmu_virtual_psize MMU_PAGE_4K
#elif defined(CONFIG_PPC_16K_PAGES)
@@ -199,71 +193,13 @@
#include
-struct slice_mask {
- u64 low_slices;
- DECLARE_BITMAP(high_slices, 0);
-};
-
typedef struct {
unsigned int id;
unsigned int active;
unsigned long vdso_base;
-#ifdef CONFIG_PPC_MM_SLICES
- u16 user_psize; /* page size index */
- unsigned char low_slices_psize[SLICE_ARRAY_SIZE];
- unsigned char high_slices_psize[0];
- unsigned long slb_addr_limit;
- struct slice_mask mask_base_psize; /* 4k or 16k */
- struct slice_mask mask_512k;
- struct slice_mask mask_8m;
-#endif
void *pte_frag;
} mm_context_t;
-#ifdef CONFIG_PPC_MM_SLICES
-static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
-{
- return ctx->user_psize;
-}
-
-static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
-{
- ctx->user_psize = user_psize;
-}
-
-static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
-{
- return ctx->low_slices_psize;
-}
-
-static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
-{
- return ctx->high_slices_psize;
-}
-
-static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
-{
- return ctx->slb_addr_limit;
-}
-
-static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long
limit)
-{
- ctx->slb_addr_limit = limit;
-}
-
-static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int
psize)
-{
- if (psize == MMU_PAGE_512K)
- return &ctx->mask_512k;
- if (psize == MMU_PAGE_8M)
- return &ctx->mask_8m;
-
- BUG_ON(psize != mmu_virtual_psize);
-
- return &ctx->mask_base_psize;
-}
-#endif /* CONFIG_PPC_MM_SLICE */
-
#define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff8)
#define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))
diff --git a/arch/powerpc/include/asm/nohash/32/slice.h
b/arch/powerpc/include/asm/nohash/32/slice.h
deleted file mode 100644
index 39eb0154ae2d..
--- a/arch/powerpc/include/asm/nohash/32/slice.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_POWERPC_NOHASH_32_SLICE_H
-#define _ASM_POWERPC_NOHASH_32_SLICE_H
-
-#ifdef CONFIG_PPC_MM_SLICES
-
-#define SLICE_LOW_SHIFT26 /* 64 slices */
-#define SLICE_LOW_TOP (0x1ull)
-#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
-#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
-
-#define SLICE_HIGH_SHIFT 0
-#define SLICE_NUM_HIGH 0ul
-#define GET_HIGH_SLICE_INDEX(addr) (addr & 0)
-
-#define SLB_ADDR_LIMIT_DEFAULT DEFAULT_MAP_WINDOW
-
-#endif /* CONFIG_PPC_MM_SLICES */
-
-#endif /* _ASM_POWERPC_NOHASH_32_SLICE_H */
diff --git a/arch/powerpc/include/asm/slice.h b/arch/powerpc/include/asm/slice.h
index c6f466f4c241..0bdd9c62eca0 100644
--- a/arch/powerpc/include/asm/slice.h
+++ b/arch/powerpc/include/asm/slice.h
@@ -4,8 +4,6 @@
#ifdef CONFIG_PPC_BOOK3S_64
#include
-#elif defined(CONFIG_PPC_MMU_NOHASH_32)
-#include
#endif
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index 27a81c291be8..5774a55a9c58 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -55,7 +55,6 @@ config PPC_8xx
select SYS_SUPPORTS_HUGETLBFS
select PPC_HAVE_KUEP
select PPC_HAVE_KUAP
- select PPC_MM_SLICES if HUGETLB_PAGE
select HAVE_ARCH_VMAP_STACK
config 40x
--
2.25.0
[PATCH v4 27/45] powerpc/8xx: Only 8M pages are hugepte pages now
512k pages are now standard pages, so only 8M pages
are hugepte.
No more handling of normal page tables through hugepd allocation
and freeing, and hugepte helpers can also be simplified.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h | 7 +++
arch/powerpc/mm/hugetlbpage.c| 16 +++-
2 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
b/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
index 785437323576..1c7d4693a78e 100644
--- a/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
@@ -13,13 +13,13 @@ static inline pte_t *hugepd_page(hugepd_t hpd)
static inline unsigned int hugepd_shift(hugepd_t hpd)
{
- return ((hpd_val(hpd) & _PMD_PAGE_MASK) >> 1) + 17;
+ return PAGE_SHIFT_8M;
}
static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr,
unsigned int pdshift)
{
- unsigned long idx = (addr & ((1UL << pdshift) - 1)) >> PAGE_SHIFT;
+ unsigned long idx = (addr & (SZ_4M - 1)) >> PAGE_SHIFT;
return hugepd_page(hpd) + idx;
}
@@ -32,8 +32,7 @@ static inline void flush_hugetlb_page(struct vm_area_struct
*vma,
static inline void hugepd_populate(hugepd_t *hpdp, pte_t *new, unsigned int
pshift)
{
- *hpdp = __hugepd(__pa(new) | _PMD_USER | _PMD_PRESENT |
-(pshift == PAGE_SHIFT_8M ? _PMD_PAGE_8M :
_PMD_PAGE_512K));
+ *hpdp = __hugepd(__pa(new) | _PMD_USER | _PMD_PRESENT | _PMD_PAGE_8M);
}
static inline int check_and_get_huge_psize(int shift)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 38bad839e608..cfacd364c7aa 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -54,24 +54,17 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t
*hpdp,
if (pshift >= pdshift) {
cachep = PGT_CACHE(PTE_T_ORDER);
num_hugepd = 1 << (pshift - pdshift);
- new = NULL;
- } else if (IS_ENABLED(CONFIG_PPC_8xx)) {
- cachep = NULL;
- num_hugepd = 1;
- new = pte_alloc_one(mm);
} else {
cachep = PGT_CACHE(pdshift - pshift);
num_hugepd = 1;
- new = NULL;
}
- if (!cachep && !new) {
+ if (!cachep) {
WARN_ONCE(1, "No page table cache created for hugetlb tables");
return -ENOMEM;
}
- if (cachep)
- new = kmem_cache_alloc(cachep, pgtable_gfp_flags(mm,
GFP_KERNEL));
+ new = kmem_cache_alloc(cachep, pgtable_gfp_flags(mm, GFP_KERNEL));
BUG_ON(pshift > HUGEPD_SHIFT_MASK);
BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
@@ -102,10 +95,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t
*hpdp,
if (i < num_hugepd) {
for (i = i - 1 ; i >= 0; i--, hpdp--)
*hpdp = __hugepd(0);
- if (cachep)
- kmem_cache_free(cachep, new);
- else
- pte_free(mm, new);
+ kmem_cache_free(cachep, new);
} else {
kmemleak_ignore(new);
}
--
2.25.0
[PATCH v4 26/45] powerpc/8xx: Manage 512k huge pages as standard pages.
At the time being, 512k huge pages are handled through hugepd page
tables. The PMD entry is flagged as a hugepd pointer and it
means that only 512k hugepages can be managed in that 4M block.
However, the hugepd table has the same size as a normal page
table, and 512k entries can therefore be nested with normal pages.
On the 8xx, TLB loading is performed by software and allthough the
page tables are organised to match the L1 and L2 level defined by
the HW, all TLB entries have both L1 and L2 independent entries.
It means that even if two TLB entries are associated with the same
PMD entry, they can be loaded with different values in L1 part.
The L1 entry contains the page size (PS field):
- 00 for 4k and 16 pages
- 01 for 512k pages
- 11 for 8M pages
By adding a flag for hugepages in the PTE (_PAGE_HUGE) and copying it
into the lower bit of PS, we can then manage 512k pages with normal
page tables:
- PMD entry has PS=11 for 8M pages
- PMD entry has PS=00 for other pages.
As a PMD entry covers 4M areas, a PMD will either point to a hugepd
table having a single entry to an 8M page, or the PMD will point to
a standard page table which will have either entries to 4k or 16k or
512k pages. For 512k pages, as the L1 entry will not know it is a
512k page before the PTE is read, there will be 128 entries in the
PTE as if it was 4k pages. But when loading the TLB, it will be
flagged as a 512k page.
Note that we can't use pmd_ptr() in asm/nohash/32/pgtable.h because
it is not defined yet.
In ITLB miss, we keep the possibility to opt it out as when kernel
text is pinned and no user hugepages are used, we can save several
instruction by not using r11.
In DTLB miss, that's just one instruction so it's not worth bothering
with it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 10 ++---
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 4 +++-
arch/powerpc/include/asm/nohash/pgtable.h| 2 +-
arch/powerpc/kernel/head_8xx.S | 12 +--
arch/powerpc/mm/hugetlbpage.c| 22 +---
arch/powerpc/mm/pgtable.c| 10 -
6 files changed, 44 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 9a287a95acad..717f995d21b8 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -229,8 +229,9 @@ static inline void pmd_clear(pmd_t *pmdp)
* those implementations.
*
* On the 8xx, the page tables are a bit special. For 16k pages, we have
- * 4 identical entries. For other page sizes, we have a single entry in the
- * table.
+ * 4 identical entries. For 512k pages, we have 128 entries as if it was
+ * 4k pages, but they are flagged as 512k pages for the hardware.
+ * For other page sizes, we have a single entry in the table.
*/
#ifdef CONFIG_PPC_8xx
static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr,
pte_t *p,
@@ -240,13 +241,16 @@ static inline pte_basic_t pte_update(struct mm_struct
*mm, unsigned long addr, p
pte_basic_t old = pte_val(*p);
pte_basic_t new = (old & ~(pte_basic_t)clr) | set;
int num, i;
+ pmd_t *pmd = pmd_offset(pud_offset(pgd_offset(mm, addr), addr), addr);
if (!huge)
num = PAGE_SIZE / SZ_4K;
+ else if ((pmd_val(*pmd) & _PMD_PAGE_MASK) != _PMD_PAGE_8M)
+ num = SZ_512K / SZ_4K;
else
num = 1;
- for (i = 0; i < num; i++, entry++)
+ for (i = 0; i < num; i++, entry++, new += SZ_4K)
*entry = new;
return old;
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
index c9e4b2d90f65..66f403a7da44 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
@@ -46,6 +46,8 @@
#define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
#define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
+#define _PAGE_HUGE 0x0800 /* Copied to L1 PS bit 29 */
+
/* cache related flags non existing on 8xx */
#define _PAGE_COHERENT 0
#define _PAGE_WRITETHRU0
@@ -128,7 +130,7 @@ static inline pte_t pte_mkuser(pte_t pte)
static inline pte_t pte_mkhuge(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_SPS);
+ return __pte(pte_val(pte) | _PAGE_SPS | _PAGE_HUGE);
}
#define pte_mkhuge pte_mkhuge
diff --git a/arch/powerpc/include/asm/nohash/pgtable.h
b/arch/powerpc/include/asm/nohash/pgtable.h
index 7fed9dc0f147..f27c967d9269 100644
--- a/arch/powerpc/include/asm/nohash/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/pgtable.h
@@ -267,7 +267,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file,
unsigned long pfn,
static inline int hugepd_ok(hugepd_t hpd)
{
#ifdef CONFIG_PPC_8xx
- return ((hpd_val(hpd) & 0x4) != 0);
+ return ((hpd_val(hpd)
[PATCH v4 25/45] powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.
Prepare ITLB handler to handle _PAGE_HUGE when CONFIG_HUGETLBFS is enabled. This means that the L1 entry has to be kept in r11 until L2 entry is read, in order to insert _PAGE_HUGE into it. Also move pgd_offset helpers before pte_update() as they will be needed there in next patch. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/nohash/32/pgtable.h | 13 ++--- arch/powerpc/kernel/head_8xx.S | 15 +-- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h index ff78bf25f832..9a287a95acad 100644 --- a/arch/powerpc/include/asm/nohash/32/pgtable.h +++ b/arch/powerpc/include/asm/nohash/32/pgtable.h @@ -206,6 +206,12 @@ static inline void pmd_clear(pmd_t *pmdp) } +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* to find an entry in a page-table-directory */ +#define pgd_index(address) ((address) >> PGDIR_SHIFT) +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) /* * PTE updates. This function is called whenever an existing @@ -348,13 +354,6 @@ static inline int pte_young(pte_t pte) pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT)) #endif -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* to find an entry in a page-table-directory */ -#define pgd_index(address) ((address) >> PGDIR_SHIFT) -#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) - /* Find an entry in the third-level page table.. */ #define pte_index(address) \ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 905205c79a25..adad8baadcf5 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -196,7 +196,7 @@ SystemCall: InstructionTLBMiss: mtspr SPRN_SPRG_SCRATCH0, r10 -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) +#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS) mtspr SPRN_SPRG_SCRATCH1, r11 #endif @@ -235,16 +235,19 @@ InstructionTLBMiss: rlwinm r10, r10, 0, 20, 31 orisr10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha 3: + mtcrr11 #endif +#ifdef CONFIG_HUGETLBFS + lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10)/* Get level 1 entry */ + mtspr SPRN_MI_TWC, r11/* Set segment attributes */ + mtspr SPRN_MD_TWC, r11 +#else lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10)/* Get level 1 entry */ mtspr SPRN_MI_TWC, r10/* Set segment attributes */ - mtspr SPRN_MD_TWC, r10 +#endif mfspr r10, SPRN_MD_TWC lwz r10, 0(r10) /* Get the pte */ -#ifdef ITLB_MISS_KERNEL - mtcrr11 -#endif #ifdef CONFIG_SWAP rlwinm r11, r10, 32-5, _PAGE_PRESENT and r11, r11, r10 @@ -263,7 +266,7 @@ InstructionTLBMiss: /* Restore registers */ 0: mfspr r10, SPRN_SPRG_SCRATCH0 -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) +#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS) mfspr r11, SPRN_SPRG_SCRATCH1 #endif rfi -- 2.25.0
[PATCH v4 24/45] powerpc/8xx: Drop CONFIG_8xx_COPYBACK option
CONFIG_8xx_COPYBACK was there to help disabling copyback cache mode for debuging hardware. But nobody will design new boards with 8xx now. All 8xx platforms select it, so make it the default and remove the option. Also remove the Mx_RESETVAL values which are pretty useless and hide the real value while reading code. Signed-off-by: Christophe Leroy --- arch/powerpc/configs/adder875_defconfig | 1 - arch/powerpc/configs/ep88xc_defconfig| 1 - arch/powerpc/configs/mpc866_ads_defconfig| 1 - arch/powerpc/configs/mpc885_ads_defconfig| 1 - arch/powerpc/configs/tqm8xx_defconfig| 1 - arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 2 -- arch/powerpc/kernel/head_8xx.S | 15 +-- arch/powerpc/platforms/8xx/Kconfig | 9 - 8 files changed, 1 insertion(+), 30 deletions(-) diff --git a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs/adder875_defconfig index f55e23cb176c..5326bc739279 100644 --- a/arch/powerpc/configs/adder875_defconfig +++ b/arch/powerpc/configs/adder875_defconfig @@ -10,7 +10,6 @@ CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PPC_ADDER875=y -CONFIG_8xx_COPYBACK=y CONFIG_GEN_RTC=y CONFIG_HZ_1000=y # CONFIG_SECCOMP is not set diff --git a/arch/powerpc/configs/ep88xc_defconfig b/arch/powerpc/configs/ep88xc_defconfig index 0e2e5e81a359..f5c3e72da719 100644 --- a/arch/powerpc/configs/ep88xc_defconfig +++ b/arch/powerpc/configs/ep88xc_defconfig @@ -12,7 +12,6 @@ CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_PPC_EP88XC=y -CONFIG_8xx_COPYBACK=y CONFIG_GEN_RTC=y CONFIG_HZ_100=y # CONFIG_SECCOMP is not set diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig index 5320735395e7..5c56d36cdfc5 100644 --- a/arch/powerpc/configs/mpc866_ads_defconfig +++ b/arch/powerpc/configs/mpc866_ads_defconfig @@ -12,7 +12,6 @@ CONFIG_EXPERT=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_MPC86XADS=y -CONFIG_8xx_COPYBACK=y CONFIG_GEN_RTC=y CONFIG_HZ_1000=y CONFIG_MATH_EMULATION=y diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig index 82a008c04eae..949ff9ccda5e 100644 --- a/arch/powerpc/configs/mpc885_ads_defconfig +++ b/arch/powerpc/configs/mpc885_ads_defconfig @@ -11,7 +11,6 @@ CONFIG_EXPERT=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y -CONFIG_8xx_COPYBACK=y CONFIG_GEN_RTC=y CONFIG_HZ_100=y # CONFIG_SECCOMP is not set diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig index eda8bfb2d0a3..77857d513022 100644 --- a/arch/powerpc/configs/tqm8xx_defconfig +++ b/arch/powerpc/configs/tqm8xx_defconfig @@ -15,7 +15,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_TQM8XX=y -CONFIG_8xx_COPYBACK=y # CONFIG_8xx_CPU15 is not set CONFIG_GEN_RTC=y CONFIG_HZ_100=y diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h index 76af5b0cb16e..26b7cee34dfe 100644 --- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h @@ -19,7 +19,6 @@ #define MI_RSV4I 0x0800 /* Reserve 4 TLB entries */ #define MI_PPCS0x0200 /* Use MI_RPN prob/priv state */ #define MI_IDXMASK 0x1f00 /* TLB index to be loaded */ -#define MI_RESETVAL0x /* Value of register at reset */ /* These are the Ks and Kp from the PowerPC books. For proper operation, * Ks = 0, Kp = 1. @@ -95,7 +94,6 @@ #define MD_TWAM0x0400 /* Use 4K page hardware assist */ #define MD_PPCS0x0200 /* Use MI_RPN prob/priv state */ #define MD_IDXMASK 0x1f00 /* TLB index to be loaded */ -#define MD_RESETVAL0x0400 /* Value of register at reset */ #define SPRN_M_CASID 793 /* Address space ID (context) to match */ #define MC_ASIDMASK0x000f /* Bits used for ASID value */ diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 073a651787df..905205c79a25 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -779,10 +779,7 @@ start_here: initial_mmu: li r8, 0 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ - lis r10, MD_RESETVAL@h -#ifndef CONFIG_8xx_COPYBACK - orisr10, r10, MD_WTDEF@h -#endif + lis r10, MD_TWAM@h mtspr SPRN_MD_CTR, r10/* remove PINNED DTLB entries */ tlbia /* Invalidate all TLB entries */ @@ -857,17 +854,7 @@ initial_mmu: mtspr SPRN_DC_CST, r8 lis r8, IDC_ENABLE@h mtspr SPRN_IC_CST, r8 -#ifdef CONFIG_8xx_COPYBACK - mtspr SPRN_DC_CST, r8 -#else - /* For a
[PATCH v4 23/45] powerpc/mm: Reduce hugepd size for 8M hugepages on 8xx
Commit 55c8fc3f4930 ("powerpc/8xx: reintroduce 16K pages with HW
assistance") redefined pte_t as a struct of 4 pte_basic_t, because
in 16K pages mode there are four identical entries in the page table.
But hugepd entries for 8M pages require only one entry of size
pte_basic_t. So there is no point in creating a cache for 4 entries
page tables.
Calculate PTE_T_ORDER using the size of pte_basic_t instead of pte_t.
Define specific huge_pte helpers (set_huge_pte_at(), huge_pte_clear(),
huge_ptep_set_wrprotect()) to write the pte in a single entry instead
of using set_pte_at() which writes 4 identical entries in 16k pages
mode. Also make sure that __ptep_set_access_flags() properly handle
the huge_pte case.
Define set_pte_filter() inline otherwise GCC doesn't inline it anymore
because it is now used twice, and that gives a pretty suboptimal code
because of pte_t being a struct of 4 entries.
Those functions are also used for 512k pages which only require one
entry as well allthough replicating it four times was harmless as 512k
pages entries are spread every 128 bytes in the table.
Signed-off-by: Christophe Leroy
---
.../include/asm/nohash/32/hugetlb-8xx.h | 20 ++
arch/powerpc/include/asm/nohash/32/pgtable.h | 3 ++-
arch/powerpc/mm/hugetlbpage.c | 3 ++-
arch/powerpc/mm/pgtable.c | 26 ---
4 files changed, 46 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
b/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
index a46616937d20..785437323576 100644
--- a/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h
@@ -41,4 +41,24 @@ static inline int check_and_get_huge_psize(int shift)
return shift_to_mmu_psize(shift);
}
+#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
pte_t pte);
+
+#define __HAVE_ARCH_HUGE_PTE_CLEAR
+static inline void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, unsigned long sz)
+{
+ pte_update(mm, addr, ptep, ~0UL, 0, 1);
+}
+
+#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ unsigned long clr = ~pte_val(pte_wrprotect(__pte(~0)));
+ unsigned long set = pte_val(pte_wrprotect(__pte(0)));
+
+ pte_update(mm, addr, ptep, clr, set, 1);
+}
+
#endif /* _ASM_POWERPC_NOHASH_32_HUGETLB_8XX_H */
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 5fb3f6798e22..ff78bf25f832 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -314,8 +314,9 @@ static inline void __ptep_set_access_flags(struct
vm_area_struct *vma,
pte_t pte_clr =
pte_mkyoung(pte_mkdirty(pte_mkwrite(pte_mkexec(__pte(~0);
unsigned long set = pte_val(entry) & pte_val(pte_set);
unsigned long clr = ~pte_val(entry) & ~pte_val(pte_clr);
+ int huge = psize > mmu_virtual_psize ? 1 : 0;
- pte_update(vma->vm_mm, address, ptep, clr, set, 0);
+ pte_update(vma->vm_mm, address, ptep, clr, set, huge);
flush_tlb_page(vma, address);
}
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index d06efb946c7d..521929a371af 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -30,7 +30,8 @@ bool hugetlb_disabled = false;
#define hugepd_none(hpd) (hpd_val(hpd) == 0)
-#define PTE_T_ORDER(__builtin_ffs(sizeof(pte_t)) -
__builtin_ffs(sizeof(void *)))
+#define PTE_T_ORDER(__builtin_ffs(sizeof(pte_basic_t)) - \
+__builtin_ffs(sizeof(void *)))
pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr, unsigned long
sz)
{
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index e3759b69f81b..214a5f4beb6c 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -100,7 +100,7 @@ static pte_t set_pte_filter_hash(pte_t pte) { return pte; }
* as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
* instead we "filter out" the exec permission for non clean pages.
*/
-static pte_t set_pte_filter(pte_t pte)
+static inline pte_t set_pte_filter(pte_t pte)
{
struct page *pg;
@@ -249,16 +249,34 @@ int huge_ptep_set_access_flags(struct vm_area_struct *vma,
#else
/*
-* Not used on non book3s64 platforms. But 8xx
-* can possibly use tsize derived from hstate.
+* Not used on non book3s64 platforms.
+* 8xx compares it with mmu_virtual_psize to
+* know if it is a huge page or not.
*/
- psize = 0;
+ psize = MMU_PAGE_COUNT;
#endif
[PATCH v4 22/45] powerpc/mm: Create a dedicated pte_update() for 8xx
pte_update() is a bit special for the 8xx. At the time
being, that's an #ifdef inside the nohash/32 pte_update().
As we are going to make it even more special in the coming
patches, create a dedicated version for pte_update() for 8xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 29 +---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 474dd1db065f..5fb3f6798e22 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -221,7 +221,31 @@ static inline void pmd_clear(pmd_t *pmdp)
* that an executable user mapping was modified, which is needed
* to properly flush the virtually tagged instruction cache of
* those implementations.
+ *
+ * On the 8xx, the page tables are a bit special. For 16k pages, we have
+ * 4 identical entries. For other page sizes, we have a single entry in the
+ * table.
*/
+#ifdef CONFIG_PPC_8xx
+static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr,
pte_t *p,
+unsigned long clr, unsigned long set, int
huge)
+{
+ pte_basic_t *entry = &p->pte;
+ pte_basic_t old = pte_val(*p);
+ pte_basic_t new = (old & ~(pte_basic_t)clr) | set;
+ int num, i;
+
+ if (!huge)
+ num = PAGE_SIZE / SZ_4K;
+ else
+ num = 1;
+
+ for (i = 0; i < num; i++, entry++)
+ *entry = new;
+
+ return old;
+}
+#else
static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr,
pte_t *p,
unsigned long clr, unsigned long set, int
huge)
{
@@ -242,11 +266,7 @@ static inline pte_basic_t pte_update(struct mm_struct *mm,
unsigned long addr, p
pte_basic_t old = pte_val(*p);
pte_basic_t new = (old & ~(pte_basic_t)clr) | set;
-#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
- p->pte = p->pte1 = p->pte2 = p->pte3 = new;
-#else
*p = __pte(new);
-#endif
#endif /* !PTE_ATOMIC_UPDATES */
#ifdef CONFIG_44x
@@ -255,6 +275,7 @@ static inline pte_basic_t pte_update(struct mm_struct *mm,
unsigned long addr, p
#endif
return old;
}
+#endif
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
--
2.25.0
[PATCH v4 21/45] powerpc/mm: Standardise pte_update() prototype between PPC32 and PPC64
PPC64 takes 3 additional parameters compared to PPC32:
- mm
- address
- huge
These 3 parameters will be needed in order to perform different
action depending on the page size on the 8xx.
Make pte_update() prototype identical for PPC32 and PPC64.
This allows dropping an #ifdef in huge_ptep_get_and_clear().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 15 ---
arch/powerpc/include/asm/hugetlb.h | 4
arch/powerpc/include/asm/nohash/32/pgtable.h | 13 +++--
3 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h
b/arch/powerpc/include/asm/book3s/32/pgtable.h
index 25c59511fcab..8a091d125f2d 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -218,7 +218,7 @@ int map_kernel_page(unsigned long va, phys_addr_t pa,
pgprot_t prot);
*/
#define pte_clear(mm, addr, ptep) \
- do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
+ do { pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) & _PMD_BAD)
@@ -254,7 +254,8 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t
*ptep,
* when using atomic updates, only the low part of the PTE is
* accessed atomically.
*/
-static inline pte_basic_t pte_update(pte_t *p, unsigned long clr, unsigned
long set)
+static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr,
pte_t *p,
+unsigned long clr, unsigned long set, int
huge)
{
pte_basic_t old;
unsigned long tmp;
@@ -292,7 +293,7 @@ static inline int __ptep_test_and_clear_young(struct
mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
unsigned long old;
- old = pte_update(ptep, _PAGE_ACCESSED, 0);
+ old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
if (old & _PAGE_HASHPTE) {
unsigned long ptephys = __pa(ptep) & PAGE_MASK;
flush_hash_pages(mm->context.id, addr, ptephys, 1);
@@ -306,14 +307,14 @@ static inline int __ptep_test_and_clear_young(struct
mm_struct *mm,
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long
addr,
pte_t *ptep)
{
- return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
+ return __pte(pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0));
}
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
pte_t *ptep)
{
- pte_update(ptep, _PAGE_RW, 0);
+ pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
}
static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
@@ -324,7 +325,7 @@ static inline void __ptep_set_access_flags(struct
vm_area_struct *vma,
unsigned long set = pte_val(entry) &
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
- pte_update(ptep, 0, set);
+ pte_update(vma->vm_mm, address, ptep, 0, set, 0);
flush_tlb_page(vma, address);
}
@@ -522,7 +523,7 @@ static inline void __set_pte_at(struct mm_struct *mm,
unsigned long addr,
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
| (pte_val(pte) & ~_PAGE_HASHPTE));
else
- pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
+ pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, pte_val(pte), 0);
#elif defined(CONFIG_PTE_64BIT)
/* Second case is 32-bit with 64-bit PTE. In this case, we
diff --git a/arch/powerpc/include/asm/hugetlb.h
b/arch/powerpc/include/asm/hugetlb.h
index bd6504c28c2f..e4276af034e9 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -40,11 +40,7 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned
long addr,
static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
-#ifdef CONFIG_PPC64
return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1));
-#else
- return __pte(pte_update(ptep, ~0UL, 0));
-#endif
}
#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index e963e6880d7c..474dd1db065f 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -166,7 +166,7 @@ int map_kernel_page(unsigned long va, phys_addr_t pa,
pgprot_t prot);
#ifndef __ASSEMBLY__
#define pte_clear(mm, addr, ptep) \
- do { pte_update(ptep, ~0, 0); } while (0)
+ do { pte_update(mm, addr, ptep, ~0, 0, 0); } while (0)
#ifndef pte_mkwrite
static inline pte_t pte_mkwrite(pte_t pte)
@@ -222,7 +222,8 @@ static inline void p
[PATCH v4 20/45] powerpc/mm: Standardise __ptep_test_and_clear_young() params between PPC32 and PPC64
On PPC32, __ptep_test_and_clear_young() takes the mm->context.id
In preparation of standardising pte_update() params between PPC32 and
PPC64, __ptep_test_and_clear_young() need mm instead of mm->context.id
Replace context param by mm.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 7 ---
arch/powerpc/include/asm/nohash/32/pgtable.h | 5 +++--
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h
b/arch/powerpc/include/asm/book3s/32/pgtable.h
index d2fc324cdf07..25c59511fcab 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -288,18 +288,19 @@ static inline pte_basic_t pte_update(pte_t *p, unsigned
long clr, unsigned long
* for our hash-based implementation, we fix that up here.
*/
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-static inline int __ptep_test_and_clear_young(unsigned int context, unsigned
long addr, pte_t *ptep)
+static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
{
unsigned long old;
old = pte_update(ptep, _PAGE_ACCESSED, 0);
if (old & _PAGE_HASHPTE) {
unsigned long ptephys = __pa(ptep) & PAGE_MASK;
- flush_hash_pages(context, addr, ptephys, 1);
+ flush_hash_pages(mm->context.id, addr, ptephys, 1);
}
return (old & _PAGE_ACCESSED) != 0;
}
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
- __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
+ __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long
addr,
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index db17f50d6ac3..e963e6880d7c 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -256,14 +256,15 @@ static inline pte_basic_t pte_update(pte_t *p, unsigned
long clr, unsigned long
}
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-static inline int __ptep_test_and_clear_young(unsigned int context, unsigned
long addr, pte_t *ptep)
+static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
{
unsigned long old;
old = pte_update(ptep, _PAGE_ACCESSED, 0);
return (old & _PAGE_ACCESSED) != 0;
}
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
- __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
+ __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long
addr,
--
2.25.0
[PATCH v4 19/45] powerpc/mm: Refactor pte_update() on book3s/32
When CONFIG_PTE_64BIT is set, pte_update() operates on
'unsigned long long'
When CONFIG_PTE_64BIT is not set, pte_update() operates on
'unsigned long'
In asm/page.h, we have pte_basic_t which is 'unsigned long long'
when CONFIG_PTE_64BIT is set and 'unsigned long' otherwise.
Refactor pte_update() using pte_basic_t.
While we are at it, drop the comment on 44x which is not applicable
to book3s version of pte_update().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 58 +++-
1 file changed, 20 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h
b/arch/powerpc/include/asm/book3s/32/pgtable.h
index 0d4bccb4b9f2..d2fc324cdf07 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -253,53 +253,35 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t
*ptep,
* and the PTE may be either 32 or 64 bit wide. In the later case,
* when using atomic updates, only the low part of the PTE is
* accessed atomically.
- *
- * In addition, on 44x, we also maintain a global flag indicating
- * that an executable user mapping was modified, which is needed
- * to properly flush the virtually tagged instruction cache of
- * those implementations.
*/
-#ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p,
- unsigned long clr,
- unsigned long set)
+static inline pte_basic_t pte_update(pte_t *p, unsigned long clr, unsigned
long set)
{
- unsigned long old, tmp;
-
- __asm__ __volatile__("\
-1: lwarx %0,0,%3\n\
- andc%1,%0,%4\n\
- or %1,%1,%5\n"
-" stwcx. %1,0,%3\n\
- bne-1b"
- : "=&r" (old), "=&r" (tmp), "=m" (*p)
- : "r" (p), "r" (clr), "r" (set), "m" (*p)
- : "cc" );
-
- return old;
-}
-#else /* CONFIG_PTE_64BIT */
-static inline unsigned long long pte_update(pte_t *p,
- unsigned long clr,
- unsigned long set)
-{
- unsigned long long old;
+ pte_basic_t old;
unsigned long tmp;
- __asm__ __volatile__("\
-1: lwarx %L0,0,%4\n\
- lwzx%0,0,%3\n\
- andc%1,%L0,%5\n\
- or %1,%1,%6\n"
-" stwcx. %1,0,%4\n\
- bne-1b"
+ __asm__ __volatile__(
+#ifndef CONFIG_PTE_64BIT
+"1:lwarx %0, 0, %3\n"
+" andc%1, %0, %4\n"
+#else
+"1:lwarx %L0, 0, %3\n"
+" lwz %0, -4(%3)\n"
+" andc%1, %L0, %4\n"
+#endif
+" or %1, %1, %5\n"
+" stwcx. %1, 0, %3\n"
+" bne-1b"
: "=&r" (old), "=&r" (tmp), "=m" (*p)
- : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
+#ifndef CONFIG_PTE_64BIT
+ : "r" (p),
+#else
+ : "b" ((unsigned long)(p) + 4),
+#endif
+ "r" (clr), "r" (set), "m" (*p)
: "cc" );
return old;
}
-#endif /* CONFIG_PTE_64BIT */
/*
* 2.6 calls this without flushing the TLB entry; this is wrong
--
2.25.0
[PATCH v4 18/45] powerpc/mm: Refactor pte_update() on nohash/32
When CONFIG_PTE_64BIT is set, pte_update() operates on
'unsigned long long'
When CONFIG_PTE_64BIT is not set, pte_update() operates on
'unsigned long'
In asm/page.h, we have pte_basic_t which is 'unsigned long long'
when CONFIG_PTE_64BIT is set and 'unsigned long' otherwise.
Refactor pte_update() using pte_basic_t.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 26 +++-
1 file changed, 4 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 7e908a176e9e..db17f50d6ac3 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -222,12 +222,9 @@ static inline void pmd_clear(pmd_t *pmdp)
* to properly flush the virtually tagged instruction cache of
* those implementations.
*/
-#ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p,
- unsigned long clr,
- unsigned long set)
+static inline pte_basic_t pte_update(pte_t *p, unsigned long clr, unsigned
long set)
{
-#ifdef PTE_ATOMIC_UPDATES
+#if defined(PTE_ATOMIC_UPDATES) && !defined(CONFIG_PTE_64BIT)
unsigned long old, tmp;
__asm__ __volatile__("\
@@ -241,8 +238,8 @@ static inline unsigned long pte_update(pte_t *p,
: "r" (p), "r" (clr), "r" (set), "m" (*p)
: "cc" );
#else /* PTE_ATOMIC_UPDATES */
- unsigned long old = pte_val(*p);
- unsigned long new = (old & ~clr) | set;
+ pte_basic_t old = pte_val(*p);
+ pte_basic_t new = (old & ~(pte_basic_t)clr) | set;
#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
p->pte = p->pte1 = p->pte2 = p->pte3 = new;
@@ -257,21 +254,6 @@ static inline unsigned long pte_update(pte_t *p,
#endif
return old;
}
-#else /* CONFIG_PTE_64BIT */
-static inline unsigned long long pte_update(pte_t *p,
- unsigned long clr,
- unsigned long set)
-{
- unsigned long long old = pte_val(*p);
- *p = __pte((old & ~(unsigned long long)clr) | set);
-
-#ifdef CONFIG_44x
- if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
- icache_44x_need_flush = 1;
-#endif
- return old;
-}
-#endif /* CONFIG_PTE_64BIT */
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int __ptep_test_and_clear_young(unsigned int context, unsigned
long addr, pte_t *ptep)
--
2.25.0
[PATCH v4 17/45] powerpc/mm: PTE_ATOMIC_UPDATES is only for 40x
Only 40x still uses PTE_ATOMIC_UPDATES.
40x cannot not select CONFIG_PTE64_BIT.
Drop handling of PTE_ATOMIC_UPDATES:
- In nohash/64
- In nohash/32 for CONFIG_PTE_64BIT
Keep PTE_ATOMIC_UPDATES only for nohash/32 for !CONFIG_PTE_64BIT
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 17
arch/powerpc/include/asm/nohash/64/pgtable.h | 28 +---
2 files changed, 1 insertion(+), 44 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 4315d40906a0..7e908a176e9e 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -262,25 +262,8 @@ static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
{
-#ifdef PTE_ATOMIC_UPDATES
- unsigned long long old;
- unsigned long tmp;
-
- __asm__ __volatile__("\
-1: lwarx %L0,0,%4\n\
- lwzx%0,0,%3\n\
- andc%1,%L0,%5\n\
- or %1,%1,%6\n"
- PPC405_ERR77(0,%3)
-" stwcx. %1,0,%4\n\
- bne-1b"
- : "=&r" (old), "=&r" (tmp), "=m" (*p)
- : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
- : "cc" );
-#else /* PTE_ATOMIC_UPDATES */
unsigned long long old = pte_val(*p);
*p = __pte((old & ~(unsigned long long)clr) | set);
-#endif /* !PTE_ATOMIC_UPDATES */
#ifdef CONFIG_44x
if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h
b/arch/powerpc/include/asm/nohash/64/pgtable.h
index 9a33b8bd842d..9c703b140d64 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -211,22 +211,9 @@ static inline unsigned long pte_update(struct mm_struct
*mm,
unsigned long set,
int huge)
{
-#ifdef PTE_ATOMIC_UPDATES
- unsigned long old, tmp;
-
- __asm__ __volatile__(
- "1: ldarx %0,0,%3 # pte_update\n\
- andc%1,%0,%4 \n\
- or %1,%1,%6\n\
- stdcx. %1,0,%3 \n\
- bne-1b"
- : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
- : "r" (ptep), "r" (clr), "m" (*ptep), "r" (set)
- : "cc" );
-#else
unsigned long old = pte_val(*ptep);
*ptep = __pte((old & ~clr) | set);
-#endif
+
/* huge pages use the old page table lock */
if (!huge)
assert_pte_locked(mm, addr);
@@ -310,21 +297,8 @@ static inline void __ptep_set_access_flags(struct
vm_area_struct *vma,
unsigned long bits = pte_val(entry) &
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
-#ifdef PTE_ATOMIC_UPDATES
- unsigned long old, tmp;
-
- __asm__ __volatile__(
- "1: ldarx %0,0,%4\n\
- or %0,%3,%0\n\
- stdcx. %0,0,%4\n\
- bne-1b"
- :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
- :"r" (bits), "r" (ptep), "m" (*ptep)
- :"cc");
-#else
unsigned long old = pte_val(*ptep);
*ptep = __pte(old | bits);
-#endif
flush_tlb_page(vma, address);
}
--
2.25.0
[PATCH v4 16/45] powerpc/mm: Fix conditions to perform MMU specific management by blocks on PPC32.
Setting init mem to NX shall depend on sinittext being mapped by
block, not on stext being mapped by block.
Setting text and rodata to RO shall depend on stext being mapped by
block, not on sinittext being mapped by block.
Fixes: 63b2bc619565 ("powerpc/mm/32s: Use BATs for STRICT_KERNEL_RWX")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable_32.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 9934659cb871..bd0cb6e3573e 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -185,7 +185,7 @@ void mark_initmem_nx(void)
unsigned long numpages = PFN_UP((unsigned long)_einittext) -
PFN_DOWN((unsigned long)_sinittext);
- if (v_block_mapped((unsigned long)_stext + 1))
+ if (v_block_mapped((unsigned long)_sinittext))
mmu_mark_initmem_nx();
else
change_page_attr(page, numpages, PAGE_KERNEL);
@@ -197,7 +197,7 @@ void mark_rodata_ro(void)
struct page *page;
unsigned long numpages;
- if (v_block_mapped((unsigned long)_sinittext)) {
+ if (v_block_mapped((unsigned long)_stext + 1)) {
mmu_mark_rodata_ro();
ptdump_check_wx();
return;
--
2.25.0
[PATCH v4 15/45] powerpc/mm: Allocate static page tables for fixmap
Allocate static page tables for the fixmap area. This allows
setting mappings through page tables before memblock is ready.
That's needed to use early_ioremap() early and to use standard
page mappings with fixmap.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/fixmap.h | 4
arch/powerpc/kernel/setup_32.c| 2 +-
arch/powerpc/mm/pgtable_32.c | 16
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fixmap.h
b/arch/powerpc/include/asm/fixmap.h
index 2ef155a3c821..ccbe2e83c950 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -86,6 +86,10 @@ enum fixed_addresses {
#define __FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
+#define FIXMAP_ALIGNED_SIZE(ALIGN(FIXADDR_TOP, PGDIR_SIZE) - \
+ALIGN_DOWN(FIXADDR_START, PGDIR_SIZE))
+#define FIXMAP_PTE_SIZE(FIXMAP_ALIGNED_SIZE / PGDIR_SIZE *
PTE_TABLE_SIZE)
+
#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NCG
#define FIXMAP_PAGE_IO PAGE_KERNEL_NCG
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 15f0a7c84944..d642e42eabb1 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -80,7 +80,7 @@ notrace void __init machine_init(u64 dt_ptr)
/* Configure static keys first, now that we're relocated. */
setup_feature_keys();
- early_ioremap_setup();
+ early_ioremap_init();
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index f62de06e3d07..9934659cb871 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -29,11 +29,27 @@
#include
#include
#include
+#include
#include
extern char etext[], _stext[], _sinittext[], _einittext[];
+static u8 early_fixmap_pagetable[FIXMAP_PTE_SIZE] __page_aligned_data;
+
+notrace void __init early_ioremap_init(void)
+{
+ unsigned long addr = ALIGN_DOWN(FIXADDR_START, PGDIR_SIZE);
+ pte_t *ptep = (pte_t *)early_fixmap_pagetable;
+ pmd_t *pmdp = pmd_ptr_k(addr);
+
+ for (; (s32)(FIXADDR_TOP - addr) > 0;
+addr += PGDIR_SIZE, ptep += PTRS_PER_PTE, pmdp++)
+ pmd_populate_kernel(&init_mm, pmdp, ptep);
+
+ early_ioremap_setup();
+}
+
static void __init *early_alloc_pgtable(unsigned long size)
{
void *ptr = memblock_alloc(size, size);
--
2.25.0
[PATCH v4 14/45] powerpc/32s: Don't warn when mapping RO data ROX.
Mapping RO data as ROX is not an issue since that data
cannot be modified to introduce an exploit.
PPC64 accepts to have RO data mapped ROX, as a trade off
between kernel size and strictness of protection.
On PPC32, kernel size is even more critical as amount of
memory is usually small.
Depending on the number of available IBATs, the last IBATs
might overflow the end of text. Only warn if it crosses
the end of RO data.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index 39ba53ca5bb5..a9b2cbc74797 100644
--- a/arch/powerpc/mm/book3s32/mmu.c
+++ b/arch/powerpc/mm/book3s32/mmu.c
@@ -187,6 +187,7 @@ void mmu_mark_initmem_nx(void)
int i;
unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
unsigned long top = (unsigned long)_etext - PAGE_OFFSET;
+ unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
unsigned long size;
if (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
@@ -201,9 +202,10 @@ void mmu_mark_initmem_nx(void)
size = block_size(base, top);
size = max(size, 128UL << 10);
if ((top - base) > size) {
- if (strict_kernel_rwx_enabled())
- pr_warn("Kernel _etext not properly aligned\n");
size <<= 1;
+ if (strict_kernel_rwx_enabled() && base + size > border)
+ pr_warn("Some RW data is getting mapped X. "
+ "Adjust CONFIG_DATA_SHIFT to avoid
that.\n");
}
setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
base += size;
--
2.25.0
[PATCH v4 12/45] powerpc/ptdump: Properly handle non standard page size
In order to properly display information regardless of the page size,
it is necessary to take into account real page size.
Signed-off-by: Christophe Leroy
Fixes: cabe8138b23c ("powerpc: dump as a single line areas mapping a single
physical page.")
Cc: sta...@vger.kernel.org
---
v3: Fixed sizes which were shifted one level (went unoticed on PPC32 as PMD and
PUD level don't exist)
---
arch/powerpc/mm/ptdump/ptdump.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index 1f97668853e3..98d82dcf6f0b 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -60,6 +60,7 @@ struct pg_state {
unsigned long start_address;
unsigned long start_pa;
unsigned long last_pa;
+ unsigned long page_size;
unsigned int level;
u64 current_flags;
bool check_wx;
@@ -168,9 +169,9 @@ static void dump_addr(struct pg_state *st, unsigned long
addr)
#endif
pt_dump_seq_printf(st->seq, REG "-" REG " ", st->start_address, addr -
1);
- if (st->start_pa == st->last_pa && st->start_address + PAGE_SIZE !=
addr) {
+ if (st->start_pa == st->last_pa && st->start_address + st->page_size !=
addr) {
pt_dump_seq_printf(st->seq, "[" REG "]", st->start_pa);
- delta = PAGE_SIZE >> 10;
+ delta = st->page_size >> 10;
} else {
pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa);
delta = (addr - st->start_address) >> 10;
@@ -195,7 +196,7 @@ static void note_prot_wx(struct pg_state *st, unsigned long
addr)
}
static void note_page(struct pg_state *st, unsigned long addr,
- unsigned int level, u64 val)
+ unsigned int level, u64 val, unsigned long page_size)
{
u64 flag = val & pg_level[level].mask;
u64 pa = val & PTE_RPN_MASK;
@@ -207,6 +208,7 @@ static void note_page(struct pg_state *st, unsigned long
addr,
st->start_address = addr;
st->start_pa = pa;
st->last_pa = pa;
+ st->page_size = page_size;
pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
/*
* Dump the section of virtual memory when:
@@ -218,7 +220,7 @@ static void note_page(struct pg_state *st, unsigned long
addr,
*/
} else if (flag != st->current_flags || level != st->level ||
addr >= st->marker[1].start_address ||
- (pa != st->last_pa + PAGE_SIZE &&
+ (pa != st->last_pa + st->page_size &&
(pa != st->start_pa || st->start_pa != st->last_pa))) {
/* Check the PTE flags */
@@ -246,6 +248,7 @@ static void note_page(struct pg_state *st, unsigned long
addr,
st->start_address = addr;
st->start_pa = pa;
st->last_pa = pa;
+ st->page_size = page_size;
st->current_flags = flag;
st->level = level;
} else {
@@ -261,7 +264,7 @@ static void walk_pte(struct pg_state *st, pmd_t *pmd,
unsigned long start)
for (i = 0; i < PTRS_PER_PTE; i++, pte++) {
addr = start + i * PAGE_SIZE;
- note_page(st, addr, 4, pte_val(*pte));
+ note_page(st, addr, 4, pte_val(*pte), PAGE_SIZE);
}
}
@@ -278,7 +281,7 @@ static void walk_pmd(struct pg_state *st, pud_t *pud,
unsigned long start)
/* pmd exists */
walk_pte(st, pmd, addr);
else
- note_page(st, addr, 3, pmd_val(*pmd));
+ note_page(st, addr, 3, pmd_val(*pmd), PMD_SIZE);
}
}
@@ -294,7 +297,7 @@ static void walk_pud(struct pg_state *st, pgd_t *pgd,
unsigned long start)
/* pud exists */
walk_pmd(st, pud, addr);
else
- note_page(st, addr, 2, pud_val(*pud));
+ note_page(st, addr, 2, pud_val(*pud), PUD_SIZE);
}
}
@@ -313,7 +316,7 @@ static void walk_pagetables(struct pg_state *st)
/* pgd exists */
walk_pud(st, pgd, addr);
else
- note_page(st, addr, 1, pgd_val(*pgd));
+ note_page(st, addr, 1, pgd_val(*pgd), PGDIR_SIZE);
}
}
@@ -368,7 +371,7 @@ static int ptdump_show(struct seq_file *m, void *v)
/* Traverse kernel page tables */
walk_pagetables(&st);
- note_page(&st, 0, 0, 0);
+ note_page(&st, 0, 0, 0, 0);
return 0;
}
--
2.25.0
[PATCH v4 13/45] powerpc/ptdump: Handle hugepd at PGD level
The 8xx is about to map kernel linear space and IMMR using huge
pages.
In order to display those pages properly, ptdump needs to handle
hugepd tables at PGD level.
For the time being do it only at PGD level. Further patches may
add handling of hugepd tables at lower level for other platforms
when needed in the future.
Signed-off-by: Christophe Leroy
---
v3: notepage() now takes page size instead of page shift
---
arch/powerpc/mm/ptdump/ptdump.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index 98d82dcf6f0b..5fc880e30175 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
@@ -269,6 +270,26 @@ static void walk_pte(struct pg_state *st, pmd_t *pmd,
unsigned long start)
}
}
+static void walk_hugepd(struct pg_state *st, hugepd_t *phpd, unsigned long
start,
+ int pdshift, int level)
+{
+#ifdef CONFIG_ARCH_HAS_HUGEPD
+ unsigned int i;
+ int shift = hugepd_shift(*phpd);
+ int ptrs_per_hpd = pdshift - shift > 0 ? 1 << (pdshift - shift) : 1;
+
+ if (start & ((1 << shift) - 1))
+ return;
+
+ for (i = 0; i < ptrs_per_hpd; i++) {
+ unsigned long addr = start + (i << shift);
+ pte_t *pte = hugepte_offset(*phpd, addr, pdshift);
+
+ note_page(st, addr, level + 1, pte_val(*pte), 1 << shift);
+ }
+#endif
+}
+
static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
{
pmd_t *pmd = pmd_offset(pud, 0);
@@ -312,11 +333,13 @@ static void walk_pagetables(struct pg_state *st)
* the hash pagetable.
*/
for (i = pgd_index(addr); i < PTRS_PER_PGD; i++, pgd++, addr +=
PGDIR_SIZE) {
- if (!pgd_none(*pgd) && !pgd_is_leaf(*pgd))
+ if (pgd_none(*pgd) || pgd_is_leaf(*pgd))
+ note_page(st, addr, 1, pgd_val(*pgd), PGDIR_SIZE);
+ else if (is_hugepd(__hugepd(pgd_val(*pgd
+ walk_hugepd(st, (hugepd_t *)pgd, addr, PGDIR_SHIFT, 1);
+ else
/* pgd exists */
walk_pud(st, pgd, addr);
- else
- note_page(st, addr, 1, pgd_val(*pgd), PGDIR_SIZE);
}
}
--
2.25.0
[PATCH v4 11/45] powerpc/ptdump: Standardise display of BAT flags
Display BAT flags the same way as page flags: rwx and wimg
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ptdump/bats.c | 37 ++-
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/bats.c b/arch/powerpc/mm/ptdump/bats.c
index d6c660f63d71..cebb58c7e289 100644
--- a/arch/powerpc/mm/ptdump/bats.c
+++ b/arch/powerpc/mm/ptdump/bats.c
@@ -15,12 +15,12 @@
static char *pp_601(int k, int pp)
{
if (pp == 0)
- return k ? "NA" : "RWX";
+ return k ? " " : "rwx";
if (pp == 1)
- return k ? "ROX" : "RWX";
+ return k ? "r x" : "rwx";
if (pp == 2)
- return k ? "RWX" : "RWX";
- return k ? "ROX" : "ROX";
+ return "rwx";
+ return "r x";
}
static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper)
@@ -48,12 +48,9 @@ static void bat_show_601(struct seq_file *m, int idx, u32
lower, u32 upper)
seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1,
pp));
- if (lower & _PAGE_WRITETHRU)
- seq_puts(m, "write through ");
- if (lower & _PAGE_NO_CACHE)
- seq_puts(m, "no cache ");
- if (lower & _PAGE_COHERENT)
- seq_puts(m, "coherent ");
+ seq_puts(m, lower & _PAGE_WRITETHRU ? "w " : " ");
+ seq_puts(m, lower & _PAGE_NO_CACHE ? "i " : " ");
+ seq_puts(m, lower & _PAGE_COHERENT ? "m " : " ");
seq_puts(m, "\n");
}
@@ -101,20 +98,16 @@ static void bat_show_603(struct seq_file *m, int idx, u32
lower, u32 upper, bool
seq_puts(m, "Kernel/User ");
if (lower & BPP_RX)
- seq_puts(m, is_d ? "RO " : "EXEC ");
+ seq_puts(m, is_d ? "r " : " x ");
else if (lower & BPP_RW)
- seq_puts(m, is_d ? "RW " : "EXEC ");
+ seq_puts(m, is_d ? "rw " : " x ");
else
- seq_puts(m, is_d ? "NA " : "NX ");
-
- if (lower & _PAGE_WRITETHRU)
- seq_puts(m, "write through ");
- if (lower & _PAGE_NO_CACHE)
- seq_puts(m, "no cache ");
- if (lower & _PAGE_COHERENT)
- seq_puts(m, "coherent ");
- if (lower & _PAGE_GUARDED)
- seq_puts(m, "guarded ");
+ seq_puts(m, is_d ? "" : "");
+
+ seq_puts(m, lower & _PAGE_WRITETHRU ? "w " : " ");
+ seq_puts(m, lower & _PAGE_NO_CACHE ? "i " : " ");
+ seq_puts(m, lower & _PAGE_COHERENT ? "m " : " ");
+ seq_puts(m, lower & _PAGE_GUARDED ? "g " : " ");
seq_puts(m, "\n");
}
--
2.25.0
[PATCH v4 10/45] powerpc/ptdump: Display size of BATs
Display the size of areas mapped with BATs.
For that, the size display for pages is refactorised.
Signed-off-by: Christophe Leroy
---
v2: Add missing include of linux/seq_file.h (Thanks to kbuild test robot)
---
arch/powerpc/mm/ptdump/bats.c | 4
arch/powerpc/mm/ptdump/ptdump.c | 23 ++-
arch/powerpc/mm/ptdump/ptdump.h | 3 +++
3 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/bats.c b/arch/powerpc/mm/ptdump/bats.c
index d3a5d6b318d1..d6c660f63d71 100644
--- a/arch/powerpc/mm/ptdump/bats.c
+++ b/arch/powerpc/mm/ptdump/bats.c
@@ -10,6 +10,8 @@
#include
#include
+#include "ptdump.h"
+
static char *pp_601(int k, int pp)
{
if (pp == 0)
@@ -42,6 +44,7 @@ static void bat_show_601(struct seq_file *m, int idx, u32
lower, u32 upper)
#else
seq_printf(m, "0x%08x ", pbn);
#endif
+ pt_dump_size(m, size);
seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1,
pp));
@@ -88,6 +91,7 @@ static void bat_show_603(struct seq_file *m, int idx, u32
lower, u32 upper, bool
#else
seq_printf(m, "0x%08x ", brpn);
#endif
+ pt_dump_size(m, size);
if (k == 1)
seq_puts(m, "User ");
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index d92bb8ea229c..1f97668853e3 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -112,6 +112,19 @@ static struct addr_marker address_markers[] = {
seq_putc(m, c); \
})
+void pt_dump_size(struct seq_file *m, unsigned long size)
+{
+ static const char units[] = "KMGTPE";
+ const char *unit = units;
+
+ /* Work out what appropriate unit to use */
+ while (!(size & 1023) && unit[1]) {
+ size >>= 10;
+ unit++;
+ }
+ pt_dump_seq_printf(m, "%9lu%c ", size, *unit);
+}
+
static void dump_flag_info(struct pg_state *st, const struct flag_info
*flag, u64 pte, int num)
{
@@ -146,8 +159,6 @@ static void dump_flag_info(struct pg_state *st, const
struct flag_info
static void dump_addr(struct pg_state *st, unsigned long addr)
{
- static const char units[] = "KMGTPE";
- const char *unit = units;
unsigned long delta;
#ifdef CONFIG_PPC64
@@ -164,13 +175,7 @@ static void dump_addr(struct pg_state *st, unsigned long
addr)
pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa);
delta = (addr - st->start_address) >> 10;
}
- /* Work out what appropriate unit to use */
- while (!(delta & 1023) && unit[1]) {
- delta >>= 10;
- unit++;
- }
- pt_dump_seq_printf(st->seq, "%9lu%c", delta, *unit);
-
+ pt_dump_size(st->seq, delta);
}
static void note_prot_wx(struct pg_state *st, unsigned long addr)
diff --git a/arch/powerpc/mm/ptdump/ptdump.h b/arch/powerpc/mm/ptdump/ptdump.h
index 5d513636de73..154efae96ae0 100644
--- a/arch/powerpc/mm/ptdump/ptdump.h
+++ b/arch/powerpc/mm/ptdump/ptdump.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include
+#include
struct flag_info {
u64 mask;
@@ -17,3 +18,5 @@ struct pgtable_level {
};
extern struct pgtable_level pg_level[5];
+
+void pt_dump_size(struct seq_file *m, unsigned long delta);
--
2.25.0
[PATCH v4 08/45] powerpc/ptdump: Reorder flags
Reorder flags in a more logical way:
- Page size (huge) first
- User
- RWX
- Present
- WIMG
- Special
- Dirty and Accessed
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ptdump/8xx.c| 30 +++---
arch/powerpc/mm/ptdump/shared.c | 30 +++---
2 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
index ca9ce94672f5..a3169677dced 100644
--- a/arch/powerpc/mm/ptdump/8xx.c
+++ b/arch/powerpc/mm/ptdump/8xx.c
@@ -11,11 +11,6 @@
static const struct flag_info flag_array[] = {
{
- .mask = _PAGE_SH,
- .val= _PAGE_SH,
- .set= "sh",
- .clear = " ",
- }, {
.mask = _PAGE_RO | _PAGE_NA,
.val= 0,
.set= "rw",
@@ -37,11 +32,26 @@ static const struct flag_info flag_array[] = {
.val= _PAGE_PRESENT,
.set= "p",
.clear = " ",
+ }, {
+ .mask = _PAGE_NO_CACHE,
+ .val= _PAGE_NO_CACHE,
+ .set= "i",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val= _PAGE_GUARDED,
.set= "g",
.clear = " ",
+ }, {
+ .mask = _PAGE_SH,
+ .val= _PAGE_SH,
+ .set= "sh",
+ .clear = " ",
+ }, {
+ .mask = _PAGE_SPECIAL,
+ .val= _PAGE_SPECIAL,
+ .set= "s",
+ .clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val= _PAGE_DIRTY,
@@ -52,16 +62,6 @@ static const struct flag_info flag_array[] = {
.val= _PAGE_ACCESSED,
.set= "a",
.clear = " ",
- }, {
- .mask = _PAGE_NO_CACHE,
- .val= _PAGE_NO_CACHE,
- .set= "i",
- .clear = " ",
- }, {
- .mask = _PAGE_SPECIAL,
- .val= _PAGE_SPECIAL,
- .set= "s",
- .clear = " ",
}
};
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index 44a8a64a664f..dab5d8028a9b 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -30,21 +30,6 @@ static const struct flag_info flag_array[] = {
.val= _PAGE_PRESENT,
.set= "p",
.clear = " ",
- }, {
- .mask = _PAGE_GUARDED,
- .val= _PAGE_GUARDED,
- .set= "g",
- .clear = " ",
- }, {
- .mask = _PAGE_DIRTY,
- .val= _PAGE_DIRTY,
- .set= "d",
- .clear = " ",
- }, {
- .mask = _PAGE_ACCESSED,
- .val= _PAGE_ACCESSED,
- .set= "a",
- .clear = " ",
}, {
.mask = _PAGE_WRITETHRU,
.val= _PAGE_WRITETHRU,
@@ -55,11 +40,26 @@ static const struct flag_info flag_array[] = {
.val= _PAGE_NO_CACHE,
.set= "i",
.clear = " ",
+ }, {
+ .mask = _PAGE_GUARDED,
+ .val= _PAGE_GUARDED,
+ .set= "g",
+ .clear = " ",
}, {
.mask = _PAGE_SPECIAL,
.val= _PAGE_SPECIAL,
.set= "s",
.clear = " ",
+ }, {
+ .mask = _PAGE_DIRTY,
+ .val= _PAGE_DIRTY,
+ .set= "d",
+ .clear = " ",
+ }, {
+ .mask = _PAGE_ACCESSED,
+ .val= _PAGE_ACCESSED,
+ .set= "a",
+ .clear = " ",
}
};
--
2.25.0
[PATCH v4 09/45] powerpc/ptdump: Add _PAGE_COHERENT flag
For platforms using shared.c (4xx, Book3e, Book3s/32),
also handle the _PAGE_COHERENT flag with corresponds to the
M bit of the WIMG flags.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ptdump/shared.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index dab5d8028a9b..634b83aa3487 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -40,6 +40,11 @@ static const struct flag_info flag_array[] = {
.val= _PAGE_NO_CACHE,
.set= "i",
.clear = " ",
+ }, {
+ .mask = _PAGE_COHERENT,
+ .val= _PAGE_COHERENT,
+ .set= "m",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val= _PAGE_GUARDED,
--
2.25.0
[PATCH v4 07/45] powerpc/ptdump: Limit size of flags text to 1/2 chars on PPC32
In order to have all flags fit on a 80 chars wide screen,
reduce the flags to 1 char (2 where ambiguous).
No cache is 'i'
User is 'ur' (Supervisor would be sr)
Shared (for 8xx) becomes 'sh' (it was 'user' when not shared but
that was ambiguous because that's not entirely right)
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ptdump/8xx.c| 33 ---
arch/powerpc/mm/ptdump/shared.c | 35 +
2 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
index 9e2d8e847d6e..ca9ce94672f5 100644
--- a/arch/powerpc/mm/ptdump/8xx.c
+++ b/arch/powerpc/mm/ptdump/8xx.c
@@ -12,9 +12,9 @@
static const struct flag_info flag_array[] = {
{
.mask = _PAGE_SH,
- .val= 0,
- .set= "user",
- .clear = "",
+ .val= _PAGE_SH,
+ .set= "sh",
+ .clear = " ",
}, {
.mask = _PAGE_RO | _PAGE_NA,
.val= 0,
@@ -30,37 +30,38 @@ static const struct flag_info flag_array[] = {
}, {
.mask = _PAGE_EXEC,
.val= _PAGE_EXEC,
- .set= " X ",
- .clear = " ",
+ .set= "x",
+ .clear = " ",
}, {
.mask = _PAGE_PRESENT,
.val= _PAGE_PRESENT,
- .set= "present",
- .clear = " ",
+ .set= "p",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val= _PAGE_GUARDED,
- .set= "guarded",
- .clear = " ",
+ .set= "g",
+ .clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val= _PAGE_DIRTY,
- .set= "dirty",
- .clear = " ",
+ .set= "d",
+ .clear = " ",
}, {
.mask = _PAGE_ACCESSED,
.val= _PAGE_ACCESSED,
- .set= "accessed",
- .clear = "",
+ .set= "a",
+ .clear = " ",
}, {
.mask = _PAGE_NO_CACHE,
.val= _PAGE_NO_CACHE,
- .set= "no cache",
- .clear = "",
+ .set= "i",
+ .clear = " ",
}, {
.mask = _PAGE_SPECIAL,
.val= _PAGE_SPECIAL,
- .set= "special",
+ .set= "s",
+ .clear = " ",
}
};
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index f7ed2f187cb0..44a8a64a664f 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -13,8 +13,8 @@ static const struct flag_info flag_array[] = {
{
.mask = _PAGE_USER,
.val= _PAGE_USER,
- .set= "user",
- .clear = "",
+ .set= "ur",
+ .clear = " ",
}, {
.mask = _PAGE_RW,
.val= _PAGE_RW,
@@ -23,42 +23,43 @@ static const struct flag_info flag_array[] = {
}, {
.mask = _PAGE_EXEC,
.val= _PAGE_EXEC,
- .set= " X ",
- .clear = " ",
+ .set= "x",
+ .clear = " ",
}, {
.mask = _PAGE_PRESENT,
.val= _PAGE_PRESENT,
- .set= "present",
- .clear = " ",
+ .set= "p",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val= _PAGE_GUARDED,
- .set= "guarded",
- .clear = " ",
+ .set= "g",
+ .clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val= _PAGE_DIRTY,
- .set= "dirty",
- .clear = " ",
+ .set= "d",
+ .clear = " ",
}, {
.mask = _PAGE_ACCESSED,
.val= _PAGE_ACCESSED,
- .set= "accessed",
- .clear = "",
+ .set= "a",
+ .clear = " ",
}, {
.mask = _PAGE_WRITETHRU,
.val= _PAGE_WRITETHRU,
- .set= "write through",
- .clear = " ",
+ .set= "w",
+ .clear = " ",
}, {
.mask = _PAGE_NO_CACHE,
.val= _PAGE_NO_CACHE,
- .set= "no cache",
- .clear = "",
+ .set= "i",
+ .clear = " ",
[PATCH v4 06/45] powerpc/kasan: Declare kasan_init_region() weak
In order to alloc sub-arches to alloc KASAN regions using optimised
methods (Huge pages on 8xx, BATs on BOOK3S, ...), declare
kasan_init_region() weak.
Also make kasan_init_shadow_page_tables() accessible from outside,
so that it can be called from the specific kasan_init_region()
functions if needed.
And populate remaining KASAN address space only once performed
the region mapping, to allow 8xx to allocate hugepd instead of
standard page tables for mapping via 8M hugepages.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/kasan.h | 3 +++
arch/powerpc/mm/kasan/kasan_init_32.c | 21 +++--
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/kasan.h b/arch/powerpc/include/asm/kasan.h
index 4769bbf7173a..107a24c3f7b3 100644
--- a/arch/powerpc/include/asm/kasan.h
+++ b/arch/powerpc/include/asm/kasan.h
@@ -34,5 +34,8 @@ static inline void kasan_init(void) { }
static inline void kasan_late_init(void) { }
#endif
+int kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_end);
+int kasan_init_region(void *start, size_t size);
+
#endif /* __ASSEMBLY */
#endif
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c
b/arch/powerpc/mm/kasan/kasan_init_32.c
index 10481d904fea..76d418af4ce8 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -28,7 +28,7 @@ static void __init kasan_populate_pte(pte_t *ptep, pgprot_t
prot)
__set_pte_at(&init_mm, va, ptep, pfn_pte(PHYS_PFN(pa), prot),
0);
}
-static int __init kasan_init_shadow_page_tables(unsigned long k_start,
unsigned long k_end)
+int __init kasan_init_shadow_page_tables(unsigned long k_start, unsigned long
k_end)
{
pmd_t *pmd;
unsigned long k_cur, k_next;
@@ -52,7 +52,7 @@ static int __init kasan_init_shadow_page_tables(unsigned long
k_start, unsigned
return 0;
}
-static int __init kasan_init_region(void *start, size_t size)
+int __init __weak kasan_init_region(void *start, size_t size)
{
unsigned long k_start = (unsigned long)kasan_mem_to_shadow(start);
unsigned long k_end = (unsigned long)kasan_mem_to_shadow(start + size);
@@ -122,14 +122,6 @@ static void __init kasan_mmu_init(void)
int ret;
struct memblock_region *reg;
- if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE) ||
- IS_ENABLED(CONFIG_KASAN_VMALLOC)) {
- ret = kasan_init_shadow_page_tables(KASAN_SHADOW_START,
KASAN_SHADOW_END);
-
- if (ret)
- panic("kasan: kasan_init_shadow_page_tables() failed");
- }
-
for_each_memblock(memory, reg) {
phys_addr_t base = reg->base;
phys_addr_t top = min(base + reg->size, total_lowmem);
@@ -141,6 +133,15 @@ static void __init kasan_mmu_init(void)
if (ret)
panic("kasan: kasan_init_region() failed");
}
+
+ if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE) ||
+ IS_ENABLED(CONFIG_KASAN_VMALLOC)) {
+ ret = kasan_init_shadow_page_tables(KASAN_SHADOW_START,
KASAN_SHADOW_END);
+
+ if (ret)
+ panic("kasan: kasan_init_shadow_page_tables() failed");
+ }
+
}
void __init kasan_init(void)
--
2.25.0
[PATCH v4 05/45] powerpc/kasan: Refactor update of early shadow mappings
kasan_remap_early_shadow_ro() and kasan_unmap_early_shadow_vmalloc()
are both updating the early shadow mapping: the first one sets
the mapping read-only while the other clears the mapping.
Refactor and create kasan_update_early_region()
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/kasan/kasan_init_32.c | 39 +--
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c
b/arch/powerpc/mm/kasan/kasan_init_32.c
index 91e2ade75192..10481d904fea 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -79,45 +79,42 @@ static int __init kasan_init_region(void *start, size_t
size)
return 0;
}
-static void __init kasan_remap_early_shadow_ro(void)
+static void __init
+kasan_update_early_region(unsigned long k_start, unsigned long k_end, pte_t
pte)
{
- pgprot_t prot = kasan_prot_ro();
- unsigned long k_start = KASAN_SHADOW_START;
- unsigned long k_end = KASAN_SHADOW_END;
unsigned long k_cur;
phys_addr_t pa = __pa(kasan_early_shadow_page);
- kasan_populate_pte(kasan_early_shadow_pte, prot);
-
- for (k_cur = k_start & PAGE_MASK; k_cur != k_end; k_cur += PAGE_SIZE) {
+ for (k_cur = k_start; k_cur != k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_ptr_k(k_cur);
pte_t *ptep = pte_offset_kernel(pmd, k_cur);
if ((pte_val(*ptep) & PTE_RPN_MASK) != pa)
continue;
- __set_pte_at(&init_mm, k_cur, ptep, pfn_pte(PHYS_PFN(pa),
prot), 0);
+ __set_pte_at(&init_mm, k_cur, ptep, pte, 0);
}
- flush_tlb_kernel_range(KASAN_SHADOW_START, KASAN_SHADOW_END);
+
+ flush_tlb_kernel_range(k_start, k_end);
}
-static void __init kasan_unmap_early_shadow_vmalloc(void)
+static void __init kasan_remap_early_shadow_ro(void)
{
- unsigned long k_start = (unsigned long)kasan_mem_to_shadow((void
*)VMALLOC_START);
- unsigned long k_end = (unsigned long)kasan_mem_to_shadow((void
*)VMALLOC_END);
- unsigned long k_cur;
+ pgprot_t prot = kasan_prot_ro();
phys_addr_t pa = __pa(kasan_early_shadow_page);
- for (k_cur = k_start & PAGE_MASK; k_cur < k_end; k_cur += PAGE_SIZE) {
- pmd_t *pmd = pmd_offset(pud_offset(pgd_offset_k(k_cur), k_cur),
k_cur);
- pte_t *ptep = pte_offset_kernel(pmd, k_cur);
+ kasan_populate_pte(kasan_early_shadow_pte, prot);
- if ((pte_val(*ptep) & PTE_RPN_MASK) != pa)
- continue;
+ kasan_update_early_region(KASAN_SHADOW_START, KASAN_SHADOW_END,
+ pfn_pte(PHYS_PFN(pa), prot));
+}
- __set_pte_at(&init_mm, k_cur, ptep, __pte(0), 0);
- }
- flush_tlb_kernel_range(k_start, k_end);
+static void __init kasan_unmap_early_shadow_vmalloc(void)
+{
+ unsigned long k_start = (unsigned long)kasan_mem_to_shadow((void
*)VMALLOC_START);
+ unsigned long k_end = (unsigned long)kasan_mem_to_shadow((void
*)VMALLOC_END);
+
+ kasan_update_early_region(k_start, k_end, __pte(0));
}
static void __init kasan_mmu_init(void)
--
2.25.0
[PATCH v4 04/45] powerpc/kasan: Remove unnecessary page table locking
Commit 45ff3c559585 ("powerpc/kasan: Fix parallel loading of
modules.") added spinlocks to manage parallele module loading.
Since then commit 47febbeeec44 ("powerpc/32: Force KASAN_VMALLOC for
modules") converted the module loading to KASAN_VMALLOC.
The spinlocking has then become unneeded and can be removed to
simplify kasan_init_shadow_page_tables()
Also remove inclusion of linux/moduleloader.h and linux/vmalloc.h
which are not needed anymore since the removal of modules management.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/kasan/kasan_init_32.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c
b/arch/powerpc/mm/kasan/kasan_init_32.c
index b7c287adfd59..91e2ade75192 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -5,9 +5,7 @@
#include
#include
#include
-#include
#include
-#include
#include
#include
#include
@@ -34,31 +32,22 @@ static int __init kasan_init_shadow_page_tables(unsigned
long k_start, unsigned
{
pmd_t *pmd;
unsigned long k_cur, k_next;
- pte_t *new = NULL;
pmd = pmd_ptr_k(k_start);
for (k_cur = k_start; k_cur != k_end; k_cur = k_next, pmd++) {
+ pte_t *new;
+
k_next = pgd_addr_end(k_cur, k_end);
if ((void *)pmd_page_vaddr(*pmd) != kasan_early_shadow_pte)
continue;
- if (!new)
- new = memblock_alloc(PTE_FRAG_SIZE, PTE_FRAG_SIZE);
+ new = memblock_alloc(PTE_FRAG_SIZE, PTE_FRAG_SIZE);
if (!new)
return -ENOMEM;
kasan_populate_pte(new, PAGE_KERNEL);
-
- smp_wmb(); /* See comment in __pte_alloc */
-
- spin_lock(&init_mm.page_table_lock);
- /* Has another populated it ? */
- if (likely((void *)pmd_page_vaddr(*pmd) ==
kasan_early_shadow_pte)) {
- pmd_populate_kernel(&init_mm, pmd, new);
- new = NULL;
- }
- spin_unlock(&init_mm.page_table_lock);
+ pmd_populate_kernel(&init_mm, pmd, new);
}
return 0;
}
--
2.25.0
[PATCH v4 03/45] powerpc/kasan: Fix shadow pages allocation failure
Doing kasan pages allocation in MMU_init is too early, kernel doesn't
have access yet to the entire memory space and memblock_alloc() fails
when the kernel is a bit big.
Do it from kasan_init() instead.
Fixes: 2edb16efc899 ("powerpc/32: Add KASAN support")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/kasan.h | 2 --
arch/powerpc/mm/init_32.c | 2 --
arch/powerpc/mm/kasan/kasan_init_32.c | 4 +++-
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/kasan.h b/arch/powerpc/include/asm/kasan.h
index fc900937f653..4769bbf7173a 100644
--- a/arch/powerpc/include/asm/kasan.h
+++ b/arch/powerpc/include/asm/kasan.h
@@ -27,12 +27,10 @@
#ifdef CONFIG_KASAN
void kasan_early_init(void);
-void kasan_mmu_init(void);
void kasan_init(void);
void kasan_late_init(void);
#else
static inline void kasan_init(void) { }
-static inline void kasan_mmu_init(void) { }
static inline void kasan_late_init(void) { }
#endif
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 872df48ae41b..a6991ef8727d 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -170,8 +170,6 @@ void __init MMU_init(void)
btext_unmap();
#endif
- kasan_mmu_init();
-
setup_kup();
/* Shortly after that, the entire linear mapping will be available */
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c
b/arch/powerpc/mm/kasan/kasan_init_32.c
index 8b15fe09b967..b7c287adfd59 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -131,7 +131,7 @@ static void __init kasan_unmap_early_shadow_vmalloc(void)
flush_tlb_kernel_range(k_start, k_end);
}
-void __init kasan_mmu_init(void)
+static void __init kasan_mmu_init(void)
{
int ret;
struct memblock_region *reg;
@@ -159,6 +159,8 @@ void __init kasan_mmu_init(void)
void __init kasan_init(void)
{
+ kasan_mmu_init();
+
kasan_remap_early_shadow_ro();
clear_page(kasan_early_shadow_page);
--
2.25.0
[PATCH v4 02/45] powerpc/kasan: Fix issues by lowering KASAN_SHADOW_END
At the time being, KASAN_SHADOW_END is 0x1, which
is 0 in 32 bits representation.
This leads to a couple of issues:
- kasan_remap_early_shadow_ro() does nothing because the comparison
k_cur < k_end is always false.
- In ptdump, address comparison for markers display fails and the
marker's name is printed at the start of the KASAN area instead of
being printed at the end.
However, there is no need to shadow the KASAN shadow area itself,
so the KASAN shadow area can stop shadowing memory at the start
of itself.
With a PAGE_OFFSET set to 0xc000, KASAN shadow area is then going
from 0xf800 to 0xff00.
Signed-off-by: Christophe Leroy
Fixes: cbd18991e24f ("powerpc/mm: Fix an Oops in kasan_mmu_init()")
Cc: sta...@vger.kernel.org
---
arch/powerpc/include/asm/kasan.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/kasan.h b/arch/powerpc/include/asm/kasan.h
index fbff9ff9032e..fc900937f653 100644
--- a/arch/powerpc/include/asm/kasan.h
+++ b/arch/powerpc/include/asm/kasan.h
@@ -23,9 +23,7 @@
#define KASAN_SHADOW_OFFSETASM_CONST(CONFIG_KASAN_SHADOW_OFFSET)
-#define KASAN_SHADOW_END 0UL
-
-#define KASAN_SHADOW_SIZE (KASAN_SHADOW_END - KASAN_SHADOW_START)
+#define KASAN_SHADOW_END (-(-KASAN_SHADOW_START >>
KASAN_SHADOW_SCALE_SHIFT))
#ifdef CONFIG_KASAN
void kasan_early_init(void);
--
2.25.0
[PATCH v4 00/45] Use hugepages to map kernel mem on 8xx
The main purpose of this big series is to: - reorganise huge page handling to avoid using mm_slices. - use huge pages to map kernel memory on the 8xx. The 8xx supports 4 page sizes: 4k, 16k, 512k and 8M. It uses 2 Level page tables, PGD having 1024 entries, each entry covering 4M address space. Then each page table has 1024 entries. At the time being, page sizes are managed in PGD entries, implying the use of mm_slices as it can't mix several pages of the same size in one page table. The first purpose of this series is to reorganise things so that standard page tables can also handle 512k pages. This is done by adding a new _PAGE_HUGE flag which will be copied into the Level 1 entry in the TLB miss handler. That done, we have 2 types of pages: - PGD entries to regular page tables handling 4k/16k and 512k pages - PGD entries to hugepd tables handling 8M pages. There is no need to mix 8M pages with other sizes, because a 8M page will use more than what a single PGD covers. Then comes the second purpose of this series. At the time being, the 8xx has implemented special handling in the TLB miss handlers in order to transparently map kernel linear address space and the IMMR using huge pages by building the TLB entries in assembly at the time of the exception. As mm_slices is only for user space pages, and also because it would anyway not be convenient to slice kernel address space, it was not possible to use huge pages for kernel address space. But after step one of the series, it is now more flexible to use huge pages. This series drop all assembly 'just in time' handling of huge pages and use huge pages in page tables instead. Once the above is done, then comes icing on the cake: - Use huge pages for KASAN shadow mapping - Allow pinned TLBs with strict kernel rwx - Allow pinned TLBs with debug pagealloc Then, last but not least, those modifications for the 8xx allows the following improvement on book3s/32: - Mapping KASAN shadow with BATs - Allowing BATs with debug pagealloc All this allows to considerably simplify TLB miss handlers and associated initialisation. The overhead of reading page tables is negligible compared to the reduction of the miss handlers. While we were at touching pte_update(), some cleanup was done there too. Tested widely on 8xx and 832x. Boot tested on QEMU MAC99. Changes in v4: - Rebased on top of powerpc/next following the merge of prefix instructions series. Changes in v3: - Fixed the handling of leaf pages page size which didn't build on PPC64 and was invisibily bogus on PPC32 (patch 12) Changes in v2: - Selecting HUGETLBFS instead of HUGETLB_PAGE which leads to link failure. - Rebase on latest powerpc/merge branch - Reworked the way TLB 28 to 31 are pinned because it was not working. Christophe Leroy (45): powerpc/kasan: Fix error detection on memory allocation powerpc/kasan: Fix issues by lowering KASAN_SHADOW_END powerpc/kasan: Fix shadow pages allocation failure powerpc/kasan: Remove unnecessary page table locking powerpc/kasan: Refactor update of early shadow mappings powerpc/kasan: Declare kasan_init_region() weak powerpc/ptdump: Limit size of flags text to 1/2 chars on PPC32 powerpc/ptdump: Reorder flags powerpc/ptdump: Add _PAGE_COHERENT flag powerpc/ptdump: Display size of BATs powerpc/ptdump: Standardise display of BAT flags powerpc/ptdump: Properly handle non standard page size powerpc/ptdump: Handle hugepd at PGD level powerpc/32s: Don't warn when mapping RO data ROX. powerpc/mm: Allocate static page tables for fixmap powerpc/mm: Fix conditions to perform MMU specific management by blocks on PPC32. powerpc/mm: PTE_ATOMIC_UPDATES is only for 40x powerpc/mm: Refactor pte_update() on nohash/32 powerpc/mm: Refactor pte_update() on book3s/32 powerpc/mm: Standardise __ptep_test_and_clear_young() params between PPC32 and PPC64 powerpc/mm: Standardise pte_update() prototype between PPC32 and PPC64 powerpc/mm: Create a dedicated pte_update() for 8xx powerpc/mm: Reduce hugepd size for 8M hugepages on 8xx powerpc/8xx: Drop CONFIG_8xx_COPYBACK option powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages. powerpc/8xx: Manage 512k huge pages as standard pages. powerpc/8xx: Only 8M pages are hugepte pages now powerpc/8xx: MM_SLICE is not needed anymore powerpc/8xx: Move PPC_PIN_TLB options into 8xx Kconfig powerpc/8xx: Add function to set pinned TLBs powerpc/8xx: Don't set IMMR map anymore at boot powerpc/8xx: Always pin TLBs at startup. powerpc/8xx: Drop special handling of Linear and IMMR mappings in I/D TLB handlers powerpc/8xx: Remove now unused TLB miss functions powerpc/8xx: Move DTLB perf handling closer. powerpc/mm: Don't be too strict with _etext alignment on PPC32 powerpc/8xx: Refactor kernel address boundary comparison powerpc/8xx: Add a function to early map kernel via huge pages powerpc/8xx: Map IMMR with a huge page powerpc/8xx: Map linear memory with huge
[PATCH v4 01/45] powerpc/kasan: Fix error detection on memory allocation
In case (k_start & PAGE_MASK) doesn't equal (kstart), 'va' will never be
NULL allthough 'block' is NULL
Check the return of memblock_alloc() directly instead of
the resulting address in the loop.
Fixes: 509cd3f2b473 ("powerpc/32: Simplify KASAN init")
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/kasan/kasan_init_32.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c
b/arch/powerpc/mm/kasan/kasan_init_32.c
index cbcad369fcb2..8b15fe09b967 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -76,15 +76,14 @@ static int __init kasan_init_region(void *start, size_t
size)
return ret;
block = memblock_alloc(k_end - k_start, PAGE_SIZE);
+ if (!block)
+ return -ENOMEM;
for (k_cur = k_start & PAGE_MASK; k_cur < k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_ptr_k(k_cur);
void *va = block + k_cur - k_start;
pte_t pte = pfn_pte(PHYS_PFN(__pa(va)), PAGE_KERNEL);
- if (!va)
- return -ENOMEM;
-
__set_pte_at(&init_mm, k_cur, pte_offset_kernel(pmd, k_cur),
pte, 0);
}
flush_tlb_kernel_range(k_start, k_end);
--
2.25.0
Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1
On Tuesday, 19 May 2020 2:04:51 PM AEST Jordan Niethe wrote:
> On Tue, May 19, 2020 at 10:39 AM Alistair Popple
wrote:
> > Newer ISA versions are enabled by clearing all bits in the PCR
> > associated with previous versions of the ISA. Enable ISA v3.1 support
> > by updating the PCR mask to include ISA v3.0. This ensures all PCR
> > bits corresponding to earlier architecture versions get cleared
> > thereby enabling ISA v3.1 if supported by the hardware.
> >
> > Signed-off-by: Alistair Popple
> > ---
> >
> > arch/powerpc/include/asm/cputable.h | 1 +
> > arch/powerpc/include/asm/reg.h | 3 ++-
> > arch/powerpc/kvm/book3s_hv.c| 3 ---
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/cputable.h
> > b/arch/powerpc/include/asm/cputable.h index 40a4d3c6fd99..36f894dea9e7
> > 100644
> > --- a/arch/powerpc/include/asm/cputable.h
> > +++ b/arch/powerpc/include/asm/cputable.h
> > @@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
> >
> > #define CPU_FTR_P9_TIDR
> > LONG_ASM_CONST(0x8000) #define CPU_FTR_P9_TLBIE_ERAT_BUG
> > LONG_ASM_CONST(0x0001) #define
> > CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002)>
> > +#define CPU_FTR_ARCH_31
> > LONG_ASM_CONST(0x0004)>
> > #ifndef __ASSEMBLY__
> >
> > diff --git a/arch/powerpc/include/asm/reg.h
> > b/arch/powerpc/include/asm/reg.h index 773f76402392..1931b1142599 100644
> > --- a/arch/powerpc/include/asm/reg.h
> > +++ b/arch/powerpc/include/asm/reg.h
> > @@ -485,10 +485,11 @@
> >
> > * determine both the compatibility level which we want to emulate and
> > the
> > * compatibility level which the host is capable of emulating.
> > */
> >
> > +#define PCR_ARCH_300 0x10/* Architecture 3.00 */
> >
> > #define PCR_ARCH_207 0x8 /* Architecture 2.07 */
> > #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
> > #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
> >
> > -#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
> > +#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 |
> > PCR_ARCH_300)>
> > #define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved
> > Bits */ #defineSPRN_HEIR 0x153 /* Hypervisor Emulated
> > Instruction Register */ #define SPRN_TLBINDEXR 0x154 /* P7 TLB control
> > register */
> >
> > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> > index 93493f0cbfe8..532215040f3e 100644
> > --- a/arch/powerpc/kvm/book3s_hv.c
> > +++ b/arch/powerpc/kvm/book3s_hv.c
> > @@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu,
> > u32 pvr)>
> > vcpu->arch.pvr = pvr;
> >
> > }
> >
> > -/* Dummy value used in computing PCR value below */
> > -#define PCR_ARCH_300 (PCR_ARCH_207 << 1)
> > -
>
> Later will we need
> +/* Dummy value used in computing PCR value below */
> +#define PCR_ARCH_310 (PCR_ARCH_300 << 1)
> ?
Correct. I left that out of this patch series though as I am putting together
a separate series for basic P10 KVM enablement which will add the definition
for ARCH 3.1.
- Alistair
> > static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
> > {
> >
> > unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
> >
> > --
> > 2.20.1
Re: [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier
Hi Dan, Apologies for the delay in response. I was waiting for feedback from hardware team before responding to this email. Dan Williams writes: > On Tue, May 12, 2020 at 8:47 PM Aneesh Kumar K.V > wrote: >> >> Architectures like ppc64 provide persistent memory specific barriers >> that will ensure that all stores for which the modifications are >> written to persistent storage by preceding dcbfps and dcbstps >> instructions have updated persistent storage before any data >> access or data transfer caused by subsequent instructions is initiated. >> This is in addition to the ordering done by wmb() >> >> Update nvdimm core such that architecture can use barriers other than >> wmb to ensure all previous writes are architecturally visible for >> the platform buffer flush. > > This seems like an exceedingly bad idea, maybe I'm missing something. > This implies that the deployed base of DAX applications using the old > instruction sequence are going to regress on new hardware that > requires the new instructions to be deployed. pmdk support for ppc64 is still work in progress and there is pull request to switch pmdk to use new instruction. https://github.com/tuliom/pmdk/commit/fix-flush All userspace applications will be switched to use the new instructions. The new instructions are designed such that when running on P8 and P9 they behave as 'dcbf' and 'hwsync'. Applications using new instructions will behave as expected when running on P8 and P9. Only future hardware will differentiate between 'dcbf' and 'dcbfps' > I'm thinking the kernel > should go as far as to disable DAX operation by default on new > hardware until userspace asserts that it is prepared to switch to the > new implementation. Is there any other way to ensure the forward > compatibility of deployed ppc64 DAX applications? AFAIU there is no released persistent memory hardware on ppc64 platform and we need to make sure before applications get enabled to use these persistent memory devices, they should switch to use the new instruction? > >> >> Signed-off-by: Aneesh Kumar K.V >> --- >> drivers/nvdimm/region_devs.c | 8 >> include/linux/libnvdimm.h| 4 >> 2 files changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c >> index ccbb5b43b8b2..88ea34a9c7fd 100644 >> --- a/drivers/nvdimm/region_devs.c >> +++ b/drivers/nvdimm/region_devs.c >> @@ -1216,13 +1216,13 @@ int generic_nvdimm_flush(struct nd_region *nd_region) >> idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); >> >> /* >> -* The first wmb() is needed to 'sfence' all previous writes >> -* such that they are architecturally visible for the platform >> -* buffer flush. Note that we've already arranged for pmem >> +* The first arch_pmem_flush_barrier() is needed to 'sfence' all >> +* previous writes such that they are architecturally visible for >> +* the platform buffer flush. Note that we've already arranged for >> pmem >> * writes to avoid the cache via memcpy_flushcache(). The final >> * wmb() ensures ordering for the NVDIMM flush write. >> */ >> - wmb(); >> + arch_pmem_flush_barrier(); >> for (i = 0; i < nd_region->ndr_mappings; i++) >> if (ndrd_get_flush_wpq(ndrd, i, 0)) >> writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); >> diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h >> index 18da4059be09..66f6c65bd789 100644 >> --- a/include/linux/libnvdimm.h >> +++ b/include/linux/libnvdimm.h >> @@ -286,4 +286,8 @@ static inline void arch_invalidate_pmem(void *addr, >> size_t size) >> } >> #endif >> >> +#ifndef arch_pmem_flush_barrier >> +#define arch_pmem_flush_barrier() wmb() >> +#endif >> + >> #endif /* __LIBNVDIMM_H__ */ >> -- >> 2.26.2 >> > ___ > Linux-nvdimm mailing list -- linux-nvd...@lists.01.org > To unsubscribe send an email to linux-nvdimm-le...@lists.01.org
Re: [PATCH v8 12/30] powerpc: Use a function for reading instructions
Le 19/05/2020 à 06:05, Michael Ellerman a écrit : Jordan Niethe writes: On Sun, May 17, 2020 at 4:39 AM Christophe Leroy wrote: Le 06/05/2020 à 05:40, Jordan Niethe a écrit : Prefixed instructions will mean there are instructions of different length. As a result dereferencing a pointer to an instruction will not necessarily give the desired result. Introduce a function for reading instructions from memory into the instruction data type. Shouldn't this function be used in mmu_patch_addis() in mm/nohash/8xx.c ? Christophe Yes, that would be a good idea. mpe here is a fix, along with one I'll post for [PATCH v8 11/30] powerpc: Use a datatype for instructions. I didn't fold this in because I'd prefer one of you send me a patch on top of the series that converts that code to use the new type. That way it can be tested separately from this big series. All this code is going away with the series implementing the use of hugepages for kernel mappings on 8xx (https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=176094) that I hope will go in 5.8, so there is no point in sending a patch to change that I guess. Is there anything special I need to do to secure the merging of that series in 5.8 ? Christophe
[PATCH] powerpc/configs: Add LIBNVDIMM to ppc64_defconfig
This gives us OF_PMEM which is useful in mambo. This adds 153K to the text of ppc64le_defconfig which 0.8% of the total text. LIBNVDIMM text databss dec hex Without 18574833 5518150 1539240 25632223 1871ddf With 18727834 5546206 1539368 25813408 189e1a0 Signed-off-by: Michael Neuling --- arch/powerpc/configs/ppc64_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig index bae8170d74..0a92549924 100644 --- a/arch/powerpc/configs/ppc64_defconfig +++ b/arch/powerpc/configs/ppc64_defconfig @@ -281,6 +281,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_VIRTIO_PCI=m CONFIG_VIRTIO_BALLOON=m +CONFIG_LIBNVDIMM=y CONFIG_RAS=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y -- 2.26.2
Re: [PATCH v8 12/30] powerpc: Use a function for reading instructions
Jordan Niethe writes:
> On Sun, May 17, 2020 at 4:39 AM Christophe Leroy
> wrote:
>>
>> Le 06/05/2020 à 05:40, Jordan Niethe a écrit :
>> > Prefixed instructions will mean there are instructions of different
>> > length. As a result dereferencing a pointer to an instruction will not
>> > necessarily give the desired result. Introduce a function for reading
>> > instructions from memory into the instruction data type.
>>
>>
>> Shouldn't this function be used in mmu_patch_addis() in mm/nohash/8xx.c ?
>>
>> Christophe
> Yes, that would be a good idea.
> mpe here is a fix, along with one I'll
> post for [PATCH v8 11/30] powerpc: Use a datatype for instructions.
I didn't fold this in because I'd prefer one of you send me a patch on
top of the series that converts that code to use the new type.
That way it can be tested separately from this big series.
cheers
> diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
> --- a/arch/powerpc/mm/nohash/8xx.c
> +++ b/arch/powerpc/mm/nohash/8xx.c
> @@ -98,7 +98,7 @@ static void mmu_patch_cmp_limit(s32 *site, unsigned
> long mapped)
>
> static void mmu_patch_addis(s32 *site, long simm)
> {
> -struct ppc_inst instr = *(struct ppc_inst *)patch_site_addr(site);
> +struct ppc_inst instr = ppc_inst_read((struct ppc_inst
> *)patch_site_addr(site));
> unsigned int val = ppc_inst_val(instr);
>
> val &= 0x;
> --
>>
>> >
>> > Reviewed-by: Alistair Popple
>> > Signed-off-by: Jordan Niethe
>> > ---
>> > v4: New to series
>> > v5: - Rename read_inst() -> probe_kernel_read_inst()
>> > - No longer modify uprobe probe type in this patch
>> > v6: - feature-fixups.c: do_final_fixups(): Use here
>> > - arch_prepare_kprobe(): patch_instruction(): no longer part of this
>> >patch
>> > - Move probe_kernel_read_inst() out of this patch
>> > - Use in uprobes
>> > v8: style
>> > ---
>> > arch/powerpc/include/asm/inst.h| 5 +
>> > arch/powerpc/kernel/kprobes.c | 6 +++---
>> > arch/powerpc/kernel/mce_power.c| 2 +-
>> > arch/powerpc/kernel/optprobes.c| 4 ++--
>> > arch/powerpc/kernel/trace/ftrace.c | 4 ++--
>> > arch/powerpc/kernel/uprobes.c | 2 +-
>> > arch/powerpc/lib/code-patching.c | 26 ++
>> > arch/powerpc/lib/feature-fixups.c | 4 ++--
>> > arch/powerpc/xmon/xmon.c | 6 +++---
>> > 9 files changed, 33 insertions(+), 26 deletions(-)
>> >
>> > diff --git a/arch/powerpc/include/asm/inst.h
>> > b/arch/powerpc/include/asm/inst.h
>> > index 19d8bb7a1c2b..552e953bf04f 100644
>> > --- a/arch/powerpc/include/asm/inst.h
>> > +++ b/arch/powerpc/include/asm/inst.h
>> > @@ -27,6 +27,11 @@ static inline struct ppc_inst ppc_inst_swab(struct
>> > ppc_inst x)
>> > return ppc_inst(swab32(ppc_inst_val(x)));
>> > }
>> >
>> > +static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
>> > +{
>> > + return *ptr;
>> > +}
>> > +
>> > static inline bool ppc_inst_equal(struct ppc_inst x, struct ppc_inst y)
>> > {
>> > return ppc_inst_val(x) == ppc_inst_val(y);
>> > diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
>> > index a08ae5803622..f64312dca84f 100644
>> > --- a/arch/powerpc/kernel/kprobes.c
>> > +++ b/arch/powerpc/kernel/kprobes.c
>> > @@ -106,7 +106,7 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name,
>> > unsigned int offset)
>> > int arch_prepare_kprobe(struct kprobe *p)
>> > {
>> > int ret = 0;
>> > - struct ppc_inst insn = *(struct ppc_inst *)p->addr;
>> > + struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->addr);
>> >
>> > if ((unsigned long)p->addr & 0x03) {
>> > printk("Attempt to register kprobe at an unaligned
>> > address\n");
>> > @@ -127,7 +127,7 @@ int arch_prepare_kprobe(struct kprobe *p)
>> > if (!ret) {
>> > memcpy(p->ainsn.insn, p->addr,
>> > MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
>> > - p->opcode = *p->addr;
>> > + p->opcode = ppc_inst_val(insn);
>> > flush_icache_range((unsigned long)p->ainsn.insn,
>> > (unsigned long)p->ainsn.insn +
>> > sizeof(kprobe_opcode_t));
>> > }
>> > @@ -217,7 +217,7 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe);
>> > static int try_to_emulate(struct kprobe *p, struct pt_regs *regs)
>> > {
>> > int ret;
>> > - struct ppc_inst insn = *(struct ppc_inst *)p->ainsn.insn;
>> > + struct ppc_inst insn = ppc_inst_read((struct ppc_inst
>> > *)p->ainsn.insn);
>> >
>> > /* regs->nip is also adjusted if emulate_step returns 1 */
>> > ret = emulate_step(regs, insn);
>> > diff --git a/arch/powerpc/kernel/mce_power.c
>> > b/arch/powerpc/kernel/mce_power.c
>> > index cd23218c60bb..45c51ba0071b 100644
>> > --- a/arch/powerpc/kernel/mce_power.c
>> > +++ b/arch/powerpc/kernel/mce_power.c
>> > @@ -374,7 +374,7 @@ static int mce_find_instr_ea_and_phys(str
Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1
On Tue, May 19, 2020 at 10:39 AM Alistair Popple wrote:
>
> Newer ISA versions are enabled by clearing all bits in the PCR
> associated with previous versions of the ISA. Enable ISA v3.1 support
> by updating the PCR mask to include ISA v3.0. This ensures all PCR
> bits corresponding to earlier architecture versions get cleared
> thereby enabling ISA v3.1 if supported by the hardware.
>
> Signed-off-by: Alistair Popple
> ---
> arch/powerpc/include/asm/cputable.h | 1 +
> arch/powerpc/include/asm/reg.h | 3 ++-
> arch/powerpc/kvm/book3s_hv.c| 3 ---
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h
> b/arch/powerpc/include/asm/cputable.h
> index 40a4d3c6fd99..36f894dea9e7 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTR_P9_TIDR
> LONG_ASM_CONST(0x8000)
> #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001)
> #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002)
> +#define CPU_FTR_ARCH_31
> LONG_ASM_CONST(0x0004)
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 773f76402392..1931b1142599 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -485,10 +485,11 @@
> * determine both the compatibility level which we want to emulate and the
> * compatibility level which the host is capable of emulating.
> */
> +#define PCR_ARCH_300 0x10/* Architecture 3.00 */
> #define PCR_ARCH_207 0x8 /* Architecture 2.07 */
> #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
> #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
> -#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
> +#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 |
> PCR_ARCH_300)
> #define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits
> */
> #defineSPRN_HEIR 0x153 /* Hypervisor Emulated Instruction
> Register */
> #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 93493f0cbfe8..532215040f3e 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu, u32
> pvr)
> vcpu->arch.pvr = pvr;
> }
>
> -/* Dummy value used in computing PCR value below */
> -#define PCR_ARCH_300 (PCR_ARCH_207 << 1)
> -
Later will we need
+/* Dummy value used in computing PCR value below */
+#define PCR_ARCH_310 (PCR_ARCH_300 << 1)
?
> static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
> {
> unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
> --
> 2.20.1
>
Re: [PATCH v2 7/7] powerpc: Add POWER10 architected mode
On Tue, May 19, 2020 at 10:48 AM Alistair Popple wrote:
>
> PVR value of 0x0F06 means we are arch v3.1 compliant (i.e. POWER10).
> This is used by phyp and kvm when booting as a pseries guest to detect
> the presence of new P10 features and to enable the appropriate hwcap and
> facility bits.
>
> Signed-off-by: Alistair Popple
> Signed-off-by: Cédric Le Goater
> ---
> arch/powerpc/include/asm/cputable.h | 15 --
> arch/powerpc/include/asm/mmu.h| 1 +
> arch/powerpc/include/asm/prom.h | 1 +
> arch/powerpc/kernel/cpu_setup_power.S | 20 --
> arch/powerpc/kernel/cputable.c| 30 +++
> arch/powerpc/kernel/prom_init.c | 12 +--
> 6 files changed, 73 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h
> b/arch/powerpc/include/asm/cputable.h
> index 36f894dea9e7..10b6d93c9d0b 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
>CPU_FTR_P9_TM_HV_ASSIST | \
>CPU_FTR_P9_TM_XER_SO_BUG)
> +#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
> + CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
> + CPU_FTR_MMCRA | CPU_FTR_SMT | \
> + CPU_FTR_COHERENT_ICACHE | \
> + CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
> + CPU_FTR_DSCR | CPU_FTR_SAO | \
> + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD |
> \
> + CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
> + CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
> + CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
> + CPU_FTR_ARCH_31)
> #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
> CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
> @@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTRS_POSSIBLE \
> (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
> -CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
> +CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
> #else
> #define CPU_FTRS_POSSIBLE \
> (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
> CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
> CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
> CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
> -CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
> +CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
> #endif /* CONFIG_CPU_LITTLE_ENDIAN */
> #endif
> #else
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index 0699cfeeb8c9..17b19510f204 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -122,6 +122,7 @@
> #define MMU_FTRS_POWER7MMU_FTRS_POWER6
> #define MMU_FTRS_POWER8MMU_FTRS_POWER6
> #define MMU_FTRS_POWER9MMU_FTRS_POWER6
> +#define MMU_FTRS_POWER10 MMU_FTRS_POWER6
> #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
> MMU_FTR_CI_LARGE_PAGE
> #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
> diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
> index 94e3fd54f2c8..324a13351749 100644
> --- a/arch/powerpc/include/asm/prom.h
> +++ b/arch/powerpc/include/asm/prom.h
> @@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
> #define OV1_PPC_2_07 0x01/* set if we support PowerPC 2.07 */
>
> #define OV1_PPC_3_00 0x80/* set if we support PowerPC 3.00 */
> +#define OV1_PPC_3_10x40/* set if we support PowerPC
> 3.1 */
>
> /* Option vector 2: Open Firmware options supported */
> #define OV2_REAL_MODE 0x20/* set if we want OF in real mode */
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S
> b/arch/powerpc/kernel/cpu_setup_power.S
> index a460298c7ddb..f3730cf904fa 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
> mtlrr11
> blr
>
> +_GLOBAL(__setup_cpu_power10)
> + mflrr11
> + bl __init_FSCR_P10
> + b 1f
> +
> _GLOBAL(__setup_cpu_power9)
> mflrr11
> bl __init_FSCR
> - bl __init_PMU
> +1: bl __init_PMU
> bl __init_hvmode_206
> mtlrr11
> beqlr
> @@ -116,10 +121,15 @@ _GLOBAL(__s
RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
On 2020/5/19 6:19, Gustavo A. R. Silva wrote:
> -Original Message-
> From: Gustavo A. R. Silva
> Sent: 2020年5月19日 6:19
> To: Qiang Zhao ; Leo Li
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Gustavo A. R. Silva ;
> Kees Cook
> Subject: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size()
> helper
>
> The current codebase makes use of one-element arrays in the following
> form:
>
> struct something {
> int length;
> u8 data[1];
> };
>
> struct something *instance;
>
> instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
> instance->length = size;
> memcpy(instance->data, source, size);
>
> but the preferred mechanism to declare variable-length types such as these
> ones is a flexible array member[1][2], introduced in C99:
>
> struct foo {
> int stuff;
> struct boo array[];
> };
>
> By making use of the mechanism above, we will get a compiler warning in case
> the flexible array does not occur last in the structure, which will help us
> prevent
> some kind of undefined behavior bugs from being inadvertently introduced[3]
> to the codebase from now on. So, replace the one-element array with a
> flexible-array member.
>
> Also, make use of the new struct_size() helper to properly calculate the size
> of
> struct qe_firmware.
>
> This issue was found with the help of Coccinelle and, audited and fixed
> _manually_.
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgcc.gnu.
> org%2Fonlinedocs%2Fgcc%2FZero-Length.html&data=02%7C01%7Cqiang.
> zhao%40nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C637254368610203908&sdata=70
> a6VBg3oWQf9a5KICuCEuIj6gw57NKYhNv2JL8JdDY%3D&reserved=0
> [2]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c
> om%2FKSPP%2Flinux%2Fissues%2F21&data=02%7C01%7Cqiang.zhao%40
> nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b4c6fa92c
> d99c5c301635%7C0%7C0%7C637254368610213901&sdata=kVyNBYHbm
> a5jCO9pbkoHMetHEYGvWDq6Xw%2BBeC7uHII%3D&reserved=0
> [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
>
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/soc/fsl/qe/qe.c | 4 ++--
> include/soc/fsl/qe/qe.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 447146861c2c1..2df20d6f85fa4 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
> unsigned int i;
> unsigned int j;
> u32 crc;
> - size_t calc_size = sizeof(struct qe_firmware);
> + size_t calc_size;
> size_t length;
> const struct qe_header *hdr;
>
> @@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
> }
>
> /* Validate the length and check if there's a CRC */
> - calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
> + calc_size = struct_size(firmware, microcode, firmware->count);
>
> for (i = 0; i < firmware->count; i++)
> /*
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index
> e282ac01ec081..3feddfec9f87d 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -307,7 +307,7 @@ struct qe_firmware {
> u8 revision;/* The microcode version revision */
> u8 padding; /* Reserved, for alignment */
> u8 reserved[4]; /* Reserved, for future expansion */
> - } __attribute__ ((packed)) microcode[1];
> + } __packed microcode[];
> /* All microcode binaries should be located here */
> /* CRC32 should be located here, after the microcode binaries */ }
> __attribute__ ((packed));
> --
> 2.26.2
[>]
Reviewed-by: Qiang Zhao
Best Regards
Qiang Zhao
Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits
On Tue, 2020-05-19 at 10:31 +1000, Alistair Popple wrote: > POWER10 introduces two new architectural features - ISAv3.1 and matrix > multiply accumulate (MMA) instructions. Userspace detects the presence > of these features via two HWCAP bits introduced in this patch. These > bits have been agreed to by the compiler and binutils team. > > Signed-off-by: Alistair Popple I've test booted this series + powerpc/next (30df74d67d) on top of powervm and OPAL on a P10 simulator. In both cases, it enables MMA and prefix instructions and advertises them via HWCAP2 MMA + ISA 3.1. Hence: Tested-by: Michael Neuling > --- > arch/powerpc/include/uapi/asm/cputable.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/powerpc/include/uapi/asm/cputable.h > b/arch/powerpc/include/uapi/asm/cputable.h > index 540592034740..2692a56bf20b 100644 > --- a/arch/powerpc/include/uapi/asm/cputable.h > +++ b/arch/powerpc/include/uapi/asm/cputable.h > @@ -50,6 +50,8 @@ > #define PPC_FEATURE2_DARN0x0020 /* darn random number insn */ > #define PPC_FEATURE2_SCV 0x0010 /* scv syscall */ > #define PPC_FEATURE2_HTM_NO_SUSPEND 0x0008 /* TM w/out suspended state > */ > +#define PPC_FEATURE2_ARCH_3_10x0004 /* ISA 3.1 */ > +#define PPC_FEATURE2_MMA 0x0002 /* Matrix Multiply Accumulate > */ > > /* > * IMPORTANT!
Re: [PATCH V3 07/15] arch/kunmap_atomic: Consolidate duplicate code
Hi Ira,
On 5/18/20 5:03 PM, Ira Weiny wrote:
> On Sun, May 17, 2020 at 09:29:32PM -0700, Guenter Roeck wrote:
>> On Sun, May 17, 2020 at 08:49:39PM -0700, Ira Weiny wrote:
>>> On Sat, May 16, 2020 at 03:33:06PM -0700, Guenter Roeck wrote:
On Thu, May 07, 2020 at 07:59:55AM -0700, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Every single architecture (including !CONFIG_HIGHMEM) calls...
>
> pagefault_enable();
> preempt_enable();
>
> ... before returning from __kunmap_atomic(). Lift this code into the
> kunmap_atomic() macro.
>
> While we are at it rename __kunmap_atomic() to kunmap_atomic_high() to
> be consistent.
>
> Reviewed-by: Christoph Hellwig
> Signed-off-by: Ira Weiny
This patch results in:
Starting init: /bin/sh exists but couldn't execute it (error -14)
when trying to boot microblazeel:petalogix-ml605 in qemu.
>>>
>>> Thanks for the report. I'm not readily seeing the issue.
>>>
>>> Do you have a kernel config? Specifically is CONFIG_HIGHMEM set?
>>>
>> See below. Yes, CONFIG_HIGHMEM is set.
>>
>> The scripts used to build and boot the image are at:
>>
>> https://github.com/groeck/linux-build-test/tree/master/rootfs/microblazeel
>
> Despite finding the obvious error earlier today I've still been trying to get
> this to work.
>
> I had to make some slight modifications to use the 0-day cross compile build
> and my local qemu build. But those were pretty minor modifications. I'm
> running on x86_64 host.
>
> With those slight mods to the scripts I get the following error even without
> my
> patch set on 5.7-rc4. I have 1 cpu pegged at 100% while it is running... Is
> there anything I can do to get more debug output? Perhaps I just need to let
> it run longer?
>
I don't think so. Try running it with "-d" parameter (run-qemu-microblazeel.sh
-d petalogix-s3adsp1800); that gives you the qemu command line. Once it says
"running", abort the script and execute qemu directly. Oh, and please update
the repository; turns out I didn't push for a while and made a number of
changes.
My compiler was compiled with buildroot (a long time ago). I don't recall if
it needed something special in the configuration, unfortunately.
Guenter
> Thanks,
> Ira
>
> 16:46:54 > ../linux-build-test/rootfs/microblazeel/run-qemu-microblazeel.sh
> Build reference: v5.7-rc4-2-g7c2411d7fb6a
>
> Building microblaze:petalogix-s3adsp1800:qemu_microblazeel_defconfig ...
> running failed (silent)
>
> qemu log:
> qemu-system-microblazeel: terminating on signal 15 from pid 3277686
> (/bin/bash)
>
> Building microblaze:petalogix-ml605:qemu_microblazeel_ml605_defconfig ...
> running failed (silent)
>
> qemu log:
> qemu-system-microblazeel: terminating on signal 15 from pid 3277686
> (/bin/bash)
>
>
>
> 16:47:23 > git di
> diff --git a/rootfs/microblazeel/run-qemu-microblazeel.sh
> b/rootfs/microblazeel/run-qemu-microblazeel.sh
> index 68d4de39ab50..0d6a4f85308f 100755
> --- a/rootfs/microblazeel/run-qemu-microblazeel.sh
> +++ b/rootfs/microblazeel/run-qemu-microblazeel.sh
> @@ -3,7 +3,8 @@
> dir=$(cd $(dirname $0); pwd)
> . ${dir}/../scripts/common.sh
>
> -QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
> +#QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
> +QEMU=/home/iweiny/dev/qemu/microblazeel-softmmu/qemu-system-microblazeel
> PREFIX=microblazeel-linux-
> ARCH=microblaze
> PATH_MICROBLAZE=/opt/kernel/microblazeel/gcc-4.9.1/usr/bin
> diff --git a/rootfs/scripts/common.sh b/rootfs/scripts/common.sh
> index 8fa6a9be2b2f..c4550a27beaa 100644
> --- a/rootfs/scripts/common.sh
> +++ b/rootfs/scripts/common.sh
> @@ -1,5 +1,9 @@
> #!/bin/bash
>
> +# Set up make.cross
> +export COMPILER_INSTALL_PATH=$HOME/0day
> +export GCC_VERSION=6.5.0
> +
> # Set the following variable to true to skip DC395/AM53C97 build tests
> __skip_dc395=0
>
> @@ -569,7 +573,7 @@ doclean()
> then
> git clean -x -d -f -q
> else
> - make ARCH=${ARCH} mrproper >/dev/null 2>&1
> + make.cross ARCH=${ARCH} mrproper >/dev/null 2>&1
> fi
> }
>
> @@ -669,7 +673,7 @@ __setup_config()
> cp ${__progdir}/${defconfig} arch/${arch}/configs
> fi
>
> -if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${defconfig} >/dev/null
> 2>&1 +if ! make.cross ARCH=${ARCH} ${defconfig} >/dev/null 2>&1 then
> return 2
> fi
>
> @@ -687,7 +691,7 @@ __setup_config()
> if [[ "${rel}" = "v3.16" ]]; then
> target="oldconfig"
> fi
> - if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${target} >/dev/null
> 2>&1 + if ! make.cross ARCH=${ARCH} ${target} >/dev/null 2>&1 then
> return 1
> fi
> fi
> @@ -1038,7 +1042,7 @@ dosetup()
> rootfs="$(setup_rootfs ${dynamic} ${rootfs})"
> __common_fixups "${fixups
[PATCH v2 7/7] powerpc: Add POWER10 architected mode
PVR value of 0x0F06 means we are arch v3.1 compliant (i.e. POWER10).
This is used by phyp and kvm when booting as a pseries guest to detect
the presence of new P10 features and to enable the appropriate hwcap and
facility bits.
Signed-off-by: Alistair Popple
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/cputable.h | 15 --
arch/powerpc/include/asm/mmu.h| 1 +
arch/powerpc/include/asm/prom.h | 1 +
arch/powerpc/kernel/cpu_setup_power.S | 20 --
arch/powerpc/kernel/cputable.c| 30 +++
arch/powerpc/kernel/prom_init.c | 12 +--
6 files changed, 73 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 36f894dea9e7..10b6d93c9d0b 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
CPU_FTR_P9_TM_HV_ASSIST | \
CPU_FTR_P9_TM_XER_SO_BUG)
+#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
+ CPU_FTR_MMCRA | CPU_FTR_SMT | \
+ CPU_FTR_COHERENT_ICACHE | \
+ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+ CPU_FTR_DSCR | CPU_FTR_SAO | \
+ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
+ CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
+ CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
+ CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
+ CPU_FTR_ARCH_31)
#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
-CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
+CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
#else
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
-CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
+CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
#endif /* CONFIG_CPU_LITTLE_ENDIAN */
#endif
#else
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 0699cfeeb8c9..17b19510f204 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -122,6 +122,7 @@
#define MMU_FTRS_POWER7MMU_FTRS_POWER6
#define MMU_FTRS_POWER8MMU_FTRS_POWER6
#define MMU_FTRS_POWER9MMU_FTRS_POWER6
+#define MMU_FTRS_POWER10 MMU_FTRS_POWER6
#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 94e3fd54f2c8..324a13351749 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
#define OV1_PPC_2_07 0x01/* set if we support PowerPC 2.07 */
#define OV1_PPC_3_00 0x80/* set if we support PowerPC 3.00 */
+#define OV1_PPC_3_10x40/* set if we support PowerPC
3.1 */
/* Option vector 2: Open Firmware options supported */
#define OV2_REAL_MODE 0x20/* set if we want OF in real mode */
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index a460298c7ddb..f3730cf904fa 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
mtlrr11
blr
+_GLOBAL(__setup_cpu_power10)
+ mflrr11
+ bl __init_FSCR_P10
+ b 1f
+
_GLOBAL(__setup_cpu_power9)
mflrr11
bl __init_FSCR
- bl __init_PMU
+1: bl __init_PMU
bl __init_hvmode_206
mtlrr11
beqlr
@@ -116,10 +121,15 @@ _GLOBAL(__setup_cpu_power9)
mtlrr11
blr
+_GLOBAL(__restore_cpu_power10)
+ mflrr11
+ bl __init_FSCR_P10
+ b 1f
+
_GLOBAL(__restore_cpu_power9)
mflrr11
bl __init_FSCR
- bl __init_PMU
[PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature
Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
POWER10. Support on powernv can be selected via a firmware CPU device
tree feature which enables it via a PCR bit.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 ++-
arch/powerpc/kernel/dt_cpu_ftrs.c | 17 -
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1931b1142599..c446863a40cf 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -479,7 +479,8 @@
#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
-#define PCR_HIGH_BITS(PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
+#define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */
+#define PCR_HIGH_BITS(PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS |
PCR_TM_DIS)
/*
* These bits are used in the function kvmppc_set_arch_compat() to specify and
* determine both the compatibility level which we want to emulate and the
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 93c340906aad..e7540ee5cad8 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -75,6 +75,7 @@ static struct {
u64 lpcr_clear;
u64 hfscr;
u64 fscr;
+ u64 pcr;
} system_registers;
static void (*init_pmu_registers)(void);
@@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
if (hv_mode) {
mtspr(SPRN_LPID, 0);
mtspr(SPRN_HFSCR, system_registers.hfscr);
- mtspr(SPRN_PCR, PCR_MASK);
+ mtspr(SPRN_PCR, system_registers.pcr);
}
mtspr(SPRN_FSCR, system_registers.fscr);
@@ -555,6 +556,18 @@ static int __init feat_enable_large_ci(struct
dt_cpu_feature *f)
return 1;
}
+static int __init feat_enable_mma(struct dt_cpu_feature *f)
+{
+ u64 pcr;
+
+ feat_enable(f);
+ pcr = mfspr(SPRN_PCR);
+ pcr &= ~PCR_MMA_DIS;
+ mtspr(SPRN_PCR, pcr);
+
+ return 1;
+}
+
struct dt_cpu_feature_match {
const char *name;
int (*enable)(struct dt_cpu_feature *f);
@@ -629,6 +642,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
{"prefix-instructions", feat_enable, 0},
+ {"matrix-multiply-accumulate", feat_enable_mma, 0},
};
static bool __initdata using_dt_cpu_ftrs;
@@ -779,6 +793,7 @@ static void __init cpufeatures_setup_finished(void)
system_registers.lpcr = mfspr(SPRN_LPCR);
system_registers.hfscr = mfspr(SPRN_HFSCR);
system_registers.fscr = mfspr(SPRN_FSCR);
+ system_registers.pcr = mfspr(SPRN_PCR);
pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
--
2.20.1
[PATCH v2 5/7] powerpc/dt_cpu_ftrs: Enable Prefixed Instructions
Prefix instructions have their own FSCR bit which needs to be enabled
via a CPU feature. The kernel will save the FSCR for problem state but
it needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 677190f70cac..93c340906aad 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -628,6 +628,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary128", feat_enable, 0},
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
+ {"prefix-instructions", feat_enable, 0},
};
static bool __initdata using_dt_cpu_ftrs;
--
2.20.1
[PATCH v2 4/7] powerpc/dt_cpu_ftrs: Set current thread fscr bits
Setting the FSCR bit directly in the SPR only sets it during the initial
boot and early init of the kernel but not for the init process or any
subsequent kthreads. This is because the thread_struct for those is
copied from the current thread_struct setup at boot which doesn't
reflect any changes made to the FSCR during cpu feature detection. This
patch ensures the current thread state is updated to match once feature
detection is complete.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index b5e21264d168..677190f70cac 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -170,6 +170,7 @@ static int __init feat_try_enable_unknown(struct
dt_cpu_feature *f)
u64 fscr = mfspr(SPRN_FSCR);
fscr |= 1UL << f->fscr_bit_nr;
mtspr(SPRN_FSCR, fscr);
+ current->thread.fscr |= 1UL << f->fscr_bit_nr;
} else {
/* Does not have a known recipe */
return 0;
@@ -205,6 +206,7 @@ static int __init feat_enable(struct dt_cpu_feature *f)
u64 fscr = mfspr(SPRN_FSCR);
fscr |= 1UL << f->fscr_bit_nr;
mtspr(SPRN_FSCR, fscr);
+ current->thread.fscr |= 1UL << f->fscr_bit_nr;
}
}
--
2.20.1
[PATCH v2 3/7] powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1 if selected
On powernv hardware support for ISAv3.1 is advertised via a cpu feature
bit in the device tree. This patch enables the associated HWCAP bit if
the device tree indicates ISAv3.1 is available.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 36bc0d5c4f3a..b5e21264d168 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -26,6 +26,7 @@
/* Device-tree visible constants follow */
#define ISA_V2_07B 2070
#define ISA_V3_0B 3000
+#define ISA_V3_13100
#define USABLE_PR (1U << 0)
#define USABLE_OS (1U << 1)
@@ -654,6 +655,11 @@ static void __init cpufeatures_setup_start(u32 isa)
cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
}
+
+ if (isa >= 3100) {
+ cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_31;
+ cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_1;
+ }
}
static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
--
2.20.1
[PATCH v2 2/7] powerpc: Add support for ISA v3.1
Newer ISA versions are enabled by clearing all bits in the PCR
associated with previous versions of the ISA. Enable ISA v3.1 support
by updating the PCR mask to include ISA v3.0. This ensures all PCR
bits corresponding to earlier architecture versions get cleared
thereby enabling ISA v3.1 if supported by the hardware.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/cputable.h | 1 +
arch/powerpc/include/asm/reg.h | 3 ++-
arch/powerpc/kvm/book3s_hv.c| 3 ---
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 40a4d3c6fd99..36f894dea9e7 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_P9_TIDR
LONG_ASM_CONST(0x8000)
#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001)
#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002)
+#define CPU_FTR_ARCH_31
LONG_ASM_CONST(0x0004)
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 773f76402392..1931b1142599 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -485,10 +485,11 @@
* determine both the compatibility level which we want to emulate and the
* compatibility level which the host is capable of emulating.
*/
+#define PCR_ARCH_300 0x10/* Architecture 3.00 */
#define PCR_ARCH_207 0x8 /* Architecture 2.07 */
#define PCR_ARCH_206 0x4 /* Architecture 2.06 */
#define PCR_ARCH_205 0x2 /* Architecture 2.05 */
-#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
+#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 |
PCR_ARCH_300)
#define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */
#defineSPRN_HEIR 0x153 /* Hypervisor Emulated Instruction
Register */
#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 93493f0cbfe8..532215040f3e 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu, u32
pvr)
vcpu->arch.pvr = pvr;
}
-/* Dummy value used in computing PCR value below */
-#define PCR_ARCH_300 (PCR_ARCH_207 << 1)
-
static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
{
unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
--
2.20.1
[PATCH v2 1/7] powerpc: Add new HWCAP bits
POWER10 introduces two new architectural features - ISAv3.1 and matrix multiply accumulate (MMA) instructions. Userspace detects the presence of these features via two HWCAP bits introduced in this patch. These bits have been agreed to by the compiler and binutils team. Signed-off-by: Alistair Popple --- arch/powerpc/include/uapi/asm/cputable.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h index 540592034740..2692a56bf20b 100644 --- a/arch/powerpc/include/uapi/asm/cputable.h +++ b/arch/powerpc/include/uapi/asm/cputable.h @@ -50,6 +50,8 @@ #define PPC_FEATURE2_DARN 0x0020 /* darn random number insn */ #define PPC_FEATURE2_SCV 0x0010 /* scv syscall */ #define PPC_FEATURE2_HTM_NO_SUSPEND0x0008 /* TM w/out suspended state */ +#define PPC_FEATURE2_ARCH_3_1 0x0004 /* ISA 3.1 */ +#define PPC_FEATURE2_MMA 0x0002 /* Matrix Multiply Accumulate */ /* * IMPORTANT! -- 2.20.1
[PATCH v2 0/7] Base support for POWER10
This series brings together several previously posted patches required for POWER10 support and introduces a new patch enabling POWER10 architected mode to enable booting as a POWER10 pseries guest. It includes support for enabling facilities related to MMA and prefix instructions. Changes from v1: - Two bug-fixes to enable prefix and MMA on pseries - Minor updates to commit message wording - Fixes a build error when CONFIG_KVM_BOOK3S_64_HV is enabled Alistair Popple (7): powerpc: Add new HWCAP bits powerpc: Add support for ISA v3.1 powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1 if selected powerpc/dt_cpu_ftrs: Set current thread fscr bits powerpc/dt_cpu_ftrs: Enable Prefixed Instructions powerpc/dt_cpu_ftrs: Add MMA feature powerpc: Add POWER10 architected mode arch/powerpc/include/asm/cputable.h | 16 +++-- arch/powerpc/include/asm/mmu.h | 1 + arch/powerpc/include/asm/prom.h | 1 + arch/powerpc/include/asm/reg.h | 6 +++-- arch/powerpc/include/uapi/asm/cputable.h | 2 ++ arch/powerpc/kernel/cpu_setup_power.S| 20 ++-- arch/powerpc/kernel/cputable.c | 30 arch/powerpc/kernel/dt_cpu_ftrs.c| 26 +++- arch/powerpc/kernel/prom_init.c | 12 -- arch/powerpc/kvm/book3s_hv.c | 3 --- 10 files changed, 105 insertions(+), 12 deletions(-) -- 2.20.1
[PATCH v3 1/1] powerpc/crash: Use NMI context for printk when starting to crash
Currently, if printk lock (logbuf_lock) is held by other thread during crash, there is a chance of deadlocking the crash on next printk, and blocking a possibly desired kdump. At the start of default_machine_crash_shutdown, make printk enter NMI context, as it will use per-cpu buffers to store the message, and avoid locking logbuf_lock. Suggested-by: Michael Ellerman Signed-off-by: Leonardo Bras --- Changes since v2: - Changes usage of printk_nmi_enter() to nmi_enter() (Suggested by Nick Piggin) Changes since v1: - Added in-code comment explaining the need of context change - Function moved to the start of default_machine_crash_shutdown, to avoid locking any printk on crashing routine. - Title was 'Use NMI context for printk after crashing other CPUs' --- arch/powerpc/kexec/crash.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/kexec/crash.c b/arch/powerpc/kexec/crash.c index d488311efab1..53c5cf9b6d3c 100644 --- a/arch/powerpc/kexec/crash.c +++ b/arch/powerpc/kexec/crash.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -311,6 +312,13 @@ void default_machine_crash_shutdown(struct pt_regs *regs) unsigned int i; int (*old_handler)(struct pt_regs *regs); + /* +* Avoid hardlocking with irresponsive CPU holding logbuf_lock, +* by using printk nmi_context +*/ + if (!in_nmi()) + nmi_enter(); + /* * This function is only called after the system * has panicked or is otherwise in a critical state. -- 2.25.4
[powerpc:merge] BUILD SUCCESS 7b06fb8795ffea9d12be45a172197c3307955479
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge branch HEAD: 7b06fb8795ffea9d12be45a172197c3307955479 Automatic merge of 'master', 'next' and 'fixes' (2020-05-18 12:23) elapsed time: 526m configs tested: 92 configs skipped: 7 The following configs have been built successfully. More configs may be tested in the coming days. arm64allyesconfig arm64 defconfig arm64allmodconfig arm64 allnoconfig arm defconfig arm allyesconfig arm allmodconfig arm allnoconfig mips allyesconfig m68k allyesconfig i386 allnoconfig i386 allyesconfig i386defconfig i386 debian-10.3 ia64 allmodconfig ia64defconfig ia64 allnoconfig ia64 allyesconfig m68k allmodconfig m68k allnoconfig m68k sun3_defconfig m68kdefconfig nds32 defconfig nds32 allnoconfig csky allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig h8300allmodconfig xtensa defconfig arc defconfig arc allyesconfig sh allmodconfig shallnoconfig microblazeallnoconfig mips allnoconfig mips allmodconfig parisc defconfig pariscallnoconfig parisc allyesconfig parisc allmodconfig powerpc defconfig powerpc allyesconfig powerpc rhel-kconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a006-20200518 i386 randconfig-a005-20200518 i386 randconfig-a001-20200518 i386 randconfig-a003-20200518 i386 randconfig-a004-20200518 i386 randconfig-a002-20200518 x86_64 randconfig-a016-20200518 x86_64 randconfig-a012-20200518 x86_64 randconfig-a015-20200518 x86_64 randconfig-a013-20200518 x86_64 randconfig-a011-20200518 x86_64 randconfig-a014-20200518 i386 randconfig-a012-20200518 i386 randconfig-a014-20200518 i386 randconfig-a016-20200518 i386 randconfig-a011-20200518 i386 randconfig-a015-20200518 i386 randconfig-a013-20200518 riscvallyesconfig riscv allnoconfig riscv defconfig riscvallmodconfig s390 allyesconfig s390 allnoconfig s390 allmodconfig s390defconfig x86_64 defconfig sparcallyesconfig sparc defconfig sparc64 defconfig sparc64 allnoconfig sparc64 allyesconfig sparc64 allmodconfig um allmodconfig umallnoconfig um allyesconfig um defconfig x86_64 rhel x86_64 rhel-7.6 x86_64rhel-7.6-kselftests x86_64 rhel-7.2-clear x86_64lkp x86_64 fedora-25 x86_64 kexec --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [PATCH V3 07/15] arch/kunmap_atomic: Consolidate duplicate code
On Sun, May 17, 2020 at 09:29:32PM -0700, Guenter Roeck wrote:
> On Sun, May 17, 2020 at 08:49:39PM -0700, Ira Weiny wrote:
> > On Sat, May 16, 2020 at 03:33:06PM -0700, Guenter Roeck wrote:
> > > On Thu, May 07, 2020 at 07:59:55AM -0700, ira.we...@intel.com wrote:
> > > > From: Ira Weiny
> > > >
> > > > Every single architecture (including !CONFIG_HIGHMEM) calls...
> > > >
> > > > pagefault_enable();
> > > > preempt_enable();
> > > >
> > > > ... before returning from __kunmap_atomic(). Lift this code into the
> > > > kunmap_atomic() macro.
> > > >
> > > > While we are at it rename __kunmap_atomic() to kunmap_atomic_high() to
> > > > be consistent.
> > > >
> > > > Reviewed-by: Christoph Hellwig
> > > > Signed-off-by: Ira Weiny
> > >
> > > This patch results in:
> > >
> > > Starting init: /bin/sh exists but couldn't execute it (error -14)
> > >
> > > when trying to boot microblazeel:petalogix-ml605 in qemu.
> >
> > Thanks for the report. I'm not readily seeing the issue.
> >
> > Do you have a kernel config? Specifically is CONFIG_HIGHMEM set?
> >
> See below. Yes, CONFIG_HIGHMEM is set.
>
> The scripts used to build and boot the image are at:
>
> https://github.com/groeck/linux-build-test/tree/master/rootfs/microblazeel
Despite finding the obvious error earlier today I've still been trying to get
this to work.
I had to make some slight modifications to use the 0-day cross compile build
and my local qemu build. But those were pretty minor modifications. I'm
running on x86_64 host.
With those slight mods to the scripts I get the following error even without my
patch set on 5.7-rc4. I have 1 cpu pegged at 100% while it is running... Is
there anything I can do to get more debug output? Perhaps I just need to let
it run longer?
Thanks,
Ira
16:46:54 > ../linux-build-test/rootfs/microblazeel/run-qemu-microblazeel.sh
Build reference: v5.7-rc4-2-g7c2411d7fb6a
Building microblaze:petalogix-s3adsp1800:qemu_microblazeel_defconfig ...
running failed (silent)
qemu log:
qemu-system-microblazeel: terminating on signal 15 from pid 3277686 (/bin/bash)
Building microblaze:petalogix-ml605:qemu_microblazeel_ml605_defconfig ...
running failed (silent)
qemu log:
qemu-system-microblazeel: terminating on signal 15 from pid 3277686 (/bin/bash)
16:47:23 > git di
diff --git a/rootfs/microblazeel/run-qemu-microblazeel.sh
b/rootfs/microblazeel/run-qemu-microblazeel.sh
index 68d4de39ab50..0d6a4f85308f 100755
--- a/rootfs/microblazeel/run-qemu-microblazeel.sh
+++ b/rootfs/microblazeel/run-qemu-microblazeel.sh
@@ -3,7 +3,8 @@
dir=$(cd $(dirname $0); pwd)
. ${dir}/../scripts/common.sh
-QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
+#QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
+QEMU=/home/iweiny/dev/qemu/microblazeel-softmmu/qemu-system-microblazeel
PREFIX=microblazeel-linux-
ARCH=microblaze
PATH_MICROBLAZE=/opt/kernel/microblazeel/gcc-4.9.1/usr/bin
diff --git a/rootfs/scripts/common.sh b/rootfs/scripts/common.sh
index 8fa6a9be2b2f..c4550a27beaa 100644
--- a/rootfs/scripts/common.sh
+++ b/rootfs/scripts/common.sh
@@ -1,5 +1,9 @@
#!/bin/bash
+# Set up make.cross
+export COMPILER_INSTALL_PATH=$HOME/0day
+export GCC_VERSION=6.5.0
+
# Set the following variable to true to skip DC395/AM53C97 build tests
__skip_dc395=0
@@ -569,7 +573,7 @@ doclean()
then
git clean -x -d -f -q
else
- make ARCH=${ARCH} mrproper >/dev/null 2>&1
+ make.cross ARCH=${ARCH} mrproper >/dev/null 2>&1
fi
}
@@ -669,7 +673,7 @@ __setup_config()
cp ${__progdir}/${defconfig} arch/${arch}/configs
fi
-if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${defconfig} >/dev/null
2>&1 /dev/null 2>&1 /dev/null
2>&1 /dev/null 2>&1 /dev/null 2>${logfile}
+make.cross -j${maxload} ARCH=${ARCH} ${EXTRAS} /dev/null
2>${logfile}
rv=$?
if [ ${rv} -ne 0 ]
then
[PATCH v6 2/2] powerpc/rtas: Implement reentrant rtas call
Implement rtas_call_reentrant() for reentrant rtas-calls:
"ibm,int-on", "ibm,int-off",ibm,get-xive" and "ibm,set-xive".
On LoPAPR Version 1.1 (March 24, 2016), from 7.3.10.1 to 7.3.10.4,
items 2 and 3 say:
2 - For the PowerPC External Interrupt option: The * call must be
reentrant to the number of processors on the platform.
3 - For the PowerPC External Interrupt option: The * argument call
buffer for each simultaneous call must be physically unique.
So, these rtas-calls can be called in a lockless way, if using
a different buffer for each cpu doing such rtas call.
For this, it was suggested to add the buffer (struct rtas_args)
in the PACA struct, so each cpu can have it's own buffer.
The PACA struct received a pointer to rtas buffer, which is
allocated in the memory range available to rtas 32-bit.
Reentrant rtas calls are useful to avoid deadlocks in crashing,
where rtas-calls are needed, but some other thread crashed holding
the rtas.lock.
This is a backtrace of a deadlock from a kdump testing environment:
#0 arch_spin_lock
#1 lock_rtas ()
#2 rtas_call (token=8204, nargs=1, nret=1, outputs=0x0)
#3 ics_rtas_mask_real_irq (hw_irq=4100)
#4 machine_kexec_mask_interrupts
#5 default_machine_crash_shutdown
#6 machine_crash_shutdown
#7 __crash_kexec
#8 crash_kexec
#9 oops_end
Signed-off-by: Leonardo Bras
---
arch/powerpc/include/asm/paca.h | 4 +++
arch/powerpc/include/asm/rtas.h | 1 +
arch/powerpc/kernel/paca.c | 34 +++
arch/powerpc/kernel/rtas.c | 52 +
arch/powerpc/sysdev/xics/ics-rtas.c | 22 ++--
5 files changed, 102 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index e3cc9eb9204d..1e2d45f3f84c 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
@@ -270,6 +271,9 @@ struct paca_struct {
#ifdef CONFIG_MMIOWB
struct mmiowb_state mmiowb_state;
#endif
+#ifdef CONFIG_PPC_RTAS
+ struct rtas_args *rtas_args_reentrant;
+#endif /* CONFIG_PPC_RTAS */
} cacheline_aligned;
extern void copy_mm_to_paca(struct mm_struct *mm);
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index c35c5350b7e4..fa7509c85881 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -236,6 +236,7 @@ extern struct rtas_t rtas;
extern int rtas_token(const char *service);
extern int rtas_service_present(const char *service);
extern int rtas_call(int token, int, int, int *, ...);
+int rtas_call_reentrant(int token, int nargs, int nret, int *outputs, ...);
void rtas_call_unlocked(struct rtas_args *args, int token, int nargs,
int nret, ...);
extern void __noreturn rtas_restart(char *cmd);
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 3f91ccaa9c74..04855ad455c7 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include "setup.h"
@@ -164,6 +165,32 @@ static struct slb_shadow * __init new_slb_shadow(int cpu,
unsigned long limit)
#endif /* CONFIG_PPC_BOOK3S_64 */
+#ifdef CONFIG_PPC_RTAS
+
+/**
+ * new_rtas_args() - Allocates rtas args
+ * @cpu: CPU number
+ * @limit: Memory limit for this allocation
+ *
+ * Allocates a struct rtas_args and return it's pointer,
+ * if not in Hypervisor mode
+ *
+ * Return: Pointer to allocated rtas_args
+ * NULL if CPU in Hypervisor Mode
+ */
+static struct rtas_args * __init new_rtas_args(int cpu, unsigned long limit)
+{
+ limit = min_t(unsigned long, limit, RTAS_INSTANTIATE_MAX);
+
+ if (early_cpu_has_feature(CPU_FTR_HVMODE))
+ return NULL;
+
+ return alloc_paca_data(sizeof(struct rtas_args), L1_CACHE_BYTES,
+ limit, cpu);
+}
+
+#endif /*CONFIG_PPC_RTAS*/
+
/* The Paca is an array with one entry per processor. Each contains an
* lppaca, which contains the information shared between the
* hypervisor and Linux.
@@ -202,6 +229,10 @@ void __init __nostackprotector initialise_paca(struct
paca_struct *new_paca, int
/* For now -- if we have threads this will be adjusted later */
new_paca->tcd_ptr = &new_paca->tcd;
#endif
+
+#ifdef CONFIG_PPC_RTAS
+ new_paca->rtas_args_reentrant = NULL;
+#endif
}
/* Put the paca pointer into r13 and SPRG_PACA */
@@ -273,6 +304,9 @@ void __init allocate_paca(int cpu)
#endif
#ifdef CONFIG_PPC_BOOK3S_64
paca->slb_shadow_ptr = new_slb_shadow(cpu, limit);
+#endif
+#ifdef CONFIG_PPC_RTAS
+ paca->rtas_args_reentrant = new_rtas_args(cpu, limit);
#endif
paca_struct_size += sizeof(struct paca_struct);
}
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index c5fa251b8950..7b8864abd1ab 100644
--- a/arch/powerpc/kernel/r
[PATCH v6 1/2] powerpc/rtas: Move type/struct definitions from rtas.h into rtas-types.h
In order to get any rtas* struct into other headers, including rtas.h
may cause a lot of errors, regarding include dependency needed for
inline functions.
Create rtas-types.h and move there all type/struct definitions
from rtas.h, then include rtas-types.h into rtas.h.
Also, as suggested by checkpath.pl, replace uint8_t for u8, and keep
the same type pattern for the whole file, as they are the same
according to powerpc/boot/types.h.
Signed-off-by: Leonardo Bras
---
arch/powerpc/include/asm/rtas-types.h | 126 ++
arch/powerpc/include/asm/rtas.h | 118 +---
2 files changed, 127 insertions(+), 117 deletions(-)
create mode 100644 arch/powerpc/include/asm/rtas-types.h
diff --git a/arch/powerpc/include/asm/rtas-types.h
b/arch/powerpc/include/asm/rtas-types.h
new file mode 100644
index ..87354e28f160
--- /dev/null
+++ b/arch/powerpc/include/asm/rtas-types.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef _POWERPC_RTAS_TYPES_H
+#define _POWERPC_RTAS_TYPES_H
+#ifdef __KERNEL__
+
+#include
+
+typedef __be32 rtas_arg_t;
+
+struct rtas_args {
+ __be32 token;
+ __be32 nargs;
+ __be32 nret;
+ rtas_arg_t args[16];
+ rtas_arg_t *rets; /* Pointer to return values in args[]. */
+};
+
+struct rtas_t {
+ unsigned long entry;/* physical address pointer */
+ unsigned long base; /* physical address pointer */
+ unsigned long size;
+ arch_spinlock_t lock;
+ struct rtas_args args;
+ struct device_node *dev;/* virtual address pointer */
+};
+
+struct rtas_suspend_me_data {
+ atomic_t working; /* number of cpus accessing this struct */
+ atomic_t done;
+ int token; /* ibm,suspend-me */
+ atomic_t error;
+ struct completion *complete; /* wait on this until working == 0 */
+};
+
+struct rtas_error_log {
+ /* Byte 0 */
+ u8 byte0; /* Architectural version */
+
+ /* Byte 1 */
+ u8 byte1;
+ /*
+* XXX 3: Severity level of error
+*XX2: Degree of recovery
+* X 1: Extended log present?
+* XX 2: Reserved
+*/
+
+ /* Byte 2 */
+ u8 byte2;
+ /*
+* 4: Initiator of event
+* 4: Target of failed operation
+*/
+ u8 byte3; /* General event or error*/
+ __be32 extended_log_length;/* length in bytes */
+ unsigned char buffer[1]; /* Start of extended log */
+ /* Variable length. */
+};
+
+/* RTAS general extended event log, Version 6. The extended log starts
+ * from "buffer" field of struct rtas_error_log defined above.
+ */
+struct rtas_ext_event_log_v6 {
+ /* Byte 0 */
+ u8 byte0;
+ /*
+* X1: Log valid
+* X 1: Unrecoverable error
+* X 1: Recoverable (correctable or successfully retried)
+*X 1: Bypassed unrecoverable error (degraded operation)
+* X1: Predictive error
+* X 1: "New" log (always 1 for data returned from RTAS)
+* X 1: Big Endian
+*X 1: Reserved
+*/
+
+ /* Byte 1 */
+ u8 byte1; /* reserved */
+
+ /* Byte 2 */
+ u8 byte2;
+ /*
+* X1: Set to 1 (indicating log is in PowerPC format)
+* XXX 3: Reserved
+* 4: Log format used for bytes 12-2047
+*/
+
+ /* Byte 3 */
+ u8 byte3; /* reserved */
+ /* Byte 4-11 */
+ u8 reserved[8]; /* reserved */
+ /* Byte 12-15 */
+ __be32 company_id; /* Company ID of the company*/
+ /* that defines the format for */
+ /* the vendor specific log type */
+ /* Byte 16-end of log */
+ u8 vendor_log[1]; /* Start of vendor specific log */
+ /* Variable length. */
+};
+
+/* Vendor specific Platform Event Log Format, Version 6, section header */
+struct pseries_errorlog {
+ __be16 id; /* 0x00 2-byte ASCII section ID */
+ __be16 length; /* 0x02 Section length in bytes */
+ u8 version; /* 0x04 Section version */
+ u8 subtype; /* 0x05 Section subtype */
+ __be16 creator_component; /* 0x06 Creator component ID*/
+ u8 data[]; /* 0x08 Start of section data */
+};
+
+/* RTAS pseries hotplug errorlog section */
+struct pse
[PATCH v6 0/2] Implement reentrant rtas call
Patch 2 implement rtas_call_reentrant() for reentrant rtas-calls: "ibm,int-on", "ibm,int-off",ibm,get-xive" and "ibm,set-xive", according to LoPAPR Version 1.1 (March 24, 2016). For that, it's necessary that every call uses a different rtas buffer (rtas_args). Paul Mackerras suggested using the PACA structure for creating a per-cpu buffer for these calls. Patch 1 was necessary to make PACA have a 'struct rtas_args' member. Reentrant rtas calls can be useful to avoid deadlocks in crashing, where rtas-calls are needed, but some other thread crashed holding the rtas.lock. This is a backtrace of a deadlock from a kdump testing environment: #0 arch_spin_lock #1 lock_rtas () #2 rtas_call (token=8204, nargs=1, nret=1, outputs=0x0) #3 ics_rtas_mask_real_irq (hw_irq=4100) #4 machine_kexec_mask_interrupts #5 default_machine_crash_shutdown #6 machine_crash_shutdown #7 __crash_kexec #8 crash_kexec #9 oops_end Signed-off-by: Leonardo Bras Special thanks to Nick Piggin, who have been helping me a lot with this series! --- Changes since v5: - Renames new paca member from reentrant_args to rtas_args_reentrant - Compile out rtas_args_reentrant if CONFIG_PPC_RTAS=n - new_rtas_args() is skipped (returns NULL) if CPU_FTR_HVMODE Changes since v4: - Insted of having the full buffer on PACA, adds only a pointer and allocate it during allocate_paca(), making sure it's in a memory range available for RTAS (32-bit). (Thanks Nick Piggin!) Changes since v3: - Adds protection from preemption and interruption Changes since v2: - Fixed build failure from ppc64e, by including spinlock_types.h on rtas-types.h - Improved commit messages Changes since v1: - Moved buffer from stack to PACA (as suggested by Paul Mackerras) - Added missing output bits - Improve documentation following kernel-doc format (as suggested by Nathan Lynch) Leonardo Bras (2): powerpc/rtas: Move type/struct definitions from rtas.h into rtas-types.h powerpc/rtas: Implement reentrant rtas call arch/powerpc/include/asm/paca.h | 2 + arch/powerpc/include/asm/rtas-types.h | 126 ++ arch/powerpc/include/asm/rtas.h | 119 +--- arch/powerpc/kernel/rtas.c| 42 + arch/powerpc/sysdev/xics/ics-rtas.c | 22 ++--- 5 files changed, 183 insertions(+), 128 deletions(-) create mode 100644 arch/powerpc/include/asm/rtas-types.h -- 2.25.4
[powerpc:next] BUILD SUCCESS 30df74d67d48949da87e3a5b57c381763e8fd526
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next branch HEAD: 30df74d67d48949da87e3a5b57c381763e8fd526 powerpc/watchpoint/xmon: Support 2nd DAWR elapsed time: 482m configs tested: 98 configs skipped: 1 The following configs have been built successfully. More configs may be tested in the coming days. arm defconfig arm allyesconfig arm allmodconfig arm allnoconfig arm64allyesconfig arm64 defconfig arm64allmodconfig arm64 allnoconfig m68k allyesconfig sparcallyesconfig mips allyesconfig i386 allnoconfig i386 allyesconfig i386defconfig i386 debian-10.3 ia64 allmodconfig ia64defconfig ia64 allnoconfig ia64 allyesconfig m68k allmodconfig m68k allnoconfig m68k sun3_defconfig m68kdefconfig nios2 defconfig nios2allyesconfig openriscdefconfig c6x allyesconfig c6x allnoconfig openrisc allyesconfig nds32 defconfig nds32 allnoconfig csky allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig h8300allmodconfig xtensa defconfig arc defconfig arc allyesconfig sh allmodconfig shallnoconfig microblazeallnoconfig mips allnoconfig mips allmodconfig pariscallnoconfig parisc defconfig parisc allyesconfig parisc allmodconfig powerpc defconfig powerpc allyesconfig powerpc rhel-kconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a006-20200518 i386 randconfig-a005-20200518 i386 randconfig-a001-20200518 i386 randconfig-a003-20200518 i386 randconfig-a004-20200518 i386 randconfig-a002-20200518 x86_64 randconfig-a016-20200518 x86_64 randconfig-a012-20200518 x86_64 randconfig-a015-20200518 x86_64 randconfig-a013-20200518 x86_64 randconfig-a011-20200518 x86_64 randconfig-a014-20200518 i386 randconfig-a012-20200518 i386 randconfig-a014-20200518 i386 randconfig-a016-20200518 i386 randconfig-a011-20200518 i386 randconfig-a015-20200518 i386 randconfig-a013-20200518 riscvallyesconfig riscv allnoconfig riscv defconfig riscvallmodconfig s390 allyesconfig s390 allnoconfig s390 allmodconfig s390defconfig x86_64 defconfig sparc defconfig sparc64 defconfig sparc64 allnoconfig sparc64 allyesconfig sparc64 allmodconfig um allmodconfig umallnoconfig um allyesconfig um defconfig x86_64 rhel x86_64 rhel-7.6 x86_64rhel-7.6-kselftests x86_64 rhel-7.2-clear x86_64lkp x86_64 fedora-25 x86_64 kexec --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [PATCH v5 2/2] powerpc/rtas: Implement reentrant rtas call
On Sat, 2020-05-16 at 17:36 +1000, Nicholas Piggin wrote: > Good, I think this should work as you want now. Can you allocate it like > lppacas? Put it under PSERIES (and in the paca) and check for !HV? Sure, I will do that. > Oh and while there, could you prefix the name with rtas_? Sure, replacing reentrant_args with rtas_args_reentrant. > > Thanks, > Nick Thank you for the feedback! Leonardo Bras
Re: [PATCH v4 6/6] ramoops: Add max_reason optional field to ramoops DT node
On Mon, May 18, 2020 at 04:45:32PM -0600, Rob Herring wrote: > On Fri, May 15, 2020 at 12:44 PM Kees Cook wrote: > > > > From: Pavel Tatashin > > Subject still has 'max_reason'. > > > > > Currently, it is possible to dump kmsges for panic, or oops. > > With max_reason it is possible to dump messages for other > > And here. Ah yeah, this was, I think, describing the internal field name, but I see it would be less confusing to refer to this by the DT name. I will adjust it. Thanks! -Kees > > > kmesg_dump events, for example reboot, halt, shutdown, kexec. > > > > Signed-off-by: Pavel Tatashin > > Link: > > https://lore.kernel.org/lkml/20200506211523.15077-6-keesc...@chromium.org/ > > Signed-off-by: Kees Cook > > --- > > .../devicetree/bindings/reserved-memory/ramoops.txt | 13 +++-- > > 1 file changed, 11 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > > b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > > index 0eba562fe5c6..b7886fea368c 100644 > > --- a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > > +++ b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > > @@ -30,7 +30,7 @@ Optional properties: > > - ecc-size: enables ECC support and specifies ECC buffer size in bytes > >(defaults to 0: no ECC) > > > > -- record-size: maximum size in bytes of each dump done on oops/panic > > +- record-size: maximum size in bytes of each kmsg dump. > >(defaults to 0: disabled) > > > > - console-size: size in bytes of log buffer reserved for kernel messages > > @@ -45,7 +45,16 @@ Optional properties: > > - unbuffered: if present, use unbuffered mappings to map the reserved > > region > >(defaults to buffered mappings) > > > > -- no-dump-oops: if present, only dump panics (defaults to panics and oops) > > +- max-reason: if present, sets maximum type of kmsg dump reasons to store > > + (defaults to 2: log Oopses and Panics). This can be set to INT_MAX to > > + store all kmsg dumps. See include/linux/kmsg_dump.h KMSG_DUMP_* for other > > + kmsg dump reason values. Setting this to 0 (KMSG_DUMP_UNDEF), means the > > + reason filtering will be controlled by the printk.always_kmsg_dump boot > > + param: if unset, it will be KMSG_DUMP_OOPS, otherwise KMSG_DUMP_MAX. > > + > > +- no-dump-oops: deprecated, use max_reason instead. If present, and > > + max_reason is not specified, it is equivalent to max_reason = 1 > > And here (3 times). > > > + (KMSG_DUMP_PANIC). > > > > - flags: if present, pass ramoops behavioral flags (defaults to 0, > >see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). > > -- > > 2.20.1 > > -- Kees Cook
Re: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
On Mon, May 18, 2020 at 05:19:04PM -0500, Gustavo A. R. Silva wrote:
> The current codebase makes use of one-element arrays in the following
> form:
>
> struct something {
> int length;
> u8 data[1];
> };
>
> struct something *instance;
>
> instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
> instance->length = size;
> memcpy(instance->data, source, size);
>
> but the preferred mechanism to declare variable-length types such as
> these ones is a flexible array member[1][2], introduced in C99:
>
> struct foo {
> int stuff;
> struct boo array[];
> };
>
> By making use of the mechanism above, we will get a compiler warning
> in case the flexible array does not occur last in the structure, which
> will help us prevent some kind of undefined behavior bugs from being
> inadvertently introduced[3] to the codebase from now on. So, replace
> the one-element array with a flexible-array member.
>
> Also, make use of the new struct_size() helper to properly calculate the
> size of struct qe_firmware.
>
> This issue was found with the help of Coccinelle and, audited and fixed
> _manually_.
>
> [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
> [2] https://github.com/KSPP/linux/issues/21
> [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
>
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/soc/fsl/qe/qe.c | 4 ++--
> include/soc/fsl/qe/qe.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
> index 447146861c2c1..2df20d6f85fa4 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
> unsigned int i;
> unsigned int j;
> u32 crc;
> - size_t calc_size = sizeof(struct qe_firmware);
> + size_t calc_size;
> size_t length;
> const struct qe_header *hdr;
>
> @@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
> }
>
> /* Validate the length and check if there's a CRC */
> - calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
> + calc_size = struct_size(firmware, microcode, firmware->count);
>
> for (i = 0; i < firmware->count; i++)
> /*
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
> index e282ac01ec081..3feddfec9f87d 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -307,7 +307,7 @@ struct qe_firmware {
> u8 revision;/* The microcode version revision */
> u8 padding; /* Reserved, for alignment */
> u8 reserved[4]; /* Reserved, for future expansion */
> - } __attribute__ ((packed)) microcode[1];
> + } __packed microcode[];
> /* All microcode binaries should be located here */
> /* CRC32 should be located here, after the microcode binaries */
> } __attribute__ ((packed));
> --
> 2.26.2
>
Hm, looking at this code, I see a few other things that need to be
fixed:
1) drivers/tty/serial/ucc_uart.c does not do a be32_to_cpu() conversion
on the length test (understandably, a little-endian system has never run
this code since it's ppc specific), but it's still wrong:
if (firmware->header.length != fw->size) {
compare to the firmware loader:
length = be32_to_cpu(hdr->length);
2) drivers/soc/fsl/qe/qe.c does not perform bounds checking on the
per-microcode offsets, so the uploader might send data outside the
firmware buffer. Perhaps:
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 447146861c2c..c4e0bc452f03 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -451,6 +451,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
+ void *firmware_end;
if (!firmware) {
printk(KERN_ERR "qe-firmware: invalid pointer\n");
@@ -491,19 +492,39 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
calc_size += sizeof(__be32) *
be32_to_cpu(firmware->microcode[i].count);
- /* Validate the length */
+ /* Validate total length */
if (length != calc_size + sizeof(__be32)) {
printk(KERN_ERR "qe-firmware: invalid length\n");
return -EPERM;
}
/* Validate the CRC */
- crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
+ firmware_end = (void *)firmware + calc_size;
+ crc = be32_to_cpu(*(__be32 *)firmware_end);
if (crc != crc32(0, firmware, calc_size)) {
printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
return -EIO;
}
+ /* Validate ucode lengths and offsets */
+ for (i = 0; i < firmware->count; i++) {
+ const
Re: [PATCH v4 6/6] ramoops: Add max_reason optional field to ramoops DT node
On Fri, May 15, 2020 at 12:44 PM Kees Cook wrote: > > From: Pavel Tatashin Subject still has 'max_reason'. > > Currently, it is possible to dump kmsges for panic, or oops. > With max_reason it is possible to dump messages for other And here. > kmesg_dump events, for example reboot, halt, shutdown, kexec. > > Signed-off-by: Pavel Tatashin > Link: > https://lore.kernel.org/lkml/20200506211523.15077-6-keesc...@chromium.org/ > Signed-off-by: Kees Cook > --- > .../devicetree/bindings/reserved-memory/ramoops.txt | 13 +++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > index 0eba562fe5c6..b7886fea368c 100644 > --- a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > +++ b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt > @@ -30,7 +30,7 @@ Optional properties: > - ecc-size: enables ECC support and specifies ECC buffer size in bytes >(defaults to 0: no ECC) > > -- record-size: maximum size in bytes of each dump done on oops/panic > +- record-size: maximum size in bytes of each kmsg dump. >(defaults to 0: disabled) > > - console-size: size in bytes of log buffer reserved for kernel messages > @@ -45,7 +45,16 @@ Optional properties: > - unbuffered: if present, use unbuffered mappings to map the reserved region >(defaults to buffered mappings) > > -- no-dump-oops: if present, only dump panics (defaults to panics and oops) > +- max-reason: if present, sets maximum type of kmsg dump reasons to store > + (defaults to 2: log Oopses and Panics). This can be set to INT_MAX to > + store all kmsg dumps. See include/linux/kmsg_dump.h KMSG_DUMP_* for other > + kmsg dump reason values. Setting this to 0 (KMSG_DUMP_UNDEF), means the > + reason filtering will be controlled by the printk.always_kmsg_dump boot > + param: if unset, it will be KMSG_DUMP_OOPS, otherwise KMSG_DUMP_MAX. > + > +- no-dump-oops: deprecated, use max_reason instead. If present, and > + max_reason is not specified, it is equivalent to max_reason = 1 And here (3 times). > + (KMSG_DUMP_PANIC). > > - flags: if present, pass ramoops behavioral flags (defaults to 0, >see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). > -- > 2.20.1 >
[PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
The current codebase makes use of one-element arrays in the following
form:
struct something {
int length;
u8 data[1];
};
struct something *instance;
instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
instance->length = size;
memcpy(instance->data, source, size);
but the preferred mechanism to declare variable-length types such as
these ones is a flexible array member[1][2], introduced in C99:
struct foo {
int stuff;
struct boo array[];
};
By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on. So, replace
the one-element array with a flexible-array member.
Also, make use of the new struct_size() helper to properly calculate the
size of struct qe_firmware.
This issue was found with the help of Coccinelle and, audited and fixed
_manually_.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
Signed-off-by: Gustavo A. R. Silva
---
drivers/soc/fsl/qe/qe.c | 4 ++--
include/soc/fsl/qe/qe.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 447146861c2c1..2df20d6f85fa4 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
unsigned int i;
unsigned int j;
u32 crc;
- size_t calc_size = sizeof(struct qe_firmware);
+ size_t calc_size;
size_t length;
const struct qe_header *hdr;
@@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
}
/* Validate the length and check if there's a CRC */
- calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
+ calc_size = struct_size(firmware, microcode, firmware->count);
for (i = 0; i < firmware->count; i++)
/*
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index e282ac01ec081..3feddfec9f87d 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -307,7 +307,7 @@ struct qe_firmware {
u8 revision;/* The microcode version revision */
u8 padding; /* Reserved, for alignment */
u8 reserved[4]; /* Reserved, for future expansion */
- } __attribute__ ((packed)) microcode[1];
+ } __packed microcode[];
/* All microcode binaries should be located here */
/* CRC32 should be located here, after the microcode binaries */
} __attribute__ ((packed));
--
2.26.2
Re: [PATCH 16/21] mm: remove early_pfn_in_nid() and CONFIG_NODES_SPAN_OTHER_NODES
Hi Mike and Baoquan,
On 4/22/20 6:13 PM, Baoquan He wrote:
On 04/12/20 at 10:48pm, Mike Rapoport wrote:
From: Mike Rapoport
The commit f47ac088c406 ("mm: memmap_init: iterate over memblock regions
This commit id should be a temporary one, will be changed when merged
into maintainer's tree and linus's tree. Only saying last patch plus the
patch subject is OK?
rather that check each PFN") made early_pfn_in_nid() obsolete and since
CONFIG_NODES_SPAN_OTHER_NODES is only used to pick a stub or a real
implementation of early_pfn_in_nid() it is also not needed anymore.
Remove both early_pfn_in_nid() and the CONFIG_NODES_SPAN_OTHER_NODES.
Co-developed-by: Hoan Tran
Signed-off-by: Hoan Tran
Signed-off-by: Mike Rapoport
---
arch/powerpc/Kconfig | 9 -
arch/sparc/Kconfig | 9 -
arch/x86/Kconfig | 9 -
mm/page_alloc.c | 20
4 files changed, 47 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 5f86b22b7d2c..74f316deeae1 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -685,15 +685,6 @@ config ARCH_MEMORY_PROBE
def_bool y
depends on MEMORY_HOTPLUG
-# Some NUMA nodes have memory ranges that span
-# other nodes. Even though a pfn is valid and
-# between a node's start and end pfns, it may not
-# reside on that node. See memmap_init_zone()
-# for details.
-config NODES_SPAN_OTHER_NODES
- def_bool y
- depends on NEED_MULTIPLE_NODES
-
config STDBINUTILS
bool "Using standard binutils settings"
depends on 44x
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 795206b7b552..0e4f3891b904 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -286,15 +286,6 @@ config NODES_SHIFT
Specify the maximum number of NUMA Nodes available on the target
system. Increases memory reserved to accommodate various tables.
-# Some NUMA nodes have memory ranges that span
-# other nodes. Even though a pfn is valid and
-# between a node's start and end pfns, it may not
-# reside on that node. See memmap_init_zone()
-# for details.
-config NODES_SPAN_OTHER_NODES
- def_bool y
- depends on NEED_MULTIPLE_NODES
-
config ARCH_SPARSEMEM_ENABLE
def_bool y if SPARC64
select SPARSEMEM_VMEMMAP_ENABLE
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d3e95b4fb85..37dac095659e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1581,15 +1581,6 @@ config X86_64_ACPI_NUMA
---help---
Enable ACPI SRAT based node topology detection.
-# Some NUMA nodes have memory ranges that span
-# other nodes. Even though a pfn is valid and
-# between a node's start and end pfns, it may not
-# reside on that node. See memmap_init_zone()
-# for details.
-config NODES_SPAN_OTHER_NODES
- def_bool y
- depends on X86_64_ACPI_NUMA
-
config NUMA_EMU
bool "NUMA emulation"
depends on NUMA
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index c43ce8709457..343d87b8697d 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -1541,26 +1541,6 @@ int __meminit early_pfn_to_nid(unsigned long pfn)
}
#endif /* CONFIG_NEED_MULTIPLE_NODES */
-#ifdef CONFIG_NODES_SPAN_OTHER_NODES
-/* Only safe to use early in boot when initialisation is single-threaded */
-static inline bool __meminit early_pfn_in_nid(unsigned long pfn, int node)
-{
- int nid;
-
- nid = __early_pfn_to_nid(pfn, &early_pfnnid_cache);
- if (nid >= 0 && nid != node)
- return false;
- return true;
-}
-
-#else
-static inline bool __meminit early_pfn_in_nid(unsigned long pfn, int node)
-{
- return true;
-}
-#endif
And macro early_pfn_valid() is not needed either, we may need remove it
too.
Otherwise, removing NODES_SPAN_OTHER_NODES in this patch looks good.
Reviewed-by: Baoquan He
I have tested this patch set on Arm64, and it worked as expected with
the case where the node memory spans to other nodes or the old
NODES_SPAN_OTHER_NODES config.
Hope to the whole patch set will be upstream soon.
Thanks and Regards
Hoan
-
-
void __init memblock_free_pages(struct page *page, unsigned long pfn,
unsigned int order)
{
--
2.25.1
Re: [RFC][PATCH 1/2] Add a layer of abstraction to use the memory reserved by device tree for ima buffer pass.
On 5/12/20 4:09 PM, Rob Herring wrote: On Mon, May 04, 2020 at 01:38:28PM -0700, Prakhar Srivastava wrote: Introduce a device tree layer for to read and store ima buffer from the reserved memory section of a device tree. But why do I need 'a layer of abstraction'? I don't like them. This is a common path for the all architectures to carry over the IMA measurement logs. A single layer will avoid any code duplication. Signed-off-by: Prakhar Srivastava --- drivers/of/Kconfig | 6 ++ drivers/of/Makefile | 1 + drivers/of/of_ima.c | 165 Who are the users of this code and why does it need to be here? Most code for specific bindings are not in drivers/of/ but with the user. It doesn't sound like there's more than 1 user. Currently the path is exercised by arm64 kexec_file_load path. A slight restructuring is needed on the powerpc side to use the same code path and other architectures can follow to add carrying over IMA logs over kexec with just a few function calls. I have attempted to bring the code path down to the highest common layer, however please do suggest if i can move this some where else. Thanks, Prakhar include/linux/of.h | 34 + 4 files changed, 206 insertions(+) create mode 100644 drivers/of/of_ima.c
Re: [RFC][PATCH 0/2] Add support for using reserved memory for ima buffer pass
On 5/12/20 4:05 PM, Rob Herring wrote: On Wed, May 06, 2020 at 10:50:04PM -0700, Prakhar Srivastava wrote: Hi Mark, Please don't top post. This patch set currently only address the Pure DT implementation. EFI and ACPI implementations will be posted in subsequent patchsets. The logs are intended to be carried over the kexec and once read the logs are no longer needed and in prior conversation with James( https://lore.kernel.org/linux-arm-kernel/0053eb68-0905-4679-c97a-00c5cb6f1...@arm.com/) the apporach of using a chosen node doesn't support the case. The DT entries make the reservation permanent and thus doesnt need kernel segments to be used for this, however using a chosen-node with reserved memory only changes the node information but memory still is reserved via reserved-memory section. I think Mark's point was whether it needs to be permanent. We don't hardcode the initrd address for example. Thankyou for clarifying my misunderstanding, i am modelling this keeping to the TPM log implementation that uses a reserved memory. I will rev up the version with chosen-node support. That will make the memory reservation free after use. On 5/5/20 2:59 AM, Mark Rutland wrote: Hi Prakhar, On Mon, May 04, 2020 at 01:38:27PM -0700, Prakhar Srivastava wrote: IMA during kexec(kexec file load) verifies the kernel signature and measures What's IMAIMA is a LSM attempting to detect if files have been accidentally or maliciously altered, both remotely and locally, it can also be used to appraise a file's measurement against a "good" value stored as an extended attribute, and enforce local file integrity. IMA also validates and measures the signers of the kernel and initrd during kexec. The measurements are extended to PCR 10(configurable) and the logs stored in memory, however once kexec'd the logs are lost. Kexec is used as secondary boot loader in may use cases and loosing the signer creates a security hole. This patch is an implementation to carry over the logs and making it possible to remotely validate the signers of the kernel and initrd. Such a support exits only in powerpc. This patch makes the carry over of logs architecture independent and puts the complexity in a driver. Thanks, Prakhar the signature of the kernel. The signature in the logs can be used to verfiy the authenticity of the kernel. The logs don not get carried over kexec and thus remote attesation cannot verify the signature of the running kernel. Introduce an ABI to carry forward the ima logs over kexec. Memory reserved via device tree reservation can be used to store and read via the of_* functions. This flow needs to work for: 1) Pure DT 2) DT + EFI memory map 3) ACPI + EFI memory map ... and if this is just for transiently passing the log, I don't think that a reserved memory region is the right thing to use, since they're supposed to be more permanent. This sounds analogous to passing the initrd, and should probably use properties under the chosen node (which can be used for all three boot flows above). For reference, how big is the IMA log likely to be? Does it need physically contiguous space? It purely depends on the policy used and the modules/files that are accessed for my local testing over a kexec session the log in about 30KB. Current implementation expects enough contiguous memory to allocated to carry forward the logs. If the log size exceeds the reserved memory the call will fail. Thanks, Prakhar Srivastava Thanks, Mark. Reserved memory stores the size(sizeof(size_t)) of the buffer in the starting address, followed by the IMA log contents. Tested on: arm64 with Uboot Prakhar Srivastava (2): Add a layer of abstraction to use the memory reserved by device tree for ima buffer pass. Add support for ima buffer pass using reserved memory for arm64 kexec. Update the arch sepcific code path in kexec file load to store the ima buffer in the reserved memory. The same reserved memory is read on kexec or cold boot. arch/arm64/Kconfig | 1 + arch/arm64/include/asm/ima.h | 22 arch/arm64/include/asm/kexec.h | 5 + arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/ima_kexec.c | 64 ++ arch/arm64/kernel/machine_kexec_file.c | 1 + arch/powerpc/include/asm/ima.h | 3 +- arch/powerpc/kexec/ima.c | 14 ++- drivers/of/Kconfig | 6 + drivers/of/Makefile| 1 + drivers/of/of_ima.c| 165 + include/linux/of.h | 34 + security/integrity/ima/ima_kexec.c | 15 ++- 13 files changed, 325 insertions(+), 7 deletions(-) create mode 100644 arch/arm64/include/asm/ima.h create mode 100644 arch/arm64/kernel/ima_kexec.c create mode 100644 drivers/of/of_ima.c -- 2.25.1
[PATCH] arch/{mips, sparc, microblaze, powerpc}: Don't enable pagefault/preempt twice
From: Ira Weiny
The kunmap_atomic clean up failed to remove one set of pagefault/preempt
enables when vaddr is not in the fixmap.
Fixes: bee2128a09e6 ("arch/kunmap_atomic: consolidate duplicate code")
Signed-off-by: Ira Weiny
---
arch/microblaze/mm/highmem.c | 5 +
arch/mips/mm/highmem.c | 5 +
arch/powerpc/mm/highmem.c| 5 +
arch/sparc/mm/highmem.c | 5 +
4 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/microblaze/mm/highmem.c b/arch/microblaze/mm/highmem.c
index ee8a422b2b76..92e0890416c9 100644
--- a/arch/microblaze/mm/highmem.c
+++ b/arch/microblaze/mm/highmem.c
@@ -57,11 +57,8 @@ void kunmap_atomic_high(void *kvaddr)
int type;
unsigned int idx;
- if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
- pagefault_enable();
- preempt_enable();
+ if (vaddr < __fix_to_virt(FIX_KMAP_END))
return;
- }
type = kmap_atomic_idx();
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 37e244cdb14e..8e8726992720 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -41,11 +41,8 @@ void kunmap_atomic_high(void *kvaddr)
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
int type __maybe_unused;
- if (vaddr < FIXADDR_START) { // FIXME
- pagefault_enable();
- preempt_enable();
+ if (vaddr < FIXADDR_START)
return;
- }
type = kmap_atomic_idx();
#ifdef CONFIG_DEBUG_HIGHMEM
diff --git a/arch/powerpc/mm/highmem.c b/arch/powerpc/mm/highmem.c
index 35071c2913f1..624b4438aff9 100644
--- a/arch/powerpc/mm/highmem.c
+++ b/arch/powerpc/mm/highmem.c
@@ -44,11 +44,8 @@ void kunmap_atomic_high(void *kvaddr)
{
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
- if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
- pagefault_enable();
- preempt_enable();
+ if (vaddr < __fix_to_virt(FIX_KMAP_END))
return;
- }
if (IS_ENABLED(CONFIG_DEBUG_HIGHMEM)) {
int type = kmap_atomic_idx();
diff --git a/arch/sparc/mm/highmem.c b/arch/sparc/mm/highmem.c
index d237d902f9c3..6ff6e2a9f9b3 100644
--- a/arch/sparc/mm/highmem.c
+++ b/arch/sparc/mm/highmem.c
@@ -86,11 +86,8 @@ void kunmap_atomic_high(void *kvaddr)
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
int type;
- if (vaddr < FIXADDR_START) { // FIXME
- pagefault_enable();
- preempt_enable();
+ if (vaddr < FIXADDR_START)
return;
- }
type = kmap_atomic_idx();
--
2.25.1
Re: [PATCH 10/29] c6x: use asm-generic/cacheflush.h
On Fri, 2020-05-15 at 16:36 +0200, Christoph Hellwig wrote:
> C6x needs almost no cache flushing routines of its own. Rely on
> asm-generic/cacheflush.h for the defaults.
>
> Signed-off-by: Christoph Hellwig
> ---
> arch/c6x/include/asm/cacheflush.h | 19 +--
> 1 file changed, 1 insertion(+), 18 deletions(-)
>
> diff --git a/arch/c6x/include/asm/cacheflush.h
> b/arch/c6x/include/asm/cacheflush.h
> index 4540b40475e6c..10922d528de6d 100644
> --- a/arch/c6x/include/asm/cacheflush.h
> +++ b/arch/c6x/include/asm/cacheflush.h
> @@ -16,21 +16,6 @@
> #include
> #include
>
> -/*
> - * virtually-indexed cache management (our cache is physically indexed)
> - */
> -#define flush_cache_all()do {} while (0)
> -#define flush_cache_mm(mm) do {} while (0)
> -#define flush_cache_dup_mm(mm) do {} while (0)
> -#define flush_cache_range(mm, start, end)do {} while (0)
> -#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
> -#define flush_cache_vmap(start, end) do {} while (0)
> -#define flush_cache_vunmap(start, end) do {} while (0)
> -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
> -#define flush_dcache_page(page) do {} while (0)
> -#define flush_dcache_mmap_lock(mapping) do {} while (0)
> -#define flush_dcache_mmap_unlock(mapping)do {} while (0)
> -
> /*
> * physically-indexed cache management
> */
> @@ -49,14 +34,12 @@ do {
> \
> (unsigned long) page_address(page) + PAGE_SIZE)); \
> } while (0)
>
> -
> #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
> do { \
> memcpy(dst, src, len); \
> flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
> } while (0)
>
> -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
> - memcpy(dst, src, len)
> +#include
>
> #endif /* _ASM_C6X_CACHEFLUSH_H */
Acked-by: Mark Salter
Re: [PATCH V3 10/15] arch/kmap: Define kmap_atomic_prot() for all arch's
On Sun, May 17, 2020 at 10:37:22AM -0700, Guenter Roeck wrote: > Hi, > > On Thu, May 07, 2020 at 07:59:58AM -0700, ira.we...@intel.com wrote: > > From: Ira Weiny > > > > To support kmap_atomic_prot(), all architectures need to support > > protections passed to their kmap_atomic_high() function. Pass > > protections into kmap_atomic_high() and change the name to > > kmap_atomic_high_prot() to match. > > > > Then define kmap_atomic_prot() as a core function which calls > > kmap_atomic_high_prot() when needed. > > > > Finally, redefine kmap_atomic() as a wrapper of kmap_atomic_prot() with > > the default kmap_prot exported by the architectures. > > > > Reviewed-by: Christoph Hellwig > > Signed-off-by: Ira Weiny > > This patch causes a variety of crashes whem booting powerpc images in qemu. PowerPC has the same issue as microblaze and sparc. I'm preping a patch with all three fixed which fixes the kunmap_atomic clean up patch... Sorry for not seeing this last night... Hopefully this can explain all the problems. It is clearly a bug. Ira > > There are lots of warnings such as: > > WARNING: CPU: 0 PID: 0 at lib/locking-selftest.c:743 > irqsafe1_hard_spin_12+0x50/0xb0 > Modules linked in: > CPU: 0 PID: 0 Comm: swapper Tainted: GW > 5.7.0-rc5-next-20200515 #1 > NIP: c0660c7c LR: c0660c44 CTR: c0660c2c > REGS: c1223e68 TRAP: 0700 Tainted: GW > (5.7.0-rc5-next-20200515) > MSR: 00021000 CR: 28000224 XER: 2000 > > GPR00: c0669c78 c1223f20 c113d560 c0660c44 0001 c1223ea8 0001 > GPR08: 0001 fffc 88000222 > GPR16: c000 c1125084 > GPR24: c1125084 c123 c1879538 fffc 0001 c1011afc c123 > NIP [c0660c7c] irqsafe1_hard_spin_12+0x50/0xb0 > LR [c0660c44] irqsafe1_hard_spin_12+0x18/0xb0 > Call Trace: > [c1223f20] [c188] megasas_mgmt_info+0xee4/0x1008 (unreliable) > [c1223f40] [c0669c78] dotest+0x38/0x550 > [c1223f70] [c066aa4c] locking_selftest+0x8bc/0x1d54 > [c1223fa0] [c10e0bc8] start_kernel+0x3ec/0x510 > [c1223ff0] [c3a0] set_ivor+0x118/0x154 > Instruction dump: > 8142 38e80001 3d4a0001 2c08 9142 90e20488 40820008 91020470 > 8129 5529031e 7d290034 5529d97e <0f09> 3fe0c11c 3bff3964 3bff00ac > irq event stamp: 588 > hardirqs last enabled at (587): [] vprintk_emit+0x1b4/0x33c > hardirqs last disabled at (588): [] irqsafe1_hard_spin_12+0x18/0xb0 > softirqs last enabled at (0): [<>] 0x0 > softirqs last disabled at (0): [<>] 0x0 > ---[ end trace b18fe9e172f99d03 ]--- > > This is followed by: > > BUG: sleeping function called from invalid context at lib/mpi/mpi-pow.c:245 > in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 14, name: > cryptomgr_test > INFO: lockdep is turned off. > CPU: 0 PID: 14 Comm: cryptomgr_test Tainted: GW > 5.7.0-rc5-next-20200515 #1 > Call Trace: > [ce221b58] [c008755c] ___might_sleep+0x280/0x2a8 (unreliable) > [ce221b78] [c06bc524] mpi_powm+0x634/0xc50 > [ce221c38] [c05eafdc] rsa_dec+0x88/0x134 > [ce221c78] [c05f3b40] test_akcipher_one+0x678/0x804 > [ce221dc8] [c05f3d7c] alg_test_akcipher+0xb0/0x130 > [ce221df8] [c05ee674] alg_test.part.0+0xb4/0x458 > [ce221ed8] [c05ed2b0] cryptomgr_test+0x30/0x50 > [ce221ef8] [c007cd74] kthread+0x134/0x170 > [ce221f38] [c001433c] ret_from_kernel_thread+0x14/0x1c > Kernel panic - not syncing: Aiee, killing interrupt handler! > CPU: 0 PID: 14 Comm: cryptomgr_test Tainted: GW > 5.7.0-rc5-next-20200515 #1 > Call Trace: > [ce221e08] [c00530fc] panic+0x148/0x34c (unreliable) > [ce221e68] [c0056460] do_exit+0xac0/0xb40 > [ce221eb8] [c00f5be8] find_kallsyms_symbol_value+0x0/0x128 > [ce221ed8] [c05ed2d0] crypto_alg_put+0x0/0x70 > [ce221ef8] [c007cd74] kthread+0x134/0x170 > [ce221f38] [c001433c] ret_from_kernel_thread+0x14/0x1c > > Bisect log is attached. The patch can not easily be reverted since > it results in compile errors. > > Note that similar failures are seen with sparc32 images. Those bisect > to a different patch, but reverting that patch doesn't fix the problem. > The failure pattern (warnings followed by a crash in cryptomgr_test) > is the same. > > Guenter > > --- > # bad: [bdecf38f228bcca73b31ada98b5b7ba1215eb9c9] Add linux-next specific > files for 20200515 > # good: [2ef96a5bb12be62ef75b5828c0aab838ebb29cb8] Linux 5.7-rc5 > git bisect start 'HEAD' 'v5.7-rc5' > # good: [3674d7aa7a8e61d993886c2fb7c896c5ef85e988] Merge remote-tracking > branch 'crypto/master' > git bisect good 3674d7aa7a8e61d993886c2fb7c896c5ef85e988 > # good: [87f6f21783522e6d62127cf33ae5e95f50874beb] Merge remote-tracking > branch 'spi/for-next' > git bisect good 87f6f21783522e6d62127cf33ae5e95f50874beb > # good: [5c428e8277d5d97c85126387d4e00aa5adde4400] Merge remote-tracking > branch 'staging/staging-next' > git bisect good 5c428e8277d5d97c85126387d4e00aa5adde4400 > # good: [f68de67ed934e7b
Re: [PATCH V3 07/15] arch/kunmap_atomic: Consolidate duplicate code
On Sun, May 17, 2020 at 09:29:32PM -0700, Guenter Roeck wrote:
> On Sun, May 17, 2020 at 08:49:39PM -0700, Ira Weiny wrote:
> > On Sat, May 16, 2020 at 03:33:06PM -0700, Guenter Roeck wrote:
> > > On Thu, May 07, 2020 at 07:59:55AM -0700, ira.we...@intel.com wrote:
> > > > From: Ira Weiny
> > > >
> > > > Every single architecture (including !CONFIG_HIGHMEM) calls...
> > > >
> > > > pagefault_enable();
> > > > preempt_enable();
> > > >
> > > > ... before returning from __kunmap_atomic(). Lift this code into the
> > > > kunmap_atomic() macro.
> > > >
> > > > While we are at it rename __kunmap_atomic() to kunmap_atomic_high() to
> > > > be consistent.
> > > >
> > > > Reviewed-by: Christoph Hellwig
> > > > Signed-off-by: Ira Weiny
> > >
> > > This patch results in:
> > >
> > > Starting init: /bin/sh exists but couldn't execute it (error -14)
> > >
> > > when trying to boot microblazeel:petalogix-ml605 in qemu.
> >
> > Thanks for the report. I'm not readily seeing the issue.
> >
> > Do you have a kernel config? Specifically is CONFIG_HIGHMEM set?
> >
> See below. Yes, CONFIG_HIGHMEM is set.
>
> The scripts used to build and boot the image are at:
>
> https://github.com/groeck/linux-build-test/tree/master/rootfs/microblazeel
>
> Hope this helps,
Thank you ...
Could you try the following patch?
commit 82c284b2bb74ca195dfcd35b70a175f010b9fd46 (HEAD -> lm-kmap17)
Author: Ira Weiny
Date: Mon May 18 11:01:10 2020 -0700
microblaze/kmap: Don't enable pagefault/preempt twice
The kunmap_atomic clean up failed to remove the pagefault/preempt
enables on this path.
Fixes: bee2128a09e6 ("arch/kunmap_atomic: consolidate duplicate code")
Signed-off-by: Ira Weiny
diff --git a/arch/microblaze/mm/highmem.c b/arch/microblaze/mm/highmem.c
index ee8a422b2b76..92e0890416c9 100644
--- a/arch/microblaze/mm/highmem.c
+++ b/arch/microblaze/mm/highmem.c
@@ -57,11 +57,8 @@ void kunmap_atomic_high(void *kvaddr)
int type;
unsigned int idx;
- if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
- pagefault_enable();
- preempt_enable();
+ if (vaddr < __fix_to_virt(FIX_KMAP_END))
return;
- }
type = kmap_atomic_idx();
[PATCH] input: i8042: Remove special PowerPC handling
This causes a build error with CONFIG_WALNUT because kb_cs and kb_data
were removed in commit 917f0af9e5a9 ("powerpc: Remove arch/ppc and
include/asm-ppc").
ld.lld: error: undefined symbol: kb_cs
> referenced by i8042-ppcio.h:28 (drivers/input/serio/i8042-ppcio.h:28)
> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
> referenced by i8042-ppcio.h:28 (drivers/input/serio/i8042-ppcio.h:28)
> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
> referenced by i8042-ppcio.h:28 (drivers/input/serio/i8042-ppcio.h:28)
> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
ld.lld: error: undefined symbol: kb_data
> referenced by i8042.c:309 (drivers/input/serio/i8042.c:309)
> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
> referenced by i8042-ppcio.h:33 (drivers/input/serio/i8042-ppcio.h:33)
> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
> referenced by i8042.c:319 (drivers/input/serio/i8042.c:319)
> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
> referenced 15 more times
Presumably since nobody has noticed this for the last 12 years, there is
not anyone actually trying to use this driver so we can just remove this
special walnut code and use the generic header so it builds for all
configurations.
Fixes: 917f0af9e5a9 ("powerpc: Remove arch/ppc and include/asm-ppc")
Reported-by: kbuild test robot
Signed-off-by: Nathan Chancellor
---
drivers/input/serio/i8042-ppcio.h | 57 ---
drivers/input/serio/i8042.h | 2 --
2 files changed, 59 deletions(-)
delete mode 100644 drivers/input/serio/i8042-ppcio.h
diff --git a/drivers/input/serio/i8042-ppcio.h
b/drivers/input/serio/i8042-ppcio.h
deleted file mode 100644
index 391f94d9e47d..
--- a/drivers/input/serio/i8042-ppcio.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _I8042_PPCIO_H
-#define _I8042_PPCIO_H
-
-
-#if defined(CONFIG_WALNUT)
-
-#define I8042_KBD_IRQ 25
-#define I8042_AUX_IRQ 26
-
-#define I8042_KBD_PHYS_DESC "walnutps2/serio0"
-#define I8042_AUX_PHYS_DESC "walnutps2/serio1"
-#define I8042_MUX_PHYS_DESC "walnutps2/serio%d"
-
-extern void *kb_cs;
-extern void *kb_data;
-
-#define I8042_COMMAND_REG (*(int *)kb_cs)
-#define I8042_DATA_REG (*(int *)kb_data)
-
-static inline int i8042_read_data(void)
-{
- return readb(kb_data);
-}
-
-static inline int i8042_read_status(void)
-{
- return readb(kb_cs);
-}
-
-static inline void i8042_write_data(int val)
-{
- writeb(val, kb_data);
-}
-
-static inline void i8042_write_command(int val)
-{
- writeb(val, kb_cs);
-}
-
-static inline int i8042_platform_init(void)
-{
- i8042_reset = I8042_RESET_ALWAYS;
- return 0;
-}
-
-static inline void i8042_platform_exit(void)
-{
-}
-
-#else
-
-#include "i8042-io.h"
-
-#endif
-
-#endif /* _I8042_PPCIO_H */
diff --git a/drivers/input/serio/i8042.h b/drivers/input/serio/i8042.h
index 38dc27ad3c18..eb376700dfff 100644
--- a/drivers/input/serio/i8042.h
+++ b/drivers/input/serio/i8042.h
@@ -17,8 +17,6 @@
#include "i8042-ip22io.h"
#elif defined(CONFIG_SNI_RM)
#include "i8042-snirm.h"
-#elif defined(CONFIG_PPC)
-#include "i8042-ppcio.h"
#elif defined(CONFIG_SPARC)
#include "i8042-sparcio.h"
#elif defined(CONFIG_X86) || defined(CONFIG_IA64)
base-commit: 72bc15d0018ebfbc9c389539d636e2e9a9002b3b
--
2.27.0.rc0
Re: [Regression 5.7-rc1] Random hangs on 32-bit PowerPC (PowerBook6, 7)
On Mon, 18 May 2020 at 18:15, Christophe Leroy wrote: > > Yeah I discovered recently that the way swap is implemented on powerpc > expects RW and other important bits not be one of the 3 least > significant bits (see __pte_to_swp_entry() ) I see, you get the swap entry by shifting the PTE right three bits. > I guess the easiest for the time being is to revert the commit with a > proper explanation of the issue, then one day we'll modify the way > powerpc manages swap. I wonder, what issues could be observable by reverting? I'm asking this because I've seen another hang on Linux 5.6, but it's harder to trigger and it involves the GPU (I usually reproduce it easily by, say, running Arctic Fox and starting a simple OpenGL game like Chromium BSU). Of course, since this is PowerPC with AGP (even though I have the AGP GART disabled), it's most likely something unrelated.
Re: [Regression 5.7-rc1] Random hangs on 32-bit PowerPC (PowerBook6,7)
Le 18/05/2020 à 17:19, Rui Salvaterra a écrit : Hi again, Christophe, On Mon, 18 May 2020 at 15:03, Christophe Leroy wrote: Can you try reverting 697ece78f8f749aeea40f2711389901f0974017a ? It may have broken swap. Yeah, that was a good call. :) Linux 5.7-rc1 with the revert on top survives the beating. I'll be happy to test a definitive patch! Yeah I discovered recently that the way swap is implemented on powerpc expects RW and other important bits not be one of the 3 least significant bits (see __pte_to_swp_entry() ) I guess the easiest for the time being is to revert the commit with a proper explanation of the issue, then one day we'll modify the way powerpc manages swap. Christophe
Re: [PATCH] ASoC: fsl_micfil: Fix unused assignment in fsl_set_clock_params()
On Mon, 18 May 2020 19:00:40 +0800, Tang Bin wrote: > Delete unused initialized value of 'ret', because it will > be assigned by the function fsl_micfil_set_mclk_rate(). Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.8 Thanks! [1/1] ASoC: fsl_micfil: Fix unused assignment in fsl_set_clock_params() commit: 15b5c496ff99ce99ab3c5e98e96981d015b3168a All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Re: [PATCH] ASoC: fsl_micfil: Fix indentation to put on one line affected code
On Mon, 18 May 2020 18:59:51 +0800, Tang Bin wrote: > In the function fsl_micfil_startup(), the two lines of dev_err() > can be shortened to one line. Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.8 Thanks! [1/1] ASoC: fsl_micfil: Fix indentation to put on one line affected code commit: 11106cb37ade76719bb3feac9fa6ba68173a38a0 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Re: [PATCH V3 07/15] arch/kunmap_atomic: Consolidate duplicate code
On Sun, May 17, 2020 at 08:49:39PM -0700, Ira Weiny wrote:
[ ... ]
> >
> > ---
> > # bad: [bdecf38f228bcca73b31ada98b5b7ba1215eb9c9] Add linux-next specific
> > files for 20200515
> > # good: [2ef96a5bb12be62ef75b5828c0aab838ebb29cb8] Linux 5.7-rc5
> > git bisect start 'HEAD' 'v5.7-rc5'
> > # good: [3674d7aa7a8e61d993886c2fb7c896c5ef85e988] Merge remote-tracking
> > branch 'crypto/master'
> > git bisect good 3674d7aa7a8e61d993886c2fb7c896c5ef85e988
> > # good: [87f6f21783522e6d62127cf33ae5e95f50874beb] Merge remote-tracking
> > branch 'spi/for-next'
> > git bisect good 87f6f21783522e6d62127cf33ae5e95f50874beb
> > # good: [5c428e8277d5d97c85126387d4e00aa5adde4400] Merge remote-tracking
> > branch 'staging/staging-next'
> > git bisect good 5c428e8277d5d97c85126387d4e00aa5adde4400
> > # good: [f68de67ed934e7bdef4799fdc86f33f14982] Merge remote-tracking
> > branch 'hyperv/hyperv-next'
> > git bisect good f68de67ed934e7bdef4799fdc86f33f14982
> > # bad: [54acd2dc52b069da59639eea0d0c92726f32fb01] mm/memblock: fix a typo
> > in comment "implict"->"implicit"
> > git bisect bad 54acd2dc52b069da59639eea0d0c92726f32fb01
> > # good: [784a17aa58a529b84f7cc50f351ed4acf3bd11f3] mm: remove the pgprot
> > argument to __vmalloc
> > git bisect good 784a17aa58a529b84f7cc50f351ed4acf3bd11f3
> > # good: [6cd8137ff37e9a37aee2d2a8889c8beb8eab192f] khugepaged: replace the
> > usage of system(3) in the test
> > git bisect good 6cd8137ff37e9a37aee2d2a8889c8beb8eab192f
> > # bad: [6987da379826ed01b8a1cf046b67cc8cc10117cc] sparc: remove unnecessary
> > includes
> > git bisect bad 6987da379826ed01b8a1cf046b67cc8cc10117cc
> > # good: [bc17b545388f64c09e83e367898e28f60277c584] mm/hugetlb: define a
> > generic fallback for is_hugepage_only_range()
> > git bisect good bc17b545388f64c09e83e367898e28f60277c584
> > # bad: [9b5aa5b43f957f03a1f4a9aff5f7924e2ebbc011]
> > arch-kmap_atomic-consolidate-duplicate-code-checkpatch-fixes
> > git bisect bad 9b5aa5b43f957f03a1f4a9aff5f7924e2ebbc011
> > # good: [0941a38ff0790c1004270f952067a5918a4ba32d] arch/kmap: remove
> > redundant arch specific kmaps
> > git bisect good 0941a38ff0790c1004270f952067a5918a4ba32d
> > # good: [56e635a64c2cbfa815c851af10e0f811e809977b]
> > arch-kunmap-remove-duplicate-kunmap-implementations-fix
> > git bisect good 56e635a64c2cbfa815c851af10e0f811e809977b
> > # bad: [60f96b2233c790d4f1c49317643051f1670bcb29] arch/kmap_atomic:
> > consolidate duplicate code
> > git bisect bad 60f96b2233c790d4f1c49317643051f1670bcb29
> > # good: [7b3708dc3bf72a647243064fe7ddf9a76248ddfd]
> > {x86,powerpc,microblaze}/kmap: move preempt disable
> > git bisect good 7b3708dc3bf72a647243064fe7ddf9a76248ddfd
> > # first bad commit: [60f96b2233c790d4f1c49317643051f1670bcb29]
> > arch/kmap_atomic: consolidate duplicate code
>
> I'm confused by this. This points to an earlier commit being bad?
>
Yes, you are correct. I was looking up the wrong commit; it had a similar
subject line. Sorry for the confusion.
Guenter
Re: [Regression 5.7-rc1] Random hangs on 32-bit PowerPC (PowerBook6, 7)
Hi again, Christophe, On Mon, 18 May 2020 at 15:03, Christophe Leroy wrote: > > Can you try reverting 697ece78f8f749aeea40f2711389901f0974017a ? It may > have broken swap. Yeah, that was a good call. :) Linux 5.7-rc1 with the revert on top survives the beating. I'll be happy to test a definitive patch! Thanks a lot, Rui
Re: [Regression 5.7-rc1] Random hangs on 32-bit PowerPC (PowerBook6,7)
Hi On 05/18/2020 01:25 PM, Rui Salvaterra wrote: Hi, Christophe, On Mon, 18 May 2020 at 12:50, Christophe Leroy wrote: Can you provide your .config, tell which GCC version you are using, and tell a bit more about your config: amount of RAM, is there swap, etc ... Ok, so this laptop has 1.5 GiB of RAM, with swap on zram (zstd compression, no backing device, no additional swap devices). I'm cross-compiling on my dual-core Power Mac G5 (since it's much faster than the iBook), running Debian ppc64, with GCC 9.3.0. Both 5.6 (good) and 5.7-rc1 (bad) configs are attached. Can you try reverting 697ece78f8f749aeea40f2711389901f0974017a ? It may have broken swap. Christophe
Re: [PATCH v2 2/2] powerpc/configs: replace deprecated riva/nvidia with nouveau
On Mai 18 2020, Michael Ellerman wrote: > The old drivers may be crufty but they presumably have been tested by > people and at least somewhat work. I can confirm that the nvidia fbdev driver is working perfectly fine. > I gave it a quick spin on a G5 I have access to and dmesg has a bunch of > errors in it (see below). I can't actually tell if the display is > working because the machine is remote, and I can't go and check it at > the moment because the office is closed. The nouveau driver is completely borked. [2.299204] nouveau :f0:10.0: NVIDIA NV34 (034100a2) [2.363100] nouveau :f0:10.0: bios: version 04.34.20.19.00 [2.363273] nouveau :f0:10.0: bios: OOB 1 0962 0962 [2.363323] nouveau :f0:10.0: bios: OOB 1 0966 0966 [2.363332] nouveau :f0:10.0: bios: OOB 1 0963 0963 [2.363341] nouveau :f0:10.0: bios: OOB 1 0964 0964 [2.363387] nouveau :f0:10.0: bios: OOB 1 096a 096a [2.363396] nouveau :f0:10.0: bios: OOB 1 0967 0967 [2.363405] nouveau :f0:10.0: bios: OOB 1 0968 0968 [2.363453] nouveau :f0:10.0: bios: OOB 1 096e 096e [2.363462] nouveau :f0:10.0: bios: OOB 1 096b 096b [2.363471] nouveau :f0:10.0: bios: OOB 1 096c 096c [2.363516] nouveau :f0:10.0: bios: OOB 1 0972 0972 [2.363526] nouveau :f0:10.0: bios: OOB 1 096f 096f [2.363534] nouveau :f0:10.0: bios: OOB 1 0970 0970 [2.363580] nouveau :f0:10.0: bios: OOB 1 0976 0976 [2.363589] nouveau :f0:10.0: bios: OOB 1 0973 0973 [2.363597] nouveau :f0:10.0: bios: OOB 1 0974 0974 [2.363643] nouveau :f0:10.0: bios: OOB 1 097a 097a [2.363652] nouveau :f0:10.0: bios: OOB 1 0977 0977 [2.363661] nouveau :f0:10.0: bios: OOB 1 0978 0978 [2.363709] nouveau :f0:10.0: bios: OOB 1 097e 097e [2.363718] nouveau :f0:10.0: bios: OOB 1 097b 097b [2.363727] nouveau :f0:10.0: bios: OOB 1 097c 097c [2.363772] nouveau :f0:10.0: bios: OOB 1 0982 0982 [2.363781] nouveau :f0:10.0: bios: OOB 1 097f 097f [2.363790] nouveau :f0:10.0: bios: OOB 1 0980 0980 [2.363836] nouveau :f0:10.0: bios: OOB 1 0986 0986 [2.363845] nouveau :f0:10.0: bios: OOB 1 0983 0983 [2.363854] nouveau :f0:10.0: bios: OOB 1 0984 0984 [2.363900] nouveau :f0:10.0: bios: OOB 1 098a 098a [2.363909] nouveau :f0:10.0: bios: OOB 1 0987 0987 [2.363918] nouveau :f0:10.0: bios: OOB 1 0988 0988 [2.363965] nouveau :f0:10.0: bios: OOB 1 098e 098e [2.363974] nouveau :f0:10.0: bios: OOB 1 098b 098b [2.363983] nouveau :f0:10.0: bios: OOB 1 098c 098c [2.364029] nouveau :f0:10.0: bios: OOB 1 0992 0992 [2.364038] nouveau :f0:10.0: bios: OOB 1 098f 098f [2.364047] nouveau :f0:10.0: bios: OOB 1 0990 0990 [2.364383] nouveau :f0:10.0: gpio: GPU is missing power, check its power cables. Boot with nouveau.config=NvPowerChecks=0 to disable. [2.364402] nouveau :f0:10.0: gpio: init failed, -22 [2.364431] nouveau :f0:10.0: init failed with -22 [2.364438] nouveau: DRM-master::0080: init failed with -22 [2.364450] nouveau :f0:10.0: DRM-master: Device allocation failed: -22 [2.365268] nouveau: probe of :f0:10.0 failed with error -22 Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."
Remove WALNUT hacks in serio/i8042 (was Re: ld.lld: error: undefined symbol: kb_cs)
[ Cc += linuxppc-dev ]
Nathan Chancellor writes:
> On Thu, May 14, 2020 at 08:13:48AM +0800, kbuild test robot wrote:
>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>> master
>> head: 24085f70a6e1b0cb647ec92623284641d8270637
>> commit: 5990cdee689c6885b27c6d969a3d58b09002b0bc lib/mpi: Fix building for
>> powerpc with clang
>
> I am certain that this patch did nothing to cause this... Maybe exposed
> it but not the root cause.
>
>> date: 3 weeks ago
>> config: powerpc-randconfig-r034-20200514 (attached as .config)
>> compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project
>> 310d32cb80a611e6384a921e85607fea05841f26)
>> reproduce:
>> wget
>> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
>> ~/bin/make.cross
>> chmod +x ~/bin/make.cross
>> # install powerpc cross compiling tool for clang build
>> # apt-get install binutils-powerpc-linux-gnu
>> git checkout 5990cdee689c6885b27c6d969a3d58b09002b0bc
>> # save the attached .config to linux build tree
>> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
>> ARCH=powerpc
>>
>> If you fix the issue, kindly add following tag as appropriate
>> Reported-by: kbuild test robot
>>
>> All errors (new ones prefixed by >>):
>>
>> >> ld.lld: error: undefined symbol: kb_cs
>> >>> referenced by i8042-ppcio.h:28 (drivers/input/serio/i8042-ppcio.h:28)
>> >>> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
>> >>> referenced by i8042-ppcio.h:28 (drivers/input/serio/i8042-ppcio.h:28)
>> >>> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
>> >>> referenced by i8042-ppcio.h:28 (drivers/input/serio/i8042-ppcio.h:28)
>> >>> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
>> >>> referenced 45 more times
>> --
>> >> ld.lld: error: undefined symbol: kb_data
>> >>> referenced by i8042.c:309 (drivers/input/serio/i8042.c:309)
>> >>> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
>> >>> referenced by i8042-ppcio.h:33 (drivers/input/serio/i8042-ppcio.h:33)
>> >>> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
>> >>> referenced by i8042.c:319 (drivers/input/serio/i8042.c:319)
>> >>> input/serio/i8042.o:(__i8042_command) in archive drivers/built-in.a
>> >>> referenced 15 more times
>
> kb_cs and kb_data are declared as extern void pointers when
> CONFIG_WALNUT is set, which this config does. However, it looks like
> the definitions of these variables were removed in
> commit 917f0af9e5a9 ("powerpc: Remove arch/ppc and include/asm-ppc"),
> way back in 2.6.27-rc1... So presumably, this has been broken for 12
> years and nobody noticed?
Hmm, nice. 12 years is a pretty typical time frame for finding bugs in
the powerpc tree ... o_O
Our ppc40x_defconfig has CONFIG_SERIO=m, but explicitly disables
CONFIG_SERIO_I8042. And walnut_defconfig disables CONFIG_SERIO.
So I guess it has a PS2 controller but most folks didn't use it?
> Probably means there is a good amount of dead
> code that can be removed, or we could just avoid ever selecting this
> driver with CONFIG_WALNUT (if it does not actually work without the
> special handling from i8042-ppcio.h) while removing the dead code.
I'm inclined to let the driver be selected, rather than carry a wart for
it. I doubt anyone will ever turn it on explicitly, and if they do they
can have fun debugging it.
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 924c541a9260..59b2f655e39e 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -138,7 +138,7 @@ config PPC
> select ARCH_HAVE_NMI_SAFE_CMPXCHG
> select ARCH_KEEP_MEMBLOCK
> select ARCH_MIGHT_HAVE_PC_PARPORT
> - select ARCH_MIGHT_HAVE_PC_SERIO
> + select ARCH_MIGHT_HAVE_PC_SERIO if !WALNUT
> select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
> select ARCH_SUPPORTS_ATOMIC_RMW
> select ARCH_USE_BUILTIN_BSWAP
So I'd drop this hunk.
> diff --git a/drivers/input/serio/i8042-ppcio.h
> b/drivers/input/serio/i8042-ppcio.h
> deleted file mode 100644
> index 391f94d9e47d..
> --- a/drivers/input/serio/i8042-ppcio.h
> +++ /dev/null
> @@ -1,57 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -#ifndef _I8042_PPCIO_H
> -#define _I8042_PPCIO_H
> -
> -
> -#if defined(CONFIG_WALNUT)
> -
> -#define I8042_KBD_IRQ 25
> -#define I8042_AUX_IRQ 26
> -
> -#define I8042_KBD_PHYS_DESC "walnutps2/serio0"
> -#define I8042_AUX_PHYS_DESC "walnutps2/serio1"
> -#define I8042_MUX_PHYS_DESC "walnutps2/serio%d"
> -
> -extern void *kb_cs;
> -extern void *kb_data;
> -
> -#define I8042_COMMAND_REG (*(int *)kb_cs)
> -#define I8042_DATA_REG (*(int *)kb_data)
> -
> -static inline int i8042_read_data(void)
> -{
> - return readb(kb_data);
> -}
> -
> -static inline int i8042_read_status(void)
> -{
> - return readb(kb_cs);
> -}
> -
> -static inline void i8042_write_data(int
Re: [PATCH v2 2/2] powerpc/configs: replace deprecated riva/nvidia with nouveau
On Mon, 18 May 2020 at 13:48, Bartlomiej Zolnierkiewicz wrote: > > > On 5/18/20 1:19 PM, Emil Velikov wrote: > > Hi Michael, > > > > On Mon, 18 May 2020 at 08:30, Michael Ellerman wrote: > >> > >> Emil Velikov writes: > >>> As mentioned in earlier commit, the riva and nvidia fbdev drivers have > >>> seen no love over the years, are short on features and overall below par > >>> > >>> Users are encouraged to switch to the nouveau drm driver instead. > >>> > >>> v2: Split configs to separate patch, enable nouveau (Bartlomiej) > >>> > >>> Cc: Antonino Daplas > >>> Cc: Bartlomiej Zolnierkiewicz > >>> Cc: linux-fb...@vger.kernel.org > >>> Cc: dri-de...@lists.freedesktop.org > >>> Cc: Michael Ellerman > >>> Cc: Benjamin Herrenschmidt > >>> Cc: Paul Mackerras > >>> Cc: linuxppc-dev@lists.ozlabs.org > >>> Signed-off-by: Emil Velikov > >>> Acked-by: Daniel Vetter (v1) > >>> --- > >>> Hi all unless, there are objections I would prefer to merge this via > >>> the drm tree. > >> > >> Have you tested that the resulting kernels work on the relevant > >> hardware? > >> > > Sadly, no I haven't. I'm updating the defconfigs as requested by the > > fbdev maintainer. > > I've just noticed that v1 (patch #1/1) & v2 (patch #1/2) lack > Cc: to powerpc Maintainers so they cannot see the context of > changes in this patch. > Haven't see any instances of fbdev/drm patches being Cc to arch/ developers. As such I made sure the commit message illustrates 1/2 as clearly as possible. > Also you've proposed v1 yourself and it has already contained > modifications to defconfigs (removal of setting the config > options for the old drivers) in addition to marking the old > drivers as BROKEN. > > It now turns out that v1 has also never been tested. :( > > Please don't submit untested patches without marking them > as such. > Does x86 box with nv34 GPU count as testing? I suspect not :-( It was been using nouveau ever since I bought it 15+ years ago. Will be more careful in the future. -Emil
Re: [PATCH 29/29] module: move the set_fs hack for flush_icache_range to m68k
+++ Christoph Hellwig [15/05/20 16:36 +0200]: flush_icache_range generally operates on kernel addresses, but for some reason m68k needed a set_fs override. Move that into the m68k code insted of keeping it in the module loader. Signed-off-by: Christoph Hellwig Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven --- arch/m68k/mm/cache.c | 4 kernel/module.c | 8 2 files changed, 4 insertions(+), 8 deletions(-) Thanks for cleaning this up. For module.c: Acked-by: Jessica Yu
Re: [PATCH v2 2/2] powerpc/configs: replace deprecated riva/nvidia with nouveau
On 5/18/20 1:19 PM, Emil Velikov wrote: > Hi Michael, > > On Mon, 18 May 2020 at 08:30, Michael Ellerman wrote: >> >> Emil Velikov writes: >>> As mentioned in earlier commit, the riva and nvidia fbdev drivers have >>> seen no love over the years, are short on features and overall below par >>> >>> Users are encouraged to switch to the nouveau drm driver instead. >>> >>> v2: Split configs to separate patch, enable nouveau (Bartlomiej) >>> >>> Cc: Antonino Daplas >>> Cc: Bartlomiej Zolnierkiewicz >>> Cc: linux-fb...@vger.kernel.org >>> Cc: dri-de...@lists.freedesktop.org >>> Cc: Michael Ellerman >>> Cc: Benjamin Herrenschmidt >>> Cc: Paul Mackerras >>> Cc: linuxppc-dev@lists.ozlabs.org >>> Signed-off-by: Emil Velikov >>> Acked-by: Daniel Vetter (v1) >>> --- >>> Hi all unless, there are objections I would prefer to merge this via >>> the drm tree. >> >> Have you tested that the resulting kernels work on the relevant >> hardware? >> > Sadly, no I haven't. I'm updating the defconfigs as requested by the > fbdev maintainer. I've just noticed that v1 (patch #1/1) & v2 (patch #1/2) lack Cc: to powerpc Maintainers so they cannot see the context of changes in this patch. Also you've proposed v1 yourself and it has already contained modifications to defconfigs (removal of setting the config options for the old drivers) in addition to marking the old drivers as BROKEN. It now turns out that v1 has also never been tested. :( Please don't submit untested patches without marking them as such. >> The old drivers may be crufty but they presumably have been tested by >> people and at least somewhat work. >> >> So I'd be inclined to leave the defconfigs alone until someone can test >> that the new driver works at all. @Michael: Fully agreed. I would also like you to review/ack patch #1/2: https://lore.kernel.org/dri-devel/20200517220524.4036334-1-emil.l.veli...@gmail.com/ Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics > Works for me. > >> I gave it a quick spin on a G5 I have access to and dmesg has a bunch of >> errors in it (see below). I can't actually tell if the display is >> working because the machine is remote, and I can't go and check it at >> the moment because the office is closed. >> > >>From what I can see, there seems to be three bits: > - attempted out-of-bound attempts to read the vbios > Genuine concern or noise? Likely using the bios from open firmware, > check any of the other options - see NvBios in [1] > - cannot figure out the timer input frequency > No idea > - the TV1 EDID is empty > Is there an actual TV connected to the device, check with another cable > > Regardless of the patches, reporting [2] the above would be a nice move. > > Thanks > Emil > [1] > https://protect2.fireeye.com/url?k=d6cf7004-8b548c67-d6cefb4b-0cc47a31cdbc-7c3b251c170ed483&q=1&u=https%3A%2F%2Fnouveau.freedesktop.org%2Fwiki%2FKernelModuleParameters%2F > [2] https://gitlab.freedesktop.org/xorg/driver/xf86-video-nouveau/-/issues
Re: [PATCH v2 2/2] powerpc/configs: replace deprecated riva/nvidia with nouveau
On Mon, 2020-05-18 at 12:19 +0100, Emil Velikov wrote: > > - attempted out-of-bound attempts to read the vbios So on these things, the actual ROM doesn't contain what you want, but the device-tree has a property "NVDA,BMP" that contains some kind of mini-BIOS (around 2.4KB) which should contain the necessary tables the driver is looking for. I think nouveau has code to find these in nvkm/subdev/bios/shadowof.c, so at least that should have been working, but maybe some debugging/instrumentation would be useful there. > Genuine concern or noise? Likely using the bios from open firmware, > check any of the other options - see NvBios in [1] > - cannot figure out the timer input frequency > No idea > - the TV1 EDID is empty > Is there an actual TV connected to the device, check with another cable Probaby not. > Regardless of the patches, reporting [2] the above would be a nice move. > > Thanks > Emil > [1] https://nouveau.freedesktop.org/wiki/KernelModuleParameters/ > [2] https://gitlab.freedesktop.org/xorg/driver/xf86-video-nouveau/-/issues
Re: [PATCH v2 2/2] powerpc/configs: replace deprecated riva/nvidia with nouveau
On Mon, 2020-05-18 at 12:00 +0100, Emil Velikov wrote: > I believe you reported issues due to different page size for the CPU/GPU. > Have you tried nouveau recently, there has been a handful of patches > on the topic since your report. > > Alternatively, it would make sense you rebase, cleanup and merge your patch. That was a problem for the G5s. There were other issues for more ancient machines with older nVidia GPUs. Additionally a lot of those Apple machines don't have a BIOS ROM to get the various tables from. At this stage unfortunately I don't have access to most of that HW to test with anymore. I do have one G5 I might be able to dig out of my basement this week to try out. In any case, digging out that patch should be useful as powerpc64 is still 64k pages :) Cheers, Ben.
Re: [PATCH v3] powerpc/64: Option to use ELF V2 ABI for big-endian kernels
Hi! On Mon, May 18, 2020 at 04:35:22PM +1000, Michael Ellerman wrote: > Nicholas Piggin writes: > > Provide an option to build big-endian kernels using the ELF V2 ABI. This > > works > > on GCC and clang (since about 2014). it is is not officially supported by > > the > > GNU toolchain, but it can give big-endian kernels some useful advantages of > > the V2 ABI (e.g., less stack usage). > This doesn't build with clang: > > /tmp/aesp8-ppc-dad624.s: Assembler messages: > /tmp/aesp8-ppc-dad624.s: Error: .size expression for aes_p8_set_encrypt_key > does not evaluate to a constant What does this assembler code that clang doesn't swallow look like? Is that valid code? Etc. Segher
[PATCH v9 4/5] Documentation/ABI: Add ABI documentation for chips and sockets
Add documentation for the following sysfs files: /sys/devices/hv_24x7/interface/chipspersocket, /sys/devices/hv_24x7/interface/sockets, /sys/devices/hv_24x7/interface/coresperchip Signed-off-by: Kajol Jain --- .../sysfs-bus-event_source-devices-hv_24x7| 21 +++ 1 file changed, 21 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 index ec27c6c9e737..e8698afcd952 100644 --- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 @@ -22,6 +22,27 @@ Description: Exposes the "version" field of the 24x7 catalog. This is also extractable from the provided binary "catalog" sysfs entry. +What: /sys/devices/hv_24x7/interface/sockets +Date: May 2020 +Contact: Linux on PowerPC Developer List +Description: read only + This sysfs interface exposes the number of sockets present in the + system. + +What: /sys/devices/hv_24x7/interface/chipspersocket +Date: May 2020 +Contact: Linux on PowerPC Developer List +Description: read only + This sysfs interface exposes the number of chips per socket + present in the system. + +What: /sys/devices/hv_24x7/interface/coresperchip +Date: May 2020 +Contact: Linux on PowerPC Developer List +Description: read only + This sysfs interface exposes the number of cores per chip + present in the system. + What: /sys/bus/event_source/devices/hv_24x7/event_descs/ Date: February 2014 Contact: Linux on PowerPC Developer List -- 2.18.2
[PATCH v9 3/5] powerpc/hv-24x7: Add sysfs files inside hv-24x7 device to show processor details
To expose the system dependent parameter like total number of
sockets and numbers of chips per socket, patch adds two sysfs files.
"sockets" and "chips" are added to /sys/devices/hv_24x7/interface/
of the "hv_24x7" pmu.
Signed-off-by: Kajol Jain
---
arch/powerpc/perf/hv-24x7.c | 24
1 file changed, 24 insertions(+)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index b8625058c2aa..324fe7fe177c 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -456,6 +456,24 @@ static ssize_t device_show_string(struct device *dev,
return sprintf(buf, "%s\n", (char *)d->var);
}
+static ssize_t sockets_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", phys_sockets);
+}
+
+static ssize_t chipspersocket_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", phys_chipspersocket);
+}
+
+static ssize_t coresperchip_show(struct device *dev,
+struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", phys_coresperchip);
+}
+
static struct attribute *device_str_attr_create_(char *name, char *str)
{
struct dev_ext_attribute *attr = kzalloc(sizeof(*attr), GFP_KERNEL);
@@ -1102,6 +1120,9 @@ PAGE_0_ATTR(catalog_len, "%lld\n",
(unsigned long long)be32_to_cpu(page_0->length) * 4096);
static BIN_ATTR_RO(catalog, 0/* real length varies */);
static DEVICE_ATTR_RO(domains);
+static DEVICE_ATTR_RO(sockets);
+static DEVICE_ATTR_RO(chipspersocket);
+static DEVICE_ATTR_RO(coresperchip);
static struct bin_attribute *if_bin_attrs[] = {
&bin_attr_catalog,
@@ -1112,6 +1133,9 @@ static struct attribute *if_attrs[] = {
&dev_attr_catalog_len.attr,
&dev_attr_catalog_version.attr,
&dev_attr_domains.attr,
+ &dev_attr_sockets.attr,
+ &dev_attr_chipspersocket.attr,
+ &dev_attr_coresperchip.attr,
NULL,
};
--
2.18.2
[PATCH v9 5/5] powerpc/pseries: Update hv-24x7 information after migration
Function 'read_sys_info_pseries()' is added to get system parameter values like number of sockets and chips per socket. and it gets these details via rtas_call with token "PROCESSOR_MODULE_INFO". Incase lpar migrate from one system to another, system parameter details like chips per sockets or number of sockets might change. So, it needs to be re-initialized otherwise, these values corresponds to previous system values. This patch adds a call to 'read_sys_info_pseries()' from 'post-mobility_fixup()' to re-init the physsockets and physchips values Signed-off-by: Kajol Jain --- arch/powerpc/platforms/pseries/mobility.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/platforms/pseries/mobility.c b/arch/powerpc/platforms/pseries/mobility.c index b571285f6c14..3dd2f7f59d9a 100644 --- a/arch/powerpc/platforms/pseries/mobility.c +++ b/arch/powerpc/platforms/pseries/mobility.c @@ -371,6 +371,9 @@ void post_mobility_fixup(void) /* Possibly switch to a new RFI flush type */ pseries_setup_rfi_flush(); + /* Reinitialise system information for hv-24x7 */ + read_sys_info_pseries(); + return; } -- 2.18.2
[PATCH v9 2/5] powerpc/hv-24x7: Add rtas call in hv-24x7 driver to get processor details
For hv_24x7 socket/chip level events, specific chip-id to which
the data requested should be added as part of pmu events.
But number of chips/socket in the system details are not exposed.
Patch implements read_sys_info_pseries() to get system
parameter values like number of sockets, cores per chip and
chips per socket. Rtas_call with token "PROCESSOR_MODULE_INFO"
is used to get these values.
Sub-sequent patch exports these values via sysfs.
Patch also make these parameters default to 1.
Signed-off-by: Kajol Jain
---
arch/powerpc/include/asm/rtas.h | 6 +++
arch/powerpc/perf/hv-24x7.c | 72 +
2 files changed, 78 insertions(+)
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 3c1887351c71..a5b302180041 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -483,5 +483,11 @@ static inline void rtas_initialize(void) { };
extern int call_rtas(const char *, int, int, unsigned long *, ...);
+#ifdef CONFIG_HV_PERF_CTRS
+void read_sys_info_pseries(void);
+#else
+static inline void read_sys_info_pseries(void) { }
+#endif
+
#endif /* __KERNEL__ */
#endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 48e8f4b17b91..b8625058c2aa 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -20,6 +20,7 @@
#include
#include
+#include
#include "hv-24x7.h"
#include "hv-24x7-catalog.h"
#include "hv-common.h"
@@ -57,6 +58,75 @@ static bool is_physical_domain(unsigned domain)
}
}
+/*
+ * The Processor Module Information system parameter allows transferring
+ * of certain processor module information from the platform to the OS.
+ * Refer PAPR+ document to get parameter token value as '43'.
+ */
+
+#define PROCESSOR_MODULE_INFO 43
+
+static u32 phys_sockets; /* Physical sockets */
+static u32 phys_chipspersocket;/* Physical chips per socket*/
+static u32 phys_coresperchip; /* Physical cores per chip */
+
+
+/*
+ * read_sys_info_pseries()
+ * Retrieve the number of sockets, chips per socket and cores per
+ * chip details through the get-system-parameter rtas call.
+ */
+void read_sys_info_pseries(void)
+{
+ int call_status, len, ntypes;
+ char *rtas_local_data_buf = kmalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
+
+ if (!rtas_local_data_buf) {
+ printk(KERN_ERR "%s %s kmalloc failure at line %d\n",
+ __FILE__, __func__, __LINE__);
+ return;
+ }
+
+ /*
+* Making system parameter: chips per socket, sockets and cores per chip
+* default to 1.
+*/
+ spin_lock(&rtas_data_buf_lock);
+ phys_sockets = 1;
+ phys_chipspersocket = 1;
+ phys_coresperchip = 1;
+ memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE);
+
+ call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
+ NULL,
+ PROCESSOR_MODULE_INFO,
+ __pa(rtas_data_buf),
+ RTAS_DATA_BUF_SIZE);
+
+ memcpy(rtas_local_data_buf, rtas_data_buf, RTAS_DATA_BUF_SIZE);
+ rtas_local_data_buf[RTAS_DATA_BUF_SIZE - 1] = '\0';
+
+ spin_unlock(&rtas_data_buf_lock);
+
+ if (call_status != 0)
+ pr_err("Error calling get-system-parameter %d\n", call_status);
+ else {
+ len = be16_to_cpup((__be16 *)&rtas_local_data_buf[0]);
+ if (len < 8)
+ return;
+
+ ntypes = be16_to_cpup((__be16 *)&rtas_local_data_buf[2]);
+
+ if (!ntypes)
+ return;
+ phys_sockets = be16_to_cpup((__be16 *)&rtas_local_data_buf[4]);
+ phys_chipspersocket = be16_to_cpup((__be16
*)&rtas_local_data_buf[6]);
+ phys_coresperchip = be16_to_cpup((__be16
*)&rtas_local_data_buf[8]);
+ }
+
+ kfree(rtas_local_data_buf);
+}
+
/* Domains for which more than one result element are returned for each event.
*/
static bool domain_needs_aggregation(unsigned int domain)
{
@@ -1605,6 +1675,8 @@ static int hv_24x7_init(void)
if (r)
return r;
+ read_sys_info_pseries();
+
return 0;
}
--
2.18.2
[PATCH v9 1/5] powerpc/perf/hv-24x7: Fix inconsistent output values incase multiple hv-24x7 events run
Commit 2b206ee6b0df ("powerpc/perf/hv-24x7: Display change in counter
values")' added to print _change_ in the counter value rather then raw
value for 24x7 counters. Incase of transactions, the event count
is set to 0 at the beginning of the transaction. It also sets
the event's prev_count to the raw value at the time of initialization.
Because of setting event count to 0, we are seeing some weird behaviour,
whenever we run multiple 24x7 events at a time.
For example:
command#: ./perf stat -e "{hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/,
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/}"
-C 0 -I 1000 sleep 100
1.000121704120 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
1.000121704 5 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
2.000357733 8 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
2.000357733 10 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
3.000495215 18,446,744,073,709,551,616
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
3.000495215 18,446,744,073,709,551,616
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
4.000641884 56 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
4.000641884 18,446,744,073,709,551,616
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
5.000791887 18,446,744,073,709,551,616
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
Getting these large values in case we do -I.
As we are setting event_count to 0, for interval case, overall event_count is
not
coming in incremental order. As we may can get new delta lesser then previous
count.
Because of which when we print intervals, we are getting negative value which
create
these large values.
This patch removes part where we set event_count to 0 in function
'h_24x7_event_read'. There won't be much impact as we do set
event->hw.prev_count
to the raw value at the time of initialization to print change value.
With this patch
In power9 platform
command#: ./perf stat -e "{hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/,
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/}"
-C 0 -I 1000 sleep 100
1.000117685 93 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
1.000117685 1 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
2.000349331 98 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
2.000349331 2 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
3.000495900131 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
3.000495900 4 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
4.000645920204 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
4.000645920 61 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=1/
4.284169997 22 hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
Signed-off-by: Kajol Jain
Suggested-by: Sukadev Bhattiprolu
---
arch/powerpc/perf/hv-24x7.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 573e0b309c0c..48e8f4b17b91 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -1400,16 +1400,6 @@ static void h_24x7_event_read(struct perf_event *event)
h24x7hw = &get_cpu_var(hv_24x7_hw);
h24x7hw->events[i] = event;
put_cpu_var(h24x7hw);
- /*
-* Clear the event count so we can compute the _change_
-* in the 24x7 raw counter value at the end of the txn.
-*
-* Note that we could alternatively read the 24x7 value
-* now and save its value in event->hw.prev_count. But
-* that would require issuing a hcall, which would then
-* defeat the purpose of using the txn interface.
-*/
- local64_set(&event->count, 0);
}
put_cpu_var(hv_24x7_reqb);
--
2.18.2
[PATCH v9 0/5] powerpc/hv-24x7: Expose chip/sockets info to add json file metric support for the hv_24x7 socket/chip level events
Patchset fixes the inconsistent results we are getting when we run multiple 24x7 events. "hv_24x7" pmu interface events needs system dependent parameter like socket/chip/core. For example, hv_24x7 chip level events needs specific chip-id to which the data is requested should be added as part of pmu events. So to enable JSON file support to "hv_24x7" interface, patchset expose total number of sockets and chips per-socket details in sysfs files (sockets, chips) under "/sys/devices/hv_24x7/interface/". To get number of sockets, chips per sockets and cores per chip patchset adds a rtas call with token "PROCESSOR_MODULE_INFO" to get these details. Patchset also handles partition migration case to re-init these system depended parameters by adding proper calls in post_mobility_fixup() (mobility.c). Changelog: v8 -> v9 - As we not need 8k data buffer we also not require new lock and buffer size. So, removed that part. - Made more changes as suggested by Nathan Lynch. v7 -> v8 - Add support for exposing cores per details as well. Suggested by: Madhavan Srinivasan. - Remove config check for 'CONFIG_PPC_RTAS' in previous implementation and address other comments by Michael Ellerman. v6 -> v7 - Split patchset into two patch series, one with kernel changes and another with perf tool side changes. This pachset contain all kernel side changes. Kajol Jain (5): powerpc/perf/hv-24x7: Fix inconsistent output values incase multiple hv-24x7 events run powerpc/hv-24x7: Add rtas call in hv-24x7 driver to get processor details powerpc/hv-24x7: Add sysfs files inside hv-24x7 device to show processor details Documentation/ABI: Add ABI documentation for chips and sockets powerpc/pseries: Update hv-24x7 information after migration .../sysfs-bus-event_source-devices-hv_24x7| 21 arch/powerpc/include/asm/rtas.h | 6 + arch/powerpc/perf/hv-24x7.c | 106 -- arch/powerpc/platforms/pseries/mobility.c | 3 + 4 files changed, 126 insertions(+), 10 deletions(-) -- 2.18.2
Re: [Regression 5.7-rc1] Random hangs on 32-bit PowerPC (PowerBook6,7)
Hi, Le 18/05/2020 à 13:20, Rui Salvaterra a écrit : [Resending since I messed up the subject, sorry] Hi, everyone, Something went wrong between Linux 5.6 and 5.7-rc1. This is an iBook G4 laptop with 1.5 GiB of RAM running the Debian powerpc port. I haven't bisected yet, since it's going to take quite a bit of time, so I'm sending this mostly as a heads-up (and to see if anybody has any clues about the possible cause). I'm using the following reproducer: stress-ng --cpu 8 --io 8 --vm 8 --vm-bytes 1G --fork 8 --timeout 10m On Linux 5.7-rc1, this completely hangs the machine in about 30 seconds. Linux 5.6 survives the test. Let me know if I can provide any additional info, otherwise I'll just bite the bullet and start bisecting. Can you provide your .config, tell which GCC version you are using, and tell a bit more about your config: amount of RAM, is there swap, etc ...
Re: [PATCH] powerpc/sysdev: fix compile errors
Jiri Kosina writes:
> On Mon, 18 May 2020, Jiri Kosina wrote:
>> > > Include linux/io.h into fsl_85xx_cache_sram.c to fix the
>> > > implicit-declaration compile errors when building Cache-Sram.
>> > >
>> > > arch/powerpc/sysdev/fsl_85xx_cache_sram.c: In function
>> > > ‘instantiate_cache_sram’:
>> > > arch/powerpc/sysdev/fsl_85xx_cache_sram.c:97:26: error: implicit
>> > > declaration
>> > > of function ‘ioremap_coherent’; did you mean ‘bitmap_complement’?
>> > > [-Werror=implicit-function-declaration]
>> > >cache_sram->base_virt = ioremap_coherent(cache_sram->base_phys,
>> > >^~~~
>> > >bitmap_complement
>> > > arch/powerpc/sysdev/fsl_85xx_cache_sram.c:97:24: error: assignment makes
>> > > pointer from integer without a cast [-Werror=int-conversion]
>> > >cache_sram->base_virt = ioremap_coherent(cache_sram->base_phys,
>> > > ^
>> > > arch/powerpc/sysdev/fsl_85xx_cache_sram.c:123:2: error: implicit
>> > > declaration
>> > > of function ‘iounmap’; did you mean ‘roundup’?
>> > > [-Werror=implicit-function-declaration]
>> > >iounmap(cache_sram->base_virt);
>> > >^~~
>> > >roundup
>> > > cc1: all warnings being treated as errors
>> > >
>> > > Fixed: commit 6db92cc9d07d ("powerpc/85xx: add cache-sram support")
>> > > Signed-off-by: WANG Wenhu
>> >
>> > Reviewed-by: Christophe Leroy
>>
>> As this doesn't seem to have been picked up for linux-next yet, I am
>> picking it up now.
>
> Only now I've noticed that this is actually a dead code o_O as this file
> can't be built by any combination of config options. So I am dropping the
> patch again, but why do we keep it in the tree in the first place?
Yeah, sigh.
As Christophe pointed out, it has been dead code for a long time but
there is a series in flight that's trying to make it usable.
cheers
debian-powe...@lists.debian.org
Hi, everyone, I strongly suspect something went wrong between Linux 5.6 and 5.7-rc1. This is an iBook G4 laptop with 1.5 GiB of RAM running the Debian powerpc port. I haven't bisected yet, since it's going to take quite a bit of time, so I'm sending this mostly as a heads-up (and to see if anybody has any clues about the possible cause). I'm using the following reproducer: stress-ng --cpu 8 --io 8 --vm 8 --vm-bytes 1G --fork 8 --timeout 10m On Linux 5.7-rc1, this completely hangs the machine in about 30 seconds. Linux 5.6 survives the test. Let me know if I can provide any additional info, otherwise I'll just bite the bullet and start bisecting. Thanks, Rui
Re: [PATCH v2 2/2] powerpc/configs: replace deprecated riva/nvidia with nouveau
Hi Michael, On Mon, 18 May 2020 at 08:30, Michael Ellerman wrote: > > Emil Velikov writes: > > As mentioned in earlier commit, the riva and nvidia fbdev drivers have > > seen no love over the years, are short on features and overall below par > > > > Users are encouraged to switch to the nouveau drm driver instead. > > > > v2: Split configs to separate patch, enable nouveau (Bartlomiej) > > > > Cc: Antonino Daplas > > Cc: Bartlomiej Zolnierkiewicz > > Cc: linux-fb...@vger.kernel.org > > Cc: dri-de...@lists.freedesktop.org > > Cc: Michael Ellerman > > Cc: Benjamin Herrenschmidt > > Cc: Paul Mackerras > > Cc: linuxppc-dev@lists.ozlabs.org > > Signed-off-by: Emil Velikov > > Acked-by: Daniel Vetter (v1) > > --- > > Hi all unless, there are objections I would prefer to merge this via > > the drm tree. > > Have you tested that the resulting kernels work on the relevant > hardware? > Sadly, no I haven't. I'm updating the defconfigs as requested by the fbdev maintainer. > The old drivers may be crufty but they presumably have been tested by > people and at least somewhat work. > > So I'd be inclined to leave the defconfigs alone until someone can test > that the new driver works at all. > Works for me. > I gave it a quick spin on a G5 I have access to and dmesg has a bunch of > errors in it (see below). I can't actually tell if the display is > working because the machine is remote, and I can't go and check it at > the moment because the office is closed. > >From what I can see, there seems to be three bits: - attempted out-of-bound attempts to read the vbios Genuine concern or noise? Likely using the bios from open firmware, check any of the other options - see NvBios in [1] - cannot figure out the timer input frequency No idea - the TV1 EDID is empty Is there an actual TV connected to the device, check with another cable Regardless of the patches, reporting [2] the above would be a nice move. Thanks Emil [1] https://nouveau.freedesktop.org/wiki/KernelModuleParameters/ [2] https://gitlab.freedesktop.org/xorg/driver/xf86-video-nouveau/-/issues
