[PATCH v5.4] powerpc/32: Fix overread/overwrite of thread_struct via ptrace
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers of the process are
laid out in some fashion.
The kernel then maps that index to a particular register in its own data
structures and gets/sets the value.
The API only allows a single machine-word to be read/written at a time.
So 4 bytes on 32-bit kernels and 8 bytes on 64-bit kernels.
The way floating point registers (FPRs) are addressed is somewhat
complicated, because double precision float values are 64-bit even on
32-bit CPUs. That means on 32-bit kernels each FPR occupies two
word-sized locations in the USER area. On 64-bit kernels each FPR
occupies one word-sized location in the USER area.
Internally the kernel stores the FPRs in an array of u64s, or if VSX is
enabled, an array of pairs of u64s where one half of each pair stores
the FPR. Which half of the pair stores the FPR depends on the kernel's
endianness.
To handle the different layouts of the FPRs depending on VSX/no-VSX and
big/little endian, the TS_FPR() macro was introduced.
Unfortunately the TS_FPR() macro does not take into account the fact
that the addressing of each FPR differs between 32-bit and 64-bit
kernels. It just takes the index into the "USER area" passed from
userspace and indexes into the fp_state.fpr array.
On 32-bit there are 64 indexes that address FPRs, but only 32 entries in
the fp_state.fpr array, meaning the user can read/write 256 bytes past
the end of the array. Because the fp_state sits in the middle of the
thread_struct there are various fields than can be overwritten,
including some pointers. As such it may be exploitable.
It has also been observed to cause systems to hang or otherwise
misbehave when using gdbserver, and is probably the root cause of this
report which could not be easily reproduced:
https://lore.kernel.org/linuxppc-dev/dc38afe9-6b78-f3f5-666b-986939e40...@keymile.com/
Rather than trying to make the TS_FPR() macro even more complicated to
fix the bug, or add more macros, instead add a special-case for 32-bit
kernels. This is more obvious and hopefully avoids a similar bug
happening again in future.
Note that because 32-bit kernels never have VSX enabled the code doesn't
need to consider TS_FPRWIDTH/OFFSET at all. Add a BUILD_BUG_ON() to
ensure that 32-bit && VSX is never enabled.
Fixes: 87fec0514f61 ("powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers
in little endian builds")
Cc: sta...@vger.kernel.org # v3.13+
Reported-by: Ariel Miculas
Tested-by: Christophe Leroy
Signed-off-by: Michael Ellerman
Link: https://lore.kernel.org/r/20220609133245.573565-1-...@ellerman.id.au
---
arch/powerpc/kernel/ptrace.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 8c92febf5f44..63bfc5250b67 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -3014,8 +3014,13 @@ long arch_ptrace(struct task_struct *child, long request,
flush_fp_to_thread(child);
if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(, >thread.TS_FPR(fpidx),
- sizeof(long));
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ // On 32-bit the index we are passed
refers to 32-bit words
+ tmp = ((u32
*)child->thread.fp_state.fpr)[fpidx];
+ } else {
+ memcpy(,
>thread.TS_FPR(fpidx),
+ sizeof(long));
+ }
else
tmp = child->thread.fp_state.fpscr;
}
@@ -3047,8 +3052,13 @@ long arch_ptrace(struct task_struct *child, long request,
flush_fp_to_thread(child);
if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(>thread.TS_FPR(fpidx), ,
- sizeof(long));
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ // On 32-bit the index we are passed
refers to 32-bit words
+ ((u32
*)child->thread.fp_state.fpr)[fpidx] = data;
+ } else {
+ memcpy(>thread.TS_FPR(fpidx),
,
+ sizeof(long));
+ }
else
child->thread.fp_state.fpscr = data;
ret = 0;
@@ -3398,4 +3408,7 @@ void __init pt_regs_check(void)
[PATCH v5.10] powerpc/32: Fix overread/overwrite of thread_struct via ptrace
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers of the process are
laid out in some fashion.
The kernel then maps that index to a particular register in its own data
structures and gets/sets the value.
The API only allows a single machine-word to be read/written at a time.
So 4 bytes on 32-bit kernels and 8 bytes on 64-bit kernels.
The way floating point registers (FPRs) are addressed is somewhat
complicated, because double precision float values are 64-bit even on
32-bit CPUs. That means on 32-bit kernels each FPR occupies two
word-sized locations in the USER area. On 64-bit kernels each FPR
occupies one word-sized location in the USER area.
Internally the kernel stores the FPRs in an array of u64s, or if VSX is
enabled, an array of pairs of u64s where one half of each pair stores
the FPR. Which half of the pair stores the FPR depends on the kernel's
endianness.
To handle the different layouts of the FPRs depending on VSX/no-VSX and
big/little endian, the TS_FPR() macro was introduced.
Unfortunately the TS_FPR() macro does not take into account the fact
that the addressing of each FPR differs between 32-bit and 64-bit
kernels. It just takes the index into the "USER area" passed from
userspace and indexes into the fp_state.fpr array.
On 32-bit there are 64 indexes that address FPRs, but only 32 entries in
the fp_state.fpr array, meaning the user can read/write 256 bytes past
the end of the array. Because the fp_state sits in the middle of the
thread_struct there are various fields than can be overwritten,
including some pointers. As such it may be exploitable.
It has also been observed to cause systems to hang or otherwise
misbehave when using gdbserver, and is probably the root cause of this
report which could not be easily reproduced:
https://lore.kernel.org/linuxppc-dev/dc38afe9-6b78-f3f5-666b-986939e40...@keymile.com/
Rather than trying to make the TS_FPR() macro even more complicated to
fix the bug, or add more macros, instead add a special-case for 32-bit
kernels. This is more obvious and hopefully avoids a similar bug
happening again in future.
Note that because 32-bit kernels never have VSX enabled the code doesn't
need to consider TS_FPRWIDTH/OFFSET at all. Add a BUILD_BUG_ON() to
ensure that 32-bit && VSX is never enabled.
Fixes: 87fec0514f61 ("powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers
in little endian builds")
Cc: sta...@vger.kernel.org # v3.13+
Reported-by: Ariel Miculas
Tested-by: Christophe Leroy
Signed-off-by: Michael Ellerman
Link: https://lore.kernel.org/r/20220609133245.573565-1-...@ellerman.id.au
---
arch/powerpc/kernel/ptrace/ptrace.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace.c
b/arch/powerpc/kernel/ptrace/ptrace.c
index f6e51be47c6e..9ea9ee513ae1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace.c
+++ b/arch/powerpc/kernel/ptrace/ptrace.c
@@ -75,8 +75,13 @@ long arch_ptrace(struct task_struct *child, long request,
flush_fp_to_thread(child);
if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(, >thread.TS_FPR(fpidx),
- sizeof(long));
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ // On 32-bit the index we are passed
refers to 32-bit words
+ tmp = ((u32
*)child->thread.fp_state.fpr)[fpidx];
+ } else {
+ memcpy(,
>thread.TS_FPR(fpidx),
+ sizeof(long));
+ }
else
tmp = child->thread.fp_state.fpscr;
}
@@ -108,8 +113,13 @@ long arch_ptrace(struct task_struct *child, long request,
flush_fp_to_thread(child);
if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(>thread.TS_FPR(fpidx), ,
- sizeof(long));
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ // On 32-bit the index we are passed
refers to 32-bit words
+ ((u32
*)child->thread.fp_state.fpr)[fpidx] = data;
+ } else {
+ memcpy(>thread.TS_FPR(fpidx),
,
+ sizeof(long));
+ }
else
child->thread.fp_state.fpscr = data;
ret = 0;
@@ -478,4 +488,7 @@ void
[powerpc:merge] BUILD SUCCESS 8582c0462f3d6c6067962623f1072daf25f6d560
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge branch HEAD: 8582c0462f3d6c6067962623f1072daf25f6d560 Automatic merge of 'fixes' into merge (2022-06-10 00:07) elapsed time: 2212m configs tested: 83 configs skipped: 3 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm64 defconfig arm64allyesconfig arm allmodconfig arm defconfig arm allyesconfig ia64defconfig ia64 allmodconfig ia64 allyesconfig m68k allyesconfig m68k allmodconfig m68kdefconfig nios2 defconfig arc allyesconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig h8300allyesconfig xtensa allyesconfig arc defconfig sh allmodconfig s390defconfig s390 allmodconfig parisc defconfig parisc64defconfig parisc allyesconfig s390 allyesconfig sparc defconfig i386 allyesconfig sparcallyesconfig i386defconfig i386 debian-10.3-kselftests i386 debian-10.3 mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allnoconfig powerpc allmodconfig i386 randconfig-a001 i386 randconfig-a003 i386 randconfig-a005 i386 randconfig-a014 i386 randconfig-a012 i386 randconfig-a016 x86_64randconfig-a004 x86_64randconfig-a002 x86_64randconfig-a006 arc randconfig-r043-20220608 s390 randconfig-r044-20220608 riscvrandconfig-r042-20220608 arc randconfig-r043-20220609 riscv defconfig riscvnommu_virt_defconfig riscv rv32_defconfig riscvnommu_k210_defconfig riscv allnoconfig riscvallmodconfig riscvallyesconfig um i386_defconfig um x86_64_defconfig x86_64 kexec x86_64 defconfig x86_64 allyesconfig x86_64 rhel-8.3 x86_64 rhel-8.3-kunit x86_64 rhel-8.3-syz x86_64 rhel-8.3-func x86_64rhel-8.3-kselftests clang tested configs: x86_64randconfig-a005 x86_64randconfig-a003 x86_64randconfig-a001 i386 randconfig-a002 i386 randconfig-a004 i386 randconfig-a006 i386 randconfig-a013 i386 randconfig-a011 i386 randconfig-a015 hexagon randconfig-r045-20220609 s390 randconfig-r044-20220609 riscvrandconfig-r042-20220609 hexagon randconfig-r041-20220609 hexagon randconfig-r045-20220608 hexagon randconfig-r041-20220608 -- 0-DAY CI Kernel Test Service https://01.org/lkp
[PATCH v5.15] powerpc/32: Fix overread/overwrite of thread_struct via ptrace
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers of the process are
laid out in some fashion.
The kernel then maps that index to a particular register in its own data
structures and gets/sets the value.
The API only allows a single machine-word to be read/written at a time.
So 4 bytes on 32-bit kernels and 8 bytes on 64-bit kernels.
The way floating point registers (FPRs) are addressed is somewhat
complicated, because double precision float values are 64-bit even on
32-bit CPUs. That means on 32-bit kernels each FPR occupies two
word-sized locations in the USER area. On 64-bit kernels each FPR
occupies one word-sized location in the USER area.
Internally the kernel stores the FPRs in an array of u64s, or if VSX is
enabled, an array of pairs of u64s where one half of each pair stores
the FPR. Which half of the pair stores the FPR depends on the kernel's
endianness.
To handle the different layouts of the FPRs depending on VSX/no-VSX and
big/little endian, the TS_FPR() macro was introduced.
Unfortunately the TS_FPR() macro does not take into account the fact
that the addressing of each FPR differs between 32-bit and 64-bit
kernels. It just takes the index into the "USER area" passed from
userspace and indexes into the fp_state.fpr array.
On 32-bit there are 64 indexes that address FPRs, but only 32 entries in
the fp_state.fpr array, meaning the user can read/write 256 bytes past
the end of the array. Because the fp_state sits in the middle of the
thread_struct there are various fields than can be overwritten,
including some pointers. As such it may be exploitable.
It has also been observed to cause systems to hang or otherwise
misbehave when using gdbserver, and is probably the root cause of this
report which could not be easily reproduced:
https://lore.kernel.org/linuxppc-dev/dc38afe9-6b78-f3f5-666b-986939e40...@keymile.com/
Rather than trying to make the TS_FPR() macro even more complicated to
fix the bug, or add more macros, instead add a special-case for 32-bit
kernels. This is more obvious and hopefully avoids a similar bug
happening again in future.
Note that because 32-bit kernels never have VSX enabled the code doesn't
need to consider TS_FPRWIDTH/OFFSET at all. Add a BUILD_BUG_ON() to
ensure that 32-bit && VSX is never enabled.
Fixes: 87fec0514f61 ("powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers
in little endian builds")
Cc: sta...@vger.kernel.org # v3.13+
Reported-by: Ariel Miculas
Tested-by: Christophe Leroy
Signed-off-by: Michael Ellerman
Link: https://lore.kernel.org/r/20220609133245.573565-1-...@ellerman.id.au
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 20 ++--
arch/powerpc/kernel/ptrace/ptrace.c | 3 +++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 5dca19361316..09c49632bfe5 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,9 +17,13 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(data, >thread.TS_FPR(fpidx), sizeof(long));
- else
+ if (fpidx < (PT_FPSCR - PT_FPR0)) {
+ if (IS_ENABLED(CONFIG_PPC32))
+ // On 32-bit the index we are passed refers to 32-bit
words
+ *data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
+ else
+ memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
+ } else
*data = child->thread.fp_state.fpscr;
#else
*data = 0;
@@ -39,9 +43,13 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(>thread.TS_FPR(fpidx), , sizeof(long));
- else
+ if (fpidx < (PT_FPSCR - PT_FPR0)) {
+ if (IS_ENABLED(CONFIG_PPC32))
+ // On 32-bit the index we are passed refers to 32-bit
words
+ ((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
+ else
+ memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
+ } else
child->thread.fp_state.fpscr = data;
#endif
diff --git a/arch/powerpc/kernel/ptrace/ptrace.c
b/arch/powerpc/kernel/ptrace/ptrace.c
index 7c7093c17c45..ff5e46dbf7c5 100644
--- a/arch/powerpc/kernel/ptrace/ptrace.c
+++ b/arch/powerpc/kernel/ptrace/ptrace.c
@@ -446,4 +446,7 @@ void __init pt_regs_check(void)
* real registers.
*/
[PATCH v5.17] powerpc/32: Fix overread/overwrite of thread_struct via ptrace
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers of the process are
laid out in some fashion.
The kernel then maps that index to a particular register in its own data
structures and gets/sets the value.
The API only allows a single machine-word to be read/written at a time.
So 4 bytes on 32-bit kernels and 8 bytes on 64-bit kernels.
The way floating point registers (FPRs) are addressed is somewhat
complicated, because double precision float values are 64-bit even on
32-bit CPUs. That means on 32-bit kernels each FPR occupies two
word-sized locations in the USER area. On 64-bit kernels each FPR
occupies one word-sized location in the USER area.
Internally the kernel stores the FPRs in an array of u64s, or if VSX is
enabled, an array of pairs of u64s where one half of each pair stores
the FPR. Which half of the pair stores the FPR depends on the kernel's
endianness.
To handle the different layouts of the FPRs depending on VSX/no-VSX and
big/little endian, the TS_FPR() macro was introduced.
Unfortunately the TS_FPR() macro does not take into account the fact
that the addressing of each FPR differs between 32-bit and 64-bit
kernels. It just takes the index into the "USER area" passed from
userspace and indexes into the fp_state.fpr array.
On 32-bit there are 64 indexes that address FPRs, but only 32 entries in
the fp_state.fpr array, meaning the user can read/write 256 bytes past
the end of the array. Because the fp_state sits in the middle of the
thread_struct there are various fields than can be overwritten,
including some pointers. As such it may be exploitable.
It has also been observed to cause systems to hang or otherwise
misbehave when using gdbserver, and is probably the root cause of this
report which could not be easily reproduced:
https://lore.kernel.org/linuxppc-dev/dc38afe9-6b78-f3f5-666b-986939e40...@keymile.com/
Rather than trying to make the TS_FPR() macro even more complicated to
fix the bug, or add more macros, instead add a special-case for 32-bit
kernels. This is more obvious and hopefully avoids a similar bug
happening again in future.
Note that because 32-bit kernels never have VSX enabled the code doesn't
need to consider TS_FPRWIDTH/OFFSET at all. Add a BUILD_BUG_ON() to
ensure that 32-bit && VSX is never enabled.
Fixes: 87fec0514f61 ("powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers
in little endian builds")
Cc: sta...@vger.kernel.org # v3.13+
Reported-by: Ariel Miculas
Tested-by: Christophe Leroy
Signed-off-by: Michael Ellerman
Link: https://lore.kernel.org/r/20220609133245.573565-1-...@ellerman.id.au
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 20 ++--
arch/powerpc/kernel/ptrace/ptrace.c | 3 +++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 5dca19361316..09c49632bfe5 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,9 +17,13 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(data, >thread.TS_FPR(fpidx), sizeof(long));
- else
+ if (fpidx < (PT_FPSCR - PT_FPR0)) {
+ if (IS_ENABLED(CONFIG_PPC32))
+ // On 32-bit the index we are passed refers to 32-bit
words
+ *data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
+ else
+ memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
+ } else
*data = child->thread.fp_state.fpscr;
#else
*data = 0;
@@ -39,9 +43,13 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(>thread.TS_FPR(fpidx), , sizeof(long));
- else
+ if (fpidx < (PT_FPSCR - PT_FPR0)) {
+ if (IS_ENABLED(CONFIG_PPC32))
+ // On 32-bit the index we are passed refers to 32-bit
words
+ ((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
+ else
+ memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
+ } else
child->thread.fp_state.fpscr = data;
#endif
diff --git a/arch/powerpc/kernel/ptrace/ptrace.c
b/arch/powerpc/kernel/ptrace/ptrace.c
index c43f77e2ac31..6d45fa288015 100644
--- a/arch/powerpc/kernel/ptrace/ptrace.c
+++ b/arch/powerpc/kernel/ptrace/ptrace.c
@@ -445,4 +445,7 @@ void __init pt_regs_check(void)
* real registers.
*/
[RFC PATCH 6/6] pkeys: Change mm_pkey_free() to void
From: Ira Weiny
Now that the pkey arch support is no longer checked in mm_pkey_free()
there is no reason to have it return int.
Change the return value to void.
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Suggested-by: Sohil Mehta
Signed-off-by: Ira Weiny
---
arch/powerpc/include/asm/pkeys.h | 4 +---
arch/x86/include/asm/pkeys.h | 4 +---
include/linux/pkeys.h| 5 +
mm/mprotect.c| 6 --
4 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h
index e96aa91f817b..4d01a48ab941 100644
--- a/arch/powerpc/include/asm/pkeys.h
+++ b/arch/powerpc/include/asm/pkeys.h
@@ -105,11 +105,9 @@ static inline int mm_pkey_alloc(struct mm_struct *mm)
return ret;
}
-static inline int mm_pkey_free(struct mm_struct *mm, int pkey)
+static inline void mm_pkey_free(struct mm_struct *mm, int pkey)
{
__mm_pkey_free(mm, pkey);
-
- return 0;
}
/*
diff --git a/arch/x86/include/asm/pkeys.h b/arch/x86/include/asm/pkeys.h
index da02737cc4d1..1f408f46fa9a 100644
--- a/arch/x86/include/asm/pkeys.h
+++ b/arch/x86/include/asm/pkeys.h
@@ -105,11 +105,9 @@ int mm_pkey_alloc(struct mm_struct *mm)
}
static inline
-int mm_pkey_free(struct mm_struct *mm, int pkey)
+void mm_pkey_free(struct mm_struct *mm, int pkey)
{
mm_set_pkey_free(mm, pkey);
-
- return 0;
}
static inline int vma_pkey(struct vm_area_struct *vma)
diff --git a/include/linux/pkeys.h b/include/linux/pkeys.h
index 86be8bf27b41..bf98c50a3437 100644
--- a/include/linux/pkeys.h
+++ b/include/linux/pkeys.h
@@ -30,10 +30,7 @@ static inline int mm_pkey_alloc(struct mm_struct *mm)
return -1;
}
-static inline int mm_pkey_free(struct mm_struct *mm, int pkey)
-{
- return -EINVAL;
-}
+static inline void mm_pkey_free(struct mm_struct *mm, int pkey) { }
static inline int arch_set_user_pkey_access(struct task_struct *tsk, int pkey,
unsigned long init_val)
diff --git a/mm/mprotect.c b/mm/mprotect.c
index 41458e729c27..e872bdd2e228 100644
--- a/mm/mprotect.c
+++ b/mm/mprotect.c
@@ -809,8 +809,10 @@ SYSCALL_DEFINE1(pkey_free, int, pkey)
return ret;
mmap_write_lock(current->mm);
- if (mm_pkey_is_allocated(current->mm, pkey))
- ret = mm_pkey_free(current->mm, pkey);
+ if (mm_pkey_is_allocated(current->mm, pkey)) {
+ mm_pkey_free(current->mm, pkey);
+ ret = 0;
+ }
mmap_write_unlock(current->mm);
/*
--
2.35.1
[RFC PATCH 4/6] pkeys: Lift pkey hardware check for pkey_alloc()
From: Ira Weiny
pkey_alloc() is documented to return ENOSPC when the hardware does not
support pkeys. On x86, pkey_alloc() incorrectly returns EINVAL.
This is because mm_pkey_alloc() does not check for pkey support before
returning a key. Therefore, if the keys are not exhausted pkey_alloc()
continues on to call arch_set_user_pkey_access(). Unfortunately, when
arch_set_user_pkey_access() detects the failed support it overwrites the
ENOSPC return value with EINVAL.
Ensure consistent behavior across architectures by lifting this check to
the core mm code.
Remove a couple of 'we' references in code comments as well.
Cc: ah...@chromium.org
Cc: cleme...@chromium.org
Cc: gdee...@chromium.org
Cc: jkumme...@chromium.org
Cc: manosk...@chromium.org
Cc: thiba...@chromium.org
Cc: Florian Weimer
Cc: Sohil Mehta
Cc: Andrew Morton
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Cc: linux-...@vger.kernel.org
Fixes: e8c24d3a23a4 ("x86/pkeys: Allocation/free syscalls")
Signed-off-by: Ira Weiny
---
Thanks to Sohil for pointing out that the commit message could be more
clear WRT how EINVAL is returned incorrectly.
---
arch/powerpc/include/asm/pkeys.h | 8 +++-
mm/mprotect.c| 3 +++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h
index 59a2c7dbc78f..2c8351248793 100644
--- a/arch/powerpc/include/asm/pkeys.h
+++ b/arch/powerpc/include/asm/pkeys.h
@@ -85,18 +85,16 @@ static inline bool mm_pkey_is_allocated(struct mm_struct
*mm, int pkey)
static inline int mm_pkey_alloc(struct mm_struct *mm)
{
/*
-* Note: this is the one and only place we make sure that the pkey is
+* Note: this is the one and only place to make sure that the pkey is
* valid as far as the hardware is concerned. The rest of the kernel
* trusts that only good, valid pkeys come out of here.
*/
u32 all_pkeys_mask = (u32)(~(0x0));
int ret;
- if (!mmu_has_feature(MMU_FTR_PKEY))
- return -1;
/*
-* Are we out of pkeys? We must handle this specially because ffz()
-* behavior is undefined if there are no zeros.
+* Out of pkeys? Handle this specially because ffz() behavior is
+* undefined if there are no zeros.
*/
if (mm_pkey_allocation_map(mm) == all_pkeys_mask)
return -1;
diff --git a/mm/mprotect.c b/mm/mprotect.c
index ba5592655ee3..56d35de33725 100644
--- a/mm/mprotect.c
+++ b/mm/mprotect.c
@@ -773,6 +773,9 @@ SYSCALL_DEFINE2(pkey_alloc, unsigned long, flags, unsigned
long, init_val)
int pkey;
int ret;
+ if (!arch_pkeys_enabled())
+ return -ENOSPC;
+
/* No flags supported yet. */
if (flags)
return -EINVAL;
--
2.35.1
[RFC PATCH 3/6] testing/pkeys: Add additional test for pkey_alloc()
From: Ira Weiny
When pkeys are not available on the hardware pkey_alloc() has specific
behavior which was previously untested.
Add test for this.
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Signed-off-by: Ira Weiny
---
tools/testing/selftests/vm/protection_keys.c | 12
1 file changed, 12 insertions(+)
diff --git a/tools/testing/selftests/vm/protection_keys.c
b/tools/testing/selftests/vm/protection_keys.c
index 43e47de19c0d..4b733a75606f 100644
--- a/tools/testing/selftests/vm/protection_keys.c
+++ b/tools/testing/selftests/vm/protection_keys.c
@@ -1554,6 +1554,16 @@ void test_implicit_mprotect_exec_only_memory(int *ptr,
u16 pkey)
do_not_expect_pkey_fault("plain read on recently PROT_EXEC area");
}
+void test_pkey_alloc_on_unsupported_cpu(void)
+{
+ int test_pkey = sys_pkey_alloc(0, 0);
+
+ dprintf1("pkey_alloc: %d (%d %s)\n", test_pkey, errno,
+strerror(errno));
+ pkey_assert(test_pkey < 0);
+ pkey_assert(errno == ENOSPC);
+}
+
void test_mprotect_pkey_on_unsupported_cpu(int *ptr, u16 pkey)
{
int size = PAGE_SIZE;
@@ -1688,6 +1698,8 @@ int main(int argc, char *argv[])
printf("running PKEY tests for unsupported CPU/OS\n");
+ test_pkey_alloc_on_unsupported_cpu();
+
ptr = mmap(NULL, size, PROT_NONE, MAP_ANONYMOUS|MAP_PRIVATE,
-1, 0);
assert(ptr != (void *)-1);
test_mprotect_pkey_on_unsupported_cpu(ptr, 1);
--
2.35.1
[RFC PATCH 0/6] User pkey minor bug fixes
From: Ira Weiny
While evaluating the possibility of defining a new type for pkeys within the
kernel I found a couple of minor bugs.
Because these patches clean up the return codes from system calls I'm sending
this out RFC hoping that users will speak up if anything breaks.
I'm not too concerned about pkey_free() because it is unlikely that anyone is
checking the return code. Interestingly enough, glibc recommends not calling
pkey_free() because it does not change the access rights to the key and may be
subsequently allocated again.[1][2]
The pkey_alloc() is more concerning. However, I checked the Chrome source and
it does not differentiate among the return codes and maps all errors into
kNoMemoryProtectionKey.
glibc says it returns ENOSYS if the system does not support pkeys but I don't
see where ENOSYS is returned? AFAICS it just returns what the kernel returns.
So it is probably up to user of glibc.
In addition I've enhanced the pkey tests to verify and test the changes.
Thanks to Rick Edgecombe and Sohil Mehta for internal review.
[1] Quote from manual/memory.texi:
Calling this function does not change the access rights of the freed
protection key. The calling thread and other threads may retain access
to it, even if it is subsequently allocated again. For this reason, it
is not recommended to call the @code{pkey_free} function.
[2] PKS had a similar issue and went to statically allocated keys instead.
Ira Weiny (6):
testing/pkeys: Add command line options
testing/pkeys: Don't use uninitialized variable
testing/pkeys: Add additional test for pkey_alloc()
pkeys: Lift pkey hardware check for pkey_alloc()
pkeys: Up level pkey_free() checks
pkeys: Change mm_pkey_free() to void
arch/powerpc/include/asm/pkeys.h | 18 ++---
arch/x86/include/asm/pkeys.h | 7 +-
include/linux/pkeys.h| 5 +-
mm/mprotect.c| 13 +++-
tools/testing/selftests/vm/pkey-helpers.h| 7 +-
tools/testing/selftests/vm/protection_keys.c | 75 +---
6 files changed, 86 insertions(+), 39 deletions(-)
base-commit: 874c8ca1e60b2c564a48f7e7acc40d328d5c8733
--
2.35.1
[RFC PATCH 1/6] testing/pkeys: Add command line options
From: Ira Weiny
It is more convenient to use command line options for debug and
iterations vs changing the code and recompiling.
Add command line options for debug level and number of iterations.
$ ./protection_keys_64 -h
Usage: ./protection_keys_64 [-h,-d,-i ]
--help,-h This help
--debug,-d Increase debug level for each -d
--iterations,-i repeate test times
default: 22
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Signed-off-by: Ira Weiny
---
tools/testing/selftests/vm/pkey-helpers.h| 7 +--
tools/testing/selftests/vm/protection_keys.c | 59 +---
2 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/tools/testing/selftests/vm/pkey-helpers.h
b/tools/testing/selftests/vm/pkey-helpers.h
index 92f3be3dd8e5..7aaac1c8ebca 100644
--- a/tools/testing/selftests/vm/pkey-helpers.h
+++ b/tools/testing/selftests/vm/pkey-helpers.h
@@ -23,9 +23,8 @@
#define PTR_ERR_ENOTSUP ((void *)-ENOTSUP)
-#ifndef DEBUG_LEVEL
-#define DEBUG_LEVEL 0
-#endif
+extern int debug_level;
+
#define DPRINT_IN_SIGNAL_BUF_SIZE 4096
extern int dprint_in_signal;
extern char dprint_in_signal_buffer[DPRINT_IN_SIGNAL_BUF_SIZE];
@@ -58,7 +57,7 @@ static inline void sigsafe_printf(const char *format, ...)
}
}
#define dprintf_level(level, args...) do { \
- if (level <= DEBUG_LEVEL) \
+ if (level <= debug_level) \
sigsafe_printf(args); \
} while (0)
#define dprintf0(args...) dprintf_level(0, args)
diff --git a/tools/testing/selftests/vm/protection_keys.c
b/tools/testing/selftests/vm/protection_keys.c
index 291bc1e07842..d0183c381859 100644
--- a/tools/testing/selftests/vm/protection_keys.c
+++ b/tools/testing/selftests/vm/protection_keys.c
@@ -44,9 +44,13 @@
#include
#include
#include
+#include
#include "pkey-helpers.h"
+#define DEFAULT_ITERATIONS 22
+
+int debug_level;
int iteration_nr = 1;
int test_nr;
@@ -361,7 +365,7 @@ void signal_handler(int signum, siginfo_t *si, void
*vucontext)
* here.
*/
dprintf1("pkey_reg_xstate_offset: %d\n", pkey_reg_xstate_offset());
- if (DEBUG_LEVEL > 4)
+ if (debug_level > 4)
dump_mem(pkey_reg_ptr - 128, 256);
pkey_assert(*pkey_reg_ptr);
#endif /* arch */
@@ -480,7 +484,7 @@ int sys_mprotect_pkey(void *ptr, size_t size, unsigned long
orig_prot,
dprintf2("SYS_mprotect_key sret: %d\n", sret);
dprintf2("SYS_mprotect_key prot: 0x%lx\n", orig_prot);
dprintf2("SYS_mprotect_key failed, errno: %d\n", errno);
- if (DEBUG_LEVEL >= 2)
+ if (debug_level >= 2)
perror("SYS_mprotect_pkey");
}
return sret;
@@ -1116,7 +1120,7 @@ void test_kernel_write_of_write_disabled_region(int *ptr,
u16 pkey)
pkey_write_deny(pkey);
ret = read(test_fd, ptr, 100);
dprintf1("read ret: %d\n", ret);
- if (ret < 0 && (DEBUG_LEVEL > 0))
+ if (ret < 0 && (debug_level > 0))
perror("verbose read result (OK for this to be bad)");
pkey_assert(ret);
}
@@ -1155,7 +1159,7 @@ void test_kernel_gup_write_to_write_disabled_region(int
*ptr, u16 pkey)
pkey_write_deny(pkey);
futex_ret = syscall(SYS_futex, ptr, FUTEX_WAIT, some_int-1, NULL,
, ignored);
- if (DEBUG_LEVEL > 0)
+ if (debug_level > 0)
perror("futex");
dprintf1("futex() ret: %d\n", futex_ret);
}
@@ -1626,11 +1630,52 @@ void pkey_setup_shadow(void)
shadow_pkey_reg = __read_pkey_reg();
}
-int main(void)
+static void print_help_and_exit(char *argv0)
+{
+ printf("Usage: %s [-h,-d,-i ]\n", argv0);
+ printf("--help,-h This help\n");
+ printf("--debug,-d Increase debug level for each -d\n");
+ printf("--iterations,-i repeate test times\n");
+ printf("default: %d\n", DEFAULT_ITERATIONS);
+ printf("\n");
+}
+
+int main(int argc, char *argv[])
{
- int nr_iterations = 22;
- int pkeys_supported = is_pkeys_supported();
+ int nr_iterations = DEFAULT_ITERATIONS;
+ int pkeys_supported;
+
+ while (1) {
+ static struct option long_options[] = {
+ {"help",no_argument,0, 'h' },
+ {"debug", no_argument,0, 'd' },
+ {"iterations", required_argument, 0, 'i' },
+ {0, 0, 0, 0 }
+ };
+ int option_index = 0;
+ int c;
+
+ c = getopt_long(argc, argv, "hdi:", long_options,
_index);
+ if (c == -1)
+ break;
+
+ switch (c) {
+ case 'h':
+ print_help_and_exit(argv[0]);
+
[RFC PATCH 5/6] pkeys: Up level pkey_free() checks
From: Ira Weiny
x86 is missing a hardware check for pkey support in pkey_free(). While
the net result is the same (-EINVAL returned), pkey_free() has well
defined behavior which will be easier to maintain in one place.
For powerpc the return code is -1 rather than -EINVAL. This changes
that behavior slightly but this is very unlikely to break any user
space.
Lift the checks for pkey_free() to the core mm code and ensure
consistency with returning -EINVAL.
Cc: ah...@chromium.org
Cc: cleme...@chromium.org
Cc: gdee...@chromium.org
Cc: jkumme...@chromium.org
Cc: manosk...@chromium.org
Cc: thiba...@chromium.org
Cc: Florian Weimer
Cc: Andrew Morton
Cc: linux-...@vger.kernel.org
Cc: Sohil Mehta
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Signed-off-by: Ira Weiny
---
Thanks to Sohil for suggesting I mention the powerpc return value in the
commit message.
Also Sohil suggested changing mm_pkey_free() from int to void. This is
added as a separate patch with his suggested by.
---
arch/powerpc/include/asm/pkeys.h | 6 --
arch/x86/include/asm/pkeys.h | 3 ---
mm/mprotect.c| 8 ++--
3 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h
index 2c8351248793..e96aa91f817b 100644
--- a/arch/powerpc/include/asm/pkeys.h
+++ b/arch/powerpc/include/asm/pkeys.h
@@ -107,12 +107,6 @@ static inline int mm_pkey_alloc(struct mm_struct *mm)
static inline int mm_pkey_free(struct mm_struct *mm, int pkey)
{
- if (!mmu_has_feature(MMU_FTR_PKEY))
- return -1;
-
- if (!mm_pkey_is_allocated(mm, pkey))
- return -EINVAL;
-
__mm_pkey_free(mm, pkey);
return 0;
diff --git a/arch/x86/include/asm/pkeys.h b/arch/x86/include/asm/pkeys.h
index 2e6c04d8a45b..da02737cc4d1 100644
--- a/arch/x86/include/asm/pkeys.h
+++ b/arch/x86/include/asm/pkeys.h
@@ -107,9 +107,6 @@ int mm_pkey_alloc(struct mm_struct *mm)
static inline
int mm_pkey_free(struct mm_struct *mm, int pkey)
{
- if (!mm_pkey_is_allocated(mm, pkey))
- return -EINVAL;
-
mm_set_pkey_free(mm, pkey);
return 0;
diff --git a/mm/mprotect.c b/mm/mprotect.c
index 56d35de33725..41458e729c27 100644
--- a/mm/mprotect.c
+++ b/mm/mprotect.c
@@ -803,10 +803,14 @@ SYSCALL_DEFINE2(pkey_alloc, unsigned long, flags,
unsigned long, init_val)
SYSCALL_DEFINE1(pkey_free, int, pkey)
{
- int ret;
+ int ret = -EINVAL;
+
+ if (!arch_pkeys_enabled())
+ return ret;
mmap_write_lock(current->mm);
- ret = mm_pkey_free(current->mm, pkey);
+ if (mm_pkey_is_allocated(current->mm, pkey))
+ ret = mm_pkey_free(current->mm, pkey);
mmap_write_unlock(current->mm);
/*
--
2.35.1
[RFC PATCH 2/6] testing/pkeys: Don't use uninitialized variable
From: Ira Weiny
err was being used in test_pkey_alloc_exhaust() prior to being assigned.
errno is useful to know after a failed alloc_pkey() call.
Change err to errno in the debug print.
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Signed-off-by: Ira Weiny
---
tools/testing/selftests/vm/protection_keys.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/vm/protection_keys.c
b/tools/testing/selftests/vm/protection_keys.c
index d0183c381859..43e47de19c0d 100644
--- a/tools/testing/selftests/vm/protection_keys.c
+++ b/tools/testing/selftests/vm/protection_keys.c
@@ -1225,9 +1225,9 @@ void test_pkey_alloc_exhaust(int *ptr, u16 pkey)
int new_pkey;
dprintf1("%s() alloc loop: %d\n", __func__, i);
new_pkey = alloc_pkey();
- dprintf4("%s()::%d, err: %d pkey_reg: 0x%016llx"
+ dprintf4("%s()::%d, errno: %d pkey_reg: 0x%016llx"
" shadow: 0x%016llx\n",
- __func__, __LINE__, err, __read_pkey_reg(),
+ __func__, __LINE__, errno, __read_pkey_reg(),
shadow_pkey_reg);
read_pkey_reg(); /* for shadow checking */
dprintf2("%s() errno: %d ENOSPC: %d\n", __func__, errno,
ENOSPC);
--
2.35.1
[PATCH v5.18] powerpc/32: Fix overread/overwrite of thread_struct via ptrace
commit 8e127846fc97778a5e5c99bca1ce0bbc5ec9 upstream.
The ptrace PEEKUSR/POKEUSR (aka PEEKUSER/POKEUSER) API allows a process
to read/write registers of another process.
To get/set a register, the API takes an index into an imaginary address
space called the "USER area", where the registers of the process are
laid out in some fashion.
The kernel then maps that index to a particular register in its own data
structures and gets/sets the value.
The API only allows a single machine-word to be read/written at a time.
So 4 bytes on 32-bit kernels and 8 bytes on 64-bit kernels.
The way floating point registers (FPRs) are addressed is somewhat
complicated, because double precision float values are 64-bit even on
32-bit CPUs. That means on 32-bit kernels each FPR occupies two
word-sized locations in the USER area. On 64-bit kernels each FPR
occupies one word-sized location in the USER area.
Internally the kernel stores the FPRs in an array of u64s, or if VSX is
enabled, an array of pairs of u64s where one half of each pair stores
the FPR. Which half of the pair stores the FPR depends on the kernel's
endianness.
To handle the different layouts of the FPRs depending on VSX/no-VSX and
big/little endian, the TS_FPR() macro was introduced.
Unfortunately the TS_FPR() macro does not take into account the fact
that the addressing of each FPR differs between 32-bit and 64-bit
kernels. It just takes the index into the "USER area" passed from
userspace and indexes into the fp_state.fpr array.
On 32-bit there are 64 indexes that address FPRs, but only 32 entries in
the fp_state.fpr array, meaning the user can read/write 256 bytes past
the end of the array. Because the fp_state sits in the middle of the
thread_struct there are various fields than can be overwritten,
including some pointers. As such it may be exploitable.
It has also been observed to cause systems to hang or otherwise
misbehave when using gdbserver, and is probably the root cause of this
report which could not be easily reproduced:
https://lore.kernel.org/linuxppc-dev/dc38afe9-6b78-f3f5-666b-986939e40...@keymile.com/
Rather than trying to make the TS_FPR() macro even more complicated to
fix the bug, or add more macros, instead add a special-case for 32-bit
kernels. This is more obvious and hopefully avoids a similar bug
happening again in future.
Note that because 32-bit kernels never have VSX enabled the code doesn't
need to consider TS_FPRWIDTH/OFFSET at all. Add a BUILD_BUG_ON() to
ensure that 32-bit && VSX is never enabled.
Fixes: 87fec0514f61 ("powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers
in little endian builds")
Cc: sta...@vger.kernel.org # v3.13+
Reported-by: Ariel Miculas
Tested-by: Christophe Leroy
Signed-off-by: Michael Ellerman
Link: https://lore.kernel.org/r/20220609133245.573565-1-...@ellerman.id.au
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 20 ++--
arch/powerpc/kernel/ptrace/ptrace.c | 3 +++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 5dca19361316..09c49632bfe5 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,9 +17,13 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(data, >thread.TS_FPR(fpidx), sizeof(long));
- else
+ if (fpidx < (PT_FPSCR - PT_FPR0)) {
+ if (IS_ENABLED(CONFIG_PPC32))
+ // On 32-bit the index we are passed refers to 32-bit
words
+ *data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
+ else
+ memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
+ } else
*data = child->thread.fp_state.fpscr;
#else
*data = 0;
@@ -39,9 +43,13 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0))
- memcpy(>thread.TS_FPR(fpidx), , sizeof(long));
- else
+ if (fpidx < (PT_FPSCR - PT_FPR0)) {
+ if (IS_ENABLED(CONFIG_PPC32))
+ // On 32-bit the index we are passed refers to 32-bit
words
+ ((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
+ else
+ memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
+ } else
child->thread.fp_state.fpscr = data;
#endif
diff --git a/arch/powerpc/kernel/ptrace/ptrace.c
b/arch/powerpc/kernel/ptrace/ptrace.c
index 6d5026a9db4f..eab6fa59d9d2 100644
--- a/arch/powerpc/kernel/ptrace/ptrace.c
+++ b/arch/powerpc/kernel/ptrace/ptrace.c
@@ -450,4 +450,7 @@ void __init pt_regs_check(void)
#else
Re: [PATCH RFC v1 4/7] swiotlb: to implement io_tlb_high_mem
Hi Christoph, On 6/8/22 10:05 PM, Christoph Hellwig wrote: > All this really needs to be hidden under the hood. > Since this patch file has 200+ lines, would you please help clarify what does 'this' indicate? The idea of this patch: 1. Convert the functions to initialize swiotlb into callee. The callee accepts 'true' or 'false' as arguments to indicate whether it is for default or new swiotlb buffer, e.g., swiotlb_init_remap() into __swiotlb_init_remap(). 2. At the caller side to decide if we are going to call the callee to create the extra buffer. Do you mean the callee if still *too high level* and all the decision/allocation/initialization should be down at *lower level functions*? E.g., if I re-work the "struct io_tlb_mem" to make the 64-bit buffer as the 2nd array of io_tlb_mem->slots[32_or_64][index], the user will only notice it is the default 'io_tlb_default_mem', but will not be able to know if it is allocated from 32-bit or 64-bit buffer. Thank you very much for the feedback. Dongli Zhang
Re: [PATCH v4 15/18] PCI: dwc: Add dw_ prefix to the pcie_port structure name
gkai Hu , "linux-arm-ker...@lists.infradead.org"
, Roy Zang , Jingoo Han
, "linuxppc-dev@lists.ozlabs.org"
, Heiko Stuebner ,
"linux-ker...@vger.kernel.org" , Serge Semin
, Krzysztof Kozlowski
, Masami Hiramatsu ,
Pengutronix Kernel Team , Gustavo Pimentel
, Shawn Guo , Lucas Stach
Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org
Sender: "Linuxppc-dev"
On Fri, Jun 10, 2022 at 04:16:42PM +0200, Jesper Nilsson wrote:
> On Fri, Jun 10, 2022 at 10:25:31AM +0200, Serge Semin wrote:
> > All of the DW PCIe core driver entities have names with the dw_ prefix in
> > order to easily distinguish local and common PCIe name spaces. All except
> > the pcie_port structure which contains the DW PCIe Root Port descriptor.
> > For historical reason the structure has retained the original name since
> > commit 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos") when
> > the DW PCIe IP-core support was added to the kernel. Let's finally fix
> > that by adding the dw_ prefix to the structure name and by adding the _rp
> > suffix to be similar to the EP counterpart. Thus the name will be coherent
> > with the common driver naming policy. It shall make the driver code more
> > readable eliminating visual confusion between the local and generic PCI
> > name spaces.
>
> Hi Serge,
Hi Jesper
>
> I think that most variable and parameters of this type is named "pp" for
> "pcie_port".
> If this is the way we want to go, those should be changed also to "rp", right?
Basically you may be right, but the change you suggest is much harder
to provide and may cause additional problems I have much doubts it is
really required. One thing is to update the struct name, but a whole
another story is to change the variables definition especially across
all the platform drivers involved here and especially of such
frequently used object as the DW PCIe Root Port descriptor.
First of all what you suggest will affect much-much-much more code
lines than this one, which in its turn will eventually cause problems
with the backporting of the new patches to the older stable kernels
released before the one with the updated names. Secondly it is a
matter of a separate patch, which can be added by someone who would
think it was really required. So to speak I don't think that changing
the variable names worth it especially seeing the driver naming
convention isn't perfect at all in many other aspects like using name
"pci" of the dw_pcie structure instance.
-Sergey
>
> /Jesper
>
> > Signed-off-by: Serge Semin
> >
> > ---
> >
> > Changelog v4:
> > - This is a new patch created on the v4 lap of the series.
> > ---
> > drivers/pci/controller/dwc/pci-dra7xx.c | 12 +++
> > drivers/pci/controller/dwc/pci-exynos.c | 6 ++--
> > drivers/pci/controller/dwc/pci-imx6.c | 6 ++--
> > drivers/pci/controller/dwc/pci-keystone.c | 20 +--
> > drivers/pci/controller/dwc/pci-layerscape.c | 2 +-
> > drivers/pci/controller/dwc/pci-meson.c| 2 +-
> > drivers/pci/controller/dwc/pcie-al.c | 6 ++--
> > drivers/pci/controller/dwc/pcie-armada8k.c| 4 +--
> > drivers/pci/controller/dwc/pcie-artpec6.c | 4 +--
> > .../pci/controller/dwc/pcie-designware-host.c | 36 +--
> > .../pci/controller/dwc/pcie-designware-plat.c | 2 +-
> > drivers/pci/controller/dwc/pcie-designware.h | 30
> > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 +--
> > drivers/pci/controller/dwc/pcie-fu740.c | 2 +-
> > drivers/pci/controller/dwc/pcie-histb.c | 10 +++---
> > drivers/pci/controller/dwc/pcie-intel-gw.c| 6 ++--
> > drivers/pci/controller/dwc/pcie-keembay.c | 4 +--
> > drivers/pci/controller/dwc/pcie-kirin.c | 2 +-
> > drivers/pci/controller/dwc/pcie-qcom.c| 4 +--
> > drivers/pci/controller/dwc/pcie-spear13xx.c | 6 ++--
> > drivers/pci/controller/dwc/pcie-tegra194.c| 22 ++--
> > drivers/pci/controller/dwc/pcie-uniphier.c| 10 +++---
> > drivers/pci/controller/dwc/pcie-visconti.c| 6 ++--
> > 23 files changed, 103 insertions(+), 103 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c
> > b/drivers/pci/controller/dwc/pci-dra7xx.c
> > index dfcdeb432dc8..a174b680b2a7 100644
> > --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> > +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> > @@ -178,7 +178,7 @@ static void dra7xx_pcie_enable_interrupts(struct
> > dra7xx_pcie *dra7xx)
> > dra7xx_pcie_enable_msi_interrupts(dra7xx);
> > }
> >
> > -static int dra7xx_pcie_host_init(struct pcie_port *pp)
> > +static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> > @@ -202,7 +202,7 @@ static const struct irq_domain_ops intx_domain_ops = {
> > .xlate = pci_irqd_intx_xlate,
> > };
> >
> > -static int dra7xx_pcie_handle_msi(struct pcie_port
[powerpc:fixes-test] BUILD SUCCESS 8e1278444446fc97778a5e5c99bca1ce0bbc5ec9
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git fixes-test branch HEAD: 8e127846fc97778a5e5c99bca1ce0bbc5ec9 powerpc/32: Fix overread/overwrite of thread_struct via ptrace elapsed time: 1543m configs tested: 64 configs skipped: 101 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm64 defconfig arm64allyesconfig arm allmodconfig arm defconfig arm allyesconfig m68k allyesconfig m68k allmodconfig m68kdefconfig nios2 defconfig arc allyesconfig h8300allyesconfig xtensa allyesconfig arc defconfig sh allmodconfig s390defconfig s390 allmodconfig parisc defconfig parisc64defconfig parisc allyesconfig s390 allyesconfig sparc defconfig i386 allyesconfig sparcallyesconfig i386defconfig i386 debian-10.3-kselftests i386 debian-10.3 powerpc allyesconfig powerpc allnoconfig powerpc allmodconfig x86_64randconfig-a006 x86_64randconfig-a004 x86_64randconfig-a002 i386 randconfig-a012 i386 randconfig-a014 i386 randconfig-a016 arc randconfig-r043-20220608 s390 randconfig-r044-20220608 riscvrandconfig-r042-20220608 riscv defconfig riscvnommu_virt_defconfig riscv rv32_defconfig riscvnommu_k210_defconfig riscv allnoconfig riscvallmodconfig riscvallyesconfig um x86_64_defconfig um i386_defconfig x86_64 kexec x86_64 defconfig x86_64 allyesconfig x86_64 rhel-8.3 x86_64 rhel-8.3-func x86_64 rhel-8.3-syz x86_64rhel-8.3-kselftests x86_64 rhel-8.3-kunit clang tested configs: x86_64randconfig-a005 x86_64randconfig-a003 x86_64randconfig-a001 hexagon randconfig-r045-20220609 s390 randconfig-r044-20220609 riscvrandconfig-r042-20220609 hexagon randconfig-r041-20220609 hexagon randconfig-r045-20220608 hexagon randconfig-r041-20220608 -- 0-DAY CI Kernel Test Service https://01.org/lkp
[PATCH v2 5/5] bpf ppc32: Add instructions for atomic_[cmp]xchg
This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc32, both
of which include the BPF_FETCH flag. The kernel's atomic_cmpxchg
operation fundamentally has 3 operands, but we only have two register
fields. Therefore the operand we compare against (the kernel's API
calls it 'old') is hard-coded to be BPF_REG_R0. Also, kernel's
atomic_cmpxchg returns the previous value at dst_reg + off. JIT the
same for BPF too with return value put in BPF_REG_0.
BPF_REG_R0 = atomic_cmpxchg(dst_reg + off, BPF_REG_R0, src_reg);
Signed-off-by: Hari Bathini
---
Changes in v2:
* Moved variable declaration to avoid late declaration error on
some compilers.
* Tried to make code readable and compact.
arch/powerpc/net/bpf_jit_comp32.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_comp32.c
b/arch/powerpc/net/bpf_jit_comp32.c
index 28dc6a1a8f2f..43f1c76d48ce 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -297,6 +297,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
u32 ax_reg = bpf_to_ppc(BPF_REG_AX);
u32 tmp_reg = bpf_to_ppc(TMP_REG);
u32 size = BPF_SIZE(code);
+ u32 save_reg, ret_reg;
s16 off = insn[i].off;
s32 imm = insn[i].imm;
bool func_addr_fixed;
@@ -799,6 +800,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
* BPF_STX ATOMIC (atomic ops)
*/
case BPF_STX | BPF_ATOMIC | BPF_W:
+ save_reg = _R0;
+ ret_reg = src_reg;
+
bpf_set_seen_register(ctx, tmp_reg);
bpf_set_seen_register(ctx, ax_reg);
@@ -829,6 +833,21 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
case BPF_XOR | BPF_FETCH:
EMIT(PPC_RAW_XOR(_R0, _R0, src_reg));
break;
+ case BPF_CMPXCHG:
+ /*
+* Return old value in BPF_REG_0 for
BPF_CMPXCHG &
+* in src_reg for other cases.
+*/
+ ret_reg = bpf_to_ppc(BPF_REG_0);
+
+ /* Compare with old value in BPF_REG_0 */
+ EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), _R0));
+ /* Don't set if different from old value */
+ PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4);
+ fallthrough;
+ case BPF_XCHG:
+ save_reg = src_reg;
+ break;
default:
pr_err_ratelimited("eBPF filter atomic op code
%02x (@%d) unsupported\n",
code, i);
@@ -836,15 +855,15 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
}
/* store new value */
- EMIT(PPC_RAW_STWCX(_R0, tmp_reg, dst_reg));
+ EMIT(PPC_RAW_STWCX(save_reg, tmp_reg, dst_reg));
/* we're done if this succeeded */
PPC_BCC_SHORT(COND_NE, tmp_idx);
/* For the BPF_FETCH variant, get old data into src_reg
*/
if (imm & BPF_FETCH) {
- EMIT(PPC_RAW_MR(src_reg, ax_reg));
+ EMIT(PPC_RAW_MR(ret_reg, ax_reg));
if (!fp->aux->verifier_zext)
- EMIT(PPC_RAW_LI(src_reg_h, 0));
+ EMIT(PPC_RAW_LI(ret_reg - 1, 0)); /*
higher 32-bit */
}
break;
--
2.35.3
[PATCH v2 4/5] bpf ppc32: add support for BPF_ATOMIC bitwise operations
Adding instructions for ppc32 for
atomic_and
atomic_or
atomic_xor
atomic_fetch_add
atomic_fetch_and
atomic_fetch_or
atomic_fetch_xor
Signed-off-by: Hari Bathini
---
Changes in v2:
* Used an additional register (BPF_REG_AX)
- to avoid clobbering src_reg.
- to keep the lwarx reservation as intended.
- to avoid the odd switch/goto construct.
* Zero'ed out the higher 32-bit explicitly when required.
arch/powerpc/net/bpf_jit_comp32.c | 53 ---
1 file changed, 41 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_comp32.c
b/arch/powerpc/net/bpf_jit_comp32.c
index e46ed1e8c6ca..28dc6a1a8f2f 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -294,6 +294,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
u32 dst_reg_h = dst_reg - 1;
u32 src_reg = bpf_to_ppc(insn[i].src_reg);
u32 src_reg_h = src_reg - 1;
+ u32 ax_reg = bpf_to_ppc(BPF_REG_AX);
u32 tmp_reg = bpf_to_ppc(TMP_REG);
u32 size = BPF_SIZE(code);
s16 off = insn[i].off;
@@ -798,25 +799,53 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
* BPF_STX ATOMIC (atomic ops)
*/
case BPF_STX | BPF_ATOMIC | BPF_W:
- if (imm != BPF_ADD) {
- pr_err_ratelimited("eBPF filter atomic op code
%02x (@%d) unsupported\n",
- code, i);
- return -ENOTSUPP;
- }
-
- /* *(u32 *)(dst + off) += src */
-
bpf_set_seen_register(ctx, tmp_reg);
+ bpf_set_seen_register(ctx, ax_reg);
+
/* Get offset into TMP_REG */
EMIT(PPC_RAW_LI(tmp_reg, off));
+ tmp_idx = ctx->idx * 4;
/* load value from memory into r0 */
EMIT(PPC_RAW_LWARX(_R0, tmp_reg, dst_reg, 0));
- /* add value from src_reg into this */
- EMIT(PPC_RAW_ADD(_R0, _R0, src_reg));
- /* store result back */
+
+ /* Save old value in BPF_REG_AX */
+ if (imm & BPF_FETCH)
+ EMIT(PPC_RAW_MR(ax_reg, _R0));
+
+ switch (imm) {
+ case BPF_ADD:
+ case BPF_ADD | BPF_FETCH:
+ EMIT(PPC_RAW_ADD(_R0, _R0, src_reg));
+ break;
+ case BPF_AND:
+ case BPF_AND | BPF_FETCH:
+ EMIT(PPC_RAW_AND(_R0, _R0, src_reg));
+ break;
+ case BPF_OR:
+ case BPF_OR | BPF_FETCH:
+ EMIT(PPC_RAW_OR(_R0, _R0, src_reg));
+ break;
+ case BPF_XOR:
+ case BPF_XOR | BPF_FETCH:
+ EMIT(PPC_RAW_XOR(_R0, _R0, src_reg));
+ break;
+ default:
+ pr_err_ratelimited("eBPF filter atomic op code
%02x (@%d) unsupported\n",
+ code, i);
+ return -EOPNOTSUPP;
+ }
+
+ /* store new value */
EMIT(PPC_RAW_STWCX(_R0, tmp_reg, dst_reg));
/* we're done if this succeeded */
- PPC_BCC_SHORT(COND_NE, (ctx->idx - 3) * 4);
+ PPC_BCC_SHORT(COND_NE, tmp_idx);
+
+ /* For the BPF_FETCH variant, get old data into src_reg
*/
+ if (imm & BPF_FETCH) {
+ EMIT(PPC_RAW_MR(src_reg, ax_reg));
+ if (!fp->aux->verifier_zext)
+ EMIT(PPC_RAW_LI(src_reg_h, 0));
+ }
break;
case BPF_STX | BPF_ATOMIC | BPF_DW: /* *(u64 *)(dst + off) +=
src */
--
2.35.3
[PATCH v2 3/5] bpf ppc64: Add instructions for atomic_[cmp]xchg
This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc64, both
of which include the BPF_FETCH flag. The kernel's atomic_cmpxchg
operation fundamentally has 3 operands, but we only have two register
fields. Therefore the operand we compare against (the kernel's API
calls it 'old') is hard-coded to be BPF_REG_R0. Also, kernel's
atomic_cmpxchg returns the previous value at dst_reg + off. JIT the
same for BPF too with return value put in BPF_REG_0.
BPF_REG_R0 = atomic_cmpxchg(dst_reg + off, BPF_REG_R0, src_reg);
Signed-off-by: Hari Bathini
---
Changes in v2:
* Moved variable declaration to avoid late declaration error on
some compilers.
* Added an optimization for 32-bit cmpxchg with regard to
commit see commit 39491867ace5.
arch/powerpc/net/bpf_jit_comp64.c | 39 +++
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_comp64.c
b/arch/powerpc/net/bpf_jit_comp64.c
index c53236b3a8b1..29ee306d6302 100644
--- a/arch/powerpc/net/bpf_jit_comp64.c
+++ b/arch/powerpc/net/bpf_jit_comp64.c
@@ -360,6 +360,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
u32 size = BPF_SIZE(code);
u32 tmp1_reg = bpf_to_ppc(TMP_REG_1);
u32 tmp2_reg = bpf_to_ppc(TMP_REG_2);
+ u32 save_reg, ret_reg;
s16 off = insn[i].off;
s32 imm = insn[i].imm;
bool func_addr_fixed;
@@ -778,6 +779,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
*/
case BPF_STX | BPF_ATOMIC | BPF_W:
case BPF_STX | BPF_ATOMIC | BPF_DW:
+ save_reg = tmp2_reg;
+ ret_reg = src_reg;
+
/* Get offset into TMP_REG_1 */
EMIT(PPC_RAW_LI(tmp1_reg, off));
tmp_idx = ctx->idx * 4;
@@ -808,6 +812,24 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
case BPF_XOR | BPF_FETCH:
EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg));
break;
+ case BPF_CMPXCHG:
+ /*
+* Return old value in BPF_REG_0 for
BPF_CMPXCHG &
+* in src_reg for other cases.
+*/
+ ret_reg = bpf_to_ppc(BPF_REG_0);
+
+ /* Compare with old value in BPF_R0 */
+ if (size == BPF_DW)
+
EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg));
+ else
+
EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg));
+ /* Don't set if different from old value */
+ PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4);
+ fallthrough;
+ case BPF_XCHG:
+ save_reg = src_reg;
+ break;
default:
pr_err_ratelimited(
"eBPF filter atomic op code %02x (@%d)
unsupported\n",
@@ -817,15 +839,22 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
/* store new value */
if (size == BPF_DW)
- EMIT(PPC_RAW_STDCX(tmp2_reg, tmp1_reg,
dst_reg));
+ EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg,
dst_reg));
else
- EMIT(PPC_RAW_STWCX(tmp2_reg, tmp1_reg,
dst_reg));
+ EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg,
dst_reg));
/* we're done if this succeeded */
PPC_BCC_SHORT(COND_NE, tmp_idx);
- /* For the BPF_FETCH variant, get old value into
src_reg */
- if (imm & BPF_FETCH)
- EMIT(PPC_RAW_MR(src_reg, _R0));
+ if (imm & BPF_FETCH) {
+ EMIT(PPC_RAW_MR(ret_reg, _R0));
+ /*
+* Skip unnecessary zero-extension for 32-bit
cmpxchg.
+* For context, see commit 39491867ace5.
+*/
+ if (size != BPF_DW && imm == BPF_CMPXCHG &&
+ insn_is_zext([i + 1]))
+ addrs[++i] = ctx->idx * 4;
+ }
break;
/*
--
2.35.3
[PATCH v2 2/5] bpf ppc64: add support for atomic fetch operations
Adding instructions for ppc64 for
atomic[64]_fetch_add
atomic[64]_fetch_and
atomic[64]_fetch_or
atomic[64]_fetch_xor
Signed-off-by: Hari Bathini
---
* No changes in v2.
arch/powerpc/net/bpf_jit_comp64.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/net/bpf_jit_comp64.c
b/arch/powerpc/net/bpf_jit_comp64.c
index c421bedd0e98..c53236b3a8b1 100644
--- a/arch/powerpc/net/bpf_jit_comp64.c
+++ b/arch/powerpc/net/bpf_jit_comp64.c
@@ -787,17 +787,25 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
else
EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg,
0));
+ /* Save old value in _R0 */
+ if (imm & BPF_FETCH)
+ EMIT(PPC_RAW_MR(_R0, tmp2_reg));
+
switch (imm) {
case BPF_ADD:
+ case BPF_ADD | BPF_FETCH:
EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg));
break;
case BPF_AND:
+ case BPF_AND | BPF_FETCH:
EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg));
break;
case BPF_OR:
+ case BPF_OR | BPF_FETCH:
EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg));
break;
case BPF_XOR:
+ case BPF_XOR | BPF_FETCH:
EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg));
break;
default:
@@ -807,13 +815,17 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
return -EOPNOTSUPP;
}
- /* store result back */
+ /* store new value */
if (size == BPF_DW)
EMIT(PPC_RAW_STDCX(tmp2_reg, tmp1_reg,
dst_reg));
else
EMIT(PPC_RAW_STWCX(tmp2_reg, tmp1_reg,
dst_reg));
/* we're done if this succeeded */
PPC_BCC_SHORT(COND_NE, tmp_idx);
+
+ /* For the BPF_FETCH variant, get old value into
src_reg */
+ if (imm & BPF_FETCH)
+ EMIT(PPC_RAW_MR(src_reg, _R0));
break;
/*
--
2.35.3
[PATCH v2 1/5] bpf ppc64: add support for BPF_ATOMIC bitwise operations
Adding instructions for ppc64 for
atomic[64]_and
atomic[64]_or
atomic[64]_xor
Signed-off-by: Hari Bathini
---
* No changes in v2.
arch/powerpc/net/bpf_jit_comp64.c | 57 ---
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_comp64.c
b/arch/powerpc/net/bpf_jit_comp64.c
index 594c54931e20..c421bedd0e98 100644
--- a/arch/powerpc/net/bpf_jit_comp64.c
+++ b/arch/powerpc/net/bpf_jit_comp64.c
@@ -777,41 +777,42 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
struct codegen_context *
* BPF_STX ATOMIC (atomic ops)
*/
case BPF_STX | BPF_ATOMIC | BPF_W:
- if (imm != BPF_ADD) {
- pr_err_ratelimited(
- "eBPF filter atomic op code %02x (@%d)
unsupported\n",
- code, i);
- return -ENOTSUPP;
- }
-
- /* *(u32 *)(dst + off) += src */
-
- /* Get EA into TMP_REG_1 */
- EMIT(PPC_RAW_ADDI(tmp1_reg, dst_reg, off));
+ case BPF_STX | BPF_ATOMIC | BPF_DW:
+ /* Get offset into TMP_REG_1 */
+ EMIT(PPC_RAW_LI(tmp1_reg, off));
tmp_idx = ctx->idx * 4;
/* load value from memory into TMP_REG_2 */
- EMIT(PPC_RAW_LWARX(tmp2_reg, 0, tmp1_reg, 0));
- /* add value from src_reg into this */
- EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg));
- /* store result back */
- EMIT(PPC_RAW_STWCX(tmp2_reg, 0, tmp1_reg));
- /* we're done if this succeeded */
- PPC_BCC_SHORT(COND_NE, tmp_idx);
- break;
- case BPF_STX | BPF_ATOMIC | BPF_DW:
- if (imm != BPF_ADD) {
+ if (size == BPF_DW)
+ EMIT(PPC_RAW_LDARX(tmp2_reg, tmp1_reg, dst_reg,
0));
+ else
+ EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg,
0));
+
+ switch (imm) {
+ case BPF_ADD:
+ EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg));
+ break;
+ case BPF_AND:
+ EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg));
+ break;
+ case BPF_OR:
+ EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg));
+ break;
+ case BPF_XOR:
+ EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg));
+ break;
+ default:
pr_err_ratelimited(
"eBPF filter atomic op code %02x (@%d)
unsupported\n",
code, i);
- return -ENOTSUPP;
+ return -EOPNOTSUPP;
}
- /* *(u64 *)(dst + off) += src */
- EMIT(PPC_RAW_ADDI(tmp1_reg, dst_reg, off));
- tmp_idx = ctx->idx * 4;
- EMIT(PPC_RAW_LDARX(tmp2_reg, 0, tmp1_reg, 0));
- EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg));
- EMIT(PPC_RAW_STDCX(tmp2_reg, 0, tmp1_reg));
+ /* store result back */
+ if (size == BPF_DW)
+ EMIT(PPC_RAW_STDCX(tmp2_reg, tmp1_reg,
dst_reg));
+ else
+ EMIT(PPC_RAW_STWCX(tmp2_reg, tmp1_reg,
dst_reg));
+ /* we're done if this succeeded */
PPC_BCC_SHORT(COND_NE, tmp_idx);
break;
--
2.35.3
[PATCH v2 0/5] Atomics support for eBPF on powerpc
This patchset adds atomic operations to the eBPF instruction set on powerpc. The instructions that are added here can be summarised with this list of kernel operations for ppc64: * atomic[64]_[fetch_]add * atomic[64]_[fetch_]and * atomic[64]_[fetch_]or * atomic[64]_[fetch_]xor * atomic[64]_xchg * atomic[64]_cmpxchg and this list of kernel operations for ppc32: * atomic_[fetch_]add * atomic_[fetch_]and * atomic_[fetch_]or * atomic_[fetch_]xor * atomic_xchg * atomic_cmpxchg The following are left out of scope for this effort: * 64 bit operations on ppc32. * Explicit memory barriers, 16 and 8 bit operations on both ppc32 & ppc64. The first patch adds support for bitwsie atomic operations on ppc64. The next patch adds fetch variant support for these instructions. The third patch adds support for xchg and cmpxchg atomic operations on ppc64. Patch #4 adds support for 32-bit atomic bitwise operations on ppc32. patch #5 adds support for xchg and cmpxchg atomic operations on ppc32. Validated these changes successfully with atomics test cases in test_bpf testsuite and test_verifier & test_progs selftests. With test_bpf testsuite: all 147 atomics related test cases (both 32-bit & 64-bit) JIT'ed successfully on ppc64: test_bpf: Summary: 1026 PASSED, 0 FAILED, [1014/1014 JIT'ed] all 76 atomics related test cases (32-bit) JIT'ed successfully on ppc32: test_bpf: Summary: 1027 PASSED, 0 FAILED, [915/1015 JIT'ed] Changes in v2: * Moved variable declaration to avoid late declaration error on some compilers. Thanks to Russell for pointing this out. * For ppc64, added an optimization for 32-bit cmpxchg with regard to commit 39491867ace5. * For ppc32, used an additional register (BPF_REG_AX): - to avoid clobbering src_reg. - to keep the lwarx reservation as intended. - to avoid the odd switch/goto construct. * For ppc32, zero'ed out the higher 32-bit explicitly when required. Hari Bathini (5): bpf ppc64: add support for BPF_ATOMIC bitwise operations bpf ppc64: add support for atomic fetch operations bpf ppc64: Add instructions for atomic_[cmp]xchg bpf ppc32: add support for BPF_ATOMIC bitwise operations bpf ppc32: Add instructions for atomic_[cmp]xchg arch/powerpc/net/bpf_jit_comp32.c | 72 +++ arch/powerpc/net/bpf_jit_comp64.c | 96 ++- 2 files changed, 129 insertions(+), 39 deletions(-) -- 2.35.3
[PATCH] powerpc/prom_init: Fix build failure with GCC_PLUGIN_STRUCTLEAK_BYREF_ALL and KASAN
When CONFIG_KASAN is selected, we expect prom_init to use __memset()
because it is too early to use memset().
But with CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL, the compiler adds calls
to memset() to clear objects on stack, hence the following failure:
PROMCHK arch/powerpc/kernel/prom_init_check
Error: External symbol 'memset' referenced from prom_init.c
make[2]: *** [arch/powerpc/kernel/Makefile:204 :
arch/powerpc/kernel/prom_init_check] Erreur 1
prom_find_machine_type() is called from prom_init() and is called only
once, so lets put compat[] in BSS instead of stack to avoid that.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/prom_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 04694ec423f6..13d6cb188835 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2302,7 +2302,7 @@ static void __init prom_init_stdout(void)
static int __init prom_find_machine_type(void)
{
- char compat[256];
+ static char compat[256] __prombss;
int len, i = 0;
#ifdef CONFIG_PPC64
phandle rtas;
--
2.35.3
Re: [PATCH 1/6] powerpc: Add ZERO_GPRS macros for register clears
Hi! On Fri, Jun 10, 2022 at 01:32:58PM +1000, Rohan McLure wrote: > > On 2 Jun 2022, at 2:00 am, Segher Boessenkool > > wrote: > > This is for unary operations, not binary operations (there is only one > > item on the RHS). You can in principle put a string "a,b" in the rhs > > parameter, but in practice you need a or b to depend on the loop counter > > as well, so even such trickiness won't do. Make the naming less > > confusing, maybe? Or don't have an unused extra level of abstraction in > > the first place :-) > Yep I see how having a macro to perform rX = rX <> Y for arbitrary infix <> > and operand > is unlikely to find much use outside of ZERO_GPRS. Aha. On PowerPC (like on most RISC-like architectures) all the normal instructions are rD := rA OP rB, not rD := rD OP rA. It looks like that is our disconnect :-) Segher
[PATCH] tools/perf/tests: Fix session topology test comparison check
commit cfd7092c31ae ("perf test session topology: Fix test to
skip the test in guest environment") added check to skip the
testcase if the socket_id can't be fetched from topology info.
But the condition check uses strncmp which should be changed to
!strncmp and to correctly match platform. Patch fixes this
condition check.
Fixes: cfd7092c31ae ("perf test session topology: Fix test to skip the test in
guest environment")
Reported-by: Thomas Richter
Signed-off-by: Athira Rajeev
---
tools/perf/tests/topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/tests/topology.c b/tools/perf/tests/topology.c
index d23a9e322ff5..0b4f61b6cc6b 100644
--- a/tools/perf/tests/topology.c
+++ b/tools/perf/tests/topology.c
@@ -115,7 +115,7 @@ static int check_cpu_topology(char *path, struct
perf_cpu_map *map)
* physical_package_id will be set to -1. Hence skip this
* test if physical_package_id returns -1 for cpu from perf_cpu_map.
*/
- if (strncmp(session->header.env.arch, "powerpc", 7)) {
+ if (!strncmp(session->header.env.arch, "ppc64le", 7)) {
if (cpu__get_socket_id(perf_cpu_map__cpu(map, 0)) == -1)
return TEST_SKIP;
}
--
2.35.1
[PATCH V3 35/35] selftest/powerpc/pmu: Add test for hardware cache events
From: Kajol Jain
The testcase checks if the transalation of a generic hardware cache
event is done properly via perf interface. The hardware cache events
has type as PERF_TYPE_HW_CACHE and each event points to raw event
code id.
Testcase checks different combination of cache level,
cache event operation type and cache event result type and verify
for a given event code, whether transalation matches with the current
cache event mappings via perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../hw_cache_event_type_test.c| 88 +++
2 files changed, 90 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/hw_cache_event_type_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 755993d210f2..4e07d7046457 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -6,7 +6,8 @@ TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_te
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
group_constraint_l2l3_sel_test group_constraint_cache_test
group_constraint_thresh_cmp_test \
- group_constraint_unit_test group_constraint_thresh_ctl_test
group_constraint_thresh_sel_test
+ group_constraint_unit_test group_constraint_thresh_ctl_test
group_constraint_thresh_sel_test \
+ hw_cache_event_type_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/hw_cache_event_type_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/hw_cache_event_type_test.c
new file mode 100644
index ..a45b1da5b568
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/hw_cache_event_type_test.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Load Missed L1, for power9 its pointing to PM_LD_MISS_L1_FIN (0x2c04e) and
+ * for power10 its pointing to PM_LD_MISS_L1 (0x3e054)
+ *
+ * Hardware cache level : PERF_COUNT_HW_CACHE_L1D
+ * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_READ
+ * Hardware cache event result type : PERF_COUNT_HW_CACHE_RESULT_MISS
+ */
+#define EventCode_1 0x1
+/*
+ * Hardware cache level : PERF_COUNT_HW_CACHE_L1D
+ * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_WRITE
+ * Hardware cache event result type : PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ */
+#define EventCode_2 0x0100
+/*
+ * Hardware cache level : PERF_COUNT_HW_CACHE_DTLB
+ * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_WRITE
+ * Hardware cache event result type : PERF_COUNT_HW_CACHE_RESULT_ACCESS
+ */
+#define EventCode_3 0x0103
+/*
+ * Hardware cache level : PERF_COUNT_HW_CACHE_L1D
+ * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_READ
+ * Hardware cache event result type : Invalid ( >
PERF_COUNT_HW_CACHE_RESULT_MAX)
+ */
+#define EventCode_4 0x03
+
+/*
+ * A perf test to check valid hardware cache events.
+ */
+static int hw_cache_event_type_test(void)
+{
+ struct event event;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* Skip for Generic compat PMU */
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /* Init the event to test hardware cache event */
+ event_init_opts(, EventCode_1, PERF_TYPE_HW_CACHE, "event");
+
+ /* Expected to success as its pointing to L1 load miss */
+ FAIL_IF(event_open());
+ event_close();
+
+ /* Init the event to test hardware cache event */
+ event_init_opts(, EventCode_2, PERF_TYPE_HW_CACHE, "event");
+
+ /* Expected to fail as the corresponding cache event entry have 0 in
that index */
+ FAIL_IF(!event_open());
+ event_close();
+
+ /* Init the event to test hardware cache event */
+ event_init_opts(, EventCode_3, PERF_TYPE_HW_CACHE, "event");
+
+ /* Expected to fail as the corresponding cache event entry have -1 in
that index */
+ FAIL_IF(!event_open());
+ event_close();
+
+ /* Init the event to test hardware cache event */
+ event_init_opts(, EventCode_4, PERF_TYPE_HW_CACHE, "event");
+
+ /* Expected to fail as hardware cache event result type is Invalid */
+ FAIL_IF(!event_open());
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(hw_cache_event_type_test,
"hw_cache_event_type_test");
+}
--
2.35.1
[PATCH V3 34/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_sel field
From: Kajol Jain
Thresh select bits in the event code is used to program thresh_sel
field in Monitor Mode Control Register A (MMCRA: 45-47). When scheduling
events as a group, all events in that group should match value in these
bits. Otherwise event open for the sibling events will fail.
Testcase uses event code PM_MRK_INST_CMPL (0x401e0) as leader and
another event PM_THRESH_MET (0x101ec) as sibling event, and checks
if group constraint checks for thresh_sel field added correctly via
perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_thresh_sel_test.c| 63 +++
2 files changed, 64 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_sel_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 16cbb2e52865..755993d210f2 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -6,7 +6,7 @@ TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_te
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
group_constraint_l2l3_sel_test group_constraint_cache_test
group_constraint_thresh_cmp_test \
- group_constraint_unit_test group_constraint_thresh_ctl_test
+ group_constraint_unit_test group_constraint_thresh_ctl_test
group_constraint_thresh_sel_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_sel_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_sel_test.c
new file mode 100644
index ..50a8cd843ce7
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_sel_test.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Primary PMU events used here are PM_MRK_INST_CMPL (0x401e0) and
+ * PM_THRESH_MET (0x101ec).
+ * Threshold event selection used is issue to complete
+ * Sampling criteria is Load or Store only sampling
+ */
+#define EventCode_1 0x35340401e0
+#define EventCode_2 0x35540101ec
+#define EventCode_3 0x35340101ec
+
+/*
+ * Testcase for group constraint check of thresh_sel bits which is
+ * used to program thresh select field in Monitor Mode Control Register A
+ * (MMCRA: 45-57).
+ * All events in the group should match thresh sel bits otherwise
+ * event_open for the group will fail.
+ */
+static int group_constraint_thresh_sel(void)
+{
+ struct event event, leader;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* Init the events for the group contraint thresh select test */
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+
+ /* Expected to fail as sibling and leader event request different
thresh_sel bits */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_close();
+
+ /* Init the event for the group contraint thresh select test */
+ event_init(, EventCode_3);
+
+/* Expected to succeed as sibling and leader event request same
thresh_sel bits */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_thresh_sel,
"group_constraint_thresh_sel");
+}
--
2.35.1
[PATCH V3 33/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_ctl field
From: Kajol Jain
Thresh control bits in the event code is used to program thresh_ctl
field in Monitor Mode Control Register A (MMCRA: 48-55). When scheduling
events as a group, all events in that group should match value in these
bits. Otherwise event open for the sibling events will fail.
Testcase uses event code PM_MRK_INST_CMPL (0x401e0) as leader and
another event PM_THRESH_MET (101ec) as sibling event, and checks if
group constraint checks for thresh_ctl field added correctly via perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_thresh_ctl_test.c| 64 +++
2 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_ctl_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index f72c73b5b79a..16cbb2e52865 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -6,7 +6,7 @@ TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_te
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
group_constraint_l2l3_sel_test group_constraint_cache_test
group_constraint_thresh_cmp_test \
- group_constraint_unit_test
+ group_constraint_unit_test group_constraint_thresh_ctl_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_ctl_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_ctl_test.c
new file mode 100644
index ..e0852ebc1671
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_ctl_test.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Primary PMU events used here are PM_MRK_INST_CMPL (0x401e0) and
+ * PM_THRESH_MET (0x101ec).
+ * Threshold event selection used is issue to complete and issue to
+ * finished for cycles
+ * Sampling criteria is Load or Store only sampling
+ */
+#define EventCode_1 0x35340401e0
+#define EventCode_2 0x34340101ec
+#define EventCode_3 0x35340101ec
+
+/*
+ * Testcase for group constraint check of thresh_ctl bits which is
+ * used to program thresh compare field in Monitor Mode Control Register A
+ * (MMCR0: 48-55).
+ * All events in the group should match thresh ctl bits otherwise
+ * event_open for the group will fail.
+ */
+static int group_constraint_thresh_ctl(void)
+{
+ struct event event, leader;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* Init the events for the group contraint thresh control test */
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+
+ /* Expected to fail as sibling and leader event request different
thresh_ctl bits */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_close();
+
+ /* Init the event for the group contraint thresh control test */
+ event_init(, EventCode_3);
+
+/* Expected to succeed as sibling and leader event request same
thresh_ctl bits */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_thresh_ctl,
"group_constraint_thresh_ctl");
+}
--
2.35.1
[PATCH V3 32/35] selftest/powerpc/pmu: Add selftest for group constraint for unit and pmc field in p9
From: Kajol Jain
Unit and pmu bits in the event code is used to program unit and pmc
fields in Monitor Mode Control Register 1 (MMCR1). For power9 platform,
incase unit field value is within 6 to 9, one of the event in the group
should use PMC4. Otherwise event_open should fail for that group.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../group_constraint_unit_test.c | 74 +++
2 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_unit_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 374044062561..f72c73b5b79a 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -5,7 +5,8 @@ TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_te
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
- group_constraint_l2l3_sel_test group_constraint_cache_test
group_constraint_thresh_cmp_test
+ group_constraint_l2l3_sel_test group_constraint_cache_test
group_constraint_thresh_cmp_test \
+ group_constraint_unit_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_unit_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_unit_test.c
new file mode 100644
index ..a2c18923dcec
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_unit_test.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/* All successful D-side store dispatches for this thread with PMC 2 */
+#define EventCode_1 0x26080
+/* All successful D-side store dispatches for this thread with PMC 4 */
+#define EventCode_2 0x46080
+/* All successful D-side store dispatches for this thread that were L2 Miss
with PMC 3 */
+#define EventCode_3 0x36880
+
+/*
+ * Testcase for group constraint check of unit and pmc bits which is
+ * used to program corresponding unit and pmc field in Monitor Mode
+ * Control Register 1 (MMCR1)
+ * One of the event in the group should use PMC 4 incase units field
+ * value is within 6 to 9 otherwise event_open for the group will fail.
+ */
+static int group_constraint_unit(void)
+{
+ struct event *e, events[3];
+
+ /*
+* Check for platform support for the test.
+* Constraint to use PMC4 with one of the event in group,
+* when the unit is within 6 to 9 is only applicable on
+* power9.
+*/
+ SKIP_IF(platform_check_for_tests());
+ SKIP_IF(have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the events for the group contraint check for unit bits */
+ e = [0];
+ event_init(e, EventCode_1);
+
+/* Expected to fail as PMC 4 is not used with unit field value 6 to 9
*/
+ FAIL_IF(!event_open([0]));
+
+ /* Init the events for the group contraint check for unit bits */
+ e = [1];
+ event_init(e, EventCode_2);
+
+ /* Expected to pass as PMC 4 is used with unit field value 6 to 9 */
+ FAIL_IF(event_open([1]));
+
+ /* Init the event for the group contraint unit test */
+ e = [2];
+ event_init(e, EventCode_3);
+
+ /* Expected to fail as PMC4 is not being used */
+ FAIL_IF(!event_open_with_group([2], events[0].fd));
+
+ /* Expected to succeed as event using PMC4 */
+ FAIL_IF(event_open_with_group([2], events[1].fd));
+
+ event_close([0]);
+ event_close([1]);
+ event_close([2]);
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_unit, "group_constraint_unit");
+}
--
2.35.1
[PATCH V3 31/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_cmp field
From: Kajol Jain
Thresh compare bits for a event is used to program thresh compare
field in Monitor Mode Control Register A (MMCRA: 9-18 bits for
power9 and MMCRA: 8-18 bits for power10). When scheduling events
as a group, all events in that group should match value in
thresh compare bits. Otherwise event open for the sibling
events will fail.
Testcase uses event code "0x401e0" as leader and another event
"0x101ec" as sibling event, and checks for thresh compare
constraint via perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_thresh_cmp_test.c| 96 +++
2 files changed, 97 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_cmp_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index dc27ca2ffcad..374044062561 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -5,7 +5,7 @@ TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_te
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
- group_constraint_l2l3_sel_test group_constraint_cache_test
+ group_constraint_l2l3_sel_test group_constraint_cache_test
group_constraint_thresh_cmp_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_cmp_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_cmp_test.c
new file mode 100644
index ..9f1197104e8c
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_thresh_cmp_test.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Primary PMU events used here is PM_MRK_INST_CMPL (0x401e0) and
+ * PM_THRESH_MET (0x101ec)
+ * Threshold event selection used is issue to complete for cycles
+ * Sampling criteria is Load or Store only sampling
+ */
+#define p9_EventCode_1 0x13e35340401e0
+#define p9_EventCode_2 0x17d34340101ec
+#define p9_EventCode_3 0x13e35340101ec
+#define p10_EventCode_1 0x35340401e0
+#define p10_EventCode_2 0x35340101ec
+
+/*
+ * Testcase for group constraint check of thresh_cmp bits which is
+ * used to program thresh compare field in Monitor Mode Control Register A
+ * (MMCRA: 9-18 bits for power9 and MMCRA: 8-18 bits for power10).
+ * All events in the group should match thresh compare bits otherwise
+ * event_open for the group will fail.
+ */
+static int group_constraint_thresh_cmp(void)
+{
+ struct event event, leader;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ if (have_hwcap2(PPC_FEATURE2_ARCH_3_1)) {
+ /* Init the events for the group contraint check for thresh_cmp
bits */
+ event_init(, p10_EventCode_1);
+
+ /* Add the thresh_cmp value for leader in config1 */
+ leader.attr.config1 = 1000;
+ FAIL_IF(event_open());
+
+ event_init(, p10_EventCode_2);
+
+ /* Add the different thresh_cmp value from the leader event in
config1 */
+ event.attr.config1 = 2000;
+
+ /* Expected to fail as sibling and leader event request
different thresh_cmp bits */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_close();
+
+ /* Init the event for the group contraint thresh compare test */
+ event_init(, p10_EventCode_2);
+
+ /* Add the same thresh_cmp value for leader and sibling event
in config1 */
+ event.attr.config1 = 1000;
+
+ /* Expected to succeed as sibling and leader event request same
thresh_cmp bits */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+ } else {
+ /* Init the events for the group contraint check for thresh_cmp
bits */
+ event_init(, p9_EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, p9_EventCode_2);
+
+ /* Expected to fail as sibling and leader event request
different thresh_cmp bits */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_close();
+
+
[PATCH V3 30/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCR1 cache bits
From: Kajol Jain
Data and instruction cache qualifier bits in the event code is
used to program cache select field in Monitor Mode Control
Register 1 (MMCR1: 16-17). When scheduling events as a group, all
events in that group should match value in these bits. Otherwise
event open for the sibling events will fail.
Testcase uses event code "0x1100fc" as leader and other events
like "0x23e054" and "0x13e054" as sibling events to checks for
l1 cache select field constraints via perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_cache_test.c | 60 +++
2 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_cache_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 58e1a7a2ed4e..dc27ca2ffcad 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -5,7 +5,7 @@ TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_te
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
- group_constraint_l2l3_sel_test
+ group_constraint_l2l3_sel_test group_constraint_cache_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_cache_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_cache_test.c
new file mode 100644
index ..f4be05aa3a3d
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_cache_test.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/* All L1 D cache load references counted at finish, gated by reject */
+#define EventCode_1 0x1100fc
+/* Load Missed L1 */
+#define EventCode_2 0x23e054
+/* Load Missed L1 */
+#define EventCode_3 0x13e054
+
+/*
+ * Testcase for group constraint check of data and instructions
+ * cache qualifier bits which is used to program cache select field in
+ * Monitor Mode Control Register 1 (MMCR1: 16-17) for l1 cache.
+ * All events in the group should match cache select bits otherwise
+ * event_open for the group will fail.
+ */
+static int group_constraint_cache(void)
+{
+ struct event event, leader;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* Init the events for the group contraint check for l1 cache select
bits */
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+
+ /* Expected to fail as sibling event doesn't request same l1 cache
select bits as leader */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_close();
+
+ /* Init the event for the group contraint l1 cache select test */
+ event_init(, EventCode_3);
+
+ /* Expected to succeed as sibling event request same l1 cache select
bits as leader */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_cache, "group_constraint_cache");
+}
--
2.35.1
[PATCH V3 29/35] selftest/powerpc/pmu: Add selftest for group constraint check for MMCR0 l2l3_sel bits
From: Kajol Jain
In power10, L2L3 select bits in the event code is used to
program l2l3_sel field in Monitor Mode Control Register 0
(MMCR0: 56-60). When scheduling events as a group,
all events in that group should match value in these bits.
Otherwise event open for the sibling events will fail.
Testcase uses event code "0x01046080" as leader and another events
"0x26880" and "0x01026880" as sibling events, and checks for
l2l3_sel constraints via perf interface for ISA v3.1 platform.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../group_constraint_l2l3_sel_test.c | 64 +++
2 files changed, 66 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_l2l3_sel_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 0d56f1ef530f..58e1a7a2ed4e 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -4,7 +4,8 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
- blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test
+ blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test \
+ group_constraint_l2l3_sel_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_l2l3_sel_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_l2l3_sel_test.c
new file mode 100644
index ..85a636886069
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_l2l3_sel_test.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "utils.h"
+#include "../sampling_tests/misc.h"
+
+/* All successful D-side store dispatches for this thread */
+#define EventCode_1 0x01046080
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+#define EventCode_2 0x26880
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+#define EventCode_3 0x01026880
+
+/*
+ * Testcase for group constraint check of l2l3_sel bits which is
+ * used to program l2l3 select field in Monitor Mode Control Register 0
+ * (MMCR0: 56-60).
+ * All events in the group should match l2l3_sel bits otherwise
+ * event_open for the group should fail.
+ */
+static int group_constraint_l2l3_sel(void)
+{
+ struct event event, leader;
+
+ /*
+* Check for platform support for the test.
+* This test is only aplicable on power10
+*/
+ SKIP_IF(platform_check_for_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the events for the group contraint check for l2l3_sel bits */
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+
+ /* Expected to fail as sibling event doesn't request same l2l3_sel bits
as leader */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_close();
+
+ /* Init the event for the group contraint l2l3_sel test */
+ event_init(, EventCode_3);
+
+ /* Expected to succeed as sibling event request same l2l3_sel bits as
leader */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_l2l3_sel,
"group_constraint_l2l3_sel");
+}
--
2.35.1
[PATCH V3 28/35] selftest/powerpc/pmu: Add selftest for PERF_TYPE_HARDWARE events valid check
Testcase to ensure that using invalid event in generic
event for PERF_TYPE_HARDWARE will fail. Invalid generic
events in power10 are:
- PERF_COUNT_HW_BUS_CYCLES
- PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
- PERF_COUNT_HW_STALLED_CYCLES_BACKEND
- PERF_COUNT_HW_REF_CPU_CYCLES
Invalid generic events in power9 are:
- PERF_COUNT_HW_BUS_CYCLES
- PERF_COUNT_HW_REF_CPU_CYCLES
Testcase does event open for valid and invalid generic
events to ensure event open works for all valid events
and fails for invalid events.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../generic_events_valid_test.c | 130 ++
2 files changed, 131 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/generic_events_valid_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 50bcc036dddf..0d56f1ef530f 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -4,7 +4,7 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
- blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10
+ blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10 generic_events_valid_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/generic_events_valid_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/generic_events_valid_test.c
new file mode 100644
index ..0d237c15d3f2
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/generic_events_valid_test.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Testcase to ensure that using invalid event in generic
+ * event for PERF_TYPE_HARDWARE should fail
+ */
+
+static int generic_events_valid_test(void)
+{
+ struct event event;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* generic events is different in compat_mode */
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /*
+* Invalid generic events in power10:
+* - PERF_COUNT_HW_BUS_CYCLES
+* - PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
+* - PERF_COUNT_HW_STALLED_CYCLES_BACKEND
+* - PERF_COUNT_HW_REF_CPU_CYCLES
+*/
+ if (PVR_VER(mfspr(SPRN_PVR)) == POWER10) {
+ event_init_opts(, PERF_COUNT_HW_CPU_CYCLES,
PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init_opts(, PERF_COUNT_HW_INSTRUCTIONS,
+ PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init_opts(, PERF_COUNT_HW_CACHE_REFERENCES,
+ PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init_opts(, PERF_COUNT_HW_CACHE_MISSES,
PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init_opts(, PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
+ PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init_opts(, PERF_COUNT_HW_BRANCH_MISSES,
PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init_opts(, PERF_COUNT_HW_BUS_CYCLES,
PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(!event_open());
+
+ event_init_opts(, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND,
+ PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(!event_open());
+
+ event_init_opts(, PERF_COUNT_HW_STALLED_CYCLES_BACKEND,
+ PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(!event_open());
+
+ event_init_opts(, PERF_COUNT_HW_REF_CPU_CYCLES,
PERF_TYPE_HARDWARE, "event");
+ FAIL_IF(!event_open());
+ } else if (PVR_VER(mfspr(SPRN_PVR)) == POWER9) {
+ /*
+* Invalid generic events in power9:
+* - PERF_COUNT_HW_BUS_CYCLES
+* - PERF_COUNT_HW_REF_CPU_CYCLES
+*/
+
[PATCH V3 27/35] selftest/powerpc/pmu: Add selftest for event alternatives for power10
Platform specific PMU supports alternative event for some
of the event codes. During perf_event_open, it any event
group doesn't match constraint check criteria, further lookup
is done to find alternative event. Code checks to see if
it is possible to schedule event as group using alternative
events.
Testcase exercises the alternative event find code for
power10. Example, Using PMC1 to PMC4 in a group and again
trying to schedule PM_CYC_ALT (0x0001e) will fail since
this exceeds number of programmable events in group. But
since 0x600f4 is an alternative event for 0x0001e, it is
possible to use 0x0001e in the group. Testcase uses such
combination all events in power10 which has alternative event.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../event_alternatives_tests_p10.c| 109 ++
2 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p10.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index cf27e612290e..50bcc036dddf 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -4,7 +4,7 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
- blacklisted_events_test event_alternatives_tests_p9
+ blacklisted_events_test event_alternatives_tests_p9
event_alternatives_tests_p10
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p10.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p10.c
new file mode 100644
index ..8be7aada6523
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p10.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+#define PM_RUN_CYC_ALT 0x200f4
+#define PM_INST_DISP 0x200f2
+#define PM_BR_2PATH 0x20036
+#define PM_LD_MISS_L1 0x3e054
+#define PM_RUN_INST_CMPL_ALT 0x400fa
+
+#define EventCode_1 0x100fc
+#define EventCode_2 0x200fa
+#define EventCode_3 0x300fc
+#define EventCode_4 0x400fc
+
+/*
+ * Check for event alternatives.
+ */
+
+static int event_alternatives_tests_p10(void)
+{
+ struct event *e, events[5];
+ int i;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* PVR check is used here since PMU specific data like
+* alternative events is handled by respective PMU driver
+* code and using PVR will work correctly for all cases
+* including generic compat mode.
+*/
+ SKIP_IF(PVR_VER(mfspr(SPRN_PVR)) != POWER10);
+
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /*
+* Test for event alternative for 0x0001e
+* and 0x2.
+*/
+ e = [0];
+ event_init(e, 0x0001e);
+
+ e = [1];
+ event_init(e, EventCode_1);
+
+ e = [2];
+ event_init(e, EventCode_2);
+
+ e = [3];
+ event_init(e, EventCode_3);
+
+ e = [4];
+ event_init(e, EventCode_4);
+
+ FAIL_IF(event_open([0]));
+
+ /*
+* Expected to pass since 0x0001e has alternative event
+* 0x600f4 in PMC6. So it can go in with other events
+* in PMC1 to PMC4.
+*/
+ for (i = 1; i < 5; i++)
+ FAIL_IF(event_open_with_group([i], events[0].fd));
+
+ for (i = 0; i < 5; i++)
+ event_close([i]);
+
+ e = [0];
+ event_init(e, 0x2);
+
+ e = [1];
+ event_init(e, EventCode_1);
+
+ e = [2];
+ event_init(e, EventCode_2);
+
+ e = [3];
+ event_init(e, EventCode_3);
+
+ e = [4];
+ event_init(e, EventCode_4);
+
+ FAIL_IF(event_open([0]));
+
+ /*
+* Expected to pass since 0x00020 has alternative event
+* 0x500fa in PMC5. So it can go in with other events
+* in PMC1 to PMC4.
+*/
+ for (i = 1; i < 5; i++)
+ FAIL_IF(event_open_with_group([i], events[0].fd));
+
+ for (i = 0; i < 5; i++)
+ event_close([i]);
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(event_alternatives_tests_p10,
"event_alternatives_tests_p10");
+}
--
2.35.1
[PATCH V3 26/35] selftest/powerpc/pmu: Add selftest for event alternatives for power9
Platform specific PMU supports alternative event for some
of the event codes. During perf_event_open, it any event
group doesn't match constraint check criteria, further lookup
is done to find alternative event. Code checks to see if
it is possible to schedule event as group using alternative
events.
Testcase exercises the alternative event find code for
power9. Example, since events in same PMC can't go in as
a group, ideally using PM_RUN_CYC_ALT (0x200f4) and
PM_BR_TAKEN_CMPL (0x200fa) will fail. But since RUN_CYC
(0x600f4) is alternative event for 0x200f4, it is possible
to use 0x600f4 and 0x200fa as group. Testcase uses such
combination for all events in power9 which has an
alternative event.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../event_alternatives_tests_p9.c | 116 ++
2 files changed, 117 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p9.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index a5916a938154..cf27e612290e 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -4,7 +4,7 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
- blacklisted_events_test
+ blacklisted_events_test event_alternatives_tests_p9
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p9.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p9.c
new file mode 100644
index ..f7dcf0e0447c
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/event_alternatives_tests_p9.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+#define PM_RUN_CYC_ALT 0x200f4
+#define PM_INST_DISP 0x200f2
+#define PM_BR_2PATH 0x20036
+#define PM_LD_MISS_L1 0x3e054
+#define PM_RUN_INST_CMPL_ALT 0x400fa
+
+#define EventCode_1 0x200fa
+#define EventCode_2 0x200fc
+#define EventCode_3 0x300fc
+#define EventCode_4 0x400fc
+
+/*
+ * Check for event alternatives.
+ */
+
+static int event_alternatives_tests_p9(void)
+{
+ struct event event, leader;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* PVR check is used here since PMU specific data like
+* alternative events is handled by respective PMU driver
+* code and using PVR will work correctly for all cases
+* including generic compat mode.
+*/
+ SKIP_IF(PVR_VER(mfspr(SPRN_PVR)) != POWER9);
+
+ /* Skip for generic compat PMU */
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /* Init the event for PM_RUN_CYC_ALT */
+ event_init(, PM_RUN_CYC_ALT);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_1);
+
+ /*
+* Expected to pass since PM_RUN_CYC_ALT in PMC2 has alternative event
+* 0x600f4. So it can go in with EventCode_1 which is using PMC2
+*/
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ event_init(, PM_INST_DISP);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+ /*
+* Expected to pass since PM_INST_DISP in PMC2 has alternative event
+* 0x300f2 in PMC3. So it can go in with EventCode_2 which is using PMC2
+*/
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ event_init(, PM_BR_2PATH);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+ /*
+* Expected to pass since PM_BR_2PATH in PMC2 has alternative event
+* 0x40036 in PMC4. So it can go in with EventCode_2 which is using PMC2
+*/
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ event_init(, PM_LD_MISS_L1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_3);
+ /*
+* Expected to pass since PM_LD_MISS_L1 in PMC3 has alternative event
+* 0x400f0 in PMC4. So it can go in with EventCode_3 which is using PMC3
+*/
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ event_init(, PM_RUN_INST_CMPL_ALT);
+ FAIL_IF(event_open());
+
+
[PATCH V3 25/35] selftest/powerpc/pmu: Add selftest for blacklist events check in power9
Some of the events are blacklisted in power9. The list
of blacklisted events are noted in power9-events-list.h
When trying to do event open for any of these blacklisted
event will cause a failure. Testcase ensures that using
blacklisted events will cause event_open to fail in power9.
This test is only applicable on power9 DD2.1 and DD2.2 and
hence test adds checks to skip on other platforms.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../blacklisted_events_test.c | 132 ++
2 files changed, 134 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/blacklisted_events_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index e50570794337..a5916a938154 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -3,7 +3,8 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
- group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test
+ group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test \
+ blacklisted_events_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/blacklisted_events_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/blacklisted_events_test.c
new file mode 100644
index ..fafeff19cb34
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/blacklisted_events_test.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+#define PM_DTLB_MISS_16G 0x1c058
+#define PM_DERAT_MISS_2M 0x1c05a
+#define PM_DTLB_MISS_2M 0x1c05c
+#define PM_MRK_DTLB_MISS_1G 0x1d15c
+#define PM_DTLB_MISS_4K 0x2c056
+#define PM_DERAT_MISS_1G 0x2c05a
+#define PM_MRK_DERAT_MISS_2M 0x2d152
+#define PM_MRK_DTLB_MISS_4K 0x2d156
+#define PM_MRK_DTLB_MISS_16G 0x2d15e
+#define PM_DTLB_MISS_64K 0x3c056
+#define PM_MRK_DERAT_MISS_1G 0x3d152
+#define PM_MRK_DTLB_MISS_64K 0x3d156
+#define PM_DISP_HELD_SYNC_HOLD 0x4003c
+#define PM_DTLB_MISS_16M 0x4c056
+#define PM_DTLB_MISS_1G 0x4c05a
+#define PM_MRK_DTLB_MISS_16M 0x4c15e
+#define PM_MRK_ST_DONE_L2 0x10134
+#define PM_RADIX_PWC_L1_HIT 0x1f056
+#define PM_FLOP_CMPL 0x100f4
+#define PM_MRK_NTF_FIN 0x20112
+#define PM_RADIX_PWC_L2_HIT 0x2d024
+#define PM_IFETCH_THROTTLE 0x3405e
+#define PM_MRK_L2_TM_ST_ABORT_SISTER 0x3e15c
+#define PM_RADIX_PWC_L3_HIT 0x3f056
+#define PM_RUN_CYC_SMT2_MODE 0x3006c
+#define PM_TM_TX_PASS_RUN_INST 0x4e014
+
+#define PVR_POWER9_CUMULUS 0x2000
+
+int blacklist_events_dd21[] = {
+ PM_MRK_ST_DONE_L2,
+ PM_RADIX_PWC_L1_HIT,
+ PM_FLOP_CMPL,
+ PM_MRK_NTF_FIN,
+ PM_RADIX_PWC_L2_HIT,
+ PM_IFETCH_THROTTLE,
+ PM_MRK_L2_TM_ST_ABORT_SISTER,
+ PM_RADIX_PWC_L3_HIT,
+ PM_RUN_CYC_SMT2_MODE,
+ PM_TM_TX_PASS_RUN_INST,
+ PM_DISP_HELD_SYNC_HOLD,
+};
+
+int blacklist_events_dd22[] = {
+ PM_DTLB_MISS_16G,
+ PM_DERAT_MISS_2M,
+ PM_DTLB_MISS_2M,
+ PM_MRK_DTLB_MISS_1G,
+ PM_DTLB_MISS_4K,
+ PM_DERAT_MISS_1G,
+ PM_MRK_DERAT_MISS_2M,
+ PM_MRK_DTLB_MISS_4K,
+ PM_MRK_DTLB_MISS_16G,
+ PM_DTLB_MISS_64K,
+ PM_MRK_DERAT_MISS_1G,
+ PM_MRK_DTLB_MISS_64K,
+ PM_DISP_HELD_SYNC_HOLD,
+ PM_DTLB_MISS_16M,
+ PM_DTLB_MISS_1G,
+ PM_MRK_DTLB_MISS_16M,
+};
+
+int pvr_min;
+
+/*
+ * check for power9 support for 2.1 and
+ * 2.2 model where blacklist is applicable.
+ */
+int check_for_power9_version(void)
+{
+ pvr_min = PVR_MIN(mfspr(SPRN_PVR));
+
+ SKIP_IF(PVR_VER(pvr) != POWER9);
+ SKIP_IF(!(pvr & PVR_POWER9_CUMULUS));
+
+ SKIP_IF(!(3 - pvr_min));
+
+ return 0;
+}
+
+/*
+ * Testcase to ensure that using blacklisted bits in
+ * event code should cause event_open to fail in power9
+ */
+
+static int blacklisted_events(void)
+{
+ struct event event;
+ int i = 0;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* check for power9 support for 2.1 and
+* 2.2 model where blacklist is applicable.
+*/
+ SKIP_IF(check_for_power9_version());
+
+ /* Skip for Generic compat mode */
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ if (pvr_min == 1) {
+ for (i = 0; i < ARRAY_SIZE(blacklist_events_dd21); i++) {
+
[PATCH V3 24/35] selftest/powerpc/pmu: Add selftest for reserved bit check for MMCRA thresh_ctl field
Testcase for reserved bits in Monitor Mode
Control Register A (MMCRA) thresh_ctl bits.
For MMCRA[48:51]/[52:55]) Threshold Start/Stop,
0b/0b is reserved.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../reserved_bits_mmcra_thresh_ctl_test.c | 44 +++
2 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_thresh_ctl_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 1ce1ef4586fd..e50570794337 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -3,7 +3,7 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
- group_constraint_mmcra_sample_test invalid_event_code_test
+ group_constraint_mmcra_sample_test invalid_event_code_test
reserved_bits_mmcra_thresh_ctl_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_thresh_ctl_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_thresh_ctl_test.c
new file mode 100644
index ..4ea1c2f8913f
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_thresh_ctl_test.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Testcase for reserved bits in Monitor Mode
+ * Control Register A (MMCRA) thresh_ctl bits.
+ * For MMCRA[48:51]/[52:55]) Threshold Start/Stop,
+ * 0b/0b is reserved.
+ */
+
+static int reserved_bits_mmcra_thresh_ctl(void)
+{
+ struct event event;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* Skip for Generic compat PMU */
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /*
+* MMCRA[48:51]/[52:55]) Threshold Start/Stop
+* events Selection. 0b/0b is reserved.
+* Expected to fail when using these reserved values.
+*/
+ event_init(, 0xf0340401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x0f340401e0);
+ FAIL_IF(!event_open());
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(reserved_bits_mmcra_thresh_ctl,
"reserved_bits_mmcra_thresh_ctl");
+}
--
2.35.1
[PATCH V3 23/35] selftest/powerpc/pmu: Add selftest for checking invalid bits in event code
Some of the bits in the event code is reserved
for specific platforms. Event code bits 52-59 are
reserved in power9, whereas in power10, these are used
for programming Monitor Mode Control Register 3 (MMCR3).
Bit 9 in event code is reserved in power9, whereas it
is used for programming "radix_scope_qual" bit 18 in Monitor
Mode Control Register 1 (MMCR1).
Testcase to ensure that using reserved bits in
event code should cause event_open to fail.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../invalid_event_code_test.c | 67 +++
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/invalid_event_code_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 590b642ef900..1ce1ef4586fd 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -3,7 +3,7 @@ CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
- group_constraint_mmcra_sample_test
+ group_constraint_mmcra_sample_test invalid_event_code_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/invalid_event_code_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/invalid_event_code_test.c
new file mode 100644
index ..f51fcab837fc
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/invalid_event_code_test.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/* The data cache was reloaded from local core's L3 due to a demand load */
+#define EventCode_1 0x134001c040
+/* PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2 */
+#define EventCode_2 0x14242
+/* Event code with IFM, EBB, BHRB bits set in event code */
+#define EventCode_3 0xf01e
+
+/*
+ * Some of the bits in the event code is
+ * reserved for specific platforms.
+ * Event code bits 52-59 are reserved in power9,
+ * whereas in power10, these are used for programming
+ * Monitor Mode Control Register 3 (MMCR3).
+ * Bit 9 in event code is reserved in power9,
+ * whereas it is used for programming "radix_scope_qual"
+ * bit 18 in Monitor Mode Control Register 1 (MMCR1).
+ *
+ * Testcase to ensure that using reserved bits in
+ * event code should cause event_open to fail.
+ */
+
+static int invalid_event_code(void)
+{
+ struct event event;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* Events using MMCR3 bits and radix scope qual bits
+* should fail in power9 and should succeed in power10.
+* Init the events and check for pass/fail in event open.
+*/
+ if (have_hwcap2(PPC_FEATURE2_ARCH_3_1)) {
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+ event_close();
+
+ event_init(, EventCode_2);
+ FAIL_IF(event_open());
+ event_close();
+ } else {
+ event_init(, EventCode_1);
+ FAIL_IF(!event_open());
+
+ event_init(, EventCode_2);
+ FAIL_IF(!event_open());
+ }
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(invalid_event_code, "invalid_event_code");
+}
--
2.35.1
[PATCH V3 22/35] selftest/powerpc/pmu: Add selftest for group constraint check MMCRA sample bits
Events with different "sample" field values which is
used to program Monitor Mode Control Register A (MMCRA)
in a group will fail to schedule. Testcase uses event with
load only sampling mode as group leader and event with
store only sampling as sibling event. So that it can check
that using different sample bits in event code will fail
in event open for group of events
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../group_constraint_mmcra_sample_test.c | 54 +++
2 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_mmcra_sample_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 5dd482843572..590b642ef900 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -2,7 +2,8 @@
CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
- group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test
+ group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test \
+ group_constraint_mmcra_sample_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_mmcra_sample_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_mmcra_sample_test.c
new file mode 100644
index ..ff625b5d80eb
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_mmcra_sample_test.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+#define EventCode_1 0x35340401e0
+#define EventCode_2 0x353c0101ec
+#define EventCode_3 0x35340101ec
+/*
+ * Test that using different sample bits in
+ * event code cause failure in schedule for
+ * group of events.
+ */
+
+static int group_constraint_mmcra_sample(void)
+{
+ struct event event, leader;
+
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* Events with different "sample" field values
+* in a group will fail to schedule.
+* Use event with load only sampling mode as
+* group leader. Use event with store only sampling
+* as sibling event.
+*/
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode_2);
+
+ /* Expected to fail as sibling event doesn't use same sampling bits as
leader */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_init(, EventCode_3);
+
+ /* Expected to pass as sibling event use same sampling bits as leader */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_mmcra_sample,
"group_constraint_mmcra_sample");
+}
--
2.35.1
[PATCH V3 21/35] selftest/powerpc/pmu: Add selftest for group constraint for MMCRA Sampling Mode field
Testcase for reserved bits in Monitor Mode Control
Register A (MMCRA) Random Sampling Mode (SM) value.
As per Instruction Set Architecture (ISA), the values
0x5, 0x9, 0xD, 0x19, 0x1D, 0x1A, 0x1E are reserved
for sampling mode field. Test that having these reserved
bit values should cause event_open to fail. Input event
code in testcases uses these sampling bits along with
401e0 (PM_MRK_INST_CMPL).
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
...eserved_bits_mmcra_sample_elig_mode_test.c | 77 +++
2 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_sample_elig_mode_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 5b61fb0b9fd6..5dd482843572 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -2,7 +2,7 @@
CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
- group_constraint_repeat_test group_constraint_radix_scope_qual_test
+ group_constraint_repeat_test group_constraint_radix_scope_qual_test
reserved_bits_mmcra_sample_elig_mode_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_sample_elig_mode_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_sample_elig_mode_test.c
new file mode 100644
index ..4c119c821b99
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/reserved_bits_mmcra_sample_elig_mode_test.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Testcase for reserved bits in Monitor Mode Control
+ * Register A (MMCRA) Random Sampling Mode (SM) value.
+ * As per Instruction Set Architecture (ISA), the values
+ * 0x5, 0x9, 0xD, 0x19, 0x1D, 0x1A, 0x1E are reserved
+ * for sampling mode field. Test that having these reserved
+ * bit values should cause event_open to fail.
+ * Input event code uses these sampling bits along with
+ * 401e0 (PM_MRK_INST_CMPL).
+ */
+
+static int reserved_bits_mmcra_sample_elig_mode(void)
+{
+ struct event event;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /* Skip for Generic compat PMU */
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /*
+* MMCRA Random Sampling Mode (SM) values: 0x5
+* 0x9, 0xD, 0x19, 0x1D, 0x1A, 0x1E is reserved.
+* Expected to fail when using these reserved values.
+*/
+ event_init(, 0x50401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x90401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0xD0401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x190401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x1D0401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x1A0401e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x1E0401e0);
+ FAIL_IF(!event_open());
+
+ /*
+* MMCRA Random Sampling Mode (SM) value 0x10
+* is reserved in power10 and 0xC is reserved in
+* power9.
+*/
+ if (PVR_VER(mfspr(SPRN_PVR)) == POWER10) {
+ event_init(, 0x100401e0);
+ FAIL_IF(!event_open());
+ } else if (PVR_VER(mfspr(SPRN_PVR)) == POWER9) {
+ event_init(, 0xC0401e0);
+ FAIL_IF(!event_open());
+ }
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(reserved_bits_mmcra_sample_elig_mode,
+ "reserved_bits_mmcra_sample_elig_mode");
+}
--
2.35.1
[PATCH V3 20/35] selftest/powerpc/pmu: Add selftest for group constraint check for radix_scope_qual field
Testcase for group constraint check for radix_scope_qual
field which is used to program Monitor Mode Control Register
(MMCR1) bit 18. All events in the group should match radix_scope_qual
bit, otherwise event_open for the group should fail. Testcase uses
"0x14242" (PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2) with radix_scope_qual
bit set for power10.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_radix_scope_qual_test.c | 56 +++
2 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_radix_scope_qual_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index ace100e3226e..5b61fb0b9fd6 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -2,7 +2,7 @@
CFLAGS += -m64
TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
- group_constraint_repeat_test
+ group_constraint_repeat_test group_constraint_radix_scope_qual_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_radix_scope_qual_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_radix_scope_qual_test.c
new file mode 100644
index ..9225618b846a
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_radix_scope_qual_test.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/* PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2 */
+#define EventCode_1 0x14242
+/* PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L3 */
+#define EventCode_2 0x24242
+
+/*
+ * Testcase for group constraint check for radix_scope_qual
+ * field which is used to program Monitor Mode Control
+ * egister (MMCR1) bit 18.
+ * All events in the group should match radix_scope_qual,
+ * bits otherwise event_open for the group should fail.
+ */
+
+static int group_constraint_radix_scope_qual(void)
+{
+ struct event event, leader;
+
+ /*
+* Check for platform support for the test.
+* This test is aplicable on power10 only.
+*/
+ SKIP_IF(platform_check_for_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+ /* Init the events for the group contraint check for radix_scope_qual
bits */
+ event_init(, EventCode_1);
+ FAIL_IF(event_open());
+
+ event_init(, 0x200fc);
+
+ /* Expected to fail as sibling event doesn't request same
radix_scope_qual bits as leader */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_init(, EventCode_2);
+ /* Expected to pass as sibling event request same radix_scope_qual bits
as leader */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_radix_scope_qual,
+ "group_constraint_radix_scope_qual");
+}
--
2.35.1
[PATCH V3 19/35] selftest/powerpc/pmu: Add selftest for group constraint check when using same PMC
Testcase for group constraint check when using events
with same PMC. Multiple events in a group asking for
same PMC should fail. Testcase uses "0x22C040" on PMC2
as leader and also subling which is expected to fail.
Using PMC1 for sibling event should pass the test.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../group_constraint_repeat_test.c| 56 +++
2 files changed, 58 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_repeat_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 6310634c5beb..ace100e3226e 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
CFLAGS += -m64
-TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test
+TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test \
+ group_constraint_repeat_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_repeat_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_repeat_test.c
new file mode 100644
index ..371cd05bb3ed
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_repeat_test.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/* The processor's L1 data cache was reloaded */
+#define EventCode1 0x21C040
+#define EventCode2 0x22C040
+
+/*
+ * Testcase for group constraint check
+ * when using events with same PMC.
+ * Multiple events in a group shouldn't
+ * ask for same PMC. If so it should fail.
+ */
+
+static int group_constraint_repeat(void)
+{
+ struct event event, leader;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* Two events in a group using same PMC
+* should fail to get scheduled. Usei same PMC2
+* for leader and sibling event which is expected
+* to fail.
+*/
+ event_init(, EventCode1);
+ FAIL_IF(event_open());
+
+ event_init(, EventCode1);
+
+ /* Expected to fail since sibling event is requesting same PMC as
leader */
+ FAIL_IF(!event_open_with_group(, leader.fd));
+
+ event_init(, EventCode2);
+
+ /* Expected to pass since sibling event is requesting different PMC */
+ FAIL_IF(event_open_with_group(, leader.fd));
+
+ event_close();
+ event_close();
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_repeat, "group_constraint_repeat");
+}
--
2.35.1
[PATCH V3 18/35] selftest/powerpc/pmu: Add selftest to check constraint for number of counters in use.
Testcase for group constraint check for number of
counters in use. The number of programmable counters
is from PMC1 to PMC4. Testcase uses four events with PMC1
to PMC4 and 5th event without any PMC which is expected to fail
since it is exceeding the number of counters in use.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_pmc_count_test.c | 70 +++
2 files changed, 71 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc_count_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index c0eb28935e6e..6310634c5beb 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
CFLAGS += -m64
-TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test
+TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test group_constraint_pmc_count_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc_count_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc_count_test.c
new file mode 100644
index ..af7c5c75101c
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc_count_test.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Testcase for number of counters in use.
+ * The number of programmable counters is from
+ * performance monitor counter 1 to performance
+ * monitor counter 4 (PMC1-PMC4). If number of
+ * counters in use exceeds the limit, next event
+ * should fail to schedule.
+ */
+
+static int group_constraint_pmc_count(void)
+{
+ struct event *e, events[5];
+ int i;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* Test for number of counters in use.
+* Use PMC1 to PMC4 for leader and 3 sibling
+* events. Trying to open fourth event should
+* fail here.
+*/
+ e = [0];
+ event_init(e, 0x1001a);
+
+ e = [1];
+ event_init(e, 0x200fc);
+
+ e = [2];
+ event_init(e, 0x30080);
+
+ e = [3];
+ event_init(e, 0x40054);
+
+ e = [4];
+ event_init(e, 0x0002c);
+
+ FAIL_IF(event_open([0]));
+
+ /*
+* The event_open will fail on event 4 if constraint
+* check fails
+*/
+ for (i = 1; i < 5; i++) {
+ if (i == 4)
+ FAIL_IF(!event_open_with_group([i],
events[0].fd));
+ else
+ FAIL_IF(event_open_with_group([i],
events[0].fd));
+ }
+
+ for (i = 1; i < 4; i++)
+ event_close([i]);
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_pmc_count,
"group_constraint_pmc_count");
+}
--
2.35.1
[PATCH V3 17/35] selftest/powerpc/pmu: Add selftest to check PMC5/6 is excluded from some constraint checks
Events using Performance Monitor Counter 5 (PMC5) and
Performance Monitor Counter 6 (PMC6) should be excluded
from constraint check when scheduled along with group of
events. Example, combination of PMC5, PMC6, and an event
with cache bit will succeed to schedule though first two
events doesn't have cache bit set. Testcase use three events,
ie, 600f4(cycles), 500fa(instructions), 22C040 with cache
bit (dc_ic) set to test this constraint check.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_pmc56_exclude_constraints_test.c| 64 +++
2 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_pmc56_exclude_constraints_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index eb0017233b0b..c0eb28935e6e 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
CFLAGS += -m64
-TEST_GEN_PROGS := group_constraint_pmc56_test
+TEST_GEN_PROGS := group_constraint_pmc56_test
group_pmc56_exclude_constraints_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_pmc56_exclude_constraints_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_pmc56_exclude_constraints_test.c
new file mode 100644
index ..cff9ac170df6
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_pmc56_exclude_constraints_test.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include
+#include
+#include "../sampling_tests/misc.h"
+
+/*
+ * Testcase for group constraint check for
+ * Performance Monitor Counter 5 (PMC5) and also
+ * Performance Monitor Counter 6 (PMC6).
+ * Test that pmc5/6 is excluded from constraint
+ * check when scheduled along with group of events.
+ */
+
+static int group_pmc56_exclude_constraints(void)
+{
+ struct event *e, events[3];
+ int i;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* PMC5/6 is excluded from constraint bit
+* check along with group of events. Use
+* group of events with PMC5, PMC6 and also
+* event with cache bit (dc_ic) set. Test expects
+* this set of events to go in as a group.
+*/
+ e = [0];
+ event_init(e, 0x500fa);
+
+ e = [1];
+ event_init(e, 0x600f4);
+
+ e = [2];
+ event_init(e, 0x22C040);
+
+ FAIL_IF(event_open([0]));
+
+ /*
+* The event_open will fail if constraint check fails.
+* Since we are asking for events in a group and since
+* PMC5/PMC6 is excluded from group constraints, even_open
+* should pass.
+*/
+ for (i = 1; i < 3; i++)
+ FAIL_IF(event_open_with_group([i], events[0].fd));
+
+ for (i = 0; i < 3; i++)
+ event_close([i]);
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_pmc56_exclude_constraints,
"group_pmc56_exclude_constraints");
+}
--
2.35.1
[PATCH V3 16/35] selftest/powerpc/pmu: Add selftest for group constraint check for PMC5 and PMC6
Events using Performance Monitor Counter 5 (PMC5) and
Performance Monitor Counter 6 (PMC6) can't have other fields in
event code like cache bits, thresholding or marked bit. PMC5 and PMC6
only supports base events: ie 500fa and 600f4. Other combinations
should fail. Testcase tries setting other bits in event code for
500fa and 600f4 to check this scenario.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_pmc56_test.c | 63 +++
2 files changed, 64 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc56_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
index 6377ae205064..eb0017233b0b 100644
--- a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
CFLAGS += -m64
-TEST_GEN_PROGS :=
+TEST_GEN_PROGS := group_constraint_pmc56_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc56_test.c
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc56_test.c
new file mode 100644
index ..f5ee4796d46c
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc56_test.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include "../event.h"
+#include "../sampling_tests/misc.h"
+
+/*
+ * Testcase for checking constraint checks for
+ * Performance Monitor Counter 5 (PMC5) and also
+ * Performance Monitor Counter 6 (PMC6). Events using
+ * PMC5/PMC6 shouldn't have other fields in event
+ * code like cache bits, thresholding or marked bit.
+ */
+
+static int group_constraint_pmc56(void)
+{
+ struct event event;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* Events using PMC5 and PMC6 with cache bit
+* set in event code is expected to fail.
+*/
+ event_init(, 0x2500fa);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x2600f4);
+ FAIL_IF(!event_open());
+
+ /*
+* PMC5 and PMC6 only supports base events:
+* ie 500fa and 600f4. Other combinations
+* should fail.
+*/
+ event_init(, 0x501e0);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x6001e);
+ FAIL_IF(!event_open());
+
+ event_init(, 0x501fa);
+ FAIL_IF(!event_open());
+
+ /*
+* Events using PMC5 and PMC6 with random
+* sampling bits set in event code should fail
+* to schedule.
+*/
+ event_init(, 0x35340500fa);
+ FAIL_IF(!event_open());
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(group_constraint_pmc56, "group_constraint_pmc56");
+}
--
2.35.1
[PATCH V3 15/35] selftest/powerpc/pmu: Add support for perf event code tests
Add new folder for enabling perf event code tests which includes checking for group constraints, valid/invalid events, also checks for event excludes, alternatives so on. A new folder "event_code_tests", is created under "selftests/powerpc/pmu". Also updates the corresponding Makefiles in "selftests/powerpc" and "event_code_tests" folder. Signed-off-by: Athira Rajeev --- tools/testing/selftests/powerpc/pmu/Makefile | 11 +-- .../selftests/powerpc/pmu/event_code_tests/Makefile | 9 + 2 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile diff --git a/tools/testing/selftests/powerpc/pmu/Makefile b/tools/testing/selftests/powerpc/pmu/Makefile index edbd96d3b2ab..30803353bd7c 100644 --- a/tools/testing/selftests/powerpc/pmu/Makefile +++ b/tools/testing/selftests/powerpc/pmu/Makefile @@ -8,7 +8,7 @@ EXTRA_SOURCES := ../harness.c event.c lib.c ../utils.c top_srcdir = ../../../../.. include ../../lib.mk -all: $(TEST_GEN_PROGS) ebb sampling_tests +all: $(TEST_GEN_PROGS) ebb sampling_tests event_code_tests $(TEST_GEN_PROGS): $(EXTRA_SOURCES) @@ -27,6 +27,7 @@ override define RUN_TESTS $(DEFAULT_RUN_TESTS) TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests + TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests endef DEFAULT_EMIT_TESTS := $(EMIT_TESTS) @@ -34,6 +35,7 @@ override define EMIT_TESTS $(DEFAULT_EMIT_TESTS) TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests + TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests endef DEFAULT_INSTALL_RULE := $(INSTALL_RULE) @@ -41,12 +43,14 @@ override define INSTALL_RULE $(DEFAULT_INSTALL_RULE) TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install + TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install endef clean: $(RM) $(TEST_GEN_PROGS) $(OUTPUT)/loop.o TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean + TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean ebb: TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all @@ -54,4 +58,7 @@ ebb: sampling_tests: TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all -.PHONY: all run_tests clean ebb sampling_tests +event_code_tests: + TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all + +.PHONY: all run_tests clean ebb sampling_tests event_code_tests diff --git a/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile new file mode 100644 index ..6377ae205064 --- /dev/null +++ b/tools/testing/selftests/powerpc/pmu/event_code_tests/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +CFLAGS += -m64 + +TEST_GEN_PROGS := + +top_srcdir = ../../../../../.. +include ../../../lib.mk + +$(TEST_GEN_PROGS): ../../harness.c ../../utils.c ../event.c ../lib.c ../sampling_tests/misc.h ../sampling_tests/misc.c -- 2.35.1
[PATCH V3 14/35] selftest/powerpc/pmu: Add interface test for bhrb disable field for non-branch samples
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Incase sample is not of branch type, bhrb disable bit is explicitly
set to 1. Testcase checks if the bhrb disable bit is set of MMCRA
register via perf interface for ISA v3.1 platform
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../mmcra_bhrb_disable_no_branch_test.c | 64 +++
2 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_no_branch_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index f966d3359c6b..9e67351fb252 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -7,7 +7,7 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test \
mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
intr_regs_no_crash_wo_pmu_test \
- bhrb_filter_map_test mmcr1_sel_unit_cache_test
+ bhrb_filter_map_test mmcr1_sel_unit_cache_test
mmcra_bhrb_disable_no_branch_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_no_branch_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_no_branch_test.c
new file mode 100644
index ..488c865387e4
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_no_branch_test.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/* Instructions */
+#define EventCode 0x500fa
+
+/*
+ * A perf sampling test for mmcra
+ * field: bhrb_disable.
+ */
+static int mmcra_bhrb_disable_no_branch_test(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /*
+* Check for platform support for the test.
+* This test is only aplicable on power10
+*/
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+/* Init the event for the sampling test */
+ event_init_sampling(, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.exclude_kernel = 1;
+
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ FAIL_IF(event_enable());
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(1);
+
+ FAIL_IF(event_disable());
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that bhrb_disable bit is set in MMCRA for non-branch samples
*/
+ FAIL_IF(!get_mmcra_bhrb_disable(get_reg_value(intr_regs, "MMCRA"), 5));
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(mmcra_bhrb_disable_no_branch_test,
"mmcra_bhrb_disable_no_branch_test");
+}
--
2.35.1
[PATCH V3 13/35] selftest/powerpc/pmu: Add selftest for mmcr1 pmcxsel/unit/cache fields
The testcase uses event code "0x21c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../mmcr1_sel_unit_cache_test.c | 77 +++
2 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index ed9befc2f836..f966d3359c6b 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -7,7 +7,7 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test \
mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
intr_regs_no_crash_wo_pmu_test \
- bhrb_filter_map_test
+ bhrb_filter_map_test mmcr1_sel_unit_cache_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
new file mode 100644
index ..f0c003282630
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+#define MALLOC_SIZE (0x1 * 10) /* Ought to be enough .. */
+
+/* The data cache was reloaded from local core's L3 due to a demand load */
+#define EventCode 0x21c040
+
+/*
+ * A perf sampling test for mmcr1
+ * fields : pmcxsel, unit, cache.
+ */
+static int mmcr1_sel_unit_cache(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ char *p;
+ int i;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ p = malloc(MALLOC_SIZE);
+ FAIL_IF(!p);
+
+ /* Init the event for the sampling test */
+ event_init_sampling(, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.sample_period = 1;
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ event_enable();
+
+ /* workload to make the event overflow */
+ for (i = 0; i < MALLOC_SIZE; i += 0x1)
+ p[i] = i;
+
+ event_disable();
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /*
+* Verify that pmcxsel, unit and cache field of MMCR1
+* match with corresponding event code fields
+*/
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, pmcxsel) !=
+ get_mmcr1_pmcxsel(get_reg_value(intr_regs, "MMCR1"),
1));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, unit) !=
+ get_mmcr1_unit(get_reg_value(intr_regs, "MMCR1"), 1));
+ FAIL_IF(EV_CODE_EXTRACT(event.attr.config, cache) !=
+ get_mmcr1_cache(get_reg_value(intr_regs, "MMCR1"), 1));
+
+ free(p);
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcr1_sel_unit_cache, "mmcr1_sel_unit_cache"));
+}
--
2.35.1
[PATCH V3 12/35] selftest/powerpc/pmu: Add selftest for checking valid and invalid bhrb filter maps
For PERF_SAMPLE_BRANCH_STACK sample type, different
branch_sample_type, ie branch filters are supported.
All the branch filters are not supported in powerpc.
Example, power10 platform supports any, ind_call and
cond branch filters. Whereas, it is different in power9.
Testcase checks event open for invalid and valid branch
sample types. The branch types for testcase are picked
from "perf_branch_sample_type" in perf_event.h
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 3 +-
.../pmu/sampling_tests/bhrb_filter_map_test.c | 105 ++
2 files changed, 107 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_filter_map_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 8d4566dac440..ed9befc2f836 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -6,7 +6,8 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test \
- mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
intr_regs_no_crash_wo_pmu_test
+ mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
intr_regs_no_crash_wo_pmu_test \
+ bhrb_filter_map_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_filter_map_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_filter_map_test.c
new file mode 100644
index ..8182647c63c8
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_filter_map_test.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/*
+ * A perf sampling test to check bhrb filter
+ * map. All the branch filters are not supported
+ * in powerpc. Supported filters in:
+ * power10: any, any_call, ind_call, cond
+ * power9: any, any_call
+ *
+ * Testcase checks event open for invalid bhrb filter
+ * types should fail and valid filter types should pass.
+ * Testcase does validity check for these branch
+ * sample types.
+ */
+
+/* Invalid types for powerpc */
+/* Valid bhrb filters in power9/power10 */
+int bhrb_filter_map_valid_common[] = {
+ PERF_SAMPLE_BRANCH_ANY,
+ PERF_SAMPLE_BRANCH_ANY_CALL,
+};
+
+/* Valid bhrb filters in power10 */
+int bhrb_filter_map_valid_p10[] = {
+ PERF_SAMPLE_BRANCH_IND_CALL,
+ PERF_SAMPLE_BRANCH_COND,
+};
+
+#define EventCode 0x1001e
+
+static int bhrb_filter_map_test(void)
+{
+ struct event event;
+ int i;
+
+ /* Check for platform support for the test */
+ SKIP_IF(platform_check_for_tests());
+
+ /*
+* Skip for Generic compat PMU since
+* bhrb filters is not supported
+*/
+ SKIP_IF(check_for_generic_compat_pmu());
+
+ /* Init the event for the sampling test */
+ event_init(, EventCode);
+
+ event.attr.sample_period = 1000;
+ event.attr.sample_type = PERF_SAMPLE_BRANCH_STACK;
+ event.attr.disabled = 1;
+
+ /* Invalid filter maps which are expected to fail in event_open */
+ for (i = PERF_SAMPLE_BRANCH_USER_SHIFT; i <
PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
+ /* Skip the valid branch sample type */
+ if (i == PERF_SAMPLE_BRANCH_ANY_SHIFT || i ==
PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT \
+ || i == PERF_SAMPLE_BRANCH_IND_CALL_SHIFT || i ==
PERF_SAMPLE_BRANCH_COND_SHIFT)
+ continue;
+ event.attr.branch_sample_type = 1U << i;
+ FAIL_IF(!event_open());
+ }
+
+ /* valid filter maps for power9/power10 which are expected to pass in
event_open */
+ for (i = 0; i < ARRAY_SIZE(bhrb_filter_map_valid_common); i++) {
+ event.attr.branch_sample_type = bhrb_filter_map_valid_common[i];
+ FAIL_IF(event_open());
+ event_close();
+ }
+
+ /*
+* filter maps which are valid in power10 and invalid in power9.
+* PVR check is used here since PMU specific data like bhrb filter
+* alternative tests is handled by respective PMU driver code and
+* using PVR will work correctly for all cases including generic
+* compat mode.
+*/
+ if (PVR_VER(mfspr(SPRN_PVR)) == POWER10) {
+ for (i = 0; i < ARRAY_SIZE(bhrb_filter_map_valid_p10); i++) {
+ event.attr.branch_sample_type =
[PATCH V3 11/35] selftest/powerpc/pmu: Add selftest to check PERF_SAMPLE_REGS_INTR option will not crash on any platforms
With sampling, --intr-regs option is used for capturing
interrupt regs. When --intr-regs option is used, PMU code
uses is_sier_available() function which uses PMU flags in
the code. In environment where platform specific PMU is
not registered, PMU flags is not defined. A fix was added
in kernel to address crash while accessing is_sier_available()
function when pmu is not set. commit f75e7d73bdf7 ("powerpc/perf:
Fix crash with is_sier_available when pmu is not set").
Add perf sampling test to exercise this code and make sure
enabling intr_regs shouldn't crash in any platform. Testcase
uses software event cycles since software event will work even
in cases without PMU.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../intr_regs_no_crash_wo_pmu_test.c | 57 +++
2 files changed, 58 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/intr_regs_no_crash_wo_pmu_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 8d4839cde013..8d4566dac440 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -6,7 +6,7 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test \
- mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
+ mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
intr_regs_no_crash_wo_pmu_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/intr_regs_no_crash_wo_pmu_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/intr_regs_no_crash_wo_pmu_test.c
new file mode 100644
index ..839d2d225da0
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/sampling_tests/intr_regs_no_crash_wo_pmu_test.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/*
+ * A perf sampling test for making sure
+ * sampling with -intr-regs doesn't crash
+ * in any environment, say:
+ * - With generic compat PMU
+ * - without any PMU registered
+ * - With platform specific PMU.
+ * A fix for crash with intr_regs was
+ * addressed in commit: f75e7d73bdf7 in kernel.
+ *
+ * This testcase exercises this code path by doing
+ * intr_regs using software event. Software event is
+ * used since s/w event will work even in platform
+ * without PMU.
+ */
+static int intr_regs_no_crash_wo_pmu_test(void)
+{
+ struct event event;
+
+ /*
+* Init the event for the sampling test.
+* This uses software event which works on
+* any platform.
+*/
+ event_init_opts(, 0, PERF_TYPE_SOFTWARE, "cycles");
+
+ event.attr.sample_period = 1000;
+ event.attr.sample_type = PERF_SAMPLE_REGS_INTR;
+ event.attr.disabled = 1;
+
+ /*
+* Return code of event_open is not considered
+* since test just expects no crash from using
+* PERF_SAMPLE_REGS_INTR.
+*/
+ event_open();
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(intr_regs_no_crash_wo_pmu_test,
"intr_regs_no_crash_wo_pmu_test");
+}
--
2.35.1
[PATCH V3 10/35] selftest/powerpc/pmu: Add selftest to check branch stack enablement will not crash on any platforms
While enabling branch stack for an event, BHRB (Branch History
Rolling Buffer) filter is set using bhrb_filter_map() callback.
This callback is not defined for cases like generic_compat_pmu
or in case where there is no PMU registered. A fix was added
in kernel to address a crash issue observed while enabling branch
stack for environments which doesn't have this callback.
commit b460b512417a ("powerpc/perf: Fix crashes with
generic_compat_pmu & BHRB").
Add perf sampling test to exercise this code path and make
sure enabling branch stack shouldn't crash in any platform.
Testcase uses software event cycles since software event is
available and can be used even in cases without PMU.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../bhrb_no_crash_wo_pmu_test.c | 59 +++
2 files changed, 60 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_no_crash_wo_pmu_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index f4da49d55d57..8d4839cde013 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -6,7 +6,7 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test \
- mmcra_bhrb_disable_test
+ mmcra_bhrb_disable_test bhrb_no_crash_wo_pmu_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_no_crash_wo_pmu_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_no_crash_wo_pmu_test.c
new file mode 100644
index ..4644c6782974
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_no_crash_wo_pmu_test.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/*
+ * A perf sampling test for making sure
+ * enabling branch stack doesn't crash in any
+ * environment, say:
+ * - With generic compat PMU
+ * - without any PMU registered
+ * - With platform specific PMU
+ * A fix for bhrb sampling crash was added in kernel
+ * via commit: b460b512417a ("powerpc/perf: Fix crashes
+ * with generic_compat_pmu & BHRB")
+ *
+ * This testcase exercises this code by doing branch
+ * stack enable for software event. s/w event is used
+ * since software event will work even in platform
+ * without PMU.
+ */
+static int bhrb_no_crash_wo_pmu_test(void)
+{
+ struct event event;
+
+ /*
+* Init the event for the sampling test.
+* This uses software event which works on
+* any platform.
+*/
+ event_init_opts(, 0, PERF_TYPE_SOFTWARE, "cycles");
+
+ event.attr.sample_period = 1000;
+ event.attr.sample_type = PERF_SAMPLE_BRANCH_STACK;
+ event.attr.disabled = 1;
+
+ /*
+* Return code of event_open is not
+* considered since test just expects no crash from
+* using PERF_SAMPLE_BRANCH_STACK. Also for environment
+* like generic compat PMU, branch stack is unsupported.
+*/
+ event_open();
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(bhrb_no_crash_wo_pmu_test,
"bhrb_no_crash_wo_pmu_test");
+}
--
2.35.1
[PATCH V3 09/35] selftest/powerpc/pmu: Refactor the platform check and add macros to find array size/PVR
The platform check for selftest support "check_pvr_for_sampling_tests"
is specific to sampling tests which includes PVR check, presence of
PMU and extended regs support. Extended regs support is needed for
sampling tests which tests whether PMU registers are programmed
correctly. There could be other sampling tests which may not need
extended regs, example, bhrb filter tests which only needs validity
check via event open.
Hence refactor the platform check to have a common function
"platform_check_for_tests" that checks only for PVR check
and presence of PMU. The existing function
"check_pvr_for_sampling_tests" will invoke the common function
and also will include checks for extended regs specific for
sampling. The common function can also be used by tests other
than sampling like event code tests.
Add macro to find array size ("ARRAY_SIZE") to sampling
tests "misc.h" file. This can be used in next tests to
find event array size. Also update "include/reg.h" to
add macros to find minor and major version from PVR which
will be used in testcases.
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/include/reg.h | 4
.../powerpc/pmu/sampling_tests/misc.c | 20 +++
.../powerpc/pmu/sampling_tests/misc.h | 3 +++
3 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/tools/testing/selftests/powerpc/include/reg.h
b/tools/testing/selftests/powerpc/include/reg.h
index c422be8a42b2..2ac7a4c7749c 100644
--- a/tools/testing/selftests/powerpc/include/reg.h
+++ b/tools/testing/selftests/powerpc/include/reg.h
@@ -55,6 +55,10 @@
#define PVR_VER(pvr) (((pvr) >> 16) & 0x)
#define SPRN_PVR 0x11F
+#define PVR_CFG(pvr)(((pvr) >> 8) & 0xF) /* Configuration field */
+#define PVR_MAJ(pvr)(((pvr) >> 4) & 0xF) /* Major revision field */
+#define PVR_MIN(pvr)(((pvr) >> 0) & 0xF) /* Minor revision field */
+
#define SPRN_DSCR_PRIV 0x11/* Privilege State DSCR */
#define SPRN_DSCR 0x03/* Data Stream Control Register */
#define SPRN_PPR 896 /* Program Priority Register */
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index 5a26fc3a9706..18babc9e16aa 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -121,12 +121,10 @@ int check_extended_regs_support(void)
return -1;
}
-int check_pvr_for_sampling_tests(void)
+int platform_check_for_tests(void)
{
pvr = PVR_VER(mfspr(SPRN_PVR));
- platform_extended_mask = perf_get_platform_reg_mask();
-
/*
* Check for supported platforms
* for sampling test
@@ -138,19 +136,33 @@ int check_pvr_for_sampling_tests(void)
* Check PMU driver registered by looking for
* PPC_FEATURE2_EBB bit in AT_HWCAP2
*/
- if (!have_hwcap2(PPC_FEATURE2_EBB))
+ if (!have_hwcap2(PPC_FEATURE2_EBB) ||
!have_hwcap2(PPC_FEATURE2_ARCH_3_00))
goto out;
+ return 0;
+
+out:
+ printf("%s: Tests un-supported for this platform\n", __func__);
+ return -1;
+}
+
+int check_pvr_for_sampling_tests(void)
+{
+ SKIP_IF(platform_check_for_tests());
+
+ platform_extended_mask = perf_get_platform_reg_mask();
/* check if platform supports extended regs */
if (check_extended_regs_support())
goto out;
init_ev_encodes();
return 0;
+
out:
printf("%s: Sampling tests un-supported\n", __func__);
return -1;
}
+
/*
* Allocate mmap buffer of "mmap_pages" number of
* pages.
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 874a1596add8..4181755cf5a0 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -18,6 +18,8 @@
#define MMCR1_RSQ 0x2000ULL /* radix scope qual field */
#define BHRB_DISABLE0x20ULL /* MMCRA BHRB DISABLE bit */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
extern int ev_mask_pmcxsel, ev_shift_pmcxsel;
extern int ev_mask_marked, ev_shift_marked;
extern int ev_mask_comb, ev_shift_comb;
@@ -36,6 +38,7 @@ extern int ev_mask_mmcr3_src, ev_shift_mmcr3_src;
extern int pvr;
extern u64 platform_extended_mask;
extern int check_pvr_for_sampling_tests(void);
+extern int platform_check_for_tests(void);
/*
* Event code field extraction macro.
--
2.35.1
[PATCH V3 08/35] selftest/powerpc/pmu: Add interface test for bhrb disable field
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Testcase checks if the bhrb disable bit of MMCRA register is
programmed correctly via perf interface for ISA v3.1 platform
Also make get_mmcra_ifm return type as u64.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/Makefile | 3 +-
.../powerpc/pmu/sampling_tests/misc.h | 2 +-
.../sampling_tests/mmcra_bhrb_disable_test.c | 66 +++
3 files changed, 69 insertions(+), 2 deletions(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 53569fbb1cda..f4da49d55d57 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -5,7 +5,8 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
- mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test
+ mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test \
+ mmcra_bhrb_disable_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index c0e923f38793..874a1596add8 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -188,7 +188,7 @@ static inline int get_mmcra_sm(u64 mmcra, int pmc)
return ((mmcra >> 42) & 0x3);
}
-static inline int get_mmcra_bhrb_disable(u64 mmcra, int pmc)
+static inline u64 get_mmcra_bhrb_disable(u64 mmcra, int pmc)
{
if (pvr == POWER10)
return mmcra & BHRB_DISABLE;
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_test.c
new file mode 100644
index ..186a853c0f62
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_disable_test.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/* Instructions */
+#define EventCode 0x500fa
+
+/*
+ * A perf sampling test for mmcra
+ * field: bhrb_disable.
+ */
+static int mmcra_bhrb_disable_test(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /*
+* Check for platform support for the test.
+* This test is only aplicable on power10
+*/
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+/* Init the event for the sampling test */
+ event_init_sampling(, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
+ event.attr.branch_sample_type = PERF_SAMPLE_BRANCH_ANY;
+ event.attr.exclude_kernel = 1;
+
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ FAIL_IF(event_enable());
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(1);
+
+ FAIL_IF(event_disable());
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that bhrb_disable bit is set in MMCRA */
+ FAIL_IF(get_mmcra_bhrb_disable(get_reg_value(intr_regs, "MMCRA"), 5));
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(mmcra_bhrb_disable_test, "mmcra_bhrb_disable_test");
+}
--
2.35.1
[PATCH V3 07/35] selftest/powerpc/pmu: Add interface test for mmcra_ifm field for conditional branch type
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for conditional branch type. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1 platform.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../pmu/sampling_tests/mmcra_bhrb_cond_test.c | 69 +++
2 files changed, 70 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_cond_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 63b084f66dbf..53569fbb1cda 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -5,7 +5,7 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
- mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
+ mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
mmcra_bhrb_cond_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_cond_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_cond_test.c
new file mode 100644
index ..3e08176eb7f8
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_cond_test.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/* Instructions */
+#define EventCode 0x500fa
+
+/* ifm field for conditional branch mode */
+#define IFM_COND_BRANCH 0x3
+
+/*
+ * A perf sampling test for mmcra
+ * field: ifm for bhrb cond call.
+ */
+static int mmcra_bhrb_cond_test(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /*
+* Check for platform support for the test.
+* This test is only aplicable on power10
+*/
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+/* Init the event for the sampling test */
+ event_init_sampling(, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
+ event.attr.branch_sample_type = PERF_SAMPLE_BRANCH_COND;
+ event.attr.exclude_kernel = 1;
+
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ FAIL_IF(event_enable());
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(1);
+
+ FAIL_IF(event_disable());
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that ifm bit is set properly in MMCRA */
+ FAIL_IF(get_mmcra_ifm(get_reg_value(intr_regs, "MMCRA"), 5) !=
IFM_COND_BRANCH);
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(mmcra_bhrb_cond_test, "mmcra_bhrb_cond_test");
+}
--
2.35.1
[PATCH V3 06/35] selftest/powerpc/pmu: Add interface test for mmcra_ifm field for any branch type
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for type any branch. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../pmu/sampling_tests/mmcra_bhrb_any_test.c | 65 +++
2 files changed, 66 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_any_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 89def6e706c8..63b084f66dbf 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -5,7 +5,7 @@ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
- mmcra_bhrb_ind_call_test
+ mmcra_bhrb_ind_call_test mmcra_bhrb_any_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_any_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_any_test.c
new file mode 100644
index ..14854694af62
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_any_test.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(int loops);
+
+/* Instructions */
+#define EventCode 0x500fa
+
+/* ifm field for any branch mode */
+#define IFM_ANY_BRANCH 0x0
+
+/*
+ * A perf sampling test for mmcra
+ * field: ifm for bhrb any call.
+ */
+static int mmcra_bhrb_any_test(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+/* Init the event for the sampling test */
+ event_init_sampling(, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
+ event.attr.branch_sample_type = PERF_SAMPLE_BRANCH_ANY;
+ event.attr.exclude_kernel = 1;
+
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ FAIL_IF(event_enable());
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop(1);
+
+ FAIL_IF(event_disable());
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that ifm bit is set properly in MMCRA */
+ FAIL_IF(get_mmcra_ifm(get_reg_value(intr_regs, "MMCRA"), 5) !=
IFM_ANY_BRANCH);
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(mmcra_bhrb_any_test, "mmcra_bhrb_any_test");
+}
--
2.35.1
[PATCH V3 05/35] selftest/powerpc/pmu: Add interface test for mmcra_ifm field of indirect call type
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for indirect branch type. Testcase checks if IFM bits are
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1 platform.
Signed-off-by: Kajol Jain
---
.../selftests/powerpc/pmu/branch_loops.S | 28
.../powerpc/pmu/sampling_tests/Makefile | 5 +-
.../sampling_tests/mmcra_bhrb_ind_call_test.c | 69 +++
3 files changed, 100 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/branch_loops.S
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_ind_call_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/branch_loops.S
b/tools/testing/selftests/powerpc/pmu/branch_loops.S
new file mode 100644
index ..de758dd3cecf
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/branch_loops.S
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+
+ .text
+
+#define ITER_SHIFT 31
+
+FUNC_START(indirect_branch_loop)
+ li r3, 1
+ sldir3, r3, ITER_SHIFT
+
+1: cmpdi r3, 0
+ beqlr
+
+ addir3, r3, -1
+
+ ld r4, 2f@got(%r2)
+ mtctr r4
+ bctr
+
+ .balign 32
+2: b 1b
+
+FUNC_END(indirect_branch_loop)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index 6508e6074bac..89def6e706c8 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -4,9 +4,10 @@ CFLAGS += -m64
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
- mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test
+ mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test \
+ mmcra_bhrb_ind_call_test
top_srcdir = ../../../../../..
include ../../../lib.mk
-$(TEST_GEN_PROGS): ../../harness.c ../../utils.c ../event.c ../lib.c misc.c
misc.h ../loop.S
+$(TEST_GEN_PROGS): ../../harness.c ../../utils.c ../event.c ../lib.c misc.c
misc.h ../loop.S ../branch_loops.S
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_ind_call_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_ind_call_test.c
new file mode 100644
index ..f0706730c099
--- /dev/null
+++
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_bhrb_ind_call_test.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+extern void indirect_branch_loop(void);
+
+/* Instructions */
+#define EventCode 0x500fa
+
+/* ifm field for indirect branch mode */
+#define IFM_IND_BRANCH 0x2
+
+/*
+ * A perf sampling test for mmcra
+ * field: ifm for bhrb ind_call.
+ */
+static int mmcra_bhrb_ind_call_test(void)
+{
+ struct event event;
+ u64 *intr_regs;
+
+ /*
+* Check for platform support for the test.
+* This test is only aplicable on power10
+*/
+ SKIP_IF(check_pvr_for_sampling_tests());
+ SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+/* Init the event for the sampling test */
+ event_init_sampling(, EventCode);
+ event.attr.sample_regs_intr = platform_extended_mask;
+ event.attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
+ event.attr.branch_sample_type = PERF_SAMPLE_BRANCH_IND_CALL;
+ event.attr.exclude_kernel = 1;
+
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ FAIL_IF(event_enable());
+
+ /* workload to make the event overflow */
+ indirect_branch_loop();
+
+ FAIL_IF(event_disable());
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that ifm bit is set properly in MMCRA */
+ FAIL_IF(get_mmcra_ifm(get_reg_value(intr_regs, "MMCRA"), 5) !=
IFM_IND_BRANCH);
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(mmcra_bhrb_ind_call_test,
"mmcra_bhrb_ind_call_test");
+}
--
2.35.1
[PATCH V3 04/35] selftest/powerpc/pmu: Add support for branch sampling in get_intr_regs function
From: Kajol Jain
Add support for sample type as PERF_SAMPLE_BRANCH_STACK in sampling
tests. This change is a precursor/helper for sampling testcases, that
test branck stack feature in perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/misc.c | 21 ++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index 6e30b455cbd6..5a26fc3a9706 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -259,13 +259,32 @@ u64 *get_intr_regs(struct event *event, void *sample_buff)
u64 *intr_regs;
size_t size = 0;
- if ((type ^ PERF_SAMPLE_REGS_INTR))
+ if ((type ^ (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_BRANCH_STACK)) &&
+ (type ^ PERF_SAMPLE_REGS_INTR))
return NULL;
intr_regs = (u64 *)perf_read_first_sample(sample_buff, );
if (!intr_regs)
return NULL;
+ if (type & PERF_SAMPLE_BRANCH_STACK) {
+ /*
+* PERF_RECORD_SAMPLE and PERF_SAMPLE_BRANCH_STACK:
+* struct {
+* struct perf_event_header hdr;
+* u64 number_of_branches;
+* struct perf_branch_entry[number_of_branches];
+* u64 data[];
+* };
+* struct perf_branch_entry {
+* u64 from;
+* u64 to;
+* u64 misc;
+* };
+*/
+ intr_regs += ((*intr_regs) * 3) + 1;
+ }
+
/*
* First entry in the sample buffer used to specify
* PERF_SAMPLE_REGS_ABI_64, skip perf regs abi to access
--
2.35.1
[PATCH V3 03/35] selftest/powerpc/pmu: Add interface test for mmcra_thresh_cmp fields
From: Kajol Jain
The testcase uses event code 0x35340401e0 for load
only sampling, to verify the settings of thresh compare field
in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9
and MMCRA: 8-18 bits for power10). Testcase checks if the thresh compare
field is programmed correctly via perf interface to MMCRA
register.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../sampling_tests/mmcra_thresh_cmp_test.c| 74 +++
2 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_cmp_test.c
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index a785c6a173b9..6508e6074bac 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -4,7 +4,7 @@ CFLAGS += -m64
TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test
mmcr0_pmccext_test \
mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test
mmcr0_fc56_pmc56_test \
mmcr1_comb_test mmcr2_l2l3_test mmcr2_fcs_fch_test \
- mmcr3_src_test mmcra_thresh_marked_sample_test
+ mmcr3_src_test mmcra_thresh_marked_sample_test
mmcra_thresh_cmp_test
top_srcdir = ../../../../../..
include ../../../lib.mk
diff --git
a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_cmp_test.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_cmp_test.c
new file mode 100644
index ..904362f172c9
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_cmp_test.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Kajol Jain, IBM Corp.
+ */
+
+#include
+#include
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/*
+ * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
+ * Threshold event selection used is issue to complete for cycles
+ * Sampling criteria is Load only sampling
+ */
+#define p9_EventCode 0x13E35340401e0
+#define p10_EventCode 0x35340401e0
+
+extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64
*ll_sc_target);
+
+/* A perf sampling test to test mmcra fields */
+static int mmcra_thresh_cmp(void)
+{
+ struct event event;
+ u64 *intr_regs;
+ u64 dummy;
+
+ /* Check for platform support for the test */
+ SKIP_IF(check_pvr_for_sampling_tests());
+
+ /* Skip for comapt mode */
+ SKIP_IF(check_for_compat_mode());
+
+ /* Init the event for the sampling test */
+ if (!have_hwcap2(PPC_FEATURE2_ARCH_3_1)) {
+ event_init_sampling(, p9_EventCode);
+ } else {
+ event_init_sampling(, p10_EventCode);
+ event.attr.config1 = 1000;
+ }
+
+ event.attr.sample_regs_intr = platform_extended_mask;
+ FAIL_IF(event_open());
+ event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+ FAIL_IF(event_enable());
+
+ /* workload to make the event overflow */
+ thirty_two_instruction_loop_with_ll_sc(100, );
+
+ FAIL_IF(event_disable());
+
+ /* Check for sample count */
+ FAIL_IF(!collect_samples(event.mmap_buffer));
+
+ intr_regs = get_intr_regs(, event.mmap_buffer);
+
+ /* Check for intr_regs */
+ FAIL_IF(!intr_regs);
+
+ /* Verify that thresh cmp match with the corresponding event code
fields */
+ FAIL_IF(get_thresh_cmp_val(event) !=
+ get_mmcra_thd_cmp(get_reg_value(intr_regs, "MMCRA"),
4));
+
+ event_close();
+ return 0;
+}
+
+int main(void)
+{
+ FAIL_IF(test_harness(mmcra_thresh_cmp, "mmcra_thresh_cmp"));
+}
--
2.35.1
[PATCH V3 02/35] testing/selftests/powerpc: Add support to fetch "platform" and "base platform" from auxv to detect platform.
The /proc/self/auxv contains information about "platform" on any
system. Also "base platform" which is an indication about platform
string corresponding to the real PVR. When systems are booted in
compat mode, say, power10 booted in power9 mode, "platform" will
point to power9 whereas base platform will point to power10. Incase,
if the distro doesn't support platform indicated by real PVR,
base platform will have a default value.
The mismatch of platform/base platform is an indication of system
booted in compat mode. In such cases, distro will have a Generic
Compat registered which supports basic features for performance
monitoring.
Some of the selftest needs to be handled differently ( ex: generic
events, alternative events, bhrb filter map) in Generic Compat PMU.
Hence selftest framework needs utility functions to identify such
cases. One way is make sure of auxv information. Below condition can
be used to detect if Generic Compat PMU is registered. ie:
<<>>
if ((AT_PLATFORM != AT_BASE_PLATFORM) && (AT_BASE_PLATFORM != PVR))
<<>>
this indicates Generic Compat PMU.
Add utility function in "include/utils.h" to return:
AT_PLATFORM and AT_BASE_PLATFORM from auxv. Also update misc.c in
"sampling_tests" folder to add function to use above check to
determine presence of generic compat pmu.
In other architecture ( like x86 ), pmu_name is exposed via
"/sys/bus/event_source/devices/cpu/caps". The same could be used
in powerpc in future. Since currently we don't have the "caps"
support in powerpc, patch uses auxv information to detect platform
type and compat mode. But as placeholder utility function is added
considering possiblity of getting "caps" information via sysfs.
If that doesn't exist, fallback to using auxv information.
Signed-off-by: Athira Rajeev
---
.../testing/selftests/powerpc/include/utils.h | 10
.../powerpc/pmu/sampling_tests/misc.c | 50 +++
.../powerpc/pmu/sampling_tests/misc.h | 3 ++
3 files changed, 63 insertions(+)
diff --git a/tools/testing/selftests/powerpc/include/utils.h
b/tools/testing/selftests/powerpc/include/utils.h
index b9fa9cd709df..e222a5858450 100644
--- a/tools/testing/selftests/powerpc/include/utils.h
+++ b/tools/testing/selftests/powerpc/include/utils.h
@@ -74,6 +74,16 @@ static inline bool have_hwcap2(unsigned long ftr2)
}
#endif
+static inline char *auxv_base_platform(void)
+{
+ return ((char *)get_auxv_entry(AT_BASE_PLATFORM));
+}
+
+static inline char *auxv_platform(void)
+{
+ return ((char *)get_auxv_entry(AT_PLATFORM));
+}
+
bool is_ppc64le(void);
int using_hash_mmu(bool *using_hash);
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index b984d1e162ac..6e30b455cbd6 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -454,3 +454,53 @@ int get_thresh_cmp_val(struct event event)
result = (exp << 8) | value;
return result;
}
+
+/*
+ * Utility function to check for generic compat PMU
+ * by comparing base_platform value from auxv and real
+ * PVR value.
+ */
+static bool auxv_generic_compat_pmu(void)
+{
+ int base_pvr = 0;
+
+ if (!strcmp(auxv_base_platform(), "power9"))
+ base_pvr = POWER9;
+ else if (!strcmp(auxv_base_platform(), "power10"))
+ base_pvr = POWER10;
+
+ return (!base_pvr);
+}
+
+/*
+ * Check for generic compat PMU.
+ * First check for presence of pmu_name from
+ * "/sys/bus/event_source/devices/cpu/caps".
+ * If doesn't exist, fallback to using value
+ * auxv.
+ */
+bool check_for_generic_compat_pmu(void)
+{
+ char pmu_name[256];
+
+ memset(pmu_name, 0, sizeof(pmu_name));
+ if (read_sysfs_file("bus/event_source/devices/cpu/caps/pmu_name",
+ pmu_name, sizeof(pmu_name)) < 0)
+ return auxv_generic_compat_pmu();
+
+ if (!strcmp(pmu_name, "ISAv3"))
+ return true;
+ else
+ return false;
+}
+
+/*
+ * Check if system is booted in compat mode.
+ */
+bool check_for_compat_mode(void)
+{
+ char *platform = auxv_platform();
+ char *base_platform = auxv_base_platform();
+
+ return strcmp(platform, base_platform);
+}
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 078120883fde..c0e923f38793 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -5,6 +5,7 @@
* Copyright 2022, Kajol Jain, IBM Corp.
*/
+#include
#include "../event.h"
#define POWER10 0x80
@@ -53,6 +54,8 @@ int collect_samples(void *sample_buff);
u64 *get_intr_regs(struct event *event, void *sample_buff);
u64 get_reg_value(u64 *intr_regs, char *register_name);
int get_thresh_cmp_val(struct event event);
+bool
[PATCH V3 01/35] selftest/powerpc/pmu: Add mask/shift bits for extracting threshold compare field
From: Kajol Jain
In power10, threshold compare field is not part of the raw
event code and provided via event attribute config1.
Hence add the mask and shift bits based on event attribute
config1, to extract the threshold compare value for power10
Also add a new function called get_thresh_cmp_val to compute
and return the threshold compare field for a given platform,
since incase of power10, threshold compare value provided
is decimal.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/misc.c | 44 +++
.../powerpc/pmu/sampling_tests/misc.h | 1 +
2 files changed, 45 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index c01a31d5f4ee..b984d1e162ac 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -60,6 +60,8 @@ static void init_ev_encodes(void)
switch (pvr) {
case POWER10:
+ ev_mask_thd_cmp = 0x3;
+ ev_shift_thd_cmp = 0;
ev_mask_rsq = 1;
ev_shift_rsq = 9;
ev_mask_comb = 3;
@@ -410,3 +412,45 @@ u64 get_reg_value(u64 *intr_regs, char *register_name)
return *(intr_regs + register_bit_position);
}
+
+int get_thresh_cmp_val(struct event event)
+{
+ int exp = 0;
+ u64 result = 0;
+ u64 value;
+
+ if (!have_hwcap2(PPC_FEATURE2_ARCH_3_1))
+ return EV_CODE_EXTRACT(event.attr.config, thd_cmp);
+
+ value = EV_CODE_EXTRACT(event.attr.config1, thd_cmp);
+
+ if (!value)
+ return value;
+
+ /*
+* Incase of P10, thresh_cmp value is not part of raw event code
+* and provided via attr.config1 parameter. To program threshold in
MMCRA,
+* take a 18 bit number N and shift right 2 places and increment
+* the exponent E by 1 until the upper 10 bits of N are zero.
+* Write E to the threshold exponent and write the lower 8 bits of N
+* to the threshold mantissa.
+* The max threshold that can be written is 261120.
+*/
+ if (value > 261120)
+ value = 261120;
+ while ((64 - __builtin_clzl(value)) > 8) {
+ exp++;
+ value >>= 2;
+ }
+
+ /*
+* Note that it is invalid to write a mantissa with the
+* upper 2 bits of mantissa being zero, unless the
+* exponent is also zero.
+*/
+ if (!(value & 0xC0) && exp)
+ result = -1;
+ else
+ result = (exp << 8) | value;
+ return result;
+}
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 7675f3177725..078120883fde 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -52,6 +52,7 @@ void *__event_read_samples(void *sample_buff, size_t *size,
u64 *sample_count);
int collect_samples(void *sample_buff);
u64 *get_intr_regs(struct event *event, void *sample_buff);
u64 get_reg_value(u64 *intr_regs, char *register_name);
+int get_thresh_cmp_val(struct event event);
static inline int get_mmcr0_fc56(u64 mmcr0, int pmc)
{
--
2.35.1
[PATCH V3 00/35] Add group constraints and event code test as part of selftest
Patch series extends the perf interface selftests to cover scenarios for event code checking, group constraints, and also thresholding/branch related interface tests in sampling area. In this series, patches 1 to 14 adds additional tests under "powerpc/sampling_tests". These adds support for handling sample type PERF_SAMPLE_BRANCH_STACK along with interrupt regs. It adds utility functions and test for thresh_cmp and branch filters programmed in control register. Some of the tests needs to be skipped for "Generic Compat PMU" environment. Hence utility functions are added in "include/utils.c" and "sampling_tests/misc.h" to detect platform based on "auxv" entries. Currently in other architectures (like x86), the pmu_name is exposed via sysfs caps folder ie: "sys/bus/event_source/devices//caps". But in powerpc, "caps" is not supported. So, though the approach for detecting compat mode currently uses auxv, patchset adds an utility function considering a possibility of getting "caps" added for powerpc. Link to the patch to add support for caps under sysfs in powerpc: http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=301270 Patches 15 to 35 covers test related to group constraints and event codes. These new set of changes are added under new folder: "selftests/powerpc/pmu/event_code_tests" Patch 15 covers changes required for new folder with Makefile changes. The other patches add tests for perf interface to check the event group constraints, valid/invalid event codes, blacklisted events etc. Also add required utility functions under header file "misc.h" in sampling_tests folder. Patch 13 of the patchset add selftest for mmcr1 pmcxsel/unit/cache fields, which was initially dropeed from sampling test patchset (patch number: 16) Link to the patch: http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20220127072012.662451-17-kj...@linux.ibm.com/ Changelog: v2 -> v3: Changed name for generic compat PMU to ISAv3 in Patch2. This is based on recent patch sent by Joel Stanley to change name for generic_compat_pmu to ISAv3. http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=304131 v1 -> v2: Patch 12: Fixed bhrb_filter_map testcase to address build failure in distro like Ubuntu 16.04. This testcase uses perf branch sample types from include/uapi/linux/perf_event.h and three of the sample types are not defined in Ubuntu 16.04. Hence changed the logic to loop over values from PERF_SAMPLE_BRANCH_USER_SHIFT to PERF_SAMPLE_BRANCH_MAX_SHIFT as suggested by Michael Ellerman. Patch 2: The sampling_tests/misc.c used pmu_name for generic compat pmu as generic_compat_pmu. But latest version of patch to expose caps in powerpc will use power_pmu->name. So change the pmu name in misc code as GENERIC_COMPAT ( which is what pmu->name uses in driver code). Link to linuxppc-ci: https://github.com/athira-rajeev/linux-ci/actions?query=branch%3Aselftest_v5_set2 Athira Rajeev (20): testing/selftests/powerpc: Add support to fetch "platform" and "base platform" from auxv to detect platform. selftest/powerpc/pmu: Refactor the platform check and add macros to find array size/PVR selftest/powerpc/pmu: Add selftest to check branch stack enablement will not crash on any platforms selftest/powerpc/pmu: Add selftest to check PERF_SAMPLE_REGS_INTR option will not crash on any platforms selftest/powerpc/pmu: Add selftest for checking valid and invalid bhrb filter maps selftest/powerpc/pmu: Add selftest for mmcr1 pmcxsel/unit/cache fields selftest/powerpc/pmu: Add support for perf event code tests selftest/powerpc/pmu: Add selftest for group constraint check for PMC5 and PMC6 selftest/powerpc/pmu: Add selftest to check PMC5/6 is excluded from some constraint checks selftest/powerpc/pmu: Add selftest to check constraint for number of counters in use. selftest/powerpc/pmu: Add selftest for group constraint check when using same PMC selftest/powerpc/pmu: Add selftest for group constraint check for radix_scope_qual field selftest/powerpc/pmu: Add selftest for group constraint for MMCRA Sampling Mode field selftest/powerpc/pmu: Add selftest for group constraint check MMCRA sample bits selftest/powerpc/pmu: Add selftest for checking invalid bits in event code selftest/powerpc/pmu: Add selftest for reserved bit check for MMCRA thresh_ctl field selftest/powerpc/pmu: Add selftest for blacklist events check in power9 selftest/powerpc/pmu: Add selftest for event alternatives for power9 selftest/powerpc/pmu: Add selftest for event alternatives for power10 selftest/powerpc/pmu: Add selftest for PERF_TYPE_HARDWARE events valid check Kajol Jain (15): selftest/powerpc/pmu: Add mask/shift bits for extracting threshold compare field selftest/powerpc/pmu: Add interface test for mmcra_thresh_cmp fields selftest/powerpc/pmu: Add support for branch sampling in get_intr_regs function
[PATCH] powerpc/papr_scm: Fix nvdimm event mappings
Commit 4c08d4bbc089 ("powerpc/papr_scm: Add perf interface support")
adds performance monitoring support for papr-scm nvdimm devices via
perf interface. It also adds one array in papr_scm_priv
structure called "nvdimm_events_map", to dynamically save the stat_id
for events specified in nvdimm driver code "nd_perf.c".
Right now the mapping is done based on the result of
H_SCM_PERFORMANCE_STATS hcall, when all the stats are
requested. Currently there is an assumption, that a
certain stat will always be found at a specific offset
in the stat buffer. The assumption may not be true or
documented as part of PAPR documentation. Fixing it,
by adding a static mapping for nvdimm events to
corresponding stat-id, and removing the map from
papr_scm_priv structure.
Fixes: 4c08d4bbc089 ("powerpc/papr_scm: Add perf interface support")
Reported-by: Aneesh Kumar K.V
Signed-off-by: Kajol Jain
---
arch/powerpc/platforms/pseries/papr_scm.c | 59 ++-
1 file changed, 25 insertions(+), 34 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.c
index 181b855b3050..5434c654a797 100644
--- a/arch/powerpc/platforms/pseries/papr_scm.c
+++ b/arch/powerpc/platforms/pseries/papr_scm.c
@@ -124,9 +124,6 @@ struct papr_scm_priv {
/* The bits which needs to be overridden */
u64 health_bitmap_inject_mask;
-
- /* array to have event_code and stat_id mappings */
- u8 *nvdimm_events_map;
};
static int papr_scm_pmem_flush(struct nd_region *nd_region,
@@ -350,6 +347,26 @@ static ssize_t drc_pmem_query_stats(struct papr_scm_priv
*p,
#ifdef CONFIG_PERF_EVENTS
#define to_nvdimm_pmu(_pmu)container_of(_pmu, struct nvdimm_pmu, pmu)
+static const char * const nvdimm_events_map[] = {
+ "N/A",
+ "CtlResCt",
+ "CtlResTm",
+ "PonSecs ",
+ "MemLife ",
+ "CritRscU",
+ "HostLCnt",
+ "HostSCnt",
+ "HostSDur",
+ "HostLDur",
+ "MedRCnt ",
+ "MedWCnt ",
+ "MedRDur ",
+ "MedWDur ",
+ "CchRHCnt",
+ "CchWHCnt",
+ "FastWCnt",
+};
+
static int papr_scm_pmu_get_value(struct perf_event *event, struct device
*dev, u64 *count)
{
struct papr_scm_perf_stat *stat;
@@ -361,7 +378,7 @@ static int papr_scm_pmu_get_value(struct perf_event *event,
struct device *dev,
size = sizeof(struct papr_scm_perf_stats) +
sizeof(struct papr_scm_perf_stat);
- if (!p || !p->nvdimm_events_map)
+ if (!p)
return -EINVAL;
stats = kzalloc(size, GFP_KERNEL);
@@ -370,7 +387,7 @@ static int papr_scm_pmu_get_value(struct perf_event *event,
struct device *dev,
stat = >scm_statistic[0];
memcpy(>stat_id,
- >nvdimm_events_map[event->attr.config *
sizeof(stat->stat_id)],
+ nvdimm_events_map[event->attr.config],
sizeof(stat->stat_id));
stat->stat_val = 0;
@@ -460,10 +477,9 @@ static void papr_scm_pmu_del(struct perf_event *event, int
flags)
static int papr_scm_pmu_check_events(struct papr_scm_priv *p, struct
nvdimm_pmu *nd_pmu)
{
- struct papr_scm_perf_stat *stat;
struct papr_scm_perf_stats *stats;
u32 available_events;
- int index, rc = 0;
+ int rc = 0;
available_events = (p->stat_buffer_len - sizeof(struct
papr_scm_perf_stats))
/ sizeof(struct papr_scm_perf_stat);
@@ -473,34 +489,12 @@ static int papr_scm_pmu_check_events(struct papr_scm_priv
*p, struct nvdimm_pmu
/* Allocate the buffer for phyp where stats are written */
stats = kzalloc(p->stat_buffer_len, GFP_KERNEL);
if (!stats) {
- rc = -ENOMEM;
- return rc;
+ return -ENOMEM;
}
/* Called to get list of events supported */
rc = drc_pmem_query_stats(p, stats, 0);
- if (rc)
- goto out;
- /*
-* Allocate memory and populate nvdimm_event_map.
-* Allocate an extra element for NULL entry
-*/
- p->nvdimm_events_map = kcalloc(available_events + 1,
- sizeof(stat->stat_id),
- GFP_KERNEL);
- if (!p->nvdimm_events_map) {
- rc = -ENOMEM;
- goto out;
- }
-
- /* Copy all stat_ids to event map */
- for (index = 0, stat = stats->scm_statistic;
-index < available_events; index++, ++stat) {
- memcpy(>nvdimm_events_map[index * sizeof(stat->stat_id)],
- >stat_id, sizeof(stat->stat_id));
- }
-out:
kfree(stats);
return rc;
}
@@ -536,7 +530,7 @@ static void papr_scm_pmu_register(struct papr_scm_priv *p)
rc = register_nvdimm_pmu(nd_pmu, p->pdev);
if (rc)
- goto pmu_register_err;
+ goto pmu_check_events_err;
/*
* Set archdata.priv
[PATCH] powerpc/32: Fix FPR index validation and fpscr access
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr into high part and low part.
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 09c49632bfe5..eabc05b439f1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,14 +17,18 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
*data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
else
+ *data = ((u32 *)>thread.fp_state.fpscr)[fpidx &
1];
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
- } else
- *data = child->thread.fp_state.fpscr;
+ else
+ *data = child->thread.fp_state.fpscr;
+ }
#else
*data = 0;
#endif
@@ -43,14 +47,18 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
else
+ ((u32 *)>thread.fp_state.fpscr)[fpidx & 1] =
data;
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
- } else
- child->thread.fp_state.fpscr = data;
+ else
+ child->thread.fp_state.fpscr = data;
+ }
#endif
return 0;
--
2.36.1
[PATCH] powerpc/32: Fix FPR index validation and fpscr access
From: Ariel Miculas
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr into high part and low part.
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 09c49632bfe5..eabc05b439f1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,14 +17,18 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
*data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
else
+ *data = ((u32 *)>thread.fp_state.fpscr)[fpidx &
1];
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
- } else
- *data = child->thread.fp_state.fpscr;
+ else
+ *data = child->thread.fp_state.fpscr;
+ }
#else
*data = 0;
#endif
@@ -43,14 +47,18 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
else
+ ((u32 *)>thread.fp_state.fpscr)[fpidx & 1] =
data;
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
- } else
- child->thread.fp_state.fpscr = data;
+ else
+ child->thread.fp_state.fpscr = data;
+ }
#endif
return 0;
--
2.36.1
[PATCH] powerpc/32: Fix FPR index validation and fpscr access
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr into high part and low part.
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 09c49632bfe5..eabc05b439f1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,14 +17,18 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
*data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
else
+ *data = ((u32 *)>thread.fp_state.fpscr)[fpidx &
1];
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
- } else
- *data = child->thread.fp_state.fpscr;
+ else
+ *data = child->thread.fp_state.fpscr;
+ }
#else
*data = 0;
#endif
@@ -43,14 +47,18 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
else
+ ((u32 *)>thread.fp_state.fpscr)[fpidx & 1] =
data;
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
- } else
- child->thread.fp_state.fpscr = data;
+ else
+ child->thread.fp_state.fpscr = data;
+ }
#endif
return 0;
--
2.36.1
[PATCH] powerpc/32: Fix FPR index validation and fpscr access
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr into high part and low part.
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 09c49632bfe5..eabc05b439f1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,14 +17,18 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
*data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
else
+ *data = ((u32 *)>thread.fp_state.fpscr)[fpidx &
1];
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
- } else
- *data = child->thread.fp_state.fpscr;
+ else
+ *data = child->thread.fp_state.fpscr;
+ }
#else
*data = 0;
#endif
@@ -43,14 +47,18 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
else
+ ((u32 *)>thread.fp_state.fpscr)[fpidx & 1] =
data;
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
- } else
- child->thread.fp_state.fpscr = data;
+ else
+ child->thread.fp_state.fpscr = data;
+ }
#endif
return 0;
--
2.36.1
[PATCH v4 15/18] PCI: dwc: Add dw_ prefix to the pcie_port structure name
All of the DW PCIe core driver entities have names with the dw_ prefix in
order to easily distinguish local and common PCIe name spaces. All except
the pcie_port structure which contains the DW PCIe Root Port descriptor.
For historical reason the structure has retained the original name since
commit 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos") when
the DW PCIe IP-core support was added to the kernel. Let's finally fix
that by adding the dw_ prefix to the structure name and by adding the _rp
suffix to be similar to the EP counterpart. Thus the name will be coherent
with the common driver naming policy. It shall make the driver code more
readable eliminating visual confusion between the local and generic PCI
name spaces.
Signed-off-by: Serge Semin
---
Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
drivers/pci/controller/dwc/pci-dra7xx.c | 12 +++
drivers/pci/controller/dwc/pci-exynos.c | 6 ++--
drivers/pci/controller/dwc/pci-imx6.c | 6 ++--
drivers/pci/controller/dwc/pci-keystone.c | 20 +--
drivers/pci/controller/dwc/pci-layerscape.c | 2 +-
drivers/pci/controller/dwc/pci-meson.c| 2 +-
drivers/pci/controller/dwc/pcie-al.c | 6 ++--
drivers/pci/controller/dwc/pcie-armada8k.c| 4 +--
drivers/pci/controller/dwc/pcie-artpec6.c | 4 +--
.../pci/controller/dwc/pcie-designware-host.c | 36 +--
.../pci/controller/dwc/pcie-designware-plat.c | 2 +-
drivers/pci/controller/dwc/pcie-designware.h | 30
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 +--
drivers/pci/controller/dwc/pcie-fu740.c | 2 +-
drivers/pci/controller/dwc/pcie-histb.c | 10 +++---
drivers/pci/controller/dwc/pcie-intel-gw.c| 6 ++--
drivers/pci/controller/dwc/pcie-keembay.c | 4 +--
drivers/pci/controller/dwc/pcie-kirin.c | 2 +-
drivers/pci/controller/dwc/pcie-qcom.c| 4 +--
drivers/pci/controller/dwc/pcie-spear13xx.c | 6 ++--
drivers/pci/controller/dwc/pcie-tegra194.c| 22 ++--
drivers/pci/controller/dwc/pcie-uniphier.c| 10 +++---
drivers/pci/controller/dwc/pcie-visconti.c| 6 ++--
23 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c
b/drivers/pci/controller/dwc/pci-dra7xx.c
index dfcdeb432dc8..a174b680b2a7 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -178,7 +178,7 @@ static void dra7xx_pcie_enable_interrupts(struct
dra7xx_pcie *dra7xx)
dra7xx_pcie_enable_msi_interrupts(dra7xx);
}
-static int dra7xx_pcie_host_init(struct pcie_port *pp)
+static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
@@ -202,7 +202,7 @@ static const struct irq_domain_ops intx_domain_ops = {
.xlate = pci_irqd_intx_xlate,
};
-static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
+static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned long val;
@@ -224,7 +224,7 @@ static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int
index)
return 1;
}
-static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
+static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
int ret, i, count, num_ctrls;
@@ -255,8 +255,8 @@ static void dra7xx_pcie_msi_irq_handler(struct irq_desc
*desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct dra7xx_pcie *dra7xx;
+ struct dw_pcie_rp *pp;
struct dw_pcie *pci;
- struct pcie_port *pp;
unsigned long reg;
u32 bit;
@@ -344,7 +344,7 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void
*arg)
return IRQ_HANDLED;
}
-static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
+static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
@@ -475,7 +475,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
{
int ret;
struct dw_pcie *pci = dra7xx->pci;
- struct pcie_port *pp = >pp;
+ struct dw_pcie_rp *pp = >pp;
struct device *dev = pci->dev;
pp->irq = platform_get_irq(pdev, 1);
diff --git a/drivers/pci/controller/dwc/pci-exynos.c
b/drivers/pci/controller/dwc/pci-exynos.c
index 467c8d1cd7e4..2044d191fba6 100644
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -249,7 +249,7 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
return (val & PCIE_ELBI_XMLH_LINKUP);
}
-static int exynos_pcie_host_init(struct pcie_port *pp)
+static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci =
[PATCH] powerpc/32: Fix FPR index validation and fpscr access
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr into high part and low part.
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 09c49632bfe5..eabc05b439f1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,14 +17,18 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
*data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
else
+ *data = ((u32 *)>thread.fp_state.fpscr)[fpidx &
1];
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
- } else
- *data = child->thread.fp_state.fpscr;
+ else
+ *data = child->thread.fp_state.fpscr;
+ }
#else
*data = 0;
#endif
@@ -43,14 +47,18 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
else
+ ((u32 *)>thread.fp_state.fpscr)[fpidx & 1] =
data;
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
- } else
- child->thread.fp_state.fpscr = data;
+ else
+ child->thread.fp_state.fpscr = data;
+ }
#endif
return 0;
--
2.36.1
[PATCH] powerpc/32: Fix FPR index validation and fpscr access
On PPC32, there are two indexes used for each FPR.
The last two indexes into the imaginary address space "USER area" are
used to access fpscr instead of the FPR registers. Fix the validation
condition so that the access of the FPR array doesn't overflow into
fpscr. Also split the access of fpscr into high part and low part.
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 09c49632bfe5..eabc05b439f1 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -17,14 +17,18 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
*data = ((u32 *)child->thread.fp_state.fpr)[fpidx];
else
+ *data = ((u32 *)>thread.fp_state.fpscr)[fpidx &
1];
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx),
sizeof(long));
- } else
- *data = child->thread.fp_state.fpscr;
+ else
+ *data = child->thread.fp_state.fpscr;
+ }
#else
*data = 0;
#endif
@@ -43,14 +47,18 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
- if (fpidx < (PT_FPSCR - PT_FPR0)) {
- if (IS_ENABLED(CONFIG_PPC32))
+ if (IS_ENABLED(CONFIG_PPC32)) {
+ if ((fpidx >> 1) < (PT_FPSCR - PT_FPR0) >> 1)
// On 32-bit the index we are passed refers to 32-bit
words
((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
else
+ ((u32 *)>thread.fp_state.fpscr)[fpidx & 1] =
data;
+ } else {
+ if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), ,
sizeof(long));
- } else
- child->thread.fp_state.fpscr = data;
+ else
+ child->thread.fp_state.fpscr = data;
+ }
#endif
return 0;
--
2.36.1
Re: [PATCH 04/36] cpuidle,intel_idle: Fix CPUIDLE_FLAG_IRQ_ENABLE
, Arnd Bergmann , ulli.kr...@googlemail.com, vgu...@kernel.org,
linux-...@vger.kernel.org, j...@joshtriplett.org, rost...@goodmis.org,
r...@vger.kernel.org, b...@alien8.de, bc...@quicinc.com,
tsbog...@alpha.franken.de, linux-par...@vger.kernel.org, sudeep.ho...@arm.com,
shawn...@kernel.org, da...@davemloft.net, dal...@libc.org, t...@atomide.com,
amakha...@vmware.com, bjorn.anders...@linaro.org, h...@zytor.com,
sparcli...@vger.kernel.org, linux-hexa...@vger.kernel.org,
linux-ri...@lists.infradead.org, anton.iva...@cambridgegreys.com,
jo...@southpole.se, yury.no...@gmail.com, rich...@nod.at, x...@kernel.org,
li...@armlinux.org.uk, mi...@redhat.com, a...@eecs.berkeley.edu,
paul...@kernel.org, h...@linux.ibm.com, stefan.kristians...@saunalahti.fi,
openr...@lists.librecores.org, paul.walms...@sifive.com,
linux-te...@vger.kernel.org, namhy...@kernel.org,
andriy.shevche...@linux.intel.com, jpoim...@kernel.org, jgr...@suse.com,
mon...@monstr.eu, linux-m...@vger.kernel.org, palmer@dab
belt.com, a...@brainfault.org, i...@jurassic.park.msu.ru,
johan...@sipsolutions.net, linuxppc-dev@lists.ozlabs.org
Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org
Sender: "Linuxppc-dev"
Hi Peter,
On Wed, 08 Jun 2022 16:27:27 +0200, Peter Zijlstra
wrote:
> Commit c227233ad64c ("intel_idle: enable interrupts before C1 on
> Xeons") wrecked intel_idle in two ways:
>
> - must not have tracing in idle functions
> - must return with IRQs disabled
>
> Additionally, it added a branch for no good reason.
>
> Fixes: c227233ad64c ("intel_idle: enable interrupts before C1 on Xeons")
> Signed-off-by: Peter Zijlstra (Intel)
> ---
> drivers/idle/intel_idle.c | 48
> +++--- 1 file changed, 37
> insertions(+), 11 deletions(-)
>
> --- a/drivers/idle/intel_idle.c
> +++ b/drivers/idle/intel_idle.c
> @@ -129,21 +137,37 @@ static unsigned int mwait_substates __in
> *
> * Must be called under local_irq_disable().
> */
nit: this comment is no long true, right?
> +
> -static __cpuidle int intel_idle(struct cpuidle_device *dev,
> - struct cpuidle_driver *drv, int index)
> +static __always_inline int __intel_idle(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv, int
> index) {
> struct cpuidle_state *state = >states[index];
> unsigned long eax = flg2MWAIT(state->flags);
> unsigned long ecx = 1; /* break on interrupt flag */
>
> - if (state->flags & CPUIDLE_FLAG_IRQ_ENABLE)
> - local_irq_enable();
> -
> mwait_idle_with_hints(eax, ecx);
>
> return index;
> }
>
> +static __cpuidle int intel_idle(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv, int index)
> +{
> + return __intel_idle(dev, drv, index);
> +}
> +
> +static __cpuidle int intel_idle_irq(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv, int
> index) +{
> + int ret;
> +
> + raw_local_irq_enable();
> + ret = __intel_idle(dev, drv, index);
> + raw_local_irq_disable();
> +
> + return ret;
> +}
> +
> /**
> * intel_idle_s2idle - Ask the processor to enter the given idle state.
> * @dev: cpuidle device of the target CPU.
> @@ -1801,6 +1824,9 @@ static void __init intel_idle_init_cstat
> /* Structure copy. */
> drv->states[drv->state_count] =
> cpuidle_state_table[cstate];
> + if (cpuidle_state_table[cstate].flags &
> CPUIDLE_FLAG_IRQ_ENABLE)
> + drv->states[drv->state_count].enter =
> intel_idle_irq; +
> if ((disabled_states_mask & BIT(drv->state_count)) ||
> ((icpu->use_acpi || force_use_acpi) &&
>intel_idle_off_by_default(mwait_hint) &&
>
>
Thanks,
Jacob
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
k...@kernel.org" , "ebied...@xmission.com" , "aneesh.ku...@linux.ibm.com" , "bris...@redhat.com" , "wangkefeng.w...@huawei.com" , "ker...@esmil.dk" , "jniet...@gmail.com" , "paul.walms...@sifive.com" , "a...@kernel.org" , "w...@kernel.org" , "masahi...@kernel.org" , "Sakkinen, Jarkko" , "samitolva...@google.com" , "naveen.n@linux.ibm.com" , "el...@google.com" , "keesc...@chromium.org" , "rost...@goodmis.org" , "nat...@kernel.org" , "rmk+ker...@armlinux.org.uk" , "broo...@kernel.org" , "b...@alien8.de" , "egore...@linux.ibm.com" , "tsbog...@alpha.franken.de" , "linux-par...@vger.kernel.org" , "nathan...@profian.com" , "dmitry.torok...@gmail.com" , "da...@davemloft.net" , "kirill.shute...@linux.intel.com" , "husc...@linux.ibm.com" , "pet...@infradead.org" , "h...@zytor.com" , "sparcli...@vger.kernel.org" , "yangtie...@loongson.cn" , "mbe...@suse.cz" , "chenzhong...@huawei.com" , "a...@kernel.org" , "x...@kernel.org" , "li...@armlinux.org.uk" , "linux-ri...@lists.infradead.org" , "mi...@redhat.com" , "atom...@redhat.com" , "a...@eecs.berkeley.edu" , "h...@linux.ibm.com" , "liaocha n...@huawei.com" , "ati...@atishpatra.org" , "jpoim...@kernel.org" , "tmri...@linux.ibm.com" , "linux-m...@vger.kernel.org" , "changbin...@intel.com" , "pal...@dabbelt.com" , "linuxppc-dev@lists.ozlabs.org" , "linux-modu...@vger.kernel.org" Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 9, 2022 at 11:41 AM Edgecombe, Rick P wrote: > > On Thu, 2022-06-09 at 06:24 -0700, Luis Chamberlain wrote: [...] > > Like say for a next step we moved prog pack out of bpf into core code, > gave it it's own copy of module_alloc(), and then made kprobes use it. > Then we would have something with improved W^X guard rails, and kprobes > would not depend on modules anymore. I think maybe it's a step in the > right direction, even if it's not perfect. I was also thinking about where to put the prog pack allocator eventually. Shall it be part of mm code or module code? Btw, prog pack has more challenges with W^X requirement: 1. The arch need to have text poke mechanism; 2. Some users of prog pack need to learn to use the ROXbuffer with text poke, for example, how to calculate relative address differently. Thanks, Song
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
con , Masahiro Yamada , Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , "Russell King \(Oracle\)" , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , Parisc List , Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparclinux , Tiezhu Yang , Miroslav Benes < mbe...@suse.cz>, Chen Zhongjin , Ard Biesheuvel , the arch/x86 maintainers , Russell King , linux-riscv , Ingo Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , "open list:BROADCOM NVRAM DRIVER" , Changbin Du , Palmer Dabbelt , linuxppc-dev , "linux-modu...@vger.kernel.org" Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 9, 2022 at 1:34 AM Christophe Leroy wrote: > > > > Le 08/06/2022 à 18:12, Song Liu a écrit : > > On Wed, Jun 8, 2022 at 7:21 AM Masami Hiramatsu wrote: > >> > >> Hi Jarkko, > >> > >> On Wed, 8 Jun 2022 08:25:38 +0300 > >> Jarkko Sakkinen wrote: > >> > >>> On Wed, Jun 08, 2022 at 10:35:42AM +0800, Guo Ren wrote: > . > > On Wed, Jun 8, 2022 at 8:02 AM Jarkko Sakkinen > wrote: > > > > Tracing with kprobes while running a monolithic kernel is currently > > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. This > > dependency is a result of kprobes code using the module allocator for > > the > > trampoline code. > > > > Detaching kprobes from modules helps to squeeze down the user space, > > e.g. when developing new core kernel features, while still having all > > the nice tracing capabilities. > > > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > > module_alloc.c, and compile as part of vmlinux when either > > CONFIG_MODULES > > or CONFIG_KPROBES is enabled. In addition, flag kernel module specific > > code with CONFIG_MODULES. > > > > As the result, kprobes can be used with a monolithic kernel. > It's strange when MODULES is n, but vmlinux still obtains module_alloc. > > Maybe we need a kprobe_alloc, right? > >>> > >>> Perhaps not the best name but at least it documents the fact that > >>> they use the same allocator. > >>> > >>> Few years ago I carved up something "half-way there" for kprobes, > >>> and I used the name text_alloc() [*]. > >>> > >>> [*] > >>> https://lore.kernel.org/all/20200724050553.1724168-1-jarkko.sakki...@linux.intel.com/ > >> > >> Yeah, I remember that. Thank you for updating your patch! > >> I think the idea (split module_alloc() from CONFIG_MODULE) is good to me. > >> If module support maintainers think this name is not good, you may be > >> able to rename it as text_alloc() and make the module_alloc() as a > >> wrapper of it. > > > > IIUC, most users of module_alloc() use it to allocate memory for text, > > except > > that module code uses it for both text and data. Therefore, I guess calling > > it > > text_alloc() is not 100% accurate until we change the module code (to use > > a different API to allocate memory for data). > > When CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC, module code uses > module_alloc() for text and vmalloc() for data, see function > move_module() in kernel/module/main.c Thanks for the pointer! I will play with it. Song
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
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Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
, Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , linux-par...@vger.kernel.org, Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparcli...@vger.kernel.org, Tiezhu Yang , Miroslav Benes , Chen Zhongjin , Ard Biesheuvel , x...@kernel.org, linux-ri...@lists.infradead.org, Ing o Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , linux-m...@vger.kernel.org, Changbin Du , Palmer Dabbelt , linuxppc-dev@lists.ozlabs.org, linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 09, 2022 at 08:47:38AM +0100, Russell King (Oracle) wrote: > On Wed, Jun 08, 2022 at 02:59:27AM +0300, Jarkko Sakkinen wrote: > > diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile > > index 553866751e1a..d2bb954cd54f 100644 > > --- a/arch/arm/kernel/Makefile > > +++ b/arch/arm/kernel/Makefile > > @@ -44,6 +44,11 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o > > obj-$(CONFIG_ISA_DMA_API) += dma.o > > obj-$(CONFIG_FIQ) += fiq.o fiqasm.o > > obj-$(CONFIG_MODULES) += armksyms.o module.o > > +ifeq ($(CONFIG_MODULES),y) > > +obj-y += module_alloc.o > > +else > > +obj-$(CONFIG_KPROBES) += module_alloc.o > > +endif > > Doesn't: > > obj-$(CONFIG_MODULES) += module_alloc.o > obj-$(CONFIG_KPROBES) += module_alloc.o That just begs for a new kconfig symbol for the object, and for the object then to be built with it. The archs which override the default can use ARCH_HAS_VM_ALLOC_EXEC. Please note that the respective free is important as well and its not clear if we need an another define for the free. Someone has to do that work. We want to ensure to noexec the code on free and this can vary on each arch. > work just as well? The kbuild modules.rst documentation says: > > The order of files in $(obj-y) is significant. Duplicates in > the lists are allowed: the first instance will be linked into > built-in.a and succeeding instances will be ignored. > > so you should be fine... or the documentation is wrong! Agreed, but this is just sloppy, better to use a new kconfig symbol to represent what is actually being required. Luis
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
Le 09/06/2022 à 14:57, Jarkko Sakkinen a écrit : > On Thu, Jun 09, 2022 at 08:30:12AM +, Christophe Leroy wrote: >> >> >> Le 08/06/2022 à 01:59, Jarkko Sakkinen a écrit : >>> [You don't often get email from jar...@profian.com. Learn why this is >>> important at https://aka.ms/LearnAboutSenderIdentification ] >>> >>> Tracing with kprobes while running a monolithic kernel is currently >>> impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. This >>> dependency is a result of kprobes code using the module allocator for the >>> trampoline code. >>> >>> Detaching kprobes from modules helps to squeeze down the user space, >>> e.g. when developing new core kernel features, while still having all >>> the nice tracing capabilities. >> >> Nice idea, could also be nice to have BPF without MODULES. > > Yeah, for sure. You have to start from somewhere :-) I'd guess this > a step forward also for BPF. > >>> >>> For kernel/ and arch/*, move module_alloc() and module_memfree() to >>> module_alloc.c, and compile as part of vmlinux when either CONFIG_MODULES >>> or CONFIG_KPROBES is enabled. In addition, flag kernel module specific >>> code with CONFIG_MODULES. >> >> Nice, but that's not enough. You have to audit every peace of code that >> depends on CONFIG_MODULES and see if it needs to be activated for your >> case as well. For instance some powerpc configurations don't honor exec >> page faults on kernel pages when CONFIG_MODULES is not selected. > > Thanks for pointing this out. With "every peace of code" you probably > are referring to the 13 arch-folders, which support kprobes in the first > place (just checking)? In a way yes, I was mainly thinking about the dozen of places in arch/powerpc/ to begin with. And also to check the 30 places with CONFIG_MODULES in includes/ directory which contains things that may be used by architectures.
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
l...@kernel.org>, Masahiro Yamada , Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , "Russell King \(Oracle\)" , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , Parisc List , Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparclinux , Tiezhu Yang , Miroslav Benes , Chen Zhongjin , Ard Biesheuvel , the arch/x86 maintainers , Russell King , linux-riscv , Ingo Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , "open list:BROADCOM NVRAM DRIVER" , Changbin Du , Palmer Dabbelt , linuxppc-dev , linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 09, 2022 at 05:48:52AM +0200, Christoph Hellwig wrote: > On Wed, Jun 08, 2022 at 01:26:19PM -0700, Luis Chamberlain wrote: > > No, that was removed because it has only one user. > > That is only part of the story. The other part is that the overall > kernel simply does not have any business allocating exutable memory. > Executable memory is a very special concept for modules or module-like > code like kprobes, and should not be exposed as a general concept. It is not just modules and kprobes, it is also ftrace and bpf too now. So while it should not be used everywhere calling it module_alloc() is just confusing at this point. Likewise, module_alloc_huge() is being proposed too and I'd rather we deal with this properly in aligment of taking care of the rename as well. If the concern is to restrict access we can use the module namespace stuff so to ensure only intended users get access to it. > Especially as executable memory really should not also be writable > for security reasons. In other words, we should actually never > allocate executable memory, every. We might seal memory and then > mark it executable after having written to it, which is how modules > and kprobes are implemented on all modern Linux ports anyway. The respective free *should* do the executable bits, and there is no generic way to do this for all archs and so it is open coded today. In fact some architectures need further work / help and so split up the module data and exect already on v5.19+ with the new ARCH_WANTS_MODULES_DATA_IN_VMALLOC. See this thread for details: https://lkml.kernel.org/r/yo1xtn441qbnt...@bombadil.infradead.org Doing this work is not easy, but if we're going to do it, it must be done right. Luis
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
@kernel.org>, Masahiro Yamada , Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , "Russell King \(Oracle\)" , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , Parisc List , Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparclinux , Tiezhu Yang , Miroslav Benes , Chen Zhongjin , linux-riscv , the arch/x86 maintainers , Russell King , Ingo Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , "open list:BROADCOM NVRAM DRIVER" , Changbin Du , Palmer Dabbelt , linuxppc-dev , linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, 9 Jun 2022 at 15:14, Jarkko Sakkinen wrote: > > On Wed, Jun 08, 2022 at 09:12:34AM -0700, Song Liu wrote: > > On Wed, Jun 8, 2022 at 7:21 AM Masami Hiramatsu wrote: > > > > > > Hi Jarkko, > > > > > > On Wed, 8 Jun 2022 08:25:38 +0300 > > > Jarkko Sakkinen wrote: > > > > > > > On Wed, Jun 08, 2022 at 10:35:42AM +0800, Guo Ren wrote: > > > > > . > > > > > > > > > > On Wed, Jun 8, 2022 at 8:02 AM Jarkko Sakkinen > > > > > wrote: > > > > > > > > > > > > Tracing with kprobes while running a monolithic kernel is currently > > > > > > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. > > > > > > This > > > > > > dependency is a result of kprobes code using the module allocator > > > > > > for the > > > > > > trampoline code. > > > > > > > > > > > > Detaching kprobes from modules helps to squeeze down the user space, > > > > > > e.g. when developing new core kernel features, while still having > > > > > > all > > > > > > the nice tracing capabilities. > > > > > > > > > > > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > > > > > > module_alloc.c, and compile as part of vmlinux when either > > > > > > CONFIG_MODULES > > > > > > or CONFIG_KPROBES is enabled. In addition, flag kernel module > > > > > > specific > > > > > > code with CONFIG_MODULES. > > > > > > > > > > > > As the result, kprobes can be used with a monolithic kernel. > > > > > It's strange when MODULES is n, but vmlinux still obtains > > > > > module_alloc. > > > > > > > > > > Maybe we need a kprobe_alloc, right? > > > > > > > > Perhaps not the best name but at least it documents the fact that > > > > they use the same allocator. > > > > > > > > Few years ago I carved up something "half-way there" for kprobes, > > > > and I used the name text_alloc() [*]. > > > > > > > > [*] > > > > https://lore.kernel.org/all/20200724050553.1724168-1-jarkko.sakki...@linux.intel.com/ > > > > > > Yeah, I remember that. Thank you for updating your patch! > > > I think the idea (split module_alloc() from CONFIG_MODULE) is good to me. > > > If module support maintainers think this name is not good, you may be > > > able to rename it as text_alloc() and make the module_alloc() as a > > > wrapper of it. > > > > IIUC, most users of module_alloc() use it to allocate memory for text, > > except > > that module code uses it for both text and data. Therefore, I guess calling > > it > > text_alloc() is not 100% accurate until we change the module code (to use > > a different API to allocate memory for data). > > After reading the feedback, I'd stay on using module_alloc() because > it has arch-specific quirks baked in. Easier to deal with them in one > place. > In that case, please ensure that you enable this only on architectures where it is needed. arm64 implements alloc_insn_page() without relying on module_alloc() so I would not expect to see any changes there.
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
ada , Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , "Russell King \(Oracle\)" , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , Parisc List , Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparclinux , Tiezhu Yang , Miroslav Benes , Chen Zhongjin , Ard Biesheuvel , the arch/x86 maintainers , Russell King , linux-riscv , Ingo Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , "open list:BROADCOM NVRAM DRIVER" , Changbin Du , Palmer Dabbelt , linuxppc-dev , linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Jun 08, 2022 at 09:12:34AM -0700, Song Liu wrote: > On Wed, Jun 8, 2022 at 7:21 AM Masami Hiramatsu wrote: > > > > Hi Jarkko, > > > > On Wed, 8 Jun 2022 08:25:38 +0300 > > Jarkko Sakkinen wrote: > > > > > On Wed, Jun 08, 2022 at 10:35:42AM +0800, Guo Ren wrote: > > > > . > > > > > > > > On Wed, Jun 8, 2022 at 8:02 AM Jarkko Sakkinen > > > > wrote: > > > > > > > > > > Tracing with kprobes while running a monolithic kernel is currently > > > > > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. > > > > > This > > > > > dependency is a result of kprobes code using the module allocator for > > > > > the > > > > > trampoline code. > > > > > > > > > > Detaching kprobes from modules helps to squeeze down the user space, > > > > > e.g. when developing new core kernel features, while still having all > > > > > the nice tracing capabilities. > > > > > > > > > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > > > > > module_alloc.c, and compile as part of vmlinux when either > > > > > CONFIG_MODULES > > > > > or CONFIG_KPROBES is enabled. In addition, flag kernel module > > > > > specific > > > > > code with CONFIG_MODULES. > > > > > > > > > > As the result, kprobes can be used with a monolithic kernel. > > > > It's strange when MODULES is n, but vmlinux still obtains module_alloc. > > > > > > > > Maybe we need a kprobe_alloc, right? > > > > > > Perhaps not the best name but at least it documents the fact that > > > they use the same allocator. > > > > > > Few years ago I carved up something "half-way there" for kprobes, > > > and I used the name text_alloc() [*]. > > > > > > [*] > > > https://lore.kernel.org/all/20200724050553.1724168-1-jarkko.sakki...@linux.intel.com/ > > > > Yeah, I remember that. Thank you for updating your patch! > > I think the idea (split module_alloc() from CONFIG_MODULE) is good to me. > > If module support maintainers think this name is not good, you may be > > able to rename it as text_alloc() and make the module_alloc() as a > > wrapper of it. > > IIUC, most users of module_alloc() use it to allocate memory for text, except > that module code uses it for both text and data. Therefore, I guess calling it > text_alloc() is not 100% accurate until we change the module code (to use > a different API to allocate memory for data). After reading the feedback, I'd stay on using module_alloc() because it has arch-specific quirks baked in. Easier to deal with them in one place. > Thanks, > Song BR, Jarkko
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
o...@kernel.org>, Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , "Russell King \(Oracle\)" , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , Parisc List , Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparclinux , Tiezhu Yang , Miroslav Benes , Chen Zhongjin , Ard Biesheuvel , the arch/x86 maintainers , Russell King , linux-riscv , Ingo Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , "open list:BROADCOM NVRAM DRIVER" , Changbin Du , Palmer Dabbelt , linuxppc-dev , linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Jun 08, 2022 at 11:21:15PM +0900, Masami Hiramatsu wrote: > Hi Jarkko, > > On Wed, 8 Jun 2022 08:25:38 +0300 > Jarkko Sakkinen wrote: > > > On Wed, Jun 08, 2022 at 10:35:42AM +0800, Guo Ren wrote: > > > . > > > > > > On Wed, Jun 8, 2022 at 8:02 AM Jarkko Sakkinen wrote: > > > > > > > > Tracing with kprobes while running a monolithic kernel is currently > > > > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. This > > > > dependency is a result of kprobes code using the module allocator for > > > > the > > > > trampoline code. > > > > > > > > Detaching kprobes from modules helps to squeeze down the user space, > > > > e.g. when developing new core kernel features, while still having all > > > > the nice tracing capabilities. > > > > > > > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > > > > module_alloc.c, and compile as part of vmlinux when either > > > > CONFIG_MODULES > > > > or CONFIG_KPROBES is enabled. In addition, flag kernel module specific > > > > code with CONFIG_MODULES. > > > > > > > > As the result, kprobes can be used with a monolithic kernel. > > > It's strange when MODULES is n, but vmlinux still obtains module_alloc. > > > > > > Maybe we need a kprobe_alloc, right? > > > > Perhaps not the best name but at least it documents the fact that > > they use the same allocator. > > > > Few years ago I carved up something "half-way there" for kprobes, > > and I used the name text_alloc() [*]. > > > > [*] > > https://lore.kernel.org/all/20200724050553.1724168-1-jarkko.sakki...@linux.intel.com/ > > > > Yeah, I remember that. Thank you for updating your patch! > I think the idea (split module_alloc() from CONFIG_MODULE) is good to me. > If module support maintainers think this name is not good, you may be > able to rename it as text_alloc() and make the module_alloc() as a > wrapper of it. > > Acked-by: Masami Hiramatsu (Google) > for kprobe side. Thanks a lot! If I split that code into its own patch with no code changes, can I attach this to the patch? I.e. most likely I'll split arch's into their own patches. > Thank you, > > -- > Masami Hiramatsu (Google) BR, Jarkko
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
Alexei Starovoitov , Will Deacon , Masahiro Yamada , Jarkko Sakkinen , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , "Russell King \(Oracle\)" , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , "linux-par...@vger.kernel.org" , Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , "sparcli...@vger.kernel.org" , Tiezhu Yang , Miroslav Benes , Chen Zhongjin , Ard Biesheuvel , "x...@kernel.org" , Russell King , "linux-ri...@lists.infradead.org" , Ingo Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , "linux-m...@vger.kernel.org" , Changbin Du , Palmer Dabbelt , "linuxppc-dev@lists.ozlabs.org" , "linux-modu...@vger.kernel.org" Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 09, 2022 at 08:30:12AM +, Christophe Leroy wrote: > > > Le 08/06/2022 à 01:59, Jarkko Sakkinen a écrit : > > [You don't often get email from jar...@profian.com. Learn why this is > > important at https://aka.ms/LearnAboutSenderIdentification ] > > > > Tracing with kprobes while running a monolithic kernel is currently > > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. This > > dependency is a result of kprobes code using the module allocator for the > > trampoline code. > > > > Detaching kprobes from modules helps to squeeze down the user space, > > e.g. when developing new core kernel features, while still having all > > the nice tracing capabilities. > > Nice idea, could also be nice to have BPF without MODULES. Yeah, for sure. You have to start from somewhere :-) I'd guess this a step forward also for BPF. > > > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > > module_alloc.c, and compile as part of vmlinux when either CONFIG_MODULES > > or CONFIG_KPROBES is enabled. In addition, flag kernel module specific > > code with CONFIG_MODULES. > > Nice, but that's not enough. You have to audit every peace of code that > depends on CONFIG_MODULES and see if it needs to be activated for your > case as well. For instance some powerpc configurations don't honor exec > page faults on kernel pages when CONFIG_MODULES is not selected. Thanks for pointing this out. With "every peace of code" you probably are referring to the 13 arch-folders, which support kprobes in the first place (just checking)? > > As the result, kprobes can be used with a monolithic kernel. > > > > Signed-off-by: Jarkko Sakkinen > > I think this patch should be split in a several patches, one (or even > one per architectures ?) to make modules_alloc() independant of > CONFIG_MODULES, then a patch to make CONFIG_KPROBES independant on > CONFIG_MOUDLES. Agreed. And also because of your previous remark, i.e. each arch needs it own conclusions of the changes. I purposely did this first as a one patch in order to get a better picture of the situation. > > --- > > Tested with the help of BuildRoot and QEMU: > > - arm (function tracer) > > - arm64 (function tracer) > > - mips (function tracer) > > - powerpc (function tracer) > > - riscv (function tracer) > > - s390 (function tracer) > > - sparc (function tracer) > > - x86 (function tracer) > > - sh (function tracer, for the "pure" kernel/modules_alloc.c path) > > --- > > arch/Kconfig | 1 - > > arch/arm/kernel/Makefile | 5 +++ > > arch/arm/kernel/module.c | 32 > > arch/arm/kernel/module_alloc.c | 42 > > arch/arm64/kernel/Makefile | 5 +++ > > arch/arm64/kernel/module.c | 47 --- > > arch/arm64/kernel/module_alloc.c | 57 > > arch/mips/kernel/Makefile | 5 +++ > > arch/mips/kernel/module.c | 9 - > > arch/mips/kernel/module_alloc.c| 18 + > > arch/parisc/kernel/Makefile| 5 +++ > > arch/parisc/kernel/module.c| 11 -- > > arch/parisc/kernel/module_alloc.c | 23 +++ > > arch/powerpc/kernel/Makefile | 5 +++ > > arch/powerpc/kernel/module.c | 37 -- > > arch/powerpc/kernel/module_alloc.c | 47 +++ > > You are missing necessary changes for powerpc. > > On powerpc 8xx or powerpc 603, software TLB handlers don't honor > instruction TLB miss when CONFIG_MODULES are not set, look into > head_8xx.S and head_book3s_32.S > > On powerpc book3s/32, all kernel space is set to NX except the module > segment. When CONFIG_MODULES is all space is set NX. See > mmu_mark_initmem_nx() and is_module_segment(). Thank you! I'll go this through and also try to build an environment with BuildRoot where I can test-run this configuration. > > arch/riscv/kernel/Makefile | 5
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
>, Jarkko Sakkinen , Sami Tolvanen >, "Naveen N. Rao" , Marco >Elver , Kees Cook , Steven Rostedt >, Nathan Chancellor , Mark Brown >, Borislav Petkov , Alexander Egorenkov >, Thomas Bogendoerfer , >linux-par...@vger.kernel.org, Nathaniel McCallum , >Dmitry Torokhov , "David S. Miller" >, "Kirill A. Shutemov" , >Tobias Huschle , "Peter Zijlstra \(Intel\)" >, "H. Peter Anvin" , >sparcli...@vger.kernel.org, Tiezhu Yang , Miroslav >Benes , Chen Zhongjin , Ard >Biesheuvel , x...@kernel.org, >linux-ri...@lists.infradead.org, In go Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , linux-m...@vger.kernel.org, Changbin Du , Palmer Dabbelt , linuxppc-dev@lists.ozlabs.org, linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 09, 2022 at 08:47:38AM +0100, Russell King (Oracle) wrote: > On Wed, Jun 08, 2022 at 02:59:27AM +0300, Jarkko Sakkinen wrote: > > diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile > > index 553866751e1a..d2bb954cd54f 100644 > > --- a/arch/arm/kernel/Makefile > > +++ b/arch/arm/kernel/Makefile > > @@ -44,6 +44,11 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o > > obj-$(CONFIG_ISA_DMA_API) += dma.o > > obj-$(CONFIG_FIQ) += fiq.o fiqasm.o > > obj-$(CONFIG_MODULES) += armksyms.o module.o > > +ifeq ($(CONFIG_MODULES),y) > > +obj-y += module_alloc.o > > +else > > +obj-$(CONFIG_KPROBES) += module_alloc.o > > +endif > > Doesn't: > > obj-$(CONFIG_MODULES) += module_alloc.o > obj-$(CONFIG_KPROBES) += module_alloc.o > > work just as well? The kbuild modules.rst documentation says: > > The order of files in $(obj-y) is significant. Duplicates in > the lists are allowed: the first instance will be linked into > built-in.a and succeeding instances will be ignored. > > so you should be fine... or the documentation is wrong! OK, I did not know this. Thanks for the tip! BR, Jarkko
Re: [PATCH 24/36] printk: Remove trace_.*_rcuidle() usage
e>, ulli.kr...@googlemail.com, vgu...@kernel.org, linux-...@vger.kernel.org, j...@joshtriplett.org, rost...@goodmis.org, r...@vger.kernel.org, b...@alien8.de, bc...@quicinc.com, tsbog...@alpha.franken.de, linux-par...@vger.kernel.org, sudeep.ho...@arm.com, shawn...@kernel.org, da...@davemloft.net, dal...@libc.org, t...@atomide.com, amakha...@vmware.com, bjorn.anders...@linaro.org, h...@zytor.com, sparcli...@vger.kernel.org, linux-hexa...@vger.kernel.org, linux-ri...@lists.infradead.org, anton.iva...@cambridgegreys.com, jo...@southpole.se, yury.no...@gmail.com, rich...@nod.at, x...@kernel.org, li...@armlinux.org.uk, mi...@redhat.com, a...@eecs.berkeley.edu, paul...@kernel.org, h...@linux.ibm.com, stefan.kristians...@saunalahti.fi, openr...@lists.librecores.org, paul.walms...@sifive.com, linux-te...@vger.kernel.org, namhy...@kernel.org, andriy.shevche...@linux.intel.com, jpoim...@kernel.org, jgr...@suse.com, mon...@monstr.eu, linux-m...@vger.kernel.org, pal...@dabbelt.com, a...@brainfault.org , i...@jurassic.park.msu.ru, johan...@sipsolutions.net, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" My emails are getting rejected... Let me try web-interface Kudos to Petr for the questions and thanks to PeterZ for the answers. On Thu, Jun 9, 2022 at 7:02 PM Peter Zijlstra wrote: > This is the tracepoint used to spool all of printk into ftrace, I > suspect there's users, but I haven't used it myself. I'm somewhat curious whether we can actually remove that trace event.
[PATCH 2/2] uio:powerpc:mpc85xx: l2-cache-sram uio driver implementation
The l2-cache could be optionally configured as SRAM partly or fully.
Users can make use of it as a block of independent memory that offers
special usage, such as for debuging or other cratical status info
storage which keeps consistently even when the whole system crashed.
The hardware related configuration process utilized the work of the
earlier implementation, which has been removed now.
See:
https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id=dc21ed2aef4150fc2fcf58227a4ff24502015c03
Cc: Christophe Leroy
Signed-off-by: Wang Wenhu
---
drivers/uio/Kconfig | 10 +
drivers/uio/Makefile | 1 +
drivers/uio/uio_fsl_85xx_cache_sram.c | 286 ++
3 files changed, 297 insertions(+)
create mode 100644 drivers/uio/uio_fsl_85xx_cache_sram.c
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index 2e16c5338e5b..9199ced03880 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -105,6 +105,16 @@ config UIO_NETX
To compile this driver as a module, choose M here; the module
will be called uio_netx.
+config UIO_FSL_85XX_CACHE_SRAM
+ tristate "Freescale 85xx Cache-Sram driver"
+ depends on FSL_SOC_BOOKE && PPC32
+ help
+ Generic driver for accessing the Cache-Sram form user level. This
+ is extremely helpful for some user-space applications that require
+ high performance memory accesses.
+
+ If you don't know what to do here, say N.
+
config UIO_FSL_ELBC_GPCM
tristate "eLBC/GPCM driver"
depends on FSL_LBC
diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
index f2f416a14228..1ba07d92a1b1 100644
--- a/drivers/uio/Makefile
+++ b/drivers/uio/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_UIO_MF624) += uio_mf624.o
obj-$(CONFIG_UIO_FSL_ELBC_GPCM)+= uio_fsl_elbc_gpcm.o
obj-$(CONFIG_UIO_HV_GENERIC) += uio_hv_generic.o
obj-$(CONFIG_UIO_DFL) += uio_dfl.o
+obj-$(CONFIG_UIO_FSL_85XX_CACHE_SRAM) += uio_fsl_85xx_cache_sram.o
diff --git a/drivers/uio/uio_fsl_85xx_cache_sram.c
b/drivers/uio/uio_fsl_85xx_cache_sram.c
new file mode 100644
index ..d363f9d2b179
--- /dev/null
+++ b/drivers/uio/uio_fsl_85xx_cache_sram.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Wang Wenhu
+ * All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DRIVER_NAME"uio_mpc85xx_cache_sram"
+#define UIO_INFO_VER "0.0.1"
+#define UIO_NAME "uio_cache_sram"
+
+#define L2CR_L2FI 0x4000 /* L2 flash
invalidate */
+#define L2CR_L2IO 0x0020 /* L2
instruction only */
+#define L2CR_SRAM_ZERO 0x /* L2SRAM zero size */
+#define L2CR_SRAM_FULL 0x0001 /* L2SRAM full size */
+#define L2CR_SRAM_HALF 0x0002 /* L2SRAM half size */
+#define L2CR_SRAM_TWO_HALFS0x0003 /* L2SRAM two half
sizes */
+#define L2CR_SRAM_QUART0x0004 /* L2SRAM one
quarter size */
+#define L2CR_SRAM_TWO_QUARTS 0x0005 /* L2SRAM two quarter size */
+#define L2CR_SRAM_EIGHTH 0x0006 /* L2SRAM one eighth
size */
+#define L2CR_SRAM_TWO_EIGHTH 0x0007 /* L2SRAM two eighth size */
+
+#define L2SRAM_OPTIMAL_SZ_SHIFT0x0003 /* Optimum size for
L2SRAM */
+
+#define L2SRAM_BAR_MSK_LO180xC000 /* Lower 18 bits */
+#define L2SRAM_BARE_MSK_HI40x000F /* Upper 4 bits */
+
+enum cache_sram_lock_ways {
+ LOCK_WAYS_ZERO,
+ LOCK_WAYS_EIGHTH,
+ LOCK_WAYS_TWO_EIGHTH,
+ LOCK_WAYS_HALF = 4,
+ LOCK_WAYS_FULL = 8,
+};
+
+struct mpc85xx_l2ctlr {
+ u32 ctl;/* 0x000 - L2 control */
+ u8 res1[0xC];
+ u32 ewar0; /* 0x010 - External write address 0 */
+ u32 ewarea0;/* 0x014 - External write address extended 0 */
+ u32 ewcr0; /* 0x018 - External write ctrl */
+ u8 res2[4];
+ u32 ewar1; /* 0x020 - External write address 1 */
+ u32 ewarea1;/* 0x024 - External write address extended 1 */
+ u32 ewcr1; /* 0x028 - External write ctrl 1 */
+ u8 res3[4];
+ u32 ewar2; /* 0x030 - External write address 2 */
+ u32 ewarea2;/* 0x034 - External write address extended 2 */
+ u32 ewcr2; /* 0x038 - External write ctrl 2 */
+ u8 res4[4];
+ u32 ewar3; /* 0x040 - External write address 3 */
+ u32 ewarea3;/* 0x044 - External write address extended 3 */
+ u32 ewcr3; /* 0x048 - External write ctrl 3 */
+ u8 res5[0xB4];
+ u32 srbar0; /* 0x100 - SRAM base address 0
[PATCH 1/2] powerpc:mm: export symbol ioremap_coherent
The function ioremap_coherent may be called by modules such as
fsl_85xx_cache_sram. So export it for access in other modules.
Signed-off-by: Wang Wenhu
---
arch/powerpc/mm/ioremap.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/mm/ioremap.c b/arch/powerpc/mm/ioremap.c
index 4f12504fb405..08a00dacef0b 100644
--- a/arch/powerpc/mm/ioremap.c
+++ b/arch/powerpc/mm/ioremap.c
@@ -40,6 +40,7 @@ void __iomem *ioremap_coherent(phys_addr_t addr, unsigned
long size)
return iowa_ioremap(addr, size, prot, caller);
return __ioremap_caller(addr, size, prot, caller);
}
+EXPORT_SYMBOL(ioremap_coherent);
void __iomem *ioremap_prot(phys_addr_t addr, unsigned long size, unsigned long
flags)
{
--
2.25.1
[PATCH 0/2] uio:ppc: cache-sram driver implementation
Patch 1 exports the symbol ioremap_coherent which is used by the driver. Patch 2 is the implementation of uio driver for freescale mpc85xx. Wang Wenhu (2): powerpc:mm: export symbol ioremap_coherent uio:powerpc:mpc85xx: l2-cache-sram uio driver implementation arch/powerpc/mm/ioremap.c | 1 + drivers/uio/Kconfig | 10 + drivers/uio/Makefile | 1 + drivers/uio/uio_fsl_85xx_cache_sram.c | 286 ++ 4 files changed, 298 insertions(+) create mode 100644 drivers/uio/uio_fsl_85xx_cache_sram.c -- 2.25.1
[PATCH] powerpc/ptrace: Fix buffer overflow when handling PTRACE_PEEKUSER and PTRACE_POKEUSER
This fixes the gdbserver issue on PPC32 described here:
Link:
https://linuxppc-dev.ozlabs.narkive.com/C46DRek4/debug-problems-on-ppc-83xx-target-due-to-changed-struct-task-struct
On PPC32, the user space code considers the floating point to be an
array of unsigned int (32 bits) - the index passed in is based on
this assumption.
fp_state is a matrix consisting of 32 lines
/* FP and VSX 0-31 register set /
struct thread_fp_state {
u64 fpr[32][TS_FPRWIDTH] attribute((aligned(16)));
u64 fpscr; / Floating point status */
};
On PPC32, PT_FPSCR is defined as: (PT_FPR0 + 2*32 + 1)
This means the fpr index validation allows a range from 0 to 65, leading
to out-of-bounds array access. This ends up corrupting
threads_struct->state, which holds the state of the task. Thus, threads
incorrectly transition from a running state to a traced state and get
stuck in that state.
On PPC32 it's ok to assume that TS_FPRWIDTH is 1 because CONFIG_VSX is
PPC64 specific. TS_FPROFFSET can be safely ignored, thus the assumption
that fpr is an array of 32 elements of type u64 holds true.
Solution taken from arch/powerpc/kernel/ptrace32.c
Signed-off-by: Ariel Miculas
---
arch/powerpc/kernel/ptrace/ptrace-fpu.c | 31 +++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
index 5dca19361316..93695abbbdfb 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-fpu.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-fpu.c
@@ -6,9 +6,16 @@
#include "ptrace-decl.h"
+#ifdef CONFIG_PPC32
+/* Macros to workout the correct index for the FPR in the thread struct */
+#define FPRNUMBER(i) (((i) - PT_FPR0) >> 1)
+#define FPRHALF(i) (((i) - PT_FPR0) & 1)
+#define FPRINDEX(i) TS_FPRWIDTH * FPRNUMBER(i) * 2 + FPRHALF(i)
+#endif
+
int ptrace_get_fpr(struct task_struct *child, int index, unsigned long *data)
{
-#ifdef CONFIG_PPC_FPU_REGS
+#if defined(CONFIG_PPC_FPU_REGS) && !defined(CONFIG_PPC32)
unsigned int fpidx = index - PT_FPR0;
#endif
@@ -17,10 +24,20 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
+#ifdef CONFIG_PPC32
+ /*
+* the user space code considers the floating point
+* to be an array of unsigned int (32 bits) - the
+* index passed in is based on this assumption.
+*/
+ *data = ((unsigned int *)child->thread.fp_state.fpr)
+ [FPRINDEX(index)];
+#else
if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(data, >thread.TS_FPR(fpidx), sizeof(long));
else
*data = child->thread.fp_state.fpscr;
+#endif
#else
*data = 0;
#endif
@@ -30,7 +47,7 @@ int ptrace_get_fpr(struct task_struct *child, int index,
unsigned long *data)
int ptrace_put_fpr(struct task_struct *child, int index, unsigned long data)
{
-#ifdef CONFIG_PPC_FPU_REGS
+#if defined(CONFIG_PPC_FPU_REGS) && !defined(CONFIG_PPC32)
unsigned int fpidx = index - PT_FPR0;
#endif
@@ -39,10 +56,20 @@ int ptrace_put_fpr(struct task_struct *child, int index,
unsigned long data)
#ifdef CONFIG_PPC_FPU_REGS
flush_fp_to_thread(child);
+#ifdef CONFIG_PPC32
+ /*
+* the user space code considers the floating point
+* to be an array of unsigned int (32 bits) - the
+* index passed in is based on this assumption.
+*/
+ ((unsigned int *)child->thread.fp_state.fpr)
+ [FPRINDEX(index)] = data;
+#else
if (fpidx < (PT_FPSCR - PT_FPR0))
memcpy(>thread.TS_FPR(fpidx), , sizeof(long));
else
child->thread.fp_state.fpscr = data;
+#endif
#endif
return 0;
--
2.36.1
Re: [PATCH 24/36] printk: Remove trace_.*_rcuidle() usage
li.kr...@googlemail.com, vgu...@kernel.org, linux-...@vger.kernel.org,
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Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org
Sender: "Linuxppc-dev"
On Thu, Jun 09, 2022 at 11:16:46AM +0200, Petr Mladek wrote:
> On Wed 2022-06-08 16:27:47, Peter Zijlstra wrote:
> > The problem, per commit fc98c3c8c9dc ("printk: use rcuidle console
> > tracepoint"), was printk usage from the cpuidle path where RCU was
> > already disabled.
> >
> > Per the patches earlier in this series, this is no longer the case.
>
> My understanding is that this series reduces a lot the amount
> of code called with RCU disabled. As a result the particular printk()
> call mentioned by commit fc98c3c8c9dc ("printk: use rcuidle console
> tracepoint") is called with RCU enabled now. Hence this particular
> problem is fixed better way now.
>
> But is this true in general?
> Does this "prevent" calling printk() a safe way in code with
> RCU disabled?
On x86_64, yes. Other architectures, less so.
Specifically, the objtool noinstr validation pass will warn at build
time (DEBUG_ENTRY=y) if any noinstr/cpuidle code does a call to
non-vetted code like printk().
At the same time; there's a few hacks that allow WARN to work, but
mostly if you hit WARN in entry/noinstr you get to keep the pieces in
any case.
On other architecture we'll need to rely on runtime coverage with
PROVE_RCU. That is, if a splat like in the above mentioned commit
happens again, we'll need to fix it by adjusting the callchain, not by
mucking about with RCU state.
> I am not sure if anyone cares. printk() is the best effort
> functionality because of the consoles code anyway. Also I wonder
> if anyone uses this trace_console().
This is the tracepoint used to spool all of printk into ftrace, I
suspect there's users, but I haven't used it myself.
> Therefore if this patch allows to remove some tricky tracing
> code then it might be worth it. But if trace_console_rcuidle()
> variant is still going to be available then I would keep using it.
My ultimate goal is to delete trace_.*_rcuidle() and RCU_NONIDLE()
entirely. We're close, but not quite there yet.
Re: [PATCH 33/36] cpuidle,omap3: Use WFI for omap3_pm_idle()
o...@users.sourceforge.jp>, Linux-sh list , Will Deacon , Helge Deller , Daniel Lezcano , Jonathan Hunter , Mathieu Desnoyers , Frederic Weisbecker , Len Brown , "open list:TENSILICA XTENSA PORT \(xtensa\)" , Sascha Hauer , Vasily Gorbik , linux-arm-msm , alpha , linux-m68k , Stafford Horne , Linux ARM , Chris Zankel , Stephen Boyd , Dinh Nguyen , Daniel Bristot de Oliveira , Alexander Shishkin , lpieral...@kernel.org, Rasmus Villemoes , Joel Fernandes , Fabio Estevam , Boris Ostrovsky , Kevin Hilman , linux-c...@vger.kernel.org, "open list:SYNOPSYS ARC ARCHITECTURE" , Mel Gorman , jacob.jun@linux.intel.com, Arnd Bergmann , Hans Ulli Kroll , Vineet Gupta , linux-clk , Josh Triplett , Steven Rostedt , r...@vger.kernel.org, Borislav Petkov , bc...@quicinc.com, Thomas Bogendoerfer , Parisc List , Sudeep Holla , Shawn Guo , David Miller , Rich Felker , Pv-drivers , amakha...@vmware.com, Bjorn Andersson , "H. Peter Anvin" , sparclinux , "open list:QUALCOMM HEXAGON..." , linux-riscv , Anton Ivanov , Jonas Bonn , Yury Norov , Richard Weinberger , the arch/x86 maintainers , Russell King - ARM Linux , Ingo Molnar , Albert Ou , "Paul E. McKenney" , Heiko Carstens , Stefan Kristiansson , Openrisc , Paul Walmsley , "open list:TEGRA ARCHITECTURE SUPPORT" , Namhyung Kim , Andy Shevchenko , jpoim...@kernel.org, Juergen Gross , Michal Simek , "open list:BROADCOM NVRAM DRIVER" , Palmer Dabbelt , Anup Patel , Ivan Kokshaysky , Johannes Berg , linuxppc-dev Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 09, 2022 at 10:39:22AM +0300, Tony Lindgren wrote: > * Arnd Bergmann [220608 18:18]: > > On Wed, Jun 8, 2022 at 4:27 PM Peter Zijlstra wrote: > > > > > > arch_cpu_idle() is a very simple idle interface and exposes only a > > > single idle state and is expected to not require RCU and not do any > > > tracing/instrumentation. > > > > > > As such, omap_sram_idle() is not a valid implementation. Replace it > > > with the simple (shallow) omap3_do_wfi() call. Leaving the more > > > complicated idle states for the cpuidle driver. > > Agreed it makes sense to limit deeper idle states to cpuidle. Hopefully > there is some informative splat for attempting to use arch_cpu_ide() > for deeper idle states :) The arch_cpu_idle() interface doesn't allow one to express a desire for deeper states. I'm not sure how anyone could even attempt this. But given what OMAP needs to go deeper, this would involve things that require RCU, combine that with the follow up patches that rip out all the trace_.*_rcuidle() hackery from the power and clock domain code, PROVE_RCU should scream if anybody were to attempt it.
Re: [PATCH 33/36] cpuidle,omap3: Use WFI for omap3_pm_idle()
o...@users.sourceforge.jp>, Linux-sh list , Fabio Estevam , Helge Deller , Daniel Lezcano , Jonathan Hunter , Mathieu Desnoyers , Frederic Weisbecker , Len Brown , "open list:TENSILICA XTENSA PORT \(xtensa\)" , Sascha Hauer , Vasily Gorbik , linux-arm-msm , alpha , linux-m68k , Stafford Horne , Linux ARM , Chris Zankel , Stephen Boyd , Dinh Nguyen , Daniel Bristot de Oliveira , Alexander Shishkin , lpieral...@kernel.org, Rasmus Villemoes , Joel Fernandes < j...@joelfernandes.org>, Will Deacon , Boris Ostrovsky , Kevin Hilman , linux-c...@vger.kernel.org, Pv-drivers , "open list:SYNOPSYS ARC ARCHITECTURE" , Mel Gorman , jacob.jun@linux.intel.com, Yury Norov , Hans Ulli Kroll , Vineet Gupta , linux-clk , Josh Triplett , Steven Rostedt , r...@vger.kernel.org, Borislav Petkov , bc...@quicinc.com, Thomas Bogendoerfer , Parisc List , Sudeep Holla , Shawn Guo , David Miller , Rich Felker , Tony Lindgren , amakha...@vmware.com, Bjorn Andersson , "H. Peter Anvin" , sparclinux , "op en list:QUALCOMM HEXAGON..." , linux-riscv , Anton Ivanov , Jonas Bonn , Richard Weinberger , the arch/x86 maintainers , Russell King - ARM Linux , Ingo Molnar , Albert Ou , "Paul E. McKenney" , Heiko Carstens , Stefan Kristiansson , Openrisc , Paul Walmsley , "open list:TEGRA ARCHITECTURE SUPPORT" , Namhyung Kim , Andy Shevchenko , jpoim...@kernel.org, Juergen Gross , Michal Simek , "open list:BROADCOM NVRAM DRIVER" , Palmer Dabbelt , Anup Patel , Ivan Kokshay sky , Johannes Berg , linuxppc-dev Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Jun 08, 2022 at 06:28:33PM +0200, Arnd Bergmann wrote: > On Wed, Jun 8, 2022 at 4:27 PM Peter Zijlstra wrote: > > > > arch_cpu_idle() is a very simple idle interface and exposes only a > > single idle state and is expected to not require RCU and not do any > > tracing/instrumentation. > > > > As such, omap_sram_idle() is not a valid implementation. Replace it > > with the simple (shallow) omap3_do_wfi() call. Leaving the more > > complicated idle states for the cpuidle driver. > > > > Signed-off-by: Peter Zijlstra (Intel) > > I see similar code in omap2: > > omap2_pm_idle() > -> omap2_enter_full_retention() > -> omap2_sram_suspend() > > Is that code path safe to use without RCU or does it need a similar change? It needs a similar change, clearly I was running on fumes to not have found that when grepping around the omap code :/
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
Le 08/06/2022 à 18:12, Song Liu a écrit : > On Wed, Jun 8, 2022 at 7:21 AM Masami Hiramatsu wrote: >> >> Hi Jarkko, >> >> On Wed, 8 Jun 2022 08:25:38 +0300 >> Jarkko Sakkinen wrote: >> >>> On Wed, Jun 08, 2022 at 10:35:42AM +0800, Guo Ren wrote: . On Wed, Jun 8, 2022 at 8:02 AM Jarkko Sakkinen wrote: > > Tracing with kprobes while running a monolithic kernel is currently > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. This > dependency is a result of kprobes code using the module allocator for the > trampoline code. > > Detaching kprobes from modules helps to squeeze down the user space, > e.g. when developing new core kernel features, while still having all > the nice tracing capabilities. > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > module_alloc.c, and compile as part of vmlinux when either CONFIG_MODULES > or CONFIG_KPROBES is enabled. In addition, flag kernel module specific > code with CONFIG_MODULES. > > As the result, kprobes can be used with a monolithic kernel. It's strange when MODULES is n, but vmlinux still obtains module_alloc. Maybe we need a kprobe_alloc, right? >>> >>> Perhaps not the best name but at least it documents the fact that >>> they use the same allocator. >>> >>> Few years ago I carved up something "half-way there" for kprobes, >>> and I used the name text_alloc() [*]. >>> >>> [*] >>> https://lore.kernel.org/all/20200724050553.1724168-1-jarkko.sakki...@linux.intel.com/ >> >> Yeah, I remember that. Thank you for updating your patch! >> I think the idea (split module_alloc() from CONFIG_MODULE) is good to me. >> If module support maintainers think this name is not good, you may be >> able to rename it as text_alloc() and make the module_alloc() as a >> wrapper of it. > > IIUC, most users of module_alloc() use it to allocate memory for text, except > that module code uses it for both text and data. Therefore, I guess calling it > text_alloc() is not 100% accurate until we change the module code (to use > a different API to allocate memory for data). When CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC, module code uses module_alloc() for text and vmalloc() for data, see function move_module() in kernel/module/main.c > > Thanks, > Song > >> >> Acked-by: Masami Hiramatsu (Google) >> for kprobe side. >> >> Thank you, >> >> -- >> Masami Hiramatsu (Google)
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
Le 08/06/2022 à 01:59, Jarkko Sakkinen a écrit : > [You don't often get email from jar...@profian.com. Learn why this is > important at https://aka.ms/LearnAboutSenderIdentification ] > > Tracing with kprobes while running a monolithic kernel is currently > impossible because CONFIG_KPROBES is dependent of CONFIG_MODULES. This > dependency is a result of kprobes code using the module allocator for the > trampoline code. > > Detaching kprobes from modules helps to squeeze down the user space, > e.g. when developing new core kernel features, while still having all > the nice tracing capabilities. Nice idea, could also be nice to have BPF without MODULES. > > For kernel/ and arch/*, move module_alloc() and module_memfree() to > module_alloc.c, and compile as part of vmlinux when either CONFIG_MODULES > or CONFIG_KPROBES is enabled. In addition, flag kernel module specific > code with CONFIG_MODULES. Nice, but that's not enough. You have to audit every peace of code that depends on CONFIG_MODULES and see if it needs to be activated for your case as well. For instance some powerpc configurations don't honor exec page faults on kernel pages when CONFIG_MODULES is not selected. > > As the result, kprobes can be used with a monolithic kernel. > > Signed-off-by: Jarkko Sakkinen I think this patch should be split in a several patches, one (or even one per architectures ?) to make modules_alloc() independant of CONFIG_MODULES, then a patch to make CONFIG_KPROBES independant on CONFIG_MOUDLES. > --- > Tested with the help of BuildRoot and QEMU: > - arm (function tracer) > - arm64 (function tracer) > - mips (function tracer) > - powerpc (function tracer) > - riscv (function tracer) > - s390 (function tracer) > - sparc (function tracer) > - x86 (function tracer) > - sh (function tracer, for the "pure" kernel/modules_alloc.c path) > --- > arch/Kconfig | 1 - > arch/arm/kernel/Makefile | 5 +++ > arch/arm/kernel/module.c | 32 > arch/arm/kernel/module_alloc.c | 42 > arch/arm64/kernel/Makefile | 5 +++ > arch/arm64/kernel/module.c | 47 --- > arch/arm64/kernel/module_alloc.c | 57 > arch/mips/kernel/Makefile | 5 +++ > arch/mips/kernel/module.c | 9 - > arch/mips/kernel/module_alloc.c| 18 + > arch/parisc/kernel/Makefile| 5 +++ > arch/parisc/kernel/module.c| 11 -- > arch/parisc/kernel/module_alloc.c | 23 +++ > arch/powerpc/kernel/Makefile | 5 +++ > arch/powerpc/kernel/module.c | 37 -- > arch/powerpc/kernel/module_alloc.c | 47 +++ You are missing necessary changes for powerpc. On powerpc 8xx or powerpc 603, software TLB handlers don't honor instruction TLB miss when CONFIG_MODULES are not set, look into head_8xx.S and head_book3s_32.S On powerpc book3s/32, all kernel space is set to NX except the module segment. When CONFIG_MODULES is all space is set NX. See mmu_mark_initmem_nx() and is_module_segment(). > arch/riscv/kernel/Makefile | 5 +++ > arch/riscv/kernel/module.c | 10 - > arch/riscv/kernel/module_alloc.c | 19 ++ > arch/s390/kernel/Makefile | 5 +++ > arch/s390/kernel/module.c | 17 - > arch/s390/kernel/module_alloc.c| 33 > arch/sparc/kernel/Makefile | 5 +++ > arch/sparc/kernel/module.c | 30 --- > arch/sparc/kernel/module_alloc.c | 39 +++ > arch/x86/kernel/Makefile | 5 +++ > arch/x86/kernel/module.c | 50 > arch/x86/kernel/module_alloc.c | 61 ++ > kernel/Makefile| 5 +++ > kernel/kprobes.c | 10 + > kernel/module/main.c | 17 - > kernel/module_alloc.c | 26 + > kernel/trace/trace_kprobe.c| 10 - > 33 files changed, 434 insertions(+), 262 deletions(-) > create mode 100644 arch/arm/kernel/module_alloc.c > create mode 100644 arch/arm64/kernel/module_alloc.c > create mode 100644 arch/mips/kernel/module_alloc.c > create mode 100644 arch/parisc/kernel/module_alloc.c > create mode 100644 arch/powerpc/kernel/module_alloc.c > create mode 100644 arch/riscv/kernel/module_alloc.c > create mode 100644 arch/s390/kernel/module_alloc.c > create mode 100644 arch/sparc/kernel/module_alloc.c > create mode 100644 arch/x86/kernel/module_alloc.c > create mode 100644 kernel/module_alloc.c > > diff --git a/arch/Kconfig b/arch/Kconfig > index fcf9a41a4ef5..e8e3e7998a2e 100644 > --- a/arch/Kconfig > +++ b/arch/Kconfig > @@ -39,7 +39,6 @@ config GENERIC_ENTRY > > config KPROBES > bool "Kprobes" > - depends on MODULES > depends on HAVE_KPROBES >
Re: [PATCH] kprobes: Enable tracing for mololithic kernel images
Masahiro Yamada , Sami Tolvanen , "Naveen N. Rao" , Marco Elver , Kees Cook , Steven Rostedt , Nathan Chancellor , Mark Brown , Borislav Petkov , Alexander Egorenkov , Thomas Bogendoerfer , linux-par...@vger.kernel.org, Nathaniel McCallum , Dmitry Torokhov , "David S. Miller" , "Kirill A. Shutemov" , Tobias Huschle , "Peter Zijlstra \(Intel\)" , "H. Peter Anvin" , sparcli...@vger.kernel.org, Tiezhu Yang , Miroslav Benes , Chen Zhongjin , Ard Biesheuvel , x...@kernel.org, linux-ri...@lists.infradead.org, Ing o Molnar , Aaron Tomlin , Albert Ou , Heiko Carstens , Liao Chang , Paul Walmsley , Josh Poimboeuf , Thomas Richter , linux-m...@vger.kernel.org, Changbin Du , Palmer Dabbelt , linuxppc-dev@lists.ozlabs.org, linux-modu...@vger.kernel.org Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Jun 08, 2022 at 02:59:27AM +0300, Jarkko Sakkinen wrote: > diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile > index 553866751e1a..d2bb954cd54f 100644 > --- a/arch/arm/kernel/Makefile > +++ b/arch/arm/kernel/Makefile > @@ -44,6 +44,11 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o > obj-$(CONFIG_ISA_DMA_API)+= dma.o > obj-$(CONFIG_FIQ)+= fiq.o fiqasm.o > obj-$(CONFIG_MODULES)+= armksyms.o module.o > +ifeq ($(CONFIG_MODULES),y) > +obj-y+= module_alloc.o > +else > +obj-$(CONFIG_KPROBES)+= module_alloc.o > +endif Doesn't: obj-$(CONFIG_MODULES) += module_alloc.o obj-$(CONFIG_KPROBES) += module_alloc.o work just as well? The kbuild modules.rst documentation says: The order of files in $(obj-y) is significant. Duplicates in the lists are allowed: the first instance will be linked into built-in.a and succeeding instances will be ignored. so you should be fine... or the documentation is wrong! -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
Re: [PATCH 33/36] cpuidle,omap3: Use WFI for omap3_pm_idle()
o...@users.sourceforge.jp>, Linux-sh list , Fabio Estevam , Helge Deller , Daniel Lezcano , Jonathan Hunter , Mathieu Desnoyers , Frederic Weisbecker , Len Brown , "open list:TENSILICA XTENSA PORT \(xtensa\)" , Sascha Hauer , Vasily Gorbik , linux-arm-msm , alpha , linux-m68k , Stafford Horne , Linux ARM , Chris Zankel , Stephen Boyd , Dinh Nguyen , Daniel Bristot de Oliveira , Alexander Shishkin , lpieral...@kernel.org, Rasmus Villemoes , Joel Fernandes < j...@joelfernandes.org>, Will Deacon , Boris Ostrovsky , Kevin Hilman , linux-c...@vger.kernel.org, Pv-drivers , "open list:SYNOPSYS ARC ARCHITECTURE" , Mel Gorman , jacob.jun@linux.intel.com, Yury Norov , Hans Ulli Kroll , Vineet Gupta , linux-clk , Josh Triplett , Steven Rostedt , r...@vger.kernel.org, Borislav Petkov , bc...@quicinc.com, Thomas Bogendoerfer , Parisc List , Sudeep Holla , Shawn Guo , David Miller , Rich Felker , Peter Zijlstra , amakha...@vmware.com, Bjorn Andersson , "H. Peter Anvin" , sparclinux , "open list:QUALCOMM HEXAGON..." , linux-riscv , Anton Ivanov , Jonas Bonn , Richard Weinberger , the arch/x86 maintainers , Russell King - ARM Linux , Ingo Molnar , Albert Ou , "Paul E. McKenney" , Heiko Carstens , Stefan Kristiansson , Openrisc , Paul Walmsley , "open list:TEGRA ARCHITECTURE SUPPORT" , Namhyung Kim , Andy Shevchenko , jpoim...@kernel.org, Juergen Gross , Michal Simek , "open list:BROADCOM NVRAM DRIVER" , Palmer Dabbelt , Anup Patel , Ivan Ko kshaysky , Johannes Berg , linuxppc-dev Errors-To: linuxppc-dev-bounces+archive=mail-archive@lists.ozlabs.org Sender: "Linuxppc-dev" * Arnd Bergmann [220608 18:18]: > On Wed, Jun 8, 2022 at 4:27 PM Peter Zijlstra wrote: > > > > arch_cpu_idle() is a very simple idle interface and exposes only a > > single idle state and is expected to not require RCU and not do any > > tracing/instrumentation. > > > > As such, omap_sram_idle() is not a valid implementation. Replace it > > with the simple (shallow) omap3_do_wfi() call. Leaving the more > > complicated idle states for the cpuidle driver. Agreed it makes sense to limit deeper idle states to cpuidle. Hopefully there is some informative splat for attempting to use arch_cpu_ide() for deeper idle states :) > I see similar code in omap2: > > omap2_pm_idle() > -> omap2_enter_full_retention() > -> omap2_sram_suspend() > > Is that code path safe to use without RCU or does it need a similar change? Seems like a similar change should be done for omap2. Then anybody who cares to implement a minimal cpuidle support can do so. Regards, Tony
Re: [PATCH v2] powerpc/perf: Give generic PMU a nice name
> On 10-Jun-2022, at 10:10 AM, Joel Stanley wrote:
>
> When booting on a machine that uses the compat pmu driver we see this:
>
> [0.071192] GENERIC_COMPAT performance monitor hardware support registered
>
> Which is a bit shouty. Give it a nicer name.
>
> Signed-off-by: Joel Stanley
> ---
> v2: Go with ISAv3
>
> arch/powerpc/perf/generic-compat-pmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/perf/generic-compat-pmu.c
> b/arch/powerpc/perf/generic-compat-pmu.c
> index f3db88aee4dd..16392962c511 100644
> --- a/arch/powerpc/perf/generic-compat-pmu.c
> +++ b/arch/powerpc/perf/generic-compat-pmu.c
> @@ -292,7 +292,7 @@ static int generic_compute_mmcr(u64 event[], int n_ev,
> }
>
> static struct power_pmu generic_compat_pmu = {
> - .name = "GENERIC_COMPAT",
> + .name = "ISAv3",
Looks good.
Reviewed-by: Athira Rajeev
> .n_counter = MAX_PMU_COUNTERS,
> .add_fields = ISA207_ADD_FIELDS,
> .test_adder = ISA207_TEST_ADDER,
> --
> 2.35.1
>
Re: [PATCH] powerpc/pci: Add config option for using OF 'reg' for PCI domain
On Friday 10 June 2022 17:33:32 Michael Ellerman wrote: > If you have scripts that are looking for certain devices they can use > the vendor/device fields in sysfs to find the actual devices they want, > not just whatever happens to be at :01:00.0. This does not work if you have more cards with same vendor+device ids in system.
Re: [PATCH] powerpc/pci: Add config option for using OF 'reg' for PCI domain
Pali Rohár writes:
> Since commit 63a72284b159 ("powerpc/pci: Assign fixed PHB number based on
> device-tree properties"), powerpc kernel always fallback to PCI domain
> assignment from OF / Device Tree 'reg' property of the PCI controller.
>
> PCI code for other Linux architectures use increasing assignment of the PCI
> domain for individual controllers (assign the first free number), like it
> was also for powerpc prior mentioned commit.
>
> Upgrading powerpc kernels from LTS 4.4 version (which does not contain
> mentioned commit) to new LTS versions brings a regression in domain
> assignment.
I'm sorry this broke your system. But I don't really consider it a
regression, the kernel provides no guarantee about the PCI domain
numbering across LTS releases.
Prior to the change the numbering was just based on the order the PHBs
were discovered in the device tree, which is not robust. A cosmetic
refactor of the device tree source could cause PHBs to be discovered in
a different order.
Similarly a change in firmware PCI discovery or device tree generation
could cause the numbering to change.
If you have scripts that are looking for certain devices they can use
the vendor/device fields in sysfs to find the actual devices they want,
not just whatever happens to be at :01:00.0.
> Fix this issue by introducing a new option CONFIG_PPC_PCI_DOMAIN_FROM_OF_REG
> When this options is disabled then powerpc kernel would assign PCI domains
> in the similar way like it is doing kernel for other architectures and also
> how it was done prior that commit.
I really don't want a config option for that.
There is a device tree property "linux,pci-domain", described in
Documentation/devicetree/bindings/pci/pci.txt.
Can you try adding that to your device tree and updating
get_phb_number() to look for it?
cheers
