RE: [PATCH] Add device file bindings for MAPLE
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 30, 2013 5:31 AM
To: Leekha Shaveta-B20052
Cc: devicetree-disc...@lists.ozlabs.org; linuxppc-dev@lists.ozlabs.org; Leekha
Shaveta-B20052
Subject: Re: [PATCH] Add device file bindings for MAPLE
On 07/27/2013 08:03:42 AM, Shaveta Leekha wrote:
Signed-off-by: Shaveta Leekha shav...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/maple.txt | 50
1 files changed, 50 insertions(+), 0 deletions(-) create mode 100644
Documentation/devicetree/bindings/powerpc/fsl/maple.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/maple.txt
b/Documentation/devicetree/bindings/powerpc/fsl/maple.txt
new file mode 100644
index 000..23b80a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/maple.txt
@@ -0,0 +1,50 @@
+* Freescale MAPLE Multi Accelerator Platform Engine Baseband 3
+ (MAPLE-B3)device nodes
+
+Supported chips:
+Example: B4860
+
+Required properties:
+
+- compatible:Should contain fsl,maple-b3 as the value
+ This identifies Multi Accelerator Platform Engine
+ Baseband 3 block.
+
+- reg: offset and length of the register set for the
device
+
+- interrupts
+ Usage: required
+ Value type: prop_encoded-array
+ Definition: Specifies the interrupts generated by this
device. The
+ value of the interrupts property consists of
one interrupt
+ specifier. The format of the specifier is
defined by the
+ binding document describing the node's
interrupt parent.
Please clean up whitespace so the text aligns.
[Leekha Shaveta-B20052] ok. Will remove whitespaces.
+
+ A single IRQ that handles error conditions is specified
by
+ this property. (Typically shared with port-write).
+
+Devices that have LIODNs need to specify links to the parent PAMU
controller
+(the actual PAMU controller that this device is connected to) and a
pointer to
+the LIODN register, if applicable.
+
+- fsl,iommu-parent
+ : phandle
+ This property should be present
+
+- status = disabled
+ In this example, status is set disabled,
+ As Maple device wouldn't be used by PPC Linux. This
representation is required
+ for doing the PAMU programming on the Linux side.
Is it proper for Linux to even set the LIODN on a device that is disabled?
Perhaps the compatible should be different, such as fsl,maple-b3-liodn to
indicate that that is the only portion of the device that is owned by this
partition.
+Example:
+ /* B4860 */
+
+ maple@80 {
+ #address-cells = 0;
+ #size-cells = 0;
+ status = disabled;
+ compatible = fsl,maple-b3;
+ reg = 0x800 0x1;
+ interrupts = 16 2 1 18;
+ fsl,iommu-parent = pamu1;
+ };
This error interrupt is documented as 13, not 18. b4860 (and maybe other b4?)
have an erratum that says that error interrupts are reversed, but this is
generally implemented in b4si-post.dtsi, not in block-specific include files.
Will no chip without the erratum ever have maple?
[Leekha Shaveta-B20052] You are right here. Will add the interrupts in b4si or
b4860si file, as other chips may have maple.
Regards,
Shaveta
-Scott
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RE: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Friday, April 05, 2013 7:53 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org list Subject: Re: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote: B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information * serdes, sfp(security fuse processor), thermal, gpio, maple, cpri, quad timers nodes Signed-off-by: Shaveta Leekha shav...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Varun Sethi varun.se...@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Andy Fleming aflem...@freescale.com Signed-off-by: Vakul Garg va...@freescale.com --- v2: - incorporated review comments on commits message - change unit address of cpu nodes to match the reg property arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++ arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 + arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++ arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++ arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 262 +++ arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++ 6 files changed, 667 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi Is there a reason you didn't get rid of b4si-pre.dtsi and just merge it into b4860si-pre.dtsi b4420-pre.dtsi? [SL] No particular reason. I have just tried to re-factored these files as you have suggested. Hence managed the commonalities in B4 files and differences in B4860's and B4420's respective files to reduce duplicity. Regards, Shaveta - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 10:10 PM
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Garg Vakul-B16394; Tang Yuantian-B29983; Fleming
Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree
files for B4860 and B4420
On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 12:49 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang
Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device
tree files for B4860 and B4420
On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
+/ {
+ compatible = fsl,B4860;
+
+ cpus {
+ cpu1: PowerPC,e6500@1 {
+ device_type = cpu;
+ reg = 2 3;
+ next-level-cache = L2;
+ };
+ cpu2: PowerPC,e6500@2 {
+ device_type = cpu;
+ reg = 4 5;
+ next-level-cache = L2;
+ };
+ cpu3: PowerPC,e6500@3 {
+ device_type = cpu;
+ reg = 6 7;
+ next-level-cache = L2;
+ };
The unit addresses need to match reg.
[SL] You mean @1 should match to reg = 2 3 ?
Yes, it should be @2 for that node.
As each e6500 core in B4860 is dual- threaded, reg property here
represents the thread's identifier in that PA core.
So convention used in T4 and B4 is: core 0 having threads 0 and 1,
Core 1 having 2 3 and
so on
The convention used in device trees is that the unit address matches the reg.
-Scott
[SL] Ok, I can change that. Will make unit address as @2 for 2 3, @4 for 4
5 and so on
Kumar, please respond here, as I have followed the convention used in T4 device
tree files for
Dual-threaded cores.
Regards,
Shaveta
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RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Wednesday, April 03, 2013 10:10 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg Vakul-B16394 Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote: B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 What are the differences between B4860 B4420, beyond # of cores? [SL] have detailed the differences in board support patch sent in this patch set. Do I need to mention the differences here also? There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information What about: serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, quad timers, [SL] I would prefer to add, what have been added in device tree so far in patch description As that is clear to me. But as u suggested, I mentioned some of the nodes/things missing, though the list is not Exhaustive. Also I am not sure of, what would be added/required in future in these device tree files. Anyways, I can add all the things you have mentioned above. Please tell if anything else is missing. Regards, Shaveta Signed-off-by: Shaveta Leekha shav...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Varun Sethi varun.se...@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Andy Fleming aflem...@freescale.com Signed-off-by: Vakul Garg va...@freescale.com --- arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++ arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 + arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++ arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++ arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 262 +++ arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++ Remove b4si-pre.dtsi, there isn't enough here to warrant not just merging it into b4420si-pre.dtsi b4860si-pre.dtsi 6 files changed, 667 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi new file mode 100644 index 000..bba0c03 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi @@ -0,0 +1,94 @@ +/* + * B4420 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of +the + * GNU General Public License (GPL) as published by the Free +Software + * Foundation, either version 2 of that License or (at your option) +any + * later version. + * + * This software is provided by Freescale Semiconductor as is and +any + * express or implied warranties, including, but not limited to, the +implied + * warranties of merchantability and fitness for a particular purpose +are + * disclaimed. In no event shall Freescale Semiconductor be liable +for any + * direct, indirect, incidental, special, exemplary, or consequential +damages + * (including, but not limited to, procurement of substitute goods or +services; + * loss of use, data, or profits; or business
RE: [PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Wednesday, April 03, 2013 10:12 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote: - Add support for B4 board in board file b4_qds.c, It is common for B4860, B4420 and B4220QDS as they share same QDS board - Add B4QDS support in Kconfig and Makefile B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor, with following major features: - Four dual-threaded e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz - Two DDR3/3L controllers for high-speed memory interface each runs at up to 1866.67 MHz - CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN - Large internal cache memory with snooping and stashing capabilities - Sixteen 10-GHz SerDes lanes that serve: - Two SRIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes - Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less antenna connection - Two 10-Gbit Ethernet controllers (10GEC) - Six 1G/2.5-Gbit Ethernet controllers for network communications - PCI Express controller - Debug (Aurora) - Various system peripherals B4420 and B4220 have some differences in comparison to B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420: B4420 has: - Fewer e6500 cores: 1 cluster with 2 e6500 cores - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC @ 1.6GHz - 2 X 4 lane serdes - 3 SGMII interfaces - no sRIO - no 10G Key differences between B4860 and B4220: B4220 has: - Fewer e6500 cores: 1 cluster with 1 e6500 core - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC @ 1.33GHz - 2 X 2 lane serdes - 2 SGMII interfaces - no sRIO - no 10G Signed-off-by: Shaveta Leekha shav...@freescale.com --- arch/powerpc/platforms/85xx/Kconfig | 17 ++ arch/powerpc/platforms/85xx/Makefile |1 + arch/powerpc/platforms/85xx/b4_qds.c | 102 ++ 3 files changed, 120 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c commit messages should line wrap at 75 chars. - k [SL] Ok, will do that. Regards, Shaveta ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, April 05, 2013 12:44 AM
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421; Zhao Chenhui-B35336; Mehresh Ramneek-B31383; Garg
Vakul-B16394; Lian Minghuan-B31939; Tang Yuantian-B29983; Fleming
Andy-AFLEMING; Sethi Varun-B16395; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree
files for B4860 and B4420
On Apr 4, 2013, at 2:03 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 10:10 PM
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao
Chenhui-B35336; Lian Minghuan-B31939; Garg Vakul-B16394; Tang
Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device
tree files for B4860 and B4420
On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 12:49 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang
Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon
device tree files for B4860 and B4420
On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
+/ {
+ compatible = fsl,B4860;
+
+ cpus {
+ cpu1: PowerPC,e6500@1 {
+ device_type = cpu;
+ reg = 2 3;
+ next-level-cache = L2;
+ };
+ cpu2: PowerPC,e6500@2 {
+ device_type = cpu;
+ reg = 4 5;
+ next-level-cache = L2;
+ };
+ cpu3: PowerPC,e6500@3 {
+ device_type = cpu;
+ reg = 6 7;
+ next-level-cache = L2;
+ };
The unit addresses need to match reg.
[SL] You mean @1 should match to reg = 2 3 ?
Yes, it should be @2 for that node.
As each e6500 core in B4860 is dual- threaded, reg property here
represents the thread's identifier in that PA core.
So convention used in T4 and B4 is: core 0 having threads 0 and 1,
Core 1 having 2 3 and
so on
The convention used in device trees is that the unit address matches the reg.
-Scott
[SL] Ok, I can change that. Will make unit address as @2 for 2 3, @4 for 4
5 and so on
Kumar, please respond here, as I have followed the convention used in
T4 device tree files for Dual-threaded cores.
Scott is correct, we probably need to fix the T4 dts.
- k
[SL] ok, will do it for B4
Regards,
Shaveta
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RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Friday, April 05, 2013 12:44 AM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg Vakul-B16394 Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 On Apr 4, 2013, at 2:10 AM, Leekha Shaveta-B20052 wrote: -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Wednesday, April 03, 2013 10:10 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg Vakul-B16394 Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote: B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 What are the differences between B4860 B4420, beyond # of cores? [SL] have detailed the differences in board support patch sent in this patch set. Do I need to mention the differences here also? There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information What about: serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, quad timers, [SL] I would prefer to add, what have been added in device tree so far in patch description As that is clear to me. But as u suggested, I mentioned some of the nodes/things missing, though the list is not Exhaustive. Also I am not sure of, what would be added/required in future in these device tree files. Anyways, I can add all the things you have mentioned above. Please tell if anything else is missing. I would add the trivial ones and just make sure the list is exhaustive for the ones missing in the commit message. [SL] Adding serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, quad timers as missing things in my commit message. If I still miss some, Please add while applying the patch. Thanks, Shaveta Regards, Shaveta Signed-off-by: Shaveta Leekha shav...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Varun Sethi varun.se...@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Andy Fleming aflem...@freescale.com Signed-off-by: Vakul Garg va...@freescale.com --- arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++ arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 + arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++ arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++ arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 262 +++ arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++ Remove b4si-pre.dtsi, there isn't enough here to warrant not just merging it into b4420si-pre.dtsi b4860si-pre.dtsi - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 12:49 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Minghuan-B31939;
Leekha Shaveta-B20052; Garg Vakul-B16394; Tang Yuantian-B29983; Fleming
Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree
files for B4860 and B4420
On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
+/ {
+ compatible = fsl,B4860;
+
+ cpus {
+ cpu1: PowerPC,e6500@1 {
+ device_type = cpu;
+ reg = 2 3;
+ next-level-cache = L2;
+ };
+ cpu2: PowerPC,e6500@2 {
+ device_type = cpu;
+ reg = 4 5;
+ next-level-cache = L2;
+ };
+ cpu3: PowerPC,e6500@3 {
+ device_type = cpu;
+ reg = 6 7;
+ next-level-cache = L2;
+ };
The unit addresses need to match reg.
[SL] You mean @1 should match to reg = 2 3 ?
As each e6500 core in B4860 is dual- threaded, reg property here represents the
thread's identifier in that PA core.
So convention used in T4 and B4 is: core 0 having threads 0 and 1,
Core 1 having 2 3 and so
on
Regards,
Shaveta
-Scott
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RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS
-Original Message-
From: Leekha Shaveta-B20052
Sent: Tuesday, March 19, 2013 11:43 AM
To: 'Kumar Gala'
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh
Ramneek-B31383; Sethi Varun-B16395
Subject: RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree
files for B4860QDS
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Monday, March 18, 2013 8:34 PM
To: Leekha Shaveta-B20052
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh
Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree
files for B4860QDS
On Mar 18, 2013, at 2:41 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Timur Tabi [mailto:ti...@tabi.org]
Sent: Friday, March 15, 2013 6:38 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh
Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device
tree files for B4860QDS
On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha shav...@freescale.com wrote:
+ iommu@2 {
+ compatible = fsl,pamu-v1.0, fsl,pamu;
+ reg = 0x2 0x4000;
+ interrupts =
+ 24 2 0 0
+ 16 2 1 1;
+ };
You need to add the PAMU topology.
[SL] Thanks for reviewing the patches.
These patches are on similar lines as T4 initial support In due course
of time, we plan to add pamu topology and pamu related support in various
devices both for T4 and B4.
Kumar can you please suggest?
I can help with the B4 topology as its reasonable well described, I've been
working on trying to get the info to finish T4.
[SL] I have seen your patches to add PAMU topology in B4. Should I include them
in my set of patches or you would send them above my initial set of patches?
BR,
Shaveta
[SL] Kumar, Waiting for your response on it. Thought I have sent new set of
patches with the refactoring suggested, but not added PAMU in them.
BR,
Shaveta
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Recall: [PATCH 0/5] powerpc/fsl-booke: Add B4(B4860QDS and B4420QDS) board support
Leekha Shaveta-B20052 would like to recall the message, [PATCH 0/5] powerpc/fsl-booke: Add B4(B4860QDS and B4420QDS) board support. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Monday, March 18, 2013 8:26 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support On Mar 18, 2013, at 1:28 AM, Leekha Shaveta-B20052 wrote: -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Friday, March 15, 2013 9:28 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote: - Add support for B4 board's personalities in board file b4_qds.c, It is common for B4 personalities B4860 and B4420QDS - Add B4QDS support in Kconfig and Makefile Code also references a B4220, what about it? [SL] I have added the basic support for it in board file as it's one of the personality of B4, missed it in description. But device trees for this has not been created and tested. So what do you suggest here: Should I add it here in B4 board support or should I remove its references altogether? What's the difference between B4220 and B4420 or B4860? - k [SL] B4220 is again a reduced personality of B4 with some differences like: Even lesser Number of cores than B4860 and B4420, lesser number of SerDes lanes and some difference in other peripherals. BR, Shaveta B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor, with following major features: - Four dual-threaded e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz - Two DDR3/3L controllers for high-speed memory interface each runs at up to 1866.67 MHz - CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN - Large internal cache memory with snooping and stashing capabilities - Sixteen 10-GHz SerDes lanes that serve: - Two SRIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes - Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less antenna connection - Two 10-Gbit Ethernet controllers (10GEC) - Six 1G/2.5-Gbit Ethernet controllers for network communications - PCI Express controller - Debug (Aurora) - Various system peripherals B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420: B4420 has: - Fewer e6500 cores: 1 cluster with 2 e6500 cores - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC - 2X 4 lane serdes - 3 SGMII interfaces - no sRIO - no 10G Signed-off-by: Shaveta Leekha shav...@freescale.com --- arch/powerpc/platforms/85xx/Kconfig | 16 + arch/powerpc/platforms/85xx/Makefile |1 + arch/powerpc/platforms/85xx/b4_qds.c | 102 ++ 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Monday, March 18, 2013 8:33 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEMING;
Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device
tree
On Mar 18, 2013, at 1:31 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, March 16, 2013 1:57 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming
Andy-AFLEMING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board
device tree
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/b4860qds.dts | 178
1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644
arch/powerpc/boot/dts/b4860qds.dts
diff --git a/arch/powerpc/boot/dts/b4860qds.dts
b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 000..ae6ac05
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,178 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or
+without
+ * modification, are permitted provided that the following conditions are
met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote
products
+ * derived from this software without specific prior written
permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms
+of the
+ * GNU General Public License (GPL) as published by the Free
+Software
+ * Foundation, either version 2 of that License or (at your option)
+any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS''
+AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
+FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/b4860si-pre.dtsi
+
+/ {
+model = fsl,B4860QDS;
+compatible = fsl,B4860QDS;
+#address-cells = 2;
+#size-cells = 2;
+interrupt-parent = mpic;
+
+ifc: localbus@ffe124000 {
+reg = 0xf 0xfe124000 0 0x2000;
+ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+nor@0,0 {
+#address-cells = 1;
+#size-cells = 1;
+compatible = cfi-flash;
+reg = 0x0 0x0 0x800;
+bank-width = 2;
+device-width = 1;
+};
+
+nand@2,0 {
+#address-cells = 1;
+#size-cells = 1;
+compatible = fsl,ifc-nand;
+reg = 0x2 0x0 0x1;
+
+partition@0 {
+/* This location must not be altered */
+/* 1MB for u-boot Bootloader Image */
+reg = 0x0 0x0010;
+label = NAND U-Boot Image;
+read-only;
+};
+
+partition@10 {
+/* 1MB for DTB Image */
+reg = 0x0010 0x0010
RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Monday, March 18, 2013 8:34 PM
To: Leekha Shaveta-B20052
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh
Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree
files for B4860QDS
On Mar 18, 2013, at 2:41 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Timur Tabi [mailto:ti...@tabi.org]
Sent: Friday, March 15, 2013 6:38 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh
Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device
tree files for B4860QDS
On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha shav...@freescale.com wrote:
+ iommu@2 {
+ compatible = fsl,pamu-v1.0, fsl,pamu;
+ reg = 0x2 0x4000;
+ interrupts =
+ 24 2 0 0
+ 16 2 1 1;
+ };
You need to add the PAMU topology.
[SL] Thanks for reviewing the patches.
These patches are on similar lines as T4 initial support In due course
of time, we plan to add pamu topology and pamu related support in various
devices both for T4 and B4.
Kumar can you please suggest?
I can help with the B4 topology as its reasonable well described, I've been
working on trying to get the info to finish T4.
[SL] I have seen your patches to add PAMU topology in B4. Should I include them
in my set of patches or you would send them above my initial set of patches?
BR,
Shaveta
- k
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RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree
-Original Message-
From: Leekha Shaveta-B20052
Sent: Tuesday, March 19, 2013 11:41 AM
To: 'Kumar Gala'
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEMING;
Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device
tree
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Monday, March 18, 2013 8:33 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEMING;
Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device
tree
On Mar 18, 2013, at 1:31 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, March 16, 2013 1:57 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming
Andy-AFLEMING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board
device tree
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/b4860qds.dts | 178
1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644
arch/powerpc/boot/dts/b4860qds.dts
diff --git a/arch/powerpc/boot/dts/b4860qds.dts
b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 000..ae6ac05
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,178 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or
+without
+ * modification, are permitted provided that the following conditions are
met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote
products
+ * derived from this software without specific prior written
permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms
+of the
+ * GNU General Public License (GPL) as published by the Free
+Software
+ * Foundation, either version 2 of that License or (at your option)
+any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS''
+AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
+FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/b4860si-pre.dtsi
+
+/ {
+model = fsl,B4860QDS;
+compatible = fsl,B4860QDS;
+#address-cells = 2;
+#size-cells = 2;
+interrupt-parent = mpic;
+
+ifc: localbus@ffe124000 {
+reg = 0xf 0xfe124000 0 0x2000;
+ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+nor@0,0 {
+#address-cells = 1;
+#size-cells = 1;
+compatible = cfi-flash;
+reg = 0x0 0x0 0x800;
+bank-width = 2;
+device-width = 1;
+};
+
+nand@2,0 {
+#address-cells = 1;
+#size-cells = 1;
+compatible = fsl,ifc-nand;
+reg = 0x2 0x0 0x1;
+
+partition@0 {
+/* This location must not be altered */
+/* 1MB for u-boot Bootloader Image */
+reg
RE: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Friday, March 15, 2013 9:28 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote: - Add support for B4 board's personalities in board file b4_qds.c, It is common for B4 personalities B4860 and B4420QDS - Add B4QDS support in Kconfig and Makefile Code also references a B4220, what about it? [SL] I have added the basic support for it in board file as it's one of the personality of B4, missed it in description. But device trees for this has not been created and tested. So what do you suggest here: Should I add it here in B4 board support or should I remove its references altogether? B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor, with following major features: - Four dual-threaded e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz - Two DDR3/3L controllers for high-speed memory interface each runs at up to 1866.67 MHz - CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN - Large internal cache memory with snooping and stashing capabilities - Sixteen 10-GHz SerDes lanes that serve: - Two SRIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes - Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less antenna connection - Two 10-Gbit Ethernet controllers (10GEC) - Six 1G/2.5-Gbit Ethernet controllers for network communications - PCI Express controller - Debug (Aurora) - Various system peripherals B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420: B4420 has: - Fewer e6500 cores: 1 cluster with 2 e6500 cores - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC - 2X 4 lane serdes - 3 SGMII interfaces - no sRIO - no 10G Signed-off-by: Shaveta Leekha shav...@freescale.com --- arch/powerpc/platforms/85xx/Kconfig | 16 + arch/powerpc/platforms/85xx/Makefile |1 + arch/powerpc/platforms/85xx/b4_qds.c | 102 ++ 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 31dc066..7bbd522 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -262,6 +262,22 @@ config SGY_CTS1000 endif # PPC32 +config B4_QDS + bool Freescale B4 QDS + select DEFAULT_UIMAGE + select E500 + select PPC_E500MC + select PHYS_64BIT + select SWIOTLB + select MPC8xxx_GPIO should be: select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB [SL] will change it. + select HAS_RAPIDIO + select PPC_EPAPR_HV_PIC + help + This option enables support for the B4 QDS board + The B4 application development system B4 QDS is a complete + debugging environment intended for engineers developing + applications for the B4. + Should be in the if PPC64 section with T4240 QDS support [SL] ok config P5020_DS bool Freescale P5020 DS select DEFAULT_UIMAGE diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 712e233..a12ae2d 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o obj-y += common.o obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o +obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c new file mode 100644 index 000..0c6702f --- /dev/null +++ b/arch/powerpc/platforms/85xx/b4_qds.c @@ -0,0 +1,102 @@ +/* + * B4 QDS Setup + * Should apply for QDS platform of B4860 and it's personalities. + * viz B4860/B4420/B4220QDS + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or +modify it + * under the terms of the GNU General Public License as published +by the + * Free Software Foundation; either version 2 of the License, or +(at your
RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, March 16, 2013 1:57 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEMING;
Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device
tree
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/b4860qds.dts | 178
1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644
arch/powerpc/boot/dts/b4860qds.dts
diff --git a/arch/powerpc/boot/dts/b4860qds.dts
b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 000..ae6ac05
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,178 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of
+the
+ * GNU General Public License (GPL) as published by the Free
+Software
+ * Foundation, either version 2 of that License or (at your option)
+any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND
+ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
+FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/b4860si-pre.dtsi
+
+/ {
+ model = fsl,B4860QDS;
+ compatible = fsl,B4860QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = 0x0 0x0010;
+ label = NAND U-Boot Image;
+ read-only;
+ };
+
+ partition@10 {
+ /* 1MB for DTB Image */
+ reg = 0x0010 0x0010;
+ label = NAND DTB Image;
+ };
+
+ partition@20 {
+ /* 10MB for Linux Kernel Image */
+ reg = 0x0020 0x00A0;
+ label = NAND Linux Kernel Image;
+ };
+
+ partition@c0 {
+ /* 500MB
RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, March 16, 2013 2:00 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tang
Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh
Ramneek-B31383; Fleming Andy-AFLEMING
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree
files for B4860QDS
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 184 +++
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 80
2 files changed, 264 insertions(+), 0 deletions(-) create mode 100644
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
* SEC node is missing
* DCSR nodes are missing.
- k
[SL] will add sec node, same reply for dcsr.
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 000..2db68b2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,184 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of
+the
+ * GNU General Public License (GPL) as published by the Free
+Software
+ * Foundation, either version 2 of that License or (at your option)
+any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND
+ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
+FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+/* controller at 0x20 */
+pci0 {
+ compatible = fsl,b4860-pcie, fsl,qoriq-pcie-v2.4;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ pcie@0 {
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
+ ;
+ };
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
+
+soc {
+ #address-cells = 1;
+ #size-cells = 1;
+ device_type
RE: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board device tree
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Saturday, March 16, 2013 2:02 AM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board device tree On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote: Signed-off-by: Shaveta Leekha shav...@freescale.com --- arch/powerpc/boot/dts/b4420qds.dts | 168 1 files changed, 168 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/b4420qds.dts If B4420 and B4860 qds are same board, refactor this into a b4qds.dtsi file for common board features like NOR, NAND, SPI, SDHC, etc. [SL] will work on refactoring and send new set of patches soon. Thanks for the feedback. Regards, Shaveta - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS
-Original Message-
From: Timur Tabi [mailto:ti...@tabi.org]
Sent: Friday, March 15, 2013 6:38 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Minghuan-B31939;
Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree
files for B4860QDS
On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha shav...@freescale.com wrote:
+ iommu@2 {
+ compatible = fsl,pamu-v1.0, fsl,pamu;
+ reg = 0x2 0x4000;
+ interrupts =
+ 24 2 0 0
+ 16 2 1 1;
+ };
You need to add the PAMU topology.
[SL] Thanks for reviewing the patches.
These patches are on similar lines as T4 initial support
In due course of time, we plan to add pamu topology and pamu related support in
various devices both for T4 and B4.
Kumar can you please suggest?
Regards,
Shaveta
--
Timur Tabi
Linux kernel developer at Freescale
___
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