RE: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, July 31, 2013 11:47 PM
> To: Liu Po-B43644
> Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org; ga...@kernel.crashing.org;
> Fleming Andy-AFLEMING; Hu Mingkai-B21284
> Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for
> C293
>
> On 07/30/2013 09:13:28 PM, Liu Po-B43644 wrote:
> >
> > > -Original Message-
> > > From: Wood Scott-B07421
> > > Sent: Wednesday, July 31, 2013 2:28 AM
> > > To: Liu Po-B43644
> > > Cc: linuxppc-...@ozlabs.org; ga...@kernel.crashing.org; Fleming
> > Andy-
> > > AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> > > Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree
> > for
> > > C293
> > >
> > > On 07/30/2013 03:49:22 AM, Po Liu wrote:
> > > > + crypto@8 {
> > > > +/include/ "qoriq-sec6.0-0.dtsi"
> > > > + };
> > > > +
> > > > + crypto@8 {
> > > > + reg = <0x8 0x2>;
> > > > + ranges = <0x0 0x8 0x2>;
> > > > +
> > > > + jr@1000{
> > > > + interrupts = <45 2 0 0>;
> > > > + };
> > > > + jr@2000{
> > > > + interrupts = <57 2 0 0>;
> > > > + };
> > > > + };
> > >
> > > Do these inline the way the example shows.
> > Sorry, Scott, I just remember in this way, the node can't be
> > recognized by system when run Uboot. The include can't be in the
> > crypto@8. See the discussion in
> > http://git.am.freescale.net:8181/#/c/736/ .
> > Maybe I should re-modify the example file.
>
> git.am.freescale.net is not accessible outside of Freescale; don't
> reference it on external lists. In any case, I don't know what
> specifically you want me to look at there. Just put the explanation here.
Sorry, I've realize that.
The fact is that: when put the include into the crypto@, it can't compile
success(make c293pcie.dtb as example). Error will show as:
ERROR (duplicate_node_names): Duplicate node name
/soc@fffe0/crypto@8/jr@1000
> I do not expect the dtc output to be any different between the two
> methods. Could you check this (by using dtc to decompile the dtb
> afterward) and point out exactly how the output differs between the two
> approaches?
Since it will compile error in this way, so will not output .dtb file
>
> -Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for C293
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, July 31, 2013 2:28 AM
> To: Liu Po-B43644
> Cc: linuxppc-...@ozlabs.org; ga...@kernel.crashing.org; Fleming Andy-
> AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> Subject: Re: [PATCH v3 2/3] powerpc/85xx: Add silicon device tree for
> C293
>
> On 07/30/2013 03:49:22 AM, Po Liu wrote:
> > From: Mingkai Hu
> >
> > Signed-off-by: Mingkai Hu
> > Signed-off-by: Po Liu
> > ---
> > Changes for v2:
> >- None
> > Changes for v3:
> >- None
> >
> > arch/powerpc/boot/dts/fsl/c293si-post.dtsi | 193
> > +
> > arch/powerpc/boot/dts/fsl/c293si-pre.dtsi | 63 ++
> > 2 files changed, 256 insertions(+)
> > create mode 100644 arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> > create mode 100644 arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
> >
> > diff --git a/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> > new file mode 100644
> > index 000..bd20832
> > --- /dev/null
> > +++ b/arch/powerpc/boot/dts/fsl/c293si-post.dtsi
> > @@ -0,0 +1,193 @@
> > +/*
> > + * C293 Silicon/SoC Device Tree Source (post include)
> > + *
> > + * Copyright 2012 Freescale Semiconductor Inc.
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following
> > conditions are met:
> > + * * Redistributions of source code must retain the above
> > copyright
> > + * notice, this list of conditions and the following
> > disclaimer.
> > + * * Redistributions in binary form must reproduce the above
> > copyright
> > + * notice, this list of conditions and the following
> > disclaimer in the
> > + * documentation and/or other materials provided with the
> > distribution.
> > + * * Neither the name of Freescale Semiconductor nor the
> > + * names of its contributors may be used to endorse or promote
> > products
> > + * derived from this software without specific prior written
> > permission.
> > + *
> > + *
> > + * ALTERNATIVELY, this software may be distributed under the terms
> > of the
> > + * GNU General Public License ("GPL") as published by the Free
> > Software
> > + * Foundation, either version 2 of that License or (at your option)
> > any
> > + * later version.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS''
> > AND ANY
> > + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> > IMPLIED
> > + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
> > PURPOSE ARE
> > + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
> > FOR ANY
> > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> > CONSEQUENTIAL DAMAGES
> > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> > OR SERVICES;
> > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
> > CAUSED AND
> > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> > LIABILITY, OR TORT
> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
> > USE OF THIS
> > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > + */
> > +
> > +&ifc {
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > + compatible = "fsl,ifc", "simple-bus";
> > + interrupts = <19 2 0 0>;
> > +};
> > +
> > +/* controller at 0xa000 */
> > +&pci0 {
> > + compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
> > + device_type = "pci";
> > + #size-cells = <2>;
> > + #address-cells = <3>;
> > + bus-range = <0 255>;
> > + clock-frequency = <>;
> > + interrupts = <16 2 0 0>;
>
> Remove clock-frequency (surely PCIe is not running at 33 MHz).
>
> > + crypto@8 {
> > +/include/ "qoriq-sec6.0-0.dtsi"
> > + };
> > +
> > + crypto@8 {
> > + reg = <0x8 0x2>;
> > + ranges = <0x0 0x8 0x2>;
> > +
> > + jr@1000{
> > + interrupts = <45 2 0 0>;
> > + };
> > + jr@2000{
> > + interrupts = <57 2 0 0>;
> > + };
> > + };
>
> Do these inline the way the example shows.
Sorry, Scott, I just remember in this way, the node can't be recognized by
system when run Uboot. The include can't be in the crypto@8. See the
discussion in http://git.am.freescale.net:8181/#/c/736/ .
Maybe I should re-modify the example file.
>
> -Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, July 27, 2013 5:59 AM
> To: Liu Po-B43644
> Cc: linuxppc-...@ozlabs.org; ga...@kernel.crashing.org; Fleming Andy-
> AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> Subject: Re: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support
>
> On 07/25/2013 09:41:19 PM, Po Liu wrote:
> > + partition@190 {
> > + /* 7MB for User Area */
> > + reg = <0x0190 0x0070>;
> > + label = "NAND User area";
> > + };
> > +
> > + partition@200 {
> > + /* 96MB for Root File System */
> > + reg = <0x0200 0x0600>;
> > + label = "NAND Root File System";
> > + };
> > +
> > + partition@800 {
> > + /* 3968MB for Others */
> > + reg = <0x0800 0xF800>;
> > + label = "NAND Others";
> > + };
>
> Again, what is the difference between "user area" and "others"? I'm not
> even sure why it needs to be separate from "root file system", but at
> least the root filesystem should be larger given the size of the overall
> flash.
Do you mean just merge up four partition into one "RFS"? Or merge up four
partition into "RFS" and "User area" is better?
>
> Also please use lowercase for hex.
>
> > + };
> > +
> > + cpld@2,0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "fsl,c293pcie-cpld";
> > + reg = <0x2 0x0 0x20>;
> > + };
>
> Remove #address-cells/#size-cells
>
> > + partition@58 {
> > + /* 10.5MB for Compressed RFS Image */
> > + reg = <0x0058 0x00a8>;
> > + label = "SPI Flash Compressed RFSImage";
> > + };
>
> Space before "Image". Why specifiy that it's compressed, versus some
> other filesystem type?
>
Remove all the "compressed" comments when express the RFS partition?
> -Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, July 27, 2013 5:55 AM
> To: Liu Po-B43644
> Cc: linuxppc-...@ozlabs.org; ga...@kernel.crashing.org; Fleming Andy-
> AFLEMING; Hu Mingkai-B21284; Liu Po-B43644
> Subject: Re: [PATCH v2 1/3] powerpc/85xx: Add SEC6.0 device tree
>
> On 07/25/2013 09:41:17 PM, Po Liu wrote:
> > +=
> > +Job Ring (JR) Node
> > +
> > +Child of the crypto node defines data processing interface to
> > SEC 6
> > +across the peripheral bus for purposes of processing
> > +cryptographic descriptors. The specified address
> > +range can be made visible to one (or more) cores.
> > +The interrupt defined for this node is controlled within
> > +the address range of this node.
> > +
> > + - compatible
> > + Usage: required
> > + Value type:
> > + Definition: Must include "fsl,sec-v6.0-job-ring", if it is
> > + back compatible with old version, better add them all.
>
> Please don't use colloquialisms such as "[you'd] better do this" in a
> formal specification.
>
> Just say 'Must include "fsl,sec-v6.0-job-ring"' and leave it at that,
> like the other bindings do.
Ok, I'll remove redundant words.
>
> > +===
> > +Full Example
> > +
> > +Since some chips may embeded with more than one SEC 6, we abstract
> > +all the same properties into one file qoriq-sec6.0-0.dtsi. Each chip
> > +want to binding the node could simply include it in its own device
> > +node tree. Below is full example in C293PCIE:
>
> Replace this with:
>
> Since some chips may contain more than one SEC, the dtsi contains only
> the node contents, not the node itself. A chip using the SEC should
> include the dtsi inside each SEC node. Example:
>
> > +In qoriq-sec6.0-0.dtsi:
> > +
> > + compatible = "fsl,sec-v6.0";
> > + fsl,sec-era = <6>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + jr@1000 {
> > + compatible = "fsl,sec-v6.0-job-ring",
> > + "fsl,sec-v5.2-job-ring",
> > + "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.4-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg= <0x1000 0x1000>;
> > + };
> > +
> > + jr@2000 {
> > + compatible = "fsl,sec-v6.0-job-ring",
> > + "fsl,sec-v5.2-job-ring",
> > + "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.4-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg= <0x2000 0x1000>;
> > + };
> > +
> > +In the C293 device tree, we add the include of public property:
> > +
> > +crypto@a {
> > +/include/ "qoriq-sec6.0-0.dtsi"
> > + };
>
> Whitespace
>
> > +
> > + crypto@a {
> > + reg = <0xa 0x2>;
> > + ranges = <0x0 0xa 0x2>;
> > +
> > + jr@1000{
> > + interrupts = <49 2 0 0>;
> > + };
> > + jr@2000{
> > + interrupts = <50 2 0 0>;
> > + };
> > + };
>
> You could combine the above like this:
>
> crypto@a {
> reg = <0xa 0x2>;
> ranges = <0 0xa 0x2>;
>
> /include/ "qoriq-sec6.0-0.dtsi"
>
> jr@1000 {
> interrupts = <49 2 0 0>;
> };
>
> jr@2000 {
> interrupts = <50 2 0 0>;
> };
> };
>
> Why is it "qoriq-sec6.0-0.dtsi" and not "qoriq-sec6.0-dtsi"?
Ok, I'll change to qoriq-sec6.0.dtsi
>
> -Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [1/4] powerpc/85xx: Add SEC6.0 device tree
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, July 23, 2013 6:41 AM
> To: Liu Po-B43644
> Cc: linuxppc-...@ozlabs.org; Hu Mingkai-B21284
> Subject: Re: [1/4] powerpc/85xx: Add SEC6.0 device tree
>
> On Thu, Apr 25, 2013 at 09:54:14AM +0800, Po Liu wrote:
> > From: Mingkai Hu
> >
> > Add device tree for SEC 6.0 used on C29x silicon.
> >
> > Signed-off-by: Mingkai Hu
> > Singed-off-by: Po Liu
>
> I've heard of patches being flamed, but here we want signing, not
> singeing. :-)
>
> Don't forget that you can use the -s option to have git add the signoff
> for you.
>
> > ---
> > Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git
>
> This URL is not accessible outside Freescale, so don't reference it when
> posting patches publicly.
>
> If your patch is against the latest upstream code, you don't need to say
> anything special about that. You only need to make a note when it's
> against some other yet-to-be-merged tree or patch.
>
> > + compatible = "fsl,sec-v6.0", "fsl,sec-v5.2",
> > + "fsl,sec-v5.0", "fsl,sec-v4.4",
> > + "fsl,sec-v4.0";
> > + fsl,sec-era = <6>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + jr@1000 {
> > + compatible = "fsl,sec-v6.0-job-ring",
> > + "fsl,sec-v5.2-job-ring",
> > + "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.4-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg= <0x1000 0x1000>;
> > + };
> > +
> > + jr@2000 {
> > + compatible = "fsl,sec-v6.0-job-ring",
> > + "fsl,sec-v5.2-job-ring",
> > + "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.4-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg= <0x2000 0x1000>;
> > + };
>
> You claim compatibility with a bunch of prior SECs, but sec-v5.2 has four
> job rings and an rtic node. Likewise for the previous compatibles listed.
> This has two job rings and no rtic.
So, shall I remove "fsl,sec-v5.2","fsl,sec-v5.0", "fsl,sec-v4.4",
"fsl,sec-v4.0" since all other SEC with 4 job rings? and only leave
"fsl,sec-v6.0"?
>
> Can you point to where in the SEC v4.0 binding (I don't see a binding for
> the subsequent versions), it says that these are optional?
I found SEC V4.0 in file qoriq-sec4.0-0.dtsi. If "fsl,sec-v4.0" not in the
compatible list, it is no use in this compatible list. But seems keep the
"fsl,sec-v4.0-job-ring" job ring compatible is ok. Is that what you were ask?
>
> -Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [3/4] powerpc/85xx: Add C293PCIE board support
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, July 23, 2013 6:59 AM
> To: Liu Po-B43644
> Cc: linuxppc-...@ozlabs.org; Hu Mingkai-B21284
> Subject: Re: [3/4] powerpc/85xx: Add C293PCIE board support
>
> On Thu, Apr 25, 2013 at 09:54:16AM +0800, Po Liu wrote:
> > From: Mingkai Hu
> >
> > C293PCIE board is a series of Freescale PCIe add-in cards to perform
> > as public key crypto accelerator or secure key management module.
> >
> > - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
> > - 512MB soldered DDR3 32bit memory
> > - CPLD System Logic
> > - 64MB x16 NOR flash and 4GB x8 NAND flash
> > - 16MB SPI flash
> >
> > Signed-off-by: Mingkai Hu
> > Singed-off-by: Po Liu
>
> Signed
>
> > + partition@90 {
> > + /* 33MB for rootfs */
> > + reg = <0x0090 0x0210>;
> > + label = "NOR Rootfs Image";
> > + };
> > +
> > + partition@2a0 {
> > + /* 20MB for JFFS2 based Root file System */
> > + reg = <0x02a0 0x0140>;
> > + label = "NOR JFFS2 Root File System";
> > + };
>
> Don't specify JFFS2. Combine these two partitions into one.
Ok, I'll merge up two partition.
>
> > + partition@60 {
> > + /* 4MB for Compressed Root file System Image */
> > + reg = <0x0060 0x0040>;
> > + label = "NAND Compressed RFS Image";
> > + };
> > +
> > + partition@a0 {
> > + /* 15MB for JFFS2 based Root file System */
> > + reg = <0x00a0 0x00f0>;
> > + label = "NAND JFFS2 Root File System";
> > + };
>
> Likewise.
>
> > + partition@190 {
> > + /* 7MB for User Area */
> > + reg = <0x0190 0x0070>;
> > + label = "NAND User area";
> > + };
>
> Above you say there's 4 GiB of NAND, but here you define partitions that
> only cover 32 MiB.
Can I set one partion include all other space(4GB- 32MB) with label name
"Others"?
>
> > + };
> > +
> > + cpld@2,0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "fsl,c293pcie-cpld";
> > + reg = <0x2 0x0 0x020>;
> > + bank-width = <1>;
> > + device-width = <1>;
> > + };
>
> What do bank-width and device-width mean here?
I will remove these two lines? I thought I copy from other platform.
>
> Why all the leading zeroes in 0x020?
I'll change to 0x20 from 0x020.
>
> > + partition@58 {
> > + /* 4MB for Compressed RFS Image */
> > + reg = <0x0058 0x0040>;
> > + label = "SPI Flash Compressed RFSImage";
> > + };
> > +
> > + partition@98 {
> > + /* 6.5MB for JFFS2 based RFS */
> > + reg = <0x0098 0x0068>;
> > + label = "SPI Flash JFFS2 RFS";
> > + };
>
> Again, merge these two and don't specify JFFS2.
Ok, thanks
>
> > diff --git a/arch/powerpc/platforms/85xx/Kconfig
> > b/arch/powerpc/platforms/85xx/Kconfig
> > index a0dcd57..df26b21 100644
> > --- a/arch/powerpc/platforms/85xx/Kconfig
> > +++ b/arch/powerpc/platforms/85xx/Kconfig
> > @@ -32,6 +32,13 @@ config BSC9131_RDB
> > StarCore SC3850 DSP
> > Manufacturer : Freescale Semiconductor, Inc
> >
> > +config C293_PCIE
> > +bool "Freescale C293PCIE"
> > +select DEFAULT_UIMAGE
> > +select SWIOTLB
> > +help
> > +This option enables support for the C293PCIE board
>
> Why do you need SWIOTLB if the board has 512 MiB soldered RAM?
I'll remove it.
>
> > diff --git a/arch/powerpc/platforms/85xx/c293pcie.c
> > b/arch/powerpc/platforms/85xx/c293pcie.c
> > new file mode 100644
> > index 000..75dda12
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/85xx/c293pcie.c
> > @@
RE: [4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, July 23, 2013 7:00 AM To: Liu Po-B43644 Cc: linuxppc-...@ozlabs.org; Hu Mingkai-B21284 Subject: Re: [4/4] powerpc/85xx: Update mpc85xx_defconfig for C293PCIE On Thu, Apr 25, 2013 at 09:54:17AM +0800, Po Liu wrote: > From: Mingkai Hu > > Signed-off-by: Mingkai Hu > > --- > Base on git://git.am.freescale.net/gitolite/mirrors/linux-2.6.git > arch/powerpc/configs/mpc85xx_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/powerpc/configs/mpc85xx_defconfig > b/arch/powerpc/configs/mpc85xx_defconfig > index cf815e8..ddc33a2 100644 > --- a/arch/powerpc/configs/mpc85xx_defconfig > +++ b/arch/powerpc/configs/mpc85xx_defconfig > @@ -28,6 +28,7 @@ CONFIG_MPC85xx_MDS=y CONFIG_MPC8536_DS=y > CONFIG_MPC85xx_DS=y CONFIG_MPC85xx_RDB=y > +CONFIG_C293_PCIE=y > CONFIG_P1010_RDB=y > CONFIG_P1022_DS=y > CONFIG_P1022_RDK=y Also, why only mpc85xx_defconfig and mpc85xx_smp_defconfig? Just because this board isn't SMP doesn't mean it can't be supported by an SMP kernel. Action: I will add configure to mpc85xx_smp_defconfig. And merge it to Add-C293PCIE-board-support.patch. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/85xx: dts - add ranges property for SEC
Thanks again for the fix. Just ignore this post. Best regards, Liu Po - 8038 -Original Message- From: Gala Kumar-B11780 Sent: Wednesday, February 20, 2013 12:01 AM To: Liu Po-B43644 Cc: Subject: Re: [PATCH] powerpc/85xx: dts - add ranges property for SEC On Feb 18, 2013, at 6:29 PM, Po Liu wrote: > This facilitates getting the physical address of the SEC node. > > Signed-off-by: Liu po > --- > arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) Why are you reposting this, I already applied it: http://git.kernel.org/?p=linux/kernel/git/galak/powerpc.git;a=commit;h=db29cd3c4497e7edf9176284ba7cf3cec1814c7a - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/85xx: dts - add ranges property for SEC
Hi Kim, Thank you for the fixing. Best regards, Liu Po - 8038 -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Wednesday, February 13, 2013 1:27 AM To: Phillips Kim-R1AAHA Cc: Liu Po-B43644; linuxppc-...@ozlabs.org Subject: Re: [PATCH] powerpc/85xx: dts - add ranges property for SEC On Jan 18, 2013, at 2:40 PM, Kim Phillips wrote: > On Fri, 18 Jan 2013 17:16:13 +0800 > Po Liu wrote: > >> This facilitates getting the physical address of the SEC node. >> >> Signed-off-by: Liu po >> --- > Reviewed-by: Kim Phillips > > Kim This was missing a trailing ';', so wondering if it was ever tested? I fixed when I applied. applied. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
